From 82a0d920d0d52dc923516262afc414ac7b6ad3b4 Mon Sep 17 00:00:00 2001 From: Alfredo Cardigliano Date: Fri, 23 Aug 2024 19:22:12 +0200 Subject: [PATCH] Add irdma - required by ice on some kernel --- drivers/intel/irdma-1.14.33/COPYING | 339 + drivers/intel/irdma-1.14.33/README_irdma.txt | 1515 + drivers/intel/irdma-1.14.33/build.sh | 275 + drivers/intel/irdma-1.14.33/build_core.sh | 299 + drivers/intel/irdma-1.14.33/install_core.sh | 175 + .../intel/irdma-1.14.33/libirdma-51.0.patch | 5126 ++ drivers/intel/irdma-1.14.33/readmefirst.txt | 14 + drivers/intel/irdma-1.14.33/src/irdma/Kbuild | 39 + drivers/intel/irdma-1.14.33/src/irdma/cm.c | 4500 ++ drivers/intel/irdma-1.14.33/src/irdma/cm.h | 410 + .../intel/irdma-1.14.33/src/irdma/configfs.c | 1559 + drivers/intel/irdma-1.14.33/src/irdma/ctrl.c | 6903 ++ .../intel/irdma-1.14.33/src/irdma/debugfs.c | 1353 + drivers/intel/irdma-1.14.33/src/irdma/defs.h | 1841 + .../irdma-1.14.33/src/irdma/distro_ver.h | 194 + drivers/intel/irdma-1.14.33/src/irdma/hmc.c | 822 + drivers/intel/irdma-1.14.33/src/irdma/hmc.h | 186 + drivers/intel/irdma-1.14.33/src/irdma/hw.c | 2832 + .../irdma-1.14.33/src/irdma/i40e_client.h | 222 + .../intel/irdma-1.14.33/src/irdma/i40iw_hw.c | 259 + .../intel/irdma-1.14.33/src/irdma/i40iw_hw.h | 163 + .../intel/irdma-1.14.33/src/irdma/i40iw_if.c | 271 + .../intel/irdma-1.14.33/src/irdma/icrdma_hw.c | 392 + .../intel/irdma-1.14.33/src/irdma/icrdma_hw.h | 106 + .../irdma-1.14.33/src/irdma/ig3rdma_hw.c | 151 + .../irdma-1.14.33/src/irdma/ig3rdma_hw.h | 22 + .../irdma-1.14.33/src/irdma/ig3rdma_regs.h | 64285 ++++++++++++++++ .../src/irdma/ig3rdma_regs_apf.h | 130 + .../src/irdma/ig3rdma_regs_avf.h | 130 + drivers/intel/irdma-1.14.33/src/irdma/iidc.h | 300 + .../intel/irdma-1.14.33/src/irdma/irdma-abi.h | 144 + drivers/intel/irdma-1.14.33/src/irdma/irdma.h | 211 + .../irdma-1.14.33/src/irdma/irdma_kcompat.c | 4010 + .../irdma-1.14.33/src/irdma/irdma_kcompat.h | 847 + .../src/irdma/kcompat-generator.sh | 336 + .../irdma-1.14.33/src/irdma/kcompat-lib.sh | 279 + .../irdma-1.14.33/src/irdma/linux_kcompat.h | 413 + drivers/intel/irdma-1.14.33/src/irdma/main.c | 1016 + drivers/intel/irdma-1.14.33/src/irdma/main.h | 717 + .../irdma-1.14.33/src/irdma/ofed_kcompat.h | 366 + .../irdma-1.14.33/src/irdma/oracle_kcompat.h | 114 + drivers/intel/irdma-1.14.33/src/irdma/osdep.h | 157 + drivers/intel/irdma-1.14.33/src/irdma/pble.c | 542 + drivers/intel/irdma-1.14.33/src/irdma/pble.h | 141 + .../intel/irdma-1.14.33/src/irdma/protos.h | 118 + drivers/intel/irdma-1.14.33/src/irdma/puda.c | 1728 + drivers/intel/irdma-1.14.33/src/irdma/puda.h | 185 + .../irdma-1.14.33/src/irdma/rhel_kcompat.h | 1345 + .../irdma-1.14.33/src/irdma/suse_kcompat.h | 766 + drivers/intel/irdma-1.14.33/src/irdma/trace.c | 112 + drivers/intel/irdma-1.14.33/src/irdma/trace.h | 3 + .../intel/irdma-1.14.33/src/irdma/trace_cm.h | 460 + drivers/intel/irdma-1.14.33/src/irdma/type.h | 1807 + .../irdma-1.14.33/src/irdma/ubuntu_kcompat.h | 505 + drivers/intel/irdma-1.14.33/src/irdma/uda.c | 266 + drivers/intel/irdma-1.14.33/src/irdma/uda.h | 88 + drivers/intel/irdma-1.14.33/src/irdma/uda_d.h | 221 + drivers/intel/irdma-1.14.33/src/irdma/uk.c | 2244 + drivers/intel/irdma-1.14.33/src/irdma/user.h | 743 + drivers/intel/irdma-1.14.33/src/irdma/utils.c | 3321 + drivers/intel/irdma-1.14.33/src/irdma/verbs.c | 4781 ++ drivers/intel/irdma-1.14.33/src/irdma/verbs.h | 440 + .../intel/irdma-1.14.33/src/irdma/virtchnl.c | 1479 + .../intel/irdma-1.14.33/src/irdma/virtchnl.h | 224 + drivers/intel/irdma-1.14.33/src/irdma/ws.c | 737 + drivers/intel/irdma-1.14.33/src/irdma/ws.h | 45 + 66 files changed, 125724 insertions(+) create mode 100644 drivers/intel/irdma-1.14.33/COPYING create mode 100644 drivers/intel/irdma-1.14.33/README_irdma.txt create mode 100755 drivers/intel/irdma-1.14.33/build.sh create mode 100755 drivers/intel/irdma-1.14.33/build_core.sh create mode 100755 drivers/intel/irdma-1.14.33/install_core.sh create mode 100644 drivers/intel/irdma-1.14.33/libirdma-51.0.patch create mode 100644 drivers/intel/irdma-1.14.33/readmefirst.txt create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/Kbuild create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/cm.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/cm.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/configfs.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ctrl.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/debugfs.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/defs.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/distro_ver.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/hmc.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/hmc.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/hw.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/i40e_client.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/i40iw_hw.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/i40iw_hw.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/i40iw_if.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/icrdma_hw.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/icrdma_hw.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_hw.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_hw.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs_apf.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs_avf.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/iidc.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/irdma-abi.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/irdma.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/irdma_kcompat.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/irdma_kcompat.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/kcompat-generator.sh create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/kcompat-lib.sh create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/linux_kcompat.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/main.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/main.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ofed_kcompat.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/oracle_kcompat.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/osdep.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/pble.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/pble.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/protos.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/puda.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/puda.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/rhel_kcompat.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/suse_kcompat.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/trace.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/trace.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/trace_cm.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/type.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ubuntu_kcompat.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/uda.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/uda.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/uda_d.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/uk.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/user.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/utils.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/verbs.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/verbs.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/virtchnl.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/virtchnl.h create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ws.c create mode 100644 drivers/intel/irdma-1.14.33/src/irdma/ws.h diff --git a/drivers/intel/irdma-1.14.33/COPYING b/drivers/intel/irdma-1.14.33/COPYING new file mode 100644 index 000000000..d511905c1 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/COPYING @@ -0,0 +1,339 @@ + GNU GENERAL PUBLIC LICENSE + Version 2, June 1991 + + Copyright (C) 1989, 1991 Free Software Foundation, Inc., + 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA + Everyone is permitted to copy and distribute verbatim copies + of this license document, but changing it is not allowed. + + Preamble + + The licenses for most software are designed to take away your +freedom to share and change it. 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Of course, the commands you use may +be called something other than `show w' and `show c'; they could even be +mouse-clicks or menu items--whatever suits your program. + +You should also get your employer (if you work as a programmer) or your +school, if any, to sign a "copyright disclaimer" for the program, if +necessary. Here is a sample; alter the names: + + Yoyodyne, Inc., hereby disclaims all copyright interest in the program + `Gnomovision' (which makes passes at compilers) written by James Hacker. + + , 1 April 1989 + Ty Coon, President of Vice + +This General Public License does not permit incorporating your program into +proprietary programs. If your program is a subroutine library, you may +consider it more useful to permit linking proprietary applications with the +library. If this is what you want to do, use the GNU Lesser General +Public License instead of this License. diff --git a/drivers/intel/irdma-1.14.33/README_irdma.txt b/drivers/intel/irdma-1.14.33/README_irdma.txt new file mode 100644 index 000000000..d474fa91f --- /dev/null +++ b/drivers/intel/irdma-1.14.33/README_irdma.txt @@ -0,0 +1,1515 @@ +============================================================================== +irdma - Linux* RDMA Driver for the E800 Series and X722 Intel(R) Ethernet Controllers +============================================================================== + +-------- +Contents +-------- +- Overview +- Prerequisites +- Supported OS List +- Building and Installation +- Confirm RDMA Functionality +- iWARP/RoCEv2 Selection +- iWARP Port Mapper (iwpmd) +- Flow Control Settings +- ECN Configuration +- DSCP Configuration +- Memory Requirements +- Resource Profile Limits +- Resource Limits Selector +- RDMA Statistics +- perftest +- MPI +- DMA Buf +- Performance +- Interoperability +- Dynamic Tracing +- Dynamic Debug +- Capturing RDMA Traffic with tcpdump +- Virtualization +- Link Aggregation +- Known Issues/Notes + +-------- +Overview +-------- + +The irdma Linux* driver enables RDMA functionality on RDMA-capable Intel +network devices. Devices supported by this driver: + - Intel(R) Ethernet Controller E800 Series + - Intel(R) Ethernet Network Connection X722 + +The Intel Ethernet 800 Series and X722 each support a different set of RDMA features. + - Intel Ethernet 800 Series supports both iWARP and RoCEv2 RDMA transports, and also supports + congestion management features like priority flow control (PFC) and + explicit congestion notification (ECN). + - X722 supports only iWARP and a more limited set of configuration + parameters. + +Differences between adapters are described in each section of this document. + +For both Intel Ethernet 800 Series and X722, the corresponding LAN driver (ice or i40e) must be +built from source included in this release and installed on your system prior +to installing irdma. + +------------- +Prerequisites +------------- + +- Compile and install the Intel Ethernet 800 Series or X722 LAN PF driver from source included in + this release. Refer to the ice or i40e driver README for installation + instructions. + * For Intel Ethernet 800 Series, use the ice driver. + * For X722 adapters, use the i40e driver. +- For best results, use a fully supported OS from the Supported OS List below. +- For server memory requirements, see the "Memory Requirements" section of this + document. +- Install required packages. Refer to the "Building" section of the rdma-core + README for required packages for your OS: + https://github.com/linux-rdma/rdma-core/blob/v51.0/README.md + * RHEL 7 and SLES: + Install all required packages listed in the rdma-core README. + * RHEL 8: + Install the required packages for RHEL 7, then install the following + additional packages: + dnf install python3-docutils perl-generators python3-Cython python3-devel + * Ubuntu: + Install the required packages listed in the rdma-core README, then + install the following additional package: + apt-get install python3-docutils libsystemd-dev + +* Note: +The following are sample repo files that can be used to get the dependent packages +for rdma-core. However, these may not be all that is required. + +- For SLES 15.2 + http://download.opensuse.org/distribution/leap/15.2/repo/oss + +- For RHEL 8.1 + http://vault.centos.org/8.1.1911/PowerTools/x86_64/os/ + +----------------- +Supported OS List +----------------- + + Supported: + * RHEL 9.4 + * RHEL 8.10 + * RHEL 8.9 + * SLES 15 SP6 + * SLES 15 SP5 + * SLES 15 SP4 + * Ubuntu 20.04.5 LTS Server(5.4 Kernel) + * Ubuntu 22.04 LTS Server(5.15 Kernel) + * Ubuntu 24.04 LTS Server(6.8 Kernel) + * CentOS 7.4 with LTS 4.14 + * Debian 11 + + Supported Not Validated: + * RHEL 9.3 + * RHEL 9.2 + * RHEL 9.1 + * RHEL 9.0 + * RHEL 8.8 + * RHEL 8.7 + * RHEL 7.6 + OFED 4.17-1 + * RHEL 7.5 + OFED 4.17-1 + * RHEL 7.4 + OFED 4.17-1 + * RHEL 7.2 + OFED 4.8-2 + * SLES 15 SP3 + * SLES 15 SP2 + * SLES 15 SP1 + * SLES 12 SP5 + * SLES 15 + OFED 4.17-1 + * SLES 12 SP 4 + OFED 4.17-1 + * SLES 12 SP 3 + OFED 4.17-1 + * Ubuntu 18.04.0 + * Ubuntu 20.04.0 + * Linux kernel stable 6.8.* + * Linux kernel longterm 6.6*, 6.1.*, 5.15.*, 5.10.*, 5.4.*, 4.19.* + +------------------------- +Building and Installation +------------------------- + +If using inbox drivers and libraries skip to step 6. + +To build and install the irdma driver + +1. Decompress the irdma driver archive: + tar zxf irdma-.tgz + +2. Build and install the RDMA driver: + cd irdma- + ./build.sh + + By default, the irdma driver is built using in-distro RDMA libraries and + modules. Optionally, irdma may also be built using OFED modules. See the + Supported OS List above for a list of OSes that support this option. + * Note: Intel products are not validated on other vendors' proprietary + software packages. + To install irdma using OFED modules: + - Download OFED-4.17-1.tgz from the OpenFabrics Alliance: + wget http://openfabrics.org/downloads/OFED/ofed-4.17-1/OFED-4.17-1.tgz + - Decompress the archive: + tar xzvf OFED-4.17.1.tgz + - Install OFED: + cd OFED-4.17-1 + ./install --all + - Reboot after installation is complete. + - Build the irdma driver with the "ofed" option: + cd /path/to/irdma- + ./build.sh ofed + - Continue with the installation steps below. + +3. Load the driver: + RHEL and Ubuntu: + modprobe irdma + + SLES: + modprobe irdma --allow-unsupported + + Notes: + - This modprobe step is required only during installation. Normally, + irdma is autoloaded via a udev rule when ice or i40e is loaded: + /usr/lib/udev/rules.d/90-rdma-hw-modules.rules + - For SLES, to automatically allow loading unsupported modules, add the + following to /etc/modprobe.d/10-unsupported-modules.conf: + allow_unsupported_modules 1 + +The release now has convenience scripts to automate the build and install of rdma-core for +Red Hat, SLES, and Ubuntu distributions. + +These scripts are: +* build_core.sh +* install_core.sh + +For a system connected to the internet, this command (as root) will build and install the core: + ./build_core.sh -y && ./install_core.sh + +The scripts are separate to allow for the migration of the build results to multiple servers. + +The build results are stored in ~/rdma_core_build_ where is the rdma_core revision from +above and can be rsync'ed to multiple hosts and installed via install_core.sh. + +As an example for rdma-core-51.0.tar.gz would be 51.0. + +The detailed usage is: + +build_core.sh -h: +Usage: build_core.sh [-yl] [-e epelrpm] [-t coretar] + +All downloads are opt-in, either by answering a yes/no question or providing the +-y override option. + +The scripts download two items from the internet: the rdma-core tarball and the +epel RPM for rhel 9. + +These downloads can be overridden via the -e and -t options with an absolute +path name for those items that have been pre-downloaded. + +For an airgapped environment, the following RPMs must be provided, either by +copying the Red Hat and SLES repos or by creating a local repo. + +The current build dependencies are: + +SLES: + +The output from this command will list the SLES rpms +rpmspec --parse suse/rdma-core.spec | grep BuildRequires | grep -v curl-mini + +At this time, the list is: + binutils + cmake >= 2.8.11 + gcc + make + ninja + pandoc + perl + pkgconfig + pkgconfig(libnl-3.0) + pkgconfig(libnl-route-3.0) + pkgconfig(libsystemd) + pkgconfig(libudev) + pkgconfig(systemd) + pkgconfig(udev) + python3-base + python3-Cython + python3-devel + python3-docutils + systemd-rpm-macros + valgrind-client-headers + valgrind-devel + +RHEL: + +The output from this command will list the RHEL rpms +rpmspec --parse redhat/rdma-core.spec | grep BuildRequires + +At this time, the list is: + binutils + cmake + gcc + libnl3-devel + ninja-build + pandoc + perl-generators + pkgconf-pkg-config + python3-Cython + python3-devel + python3-docutils + systemd + systemd-devel + valgrind-devel + +UBUNTU: +The output from this command will list the UBUNTU debs +dpkg-checkbuilddeps 2>&1 | sed 's/([^)]*) *//g' | sed 's/dpkg-checkbuilddeps:\serror:\sUnmet build dependencies://g' + +At this time, the list is: + cmake + cython3 + debhelper + dh-systemd + dh-python + dpkg-dev + libnl-3-dev + libnl-route-3-dev + libsystemd-dev + libudev-dev + ninja-build + pandoc + pkg-config + python3-dev + python3-docutils + valgrind + +The following RHEL RPMs are required to support the scripts themselves: + + dnf-plugins-core (dnf based) + yum-utils (yum based) + +To manually build the supporting rdma-core libraries follow steps 4 - 6: + +4. Uninstall any previous versions of rdma-core user-space libraries. + For example, in RHEL: + yum erase rdma-core + + If yum erase doesn't work (on RHEL 8.4 it fails with "Error: The operation would result in removing the following protected packages: systemd"), + use the following command to uninstall the rdma-core packages: + + rpm -e --nodeps ibacm iwpmd libibumad libibverbs librdmacm srp_daemon infiniband-diags 2>/dev/null + rpm -e --nodeps rdma-core + + Note: The errors in post-uninstall scritps of these packages can be ignored with 2>/dev/null. + The packages provided to rpm -e --nodeps above could be looked up with the following command: rpm -e rdma-core + The output is "error: Failed dependencies: rdma-core(x86-64) = is needed by (installed) rdma-core-devel + rdma-core(x86-64) = is needed by (installed) iwpmd + rdma-core(x86-64) = is needed by (installed) libibumad + rdma-core(x86-64) = is needed by (installed) libibverbs + rdma-core(x86-64) = is needed by (installed) ibacm + rdma-core(x86-64) = is needed by (installed) librdmacm + rdma-core(x86-64) = is needed by (installed) srp_daemon" + + To confirm that rdma-core is uninstalled after rpm -e --nodeps run: yum erase rdma-core + The output should look like this: "No match for argument: rdma-core No packages marked for removal... Nothing to do. Complete!" + + + Note: "yum erase rdma-core" will also remove any packages that depend on + rdma-core, such as perftest or fio. Please re-install them after + installing rdma-core. + + RHEL 9.0 does not have pandoc and ninja packages available through redhat repo. + Temporary workaround is to bypass the issue for compiling rdma core by: + sed -i s/"BuildRequires: pandoc"/"#BuildRequires: pandoc"/g rdma-core.spec + sed -i s/"%if 0%{?fedora} >= 33"/"%if 0%{?fedora} >= 33 || 0%{?rhel} >= 9"/g rdma-core.spec + +5. Patch, build, and install rdma-core user space libraries: + + RHEL: + # Download rdma-core-51.0.tar.gz from GitHub + wget https://github.com/linux-rdma/rdma-core/releases/download/v51.0/rdma-core-51.0.tar.gz + # Apply patch libirdma-51.0.patch to rdma-core + tar -xzvf rdma-core-51.0.tar.gz + cd rdma-core-51.0 + patch -p2 < /path/to/irdma-/libirdma-51.0.patch + # Make sure directories rdma-core/redhat and contents are under group 'root' + cd .. + chgrp -R root rdma-core-51.0/redhat + tar -zcvf rdma-core-51.0.tar.gz rdma-core-51.0 + # Build rdma-core + mkdir -p ~/rpmbuild/SOURCES + mkdir -p ~/rpmbuild/SPECS + cp rdma-core-51.0.tar.gz ~/rpmbuild/SOURCES/ + cd ~/rpmbuild/SOURCES + tar -xzvf rdma-core-51.0.tar.gz + cp ~/rpmbuild/SOURCES/rdma-core-51.0/redhat/rdma-core.spec ~/rpmbuild/SPECS/ + cd ~/rpmbuild/SPECS/ + rpmbuild -ba rdma-core.spec + # Install RPMs + cd ~/rpmbuild/RPMS/x86_64 + yum install *51.0*.rpm + + SLES: + # Download rdma-core-51.0.tar.gz from GitHub + wget https://github.com/linux-rdma/rdma-core/releases/download/v51.0/rdma-core-51.0.tar.gz + # Apply patch libirdma-51.0.patch to rdma-core + tar -xzvf rdma-core-51.0.tar.gz + cd rdma-core-51.0 + patch -p2 < /path/to/irdma-/libirdma-51.0.patch + cd .. + # Zip the rdma-core directory into a tar.gz archive + tar -zcvf rdma-core-51.0.tar.gz rdma-core-51.0 + # Create an empty placeholder baselibs.conf file + touch /usr/src/packages/SOURCES/baselibs.conf + # Build rdma-core + cp rdma-core-51.0.tar.gz /usr/src/packages/SOURCES + cp rdma-core-51.0/suse/rdma-core.spec /usr/src/packages/SPECS/ + cd /usr/src/packages/SPECS/ + rpmbuild -ba rdma-core.spec --without=curlmini + cd /usr/src/packages/RPMS/x86_64 + rpm -ivh --force *51.0*.rpm + + Ubuntu: + To create Debian packages from rdma-core: + # Download rdma-core-51.0.tar.gz from GitHub + wget https://github.com/linux-rdma/rdma-core/releases/download/v51.0/rdma-core-51.0.tar.gz + # Apply patch libirdma-51.0.patch to rdma-core + tar -xzvf rdma-core-51.0.tar.gz + cd rdma-core-51.0 + patch -p2 < /path/to/irdma-/libirdma-51.0.patch + # Note: The following change to debian/ibverbs-providers.install may be needed: + # "usr/lib/*/libmana.so*" change to "usr/lib/*/libmana.so.*" + # Build rdma-core + dh clean --with python3,systemd --builddirectory=build-deb + dh build --with systemd --builddirectory=build-deb + sudo dh binary --with systemd --builddirectory=build-deb + # This creates .deb packages in the parent directory + # To install the .deb packages + sudo dpkg -i ../*.deb + +6. Add the following to /etc/security/limits.conf: + * soft memlock unlimited + * hard memlock unlimited + * soft nofile 1048000 + * hard nofile 1048000 + + In addition, the files /etc/systemd/user.conf and /etc/systemd/system.conf may need to have the following line: + DefaultLimitMEMLOCK=1073741824 + This will change the Max locked memory for all process to 1G. + + Restart the active session so new values will take effect. + This avoids any limits on user mode applications as far as pinned memory and number of open files used. + + Note: A reboot may be needed if any RDMA applications were running during the rdma-core reinstall. + +The release includes: +* Driver signed with Intel’s private key in precompiled kernel module form +* Complete source code for this driver +* Intel’s public key + +The Intel public key allows you to authenticate the signed driver in secure boot mode. +To authenticate the signed driver, you must place Intel's public key in the UEFI Secure Boot key database. + +If you decide to recompile the .ko module from the provided source files, the new .ko module will not be signed. +To use this .ko module in Secure Boot mode, you must: +- Sign it yourself with your own private key. +- Add your public key to the UEFI Secure Boot key database. + +-------------------------- +Confirm RDMA functionality +-------------------------- + +After successful installation, RDMA devices are listed in the output of +"ibv_devices". For example: + # ibv_devices + device node GUID + ------ ---------------- + rdmap175s0f0 40a6b70b6f300000 + rdmap175s0f1 40a6b70b6f310000 + +Notes: + - Device names may differ depending on OS or kernel. + - Node GUID is different for the same device in iWARP vs. RoCEv2 mode. + +Each RDMA device is associated with a network interface. The sysfs filesystem +can help show how these devices are related. For example: + - To show RDMA devices associated with the "ens801f0" network interface: + # ls /sys/class/net/ens801f0/device/infiniband/ + rdmap175s0f0 + - To show the network interface associated with the "rdmap175s0f0" RDMA + device: + # ls /sys/class/infiniband/rdmap175s0f0/device/net/ + ens801f0 + +Before running RDMA applications, ensure that all hosts have IP addresses +assigned to the network interface associated with the RDMA device. The RDMA +device uses the IP configuration from the corresponding network interface. +There is no additional configuration required for the RDMA device. + +To confirm RDMA functionality, run rping: + + 1) Start the rping server: + rping -sdvVa [server IP address] + + 2) Start the rping client: + rping -cdvVa [server IP address] -C 10 + + 3) rping will run for 10 iterations (-C 10) and print data payloads on + the console. + + Notes: + - Confirm rping functionality both from each host to itself and between + hosts. For example: + * Run rping server and client both on Host A. + * Run rping server and client both on Host B. + * Run rping server on Host A and rping client on Host B. + * Run rping server on Host B and rping client on Host A. + - When connecting multiple rping clients to a persistent rping server, + older kernels may experience a crash related to the handling of cm_id + values in the kernel stack. With Intel Ethernet 800 Series, this problem typically appears + in the system log as a kernel oops and stack trace pointing to + irdma_accept. The issue has been fixed in kernels 5.4.61 and later. + For patch details, see: + https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/drivers/infiniband/core/ucma.c?h=v5.9-rc2&id=7c11910783a1ea17e88777552ef146cace607b3c + +---------------------- +iWARP/RoCEv2 Selection +---------------------- + +X722: +The X722 adapter supports only the iWARP transport. + +Intel Ethernet 800 Series: +The Intel Ethernet 800 Series supports both iWARP and RoCEv2 transports. By default, the +irdma driver is loaded in iWARP mode. RoCEv2 may be selected globally +(for all ports) using the module parameter "roce_ena=1" + +--- Global Selection +To automatically enable RoCEv2 mode for all ports when the irdma driver is +loaded, add the following line to /etc/modprobe.d/irdma.conf: + options irdma roce_ena=1 + +The irdma driver may also be manually loaded with the "roce_ena=1" parameter +on the modprobe command line. To manually load all irdma ports in RoCEv2 mode: + - If the irdma driver is currently loaded, first unload it: + rmmod irdma + - Reload the driver in RoCEv2 mode: + modprobe irdma roce_ena=1 + +Alternatively, ports may be individually set to RoCEv2 mode using the module +parameter roce_port_cfg set as a binary bit field converted to a decimal number. +All other ports are configured for iWARP mode. + Example 1 - to configure only port 0 in RoCE v2 mode (0001b -> 1): + modprobe irdma roce_port_cfg=1 + Example 2 - to configure both port 0 and port 1 in RoCE v2 mode (0011b -> 3): + modprobe irdma roce_port_cfg=3 + Example 3 - to configure only port 3 in RoCE v2 mode (1000b -> 8): + modprobe irdma roce_port_cfg=8 + +Note: The roce_ena module parameter supersedes roce_port_cfg. + +If the irdma driver is currently loaded, first unload it: + rmmod irdma +Reload the driver with appropriate roce_ena value: + modprobe irdma roce_ena=1 + +------------------------- +iWARP Port Mapper (iwpmd) +------------------------- +The iWARP port mapper service (iwpmd) coordinates with the host network stack +and manages TCP port space for iWARP applications. + +iwpmd is automatically loaded when ice or i40e is loaded via udev rules in +/usr/lib/udev/rules.d/90-iwpmd.rules. + +To verify iWARP port mapper status: + systemctl status iwpmd + +--------------------- +Flow Control Settings +--------------------- + +X722: +The X722 supports only link-level flow control (LFC). + +Intel Ethernet 800 Series: +The Intel Ethernet 800 Series supports both link-level flow control (LFC) and priority +flow control (PFC). Enabling flow control is strongly recommended when using +Intel Ethernet 800 Series in RoCEv2 mode. + +--- Link Level Flow Control (LFC) (Intel Ethernet 800 Series and X722) + +To enable link-level flow control on Intel Ethernet 800 Series or X722, use "ethtool -A". +For example, to enable LFC in both directions (rx and tx): + ethtool -A rx on tx on + +Confirm the setting with "ethtool -a": + ethtool -a + +Sample output: + Pause parameters for interface: + Autonegotiate: on + RX: on + TX: on + RX negotiated: on + TX negotiated: on + +Full enablement of LFC requires the switch or link partner be configured for +rx and tx pause frames. Refer to switch vendor documentation for more details. + +--- Priority Level Flow Control (PFC) (Intel Ethernet 800 Series only) + +Priority flow control (PFC) is supported on Intel Ethernet 800 Series in both willing and +non-willing modes. Intel Ethernet 800 Series also has two Data Center Bridging (DCB) modes: software +and firmware. For more background on software and firmware modes, refer to the +Intel Ethernet 800 Series ice driver README. +- For PFC willing mode, software DCB is recommended. +- For PFC non-willing mode, software DCB must be used. + +Notes: Intel Ethernet 800 Series supports a maximum of 4 traffic classes (TCs), one of which may + have PFC enabled. In addition, iWARP mode requires a VLAN to be configured to fully enable PFC. + + +*** PFC willing mode + +In willing mode, Intel Ethernet 800 Series is "willing" to accept DCB settings from its link +partner. DCB is configured on the link partner (typically a switch), and the +Intel Ethernet 800 Series will automatically discover and apply the DCB settings to its own port. +This simplifies DCB configuration in a larger cluster and eliminates the need +to independently configure DCB on both sides of the link. + +To enable PFC in willing mode on Intel Ethernet 800 Series: +1. Use ethtool to disable firmware DCB. + ethtool --set-priv-flags fw-lldp-agent off + +To confirm settings, use following command: + ethtool --show-priv-flags + +Expected output: + fw-lldp-agent :off + +2. Install OpenLLDP if not already installed: + yum install lldpad + +3. Start the Open LLDP daemon: + lldpad -d + +4. Disable CEE transmission: + lldptool -Ti -V CEE-DCBX enableTx=no + +5. Reset the DCBX mode to be 'auto' (start in IEEE DCBX mode) after the next lldpad restart: + lldptool -Ti -V IEEE-DCBX mode=reset + +6. Configure willing configuration for interface: + lldptool -Ti -V ETS-CFG enableTx=yes willing=yes + +7. Configure willing recommendation for interface: + lldptool -Ti -V ETS-REC enableTx=yes + +8. Configure willing PFC for interface: + lldptool -Ti -V PFC willing=yes enableTx=yes + +9. Terminate the first instance of lldpad that was started (e.g. from initrd): + lldpad -k + +10. Remove lldpad state records from shared memory: + lldpad -s + +11. Restart service lldpad: + systemctl restart lldpad.service + +12. Check CEE mode enableTx settings. Must be no: + lldptool -ti -V CEE-DCBX -c + +Expected output: + enableTx=no + +13. Check DCBX mode settings. Must be auto: + lldptool -ti -V IEEE-DCBX -c + +Expected output: + mode=auto + +Switch DCB and PFC configuration syntax varies by vendor. Consult your switch +manual for details. Sample Arista switch configuration commands: +- Example: Enable PFC for priority 0 on switch port 21 + * Enter configuration mode for switch port 21: + switch#configure + switch(config)#interface ethernet 21/1 + * Turn PFC on: + switch(config-if-Et21/1)#priority-flow-control mode on + * Set priority 0 for "no-drop" (i.e., PFC enabled): + switch(config-if-Et21/1)#priority-flow-control priority 0 no-drop + * Verify switch port PFC configuration: + switch(config-if-Et21/1)#show priority-flow-control +- Example: Enable DCBX on switch port 21 + * Enable DCBX in IEEE mode: + switch(config-if-Et21/1)#dcbx mode ieee + * Show DCBX settings (including neighbor port settings): + switch(config-if-Et21/1)#show dcbx + +*** PFC non-willing mode + +In non-willing mode, DCB settings must be configured on both Intel Ethernet 800 Series and its link +partner. Non-willing mode is software-based. OpenLLDP (lldpad and lldptool) is +recommended. + +To enable non-willing PFC on Intel Ethernet 800 Series: + 1. Disable firmware DCB. Firmware DCB is always willing. If enabled, it + will override any software settings. + ethtool --set-priv-flags fw-lldp-agent off + 2. Install OpenLLDP + yum install lldpad + 3. Start the Open LLDP daemon: + lldpad -d + 4. Verify functionality by showing current DCB settings on the NIC: + lldptool -ti + 5. Configure your desired DCB settings, including traffic classes, + bandwidth allocations, and PFC. + The following example enables PFC on priority 0, maps all priorities to + traffic class (TC) 0, and allocates all bandwidth to TC0. + This simple configuration is suitable for enabling PFC for all traffic, + which may be useful for back-to-back benchmarking. Datacenters will + typically use a more complex configuration to ensure quality-of-service + (QoS). + a. Enable PFC for priority 0: + lldptool -Ti -V PFC willing=no enabled=0 + b. Map all priorities to TC0 and allocate all bandwidth to TC0: + lldptool -Ti -V ETS-CFG willing=no \ + up2tc=0:0,1:0,2:0,3:0,4:0,5:0,6:0,7:0 \ + tsa=0:ets,1:strict,2:strict,3:strict,4:strict,5:strict,6:strict,7:strict \ + tcbw=100,0,0,0,0,0,0,0 + 6. Verify output of "lldptool -ti ": + Chassis ID TLV + MAC: 68:05:ca:a3:89:78 + Port ID TLV + MAC: 68:05:ca:a3:89:78 + Time to Live TLV + 120 + IEEE 8021QAZ ETS Configuration TLV + Willing: no + CBS: not supported + MAX_TCS: 8 + PRIO_MAP: 0:0 1:0 2:0 3:0 4:0 5:0 6:0 7:0 + TC Bandwidth: 100% 0% 0% 0% 0% 0% 0% 0% + TSA_MAP: 0:ets 1:strict 2:strict 3:strict 4:strict 5:strict 6:strict 7:strict + IEEE 8021QAZ PFC TLV + Willing: no + MACsec Bypass Capable: no + PFC capable traffic classes: 8 + PFC enabled: 0 + End of LLDPDU LTV + 7. Configure the same settings on the link partner. + +Full enablement of PFC requires the switch or link partner be configured for +PFC pause frames. Refer to switch vendor documentation for more details. + +Additional notes and example: + The 800 Series supports a maximum of four TCs, only one of which has PFC enabled. + Traffic classes must be contiguous and must start at zero. + ETS bandwidth allocations must total 100%. + Multiple priorities can map to the same TC. + Linux PFC defines eight TCs, but if you are steering traffic using ToS, there are only four priorities + available: 0, 2, 4, and 6, which correspond with ToS 0, 8, 24, and 16 respectively. + +The following example configures RDMA on Priority = 2 and TC = 2: + Follow steps 1 - 5 for non-willing mode above. Then Configure DCB: + a. Enable PFC for priority 2: + lldptool -Ti -V PFC willing=no enabled=2 + b. Map all priorities to TC0, TC1 and TC2 and allocate all bandwidth to TC2: + lldptool -Ti -V ETS-CFG willing=no up2tc=0:0,1:1,2:2,3:0,4:0,5:0,6:0,7:0 \ + tsa=0:ets,1:ets,2:ets,3:strict,4:strict,5:strict,6:strict,7:strict tcbw=0,0,100,0,0,0,0,0 + Note: Even with 0 allocated BW on TC0 and TC1, traffic can still occur on those TC's. + c. Verify settings: + lldptool -ti + Chassis ID TLV + MAC: 12:ce:dc:05:92:25 + Port ID TLV + MAC: 12:ce:dc:05:92:25 + Time to Live TLV + 120 + IEEE 8021QAZ ETS Configuration TLV + Willing: no + CBS: not supported + MAX_TCS: 8 + PRIO_MAP: 0:0 1:1 2:2 3:0 4:0 5:0 6:0 7:0 + TC Bandwidth: 0% 0% 100% 0% 0% 0% 0% 0% + TSA_MAP: 0:ets 1:ets 2:ets 3:strict 4:strict 5:strict 6:strict 7:strict + IEEE 8021QAZ PFC TLV + Willing: no + MACsec Bypass Capable: no + PFC capable traffic classes: 8 + PFC enabled: 2 + End of LLDPDU TL + d. Set the default TOS for all RoCEv2 traffic to 8 (which maps to priority 2): + echo 8 > /sys/kernel/config/rdma_cm/rdma/ports/1/default_roce_tos + + +--- Directing RDMA traffic to a traffic class + +When using PFC, traffic may be directed to one or more traffic classes (TCs). +Because RDMA traffic bypasses the kernel, Linux traffic control methods like +tc or cgroups can't be used. Instead, set the Type of Service (ToS) field on +your application command line. ToS-to-priority mappings are hardcoded in Linux +as follows: + ToS Priority + --- -------- + 0 0 + 8 2 + 24 4 + 16 6 +Priorities are then mapped to traffic classes using ETS using lldptool or switch +utilities. + +Examples of setting ToS 16 in an application: + ucmatose -t 16 + ib_write_bw -t 16 + +Alternatively, for RoCEv2, ToS may be set for all RoCEv2 traffic using +configfs. For example, to set ToS 16 on device rdma, port 1: + mkdir /sys/kernel/config/rdma_cm/rdma + echo 16 > /sys/kernel/config/rdma_cm/rdma/ports/1/default_roce_tos + +In order to use other priorities(i.e. 1, 3, 5, 7), a VLAN is required to be setup using the +egress-qos-map option. For example to map all priority 0 as priority 3: + ip link add link name type vlan id egress-qos-map 0:3 1:0 + +----------------- +ECN Configuration +----------------- +X722: +Congestion control settings are not supported on X722. + +Intel Ethernet 800 Series: +The Intel Ethernet 800 Series supports the following congestion control algorithms: + - iWARP DCTCP + - iWARP TCP New Reno plus ECN + - iWARP TIMELY + - RoCEv2 DCQCN + - RoCEv2 DCTCP + - RoCEv2 TIMELY + +Congestion control settings are accessed through configfs. Additional DCQCN +tunings are available via module parameters. + +--- Configuration in configfs + +To access congestion control settings: + +1. After driver load, change to the irdma configfs directory: + cd /sys/kernel/config/irdma + +2. Create a new directory for each RDMA device you want to configure. + Note: Use "ibv_devices" for a list of RDMA devices. + For example, to create configfs entries for the rdmap device: + mkdir rdmap + +3. List the new directory to get its dynamic congestion control knobs and + values: + cd rdmap + for f in *; do echo -n "$f: "; cat "$f"; done; + + If the interface is in iWARP mode, the files have a "iw_" prefix: + - iw_dctcp_enable + - iw_ecn_enable + - iw_timely_enable + + If the interface is in RoCEv2 mode, the files have a "roce_" prefix: + - roce_dcqcn_enable + - roce_dctcp_enable + - roce_timely_enable + +4. Enable or disable the desired algorithms. + + To enable an algorithm: echo 1 > + For example, to add ECN marker processing to the default TCP New Reno iWARP + congestion control algorithm: + echo 1 > /sys/kernel/config/irdma/rdmap/iw_ecn_enable + + To disable an algorithm: echo 0 > + For example: + echo 0 > /sys/kernel/config/irdma/rdmap/iw_ecn_enable + + To read the current status: cat + + Default values: + iwarp_dctcp_en: off + iwarp_timely_en: off + iwarp_ecn_en: ON + + roce_timely_en: off + roce_dctcp_en: off + roce_dcqcn_en: off + +5. Remove the configfs directory created above. Without removing these + directories, the driver will not unload. + rmdir /sys/kernel/config/irdma/rdmap + +--- Advanced Congestion Control Knobs + +NOTE: These module parameters cannot be used if using inbox drivers + +Module parameters on Intel Ethernet 800 Series for RoCEv2 DCQCN tuning: + dcqcn_enable + Enables the DCQCN algorithm for RoCEv2. + Note: "roce_ena" must also be set to "true". + dcqcn_cc_cfg_valid + Indicates that all DCQCN parameters are valid and should be updated + in registers or QP context. + dcqcn_min_dec_factor + The minimum factor by which the current transmit rate can be + changed when processing a CNP. Value is given as a percentage + (1-100). + dcqcn_min_rate + The minimum value, in Mbits per second, for rate to limit. + dcqcn_F + The number of times to stay in each stage of bandwidth recovery. + dcqcn_T + The number of microseconds that should elapse before increasing the + CWND in DCQCN mode. + dcqcn_B + The number of bytes to transmit before updating CWND in DCQCN mode. + dcqcn_rai_factor + The number of MSS to add to the congestion window in additive + increase mode. + dcqcn_hai_factor + The number of MSS to add to the congestion window in hyperactive + increase mode. + dcqcn_rreduce_mperiod + The minimum time between 2 consecutive rate reductions for a single + flow. Rate reduction will occur only if a CNP is received during + the relevant time interval. + +------------------ +DSCP Configuration +------------------ +The ice driver supports setting DSCP-based Layer 3 Quality of Service (L3 QoS) in the PF driver. + +The following is an example of how to map all RoCEv2 traffic to a DSCP/ToS: +1. Map a DSCP/ToS to a TC + lldptool -T -i -V APP app=,, + where: + : The TC assigned to the DSCP/ToS code point + : 5 for DSCP to TC mapping + : The DSCP/ToS code point + For example, to map DSCP value 63 to traffic class 0: + lldptool -T -i eth0 -V APP app=0,5,63 +2. Set the default_roce_tos + Since the ToS field is 8 bits and the DSCP field is only 6 bits, set the ToS value to + 4 X DSCP value(4 X 63 = 252): + mkdir /sys/kernel/config/rdma_cm/rdma + echo 252 > /sys/kernel/config/rdma_cm/rdma/ports/1/default_roce_tos + +NOTE: + L3 QoS mode is not available when FW-LLDP is enabled. You also cannot enable + FW-LLDP if L3 QoS mode is active. Please see the "L3 QoS mode" section, in the ice README, + for more details. + +------------------- +Memory Requirements +------------------- +Default irdma initialization requires a minimum of ~210 MB (for Intel Ethernet 800 Series) or +~160 MB (for X722) of memory per port. + +For servers where the amount of memory is constrained, you can decrease the +required memory by lowering the resources available to Intel Ethernet 800 Series or X722 by loading +the driver with the following resource profile setting: + + modprobe irdma resource_profile=2 + +To automatically apply the setting when the driver is loaded, add the following +to /etc/modprobe.d/irdma.conf: + options irdma resource_profile=2 + +Note: This can have performance and scaling impacts as the number of queue +pairs and other RDMA resources are decreased in order to lower memory usage to +approximately 55 MB (for Intel Ethernet 800 Series) or 51 MB (for X722) per port. + +----------------------- +Resource Profiles +----------------------- +Resource profiles determine how resources are allocated between PFs and VFs. +Please see the Virtualization section for more information on profiles. + +In the default resource profile, the RDMA resources configured for each +adapter are as follows: + + Intel Ethernet 800 Series (2 ports): + Queue Pairs: 4092 + Completion Queues: 8189 + Memory Regions: 4194302 + X722 (4 ports): + Queue Pairs: 1020 + Completion Queues: 2045 + Memory Regions: 2097150 + +For resource profile 2, the configuration is: + + Intel Ethernet 800 Series (2 ports): + Queue Pairs: 508 + Completion Queues: 1021 + Memory Regions: 524286 + + X722 (4 ports): + Queue Pairs: 252 + Completion Queues: 509 + Memory Regions: 524286 + +------------------------ +Resource Limits Selector +------------------------ +In addition to resource profile, you can further limit resources via the +"limits_sel" module parameter: + +Intel Ethernet 800 Series: + modprobe irdma limits_sel=<0-6> +X722: + modprobe irdma gen1_limits_sel=<0-5> + +To automatically apply this setting when the driver is loaded, add the +following to /etc/modprobe.d/irdma.conf: + options irdma limits_sel= + +The values below apply to a 2-port Intel Ethernet 800 Series. + 0 - Minimum, up to 124 QPs + 1 - Up to 1020 QPs + 2 - Up to 2044 QPs + 3 - Default, up to 4092 QPs + 4 - Up to 16380 QPs + 5 - Up to 65532 QPs + 6 - Maximum, up to 131068 QPs + +For X722, the resource limit selector defaults to a value of 1 and provides +2K QPs. A single X722 port supports a maximum of 32k QPs, and a 4-port X722 +supports up to 8k QPs per port. + +--------------- +RDMA Statistics +--------------- +RDMA protocol statistics for Intel Ethernet 800 Series or X722 are found in sysfs. To display all +counters and values: + cd /sys/class/infiniband/rdmap/hw_counters; + for f in *; do echo -n "$f: "; cat "$f"; done; + +The following counters will increment when RDMA applications are transferring +data over the network in iWARP mode: + - tcpInSegs + - tcpOutSegs + +Available counters: + ip4InDiscards IPv4 packets received and discarded. + ip4InReasmRqd IPv4 fragments received by Protocol Engine. + ip4InMcastOctets IPv4 multicast octets received. + ip4InMcastPkts IPv4 multicast packets received. + ip4InOctets IPv4 octets received. + ip4InPkts IPv4 packets received. + ip4InTruncatedPkts IPv4 packets received and truncated due to insufficient + buffering space in UDA RQ. + ip4OutSegRqd IPv4 fragments supplied by Protocol Engine to the lower + layers for transmission + ip4OutMcastOctets IPv4 multicast octets transmitted. + ip4OutMcastPkts IPv4 multicast packets transmitted. + ip4OutNoRoutes IPv4 datagrams discarded due to routing problem (no hit + in ARP table). + ip4OutOctets IPv4 octets supplied by the PE to the lower layers for + transmission. + ip4OutPkts IPv4 packets supplied by the PE to the lower layers for + transmission. + ip6InDiscards IPv6 packets received and discarded. + ip6InReasmRqd IPv6 fragments received by Protocol Engine. + ip6InMcastOctets IPv6 multicast octets received. + ip6InMcastPkts IPv6 multicast packets received. + ip6InOctets IPv6 octets received. + ip6InPkts IPv6 packets received. + ip6InTruncatedPkts IPv6 packets received and truncated due to insufficient + buffering space in UDA RQ. + ip6OutSegRqd IPv6 fragments received by Protocol Engine + ip6OutMcastOctets IPv6 multicast octets transmitted. + ip6OutMcastPkts IPv6 multicast packets transmitted. + ip6OutNoRoutes IPv6 datagrams discarded due to routing problem (no hit + in ARP table). + ip6OutOctets IPv6 octets supplied by the PE to the lower layers for + transmission. + ip6OutPkts IPv6 packets supplied by the PE to the lower layers for + transmission. + iwInRdmaReads RDMAP total RDMA read request messages received. + iwInRdmaSends RDMAP total RDMA send-type messages received. + iwInRdmaWrites RDMAP total RDMA write messages received. + iwOutRdmaReads RDMAP total RDMA read request messages sent. + iwOutRdmaSends RDMAP total RDMA send-type messages sent. + iwOutRdmaWrites RDMAP total RDMA write messages sent. + iwRdmaBnd RDMA verbs total bind operations carried out. + iwRdmaInv RDMA verbs total invalidate operations carried out. + RxECNMrkd Number of packets that have the ECN bits set to + indicate congestion + cnpHandled Number of Congestion Notification Packets that have + been handled by the reaction point. + cnpIgnored Number of Congestion Notification Packets that have + been ignored by the reaction point. + rxVlanErrors Ethernet received packets with incorrect VLAN_ID. + tcpRetransSegs Total number of TCP segments retransmitted. + tcpInOptErrors TCP segments received with unsupported TCP options or + TCP option length errors. + tcpInProtoErrors TCP segments received that are dropped by TRX due to + TCP protocol errors. + tcpInSegs TCP segments received. + tcpOutSegs TCP segments transmitted. + cnpSent Number of Congestion Notification Packets that have + been sent by the reaction point. + RxUDP UDP segments received without errors + TxUDP UDP segments transmitted without errors + +-------- +perftest +-------- +The perftest package is a set of RDMA microbenchmarks designed to test +bandwidth and latency using RDMA verbs. The package is maintained upstream +here: https://github.com/linux-rdma/perftest + +perftest-4.5-0.17 is recommended. + +Earlier versions of perftest had known issues with iWARP that have since been +fixed. Versions 4.4-0.4 through 4.4-0.18 are therefore NOT recommended. + +To run a basic ib_write_bw test: + 1. Start server + ib_write_bw -R + 2. Start client: + ib_write_bw -R + 3. Benchmark will run to completion and print performance data on both + client and server consoles. + +Notes: + - The "-R" option is required for iWARP and optional for RoCEv2. + - Use "-d " on the perftest command lines to use a specific RDMA + device. + - For ib_read_bw, use "-o 1" for testing with 3rd-party link partners. + - For ib_send_lat and ib_write lat, use "-I 96" to limit inline data size + to the supported value. + - iWARP supports only RC connections. + RoCEv2 supports RC and UD. + Connection types XRC, UC, and DC are not supported. + - Atomic operations are not supported on Intel Ethernet 800 Series or X722. + +----------- +MPI Testing +----------- +--- Intel MPI +Intel MPI uses the OpenFabrics Interfaces (OFI) framework and libfabric user +space libraries to communicate with network hardware. + +* Recommended Intel MPI versions: + Single-rail: Intel MPI 2021.6 + Multi-rail: Intel MPI 2021.6 + + Note: Intel MPI 2019u4 is not recommended due to known incompatabilites with + iWARP. + +* Recommended libfabric version: libfabric-1.11.0 or the latest release + + The Intel MPI package includes a version of libfabric. This "internal" + version is automatically installed along with Intel MPI and used by default. + To use a different ("external") version of libfabric with Intel MPI: + 1. Download libfabric from https://github.com/ofiwg/libfabric. + 2. Build and install it according to the libfabric documentation. + 3. Configure Intel MPI to use a non-internal version of libfabric: + export I_MPI_OFI_LIBRARY_INTERNAL=0 + or source /intel64/bin/mpivars.sh -ofi_internal=0 + 4. Verify your libfabric version by using the I_MPI_DEBUG environment + variable on the mpirun command line: + -genv I_MPI_DEBUG=1 + The libfabric version will appear in the mpirun output. + +* Sample command line for a 2-process pingpong test: + + mpirun -l -n 2 -ppn 1 -host myhost1,myhost2 -genv I_MPI_DEBUG=5 \ + -genv FI_VERBS_MR_CACHE_ENABLE=1 -genv FI_VERBS_IFACE= \ + -genv FI_OFI_RXM_USE_SRX=0 -genv FI_PROVIDER='verbs;ofi_rxm' \ + /path/to/IMB-MPI1 Pingpong + + Notes: + - For RoCEv2 use FI_PROVIDER=psm3 + - Example is for libfabrics 1.8 or greater. For earlier versions, use + "-genv FI_PROVIDER='verbs'" + - SRQ is not supported, set FI_OFI_RXM_USE_SRX=0 + - For Intel MPI 2019u6, use "-genv MPIR_CVAR_CH4_OFI_ENABLE_DATA=0". + - When using Intel MPI, it's recommended to enable only one interface on + your networking device to avoid MPI application connectivity issues or + hangs. This issue affects all Intel MPI transports, including TCP and + RDMA. To avoid the issue, use "ifdown " or "ip link set down + " to disable all network interfaces on your adapter except for + the one used for MPI. + +--- OpenMPI + +* OpenMPI version 4.0.3 is recommended. +* iWARP is not supported after version 4.1.4. + +----------- +Performance +----------- +RDMA performance may be optimized by adjusting system, application, or driver +settings. + +- Flow control is required for best performance in RoCEv2 mode and is optional + in iWARP mode. Both link-level flow control (LFC) and priority flow control + (PFC) are supported, but PFC is recommended. See the "Flow Control Settings" + section of this document for configuration details. + +- For bandwidth applications, multiple queue pairs (QPs) are required for best + performance. For example, in the perftest suite, use "-q 8" on the command + line to run with 8 QP. + +- For best results, configure your application to use CPUs on the same NUMA + node as your adapter. For example: + * To list CPUs local to your NIC: + cat /sys/class/infiniband//device/local_cpulist + * To specify CPUs (e.g., 27-47) when running a perftest application: + taskset -c 24-47 ib_write_bw + * To specify CPUs when running an Intel MPI application: + mpirun -genv I_MPI_PIN_PROCESSOR_LIST=24-47 ./my_prog + +- For some workloads, latency may be improved by enabling push_mode in the + irdma driver. + * Create the configfs directory for your RDMA device: + mkdir /sys/kernel/config/irdma/rdmap + * Enable push_mode: + echo 1 > /sys/kernel/config/irdma/rdmap/push_mode + * Remove the directory + rmdir /sys/kernel/config/irdma/rdmap + +- System and BIOS tunings may also improve performance. Settings vary by + platform - consult your OS and BIOS documentation for details. + In general: + * Disable power-saving features such as P-states and C-states + * Set BIOS CPU power policies to "Performance" or similar + * Set BIOS CPU workload configuration to "I/O Sensitive" or similar + * On RHEL 7.*/8.*, use the "latency-performance" tuning profile: + tuned-adm profile latency-performance + +---------------- +DMA Buf +---------------- + +Download and install intel-i915-dkms by following the instructions in +https://dgpu-docs.intel.com/driver/installation.html + +Modify file /etc/modprobe.d/i915.conf + cat /etc/modprobe.d/i915.conf + options i915 force_probe=* enable_guc=3 enable_rc6=0 prelim_override_p2p_dit=1 + +If the file doesn't exist, create one. Reboot the system after this change. + +Install libfabric and fabtests. There is a modification required in libfabric +as described in the Note section. + +Example: + fi_xe_rdmabw -m device -p "verbs;ofi_rxm" -t write + fi_xe_rdmabw -m host -p "verbs;ofi_rxm" -t write + +Note: +To use DMA Buf with libfabric and irdma, the following change is required in +libfabric prov/verbs/src/verbs_info.c: + +static bool vrb_hmem_supported(const char *dev_name) + +{ + if (ofi_hmem_p2p_disabled()) + + return false; + + */ Adding a check to allow devices to use hmem */ + if (vrb_gl_data.dmabuf_support) + + return true; + + + return false; +} + +For good performance (especially peer-to-peer PCIe READ performance) Intel GPU +with PVC is needed. + +---------------- +Interoperability +---------------- + +--- Mellanox + +Intel Ethernet 800 Series and X722 support interop with Mellanox RoCEv2-capable adapters. + +In tests like ib_send_bw, use -R option to select rdma_cm for connection +establishment. You can also use gid-index with -x option instead of -R: + +Example: + On Intel Ethernet 800 Series or X722: ib_send_bw -F -n 5 -x 0 + On Mellanox : ib_send_bw -F -n 5 -x + + ...where x specifies the gid index value for RoCEv2. + +Look in /sys/class/infiniband/mlx5_0/ports/1/gid_attrs/types directory for +port 1. + +Note: Using RDMA reads with Mellanox may result in poor performance if there is + packet loss. + +--- Chelsio + +X722 supports interop with Chelsio iWARP devices. + +Load Chelsio T4/T5 RDMA driver (iw_cxgb4) with parameter "dack_mode" set to 0. + + modprobe iw_cxgb4 dack_mode=0 + +To automatically apply this setting when the iw_cxgb4 driver is loaded, add the +following to /etc/modprobe.d/iw_cxgb4.conf: + options iw_cxgb4 dack_mode=0 + + +--------------- +Dynamic Tracing +--------------- +Dynamic tracing is available for irdma's connection manager. +Turn on tracing with the following command: + echo 1 > /sys/kernel/debug/tracing/events/irdma_cm/enable + +To retrieve the trace: + cat /sys/kernel/debug/tracing/trace + +------------- +Dynamic Debug +------------- +irdma support Linux dynamic debug. + +To enable all dynamic debug messages upon irdma driver load, use the "dyndbg" +module parameter: + modprobe irdma dyndbg='+p' + +Debug messages will then appear in the system log or dmesg. + +Enabling dynamic debug can be extremely verbose and is not recommended for +normal operation. For more info on dynamic debug, including tips on how to +refine the debug output, see: + https://www.kernel.org/doc/html/v4.11/admin-guide/dynamic-debug-howto.html + +----------------------------------- +Capturing RDMA Traffic with tcpdump +----------------------------------- +RDMA traffic bypasses the kernel and is not normally available to the Linux +tcpdump utility. You may capture RDMA traffic with tcpdump by using port +mirroring on a switch. + +1. Connect 3 hosts to a switch: + - 2 compute nodes to run RDMA traffic + - 1 host to monitor traffic + +2. Configure the switch to mirror traffic from one compute node's switch port + to the monitoring host's switch port. Consult your switch documentation + for syntax. + +3. Unload the irdma driver on the monitoring host: + # rmmod irdma + Traffic may not be captured correctly if the irdma driver is loaded. + +4. Start tcpdump on the monitoring host. For example: + # tcpdump -nXX -i + +5. Run RDMA traffic between the 2 compute nodes. RDMA packets will appear in + tcpdump on the monitoring host. + +------------------- +Virtualization +------------------- +The irdma driver supports virtualization on Intel Ethernet 800 Series only and requires +the iavf driver. Please refer to its README for installation instructions. + +Loading the drivers: +Reload the irdma driver, on the host, with a VF specific resource_profile and +set the number of VFs needed. +The resource_profile value is one of the following: + 0 = PF only(default), no VF support, all resources assigned to PFs + 1 = Weighted VF, most resources assigned to the VFs, the PF gets minimal resources + 2 = Even Distribution, resources are distributed evenly among PFs and VFs + +For example: + modprobe -r irdma + modprobe irdma resource_profile=2 max_rdma_vfs=2 + +Load the ice driver on the host and enable virtualization by setting the +number of VFs. For example, to set 2 VFs: + echo 2 > /sys/class/net/p4p1/device/sriov_numvfs + +Next, start the VM and make sure the iavf and irdma drivers are loaded. For example: + modprobe iavf + modprobe irdma + +Notes: + * The irdma driver must be loaded on the host when the VM is started. Otherwise, + the iavf must be reloaded to enable RDMA functionality. + * If the irdma driver on the host is unloaded, then any client VFs will require + the iavf to be reloaded. + * If LAG is active on an interface, SR-IOV VFs cannot be created on that interface. + * Setting the sriov_numvfs on the host will load iavf driver on the host. + +------------------- +Link Aggregation +------------------- +Link aggregation (LAG) and RDMA are compatible only if all the following are true: +- You are using an Intel Ethernet 800 Series device with the latest drivers and +NVM installed. +- RDMA technology is set to RoCEv2. +- LAG configuration is active-backup. +- Bonding is between two ports within the same device. +- The QoS configuration of the two ports matches prior to the bonding of the +devices. + +If the above conditions are not met the ICE driver will disable RDMA. + +NOTE: The first interface added to an aggregate (bond) is assigned as the +"primary" interface for RDMA and LAG functionality. If LAN interfaces are +assigned to the bond and you remove the primary interface from the bond, RDMA +will not function properly over the bonded interface. To address the issue, +remove all interfaces from the bond and add them again. Interfaces that are not +assigned to the bond will operate normally. + +------------------- +Known Issues/Notes +------------------- + +* Memory Windows are not supported. + +* In iWARP mode, the establishment of a large number of connections may fail due + to port collisions. This issue can occur if in-box rdma-core is used, because + it doesn't enable the port mapper service (iwpmd). + +* RHEL 8.7 +Building irdma on RHEL 8.7 may fail due to issue in scripts/kernel-doc file. +To workaround this issue edit /usr/src/kernels/$(uname -r)/scripts/kernel-doc +Comment out the following line: + # $members =~ s/(?:__)?DECLARE_FLEX_ARRAY\s*\($args,\s*$args\)/$1 $2\[\]/gos; +Replace with: + $members =~ s/(?:__)?DECLARE_FLEX_ARRAY\s*\(([^,)]+),\s*([^,)]+)\)/$1 $2\[\]/gos; + +X722: +* Support for the Intel(R) Ethernet Connection X722 iWARP RDMA VF driver +(i40iwvf) has been discontinued. + +* There may be incompatible drivers in the initramfs image. You can either +update the image or remove the drivers from initramfs. + +Specifically, look for i40e, ib_addr, ib_cm, ib_core, ib_mad, ib_sa, ib_ucm, +ib_uverbs, iw_cm, rdma_cm, rdma_ucm in the output of the following command: + lsinitrd |less +If you see any of those modules, rebuild initramfs with the following command +and include the name of the module in the "" list. For example: + dracut --force --omit-drivers "i40e ib_addr ib_cm ib_core ib_mad ib_sa + ib_ucm ib_uverbs iw_cm rdma_cm rdma_ucm" + + +Intel Ethernet 800 Series: +* Statistics may not be accurate for loopback operations. + +* RDMA is not supported when Intel Ethernet 800 Series is configured for more than 4 ports. + +* Intel Ethernet 800 Series is limited to 4 traffic classes (TCs), one of which may be enabled for + priority flow control (PFC). + +* When using RoCEv2 on Linux kernel version 5.9 or earlier, some iSER operations +may experience errors related to iSER's handling of work requests. To work +around this issue, set the Intel Ethernet 800 Series fragment_count_limit module parameter to 13. + +* RoCEv2 devices require application level flow control in order to prevent message +loss due to insufficient receive buffers. The libfabric RxM provider implements application +level flow control for RDM endpoints running over RoCEv2 queue pairs. The recommended way +to specify the provider in the RDM tests (e.g. fi_rdm) is with -p "ofi_rxm;verbs". + +However, message endpoint tests (e.g. fi_msg_bw) which don't support the libfabric RxM +provider use the verbs provider with -p "verbs" directly and can fail without application +level flow control. + +* iWARP and RoCEv2 do not interoperate. Configure Intel Ethernet 800 Series to use the same protocol(iWARP/ +RoCEv2) as its connection partner. + +X722 and Intel Ethernet 800 Series: +* Some commands (such as 'tc qdisc add' and 'ethtool -L') will cause the ice +driver to close the associated RDMA interface and reopen it. This will disrupt +RDMA traffic for a few seconds until the RDMA interface is available again. + +* NOTE: Installing the ice driver, on RHEL, currently installs ice into initrd. +The implication is that the ice driver will be loaded on boot. The installation +process will also install any currently installed version of irdma into initrd. +This might result in an unintended version of irdma being installed. Depending +on your desired configuration and behavior of ice and irdma please look at the +following instructions to ensure the desired drivers are installed correctly. + + A. Desired that both ice and irdma are loaded on boot (default) + 1. Follow installation procedure for the ice driver + 2. Follow installation procedure for the irdma driver + + B. Desired that only ice driver is loaded on boot + 1. Untar ice driver + 2. Follow installation procedure for ice driver + 3. Untar irdma driver + 4. Follow installation procedure for irdma driver + 5. % dracut --force --omit-drivers "irdma" + + C. Desired that neither ice nor irdma is loaded on boot + 1. Perform all steps in B + 2. % dracut --force --omit-drivers "ice irdma" + +* Note: Application use of fork() +If the RDMA application uses fork(), or any other function that generates a fork() call, +the application must call ibv_fork_init() before any RDMA resources are created. Failure +to do so may results in one or more of the following: data corruption, missed completions, +CQ overflows and SQ stalls. + +------- +Support +------- +For general information, go to the Intel support website at: +http://www.intel.com/support/ + +If an issue is identified with the released source code on a supported kernel +with a supported adapter, email the specific information related to the issue +to linux.nics@intel.com + +------- +License +------- +This software is available to you under a choice of one of two +licenses. You may choose to be licensed under the terms of the GNU +General Public License (GPL) Version 2, available from the file +COPYING in the main directory of this source tree, or the +OpenFabrics.org BSD license below: + + Redistribution and use in source and binary forms, with or + without modification, are permitted provided that the following + conditions are met: + + - Redistributions of source code must retain the above + copyright notice, this list of conditions and the following + disclaimer. + + - Redistributions in binary form must reproduce the above + copyright notice, this list of conditions and the following + disclaimer in the documentation and/or other materials + provided with the distribution. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, +EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF +MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND +NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS +BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN +ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN +CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. + +---------- +Trademarks +---------- +Intel is a trademark or registered trademark of Intel Corporation +or its subsidiaries in the United States and/or other countries. + +* Other names and brands may be claimed as the property of others diff --git a/drivers/intel/irdma-1.14.33/build.sh b/drivers/intel/irdma-1.14.33/build.sh new file mode 100755 index 000000000..9a28c5ef4 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/build.sh @@ -0,0 +1,275 @@ +#!/bin/bash + +# SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +# Copyright (c) 2015 - 2023 Intel Corporation + +print_usage() { + echo + echo "usage: $0 {ofed} {noinstall} {sparse} { ...}" + echo " ofed - compile using OFED 4.17 or above modules" + echo " noinstall - skip driver installation" + echo " sparse - enforce source code checks (requires sparse)" + echo " dir - extra directory to be searched for header files" + exit 1 +} + +get_suse_local_ver() { + CONFIG_SUSE_KERNEL=`grep " CONFIG_SUSE_KERNEL " $1 | cut -d' ' -f3` + if [ "$CONFIG_SUSE_KERNEL" == "1" ]; then + LV=`grep " CONFIG_LOCALVERSION " $1 | cut -d'-' -f2 | sed 's/\.g[[:xdigit:]]\{7\}//'` + LV_A=`echo $LV | cut -d'.' -f1` + LV_B=`echo $LV | cut -s -d'.' -f2` + LV_C=`echo $LV | cut -s -d'.' -f3` + SLE_LOCALVERSION_CODE=$((LV_A * 65536 + LV_B * 256 + LV_C)) + else + SLE_LOCALVERSION_CODE=0 + fi +} + +cmd_initrd() { + echo "Updating initramfs..." + if which dracut > /dev/null 2>&1 ; then + echo 'dracut --force --omit-drivers "irdma i40iw"' + echo "omit_drivers+=\" irdma i40iw \"" > /etc/dracut.conf.d/irdma_omit.conf + dracut --force --omit-drivers "irdma i40iw" + elif which update-initramfs > /dev/null 2>&1 ; then + echo "update-initramfs -u -k $(uname -r)" + update-initramfs -u -k $(uname -r) + else + echo "Unable to update initramfs. You may need to do this manually." + fi +} + +# Use KSRC if defined. +if [ -z "$KSRC" ]; then + + if [ -z "$BUILD_KERNEL" ]; then + BUILD_KERNEL=`uname -r` + fi + + if [ -e /usr/src/kernels/linux-$BUILD_KERNEL/include/config ]; then + KSRC="/usr/src/kernels/linux-$BUILD_KERNEL/" + elif [ -e /usr/src/kernels/$BUILD_KERNEL/include/config ]; then + KSRC="/usr/src/kernels/$BUILD_KERNEL/" + elif [ -e /lib/modules/$BUILD_KERNEL/build/include/config ]; then + KSRC="/lib/modules/$BUILD_KERNEL/build/" + fi + + if [ -z "$KSRC" ]; then + BUILD_KERNEL=`uname -r | sed 's/\([0-9]*\.[0-9]*\)\..*/\1/'` + if [ -e /usr/src/kernels/linux-$BUILD_KERNEL/include/config ]; then + KSRC="/usr/src/kernels/linux-$BUILD_KERNEL/" + elif [ -e /usr/src/kernels/$BUILD_KERNEL/include/config ]; then + KSRC="/usr/src/kernels/$BUILD_KERNEL/" + elif [ -e /lib/modules/$BUILD_KERNEL/build/include/config ]; then + KSRC="/lib/modules/$BUILD_KERNEL/build/" + fi + fi + export KSRC +else + if [ -z "$BUILD_KERNEL" ]; then + found=0 + BUILD_KERNEL=`uname -r` + if [ -e /usr/src/kernels/linux-$BUILD_KERNEL/include/config ]; then + found=1 + elif [ -e /usr/src/kernels/$BUILD_KERNEL/include/config ]; then + found=1 + elif [ -e /lib/modules/$BUILD_KERNEL/build/include/config ]; then + found=1 + fi + + if [ $found -ne 1 ]; then + BUILD_KERNEL=`uname -r | sed 's/\([0-9]*\.[0-9]*\)\..*/\1/'` + if [ -e /usr/src/kernels/linux-$BUILD_KERNEL/include/config ]; then + found=1 + elif [ -e /usr/src/kernels/$BUILD_KERNEL/include/config ]; then + found=1 + elif [ -e /lib/modules/$BUILD_KERNEL/build/include/config ]; then + found=1 + fi + fi + if [ $found -ne 1 ]; then + echo Cannot find BUILD_KERNEL + exit 1 + fi + fi +fi + +if [ -e ${KSRC}/include/linux/kconfig.h ]; then + INCLUDE_KCONF_HDR="-include ${KSRC}/include/linux/kconfig.h" + export INCLUDE_KCONF_HDR +fi + +if [ -e ${KSRC}/include/generated/autoconf.h ]; then + INCLUDE_AUTOCONF_HDR="-include ${KSRC}/include/generated/autoconf.h" + export INCLUDE_AUTOCONF_HDR + get_suse_local_ver "${KSRC}/include/generated/autoconf.h" +elif [ -e ${KSRC}/include/linux/autoconf.h ]; then + INCLUDE_AUTOCONF_HDR="-include ${KSRC}/include/linux/autoconf.h" + export INCLUDE_AUTOCONF_HDR + get_suse_local_ver "${KSRC}/include/linux/autoconf.h" +fi + +if [ -e ${KSRC}/include/generated/utsrelease.h ]; then + UTSRELEASE_HDR="-include ${KSRC}/include/generated/utsrelease.h" + export UTSRELEASE_HDR +fi + +USE_OFED=0 +NO_INSTALL=0 +CHECK=0 +CHECK_FLAGS= +EXTRA_INCS= + +for arg in "$@"; do + if [ "$arg" == "ofed" ]; then + USE_OFED=1 + elif [ "$arg" == "noinstall" ]; then + NO_INSTALL=1 + elif [ "$arg" == "sparse" ]; then + CHECK=1 + CHECK_FLAGS="-fdiagnostic-prefix -D__CHECK_ENDIAN__ -Wsparse-error" + elif [ -d "$arg" ]; then + EXTRA_INCS+="-I${arg} " + fi +done + +# Generate irdma_kcompat_gen.h +export CONFFILE=$KSRC/include/generated/autoconf.h +chmod +x $PWD/src/irdma/kcompat-generator.sh +GSRC=$KSRC +if [ ! -d ${KSRC}/include/rdma ]; then + echo "Detect other Debian/SLES include directory using KSRC..." + # detect other SLES include directory using KSRC + t=$(dirname $KSRC)/$(basename $KSRC) + if [ -L "$t" ]; then + # a symlink + t=$(readlink -f $t) + fi + # SLES + t=${t%-obj*} + # Debian + t=${t/-amd64/-common} + if [ -d ${t}/include/rdma ]; then + GSRC=$t + fi +fi + +echo "KSRC: $KSRC" +echo "GSRC: $GSRC" + +OUT=$PWD/src/irdma/irdma_kcompat_gen.h KSRC=$GSRC QUIET_COMPAT=1 $PWD/src/irdma/kcompat-generator.sh +if [ $? -ne 0 ]; then + echo "Failed to generate $PWD/src/irdma/irdma_kcompat_gen.h" + exit 1 +fi +make -C $KSRC CFLAGS_MODULE="${EXTRA_INCS}" M=$PWD/src/irdma clean + +which nproc > /dev/null 2>&1 +if [ $? -ne 0 ]; then + nproc=1 +else + nproc=`nproc` +fi + +# Run compile-time source code checks if 'sparse' tool is installed +if [ $CHECK -eq 1 ]; then + SPARSE=`which sparse` + if [ -n "$SPARSE" ]; then + echo "Building with source code checker (sparse) enabled" + else + echo "Unable to run source code checks if 'sparse' tool is not installed" + exit 1 + fi +fi + +if [ -e "/lib/modules/$BUILD_KERNEL/extern-symvers/intel_auxiliary.symvers" -a \ + -e "/lib/modules/$BUILD_KERNEL/extern-symvers/auxiliary.symvers" ]; then + echo "WARNING: Two incompatible auxiliary bus drivers installed" + echo "The irdma driver may not load or may not operate properly" + ls /lib/modules/$BUILD_KERNEL/extern-symvers/* +fi + +if [ -e "/lib/modules/$BUILD_KERNEL/extern-symvers/intel_auxiliary.symvers" ]; then + KBUILD_EXTRA_SYMBOLS="/lib/modules/$BUILD_KERNEL/extern-symvers/intel_auxiliary.symvers" + export KBUILD_EXTRA_SYMBOLS +elif [ -e "/lib/modules/$BUILD_KERNEL/extern-symvers/auxiliary.symvers" ]; then + KBUILD_EXTRA_SYMBOLS="/lib/modules/$BUILD_KERNEL/extern-symvers/auxiliary.symvers" + export KBUILD_EXTRA_SYMBOLS +fi + +if [ "$USE_OFED" == "1" ]; then + if [ -z "$OFED_OPENIB_PATH" ]; then + OFED_OPENIB_PATH="/usr/src/openib" + fi + if [ ! -e $OFED_OPENIB_PATH ]; then + echo "Please install OFED development package" + print_usage + fi + + if [ -z "$OFED_VERSION_CODE" ]; then + V1=$(ofed_info | head -1 | cut -d '-' -f 2 | cut -d '.' -f 1) + V2=$(ofed_info | head -1 | cut -d '-' -f 2 | cut -d '.' -f 2 | cut -d ':' -f 1) + OFED_VERSION_CODE=$(( ($V1 << 16) + ($V2 << 8) )) + fi + + if [ ${OFED_VERSION_CODE} -lt $(( (4 << 16) + (8 << 8) )) ]; then + echo "Unsupported OFED version installed, requires 4.8 or above" + exit 1 + fi + + KBUILD_EXTRA_SYMBOLS+=" $OFED_OPENIB_PATH/Module.symvers " + export KBUILD_EXTRA_SYMBOLS + + INCLUDE_COMPAT_HDR="-include $OFED_OPENIB_PATH/include/linux/compat-2.6.h -I$OFED_OPENIB_PATH/include -I$OFED_OPENIB_PATH/include/uapi" + export INCLUDE_COMPAT_HDR + + # WA required to build RHEL OFED using gcc >= 5.x + # - silence certain compilation warnings (for RHEL 7.4-7.6) + KCFLAGS="-Wno-attributes -Wno-address-of-packed-member -Wno-missing-attributes " + # - make the compiler pretend to be gcc 4.x (for RHEL 7.2) + KCFLAGS+="-U__GNUC__ -D__GNUC__=4 " + # WA to prevent including content of kcompat_generated_defs.h + # from LAN or auxiliary_bus driver, as some macros defined there + # may be in conflict in those defined in OFEDs compat.h. + KCFLAGS+="-D_KCOMPAT_GENERATED_DEFS_H_ " + export KCFLAGS + + if [ ${OFED_VERSION_CODE} == $(( (4 << 16) + (8 << 8) )) ]; then + make "CFLAGS_MODULE=-DMODULE -DSLE_LOCALVERSION_CODE=${SLE_LOCALVERSION_CODE} -D__OFED_4_8__ -DOFED_VERSION_CODE=${OFED_VERSION_CODE} ${EXTRA_INCS}" -j$nproc -C $KSRC M=$PWD/src/irdma W=1 C=$CHECK CF="$CHECK_FLAGS" + else + make "CFLAGS_MODULE=-DMODULE -DSLE_LOCALVERSION_CODE=${SLE_LOCALVERSION_CODE} -D__OFED_BUILD__ -DOFED_VERSION_CODE=${OFED_VERSION_CODE} ${EXTRA_INCS}" -j$nproc -C $KSRC M=$PWD/src/irdma W=1 C=$CHECK CF="$CHECK_FLAGS" + fi +else + make "CFLAGS_MODULE=-DMODULE -DSLE_LOCALVERSION_CODE=${SLE_LOCALVERSION_CODE} -DOFED_VERSION_CODE=${OFED_VERSION_CODE} ${EXTRA_INCS}" -j$nproc -C $KSRC M=$PWD/src/irdma W=1 C=$CHECK CF="$CHECK_FLAGS" +fi + +if [ $? -eq 0 ]; then + if [ "$NO_INSTALL" == "0" ]; then + make -C $KSRC CFLAGS_MODULE="${EXTRA_INCS}" M=$PWD/src/irdma INSTALL_MOD_DIR=updates/drivers/infiniband/hw/irdma C=$CHECK CF="$CHECK_FLAGS" modules_install + if [ $? -eq 0 ]; then + rmmod i40iw 2> /dev/null + rm -f /lib/modules/$BUILD_KERNEL/kernel/drivers/infiniband/hw/i40iw/i40iw.ko 2> /dev/null + rm -f /lib/modules/$BUILD_KERNEL/updates/drivers/infiniband/hw/i40iw/i40iw.ko 2> /dev/null + rm -f /lib/modules/$BUILD_KERNEL/kernel/drivers/infiniband/hw/i40iw/i40iw.ko.xz 2> /dev/null + rm -f /lib/modules/$BUILD_KERNEL/updates/drivers/infiniband/hw/i40iw/i40iw.ko.xz 2> /dev/null + echo "Creating /etc/modprobe.d/irdma.conf file ..." + mkdir -p "/etc/modprobe.d/" + if [ -e "/etc/modprobe.d/irdma.conf" ]; then + if [ "" = "$(grep 'blacklist i40iw' /etc/modprobe.d/irdma.conf)" ]; then + echo "blacklist i40iw" >> "/etc/modprobe.d/irdma.conf" + echo "alias i40iw irdma" >> "/etc/modprobe.d/irdma.conf" + fi + else + echo "blacklist i40iw" > "/etc/modprobe.d/irdma.conf" + echo "alias i40iw irdma" >> "/etc/modprobe.d/irdma.conf" + fi + depmod -a + cmd_initrd + else + exit 1 + fi + fi +else + exit 1 +fi diff --git a/drivers/intel/irdma-1.14.33/build_core.sh b/drivers/intel/irdma-1.14.33/build_core.sh new file mode 100755 index 000000000..8304211f3 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/build_core.sh @@ -0,0 +1,299 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# Copyright(c) 2023 Intel Corporation. All rights reserved. +# +# This script downloads and builds the rdma-core from git. +# There is support for SLES and RHEL and clones. +# +# The build results are put into ~/rdma_core-build/rpmbuild. +# +# The access is assumed to be there for the following RHEL repos +# AppStream +# BaseOS +# CRB* +# +# *Note CRB may be called powertools +# +# Access for the additional SLES Package Hub repo is required. +# +# Assuming correct repo access the script will use the spec file to +# load build dependencies automatically and build. + +yes_no() +{ + local url=$1 + if [ "$force_download" -eq 1 ] + then + return 0 + fi + while true + do + read -p "Downloading from $url, Y or N: " response + case $response in + [Yy]) + return 0 + ;; + [Nn]) + return 1 + ;; + esac + done +} + +load_epel9() { + if [ "$nointernet" -eq 1 ] + then + return + fi + if [ -z "$epel_rpm" ] + then + yes_no https://dl.fedoraproject.org/pub/epel/epel-release-latest-9.noarch.rpm || exit 1 + dnf install https://dl.fedoraproject.org/pub/epel/epel-release-latest-9.noarch.rpm -y + else + dnf install $epel_rpm + fi +} + +get_core() { + local version=$1 + local builddir=$2 + pushd ${builddir} + if [ -z "$core_tar" ] + then + yes_no https://github.com/linux-rdma/rdma-core/releases/download/v${version}/rdma-core-${version}.tar.gz || exit 1 + if wget -O /tmp/rdma-core-${version}.tar.gz https://github.com/linux-rdma/rdma-core/releases/download/v${version}/rdma-core-${version}.tar.gz + then + mv /tmp/rdma-core-${version}.tar.gz rdma-core-${version}.tar.gz + rm -rf rdma-core-${version} + tar -zxf rdma-core-${version}.tar.gz + else + echo "Unable to download rdma-core-${version}.tar.gz" + exit 1 + fi + else + if ! tar -zxf $core_tar + then + echo "Unable to extract $core_tar" + exit 1 + fi + fi + popd +} + +get_version() { + local patchdir=$1 + local patchfile=$(echo $patchdir/libirdma-*.patch) + local version=$(basename $patchfile .patch) + echo ${version#libirdma-} +} + +patch_core() { + local version=$1 + local builddir=$3 + local patchfile=$2 + pushd ${builddir}/rdma-core-${version} + patch -p2 < ${patchfile} + popd +} + +get_tar_suffix() { + local version=$1 + echo $(rpmspec --parse $2 | grep '^Source:' | sed "s/.*${version}\.\(.*\)$/\1/") +} + +create_rhel_build() { + local builddir=$2 + local version=$1 + local version_major=${1%.*} + local suffix + pushd ${builddir} + rm -rf ${builddir}/rpmbuild + mkdir -p ${builddir}/rpmbuild/{BUILD,BUILDROOT,RPMS,SOURCES,SPECS,SRPMS,OTHER} + # need to copy spec post patch + cp rdma-core-${version}/redhat/rdma-core.spec ${builddir}/rpmbuild/SPECS + suffix=$(get_tar_suffix $version ${builddir}/rpmbuild/SPECS/rdma-core.spec) + tar -zcf ${builddir}/rpmbuild/SOURCES/rdma-core-${version}.${suffix} rdma-core-${version} + cd ${builddir}/rpmbuild/SPECS + # probe and install dependencies + if type dnf >/dev/null 2>/dev/null; then + dnf install -y dnf-plugins-core rpm-build + dnf builddep -y rdma-core.spec + else + yum install -y yum-utils rpm-build + yum-builddep -y rdma-core.spec + fi + # 0914948e redhat: Support rpmbuild on RHEL9 + sed -i s/"%if 0%{?fedora} >= 33"/"%if 0%{?fedora} >= 33 || 0%{?rhel} >= 9"/g rdma-core.spec + [ "$version_major" -gt 49 ] && sed -i 's/-DPYTHON_EXECUTABLE:PATH/-DPython_EXECUTABLE/' rdma-core.spec + if rpmbuild --noclean -ba --define "_topdir ${builddir}/rpmbuild" rdma-core.spec + then + echo "Build succeeded" + else + echo "Build failed" + exit 1 + fi + popd +} + +create_sles_build() { + local builddir=$2 + local version=$1 + local suffix + pushd ${builddir} + rm -rf ${builddir}/rpmbuild + mkdir -p ${builddir}/rpmbuild/{BUILD,BUILDROOT,RPMS,SOURCES,SPECS,SRPMS,OTHER} + # need to copy spec post patch + cp rdma-core-${version}/suse/rdma-core.spec ${builddir}/rpmbuild/SPECS + suffix=$(get_tar_suffix $version ${builddir}/rpmbuild/SPECS/rdma-core.spec) + touch ${builddir}/rpmbuild//SOURCES/baselibs.conf + tar -zcf ${builddir}/rpmbuild/SOURCES/rdma-core-${version}.${suffix} rdma-core-${version} + cd ${builddir}/rpmbuild/SPECS + # Ensure rpmbuild is here + zypper install -y rpm-build + # probe and install dependencies + rpmspec --parse rdma-core.spec | grep BuildRequires | grep -v curl-mini | cut -d' ' -f2- | xargs -r zypper install -y + if rpmbuild --noclean -ba --define "_topdir ${builddir}/rpmbuild" --define '_build_create_debug 1' rdma-core.spec --without=curlmini + then + echo "Build succeeded" + else + echo "Build failed" + exit 1 + fi + popd +} + +create_ubuntu_build() { + local builddir=$2 + local version=$1 + pushd ${builddir} + rm -rf ${builddir}/debbuild + cp -r rdma-core-${version} ${builddir}/debbuild + cd ${builddir}/debbuild + # apply: + # 766f88465 debian: Exclude libmana.so from ibverbs-providers + sed -i 's/so\*/so.\*/' debian/ibverbs-providers.install + dpkg-checkbuilddeps > /dev/null 2>&1 + if [ $? -ne 0 ] + then + sudo apt-get install --yes $(dpkg-checkbuilddeps 2>&1 | sed 's/([^)]*) *//g' | sed 's/dpkg-checkbuilddeps:\serror:\sUnmet build dependencies://g') + fi + # Build rdma-core + dh clean --with python3,systemd --builddirectory=build-deb + dh build --with systemd --builddirectory=build-deb + if sudo dh binary --with systemd --builddirectory=build-deb + then + echo "Build succeeded" + else + echo "Build failed" + exit 1 + fi +} + +usage() +{ + echo "Usage: $name [-hyl] [-e epelrpm] [-t coretar]" + echo + echo "Options:" + echo "-h - print usage" + echo "-y - do download without prompt" + echo "-l - local (no internet)" + echo "-t - rdma_core download tar ball" + echo "-e - epel rpm" +} + +if [ -r /etc/os-release ] +then + source /etc/os-release +else + echo "Unable to determine release" + exit 1 +fi + +name=$(basename $0) +force_download=0 +nointernet=0 +cdir=$(pwd) +while getopts 'hlye:t:' opt +do + case "$opt" in + y) + force_download=1 + ;; + l) + nointernet=1 + ;; + e) + epel_rpm=$(realpath -m --relative-to=$cdir $OPTARG) + if [ -z "$epel_rpm" -o ! -f $epel_rpm ] + then + echo "Invalid epel file: $OPTARG not in $cdir" + exit 1 + fi + ;; + t) + core_tar=$(realpath -m --relative-to=$cdir $OPTARG) + if [ -z "$core_tar" -o ! -f $core_tar ] + then + echo "Invalid coretar file: $OPTARG not in $cdir" + exit 1 + fi + ;; + h) + usage + exit 0 + ;; + ?) + usage + exit 1 + ;; + esac +done +if [ $nointernet -eq 1 -a -z "$core_tar" ] +then + echo "ERROR: -l and -t must both be specified" + usage + exit 1 +fi + + +# patch defaults for directory of script +patchdir=$(realpath `dirname "$0"`) +CORE_VERSION=$(get_version $patchdir) +builddir=~/rdma_core_build_${CORE_VERSION} +mkdir -p ${builddir} +# determine distro +case $ID in +rhel|rocky|centos|ol|anolis|almalinux|openEuler) + # RHEL9 needs epel + if echo $VERSION_ID | grep '^9' + then + load_epel9 + fi + # Download rdma-core from GitHub + get_core $CORE_VERSION $builddir + # patch core + patch_core $CORE_VERSION ${patchdir}/libirdma-${CORE_VERSION}.patch $builddir + # build rdma-core + create_rhel_build $CORE_VERSION $builddir + ;; +sles) + # Download rdma-core from GitHub + get_core $CORE_VERSION $builddir + # patch core + patch_core $CORE_VERSION ${patchdir}/libirdma-${CORE_VERSION}.patch $builddir + # build rdma-core + create_sles_build $CORE_VERSION $builddir + ;; +ubuntu) + # Download rdma-core from GitHub + get_core $CORE_VERSION $builddir + # patch core + patch_core $CORE_VERSION ${patchdir}/libirdma-${CORE_VERSION}.patch $builddir + # build rdma-core + create_ubuntu_build $CORE_VERSION $builddir + ;; +*) + echo "Unknown distribution" + exit 1 + ;; +esac diff --git a/drivers/intel/irdma-1.14.33/install_core.sh b/drivers/intel/irdma-1.14.33/install_core.sh new file mode 100755 index 000000000..797e6e75a --- /dev/null +++ b/drivers/intel/irdma-1.14.33/install_core.sh @@ -0,0 +1,175 @@ +#!/bin/bash +# SPDX-License-Identifier: GPL-2.0 +# Copyright(c) 2023 Intel Corporation. All rights reserved. + +# $1 is the directory containing the built packages +# assumes directory only contains packages from +# rdma-core. The directory home directory is probed +# for rdma_core_build* and the directory with the +# highest lexical sort is picked. To override +# that selection the explicit rpm directory can be passed +# as an argument. +# +# The script assumes that ALL the pages in install directory will be installed. + +cleanup () { + rm -f /tmp/built$$.txt /tmp/installed$$.txt +} + +usage() +{ + echo "Usage: $name [-h] [builddir]" + echo + echo "Options:" + echo "-h - print usage" + echo + echo "The first arg is the builddir" + echo "otherwise the \$HOME/rdma_core_build* is used" +} + +trap cleanup SIGINT SIGTERM + +if [ -r /etc/os-release ] +then + source /etc/os-release +else + echo "Unable to determine release" + exit 1 +fi + +case $ID in +rhel|rocky|centos|ol|sles|anolis|almalinux|openEuler) + pkgdirsuffix="rpmbuild/RPMS/$(uname -m)" + pkgtype=rpm + ;; +ubuntu) + pkgdirsuffix="." + pkgtype=deb + ;; +*) + echo "Unknown distribution" + exit 1 + ;; +esac + +cdir=$(pwd) +while getopts 'h' opt +do + case "$opt" in + h) + usage + exit 0 + ;; + ?) + usage + exit 1 + ;; + esac +done + +if [ -z "$1" ] +then + # sort order determines + builddir=$(ls -d ~/rdma_core_build* | tail -1) + if [ -z "$builddir" -o ! -d "$builddir" ] + then + echo build directory cannot be determinted + exit 1 + fi + pkgdir=${builddir}/${pkgdirsuffix} +else + pkgdir=$(realpath -m --relative-to=$cdir $1) + if ! ls ${pkgdir}/*.${pkgtype} > /dev/null 2>&1 + then + echo "$pkgdir has no ${pkgtype} packages" + usage + exit 1 + fi +fi +if [ ! -d "${pkgdir}" ] +then + echo ${pkgdir} not found + usage + exit 1 +fi + +get_built() +{ + rm -f /tmp/built$$.txt + # build a list of package names from built files + case $pkgtype in + rpm) + rpm -qp --qf "%{NAME}\n" *.rpm > /tmp/built$$.txt + ;; + deb) + for pkg in $(echo *.deb) + do + dpkg -f $pkg Package >> /tmp/built$$.txt + done + ;; + esac +} + +remove_installed() +{ + rm -f /tmp/installed$$.txt + case $pkgtype in + rpm) + for name in `cat /tmp/built$$.txt` libmana-1 libmana-1-debuginfo + do + if rpm -q $name 2>/dev/null + then + echo $name >> /tmp/installed$$.txt + fi + done + [ -f /tmp/installed$$.txt ] && rpm -e --nodeps `cat /tmp/installed$$.txt` + ;; + deb) + for name in `cat /tmp/built$$.txt` + do + if dpkg -l $name > /dev/null 2>&1 + then + echo $name >> /tmp/installed$$.txt + fi + done + [ -f /tmp/installed$$.txt ] && dpkg -r --force-depends `cat /tmp/installed$$.txt` + ;; + esac +} + +do_install() { + case $ID in + rhel|rocky|centos|ol|anolis|almalinux|openEuler) + get_built + remove_installed + if type dnf >/dev/null 2>/dev/null + then + dnf install -y *.rpm + else + yum install -y *.rpm + fi + ;; + sles) + get_built + remove_installed + if zypper install --help | grep -q -- '--allow-unsigned-rpm' + then + zypper install -y --allow-unsigned-rpm *.rpm + elif zypper --help | grep -q -- '--no-gpg-checks' + then + zypper --no-gpg-checks install -y *.rpm + else + zypper install -y *.rpm + fi + ;; + ubuntu) + get_built + remove_installed + dpkg -i *.deb + ;; + esac +} + +pushd $pkgdir +do_install +cleanup diff --git a/drivers/intel/irdma-1.14.33/libirdma-51.0.patch b/drivers/intel/irdma-1.14.33/libirdma-51.0.patch new file mode 100644 index 000000000..9d25d02f6 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/libirdma-51.0.patch @@ -0,0 +1,5126 @@ +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/kernel-boot/rdma-description.rules nd_linux-irdma-rdma-core/rdma-core-51.0/kernel-boot/rdma-description.rules +--- nd_linux-irdma-rdma-core/rdma-core-copy/kernel-boot/rdma-description.rules 2024-07-03 16:16:04.612700004 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/kernel-boot/rdma-description.rules 2024-07-03 16:16:04.635700230 -0700 +@@ -24,11 +24,15 @@ + # Hardware that supports iWarp + DRIVERS=="cxgb4", ENV{ID_RDMA_IWARP}="1" + DRIVERS=="i40e", ENV{ID_RDMA_IWARP}="1" ++DRIVERS=="ice", ENV{ID_RDMA_IWARP}="1" ++DRIVERS=="iavf", ENV{ID_RDMA_IWARP}="1" + + # Hardware that supports RoCE + DRIVERS=="be2net", ENV{ID_RDMA_ROCE}="1" + DRIVERS=="bnxt_en", ENV{ID_RDMA_ROCE}="1" + DRIVERS=="hns", ENV{ID_RDMA_ROCE}="1" ++DRIVERS=="ice", ENV{ID_RDMA_ROCE}="1" ++DRIVERS=="iavf", ENV{ID_RDMA_ROCE}="1" + DRIVERS=="mlx4_core", ENV{ID_RDMA_ROCE}="1" + DRIVERS=="mlx5_core", ENV{ID_RDMA_ROCE}="1" + DRIVERS=="qede", ENV{ID_RDMA_ROCE}="1" +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/kernel-headers/rdma/irdma-abi.h nd_linux-irdma-rdma-core/rdma-core-51.0/kernel-headers/rdma/irdma-abi.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/kernel-headers/rdma/irdma-abi.h 2024-07-03 16:16:04.625700132 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/kernel-headers/rdma/irdma-abi.h 2024-07-03 16:16:11.195764909 -0700 +@@ -1,6 +1,6 @@ +-/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB */ ++/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */ + /* +- * Copyright (c) 2006 - 2021 Intel Corporation. All rights reserved. ++ * Copyright (c) 2006 - 2022 Intel Corporation. All rights reserved. + * Copyright (c) 2005 Topspin Communications. All rights reserved. + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved. +@@ -20,11 +20,19 @@ + IRDMA_MEMREG_TYPE_MEM = 0, + IRDMA_MEMREG_TYPE_QP = 1, + IRDMA_MEMREG_TYPE_CQ = 2, ++ IRDMA_MEMREG_TYPE_SRQ = 3, + }; + + enum { + IRDMA_ALLOC_UCTX_USE_RAW_ATTR = 1 << 0, + IRDMA_ALLOC_UCTX_MIN_HW_WQ_SIZE = 1 << 1, ++ IRDMA_ALLOC_UCTX_MAX_HW_SRQ_QUANTA = 1 << 2, ++ IRDMA_SUPPORT_WQE_FORMAT_V2 = 1 << 3, ++ IRDMA_SUPPORT_MAX_HW_PUSH_LEN = 1 << 4, ++}; ++ ++enum { ++ IRDMA_CREATE_QP_USE_START_WQE_IDX = 1 << 0, + }; + + struct irdma_alloc_ucontext_req { +@@ -54,7 +62,8 @@ + __u8 rsvd2; + __aligned_u64 comp_mask; + __u16 min_hw_wq_size; +- __u8 rsvd3[6]; ++ __u32 max_hw_srq_quanta; ++ __u16 max_hw_push_len; + }; + + struct irdma_alloc_pd_resp { +@@ -71,9 +80,20 @@ + __aligned_u64 user_shadow_area; + }; + ++struct irdma_create_srq_req { ++ __aligned_u64 user_srq_buf; ++ __aligned_u64 user_shadow_area; ++}; ++ ++struct irdma_create_srq_resp { ++ __u32 srq_id; ++ __u32 srq_size; ++}; ++ + struct irdma_create_qp_req { + __aligned_u64 user_wqe_bufs; + __aligned_u64 user_compl_ctx; ++ __aligned_u64 comp_mask; + }; + + struct irdma_mem_reg_req { +@@ -103,6 +123,9 @@ + __u8 lsmm; + __u8 rsvd; + __u32 qp_caps; ++ __aligned_u64 comp_mask; ++ __u8 start_wqe_idx; ++ __u8 rsvd2[7]; + }; + + struct irdma_modify_qp_resp { +@@ -110,7 +133,8 @@ + __aligned_u64 push_db_mmap_key; + __u16 push_offset; + __u8 push_valid; +- __u8 rsvd[5]; ++ __u8 rd_fence_rate; ++ __u8 rsvd[4]; + }; + + struct irdma_create_ah_resp { +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/abi.h nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/abi.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/abi.h 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/abi.h 2024-07-03 16:16:11.191764870 -0700 +@@ -1,5 +1,5 @@ + /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +-/* Copyright (C) 2019 - 2020 Intel Corporation */ ++/* Copyright (C) 2019 - 2023 Intel Corporation */ + #ifndef PROVIDER_IRDMA_ABI_H + #define PROVIDER_IRDMA_ABI_H + +@@ -22,7 +22,7 @@ + DECLARE_DRV_CMD(irdma_ucreate_qp, IB_USER_VERBS_CMD_CREATE_QP, + irdma_create_qp_req, irdma_create_qp_resp); + DECLARE_DRV_CMD(irdma_umodify_qp, IB_USER_VERBS_EX_CMD_MODIFY_QP, +- irdma_modify_qp_req, irdma_modify_qp_resp); ++ empty, irdma_modify_qp_resp); + DECLARE_DRV_CMD(irdma_get_context, IB_USER_VERBS_CMD_GET_CONTEXT, + irdma_alloc_ucontext_req, irdma_alloc_ucontext_resp); + DECLARE_DRV_CMD(irdma_ureg_mr, IB_USER_VERBS_CMD_REG_MR, +@@ -31,5 +31,13 @@ + irdma_mem_reg_req, empty); + DECLARE_DRV_CMD(irdma_ucreate_ah, IB_USER_VERBS_CMD_CREATE_AH, + empty, irdma_create_ah_resp); ++DECLARE_DRV_CMD(irdma_ucreate_srq, IB_USER_VERBS_CMD_CREATE_SRQ, ++ irdma_create_srq_req, irdma_create_srq_resp); + ++struct irdma_modify_qp_cmd { ++ struct ibv_modify_qp_ex ibv_cmd; ++ __u8 sq_flush; ++ __u8 rq_flush; ++ __u8 rsvd[6]; ++}; + #endif /* PROVIDER_IRDMA_ABI_H */ +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/defs.h nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/defs.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/defs.h 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/defs.h 2024-07-03 16:16:11.193764889 -0700 +@@ -5,6 +5,7 @@ + + #include "osdep.h" + ++ + #define IRDMA_QP_TYPE_IWARP 1 + #define IRDMA_QP_TYPE_UDA 2 + #define IRDMA_QP_TYPE_ROCE_RC 3 +@@ -15,18 +16,29 @@ + #define IRDMA_CQE_QTYPE_RQ 0 + #define IRDMA_CQE_QTYPE_SQ 1 + +-#define IRDMA_QP_SW_MIN_WQSIZE 8u /* in WRs*/ ++#define IRDMA_QP_SW_MIN_WQSIZE 8 /* in WRs*/ + #define IRDMA_QP_WQE_MIN_SIZE 32 + #define IRDMA_QP_WQE_MAX_SIZE 256 + #define IRDMA_QP_WQE_MIN_QUANTA 1 + #define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2 + #define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3 + ++#define IRDMA_DEFAULT_MAX_PUSH_LEN 8192 ++ + #define IRDMA_SQ_RSVD 258 + #define IRDMA_RQ_RSVD 1 ++#define IRDMAQP_ATOMIC_WRITE_FRAG_LEN 0x8 ++ ++#define IRDMA_FEATURE_RTS_AE BIT_ULL(0) ++#define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1) ++#define IRDMA_FEATURE_RELAX_RQ_ORDER BIT_ULL(2) ++#define IRDMA_FEATURE_ENFORCE_SQ_SIZE BIT_ULL(3) ++#define IRDMA_FEATURE_FORCE_FENCE BIT_ULL(4) ++#define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5) ++#define IRDMA_FEATURE_ATOMIC_OPS BIT_ULL(6) ++#define IRDMA_FEATURE_SRQ BIT_ULL(7) ++#define IRDMA_FEATURE_CQE_TIMESTAMPING BIT_ULL(8) + +-#define IRDMA_FEATURE_RTS_AE 1ULL +-#define IRDMA_FEATURE_CQ_RESIZE 2ULL + #define IRDMAQP_OP_RDMA_WRITE 0x00 + #define IRDMAQP_OP_RDMA_READ 0x01 + #define IRDMAQP_OP_RDMA_SEND 0x03 +@@ -38,114 +50,231 @@ + #define IRDMAQP_OP_LOCAL_INVALIDATE 0x0a + #define IRDMAQP_OP_RDMA_READ_LOC_INV 0x0b + #define IRDMAQP_OP_NOP 0x0c ++#define IRDMAQP_OP_ATOMIC_FETCH_ADD 0x0f ++#define IRDMAQP_OP_ATOMIC_COMPARE_SWAP_ADD 0x11 ++#define IRDMAQP_OP_ATOMIC_WRITE 0x12 ++#define IRDMAQP_OP_FLUSH_MEM_REGION 0x13 ++ ++#define LS_64_1(val, bits) ((__u64)(uintptr_t)(val) << (bits)) ++#define RS_64_1(val, bits) ((__u64)(uintptr_t)(val) >> (bits)) ++#define LS_32_1(val, bits) ((__u32)((val) << (bits))) ++#define RS_32_1(val, bits) ((__u32)((val) >> (bits))) + ++#define IRDMA_CQPHC_QPCTX_S 0 + #define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0) ++#define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0 + #define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0) ++#define IRDMA_CQ_DBSA_CQEIDX_S 0 + #define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0) ++#define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0 + #define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0) ++#define IRDMA_CQ_DBSA_ARM_NEXT_S 14 + #define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14) ++#define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15 + #define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15) ++#define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16 + #define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16) + + /* CQP and iWARP Completion Queue */ ++#define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S + #define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX + ++#define IRDMA_CQ_MINERR_S 0 + #define IRDMA_CQ_MINERR GENMASK_ULL(15, 0) ++#define IRDMA_CQ_MAJERR_S 16 + #define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16) ++#define IRDMA_CQ_WQEIDX_S 32 + #define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32) ++#define IRDMA_CQ_EXTCQE_S 50 + #define IRDMA_CQ_EXTCQE BIT_ULL(50) ++#define IRDMA_OOO_CMPL_S 54 + #define IRDMA_OOO_CMPL BIT_ULL(54) ++#define IRDMA_CQ_ERROR_S 55 + #define IRDMA_CQ_ERROR BIT_ULL(55) ++#define IRDMA_CQ_SQ_S 62 + #define IRDMA_CQ_SQ BIT_ULL(62) + ++#define IRDMA_CQ_SRQ_S 52 ++#define IRDMA_CQ_SRQ BIT_ULL(52) ++#define IRDMA_CQ_VALID_S 63 + #define IRDMA_CQ_VALID BIT_ULL(63) + #define IRDMA_CQ_IMMVALID BIT_ULL(62) ++#define IRDMA_CQ_UDSMACVALID_S 61 + #define IRDMA_CQ_UDSMACVALID BIT_ULL(61) ++#define IRDMA_CQ_UDVLANVALID_S 60 + #define IRDMA_CQ_UDVLANVALID BIT_ULL(60) ++#define IRDMA_CQ_UDSMAC_S 0 + #define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0) ++#define IRDMA_CQ_UDVLAN_S 48 + #define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48) + + #define IRDMA_CQ_IMMDATA_S 0 +-#define IRDMA_CQ_IMMDATA_M (0xffffffffffffffffULL << IRDMA_CQ_IMMVALID_S) ++#define IRDMA_CQ_IMMVALID_S 62 ++#define IRDMA_CQ_IMMDATA GENMASK_ULL(125, 62) ++#define IRDMA_CQ_IMMDATALOW32_S 0 + #define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0) ++#define IRDMA_CQ_IMMDATAUP32_S 32 + #define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32) ++#define IRDMACQ_PAYLDLEN_S 0 + #define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0) +-#define IRDMACQ_TCPSEQNUMRTT GENMASK_ULL(63, 32) ++#define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS_S 32 ++#define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32) ++#define IRDMACQ_INVSTAG_S 0 + #define IRDMACQ_INVSTAG GENMASK_ULL(31, 0) ++#define IRDMACQ_QPID_S 32 + #define IRDMACQ_QPID GENMASK_ULL(55, 32) + ++#define IRDMACQ_UDSRCQPN_S 0 + #define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0) ++#define IRDMACQ_PSHDROP_S 51 + #define IRDMACQ_PSHDROP BIT_ULL(51) ++#define IRDMACQ_STAG_S 53 + #define IRDMACQ_STAG BIT_ULL(53) ++#define IRDMACQ_IPV4_S 53 + #define IRDMACQ_IPV4 BIT_ULL(53) ++#define IRDMACQ_SOEVENT_S 54 + #define IRDMACQ_SOEVENT BIT_ULL(54) ++#define IRDMACQ_OP_S 56 + #define IRDMACQ_OP GENMASK_ULL(61, 56) + + /* Manage Push Page - MPP */ + #define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff + #define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff + ++#define IRDMAQPSQ_OPCODE_S 32 + #define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32) ++#define IRDMAQPSQ_COPY_HOST_PBL_S 43 + #define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43) ++#define IRDMAQPSQ_ADDFRAGCNT_S 38 + #define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38) ++#define IRDMAQPSQ_PUSHWQE_S 56 + #define IRDMAQPSQ_PUSHWQE BIT_ULL(56) ++#define IRDMAQPSQ_STREAMMODE_S 58 + #define IRDMAQPSQ_STREAMMODE BIT_ULL(58) ++#define IRDMAQPSQ_WAITFORRCVPDU_S 59 + #define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59) ++#define IRDMAQPSQ_READFENCE_S 60 + #define IRDMAQPSQ_READFENCE BIT_ULL(60) ++#define IRDMAQPSQ_LOCALFENCE_S 61 + #define IRDMAQPSQ_LOCALFENCE BIT_ULL(61) ++#define IRDMAQPSQ_UDPHEADER_S 61 + #define IRDMAQPSQ_UDPHEADER BIT_ULL(61) ++#define IRDMAQPSQ_L4LEN_S 42 + #define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42) ++#define IRDMAQPSQ_SIGCOMPL_S 62 + #define IRDMAQPSQ_SIGCOMPL BIT_ULL(62) ++#define IRDMAQPSQ_VALID_S 63 + #define IRDMAQPSQ_VALID BIT_ULL(63) + ++#define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S + #define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX ++#define IRDMAQPSQ_FRAG_VALID_S 63 + #define IRDMAQPSQ_FRAG_VALID BIT_ULL(63) ++#define IRDMAQPSQ_FRAG_LEN_S 32 + #define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32) ++#define IRDMAQPSQ_FRAG_STAG_S 0 + #define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0) ++#define IRDMAQPSQ_GEN1_FRAG_LEN_S 0 + #define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0) ++#define IRDMAQPSQ_GEN1_FRAG_STAG_S 32 + #define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32) ++#define IRDMAQPSQ_REMSTAGINV_S 0 + #define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0) ++#define IRDMAQPSQ_DESTQKEY_S 0 + #define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0) ++#define IRDMAQPSQ_DESTQPN_S 32 + #define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32) +-#define IRDMAQPSQ_AHID GENMASK_ULL(16, 0) ++#define IRDMAQPSQ_AHID_S 0 ++#define IRDMAQPSQ_AHID GENMASK_ULL(24, 0) ++#define IRDMAQPSQ_INLINEDATAFLAG_S 57 + #define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57) + + #define IRDMA_INLINE_VALID_S 7 ++#define IRDMAQPSQ_INLINEDATALEN_S 48 + #define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48) ++#define IRDMAQPSQ_IMMDATAFLAG_S 47 + #define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47) ++#define IRDMAQPSQ_REPORTRTT_S 46 + #define IRDMAQPSQ_REPORTRTT BIT_ULL(46) + ++#define IRDMAQPSQ_COMBINED_SGE_INLINE_RELIABLE_S 45 ++#define IRDMAQPSQ_COMBINED_SGE_INLINE_RELIABLE BIT_ULL(45) ++#define IRDMAQPSQ_COMBINED_SGE_INLINE_UNRELIABLE_S 63 ++#define IRDMAQPSQ_COMBINED_SGE_INLINE_UNRELIABLE BIT_ULL(63) ++ ++#define IRDMAQPSQ_FLUSH_MEM_LEN_S 0 ++#define IRDMAQPSQ_FLUSH_MEM_LEN GENMASK_ULL(31, 0) ++#define IRDMAQPSQ_SELECTIVITY_S 52 ++#define IRDMAQPSQ_SELECTIVITY GENMASK_ULL(53, 52) ++#define IRDMAQPSQ_PLACEMENT_TYPE_S 48 ++#define IRDMAQPSQ_PLACEMENT_TYPE GENMASK_ULL(51, 48) ++#define IRDMAQPSQ_IMMDATA_S 0 + #define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0) ++#define IRDMAQPSQ_REMSTAG_S 0 + #define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0) + ++#define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S + #define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX + ++#define IRDMAQPSQ_STAGRIGHTS_S 48 + #define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48) ++#define IRDMAQPSQ_VABASEDTO_S 53 + #define IRDMAQPSQ_VABASEDTO BIT_ULL(53) ++#define IRDMAQPSQ_MEMWINDOWTYPE_S 54 + #define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54) + ++#define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S + #define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX ++#define IRDMAQPSQ_PARENTMRSTAG_S 32 + #define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32) ++#define IRDMAQPSQ_MWSTAG_S 0 + #define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0) + ++#define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S + #define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX + ++#define IRDMAQPSQ_FLUSH_MR_S 20 ++#define IRDMAQPSQ_FLUSH_MR BIT_ULL(20) ++#define IRDMAQPSQ_REMOTE_ATOMICS_EN_S 55 ++#define IRDMAQPSQ_REMOTE_ATOMICS_EN BIT_ULL(55) ++ ++#define IRDMAQPSQ_LOCSTAG_S 0 + #define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0) + + /* iwarp QP RQ WQE common fields */ ++#define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S + #define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT ++ ++#define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S + #define IRDMAQPRQ_VALID IRDMAQPSQ_VALID ++ ++#define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S + #define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX ++ ++#define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S + #define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN ++ ++#define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S + #define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG ++ ++#define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S + #define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO + + #define IRDMAPFINT_OICR_HMC_ERR_M BIT(26) + #define IRDMAPFINT_OICR_PE_PUSH_M BIT(27) + #define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28) + +-#define IRDMA_CQP_INIT_WQE(wqe) memset(wqe, 0, 64) ++#define IRDMA_GET_RING_OFFSET(_ring, _i) \ ++ ( \ ++ ((_ring).head + (_i)) % (_ring).size \ ++ ) + ++#define IRDMA_GET_CQ_ELEM_AT_OFFSET(_cq, _i, _cqe) \ ++ { \ ++ __u32 offset; \ ++ offset = IRDMA_GET_RING_OFFSET((_cq)->cq_ring, _i); \ ++ (_cqe) = (_cq)->cq_base[offset].buf; \ ++ } + #define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \ + ( \ + (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \ +@@ -168,7 +297,7 @@ + + #define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \ + { \ +- register __u32 size; \ ++ __u32 size; \ + size = (_ring).size; \ + if (!IRDMA_RING_FULL_ERR(_ring)) { \ + (_ring).head = ((_ring).head + 1) % size; \ +@@ -179,7 +308,7 @@ + } + #define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ + { \ +- register __u32 size; \ ++ __u32 size; \ + size = (_ring).size; \ + if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \ + (_ring).head = ((_ring).head + (_count)) % size; \ +@@ -190,7 +319,7 @@ + } + #define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \ + { \ +- register __u32 size; \ ++ __u32 size; \ + size = (_ring).size; \ + if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \ + (_ring).head = ((_ring).head + 1) % size; \ +@@ -201,7 +330,7 @@ + } + #define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ + { \ +- register __u32 size; \ ++ __u32 size; \ + size = (_ring).size; \ + if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \ + (_ring).head = ((_ring).head + (_count)) % size; \ +@@ -330,4 +459,5 @@ + { + *val = le32toh(wqe_words[byte_index >> 2]); + } ++ + #endif /* IRDMA_DEFS_H */ +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/i40iw_hw.h nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/i40iw_hw.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/i40iw_hw.h 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/i40iw_hw.h 2024-07-03 16:16:11.193764889 -0700 +@@ -8,8 +8,8 @@ + I40IW_MAX_SGE_RD = 1, + I40IW_MAX_PUSH_PAGE_COUNT = 0, + I40IW_MAX_INLINE_DATA_SIZE = 48, +- I40IW_MAX_IRD_SIZE = 63, +- I40IW_MAX_ORD_SIZE = 127, ++ I40IW_MAX_IRD_SIZE = 64, ++ I40IW_MAX_ORD_SIZE = 64, + I40IW_MAX_WQ_ENTRIES = 2048, + I40IW_MAX_WQE_SIZE_RQ = 128, + I40IW_MAX_PDS = 32768, +@@ -17,7 +17,7 @@ + I40IW_MAX_CQ_SIZE = 1048575, + I40IW_MAX_OUTBOUND_MSG_SIZE = 2147483647, + I40IW_MAX_INBOUND_MSG_SIZE = 2147483647, +- I40IW_MIN_WQ_SIZE = 4 /* WQEs */, ++ I40IW_MIN_WQ_SIZE = 4 /* WQEs */, + }; + + #define I40IW_QP_WQE_MIN_SIZE 32 +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/ice_devids.h nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/ice_devids.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/ice_devids.h 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/ice_devids.h 2024-07-03 16:16:11.193764889 -0700 +@@ -1,11 +1,12 @@ + /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +-/* Copyright (c) 2019 - 2020 Intel Corporation */ ++/* Copyright (c) 2019 - 2024 Intel Corporation */ + #ifndef ICE_DEVIDS_H + #define ICE_DEVIDS_H + + #define PCI_VENDOR_ID_INTEL 0x8086 + + /* Device IDs */ ++#define IAVF_DEV_ID_ADAPTIVE_VF 0x1889 + /* Intel(R) Ethernet Connection E823-L for backplane */ + #define ICE_DEV_ID_E823L_BACKPLANE 0x124C + /* Intel(R) Ethernet Connection E823-L for SFP */ +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/idpf_devids.h nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/idpf_devids.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/idpf_devids.h 1969-12-31 16:00:00.000000000 -0800 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/idpf_devids.h 2024-07-03 16:16:11.193764889 -0700 +@@ -0,0 +1,20 @@ ++/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* Copyright (C) 2023 Intel Corporation */ ++ ++#ifndef _IDPF_DEVIDS_H_ ++#define _IDPF_DEVIDS_H_ ++ ++/* Device IDs common to emr, silicon and simics */ ++#define IDPF_DEV_ID_PF 0x1452 ++#define IAVF_DEV_ID_VF 0x145C ++#ifdef SIOV_SUPPORT ++#define IAVF_DEV_ID_VF_SIOV 0x0DD5 ++#endif /* SIOV_SUPPORT */ ++ ++#define IAVF_DEV_ID_ADAPTIVE_VF 0x1889 ++ ++#define IDPF_DEV_ID_PF_SIMICS 0xF002 ++#define IAVF_DEV_ID_VF_SIMICS 0xF00C ++ ++#endif /* _IDPF_DEVIDS_H_ */ +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/irdma.h nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/irdma.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/irdma.h 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/irdma.h 2024-07-03 16:16:11.193764889 -0700 +@@ -1,14 +1,21 @@ + /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +-/* Copyright (c) 2017 - 2023 Intel Corporation */ ++/* Copyright (c) 2017 - 2022 Intel Corporation */ + #ifndef IRDMA_H + #define IRDMA_H + ++#define RDMA_BIT2(type, a) ((u##type) 1UL << a) ++#define RDMA_MASK3(type, mask, shift) ((u##type) mask << shift) ++#define MAKEMASK(m, s) ((m) << (s)) ++ ++#define IRDMA_WQEALLOC_WQE_DESC_INDEX_S 20 + #define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20) + + enum irdma_vers { +- IRDMA_GEN_RSVD, +- IRDMA_GEN_1, +- IRDMA_GEN_2, ++ IRDMA_GEN_RSVD = 0, ++ IRDMA_GEN_1 = 1, ++ IRDMA_GEN_2 = 2, ++ IRDMA_GEN_3 = 3, ++ IRDMA_GEN_4 = 4, + }; + + struct irdma_uk_attrs { +@@ -20,6 +27,8 @@ + __u32 max_hw_wq_quanta; + __u32 min_hw_cq_size; + __u32 max_hw_cq_size; ++ __u32 max_hw_srq_quanta; ++ __u16 max_hw_push_len; + __u16 max_hw_sq_chunk; + __u16 min_hw_wq_size; + __u8 hw_rev; +@@ -30,6 +39,7 @@ + __u64 max_hw_outbound_msg_size; + __u64 max_hw_inbound_msg_size; + __u64 max_mr_size; ++ __u64 page_size_cap; + __u32 min_hw_qp_id; + __u32 min_hw_aeq_size; + __u32 max_hw_aeq_size; +@@ -49,6 +59,7 @@ + __u32 max_sleep_count; + __u32 max_cqp_compl_wait_time_ms; + __u16 max_stat_inst; ++ __u16 max_stat_idx; + }; + + #endif /* IRDMA_H*/ +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/osdep.h nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/osdep.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/osdep.h 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/osdep.h 2024-07-03 16:16:11.193764889 -0700 +@@ -1,5 +1,5 @@ + /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +-/* Copyright (c) 2015 - 2021 Intel Corporation */ ++/* Copyright (c) 2015 - 2022 Intel Corporation */ + #ifndef IRDMA_OSDEP_H + #define IRDMA_OSDEP_H + +@@ -8,15 +8,56 @@ + #include + #include + #include ++#include + #include + #include +-#include + #include + #include + #include + #include ++#include ++#include + #include ++extern unsigned int irdma_dbg; ++#define libirdma_debug(fmt, args...) \ ++do { \ ++ if (irdma_dbg) \ ++ fprintf(stderr, "libirdma-%s: " fmt, __func__, ##args); \ ++} while (0) ++#ifndef BIT ++#define BIT(nr) (1UL << (nr)) ++#endif ++#ifndef BITS_PER_LONG ++#define BITS_PER_LONG (8 * sizeof(long)) ++#endif ++#ifndef GENMASK ++#define GENMASK(h, l) \ ++ (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) ++#endif ++#ifndef BIT_ULL ++#define BIT_ULL(nr) (1ULL << (nr)) ++#endif ++#ifndef BITS_PER_LONG_LONG ++#define BITS_PER_LONG_LONG (8 * sizeof(long long)) ++#endif ++#ifndef GENMASK_ULL ++#define GENMASK_ULL(h, l) \ ++ (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) ++#endif ++#ifndef FIELD_PREP ++ ++/* Compat for rdma-core-27.0 and OFED 4.8/RHEL 7.2. Not for UPSTREAM */ ++#define __bf_shf(x) (__builtin_ffsll(x) - 1) ++#define FIELD_PREP(_mask, _val) \ ++ ({ \ ++ ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ ++ }) + ++#define FIELD_GET(_mask, _reg) \ ++ ({ \ ++ (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ ++ }) ++#endif /* FIELD_PREP */ + static inline void db_wr32(__u32 val, __u32 *wqe_word) + { + *wqe_word = val; +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/uk.c nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/uk.c +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/uk.c 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/uk.c 2024-07-03 16:16:11.193764889 -0700 +@@ -1,7 +1,5 @@ + // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB + /* Copyright (c) 2015 - 2023 Intel Corporation */ +-#include +- + #include "osdep.h" + #include "defs.h" + #include "user.h" +@@ -54,15 +52,24 @@ + } + + /** ++ * irdma_nop_hdr - Format header section of noop WQE ++ * @qp: hw qp ptr ++ */ ++static inline __u64 irdma_nop_hdr(struct irdma_qp_uk *qp) ++{ ++ return FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | ++ FIELD_PREP(IRDMAQPSQ_SIGCOMPL, false) | ++ FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); ++} ++ ++/** + * irdma_nop_1 - insert a NOP wqe + * @qp: hw qp ptr + */ + static int irdma_nop_1(struct irdma_qp_uk *qp) + { +- __u64 hdr; + __le64 *wqe; + __u32 wqe_idx; +- bool signaled = false; + + if (!qp->sq_ring.head) + return EINVAL; +@@ -76,14 +83,10 @@ + set_64bit_val(wqe, 8, 0); + set_64bit_val(wqe, 16, 0); + +- hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | +- FIELD_PREP(IRDMAQPSQ_SIGCOMPL, signaled) | +- FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); +- + /* make sure WQE is written before valid bit is set */ + udma_to_device_barrier(); + +- set_64bit_val(wqe, 24, hdr); ++ set_64bit_val(wqe, 24, irdma_nop_hdr(qp)); + + return 0; + } +@@ -95,16 +98,18 @@ + */ + void irdma_clr_wqes(struct irdma_qp_uk *qp, __u32 qp_wqe_idx) + { +- __le64 *wqe; ++ struct irdma_qp_quanta *sq; + __u32 wqe_idx; + + if (!(qp_wqe_idx & 0x7F)) { + wqe_idx = (qp_wqe_idx + 128) % qp->sq_ring.size; +- wqe = qp->sq_base[wqe_idx].elem; ++ sq = qp->sq_base + wqe_idx; + if (wqe_idx) +- memset(wqe, qp->swqe_polarity ? 0 : 0xFF, 0x1000); ++ memset(sq, qp->swqe_polarity ? 0 : 0xFF, ++ 128 * sizeof(*sq)); + else +- memset(wqe, qp->swqe_polarity ? 0xFF : 0, 0x1000); ++ memset(sq, qp->swqe_polarity ? 0xFF : 0, ++ 128 * sizeof(*sq)); + } + } + +@@ -114,10 +119,35 @@ + */ + void irdma_uk_qp_post_wr(struct irdma_qp_uk *qp) + { +- /* valid bit is written before ringing doorbell */ +- udma_to_device_barrier(); ++ __u64 temp; ++ __u32 hw_sq_tail; ++ __u32 sw_sq_head; ++ ++ /* valid bit is written and loads completed before reading shadow */ ++ atomic_thread_fence(memory_order_seq_cst); ++ ++ /* read the doorbell shadow area */ ++ get_64bit_val(qp->shadow_area, 0, &temp); ++ ++ hw_sq_tail = (__u32)FIELD_GET(IRDMA_QP_DBSA_HW_SQ_TAIL, temp); ++ sw_sq_head = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); ++ if (sw_sq_head != qp->initial_ring.head) { ++ if (qp->push_dropped) { ++ db_wr32(qp->qp_id, qp->wqe_alloc_db); ++ qp->push_dropped = false; ++ } else if (sw_sq_head != hw_sq_tail) { ++ if (sw_sq_head > qp->initial_ring.head) { ++ if (hw_sq_tail >= qp->initial_ring.head && ++ hw_sq_tail < sw_sq_head) ++ db_wr32(qp->qp_id, qp->wqe_alloc_db); ++ } else { ++ if (hw_sq_tail >= qp->initial_ring.head || ++ hw_sq_tail < sw_sq_head) ++ db_wr32(qp->qp_id, qp->wqe_alloc_db); ++ } ++ } ++ } + +- db_wr32(qp->qp_id, qp->wqe_alloc_db); + qp->initial_ring.head = qp->sq_ring.head; + } + +@@ -143,12 +173,11 @@ + if (IRDMA_RING_CURRENT_HEAD(qp->initial_ring) != + IRDMA_RING_CURRENT_TAIL(qp->sq_ring) && + !qp->push_mode) { +- if (post_sq) +- irdma_uk_qp_post_wr(qp); ++ irdma_uk_qp_post_wr(qp); + } else { + push = (__le64 *)((uintptr_t)qp->push_wqe + + (wqe_idx & 0x7) * 0x20); +- memcpy(push, wqe, quanta * IRDMA_QP_WQE_MIN_SIZE); ++ mmio_memcpy_x64(push, wqe, quanta * IRDMA_QP_WQE_MIN_SIZE); + irdma_qp_ring_push_db(qp, wqe_idx); + } + } +@@ -157,30 +186,42 @@ + * irdma_qp_get_next_send_wqe - pad with NOP if needed, return where next WR should go + * @qp: hw qp ptr + * @wqe_idx: return wqe index +- * @quanta: size of WR in quanta ++ * @quanta: (in/out) ptr to size of WR in quanta. Modified in case pad is needed + * @total_size: size of WR in bytes + * @info: info on WR + */ + __le64 *irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, __u32 *wqe_idx, +- __u16 quanta, __u32 total_size, ++ __u16 *quanta, __u32 total_size, + struct irdma_post_sq_info *info) + { + __le64 *wqe; + __le64 *wqe_0 = NULL; + __u32 nop_wqe_idx; ++ __u16 wqe_quanta = *quanta; ++ bool push_wqe_pad = false; + __u16 avail_quanta; + __u16 i; ++ __u32 idx; + ++ if ((qp->uk_attrs->feature_flags & IRDMA_FEATURE_ENFORCE_SQ_SIZE) && ++ atomic_load(&qp->sq_ring.post_cnt) >= qp->sq_ring.user_size) ++ return NULL; ++ ++ if (info->push_wqe && (*quanta & 0x1)) { ++ *quanta = *quanta + 1; ++ push_wqe_pad = true; ++ } + avail_quanta = qp->uk_attrs->max_hw_sq_chunk - + (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) % + qp->uk_attrs->max_hw_sq_chunk); +- if (quanta <= avail_quanta) { ++ ++ if (*quanta <= avail_quanta) { + /* WR fits in current chunk */ +- if (quanta > IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring)) ++ if (*quanta > IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring)) + return NULL; + } else { + /* Need to pad with NOP */ +- if (quanta + avail_quanta > ++ if (*quanta + avail_quanta > + IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring)) + return NULL; + +@@ -198,17 +239,66 @@ + if (!*wqe_idx) + qp->swqe_polarity = !qp->swqe_polarity; + +- IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, quanta); ++ IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, *quanta); ++ ++ irdma_clr_wqes(qp, *wqe_idx); + + wqe = qp->sq_base[*wqe_idx].elem; +- if (qp->uk_attrs->hw_rev == IRDMA_GEN_1 && quanta == 1 && ++ if (qp->uk_attrs->hw_rev == IRDMA_GEN_1 && wqe_quanta == 1 && + (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) & 1)) { + wqe_0 = qp->sq_base[IRDMA_RING_CURRENT_HEAD(qp->sq_ring)].elem; +- wqe_0[3] = htole64(FIELD_PREP(IRDMAQPSQ_VALID, !qp->swqe_polarity)); ++ wqe_0[3] = htole64(FIELD_PREP(IRDMAQPSQ_VALID, ++ qp->swqe_polarity ? 0 : 1)); + } + qp->sq_wrtrk_array[*wqe_idx].wrid = info->wr_id; + qp->sq_wrtrk_array[*wqe_idx].wr_len = total_size; +- qp->sq_wrtrk_array[*wqe_idx].quanta = quanta; ++ qp->sq_wrtrk_array[*wqe_idx].quanta = wqe_quanta; ++ if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_ENFORCE_SQ_SIZE) { ++ atomic_fetch_add(&qp->sq_ring.post_cnt, 1); ++ if (info->signaled) { ++ idx = IRDMA_RING_CURRENT_HEAD(qp->sq_sig_ring); ++ qp->sq_sigwrtrk_array[idx].wqe_idx = *wqe_idx; ++ qp->sq_sigwrtrk_array[idx].post_cnt = ++ 1 + qp->sq_ring.unsig_post_cnt; ++ qp->sq_ring.unsig_post_cnt = 0; ++ IRDMA_RING_MOVE_HEAD_NOCHECK(qp->sq_sig_ring); ++ } else { ++ qp->sq_ring.unsig_post_cnt++; ++ } ++ } ++ ++ /* Push mode to WC memory requires multiples of 64-byte block writes. */ ++ if (push_wqe_pad) { ++ __le64 *push_wqe; ++ ++ nop_wqe_idx = *wqe_idx + wqe_quanta; ++ push_wqe = qp->sq_base[nop_wqe_idx].elem; ++ qp->sq_wrtrk_array[nop_wqe_idx].quanta = IRDMA_QP_WQE_MIN_QUANTA; ++ ++ set_64bit_val(push_wqe, 0, 0); ++ set_64bit_val(push_wqe, 8, 0); ++ set_64bit_val(push_wqe, 16, 0); ++ set_64bit_val(push_wqe, 24, irdma_nop_hdr(qp)); ++ } ++ ++ return wqe; ++} ++ ++__le64 *irdma_srq_get_next_recv_wqe(struct irdma_srq_uk *srq, __u32 *wqe_idx) ++{ ++ int ret_code; ++ __le64 *wqe; ++ ++ if (IRDMA_RING_FULL_ERR(srq->srq_ring)) ++ return NULL; ++ ++ IRDMA_ATOMIC_RING_MOVE_HEAD(srq->srq_ring, *wqe_idx, ret_code); ++ if (ret_code) ++ return NULL; ++ ++ if (!*wqe_idx) ++ srq->srwqe_polarity = !srq->srwqe_polarity; ++ wqe = srq->srq_base[*wqe_idx * srq->wqe_size_multiplier].elem; + + return wqe; + } +@@ -277,13 +367,10 @@ + if (ret_code) + return ret_code; + +- wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size, +- info); ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return ENOMEM; + +- irdma_clr_wqes(qp, wqe_idx); +- + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.addr)); + +@@ -314,6 +401,12 @@ + ++addl_frag_cnt; + } + ++ if (!op_info->rem_addr.lkey && !total_size) ++ op_info->rem_addr.lkey = 0x1234; ++ if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_FORCE_FENCE) { ++ read_fence = 1; ++ info->local_fence = 1; ++ } + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.lkey) | + FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | + FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, info->imm_data_valid) | +@@ -328,17 +421,264 @@ + udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); +- if (info->push_wqe) { ++ if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); +- } else { +- if (post_sq) +- irdma_uk_qp_post_wr(qp); +- } ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); ++ ++ return 0; ++} ++ ++int irdma_uk_atomic_write(struct irdma_qp_uk *qp, ++ struct irdma_post_sq_info *info, bool post_sq) ++{ ++ struct irdma_atomic_write *op_info; ++ __u32 total_size = 0; ++ __u32 wqe_idx; ++ __u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; ++ __le64 *wqe; ++ __u64 hdr; ++ ++ info->push_wqe = qp->push_db ? true : false; ++ ++ op_info = &info->op.atomic_write; ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); ++ if (!wqe) ++ return ENOMEM; ++ ++ set_64bit_val(wqe, 0, op_info->tagged_offset); ++ if (op_info->is_inline_data) ++ set_64bit_val(wqe, 8, op_info->inline_data); ++ else { ++ set_64bit_val(wqe, 8, ++ FIELD_PREP(IRDMAQPSQ_LOCSTAG, op_info->stag) | ++ FIELD_PREP(IRDMAQPSQ_FRAG_LEN, IRDMAQP_ATOMIC_WRITE_FRAG_LEN) | ++ FIELD_PREP(IRDMAQPSQ_FRAG_VALID, qp->swqe_polarity)); ++ } ++ set_64bit_val(wqe, 16, op_info->remote_tagged_offset); ++ ++ hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->remote_stag) | ++ FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, op_info->is_inline_data) | ++ FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_ATOMIC_WRITE) | ++ FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | ++ FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | ++ FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | ++ FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | ++ FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); ++ ++ udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ ++ ++ set_64bit_val(wqe, 24, hdr); ++ if (info->push_wqe) ++ irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); ++ ++ return 0; ++} ++ ++int irdma_uk_flush_mem_region(struct irdma_qp_uk *qp, ++ struct irdma_post_sq_info *info, bool post_sq) ++{ ++ struct irdma_flush_mem_region *op_info; ++ __u32 total_size = 0; ++ __u32 wqe_idx; ++ __u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; ++ __le64 *wqe; ++ __u64 hdr; ++ ++ info->push_wqe = qp->push_db ? true : false; ++ ++ op_info = &info->op.flush_mem_region; ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); ++ if (!wqe) ++ return ENOMEM; ++ ++ set_64bit_val(wqe, 8, ++ FIELD_PREP(IRDMAQPSQ_FLUSH_MEM_LEN, op_info->length)); ++ set_64bit_val(wqe, 16, op_info->remote_tagged_offset); ++ ++ hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->remote_stag) | ++ FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FLUSH_MEM_REGION) | ++ FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | ++ FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | ++ FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | ++ FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | ++ FIELD_PREP(IRDMAQPSQ_PLACEMENT_TYPE, op_info->placement_type) | ++ FIELD_PREP(IRDMAQPSQ_SELECTIVITY, op_info->selectivity) | ++ FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); ++ ++ udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ ++ ++ set_64bit_val(wqe, 24, hdr); ++ if (info->push_wqe) ++ irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); + + return 0; + } + + /** ++ * irdma_uk_atomic_fetch_add - atomic fetch and add operation ++ * @qp: hw qp ptr ++ * @info: post sq information ++ * @post_sq: flag to post sq ++ */ ++int irdma_uk_atomic_fetch_add(struct irdma_qp_uk *qp, ++ struct irdma_post_sq_info *info, bool post_sq) ++{ ++ struct irdma_atomic_fetch_add *op_info; ++ __u32 total_size = 0; ++ __u16 quanta = 2; ++ __u32 wqe_idx; ++ __le64 *wqe; ++ __u64 hdr; ++ ++ info->push_wqe = qp->push_db ? true : false; ++ ++ op_info = &info->op.atomic_fetch_add; ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); ++ if (!wqe) ++ return ENOMEM; ++ ++ set_64bit_val(wqe, 0, op_info->tagged_offset); ++ set_64bit_val(wqe, 8, ++ FIELD_PREP(IRDMAQPSQ_LOCSTAG, op_info->stag)); ++ set_64bit_val(wqe, 16, op_info->remote_tagged_offset); ++ ++ hdr = FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, 1) | ++ FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->remote_stag) | ++ FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_ATOMIC_FETCH_ADD) | ++ FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | ++ FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | ++ FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | ++ FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | ++ FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); ++ ++ set_64bit_val(wqe, 32, op_info->fetch_add_data_bytes); ++ set_64bit_val(wqe, 40, 0); ++ set_64bit_val(wqe, 48, 0); ++ set_64bit_val(wqe, 56, ++ FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity)); ++ ++ udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ ++ ++ set_64bit_val(wqe, 24, hdr); ++ if (info->push_wqe) ++ irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); ++ ++ return 0; ++} ++ ++/** ++ * irdma_uk_atomic_compare_swap - atomic compare and swap operation ++ * @qp: hw qp ptr ++ * @info: post sq information ++ * @post_sq: flag to post sq ++ */ ++int irdma_uk_atomic_compare_swap(struct irdma_qp_uk *qp, ++ struct irdma_post_sq_info *info, bool post_sq) ++{ ++ struct irdma_atomic_compare_swap *op_info; ++ __u32 total_size = 0; ++ __u16 quanta = 2; ++ __u32 wqe_idx; ++ __le64 *wqe; ++ __u64 hdr; ++ ++ info->push_wqe = qp->push_db ? true : false; ++ ++ op_info = &info->op.atomic_compare_swap; ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); ++ if (!wqe) ++ return ENOMEM; ++ ++ set_64bit_val(wqe, 0, op_info->tagged_offset); ++ set_64bit_val(wqe, 8, ++ FIELD_PREP(IRDMAQPSQ_LOCSTAG, op_info->stag)); ++ set_64bit_val(wqe, 16, op_info->remote_tagged_offset); ++ ++ hdr = FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, 1) | ++ FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->remote_stag) | ++ FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_ATOMIC_COMPARE_SWAP_ADD) | ++ FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | ++ FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | ++ FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | ++ FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | ++ FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); ++ ++ set_64bit_val(wqe, 32, op_info->swap_data_bytes); ++ set_64bit_val(wqe, 40, op_info->compare_data_bytes); ++ set_64bit_val(wqe, 48, 0); ++ set_64bit_val(wqe, 56, ++ FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity)); ++ ++ udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ ++ ++ set_64bit_val(wqe, 24, hdr); ++ if (info->push_wqe) ++ irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); ++ ++ return 0; ++} ++ ++/** ++ * irdma_uk_srq_post_receive - post a receive wqe to a shared rq ++ * @srq: shared rq ptr ++ * @info: post rq information ++ */ ++int irdma_uk_srq_post_receive(struct irdma_srq_uk *srq, ++ struct irdma_post_rq_info *info) ++{ ++ __u32 wqe_idx, i, byte_off; ++ __u32 addl_frag_cnt; ++ __le64 *wqe; ++ __u64 hdr; ++ ++ if (srq->max_srq_frag_cnt < info->num_sges) ++ return EINVAL; ++ ++ wqe = irdma_srq_get_next_recv_wqe(srq, &wqe_idx); ++ if (!wqe) ++ return ENOMEM; ++ ++ addl_frag_cnt = info->num_sges > 1 ? info->num_sges - 1 : 0; ++ srq->wqe_ops.iw_set_fragment(wqe, 0, info->sg_list, ++ srq->srwqe_polarity); ++ ++ for (i = 1, byte_off = 32; i < info->num_sges; i++) { ++ srq->wqe_ops.iw_set_fragment(wqe, byte_off, &info->sg_list[i], ++ srq->srwqe_polarity); ++ byte_off += 16; ++ } ++ ++ /* if not an odd number set valid bit in next fragment */ ++ if (srq->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(info->num_sges & 0x01) && ++ info->num_sges) { ++ srq->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, ++ srq->srwqe_polarity); ++ if (srq->uk_attrs->hw_rev == IRDMA_GEN_2) ++ ++addl_frag_cnt; ++ } ++ ++ set_64bit_val(wqe, 16, (__u64)info->wr_id); ++ hdr = FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | ++ FIELD_PREP(IRDMAQPSQ_VALID, srq->srwqe_polarity); ++ ++ udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ ++ ++ set_64bit_val(wqe, 24, hdr); ++ ++ set_64bit_val(srq->shadow_area, 0, (wqe_idx + 1) % srq->srq_ring.size); ++ ++ return 0; ++} ++/** + * irdma_uk_rdma_read - rdma read command + * @qp: hw qp ptr + * @info: post sq information +@@ -352,6 +692,7 @@ + int ret_code; + __u32 i, byte_off, total_size = 0; + bool local_fence = false; ++ bool ord_fence = false; + __u32 addl_frag_cnt; + __le64 *wqe; + __u32 wqe_idx; +@@ -371,12 +712,14 @@ + if (ret_code) + return ret_code; + +- wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size, +- info); ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return ENOMEM; + +- irdma_clr_wqes(qp, wqe_idx); ++ if (qp->rd_fence_rate && (qp->ord_cnt++ == qp->rd_fence_rate)) { ++ ord_fence = true; ++ qp->ord_cnt = 0; ++ } + + addl_frag_cnt = op_info->num_lo_sges > 1 ? + (op_info->num_lo_sges - 1) : 0; +@@ -401,13 +744,18 @@ + } + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.addr)); ++ if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_FORCE_FENCE) { ++ info->read_fence = 1; ++ local_fence = 1; ++ } + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.lkey) | + FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | + FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | + FIELD_PREP(IRDMAQPSQ_OPCODE, + (inv_stag ? IRDMAQP_OP_RDMA_READ_LOC_INV : IRDMAQP_OP_RDMA_READ)) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | +- FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | ++ FIELD_PREP(IRDMAQPSQ_READFENCE, ++ info->read_fence || ord_fence ? 1 : 0) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); +@@ -415,12 +763,10 @@ + udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); +- if (info->push_wqe) { ++ if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); +- } else { +- if (post_sq) +- irdma_uk_qp_post_wr(qp); +- } ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); + + return 0; + } +@@ -460,13 +806,10 @@ + if (ret_code) + return ret_code; + +- wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size, +- info); ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return ENOMEM; + +- irdma_clr_wqes(qp, wqe_idx); +- + read_fence |= info->read_fence; + addl_frag_cnt = frag_cnt > 1 ? (frag_cnt - 1) : 0; + if (info->imm_data_valid) { +@@ -498,6 +841,10 @@ + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_DESTQKEY, op_info->qkey) | + FIELD_PREP(IRDMAQPSQ_DESTQPN, op_info->dest_qp)); ++ if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_FORCE_FENCE) { ++ read_fence = 1; ++ info->local_fence = 1; ++ } + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, info->stag_to_inv) | + FIELD_PREP(IRDMAQPSQ_AHID, op_info->ah_id) | + FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, +@@ -516,12 +863,10 @@ + udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); +- if (info->push_wqe) { ++ if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); +- } else { +- if (post_sq) +- irdma_uk_qp_post_wr(qp); +- } ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); + + return 0; + } +@@ -569,7 +914,7 @@ + sge_len -= bytes_copied; + + if (!quanta_bytes_remaining) { +- /* Remaining inline bytes reside after the hdr */ ++ /* Remaining inline bytes reside after hdr */ + wqe += 16; + quanta_bytes_remaining = 32; + } +@@ -637,7 +982,7 @@ + if (!quanta_bytes_remaining) { + quanta_bytes_remaining = 31; + +- /* Remaining inline bytes reside after the hdr */ ++ /* Remaining inline bytes reside after hdr */ + if (first_quanta) { + first_quanta = false; + wqe += 16; +@@ -692,8 +1037,8 @@ + __u64 hdr = 0; + __u32 wqe_idx; + bool read_fence = false; +- __u32 i, total_size = 0; + __u16 quanta; ++ __u32 i, total_size = 0; + + info->push_wqe = qp->push_db ? true : false; + op_info = &info->op.rdma_write; +@@ -708,17 +1053,18 @@ + return EINVAL; + + quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(total_size); +- wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size, +- info); ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return ENOMEM; + +- irdma_clr_wqes(qp, wqe_idx); +- + read_fence |= info->read_fence; + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.addr)); + ++ if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_FORCE_FENCE) { ++ read_fence = 1; ++ info->local_fence = 1; ++ } + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.lkey) | + FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | + FIELD_PREP(IRDMAQPSQ_INLINEDATALEN, total_size) | +@@ -737,16 +1083,15 @@ + + qp->wqe_ops.iw_copy_inline_data((__u8 *)wqe, op_info->lo_sg_list, + op_info->num_lo_sges, qp->swqe_polarity); ++ + udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + +- if (info->push_wqe) { ++ if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); +- } else { +- if (post_sq) +- irdma_uk_qp_post_wr(qp); +- } ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); + + return 0; + } +@@ -765,8 +1110,8 @@ + __u64 hdr; + __u32 wqe_idx; + bool read_fence = false; +- __u32 i, total_size = 0; + __u16 quanta; ++ __u32 i, total_size = 0; + + info->push_wqe = qp->push_db ? true : false; + op_info = &info->op.send; +@@ -781,18 +1126,19 @@ + return EINVAL; + + quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(total_size); +- wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, quanta, total_size, +- info); ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return ENOMEM; + +- irdma_clr_wqes(qp, wqe_idx); +- + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_DESTQKEY, op_info->qkey) | + FIELD_PREP(IRDMAQPSQ_DESTQPN, op_info->dest_qp)); + + read_fence |= info->read_fence; ++ if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_FORCE_FENCE) { ++ read_fence = 1; ++ info->local_fence = 1; ++ } + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, info->stag_to_inv) | + FIELD_PREP(IRDMAQPSQ_AHID, op_info->ah_id) | + FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | +@@ -819,12 +1165,10 @@ + + set_64bit_val(wqe, 24, hdr); + +- if (info->push_wqe) { ++ if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); +- } else { +- if (post_sq) +- irdma_uk_qp_post_wr(qp); +- } ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); + + return 0; + } +@@ -845,23 +1189,25 @@ + __u32 wqe_idx; + bool local_fence = false; + struct ibv_sge sge = {}; ++ __u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; + + info->push_wqe = qp->push_db ? true : false; + op_info = &info->op.inv_local_stag; + local_fence = info->local_fence; + +- wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, IRDMA_QP_WQE_MIN_QUANTA, +- 0, info); ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, 0, info); + if (!wqe) + return ENOMEM; + +- irdma_clr_wqes(qp, wqe_idx); +- + sge.lkey = op_info->target_stag; + qp->wqe_ops.iw_set_fragment(wqe, 0, &sge, 0); + + set_64bit_val(wqe, 16, 0); + ++ if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_FORCE_FENCE) { ++ info->read_fence = 1; ++ local_fence = 1; ++ } + hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMA_OP_TYPE_INV_STAG) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | +@@ -873,13 +1219,10 @@ + + set_64bit_val(wqe, 24, hdr); + +- if (info->push_wqe) { +- irdma_qp_push_wqe(qp, wqe, IRDMA_QP_WQE_MIN_QUANTA, wqe_idx, +- post_sq); +- } else { +- if (post_sq) +- irdma_uk_qp_post_wr(qp); +- } ++ if (info->push_wqe) ++ irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); + + return 0; + } +@@ -897,19 +1240,17 @@ + struct irdma_bind_window *op_info; + __u64 hdr; + __u32 wqe_idx; +- bool local_fence = false; ++ bool local_fence; ++ __u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; + + info->push_wqe = qp->push_db ? true : false; + op_info = &info->op.bind_window; +- local_fence |= info->local_fence; ++ local_fence = info->local_fence; + +- wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, IRDMA_QP_WQE_MIN_QUANTA, +- 0, info); ++ wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, 0, info); + if (!wqe) + return ENOMEM; + +- irdma_clr_wqes(qp, wqe_idx); +- + qp->wqe_ops.iw_set_mw_bind_wqe(wqe, op_info); + + hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMA_OP_TYPE_BIND_MW) | +@@ -923,19 +1264,17 @@ + FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | ++ FIELD_PREP(IRDMAQPSQ_REMOTE_ATOMICS_EN, op_info->remote_atomics_en) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + +- if (info->push_wqe) { +- irdma_qp_push_wqe(qp, wqe, IRDMA_QP_WQE_MIN_QUANTA, wqe_idx, +- post_sq); +- } else { +- if (post_sq) +- irdma_uk_qp_post_wr(qp); +- } ++ if (info->push_wqe) ++ irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); ++ else if (post_sq) ++ irdma_uk_qp_post_wr(qp); + + return 0; + } +@@ -1069,6 +1408,120 @@ + db_wr32(cq->cq_id, cq->cqe_alloc_db); + } + ++static void irdma_copy_quanta(__le64 *dst, __le64 *src, __u32 offset, bool flip, ++ bool barrier) ++{ ++ __le64 val; ++ ++ get_64bit_val(src, offset, &val); ++ set_64bit_val(dst, offset, val); ++ ++ get_64bit_val(src, offset + 8, &val); ++ if (flip) ++ val ^= IRDMAQPSQ_VALID; ++ set_64bit_val(dst, offset + 8, val); ++ ++ get_64bit_val(src, offset + 24, &val); ++ if (flip) ++ val ^= IRDMAQPSQ_VALID; ++ if (barrier) ++ udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ ++ set_64bit_val(dst, offset + 24, val); ++} ++ ++static void irdma_copy_wqe(__le64 *dst, __le64 *src, __u8 wqe_quanta, ++ bool flip_polarity) ++{ ++ __u32 offset; ++ ++ offset = 32; ++ while (--wqe_quanta) { ++ irdma_copy_quanta(dst, src, offset, flip_polarity, false); ++ offset += 32; ++ } ++ ++ irdma_copy_quanta(dst, src, 0, flip_polarity, true); ++} ++ ++static void irdma_repost_rq_wqes(struct irdma_qp_uk *qp, __u32 start_idx, ++ __u32 end_idx) ++{ ++ __le64 *dst_wqe, *src_wqe; ++ /* This wqe_idx initialization is just to silence compiler warning. ++ * Theoreticaly, the call to irdma_qp_get_next_recv_wqe() below ++ * may fail if rq ring is full. In such case, the uninitialized ++ * wqe_idx would be used as an index to rq_wrid_array[]. ++ * However, because rq ring tail is advanced first, the ring ++ * is never full and irdma_qp_get_next_recv_wqe() always returns ++ * valid dst_wqe pointer and wqe_idx. ++ */ ++ __u32 wqe_idx = 0; ++ __u8 wqe_quanta = qp->rq_wqe_size_multiplier; ++ bool flip_polarity; ++ __u64 val; ++ ++ libirdma_debug("reposting_wqes: from start_idx=%d to end_idx = %d\n", start_idx, end_idx); ++ if (pthread_spin_lock(qp->lock)) ++ return; ++ while (start_idx != end_idx) { ++ IRDMA_RING_SET_TAIL(qp->rq_ring, start_idx + 1); ++ src_wqe = qp->rq_base[start_idx * qp->rq_wqe_size_multiplier].elem; ++ dst_wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx); ++ ++ /* Check to see if polarity has changed */ ++ get_64bit_val(src_wqe, 24, &val); ++ if (FIELD_GET(IRDMAQPSQ_VALID, val) != qp->rwqe_polarity) ++ flip_polarity = true; ++ else ++ flip_polarity = false; ++ ++ qp->rq_wrid_array[wqe_idx] = qp->rq_wrid_array[start_idx]; ++ irdma_copy_wqe(dst_wqe, src_wqe, wqe_quanta, flip_polarity); ++ ++ start_idx = (start_idx + 1) % qp->rq_size; ++ } ++ ++ pthread_spin_unlock(qp->lock); ++} ++ ++static int irdma_check_rq_cqe(struct irdma_qp_uk *qp, __u32 *array_idx) ++{ ++ __u32 exp_idx = (qp->last_rx_cmpl_idx + 1) % qp->rq_size; ++ ++ if (*array_idx != exp_idx) { ++ libirdma_debug("qp_id = %d Error completing RQ request at index = %d.\n", ++ qp->qp_id, exp_idx); ++ if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_RELAX_RQ_ORDER) { ++ irdma_repost_rq_wqes(qp, exp_idx, *array_idx); ++ qp->last_rx_cmpl_idx = *array_idx; ++ ++ return 0; ++ } ++ ++ *array_idx = exp_idx; ++ qp->last_rx_cmpl_idx = exp_idx; ++ ++ return -1; ++ } ++ ++ qp->last_rx_cmpl_idx = *array_idx; ++ ++ return 0; ++} ++ ++static int irdma_check_sq_cqe(struct irdma_qp_uk *qp, __u32 *wqe_idx) ++{ ++ __u32 tail = IRDMA_RING_CURRENT_TAIL(qp->sq_sig_ring); ++ ++ if (qp->uk_attrs->feature_flags & IRDMA_FEATURE_ENFORCE_SQ_SIZE) { ++ atomic_fetch_sub(&qp->sq_ring.post_cnt, qp->sq_sigwrtrk_array[tail].post_cnt); ++ qp->sq_sigwrtrk_array[tail].post_cnt = 0; ++ } ++ IRDMA_RING_MOVE_TAIL(qp->sq_sig_ring); ++ ++ return 0; ++} ++ + /** + * irdma_uk_cq_poll_cmpl - get cq completion info + * @cq: hw cq +@@ -1080,6 +1533,9 @@ + __u64 comp_ctx, qword0, qword2, qword3; + __le64 *cqe; + struct irdma_qp_uk *qp; ++ struct irdma_srq_uk *srq; ++ struct qp_err_code qp_err; ++ __u8 is_srq; + struct irdma_ring *pring = NULL; + __u32 wqe_idx; + int ret_code; +@@ -1153,22 +1609,39 @@ + } + + info->q_type = (__u8)FIELD_GET(IRDMA_CQ_SQ, qword3); ++ is_srq = (__u8)FIELD_GET(IRDMA_CQ_SRQ, qword3); + info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); + info->push_dropped = (bool)FIELD_GET(IRDMACQ_PSHDROP, qword3); + info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); ++ get_64bit_val(cqe, 8, &comp_ctx); ++ if (is_srq) ++ get_64bit_val(cqe, 40, (__u64 *)&qp); ++ else ++ qp = (struct irdma_qp_uk *)(uintptr_t)comp_ctx; ++ if (!qp || qp->destroy_pending) { ++ ret_code = EFAULT; ++ goto exit; ++ } + if (info->error) { + info->major_err = FIELD_GET(IRDMA_CQ_MAJERR, qword3); + info->minor_err = FIELD_GET(IRDMA_CQ_MINERR, qword3); +- if (info->major_err == IRDMA_FLUSH_MAJOR_ERR) { +- info->comp_status = IRDMA_COMPL_STATUS_FLUSHED; ++ switch (info->major_err) { ++ case IRDMA_SRQFLUSH_RSVD_MAJOR_ERR: ++ qp_err = irdma_ae_to_qp_err_code(info->minor_err); ++ info->minor_err = qp_err.flush_code; ++ SWITCH_FALLTHROUGH; ++ case IRDMA_FLUSH_MAJOR_ERR: + /* Set the min error to standard flush error code for remaining cqes */ + if (info->minor_err != FLUSH_GENERAL_ERR) { + qword3 &= ~IRDMA_CQ_MINERR; + qword3 |= FIELD_PREP(IRDMA_CQ_MINERR, FLUSH_GENERAL_ERR); + set_64bit_val(cqe, 24, qword3); + } +- } else { ++ info->comp_status = IRDMA_COMPL_STATUS_FLUSHED; ++ break; ++ default: + info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; ++ break; + } + } else { + info->comp_status = IRDMA_COMPL_STATUS_SUCCESS; +@@ -1177,23 +1650,30 @@ + get_64bit_val(cqe, 0, &qword0); + get_64bit_val(cqe, 16, &qword2); + +- info->tcp_seq_num_rtt = (__u32)FIELD_GET(IRDMACQ_TCPSEQNUMRTT, qword0); ++ info->stat.raw = (__u32)FIELD_GET(IRDMACQ_TCPSQN_ROCEPSN_RTT_TS, qword0); + info->qp_id = (__u32)FIELD_GET(IRDMACQ_QPID, qword2); + info->ud_src_qpn = (__u32)FIELD_GET(IRDMACQ_UDSRCQPN, qword2); + +- get_64bit_val(cqe, 8, &comp_ctx); +- + info->solicited_event = (bool)FIELD_GET(IRDMACQ_SOEVENT, qword3); +- qp = (struct irdma_qp_uk *)(uintptr_t)comp_ctx; +- if (!qp || qp->destroy_pending) { +- ret_code = EFAULT; +- goto exit; +- } + wqe_idx = (__u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); + info->qp_handle = (irdma_qp_handle)(uintptr_t)qp; + info->op_type = (__u8)FIELD_GET(IRDMACQ_OP, qword3); + +- if (info->q_type == IRDMA_CQE_QTYPE_RQ) { ++ if (info->q_type == IRDMA_CQE_QTYPE_RQ && is_srq) { ++ srq = qp->srq_uk; ++ ++ get_64bit_val(cqe, 8, &info->wr_id); ++ info->bytes_xfered = (__u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); ++ ++ if (qword3 & IRDMACQ_STAG) { ++ info->stag_invalid_set = true; ++ info->inv_stag = (__u32)FIELD_GET(IRDMACQ_INVSTAG, qword2); ++ } else { ++ info->stag_invalid_set = false; ++ } ++ IRDMA_RING_MOVE_TAIL(srq->srq_ring); ++ pring = &srq->srq_ring; ++ } else if (info->q_type == IRDMA_CQE_QTYPE_RQ && !is_srq) { + __u32 array_idx; + + array_idx = wqe_idx / qp->rq_wqe_size_multiplier; +@@ -1209,14 +1689,16 @@ + array_idx = qp->rq_ring.tail; + } else { + info->wr_id = qp->rq_wrid_array[array_idx]; ++ if (irdma_check_rq_cqe(qp, &array_idx)) { ++ info->wr_id = qp->rq_wrid_array[array_idx]; ++ info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; ++ IRDMA_RING_SET_TAIL(qp->rq_ring, array_idx + 1); ++ return 0; ++ } + } + + info->bytes_xfered = (__u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); + +- if (info->imm_valid) +- info->op_type = IRDMA_OP_TYPE_REC_IMM; +- else +- info->op_type = IRDMA_OP_TYPE_REC; + if (qword3 & IRDMACQ_STAG) { + info->stag_invalid_set = true; + info->inv_stag = (__u32)FIELD_GET(IRDMACQ_INVSTAG, qword2); +@@ -1242,8 +1724,7 @@ + IRDMA_RING_MOVE_TAIL(cq->cq_ring); + set_64bit_val(cq->shadow_area, 0, + IRDMA_RING_CURRENT_HEAD(cq->cq_ring)); +- memset(info, 0, +- sizeof(struct irdma_cq_poll_info)); ++ memset(info, 0, sizeof(*info)); + return irdma_uk_cq_poll_cmpl(cq, info); + } + } +@@ -1256,11 +1737,24 @@ + info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid; + if (!info->comp_status) + info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len; ++ if (irdma_check_sq_cqe(qp, &wqe_idx)) { ++ info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid; ++ info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; ++ info->bytes_xfered = 0; ++ IRDMA_RING_SET_TAIL(qp->sq_ring, ++ wqe_idx + qp->sq_wrtrk_array[wqe_idx].quanta); ++ return 0; ++ } + info->op_type = (__u8)FIELD_GET(IRDMACQ_OP, qword3); + IRDMA_RING_SET_TAIL(qp->sq_ring, + wqe_idx + qp->sq_wrtrk_array[wqe_idx].quanta); + } else { ++ if (pthread_spin_lock(qp->lock)) { ++ ret_code = ENOENT; ++ goto exit; ++ } + if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) { ++ pthread_spin_unlock(qp->lock); + ret_code = ENOENT; + goto exit; + } +@@ -1274,7 +1768,8 @@ + sw_wqe = qp->sq_base[tail].elem; + get_64bit_val(sw_wqe, 24, + &wqe_qword); +- info->op_type = (__u8)FIELD_GET(IRDMAQPSQ_OPCODE, wqe_qword); ++ info->op_type = (__u8)FIELD_GET(IRDMAQPSQ_OPCODE, ++ wqe_qword); + IRDMA_RING_SET_TAIL(qp->sq_ring, + tail + qp->sq_wrtrk_array[tail].quanta); + if (info->op_type != IRDMAQP_OP_NOP) { +@@ -1283,9 +1778,14 @@ + break; + } + } while (1); ++ ++ if (info->op_type == IRDMA_OP_TYPE_BIND_MW && ++ info->minor_err == FLUSH_PROT_ERR) ++ info->minor_err = FLUSH_MW_BIND_ERR; + qp->sq_flush_seen = true; + if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) + qp->sq_flush_complete = true; ++ pthread_spin_unlock(qp->lock); + } + pring = &qp->sq_ring; + } +@@ -1293,11 +1793,16 @@ + ret_code = 0; + + exit: +- if (!ret_code && info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) ++ if (!ret_code && info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) { + if (pring && IRDMA_RING_MORE_WORK(*pring)) + move_cq_head = false; +- +- if (move_cq_head) { ++ } ++ /* Park CQ head during a flush to generate additional CQEs from SW ++ * for all unprocessed WQEs. ++ * For GEN3 and beyond FW will generate/flush these CQEs so move ++ * to the next CQE. ++ */ ++ if (move_cq_head || qp->uk_attrs->hw_rev >= IRDMA_GEN_3) { + IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); + if (!IRDMA_RING_CURRENT_HEAD(cq->cq_ring)) + cq->polarity ^= 1; +@@ -1322,11 +1827,222 @@ + return ret_code; + } + ++#ifdef PRINT_CQES ++/** ++ * irdma_print_cqes - print cq completion info ++ * @cq: hw cq ++ */ ++void irdma_print_cqes(struct irdma_cq_uk *cq) ++{ ++ __u8 cq_polarity = cq->polarity; ++ int i = 0; ++ ++ fprintf(stderr, "%s[%d]: CQ (cq_id=%u, polarity=%d, head=%u, size=%u)\n", ++ __func__, __LINE__, cq->cq_id, cq_polarity, ++ cq->cq_ring.head, cq->cq_ring.size); ++ ++ while (true) { ++ __u64 comp_ctx, qword0, qword2, qword3; ++ struct irdma_cq_poll_info cqe_info; ++ struct irdma_cq_poll_info *info = &cqe_info; ++ struct irdma_qp_uk *qp; ++ __le64 *ext_cqe = NULL; ++ bool ext_valid; ++ __u8 polarity; ++ __u32 wqe_idx; ++ __le64 *cqe; ++ ++ IRDMA_GET_CQ_ELEM_AT_OFFSET(cq, i, cqe); ++ get_64bit_val(cqe, 24, &qword3); ++ polarity = (__u8)FIELD_GET(IRDMA_CQ_VALID, qword3); ++ ++ if (polarity != cq_polarity) { ++ fprintf(stderr, "%s[%d]: CQ (cq_id=%u) is empty\n", ++ __func__, __LINE__, cq->cq_id); ++ return; ++ } ++ ++ /* Ensure CQE contents are read after valid bit is checked */ ++ udma_from_device_barrier(); ++ ++ ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); ++ if (ext_valid) { ++ __u64 qword7; ++ __u32 peek_head; ++ ++ if (cq->avoid_mem_cflct) { ++ ext_cqe = (__le64 *)((__u8 *)cqe + 32); ++ get_64bit_val(ext_cqe, 24, &qword7); ++ polarity = (__u8)FIELD_GET(IRDMA_CQ_VALID, qword7); ++ } else { ++ peek_head = IRDMA_GET_RING_OFFSET(cq->cq_ring, i + 1); ++ ext_cqe = cq->cq_base[peek_head].buf; ++ get_64bit_val(ext_cqe, 24, &qword7); ++ polarity = (__u8)FIELD_GET(IRDMA_CQ_VALID, qword7); ++ if (!peek_head) ++ polarity ^= 1; ++ } ++ if (polarity != cq_polarity) { ++ fprintf(stderr, "%s[%d]: Extended CQ (cq_id=%u) is empty\n", ++ __func__, __LINE__, cq->cq_id); ++ return; ++ } ++ ++ /* Ensure ext CQE contents are read after ext valid bit is checked */ ++ udma_from_device_barrier(); ++ ++ memset(info, 0, sizeof(*info)); ++ info->imm_valid = (bool)FIELD_GET(IRDMA_CQ_IMMVALID, qword7); ++ if (info->imm_valid) { ++ __u64 qword4; ++ ++ get_64bit_val(ext_cqe, 0, &qword4); ++ info->imm_data = (__u32)FIELD_GET(IRDMA_CQ_IMMDATALOW32, qword4); ++ } ++ } else { ++ info->imm_valid = false; ++ } ++ ++ info->q_type = (__u8)FIELD_GET(IRDMA_CQ_SQ, qword3); ++ info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); ++ info->push_dropped = (bool)FIELD_GET(IRDMACQ_PSHDROP, qword3); ++ info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); ++ if (info->error) { ++ info->major_err = FIELD_GET(IRDMA_CQ_MAJERR, qword3); ++ info->minor_err = FIELD_GET(IRDMA_CQ_MINERR, qword3); ++ if (info->major_err == IRDMA_FLUSH_MAJOR_ERR) ++ info->comp_status = IRDMA_COMPL_STATUS_FLUSHED; ++ else ++ info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; ++ } else { ++ info->comp_status = IRDMA_COMPL_STATUS_SUCCESS; ++ info->major_err = 0; ++ info->minor_err = 0; ++ } ++ ++ get_64bit_val(cqe, 0, &qword0); ++ get_64bit_val(cqe, 16, &qword2); ++ ++ info->qp_id = (__u32)FIELD_GET(IRDMACQ_QPID, qword2); ++ get_64bit_val(cqe, 8, &comp_ctx); ++ info->solicited_event = (bool)FIELD_GET(IRDMACQ_SOEVENT, qword3); ++ ++ fprintf(stderr, "%s[%d]: Found CQE (cq_id=%u major_err=%u minor_err=%u q_type=%u " ++ "push_dropped=%s ipv4=%s solicited_event=%s imm_data=%u qp_id=%u)\n", ++ __func__, __LINE__, cq->cq_id, info->major_err, info->minor_err, ++ info->q_type, info->push_dropped ? "true" : "false", ++ info->ipv4 ? "true" : "false", ++ info->solicited_event ? "true" : "false", ++ info->imm_valid ? info->imm_data : 0, info->qp_id); ++ ++ qp = (struct irdma_qp_uk *)(uintptr_t)comp_ctx; ++ if (!qp || qp->destroy_pending) { ++ fprintf(stderr, "%s[%d]: Found CQE for (cq_id=%u qp_id=%u): QP destroyed\n", ++ __func__, __LINE__, cq->cq_id, info->qp_id); ++ goto loop_end; ++ } ++ wqe_idx = (__u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); ++ info->qp_handle = (irdma_qp_handle)(uintptr_t)qp; ++ info->op_type = (__u8)FIELD_GET(IRDMACQ_OP, qword3); ++ ++ if (info->q_type == IRDMA_CQE_QTYPE_RQ) { ++ __u32 array_idx; ++ ++ array_idx = wqe_idx / qp->rq_wqe_size_multiplier; ++ info->wr_id = qp->rq_wrid_array[array_idx]; ++ ++ if (qword3 & IRDMACQ_STAG) { ++ info->stag_invalid_set = true; ++ info->inv_stag = (__u32)FIELD_GET(IRDMACQ_INVSTAG, qword2); ++ } else { ++ info->stag_invalid_set = false; ++ } ++ ++ fprintf(stderr, "%s[%d]: Found CQE for RQ qp_id=%u rq_ring (head=%u tail=%u size=%u) " ++ "wr_id=%llu wqe_idx=%u, stag_invalid_set=%s op_type=%u\n", ++ __func__, __LINE__, info->qp_id, qp->rq_ring.head, qp->rq_ring.tail, ++ qp->rq_ring.size, info->wr_id, wqe_idx, ++ info->stag_invalid_set ? "true" : "false", info->op_type); ++ ++ } else { /* q_type is IRDMA_CQE_QTYPE_SQ */ ++ ++ if (qp->first_sq_wq) { ++ fprintf(stderr, "%s[%d]: Found CQE for SQ first_sq_wq (qp_id=%u, wqe_idx=%u, conn_wqes=%d)\n", ++ __func__, __LINE__, info->qp_id, wqe_idx, qp->conn_wqes); ++ ++ if (wqe_idx < qp->conn_wqes && qp->sq_ring.head == qp->sq_ring.tail) ++ goto loop_end; ++ } ++ ++ info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid; ++ info->op_type = (__u8)FIELD_GET(IRDMACQ_OP, qword3); ++ ++ fprintf(stderr, "%s[%d]: Found CQE for SQ qp_id=%u, sq_ring (head=%u tail=%u size=%u) " ++ "wr_id=%llu wqe_idx=%u op_type=%u\n", ++ __func__, __LINE__, info->qp_id, qp->sq_ring.head, qp->sq_ring.tail, ++ qp->sq_ring.size, info->wr_id, wqe_idx, info->op_type); ++ } ++loop_end: ++ i++; ++ if (!IRDMA_GET_RING_OFFSET(cq->cq_ring, i)) ++ cq_polarity ^= 1; ++ ++ if (ext_valid && !cq->avoid_mem_cflct) { ++ i++; ++ if (!IRDMA_GET_RING_OFFSET(cq->cq_ring, i)) ++ cq_polarity ^= 1; ++ } ++ } ++} ++ ++/** ++ * irdma_print_sq_wqes - print sqp wqes ++ * @qp: hw qp ++ */ ++void irdma_print_sq_wqes(struct irdma_qp_uk *qp) ++{ ++ __u32 wqe_idx = IRDMA_RING_CURRENT_TAIL(qp->sq_ring); ++ __u8 sq_polarity = qp->swqe_polarity; ++ ++ fprintf(stderr, "%s[%d]: SQ (qp_id=%u sq_polarity=%d head=%u tail=%u size=%u)\n", ++ __func__, __LINE__, qp->qp_id, sq_polarity, ++ qp->sq_ring.head, qp->sq_ring.tail, qp->sq_ring.size); ++ ++ if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) { ++ fprintf(stderr, "%s[%d]: SQ is empty (qp_id=%u)\n", __func__, __LINE__, qp->qp_id); ++ return; ++ } ++ ++ while (true) { ++ __u8 wqe_polarity; ++ __le64 *wqe; ++ __u64 val; ++ ++ wqe = qp->sq_base[wqe_idx].elem; ++ get_64bit_val(wqe, 24, &val); ++ wqe_polarity = FIELD_GET(IRDMAQPSQ_VALID, val); ++ ++ if (wqe_polarity != sq_polarity) ++ break; ++ ++ fprintf(stderr, "%s[%d]: Found WQE in SQ qp_id=%u wr_id=%llu wqe_idx=%u " ++ "wr_len=%u quanta=%u hdr=0x%0llX\n", ++ __func__, __LINE__, qp->qp_id, qp->sq_wrtrk_array[wqe_idx].wrid, wqe_idx, ++ qp->sq_wrtrk_array[wqe_idx].wr_len, qp->sq_wrtrk_array[wqe_idx].quanta, val); ++ ++ wqe_idx += qp->sq_wrtrk_array[wqe_idx].quanta; ++ ++ if (!wqe_idx) ++ sq_polarity = !qp->swqe_polarity; ++ } ++} ++#endif /* defined(CONFIG_DEBUG_FS) || (!defined(__KERNEL__) && !defined(UPSTREAM_RELEASE)) */ ++ + /** +- * irdma_qp_round_up - return round up qp wq depth ++ * irdma_round_up_wq - return round up qp wq depth + * @wqdepth: wq depth in quanta to round up + */ +-static int irdma_qp_round_up(__u32 wqdepth) ++static int irdma_round_up_wq(__u32 wqdepth) + { + int scount = 1; + +@@ -1374,14 +2090,12 @@ + * @sq_size: SQ size + * @shift: shift which determines size of WQE + * @sqdepth: depth of SQ +- * + */ +-int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, +- __u32 sq_size, __u8 shift, __u32 *sqdepth) ++int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, __u32 sq_size, __u8 shift, __u32 *sqdepth) + { + __u32 min_size = (__u32)uk_attrs->min_hw_wq_size << shift; + +- *sqdepth = irdma_qp_round_up((sq_size << shift) + IRDMA_SQ_RSVD); ++ *sqdepth = irdma_round_up_wq((sq_size << shift) + IRDMA_SQ_RSVD); + + if (*sqdepth < min_size) + *sqdepth = min_size; +@@ -1394,16 +2108,15 @@ + /* + * irdma_get_rqdepth - get RQ depth (quanta) + * @uk_attrs: qp HW attributes +- * @rq_size: RQ size ++ * @rq_size: SRQ size + * @shift: shift which determines size of WQE +- * @rqdepth: depth of RQ ++ * @rqdepth: depth of RQ/SRQ + */ +-int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, +- __u32 rq_size, __u8 shift, __u32 *rqdepth) ++int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, __u32 rq_size, __u8 shift, __u32 *rqdepth) + { + __u32 min_size = (__u32)uk_attrs->min_hw_wq_size << shift; + +- *rqdepth = irdma_qp_round_up((rq_size << shift) + IRDMA_RQ_RSVD); ++ *rqdepth = irdma_round_up_wq((rq_size << shift) + IRDMA_RQ_RSVD); + + if (*rqdepth < min_size) + *rqdepth = min_size; +@@ -1413,6 +2126,25 @@ + return 0; + } + ++/* ++ * irdma_get_srqdepth - get SRQ depth (quanta) ++ * @uk_attrs: qp HW attributes ++ * @srq_size: SRQ size ++ * @shift: shift which determines size of WQE ++ * @srqdepth: depth of SRQ ++ */ ++int irdma_get_srqdepth(struct irdma_uk_attrs *uk_attrs, __u32 srq_size, __u8 shift, __u32 *srqdepth) ++{ ++ *srqdepth = irdma_round_up_wq((srq_size << shift) + IRDMA_RQ_RSVD); ++ ++ if (*srqdepth < ((__u32)uk_attrs->min_hw_wq_size << shift)) ++ *srqdepth = uk_attrs->min_hw_wq_size << shift; ++ else if (*srqdepth > uk_attrs->max_hw_srq_quanta) ++ return EINVAL; ++ ++ return 0; ++} ++ + static const struct irdma_wqe_uk_ops iw_wqe_uk_ops = { + .iw_copy_inline_data = irdma_copy_inline_data, + .iw_inline_data_size_to_quanta = irdma_inline_data_size_to_quanta, +@@ -1438,10 +2170,11 @@ + { + __u16 move_cnt = 1; + +- if (!info->legacy_mode && +- (qp->uk_attrs->feature_flags & IRDMA_FEATURE_RTS_AE)) ++ if (info->start_wqe_idx) ++ move_cnt = info->start_wqe_idx; ++ else if (!info->legacy_mode && ++ (qp->uk_attrs->feature_flags & IRDMA_FEATURE_RTS_AE)) + move_cnt = 3; +- + qp->conn_wqes = move_cnt; + IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, move_cnt); + IRDMA_RING_MOVE_TAIL_BY_COUNT(qp->sq_ring, move_cnt); +@@ -1449,6 +2182,42 @@ + } + + /** ++ * irdma_uk_srq_init - initialize shared qp ++ * @srq: hw srq (user and kernel) ++ * @info: srq initialization info ++ * ++ * initializes the vars used in both user and kernel mode. ++ * size of the wqe depends on numbers of max. fragements ++ * allowed. Then size of wqe * the number of wqes should be the ++ * amount of memory allocated for srq. ++ */ ++int irdma_uk_srq_init(struct irdma_srq_uk *srq, ++ struct irdma_srq_uk_init_info *info) ++{ ++ __u8 rqshift; ++ ++ srq->uk_attrs = info->uk_attrs; ++ if (info->max_srq_frag_cnt > srq->uk_attrs->max_hw_wq_frags) ++ return EINVAL; ++ ++ irdma_get_wqe_shift(srq->uk_attrs, info->max_srq_frag_cnt, 0, &rqshift); ++ srq->srq_caps = info->srq_caps; ++ srq->srq_base = info->srq; ++ srq->shadow_area = info->shadow_area; ++ srq->srq_id = info->srq_id; ++ srq->srwqe_polarity = 0; ++ srq->srq_size = info->srq_size; ++ srq->wqe_size = rqshift; ++ srq->max_srq_frag_cnt = min(srq->uk_attrs->max_hw_wq_frags, ++ ((__u32)2 << rqshift) - 1); ++ IRDMA_RING_INIT(srq->srq_ring, srq->srq_size); ++ srq->wqe_size_multiplier = 1 << rqshift; ++ srq->wqe_ops = iw_wqe_uk_ops; ++ ++ return 0; ++} ++ ++/** + * irdma_uk_calc_depth_shift_sq - calculate depth and shift for SQ size. + * @ukinfo: qp initialization info + * @sq_depth: Returns depth of SQ +@@ -1459,10 +2228,9 @@ + { + bool imm_support = ukinfo->uk_attrs->hw_rev >= IRDMA_GEN_2 ? true : false; + int status; +- + irdma_get_wqe_shift(ukinfo->uk_attrs, + imm_support ? ukinfo->max_sq_frag_cnt + 1 : +- ukinfo->max_sq_frag_cnt, ++ ukinfo->max_sq_frag_cnt, + ukinfo->max_inline_data, sq_shift); + status = irdma_get_sqdepth(ukinfo->uk_attrs, ukinfo->sq_size, + *sq_shift, sq_depth); +@@ -1505,8 +2273,7 @@ + * allowed. Then size of wqe * the number of wqes should be the + * amount of memory allocated for sq and rq. + */ +-int irdma_uk_qp_init(struct irdma_qp_uk *qp, +- struct irdma_qp_uk_init_info *info) ++int irdma_uk_qp_init(struct irdma_qp_uk *qp, struct irdma_qp_uk_init_info *info) + { + int ret_code = 0; + __u32 sq_ring_size; +@@ -1525,6 +2292,8 @@ + + qp->rq_wrid_array = info->rq_wrid_array; + qp->wqe_alloc_db = info->wqe_alloc_db; ++ qp->last_rx_cmpl_idx = 0xffffffff; ++ qp->rd_fence_rate = info->rd_fence_rate; + qp->qp_id = info->qp_id; + qp->sq_size = info->sq_size; + qp->push_mode = false; +@@ -1532,6 +2301,7 @@ + sq_ring_size = qp->sq_size << info->sq_shift; + IRDMA_RING_INIT(qp->sq_ring, sq_ring_size); + IRDMA_RING_INIT(qp->initial_ring, sq_ring_size); ++ atomic_init(&qp->sq_ring.post_cnt, 0); + if (info->first_sq_wq) { + irdma_setup_connection_wqes(qp, info); + qp->swqe_polarity = 1; +@@ -1551,6 +2321,11 @@ + qp->wqe_ops = iw_wqe_uk_ops_gen_1; + else + qp->wqe_ops = iw_wqe_uk_ops; ++ qp->sq_sigwrtrk_array = info->sq_sigwrtrk_array; ++ IRDMA_RING_INIT(qp->sq_sig_ring, sq_ring_size); ++ qp->srq_uk = info->srq_uk; ++ qp->start_wqe_idx = info->start_wqe_idx; ++ + return ret_code; + } + +@@ -1599,6 +2374,9 @@ + if (polarity != temp) + break; + ++ /* Ensure CQE contents are read after valid bit is checked */ ++ udma_from_device_barrier(); ++ + get_64bit_val(cqe, 8, &comp_ctx); + if ((void *)(uintptr_t)comp_ctx == q) + set_64bit_val(cqe, 8, 0); +@@ -1610,46 +2388,6 @@ + } + + /** +- * irdma_nop - post a nop +- * @qp: hw qp ptr +- * @wr_id: work request id +- * @signaled: signaled for completion +- * @post_sq: ring doorbell +- */ +-int irdma_nop(struct irdma_qp_uk *qp, __u64 wr_id, bool signaled, bool post_sq) +-{ +- __le64 *wqe; +- __u64 hdr; +- __u32 wqe_idx; +- struct irdma_post_sq_info info = {}; +- +- info.push_wqe = false; +- info.wr_id = wr_id; +- wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, IRDMA_QP_WQE_MIN_QUANTA, +- 0, &info); +- if (!wqe) +- return ENOMEM; +- +- irdma_clr_wqes(qp, wqe_idx); +- +- set_64bit_val(wqe, 0, 0); +- set_64bit_val(wqe, 8, 0); +- set_64bit_val(wqe, 16, 0); +- +- hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | +- FIELD_PREP(IRDMAQPSQ_SIGCOMPL, signaled) | +- FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); +- +- udma_to_device_barrier(); /* make sure WQE is populated before valid bit is set */ +- +- set_64bit_val(wqe, 24, hdr); +- if (post_sq) +- irdma_uk_qp_post_wr(qp); +- +- return 0; +-} +- +-/** + * irdma_fragcnt_to_quanta_sq - calculate quanta based on fragment count for SQ + * @frag_cnt: number of fragments + * @quanta: quanta for frag_cnt +@@ -1733,3 +2471,4 @@ + + return 0; + } ++ +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/umain.c nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/umain.c +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/umain.c 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/umain.c 2024-07-03 16:16:11.193764889 -0700 +@@ -1,6 +1,8 @@ + // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB + /* Copyright (C) 2019 - 2023 Intel Corporation */ ++#if HAVE_CONFIG_H + #include ++#endif + #include + #include + #include +@@ -10,12 +12,24 @@ + #include + #include + #include ++#include ++#include ++#include + + #include "ice_devids.h" + #include "i40e_devids.h" ++#include "idpf_devids.h" + #include "umain.h" + #include "abi.h" + ++unsigned int irdma_dbg; ++static pthread_t dbg_thread; ++static pthread_cond_t cond_sigusr1_rcvd; ++static _Atomic(int) dbg_thread_exit; ++pthread_mutex_t sigusr1_wait_mutex = PTHREAD_MUTEX_INITIALIZER; ++LIST_HEAD(dbg_ucq_list); /* list of alive cqs */ ++LIST_HEAD(dbg_uqp_list); /* list of alive qps */ ++ + #define INTEL_HCA(v, d) VERBS_PCI_MATCH(v, d, NULL) + static const struct verbs_match_ent hca_table[] = { + VERBS_DRIVER_ID(RDMA_DRIVER_IRDMA), +@@ -56,6 +70,9 @@ + INTEL_HCA(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF), + INTEL_HCA(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV), + ++ INTEL_HCA(PCI_VENDOR_ID_INTEL, IDPF_DEV_ID_PF), ++ INTEL_HCA(PCI_VENDOR_ID_INTEL, IAVF_DEV_ID_VF), ++ INTEL_HCA(PCI_VENDOR_ID_INTEL, IAVF_DEV_ID_ADAPTIVE_VF), + {} + }; + +@@ -69,37 +86,49 @@ + + iwvctx = container_of(ibctx, struct irdma_uvcontext, + ibv_ctx.context); +- + irdma_ufree_pd(&iwvctx->iwupd->ibv_pd); + irdma_munmap(iwvctx->db); + verbs_uninit_context(&iwvctx->ibv_ctx); ++ irdma_spin_destroy(&iwvctx->pd_lock); ++ + free(iwvctx); + } + ++static const struct verbs_context_ops irdma_uctx_mcast_ops = { ++ .attach_mcast = irdma_uattach_mcast, ++ .detach_mcast = irdma_udetach_mcast, ++}; ++ + static const struct verbs_context_ops irdma_uctx_ops = { + .alloc_mw = irdma_ualloc_mw, + .alloc_pd = irdma_ualloc_pd, +- .attach_mcast = irdma_uattach_mcast, ++ .alloc_parent_domain = irdma_ualloc_parent_domain, ++ .alloc_td = irdma_ualloc_td, + .bind_mw = irdma_ubind_mw, + .cq_event = irdma_cq_event, + .create_ah = irdma_ucreate_ah, + .create_cq = irdma_ucreate_cq, + .create_cq_ex = irdma_ucreate_cq_ex, + .create_qp = irdma_ucreate_qp, ++ .create_srq = irdma_ucreate_srq, + .dealloc_mw = irdma_udealloc_mw, + .dealloc_pd = irdma_ufree_pd, ++ .dealloc_td = irdma_udealloc_td, + .dereg_mr = irdma_udereg_mr, + .destroy_ah = irdma_udestroy_ah, + .destroy_cq = irdma_udestroy_cq, + .destroy_qp = irdma_udestroy_qp, +- .detach_mcast = irdma_udetach_mcast, ++ .destroy_srq = irdma_udestroy_srq, + .modify_qp = irdma_umodify_qp, ++ .modify_srq = irdma_umodify_srq, + .poll_cq = irdma_upoll_cq, + .post_recv = irdma_upost_recv, + .post_send = irdma_upost_send, ++ .post_srq_recv = irdma_upost_srq, + .query_device_ex = irdma_uquery_device_ex, + .query_port = irdma_uquery_port, + .query_qp = irdma_uquery_qp, ++ .query_srq = irdma_uquery_srq, + .reg_dmabuf_mr = irdma_ureg_mr_dmabuf, + .reg_mr = irdma_ureg_mr, + .rereg_mr = irdma_urereg_mr, +@@ -147,26 +176,34 @@ + struct irdma_get_context_resp resp = {}; + __u64 mmap_key; + __u8 user_ver = IRDMA_ABI_VER; ++ int ret; + + iwvctx = verbs_init_and_alloc_context(ibdev, cmd_fd, iwvctx, ibv_ctx, + RDMA_DRIVER_IRDMA); + if (!iwvctx) + return NULL; + ++ if (irdma_spin_init(&iwvctx->pd_lock, false)) { ++ free(iwvctx); ++ return NULL; ++ } ++ + cmd.comp_mask |= IRDMA_ALLOC_UCTX_USE_RAW_ATTR; ++ cmd.comp_mask |= IRDMA_SUPPORT_WQE_FORMAT_V2; ++retry: + cmd.userspace_ver = user_ver; +- if (ibv_cmd_get_context(&iwvctx->ibv_ctx, +- (struct ibv_get_context *)&cmd, sizeof(cmd), +- &resp.ibv_resp, sizeof(resp))) { +- cmd.userspace_ver = 4; +- if (ibv_cmd_get_context(&iwvctx->ibv_ctx, +- (struct ibv_get_context *)&cmd, sizeof(cmd), +- &resp.ibv_resp, sizeof(resp))) +- goto err_free; +- user_ver = cmd.userspace_ver; ++ ret = ibv_cmd_get_context(&iwvctx->ibv_ctx, (struct ibv_get_context *)&cmd, ++ sizeof(cmd), &resp.ibv_resp, sizeof(resp)); ++ if (ret) { ++ if (--user_ver >= 4) ++ goto retry; ++ ++ goto err_free; + } + + verbs_set_ops(&iwvctx->ibv_ctx, &irdma_uctx_ops); ++ if (resp.hw_rev == IRDMA_GEN_2 && ibdev->transport_type != IBV_TRANSPORT_IWARP) ++ verbs_set_ops(&iwvctx->ibv_ctx, &irdma_uctx_mcast_ops); + + /* Legacy i40iw does not populate hw_rev. The irdma driver always sets it */ + if (!resp.hw_rev) { +@@ -192,6 +229,11 @@ + iwvctx->uk_attrs.min_hw_wq_size = resp.min_hw_wq_size; + else + iwvctx->uk_attrs.min_hw_wq_size = IRDMA_QP_SW_MIN_WQSIZE; ++ iwvctx->uk_attrs.max_hw_srq_quanta = resp.max_hw_srq_quanta; ++ if (resp.comp_mask & IRDMA_SUPPORT_MAX_HW_PUSH_LEN) ++ iwvctx->uk_attrs.max_hw_push_len = resp.max_hw_push_len; ++ else ++ iwvctx->uk_attrs.max_hw_push_len = IRDMA_DEFAULT_MAX_PUSH_LEN; + mmap_key = resp.db_mmap_key; + } + +@@ -199,6 +241,7 @@ + if (iwvctx->db == MAP_FAILED) + goto err_free; + ++ list_head_init(&iwvctx->pd_list); + ibv_pd = irdma_ualloc_pd(&iwvctx->ibv_ctx.context); + if (!ibv_pd) { + irdma_munmap(iwvctx->db); +@@ -210,6 +253,9 @@ + return &iwvctx->ibv_ctx; + + err_free: ++ fprintf(stderr, PFX "%s: failed to allocate context for device, kernel ver:%d, user ver:%d hw_rev=%d\n", ++ __func__, resp.kernel_ver, IRDMA_ABI_VER, resp.hw_rev); ++ irdma_spin_destroy(&iwvctx->pd_lock); + free(iwvctx); + + return NULL; +@@ -219,19 +265,96 @@ + { + struct irdma_udevice *dev; + ++ if (irdma_dbg) { ++ atomic_store(&dbg_thread_exit, 1); ++ pthread_cond_signal(&cond_sigusr1_rcvd); ++ pthread_join(dbg_thread, NULL); ++ pthread_cond_destroy(&cond_sigusr1_rcvd); ++ } + dev = container_of(&verbs_device->device, struct irdma_udevice, + ibv_dev.device); + free(dev); + } + ++static void *dump_data_handler(void *unused) ++{ ++ struct irdma_ucq *dbg_ucq, *next; ++ struct irdma_uqp *dbg_uqp, *next_qp; ++ int ret = 0; ++ ++ pthread_mutex_lock(&sigusr1_wait_mutex); ++ while (1) { ++ ret = pthread_cond_wait(&cond_sigusr1_rcvd, &sigusr1_wait_mutex); ++ ++ if (ret || atomic_load(&dbg_thread_exit)) { ++ pthread_mutex_unlock(&sigusr1_wait_mutex); ++ return NULL; ++ } ++ ++ list_for_each_safe(&dbg_ucq_list, dbg_ucq, next, dbg_entry) { ++ ret = irdma_spin_lock(&dbg_ucq->lock); ++ if (ret) { ++ pthread_mutex_unlock(&sigusr1_wait_mutex); ++ return NULL; ++ } ++ irdma_print_cqes(&dbg_ucq->cq); ++ irdma_spin_unlock(&dbg_ucq->lock); ++ } ++ ++ list_for_each_safe(&dbg_uqp_list, dbg_uqp, next_qp, dbg_entry) { ++ ret = irdma_spin_lock(&dbg_uqp->lock); ++ if (ret) { ++ pthread_mutex_unlock(&sigusr1_wait_mutex); ++ return NULL; ++ } ++ irdma_print_sq_wqes(&dbg_uqp->qp); ++ irdma_spin_unlock(&dbg_uqp->lock); ++ } ++ } ++ pthread_mutex_unlock(&sigusr1_wait_mutex); ++} ++ ++static void irdma_signal_handler(int signum) ++{ ++ switch (signum) { ++ case SIGUSR1: ++ fprintf(stdout, "%s: Received SIGUSR1 signal\n", __func__); ++ pthread_cond_signal(&cond_sigusr1_rcvd); ++ break; ++ default: ++ fprintf(stdout, "%s: Unhandled signal %d\n", __func__, signum); ++ break; ++ } ++} ++ + static struct verbs_device *irdma_device_alloc(struct verbs_sysfs_dev *sysfs_dev) + { + struct irdma_udevice *dev; ++ char *env_val; + + dev = calloc(1, sizeof(*dev)); + if (!dev) + return NULL; + ++ env_val = getenv("IRDMA_DEBUG"); ++ if (env_val) ++ irdma_dbg = atoi(env_val); ++ ++ if (irdma_dbg) { ++ int ret; ++ ++ atomic_init(&dbg_thread_exit, 0); ++ signal(SIGUSR1, irdma_signal_handler); ++ pthread_cond_init(&cond_sigusr1_rcvd, NULL); ++ ++ ret = pthread_create(&dbg_thread, NULL, dump_data_handler, NULL); ++ if (ret) { ++ free(dev); ++ pthread_cond_destroy(&cond_sigusr1_rcvd); ++ return NULL; ++ } ++ } ++ + return &dev->ibv_dev; + } + +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/umain.h nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/umain.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/umain.h 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/umain.h 2024-07-03 16:16:11.193764889 -0700 +@@ -1,5 +1,5 @@ + /* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +-/* Copyright (C) 2019 - 2023 Intel Corporation */ ++/* Copyright (C) 2019 - 2022 Intel Corporation */ + #ifndef IRDMA_UMAIN_H + #define IRDMA_UMAIN_H + +@@ -15,21 +15,32 @@ + #include "i40iw_hw.h" + #include "user.h" + ++#ifndef likely ++#define likely(x) __builtin_expect((x), 1) ++#endif ++#ifndef unlikely ++#define unlikely(x) __builtin_expect((x), 0) ++#endif ++#define PFX "libirdma-" ++ + #define IRDMA_BASE_PUSH_PAGE 1 + #define IRDMA_U_MINCQ_SIZE 4 + #define IRDMA_DB_SHADOW_AREA_SIZE 64 + #define IRDMA_DB_CQ_OFFSET 64 + +-enum irdma_supported_wc_flags { +- IRDMA_CQ_SUPPORTED_WC_FLAGS = IBV_WC_EX_WITH_BYTE_LEN ++enum irdma_supported_wc_flags_ex { ++ IRDMA_STANDARD_WC_FLAGS_EX = IBV_WC_EX_WITH_BYTE_LEN + | IBV_WC_EX_WITH_IMM + | IBV_WC_EX_WITH_QP_NUM + | IBV_WC_EX_WITH_SRC_QP +- | IBV_WC_EX_WITH_SLID +- | IBV_WC_EX_WITH_SL +- | IBV_WC_EX_WITH_DLID_PATH_BITS +- | IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK +- | IBV_WC_EX_WITH_COMPLETION_TIMESTAMP, ++ | IBV_WC_EX_WITH_SL, ++ IRDMA_GEN3_WC_FLAGS_EX = IRDMA_STANDARD_WC_FLAGS_EX | ++ IBV_WC_EX_WITH_COMPLETION_TIMESTAMP, ++}; ++ ++struct irdma_spinlock { ++ pthread_spinlock_t lock; ++ bool skip_lock; + }; + + struct irdma_udevice { +@@ -47,6 +58,9 @@ + void *arm_cq_page; + void *arm_cq; + uint32_t pd_id; ++ struct list_node list; ++ atomic_int refcount; ++ struct irdma_upd *container_iwupd; + }; + + struct irdma_uvcontext { +@@ -57,6 +71,8 @@ + int abi_ver; + bool legacy_mode:1; + bool use_raw_attrs:1; ++ struct list_head pd_list; ++ struct irdma_spinlock pd_lock; + }; + + struct irdma_uqp; +@@ -65,25 +81,38 @@ + struct list_node list; + struct irdma_cq_uk cq; + struct verbs_mr vmr; ++ size_t buf_size; ++}; ++ ++extern struct list_head dbg_ucq_list; ++extern struct list_head dbg_uqp_list; ++extern pthread_mutex_t sigusr1_wait_mutex; ++ ++struct irdma_usrq { ++ struct verbs_srq v_srq; ++ struct verbs_mr vmr; ++ struct irdma_spinlock lock; ++ struct irdma_srq_uk srq; ++ size_t buf_size; + }; + + struct irdma_ucq { + struct verbs_cq verbs_cq; + struct verbs_mr vmr; + struct verbs_mr vmr_shadow_area; +- pthread_spinlock_t lock; ++ struct irdma_spinlock lock; + size_t buf_size; + bool is_armed; + bool skip_arm; + bool arm_sol; + bool skip_sol; + int comp_vector; +- uint32_t report_rtt; + struct irdma_uqp *uqp; + struct irdma_cq_uk cq; + struct list_head resize_list; + /* for extended CQ completion fields */ + struct irdma_cq_poll_info cur_cqe; ++ struct list_node dbg_entry; + }; + + struct irdma_uqp { +@@ -93,7 +122,7 @@ + struct verbs_mr vmr; + size_t buf_size; + uint32_t irdma_drv_opt; +- pthread_spinlock_t lock; ++ struct irdma_spinlock lock; + uint16_t sq_sig_all; + uint16_t qperr; + uint16_t rsvd; +@@ -102,13 +131,76 @@ + struct ibv_recv_wr *pend_rx_wr; + struct irdma_qp_uk qp; + enum ibv_qp_type qp_type; ++ struct list_node dbg_entry; + }; + +-struct irdma_umr { +- struct verbs_mr vmr; +- uint32_t acc_flags; ++struct irdma_utd { ++ struct ibv_td ibv_td; ++ atomic_int refcount; ++}; ++ ++struct irdma_uparent_domain { ++ struct irdma_upd iwupd; ++ struct irdma_utd *iwutd; + }; + ++static inline struct irdma_uparent_domain *to_iw_uparent_domain(struct ibv_pd *ibv_pd) ++{ ++ struct irdma_uparent_domain *iw_parent_domain = ++ container_of(ibv_pd, struct irdma_uparent_domain, iwupd.ibv_pd); ++ ++ if (iw_parent_domain && iw_parent_domain->iwupd.container_iwupd) ++ return iw_parent_domain; ++ ++ return NULL; ++} ++ ++static inline int irdma_spin_lock(struct irdma_spinlock *lock) ++{ ++ if (lock->skip_lock) ++ return 0; ++ ++ return pthread_spin_lock(&lock->lock); ++} ++ ++static inline int irdma_spin_unlock(struct irdma_spinlock *lock) ++{ ++ if (lock->skip_lock) ++ return 0; ++ ++ return pthread_spin_unlock(&lock->lock); ++ ++} ++ ++static inline int irdma_spin_init(struct irdma_spinlock *lock, bool skip_lock) ++{ ++ lock->skip_lock = skip_lock; ++ ++ if (lock->skip_lock) ++ return 0; ++ ++ return pthread_spin_init(&lock->lock, PTHREAD_PROCESS_PRIVATE); ++} ++ ++static inline int irdma_spin_init_pd(struct irdma_spinlock *lock, struct ibv_pd *pd) ++{ ++ struct irdma_uparent_domain *iw_parent_domain = to_iw_uparent_domain(pd); ++ bool skip_lock = false; ++ ++ if (iw_parent_domain && iw_parent_domain->iwutd) ++ skip_lock = true; ++ ++ return irdma_spin_init(lock, skip_lock); ++} ++ ++static inline int irdma_spin_destroy(struct irdma_spinlock *lock) ++{ ++ if (lock->skip_lock) ++ return 0; ++ ++ return pthread_spin_destroy(&lock->lock); ++} ++ + /* irdma_uverbs.c */ + int irdma_uquery_device_ex(struct ibv_context *context, + const struct ibv_query_device_ex_input *input, +@@ -123,8 +215,10 @@ + size_t length, uint64_t iova, int fd, + int access); + int irdma_udereg_mr(struct verbs_mr *vmr); +-int irdma_urereg_mr(struct verbs_mr *mr, int flags, struct ibv_pd *pd, +- void *addr, size_t length, int access); ++ ++int irdma_urereg_mr(struct verbs_mr *mr, int flags, struct ibv_pd *pd, void *addr, ++ size_t length, int access); ++ + struct ibv_mw *irdma_ualloc_mw(struct ibv_pd *pd, enum ibv_mw_type type); + int irdma_ubind_mw(struct ibv_qp *qp, struct ibv_mw *mw, + struct ibv_mw_bind *mw_bind); +@@ -158,9 +252,22 @@ + uint16_t lid); + int irdma_udetach_mcast(struct ibv_qp *qp, const union ibv_gid *gid, + uint16_t lid); ++struct ibv_srq *irdma_ucreate_srq(struct ibv_pd *pd, ++ struct ibv_srq_init_attr *initattr); ++int irdma_udestroy_srq(struct ibv_srq *ibsrq); ++int irdma_uquery_srq(struct ibv_srq *ibsrq, struct ibv_srq_attr *attr); ++int irdma_umodify_srq(struct ibv_srq *ibsrq, struct ibv_srq_attr *attr, ++ int attr_mask); ++int irdma_upost_srq(struct ibv_srq *ib_srq, struct ibv_recv_wr *ib_wr, ++ struct ibv_recv_wr **bad_wr); + void irdma_async_event(struct ibv_context *context, + struct ibv_async_event *event); + void irdma_set_hw_attrs(struct irdma_hw_attrs *attrs); + void *irdma_mmap(int fd, off_t offset); + void irdma_munmap(void *map); ++struct ibv_td *irdma_ualloc_td(struct ibv_context *context, ++ struct ibv_td_init_attr *init_attr); ++int irdma_udealloc_td(struct ibv_td *td); ++struct ibv_pd *irdma_ualloc_parent_domain(struct ibv_context *context, ++ struct ibv_parent_domain_init_attr *int_attr); + #endif /* IRDMA_UMAIN_H */ +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/user.h nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/user.h +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/user.h 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/user.h 2024-07-03 16:16:11.193764889 -0700 +@@ -5,6 +5,8 @@ + + #include "osdep.h" + ++#define PRINT_CQES ++ + #define irdma_handle void * + #define irdma_adapter_handle irdma_handle + #define irdma_qp_handle irdma_handle +@@ -19,7 +21,7 @@ + #define irdma_physical_fragment __u64 + #define irdma_address_list __u64 * + +-#define IRDMA_MAX_MR_SIZE 0x200000000000ULL ++#define IRDMA_MAX_MR_SIZE 0x200000000000ULL + + #define IRDMA_ACCESS_FLAGS_LOCALREAD 0x01 + #define IRDMA_ACCESS_FLAGS_LOCALWRITE 0x02 +@@ -31,6 +33,11 @@ + #define IRDMA_ACCESS_FLAGS_ZERO_BASED 0x20 + #define IRDMA_ACCESS_FLAGS_ALL 0x3f + ++#define IRDMA_FLUSH_MEM_REGION_PLACE_TYPE_GLOBAL_VIS BIT(0) ++#define IRDMA_FLUSH_MEM_REGION_PLACE_TYPE_PERSISTENCE BIT(1) ++#define IRDMA_FLUSH_MEM_REGION_SELECTIVITY_TYPE_WRITES_IN_RANGE 0x0 ++#define IRDMA_FLUSH_MEM_REGION_SELECTIVITY_TYPE_ALL_WRITES 0x1 ++ + #define IRDMA_OP_TYPE_RDMA_WRITE 0x00 + #define IRDMA_OP_TYPE_RDMA_READ 0x01 + #define IRDMA_OP_TYPE_SEND 0x03 +@@ -43,10 +50,118 @@ + #define IRDMA_OP_TYPE_INV_STAG 0x0a + #define IRDMA_OP_TYPE_RDMA_READ_INV_STAG 0x0b + #define IRDMA_OP_TYPE_NOP 0x0c ++#define IRDMA_OP_TYPE_ATOMIC_FETCH_AND_ADD 0x0f ++#define IRDMA_OP_TYPE_ATOMIC_COMPARE_AND_SWAP 0x11 ++#define IRDMA_OP_TYPE_ATOMIC_WRITE 0x12 ++#define IRDMA_OP_TYPE_FLUSH_MEMORY_REGION 0x13 + #define IRDMA_OP_TYPE_REC 0x3e + #define IRDMA_OP_TYPE_REC_IMM 0x3f + +-#define IRDMA_FLUSH_MAJOR_ERR 1 ++#define IRDMA_FLUSH_MAJOR_ERR 1 ++#define IRDMA_SRQFLUSH_RSVD_MAJOR_ERR 0xfffe ++/* Async Events codes */ ++#define IRDMA_AE_AMP_UNALLOCATED_STAG 0x0102 ++#define IRDMA_AE_AMP_INVALID_STAG 0x0103 ++#define IRDMA_AE_AMP_BAD_QP 0x0104 ++#define IRDMA_AE_AMP_BAD_PD 0x0105 ++#define IRDMA_AE_AMP_BAD_STAG_KEY 0x0106 ++#define IRDMA_AE_AMP_BAD_STAG_INDEX 0x0107 ++#define IRDMA_AE_AMP_BOUNDS_VIOLATION 0x0108 ++#define IRDMA_AE_AMP_RIGHTS_VIOLATION 0x0109 ++#define IRDMA_AE_AMP_TO_WRAP 0x010a ++#define IRDMA_AE_AMP_FASTREG_VALID_STAG 0x010c ++#define IRDMA_AE_AMP_FASTREG_MW_STAG 0x010d ++#define IRDMA_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e ++#define IRDMA_AE_AMP_FASTREG_INVALID_LENGTH 0x0110 ++#define IRDMA_AE_AMP_INVALIDATE_SHARED 0x0111 ++#define IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112 ++#define IRDMA_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113 ++#define IRDMA_AE_AMP_MWBIND_VALID_STAG 0x0114 ++#define IRDMA_AE_AMP_MWBIND_OF_MR_STAG 0x0115 ++#define IRDMA_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116 ++#define IRDMA_AE_AMP_MWBIND_TO_MW_STAG 0x0117 ++#define IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118 ++#define IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119 ++#define IRDMA_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a ++#define IRDMA_AE_AMP_MWBIND_BIND_DISABLED 0x011b ++#define IRDMA_AE_PRIV_OPERATION_DENIED 0x011c ++#define IRDMA_AE_AMP_INVALIDATE_TYPE1_MW 0x011d ++#define IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW 0x011e ++#define IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG 0x011f ++#define IRDMA_AE_AMP_MWBIND_WRONG_TYPE 0x0120 ++#define IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH 0x0121 ++#define IRDMA_AE_AMP_MEM_FLUSH_OVER_REACH 0x0125 ++#define IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132 ++#define IRDMA_AE_UDA_XMIT_BAD_PD 0x0133 ++#define IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134 ++#define IRDMA_AE_UDA_L4LEN_INVALID 0x0135 ++#define IRDMA_AE_BAD_CLOSE 0x0201 ++#define IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202 ++#define IRDMA_AE_CQ_OPERATION_ERROR 0x0203 ++#define IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205 ++#define IRDMA_AE_STAG_ZERO_INVALID 0x0206 ++#define IRDMA_AE_IB_RREQ_AND_Q1_FULL 0x0207 ++#define IRDMA_AE_IB_INVALID_REQUEST 0x0208 ++#define IRDMA_AE_SRQ_LIMIT 0x0209 ++#define IRDMA_AE_WQE_UNEXPECTED_OPCODE 0x020a ++#define IRDMA_AE_WQE_INVALID_PARAMETER 0x020b ++#define IRDMA_AE_WQE_INVALID_FRAG_DATA 0x020c ++#define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d ++#define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e ++#define IRDMA_AE_SRQ_CATASTROPHIC_ERROR 0x020f ++#define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220 ++#define IRDMA_AE_ATOMIC_ALIGNMENT 0x0221 ++#define IRDMA_AE_ATOMIC_MASK 0x0222 ++#define IRDMA_AE_INVALID_REQUEST 0x0223 ++#define IRDMA_AE_PCIE_ATOMIC_DISABLE 0x0224 ++#define IRDMA_AE_MEM_FLUSH_DISABLE 0x0230 ++#define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301 ++#define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303 ++#define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304 ++#define IRDMA_AE_DDP_UBE_INVALID_MO 0x0305 ++#define IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306 ++#define IRDMA_AE_DDP_UBE_INVALID_QN 0x0307 ++#define IRDMA_AE_DDP_NO_L_BIT 0x0308 ++#define IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311 ++#define IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312 ++#define IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313 ++#define IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314 ++#define IRDMA_AE_ROCE_RSP_LENGTH_ERROR 0x0316 ++#define IRDMA_AE_ROCE_REQ_LENGTH_ERROR 0x0318 ++#define IRDMA_AE_ROCE_EMPTY_MCG 0x0380 ++#define IRDMA_AE_ROCE_BAD_MC_IP_ADDR 0x0381 ++#define IRDMA_AE_ROCE_BAD_MC_QPID 0x0382 ++#define IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH 0x0383 ++#define IRDMA_AE_INVALID_ARP_ENTRY 0x0401 ++#define IRDMA_AE_INVALID_TCP_OPTION_RCVD 0x0402 ++#define IRDMA_AE_STALE_ARP_ENTRY 0x0403 ++#define IRDMA_AE_INVALID_AH_ENTRY 0x0406 ++#define IRDMA_AE_LLP_CLOSE_COMPLETE 0x0501 ++#define IRDMA_AE_LLP_CONNECTION_RESET 0x0502 ++#define IRDMA_AE_LLP_FIN_RECEIVED 0x0503 ++#define IRDMA_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504 ++#define IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505 ++#define IRDMA_AE_LLP_SEGMENT_TOO_SMALL 0x0507 ++#define IRDMA_AE_LLP_SYN_RECEIVED 0x0508 ++#define IRDMA_AE_LLP_TERMINATE_RECEIVED 0x0509 ++#define IRDMA_AE_LLP_TOO_MANY_RETRIES 0x050a ++#define IRDMA_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b ++#define IRDMA_AE_LLP_DOUBT_REACHABILITY 0x050c ++#define IRDMA_AE_LLP_CONNECTION_ESTABLISHED 0x050e ++#define IRDMA_AE_LLP_TOO_MANY_RNRS 0x050f ++#define IRDMA_AE_RESOURCE_EXHAUSTION 0x0520 ++#define IRDMA_AE_RESET_SENT 0x0601 ++#define IRDMA_AE_TERMINATE_SENT 0x0602 ++#define IRDMA_AE_RESET_NOT_SENT 0x0603 ++#define IRDMA_AE_LCE_QP_CATASTROPHIC 0x0700 ++#define IRDMA_AE_LCE_FUNCTION_CATASTROPHIC 0x0701 ++#define IRDMA_AE_LCE_CQ_CATASTROPHIC 0x0702 ++#define IRDMA_AE_REMOTE_QP_CATASTROPHIC 0x0703 ++#define IRDMA_AE_LOCAL_QP_CATASTROPHIC 0x0704 ++#define IRDMA_AE_RCE_QP_CATASTROPHIC 0x0705 ++#define IRDMA_AE_QP_SUSPEND_COMPLETE 0x0900 ++#define IRDMA_AE_CQP_DEFERRED_COMPLETE 0x0901 ++#define IRDMA_AE_ADAPTER_CATASTROPHIC 0x0B0B + + enum irdma_device_caps_const { + IRDMA_WQE_SIZE = 4, +@@ -55,31 +170,27 @@ + IRDMA_EXTENDED_CQE_SIZE = 8, + IRDMA_AEQE_SIZE = 2, + IRDMA_CEQE_SIZE = 1, +- IRDMA_CQP_CTX_SIZE = 8, ++ IRDMA_CQP_CTX_SIZE = 16, + IRDMA_SHADOW_AREA_SIZE = 8, + IRDMA_GATHER_STATS_BUF_SIZE = 1024, + IRDMA_MIN_IW_QP_ID = 0, +- IRDMA_QUERY_FPM_BUF_SIZE = 176, +- IRDMA_COMMIT_FPM_BUF_SIZE = 176, +- IRDMA_MAX_IW_QP_ID = 262143, ++ IRDMA_QUERY_FPM_BUF_SIZE = 184, ++ IRDMA_COMMIT_FPM_BUF_SIZE = 192, + IRDMA_MIN_CEQID = 0, + IRDMA_MAX_CEQID = 1023, + IRDMA_CEQ_MAX_COUNT = IRDMA_MAX_CEQID + 1, + IRDMA_MIN_CQID = 0, +- IRDMA_MAX_CQID = 524287, + IRDMA_MIN_AEQ_ENTRIES = 1, + IRDMA_MAX_AEQ_ENTRIES = 524287, ++ IRDMA_MAX_AEQ_ENTRIES_GEN_3 = 262144, + IRDMA_MIN_CEQ_ENTRIES = 1, + IRDMA_MAX_CEQ_ENTRIES = 262143, + IRDMA_MIN_CQ_SIZE = 1, + IRDMA_MAX_CQ_SIZE = 1048575, + IRDMA_DB_ID_ZERO = 0, +- IRDMA_MAX_WQ_FRAGMENT_COUNT = 13, +- IRDMA_MAX_SGE_RD = 13, + IRDMA_MAX_OUTBOUND_MSG_SIZE = 2147483647, + IRDMA_MAX_INBOUND_MSG_SIZE = 2147483647, +- IRDMA_MAX_PUSH_PAGE_COUNT = 1024, +- IRDMA_MAX_PE_ENA_VF_COUNT = 32, ++ IRDMA_MAX_PE_ENA_VF_COUNT = 32, + IRDMA_MAX_VF_FPM_ID = 47, + IRDMA_MAX_SQ_PAYLOAD_SIZE = 2145386496, + IRDMA_MAX_INLINE_DATA_SIZE = 101, +@@ -106,6 +217,13 @@ + FLUSH_RETRY_EXC_ERR, + FLUSH_MW_BIND_ERR, + FLUSH_REM_INV_REQ_ERR, ++ FLUSH_RNR_RETRY_EXC_ERR, ++}; ++ ++enum irdma_qp_event_type { ++ IRDMA_QP_EVENT_CATASTROPHIC, ++ IRDMA_QP_EVENT_ACCESS_ERR, ++ IRDMA_QP_EVENT_REQ_ERR, + }; + + enum irdma_cmpl_status { +@@ -148,6 +266,8 @@ + IRDMA_PUSH_MODE = 8, + }; + ++struct irdma_srq_uk; ++struct irdma_srq_uk_init_info; + struct irdma_qp_uk; + struct irdma_cq_uk; + struct irdma_qp_uk_init_info; +@@ -155,8 +275,11 @@ + + struct irdma_ring { + __u32 head; +- __u32 tail; ++ __u32 tail; /* effective tail */ + __u32 size; ++ __u32 user_size; ++ _Atomic(int) post_cnt; ++ __u32 unsig_post_cnt; + }; + + struct irdma_cqe { +@@ -167,6 +290,16 @@ + __le64 buf[IRDMA_EXTENDED_CQE_SIZE]; + }; + ++struct irdma_post_send_combined_inline_sge { ++ struct ibv_sge *sg_list; ++ void *data; ++ __u32 num_sges; ++ __u32 len; ++ __u32 ah_id; ++ __u32 qkey; ++ __u32 dest_qp; ++}; ++ + struct irdma_post_send { + struct ibv_sge *sg_list; + __u32 num_sges; +@@ -181,6 +314,14 @@ + __u32 num_sges; + }; + ++struct irdma_rdma_write_combined_inline_sge { ++ struct ibv_sge *lo_sg_list; ++ void *data; ++ __u32 num_lo_sges; ++ __u32 len; ++ struct ibv_sge rem_addr; ++}; ++ + struct irdma_rdma_write { + struct ibv_sge *lo_sg_list; + __u32 num_lo_sges; +@@ -202,8 +343,43 @@ + bool ena_writes:1; + irdma_stag mw_stag; + bool mem_window_type_1:1; ++ bool remote_atomics_en:1; + }; + ++struct irdma_atomic_fetch_add { ++ __u64 tagged_offset; ++ __u64 remote_tagged_offset; ++ __u64 fetch_add_data_bytes; ++ __u32 stag; ++ __u32 remote_stag; ++}; ++ ++struct irdma_atomic_compare_swap { ++ __u64 tagged_offset; ++ __u64 remote_tagged_offset; ++ __u64 swap_data_bytes; ++ __u64 compare_data_bytes; ++ __u32 stag; ++ __u32 remote_stag; ++}; ++ ++struct irdma_atomic_write { ++ __u64 tagged_offset; ++ __u64 remote_tagged_offset; ++ __u64 write_data_bytes; ++ __u64 inline_data; ++ __u32 remote_stag; ++ __u32 stag; ++ bool is_inline_data:1; ++}; ++ ++struct irdma_flush_mem_region { ++ __u64 remote_tagged_offset; ++ __u32 remote_stag; ++ __u32 length; ++ __u8 selectivity; ++ __u8 placement_type; ++}; + struct irdma_inv_local_stag { + irdma_stag target_stag; + }; +@@ -221,6 +397,7 @@ + bool report_rtt:1; + bool udp_hdr:1; + bool defer_flag:1; ++ bool remote_atomic_en:1; + __u32 imm_data; + __u32 stag_to_inv; + union { +@@ -229,6 +406,12 @@ + struct irdma_rdma_read rdma_read; + struct irdma_bind_window bind_window; + struct irdma_inv_local_stag inv_local_stag; ++ struct irdma_atomic_fetch_add atomic_fetch_add; ++ struct irdma_atomic_compare_swap atomic_compare_swap; ++ struct irdma_rdma_write_combined_inline_sge rdma_write_combined_sge_inline; ++ struct irdma_post_send_combined_inline_sge send_combined_sge_inline; ++ struct irdma_atomic_write atomic_write; ++ struct irdma_flush_mem_region flush_mem_region; + } op; + }; + +@@ -236,7 +419,6 @@ + __u64 wr_id; + irdma_qp_handle qp_handle; + __u32 bytes_xfered; +- __u32 tcp_seq_num_rtt; + __u32 qp_id; + __u32 ud_src_qpn; + __u32 imm_data; +@@ -256,8 +438,29 @@ + bool ud_vlan_valid:1; + bool ud_smac_valid:1; + bool imm_valid:1; +-}; +- ++ union { ++ __u32 tcp_sqn; ++ __u32 roce_psn; ++ __u32 rtt; ++ __u32 timestamp; ++ __u32 raw; ++ } stat; ++}; ++ ++struct qp_err_code { ++ enum irdma_flush_opcode flush_code; ++ enum irdma_qp_event_type event_type; ++}; ++ ++int irdma_uk_flush_mem_region(struct irdma_qp_uk *qp, ++ struct irdma_post_sq_info *info, bool post_sq); ++int irdma_uk_atomic_write(struct irdma_qp_uk *qp, ++ struct irdma_post_sq_info *info, bool post_sq); ++ ++int irdma_uk_atomic_compare_swap(struct irdma_qp_uk *qp, ++ struct irdma_post_sq_info *info, bool post_sq); ++int irdma_uk_atomic_fetch_add(struct irdma_qp_uk *qp, ++ struct irdma_post_sq_info *info, bool post_sq); + int irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq); + int irdma_uk_inline_send(struct irdma_qp_uk *qp, +@@ -280,8 +483,7 @@ + bool post_sq); + + struct irdma_wqe_uk_ops { +- void (*iw_copy_inline_data)(__u8 *dest, struct ibv_sge *sge_list, +- __u32 num_sges, __u8 polarity); ++ void (*iw_copy_inline_data)(__u8 *dest, struct ibv_sge *sge_list, __u32 num_sges, __u8 polarity); + __u16 (*iw_inline_data_size_to_quanta)(__u32 data_size); + void (*iw_set_fragment)(__le64 *wqe, __u32 offset, struct ibv_sge *sge, + __u8 valid); +@@ -303,6 +505,43 @@ + __u32 *sq_depth, __u8 *sq_shift); + int irdma_uk_calc_depth_shift_rq(struct irdma_qp_uk_init_info *ukinfo, + __u32 *rq_depth, __u8 *rq_shift); ++int irdma_uk_srq_init(struct irdma_srq_uk *srq, ++ struct irdma_srq_uk_init_info *info); ++int irdma_uk_srq_post_receive(struct irdma_srq_uk *srq, ++ struct irdma_post_rq_info *info); ++ ++struct irdma_srq_uk { ++ __u32 srq_caps; ++ struct irdma_qp_quanta *srq_base; ++ struct irdma_uk_attrs *uk_attrs; ++ __le64 *shadow_area; ++ struct irdma_ring srq_ring; ++ struct irdma_ring initial_ring; ++ __u32 srq_id; ++ __u32 srq_size; ++ __u32 max_srq_frag_cnt; ++ struct irdma_wqe_uk_ops wqe_ops; ++ __u8 srwqe_polarity; ++ __u8 wqe_size; ++ __u8 wqe_size_multiplier; ++ __u8 deferred_flag; ++}; ++ ++struct irdma_srq_uk_init_info { ++ struct irdma_qp_quanta *srq; ++ struct irdma_uk_attrs *uk_attrs; ++ __le64 *shadow_area; ++ __u64 *srq_wrid_array; ++ __u32 srq_id; ++ __u32 srq_caps; ++ __u32 srq_size; ++ __u32 max_srq_frag_cnt; ++}; ++ ++struct irdma_sig_wr_trk_info { ++ __u32 wqe_idx; ++ __u32 post_cnt; ++}; + + struct irdma_sq_uk_wr_trk_info { + __u64 wrid; +@@ -318,14 +557,19 @@ + struct irdma_qp_uk { + struct irdma_qp_quanta *sq_base; + struct irdma_qp_quanta *rq_base; ++ struct irdma_srq_uk *srq_uk; + struct irdma_uk_attrs *uk_attrs; + __u32 *wqe_alloc_db; + struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; ++ struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; + __u64 *rq_wrid_array; + __le64 *shadow_area; + __le32 *push_db; + __le64 *push_wqe; ++ void *push_db_map; ++ void *push_wqe_map; + struct irdma_ring sq_ring; ++ struct irdma_ring sq_sig_ring; + struct irdma_ring rq_ring; + struct irdma_ring initial_ring; + __u32 qp_id; +@@ -335,6 +579,8 @@ + __u32 max_sq_frag_cnt; + __u32 max_rq_frag_cnt; + __u32 max_inline_data; ++ __u32 last_rx_cmpl_idx; ++ __u32 last_tx_cmpl_idx; + struct irdma_wqe_uk_ops wqe_ops; + __u16 conn_wqes; + __u8 qp_type; +@@ -343,6 +589,7 @@ + __u8 rwqe_polarity; + __u8 rq_wqe_size; + __u8 rq_wqe_size_multiplier; ++ __u8 start_wqe_idx; + bool deferred_flag:1; + bool push_mode:1; /* whether the last post wqe was pushed */ + bool push_dropped:1; +@@ -353,8 +600,10 @@ + void *back_qp; + pthread_spinlock_t *lock; + __u8 dbg_rq_flushed; ++ __u16 ord_cnt; + __u8 sq_flush_seen; + __u8 rq_flush_seen; ++ __u8 rd_fence_rate; + }; + + struct irdma_cq_uk { +@@ -372,10 +621,12 @@ + struct irdma_qp_uk_init_info { + struct irdma_qp_quanta *sq; + struct irdma_qp_quanta *rq; ++ struct irdma_srq_uk *srq_uk; + struct irdma_uk_attrs *uk_attrs; + __u32 *wqe_alloc_db; + __le64 *shadow_area; + struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; ++ struct irdma_sig_wr_trk_info *sq_sigwrtrk_array; + __u64 *rq_wrid_array; + __u32 qp_id; + __u32 qp_caps; +@@ -387,9 +638,11 @@ + __u32 sq_depth; + __u32 rq_depth; + __u8 first_sq_wq; ++ __u8 start_wqe_idx; + __u8 type; + __u8 sq_shift; + __u8 rq_shift; ++ __u8 rd_fence_rate; + int abi_ver; + bool legacy_mode; + }; +@@ -404,9 +657,12 @@ + bool avoid_mem_cflct; + }; + ++void irdma_print_cqes(struct irdma_cq_uk *cq); ++void irdma_print_sq_wqes(struct irdma_qp_uk *qp); + __le64 *irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, __u32 *wqe_idx, +- __u16 quanta, __u32 total_size, ++ __u16 *quanta, __u32 total_size, + struct irdma_post_sq_info *info); ++__le64 *irdma_srq_get_next_recv_wqe(struct irdma_srq_uk *srq, __u32 *wqe_idx); + __le64 *irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, __u32 *wqe_idx); + void irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq); + int irdma_nop(struct irdma_qp_uk *qp, __u64 wr_id, bool signaled, bool post_sq); +@@ -415,10 +671,91 @@ + void irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, __u32 sge, + __u32 inline_data, __u8 *shift); + int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, __u32 sq_size, +- __u8 shift, __u32 *wqdepth); ++ __u8 shift, __u32 *sqdepth); + int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, __u32 rq_size, +- __u8 shift, __u32 *wqdepth); ++ __u8 shift, __u32 *rqdepth); ++int irdma_get_srqdepth(struct irdma_uk_attrs *uk_attrs, __u32 srq_size, ++ __u8 shift, __u32 *srqdepth); + void irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 *wqe, __u16 quanta, + __u32 wqe_idx, bool post_sq); + void irdma_clr_wqes(struct irdma_qp_uk *qp, __u32 qp_wqe_idx); ++ ++static inline struct qp_err_code irdma_ae_to_qp_err_code(__u16 ae_id) ++{ ++ struct qp_err_code qp_err = {}; ++ ++ switch (ae_id) { ++ case IRDMA_AE_AMP_BOUNDS_VIOLATION: ++ case IRDMA_AE_AMP_INVALID_STAG: ++ case IRDMA_AE_AMP_RIGHTS_VIOLATION: ++ case IRDMA_AE_AMP_UNALLOCATED_STAG: ++ case IRDMA_AE_AMP_BAD_PD: ++ case IRDMA_AE_AMP_BAD_QP: ++ case IRDMA_AE_AMP_BAD_STAG_KEY: ++ case IRDMA_AE_AMP_BAD_STAG_INDEX: ++ case IRDMA_AE_AMP_TO_WRAP: ++ case IRDMA_AE_PRIV_OPERATION_DENIED: ++ qp_err.flush_code = FLUSH_PROT_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; ++ break; ++ case IRDMA_AE_UDA_XMIT_BAD_PD: ++ case IRDMA_AE_WQE_UNEXPECTED_OPCODE: ++ qp_err.flush_code = FLUSH_LOC_QP_OP_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; ++ break; ++ case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: ++ case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: ++ case IRDMA_AE_UDA_L4LEN_INVALID: ++ case IRDMA_AE_DDP_UBE_INVALID_MO: ++ case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: ++ qp_err.flush_code = FLUSH_LOC_LEN_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; ++ break; ++ case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: ++ case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: ++ qp_err.flush_code = FLUSH_REM_ACCESS_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; ++ break; ++ case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS: ++ case IRDMA_AE_AMP_MWBIND_BIND_DISABLED: ++ case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS: ++ case IRDMA_AE_AMP_MWBIND_VALID_STAG: ++ qp_err.flush_code = FLUSH_MW_BIND_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; ++ break; ++ case IRDMA_AE_LLP_TOO_MANY_RETRIES: ++ qp_err.flush_code = FLUSH_RETRY_EXC_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; ++ break; ++ case IRDMA_AE_IB_INVALID_REQUEST: ++ qp_err.flush_code = FLUSH_REM_INV_REQ_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_REQ_ERR; ++ break; ++ case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: ++ case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: ++ case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: ++ case IRDMA_AE_ROCE_REQ_LENGTH_ERROR: ++ case IRDMA_AE_IB_REMOTE_OP_ERROR: ++ qp_err.flush_code = FLUSH_REM_OP_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; ++ break; ++ case IRDMA_AE_LLP_TOO_MANY_RNRS: ++ qp_err.flush_code = FLUSH_RNR_RETRY_EXC_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; ++ break; ++ case IRDMA_AE_LCE_QP_CATASTROPHIC: ++ case IRDMA_AE_REMOTE_QP_CATASTROPHIC: ++ case IRDMA_AE_LOCAL_QP_CATASTROPHIC: ++ case IRDMA_AE_RCE_QP_CATASTROPHIC: ++ qp_err.flush_code = FLUSH_FATAL_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; ++ break; ++ default: ++ qp_err.flush_code = FLUSH_GENERAL_ERR; ++ qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; ++ break; ++ } ++ ++ return qp_err; ++} + #endif /* IRDMA_USER_H */ +diff -N -u -r -x .clang-format -x '.git*' -x '.tr*' -x '.ma*' -x 'pandoc*' nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/uverbs.c nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/uverbs.c +--- nd_linux-irdma-rdma-core/rdma-core-copy/providers/irdma/uverbs.c 2024-07-03 16:16:04.624700122 -0700 ++++ nd_linux-irdma-rdma-core/rdma-core-51.0/providers/irdma/uverbs.c 2024-07-03 16:16:11.193764889 -0700 +@@ -1,6 +1,8 @@ + // SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB + /* Copyright (C) 2019 - 2023 Intel Corporation */ ++#if HAVE_CONFIG_H + #include ++#endif + #include + #include + #include +@@ -19,6 +21,29 @@ + #include "umain.h" + #include "abi.h" + ++static int irdma_validate_pd(struct ibv_pd *pd) ++{ ++ struct irdma_upd *iwupd, *next; ++ struct irdma_uvcontext *iwvctx = container_of(pd->context, struct irdma_uvcontext, ++ ibv_ctx.context); ++ int ret; ++ ++ ret = irdma_spin_lock(&iwvctx->pd_lock); ++ if (ret) ++ return ret; ++ ++ list_for_each_safe(&iwvctx->pd_list, iwupd, next, list) { ++ if (&iwupd->ibv_pd == pd) { ++ irdma_spin_unlock(&iwvctx->pd_lock); ++ return 0; ++ } ++ } ++ ++ irdma_spin_unlock(&iwvctx->pd_lock); ++ ++ return EINVAL; ++} ++ + static inline void print_fw_ver(uint64_t fw_ver, char *str, size_t len) + { + uint16_t major, minor; +@@ -54,6 +79,28 @@ + return 0; + } + ++struct ibv_mr *irdma_ureg_mr_dmabuf(struct ibv_pd *pd, uint64_t offset, ++ size_t length, uint64_t iova, int fd, ++ int access) ++{ ++ struct verbs_mr *vmr; ++ int err; ++ ++ vmr = malloc(sizeof(*vmr)); ++ if (!vmr) ++ return NULL; ++ ++ err = ibv_cmd_reg_dmabuf_mr(pd, offset, length, iova, fd, access, ++ vmr); ++ if (err) { ++ free(vmr); ++ errno = err; ++ return NULL; ++ } ++ ++ return &vmr->ibv_mr; ++} ++ + /** + * irdma_uquery_port - get port attributes (msg size, lnk, mtu...) + * @context: user context of the device +@@ -68,6 +115,79 @@ + return ibv_cmd_query_port(context, port, attr, &cmd, sizeof(cmd)); + } + ++struct ibv_pd *irdma_ualloc_parent_domain(struct ibv_context *context, ++ struct ibv_parent_domain_init_attr *init_attr) ++{ ++ struct irdma_uparent_domain *iw_parent_domain; ++ struct irdma_uvcontext *iwvctx; ++ int ret; ++ ++ if (ibv_check_alloc_parent_domain(init_attr)) ++ return NULL; ++ ++ /* Add Input validation for any optional fields we dont support */ ++ ++ iw_parent_domain = calloc(1, sizeof(*iw_parent_domain)); ++ if (!iw_parent_domain) ++ return NULL; ++ ++ if (init_attr->td) { ++ iw_parent_domain->iwutd = ++ container_of(init_attr->td, struct irdma_utd, ibv_td); ++ atomic_fetch_add(&iw_parent_domain->iwutd->refcount, 1); ++ } ++ ++ iw_parent_domain->iwupd.container_iwupd = ++ container_of(init_attr->pd, struct irdma_upd, ibv_pd); ++ ++ atomic_fetch_add(&iw_parent_domain->iwupd.container_iwupd->refcount, 1); ++ atomic_init(&iw_parent_domain->iwupd.refcount, 1); ++ ++ ibv_initialize_parent_domain(&iw_parent_domain->iwupd.ibv_pd, ++ &iw_parent_domain->iwupd.container_iwupd->ibv_pd); ++ iwvctx = container_of(context, struct irdma_uvcontext, ibv_ctx.context); ++ ret = irdma_spin_lock(&iwvctx->pd_lock); ++ if (ret) { ++ if (iw_parent_domain->iwutd) ++ atomic_fetch_sub(&iw_parent_domain->iwutd->refcount, 1); ++ ++ atomic_fetch_sub(&iw_parent_domain->iwupd.container_iwupd->refcount, 1); ++ free(iw_parent_domain); ++ errno = ret; ++ return NULL; ++ } ++ ++ list_add_tail(&iwvctx->pd_list, &iw_parent_domain->iwupd.list); ++ irdma_spin_unlock(&iwvctx->pd_lock); ++ ++ return &iw_parent_domain->iwupd.ibv_pd; ++} ++ ++static int irdma_udealloc_parent_domain(struct irdma_uparent_domain *iw_parent_domain) ++{ ++ struct irdma_uvcontext *iwvctx; ++ int ret; ++ if (atomic_load(&iw_parent_domain->iwupd.refcount) > 1) ++ return EBUSY; ++ ++ atomic_fetch_sub(&iw_parent_domain->iwupd.container_iwupd->refcount, 1); ++ ++ if (iw_parent_domain->iwutd) ++ atomic_fetch_sub(&iw_parent_domain->iwutd->refcount, 1); ++ ++ iwvctx = container_of(iw_parent_domain->iwupd.ibv_pd.context, ++ struct irdma_uvcontext, ibv_ctx.context); ++ ret = irdma_spin_lock(&iwvctx->pd_lock); ++ if (ret) ++ return ret; ++ list_del(&iw_parent_domain->iwupd.list); ++ irdma_spin_unlock(&iwvctx->pd_lock); ++ ++ free(iw_parent_domain); ++ ++ return 0; ++} ++ + /** + * irdma_ualloc_pd - allocates protection domain and return pd ptr + * @context: user context of the device +@@ -77,9 +197,11 @@ + struct ibv_alloc_pd cmd; + struct irdma_ualloc_pd_resp resp = {}; + struct irdma_upd *iwupd; ++ struct irdma_uvcontext *iwvctx = container_of(context, struct irdma_uvcontext, ++ ibv_ctx.context); + int err; + +- iwupd = malloc(sizeof(*iwupd)); ++ iwupd = calloc(1, sizeof(*iwupd)); + if (!iwupd) + return NULL; + +@@ -89,11 +211,21 @@ + goto err_free; + + iwupd->pd_id = resp.pd_id; ++ err = irdma_spin_lock(&iwvctx->pd_lock); ++ if (err) ++ goto err_del_pd; ++ ++ list_add_tail(&iwvctx->pd_list, &iwupd->list); ++ irdma_spin_unlock(&iwvctx->pd_lock); ++ atomic_init(&iwupd->refcount, 1); + + return &iwupd->ibv_pd; + ++err_del_pd: ++ ibv_cmd_dealloc_pd(&iwupd->ibv_pd); + err_free: + free(iwupd); ++ + errno = err; + return NULL; + } +@@ -104,14 +236,30 @@ + */ + int irdma_ufree_pd(struct ibv_pd *pd) + { ++ struct irdma_uvcontext *iwvctx = container_of(pd->context, struct irdma_uvcontext, ++ ibv_ctx.context); ++ struct irdma_uparent_domain *iw_parent_domain; + struct irdma_upd *iwupd; + int ret; + ++ iw_parent_domain = to_iw_uparent_domain(pd); ++ if (iw_parent_domain) ++ return irdma_udealloc_parent_domain(iw_parent_domain); ++ + iwupd = container_of(pd, struct irdma_upd, ibv_pd); ++ if (atomic_load(&iwupd->refcount) > 1) ++ return EBUSY; ++ + ret = ibv_cmd_dealloc_pd(pd); + if (ret) + return ret; + ++ ret = irdma_spin_lock(&iwvctx->pd_lock); ++ if (ret) ++ return ret; ++ list_del(&iwupd->list); ++ irdma_spin_unlock(&iwvctx->pd_lock); ++ + free(iwupd); + + return 0; +@@ -128,49 +276,32 @@ + struct ibv_mr *irdma_ureg_mr(struct ibv_pd *pd, void *addr, size_t length, + uint64_t hca_va, int access) + { +- struct irdma_umr *umr; +- struct irdma_ureg_mr cmd; ++ struct verbs_mr *vmr; ++ struct irdma_ureg_mr cmd = {}; + struct ib_uverbs_reg_mr_resp resp; + int err; + +- umr = malloc(sizeof(*umr)); +- if (!umr) +- return NULL; +- +- cmd.reg_type = IRDMA_MEMREG_TYPE_MEM; +- err = ibv_cmd_reg_mr(pd, addr, length, +- hca_va, access, &umr->vmr, &cmd.ibv_cmd, +- sizeof(cmd), &resp, sizeof(resp)); ++ err = irdma_validate_pd(pd); + if (err) { +- free(umr); + errno = err; + return NULL; + } +- umr->acc_flags = access; +- +- return &umr->vmr.ibv_mr; +-} + +-struct ibv_mr *irdma_ureg_mr_dmabuf(struct ibv_pd *pd, uint64_t offset, +- size_t length, uint64_t iova, int fd, +- int access) +-{ +- struct irdma_umr *umr; +- int err; +- +- umr = calloc(1, sizeof(*umr)); +- if (!umr) ++ vmr = malloc(sizeof(*vmr)); ++ if (!vmr) + return NULL; + +- err = ibv_cmd_reg_dmabuf_mr(pd, offset, length, iova, fd, access, +- &umr->vmr); ++ cmd.reg_type = IRDMA_MEMREG_TYPE_MEM; ++ err = ibv_cmd_reg_mr(pd, addr, length, ++ hca_va, access, vmr, &cmd.ibv_cmd, ++ sizeof(cmd), &resp, sizeof(resp)); + if (err) { +- free(umr); ++ free(vmr); + errno = err; + return NULL; + } + +- return &umr->vmr.ibv_mr; ++ return &vmr->ibv_mr; + } + + /* +@@ -221,9 +352,11 @@ + struct ibv_mw *mw; + struct ibv_alloc_mw cmd; + struct ib_uverbs_alloc_mw_resp resp; ++ int err; + +- if (type != IBV_MW_TYPE_1) { +- errno = ENOTSUP; ++ err = irdma_validate_pd(pd); ++ if (err) { ++ errno = err; + return NULL; + } + +@@ -231,9 +364,13 @@ + if (!mw) + return NULL; + +- if (ibv_cmd_alloc_mw(pd, type, mw, &cmd, sizeof(cmd), &resp, +- sizeof(resp))) { ++ err = ibv_cmd_alloc_mw(pd, type, mw, &cmd, sizeof(cmd), &resp, ++ sizeof(resp)); ++ if (err) { ++ fprintf(stderr, PFX "%s: Failed to alloc memory window\n", ++ __func__); + free(mw); ++ errno = err; + return NULL; + } + +@@ -250,19 +387,27 @@ + struct ibv_mw_bind *mw_bind) + { + struct ibv_mw_bind_info *bind_info = &mw_bind->bind_info; +- struct verbs_mr *vmr = verbs_get_mr(bind_info->mr); +- struct irdma_umr *umr = container_of(vmr, struct irdma_umr, vmr); ++ struct verbs_mr *vmr; + + struct ibv_send_wr wr = {}; + struct ibv_send_wr *bad_wr; + int err; + +- if (vmr->mr_type != IBV_MR_TYPE_MR) +- return ENOTSUP; +- +- if (umr->acc_flags & IBV_ACCESS_ZERO_BASED) ++ if (!bind_info->mr && (bind_info->addr || bind_info->length)) + return EINVAL; + ++ if (bind_info->mr) { ++ vmr = verbs_get_mr(bind_info->mr); ++ if (vmr->mr_type != IBV_MR_TYPE_MR) ++ return ENOTSUP; ++ ++ if (vmr->access & IBV_ACCESS_ZERO_BASED) ++ return EINVAL; ++ ++ if (mw->pd != bind_info->mr->pd) ++ return EPERM; ++ } ++ + wr.opcode = IBV_WR_BIND_MW; + wr.bind_mw.bind_info = mw_bind->bind_info; + wr.bind_mw.mw = mw; +@@ -294,11 +439,11 @@ + return 0; + } + +-static void *irdma_alloc_hw_buf(size_t size) ++static void *irdma_calloc_hw_buf_sz(size_t size, size_t alignment) + { + void *buf; + +- buf = memalign(IRDMA_HW_PAGE_SIZE, size); ++ buf = memalign(alignment, size); + + if (!buf) + return NULL; +@@ -306,10 +451,16 @@ + free(buf); + return NULL; + } ++ memset(buf, 0, size); + + return buf; + } + ++static void *irdma_calloc_hw_buf(size_t size) ++{ ++ return irdma_calloc_hw_buf_sz(size, IRDMA_HW_PAGE_SIZE); ++} ++ + static void irdma_free_hw_buf(void *buf, size_t size) + { + ibv_dofork_range(buf, size); +@@ -317,16 +468,192 @@ + } + + /** ++ * irdma_uquery_srq - query srq ++ * @ibsrq: ib srq structure ++ * @attr: srq attributes to fill in ++ */ ++int irdma_uquery_srq(struct ibv_srq *ibsrq, struct ibv_srq_attr *attr) ++{ ++ struct ibv_query_srq cmd; ++ ++ return ibv_cmd_query_srq(ibsrq, attr, &cmd, sizeof(cmd)); ++} ++ ++/** ++ * irdma_umodify_srq - modify srq ++ * @ibsrq: ib srq structure ++ * @attr: srq attributes to use ++ * @attr_mask: mask of the attributes ++ */ ++int irdma_umodify_srq(struct ibv_srq *ibsrq, ++ struct ibv_srq_attr *attr, ++ int attr_mask) ++{ ++ struct ibv_modify_srq cmd; ++ ++ return ibv_cmd_modify_srq(ibsrq, attr, attr_mask, &cmd, sizeof(cmd)); ++} ++ ++/** ++ * irdma_udestroy_srq - destroy srq ++ * @ibsrq: ib srq structure ++ */ ++int irdma_udestroy_srq(struct ibv_srq *ibsrq) ++{ ++ struct irdma_usrq *iwusrq; ++ struct verbs_srq *vsrq; ++ int ret; ++ ++ vsrq = container_of(ibsrq, struct verbs_srq, srq); ++ iwusrq = container_of(vsrq, struct irdma_usrq, v_srq); ++ ++ ret = irdma_spin_destroy(&iwusrq->lock); ++ if (ret) ++ goto err; ++ ++ ret = ibv_cmd_destroy_srq(ibsrq); ++ if (ret) ++ return ret; ++ ++ ibv_cmd_dereg_mr(&iwusrq->vmr); ++ irdma_free_hw_buf(iwusrq->srq.srq_base, iwusrq->buf_size); ++ free(iwusrq); ++ return 0; ++err: ++ return ret; ++} ++ ++/** ++ * irdma_ucreate_srq - create srq on user app ++ * @pd: pd for the qp ++ * @initattr: attributes of the srq to be created ++ */ ++struct ibv_srq *irdma_ucreate_srq(struct ibv_pd *pd, ++ struct ibv_srq_init_attr *initattr) ++{ ++ struct ib_uverbs_reg_mr_resp reg_mr_resp = {}; ++ struct irdma_srq_uk_init_info info = {}; ++ struct irdma_ucreate_srq_resp resp = {}; ++ struct irdma_ureg_mr reg_mr_cmd = {}; ++ struct irdma_ucreate_srq cmd = {}; ++ struct irdma_uk_attrs *uk_attrs; ++ struct irdma_uvcontext *iwvctx; ++ struct irdma_usrq *iwusrq; ++ struct ibv_srq_attr *attr; ++ size_t total_size; ++ size_t size; ++ __u32 depth; ++ __u8 shift; ++ int ret; ++ ++ iwvctx = container_of(pd->context, struct irdma_uvcontext, ibv_ctx.context); ++ uk_attrs = &iwvctx->uk_attrs; ++ attr = &initattr->attr; ++ ++ if (!(uk_attrs->feature_flags & IRDMA_FEATURE_SRQ)) { ++ errno = EOPNOTSUPP; ++ return NULL; ++ } ++ ++ if (attr->max_sge > uk_attrs->max_hw_wq_frags || ++ attr->max_wr > uk_attrs->max_hw_srq_quanta) { ++ errno = EINVAL; ++ return NULL; ++ } ++ ++ irdma_get_wqe_shift(uk_attrs, attr->max_sge, 0, &shift); ++ ++ ret = irdma_get_srqdepth(uk_attrs, attr->max_wr, shift, &depth); ++ if (ret) { ++ errno = ret; ++ fprintf(stderr, PFX "%s: invalid SRQ attributes, max_wr=%d max_recv_sge=%d\n", ++ __func__, attr->max_wr, attr->max_sge); ++ return NULL; ++ } ++ ++ iwusrq = calloc(1, sizeof(*iwusrq)); ++ if (!iwusrq) ++ return NULL; ++ ++ ret = irdma_spin_init_pd(&iwusrq->lock, pd); ++ if (ret) ++ goto err_lock; ++ ++ info.uk_attrs = uk_attrs; ++ info.max_srq_frag_cnt = attr->max_sge; ++ ++ size = roundup(depth * IRDMA_QP_WQE_MIN_SIZE, IRDMA_HW_PAGE_SIZE); ++ total_size = size + IRDMA_DB_SHADOW_AREA_SIZE; ++ iwusrq->buf_size = total_size; ++ info.srq = irdma_calloc_hw_buf(total_size); ++ ++ if (!info.srq) { ++ ret = ENOMEM; ++ goto err_sges; ++ } ++ ++ reg_mr_cmd.reg_type = IRDMA_MEMREG_TYPE_SRQ; ++ reg_mr_cmd.rq_pages = size >> IRDMA_HW_PAGE_SHIFT; ++ ++ ret = ibv_cmd_reg_mr(pd, info.srq, total_size, ++ (uintptr_t)info.srq, IBV_ACCESS_LOCAL_WRITE, ++ &iwusrq->vmr, ®_mr_cmd.ibv_cmd, ++ sizeof(reg_mr_cmd), ®_mr_resp, ++ sizeof(reg_mr_resp)); ++ if (ret) ++ goto err_cmd_reg; ++ ++ iwusrq->vmr.ibv_mr.pd = pd; ++ info.shadow_area = (__le64 *)((__u8 *)info.srq + size); ++ ++ cmd.user_srq_buf = (__u64)((uintptr_t)info.srq); ++ cmd.user_shadow_area = (__u64)((uintptr_t)info.shadow_area); ++ ret = ibv_cmd_create_srq(pd, &iwusrq->v_srq.srq, initattr, &cmd.ibv_cmd, ++ sizeof(cmd), &resp.ibv_resp, sizeof(resp)); ++ if (ret) ++ goto err_create_srq; ++ ++ info.uk_attrs = uk_attrs; ++ info.max_srq_frag_cnt = attr->max_sge; ++ info.srq_id = resp.srq_id; ++ info.srq_size = resp.srq_size; ++ ++ ret = irdma_uk_srq_init(&iwusrq->srq, &info); ++ if (ret) ++ goto err_srq_init; ++ ++ attr->max_wr = (depth - IRDMA_RQ_RSVD) >> shift; ++ ++ return &iwusrq->v_srq.srq; ++ ++err_srq_init: ++ ibv_cmd_destroy_srq(&iwusrq->v_srq.srq); ++err_create_srq: ++ ibv_cmd_dereg_mr(&iwusrq->vmr); ++err_cmd_reg: ++ irdma_free_hw_buf(info.srq, total_size); ++err_sges: ++ irdma_spin_destroy(&iwusrq->lock); ++err_lock: ++ fprintf(stderr, PFX "%s: failed to create SRQ, status %d\n", __func__, ret); ++ free(iwusrq); ++ ++ errno = ret; ++ return NULL; ++} ++ ++/** + * get_cq_size - returns actual cqe needed by HW + * @ncqe: minimum cqes requested by application + * @hw_rev: HW generation ++ * @cqe_64byte_ena: enable 64byte cqe + */ +-static inline int get_cq_size(int ncqe, __u8 hw_rev) ++static inline int get_cq_size(int ncqe, __u8 hw_rev, bool cqe_64byte_ena) + { + ncqe++; + + /* Completions with immediate require 1 extra entry */ +- if (hw_rev > IRDMA_GEN_1) ++ if (!cqe_64byte_ena && hw_rev > IRDMA_GEN_1) + ncqe *= 2; + + if (ncqe < IRDMA_U_MINCQ_SIZE) +@@ -335,9 +662,12 @@ + return ncqe; + } + +-static inline size_t get_cq_total_bytes(__u32 cq_size) ++static inline size_t get_cq_total_bytes(__u32 cq_size, bool cqe_64byte_ena) + { +- return roundup(cq_size * sizeof(struct irdma_cqe), IRDMA_HW_PAGE_SIZE); ++ if (cqe_64byte_ena) ++ return roundup(cq_size * sizeof(struct irdma_extended_cqe), IRDMA_HW_PAGE_SIZE); ++ else ++ return roundup(cq_size * sizeof(struct irdma_cqe), IRDMA_HW_PAGE_SIZE); + } + + /** +@@ -364,47 +694,59 @@ + __u32 cq_pages; + int ret, ncqe; + __u8 hw_rev; ++ bool cqe_64byte_ena; + + iwvctx = container_of(context, struct irdma_uvcontext, ibv_ctx.context); + uk_attrs = &iwvctx->uk_attrs; + hw_rev = uk_attrs->hw_rev; + +- if (ext_cq && hw_rev == IRDMA_GEN_1) { +- errno = EOPNOTSUPP; +- return NULL; ++ if (ext_cq) { ++ __u32 supported_flags = hw_rev >= IRDMA_GEN_3 ? ++ IRDMA_GEN3_WC_FLAGS_EX : IRDMA_STANDARD_WC_FLAGS_EX; ++ ++ if (hw_rev == IRDMA_GEN_1 || attr_ex->wc_flags & ~supported_flags) { ++ errno = EOPNOTSUPP; ++ return NULL; ++ } + } + +- if (attr_ex->cqe < IRDMA_MIN_CQ_SIZE || attr_ex->cqe > uk_attrs->max_hw_cq_size - 1) { ++ if (attr_ex->cqe < uk_attrs->min_hw_cq_size || attr_ex->cqe > uk_attrs->max_hw_cq_size - 1) { + errno = EINVAL; + return NULL; + } + + /* save the cqe requested by application */ + ncqe = attr_ex->cqe; ++ + iwucq = calloc(1, sizeof(*iwucq)); + if (!iwucq) + return NULL; + +- if (pthread_spin_init(&iwucq->lock, PTHREAD_PROCESS_PRIVATE)) { ++ ret = irdma_spin_init(&iwucq->lock, ++ attr_ex->flags & IBV_CREATE_CQ_ATTR_SINGLE_THREADED ? true : false); ++ if (ret) { + free(iwucq); ++ errno = ret; + return NULL; + } + +- info.cq_size = get_cq_size(attr_ex->cqe, hw_rev); ++ cqe_64byte_ena = uk_attrs->feature_flags & IRDMA_FEATURE_64_BYTE_CQE ? true : false; ++ info.cq_size = get_cq_size(attr_ex->cqe, hw_rev, cqe_64byte_ena); ++ total_size = get_cq_total_bytes(info.cq_size, cqe_64byte_ena); + iwucq->comp_vector = attr_ex->comp_vector; + list_head_init(&iwucq->resize_list); +- total_size = get_cq_total_bytes(info.cq_size); + cq_pages = total_size >> IRDMA_HW_PAGE_SHIFT; + + if (!(uk_attrs->feature_flags & IRDMA_FEATURE_CQ_RESIZE)) + total_size = (cq_pages << IRDMA_HW_PAGE_SHIFT) + IRDMA_DB_SHADOW_AREA_SIZE; + + iwucq->buf_size = total_size; +- info.cq_base = irdma_alloc_hw_buf(total_size); +- if (!info.cq_base) ++ info.cq_base = irdma_calloc_hw_buf(total_size); ++ if (!info.cq_base) { ++ ret = ENOMEM; + goto err_cq_base; ++ } + +- memset(info.cq_base, 0, total_size); + reg_mr_cmd.reg_type = IRDMA_MEMREG_TYPE_CQ; + reg_mr_cmd.cq_pages = cq_pages; + +@@ -413,19 +755,18 @@ + IBV_ACCESS_LOCAL_WRITE, &iwucq->vmr, + ®_mr_cmd.ibv_cmd, sizeof(reg_mr_cmd), + ®_mr_resp, sizeof(reg_mr_resp)); +- if (ret) { +- errno = ret; ++ if (ret) + goto err_dereg_mr; +- } + + iwucq->vmr.ibv_mr.pd = &iwvctx->iwupd->ibv_pd; + + if (uk_attrs->feature_flags & IRDMA_FEATURE_CQ_RESIZE) { +- info.shadow_area = irdma_alloc_hw_buf(IRDMA_DB_SHADOW_AREA_SIZE); +- if (!info.shadow_area) +- goto err_dereg_mr; ++ info.shadow_area = irdma_calloc_hw_buf(IRDMA_DB_SHADOW_AREA_SIZE); ++ if (!info.shadow_area) { ++ ret = ENOMEM; ++ goto err_alloc_shadow; ++ } + +- memset(info.shadow_area, 0, IRDMA_DB_SHADOW_AREA_SIZE); + reg_mr_shadow_cmd.reg_type = IRDMA_MEMREG_TYPE_CQ; + reg_mr_shadow_cmd.cq_pages = 1; + +@@ -435,15 +776,14 @@ + ®_mr_shadow_cmd.ibv_cmd, sizeof(reg_mr_shadow_cmd), + ®_mr_shadow_resp, sizeof(reg_mr_shadow_resp)); + if (ret) { +- errno = ret; +- goto err_dereg_shadow; ++ irdma_free_hw_buf(info.shadow_area, IRDMA_DB_SHADOW_AREA_SIZE); ++ goto err_alloc_shadow; + } + + iwucq->vmr_shadow_area.ibv_mr.pd = &iwvctx->iwupd->ibv_pd; + + } else { +- info.shadow_area = (__le64 *)((__u8 *)info.cq_base + +- (cq_pages << IRDMA_HW_PAGE_SHIFT)); ++ info.shadow_area = (__le64 *)((__u8 *)info.cq_base + (cq_pages << IRDMA_HW_PAGE_SHIFT)); + } + + attr_ex->cqe = info.cq_size; +@@ -453,35 +793,40 @@ + ret = ibv_cmd_create_cq_ex(context, attr_ex, &iwucq->verbs_cq, + &cmd.ibv_cmd, sizeof(cmd), &resp.ibv_resp, + sizeof(resp), 0); +- if (ret) { +- errno = ret; +- goto err_dereg_shadow; +- } ++ attr_ex->cqe = ncqe; ++ if (ret) ++ goto err_create_cq; + + if (ext_cq) + irdma_ibvcq_ex_fill_priv_funcs(iwucq, attr_ex); + info.cq_id = resp.cq_id; +- /* Do not report the cqe's burned by HW */ ++ /* Do not report the CQE's reserved for immediate and burned by HW */ + iwucq->verbs_cq.cq.cqe = ncqe; +- ++ if (cqe_64byte_ena) ++ info.avoid_mem_cflct = true; + info.cqe_alloc_db = (__u32 *)((__u8 *)iwvctx->db + IRDMA_DB_CQ_OFFSET); + irdma_uk_cq_init(&iwucq->cq, &info); +- ++ pthread_mutex_lock(&sigusr1_wait_mutex); ++ list_add(&dbg_ucq_list, &iwucq->dbg_entry); ++ pthread_mutex_unlock(&sigusr1_wait_mutex); + return &iwucq->verbs_cq.cq_ex; + +-err_dereg_shadow: +- ibv_cmd_dereg_mr(&iwucq->vmr); ++err_create_cq: + if (iwucq->vmr_shadow_area.ibv_mr.handle) { + ibv_cmd_dereg_mr(&iwucq->vmr_shadow_area); +- irdma_free_hw_buf(info.shadow_area, IRDMA_HW_PAGE_SIZE); ++ irdma_free_hw_buf(info.shadow_area, IRDMA_DB_SHADOW_AREA_SIZE); + } ++err_alloc_shadow: ++ ibv_cmd_dereg_mr(&iwucq->vmr); + err_dereg_mr: + irdma_free_hw_buf(info.cq_base, total_size); + err_cq_base: +- pthread_spin_destroy(&iwucq->lock); ++ fprintf(stderr, PFX "%s: failed to initialize CQ\n", __func__); ++ irdma_spin_destroy(&iwucq->lock); + + free(iwucq); + ++ errno = ret; + return NULL; + } + +@@ -504,11 +849,6 @@ + struct ibv_cq_ex *irdma_ucreate_cq_ex(struct ibv_context *context, + struct ibv_cq_init_attr_ex *attr_ex) + { +- if (attr_ex->wc_flags & ~IRDMA_CQ_SUPPORTED_WC_FLAGS) { +- errno = EOPNOTSUPP; +- return NULL; +- } +- + return ucreate_cq(context, attr_ex, true); + } + +@@ -519,7 +859,7 @@ + static void irdma_free_cq_buf(struct irdma_cq_buf *cq_buf) + { + ibv_cmd_dereg_mr(&cq_buf->vmr); +- irdma_free_hw_buf(cq_buf->cq.cq_base, get_cq_total_bytes(cq_buf->cq.cq_size)); ++ irdma_free_hw_buf(cq_buf->cq.cq_base, cq_buf->buf_size); + free(cq_buf); + } + +@@ -562,7 +902,10 @@ + ibv_ctx.context); + uk_attrs = &iwvctx->uk_attrs; + +- ret = pthread_spin_destroy(&iwucq->lock); ++ pthread_mutex_lock(&sigusr1_wait_mutex); ++ list_del(&iwucq->dbg_entry); ++ pthread_mutex_unlock(&sigusr1_wait_mutex); ++ ret = irdma_spin_destroy(&iwucq->lock); + if (ret) + goto err; + +@@ -600,12 +943,14 @@ + return IBV_WC_LOC_LEN_ERR; + case FLUSH_GENERAL_ERR: + return IBV_WC_WR_FLUSH_ERR; +- case FLUSH_RETRY_EXC_ERR: +- return IBV_WC_RETRY_EXC_ERR; + case FLUSH_MW_BIND_ERR: + return IBV_WC_MW_BIND_ERR; + case FLUSH_REM_INV_REQ_ERR: + return IBV_WC_REM_INV_REQ_ERR; ++ case FLUSH_RETRY_EXC_ERR: ++ return IBV_WC_RETRY_EXC_ERR; ++ case FLUSH_RNR_RETRY_EXC_ERR: ++ return IBV_WC_RNR_RETRY_EXC_ERR; + case FLUSH_FATAL_ERR: + default: + return IBV_WC_FATAL_ERR; +@@ -631,21 +976,37 @@ + case IRDMA_OP_TYPE_BIND_MW: + entry->opcode = IBV_WC_BIND_MW; + break; ++ case IRDMA_OP_TYPE_ATOMIC_COMPARE_AND_SWAP: ++ entry->opcode = IBV_WC_COMP_SWAP; ++ break; ++ case IRDMA_OP_TYPE_ATOMIC_FETCH_AND_ADD: ++ entry->opcode = IBV_WC_FETCH_ADD; ++ break; + case IRDMA_OP_TYPE_INV_STAG: + entry->opcode = IBV_WC_LOCAL_INV; + break; + default: + entry->status = IBV_WC_GENERAL_ERR; ++ fprintf(stderr, PFX "%s: Invalid opcode = %d in CQE\n", ++ __func__, cur_cqe->op_type); ++ } ++} ++ ++static inline void set_ib_wc_op_rq_gen_3(struct irdma_cq_poll_info *cur_cqe, struct ibv_wc *entry) ++{ ++ switch (cur_cqe->op_type) { ++ case IRDMA_OP_TYPE_RDMA_WRITE: ++ case IRDMA_OP_TYPE_RDMA_WRITE_SOL: ++ entry->opcode = IBV_WC_RECV_RDMA_WITH_IMM; ++ break; ++ default: ++ entry->opcode = IBV_WC_RECV; + } + } + + static inline void set_ib_wc_op_rq(struct irdma_cq_poll_info *cur_cqe, + struct ibv_wc *entry, bool send_imm_support) + { +- /** +- * iWARP does not support sendImm, so the presence of Imm data +- * must be WriteImm. +- */ + if (!send_imm_support) { + entry->opcode = cur_cqe->imm_valid ? IBV_WC_RECV_RDMA_WITH_IMM : + IBV_WC_RECV; +@@ -711,9 +1072,12 @@ + if (cur_cqe->q_type == IRDMA_CQE_QTYPE_SQ) { + set_ib_wc_op_sq(cur_cqe, entry); + } else { +- set_ib_wc_op_rq(cur_cqe, entry, +- qp->qp_caps & IRDMA_SEND_WITH_IMM ? +- true : false); ++ if (qp->uk_attrs->hw_rev <= IRDMA_GEN_2) ++ set_ib_wc_op_rq(cur_cqe, entry, ++ qp->qp_caps & IRDMA_SEND_WITH_IMM ? ++ true : false); ++ else ++ set_ib_wc_op_rq_gen_3(cur_cqe, entry); + if (ib_qp->qp_type != IBV_QPT_UD && + cur_cqe->stag_invalid_set) { + entry->invalidated_rkey = cur_cqe->inv_stag; +@@ -761,7 +1125,7 @@ + * @entry: pointer to array of ibv_wc objects to be filled in for each completion or NULL if ext CQ + * + * Returns non-negative value equal to the number of completions +- * found. On failure, -EINVAL ++ * found. On failure, EINVAL + */ + static int __irdma_upoll_cq(struct irdma_ucq *iwucq, int num_entries, + struct ibv_wc *entry) +@@ -832,8 +1196,9 @@ + return npolled; + + error: ++ fprintf(stderr, PFX "%s: Error polling CQ, irdma_err: %d\n", __func__, ret); + +- return -EINVAL; ++ return EINVAL; + } + + /** +@@ -851,13 +1216,13 @@ + int ret; + + iwucq = container_of(cq, struct irdma_ucq, verbs_cq.cq); +- ret = pthread_spin_lock(&iwucq->lock); ++ ret = irdma_spin_lock(&iwucq->lock); + if (ret) + return -ret; + + ret = __irdma_upoll_cq(iwucq, num_entries, entry); + +- pthread_spin_unlock(&iwucq->lock); ++ irdma_spin_unlock(&iwucq->lock); + + return ret; + } +@@ -876,7 +1241,7 @@ + int ret; + + iwucq = container_of(ibvcq_ex, struct irdma_ucq, verbs_cq.cq_ex); +- ret = pthread_spin_lock(&iwucq->lock); ++ ret = irdma_spin_lock(&iwucq->lock); + if (ret) + return ret; + +@@ -888,7 +1253,7 @@ + if (!ret) + ret = ENOENT; + +- pthread_spin_unlock(&iwucq->lock); ++ irdma_spin_unlock(&iwucq->lock); + + return ret; + } +@@ -926,7 +1291,7 @@ + struct irdma_ucq *iwucq = container_of(ibvcq_ex, struct irdma_ucq, + verbs_cq.cq_ex); + +- pthread_spin_unlock(&iwucq->lock); ++ irdma_spin_unlock(&iwucq->lock); + } + + /** +@@ -939,24 +1304,8 @@ + { + struct irdma_ucq *iwucq = container_of(ibvcq_ex, struct irdma_ucq, + verbs_cq.cq_ex); +-#define HCA_CORE_CLOCK_800_MHZ 800 + +- return iwucq->cur_cqe.tcp_seq_num_rtt / HCA_CORE_CLOCK_800_MHZ; +-} +- +-/** +- * irdma_wc_read_completion_wallclock_ns - Get completion timestamp in ns +- * @ibvcq_ex: ibv extended CQ +- * +- * Get completion timestamp from current completion in wall clock nanoseconds +- */ +-static uint64_t irdma_wc_read_completion_wallclock_ns(struct ibv_cq_ex *ibvcq_ex) +-{ +- struct irdma_ucq *iwucq = container_of(ibvcq_ex, struct irdma_ucq, +- verbs_cq.cq_ex); +- +- /* RTT is in usec */ +- return iwucq->cur_cqe.tcp_seq_num_rtt * 1000; ++ return iwucq->cur_cqe.stat.timestamp; + } + + static enum ibv_wc_opcode irdma_wc_read_opcode(struct ibv_cq_ex *ibvcq_ex) +@@ -977,6 +1326,10 @@ + return IBV_WC_SEND; + case IRDMA_OP_TYPE_BIND_MW: + return IBV_WC_BIND_MW; ++ case IRDMA_OP_TYPE_ATOMIC_COMPARE_AND_SWAP: ++ return IBV_WC_COMP_SWAP; ++ case IRDMA_OP_TYPE_ATOMIC_FETCH_AND_ADD: ++ return IBV_WC_FETCH_ADD; + case IRDMA_OP_TYPE_REC: + return IBV_WC_RECV; + case IRDMA_OP_TYPE_REC_IMM: +@@ -985,6 +1338,9 @@ + return IBV_WC_LOCAL_INV; + } + ++ fprintf(stderr, PFX "%s: Invalid opcode = %d in CQE\n", __func__, ++ iwucq->cur_cqe.op_type); ++ + return 0; + } + +@@ -1075,21 +1431,11 @@ + return ib_qp->qp_type == IBV_QPT_UD ? cur_cqe->ud_src_qpn : cur_cqe->qp_id; + } + +-static uint32_t irdma_wc_read_slid(struct ibv_cq_ex *ibvcq_ex) +-{ +- return 0; +-} +- + static uint8_t irdma_wc_read_sl(struct ibv_cq_ex *ibvcq_ex) + { + return 0; + } + +-static uint8_t irdma_wc_read_dlid_path_bits(struct ibv_cq_ex *ibvcq_ex) +-{ +- return 0; +-} +- + void irdma_ibvcq_ex_fill_priv_funcs(struct irdma_ucq *iwucq, + struct ibv_cq_init_attr_ex *attr_ex) + { +@@ -1099,15 +1445,8 @@ + ibvcq_ex->end_poll = irdma_end_poll; + ibvcq_ex->next_poll = irdma_next_poll; + +- if (attr_ex->wc_flags & IBV_WC_EX_WITH_COMPLETION_TIMESTAMP) { ++ if (attr_ex->wc_flags & IBV_WC_EX_WITH_COMPLETION_TIMESTAMP) + ibvcq_ex->read_completion_ts = irdma_wc_read_completion_ts; +- iwucq->report_rtt = true; +- } +- if (attr_ex->wc_flags & IBV_WC_EX_WITH_COMPLETION_TIMESTAMP_WALLCLOCK) { +- ibvcq_ex->read_completion_wallclock_ns = irdma_wc_read_completion_wallclock_ns; +- iwucq->report_rtt = true; +- } +- + ibvcq_ex->read_opcode = irdma_wc_read_opcode; + ibvcq_ex->read_vendor_err = irdma_wc_read_vendor_err; + ibvcq_ex->read_wc_flags = irdma_wc_read_wc_flags; +@@ -1120,12 +1459,8 @@ + ibvcq_ex->read_qp_num = irdma_wc_read_qp_num; + if (attr_ex->wc_flags & IBV_WC_EX_WITH_SRC_QP) + ibvcq_ex->read_src_qp = irdma_wc_read_src_qp; +- if (attr_ex->wc_flags & IBV_WC_EX_WITH_SLID) +- ibvcq_ex->read_slid = irdma_wc_read_slid; + if (attr_ex->wc_flags & IBV_WC_EX_WITH_SL) + ibvcq_ex->read_sl = irdma_wc_read_sl; +- if (attr_ex->wc_flags & IBV_WC_EX_WITH_DLID_PATH_BITS) +- ibvcq_ex->read_dlid_path_bits = irdma_wc_read_dlid_path_bits; + } + + /** +@@ -1158,7 +1493,7 @@ + if (solicited) + cq_notify = IRDMA_CQ_COMPL_SOLICITED; + +- ret = pthread_spin_lock(&iwucq->lock); ++ ret = irdma_spin_lock(&iwucq->lock); + if (ret) + return ret; + +@@ -1173,7 +1508,7 @@ + irdma_arm_cq(iwucq, cq_notify); + } + +- pthread_spin_unlock(&iwucq->lock); ++ irdma_spin_unlock(&iwucq->lock); + + return 0; + } +@@ -1187,7 +1522,7 @@ + struct irdma_ucq *iwucq; + + iwucq = container_of(cq, struct irdma_ucq, verbs_cq.cq); +- if (pthread_spin_lock(&iwucq->lock)) ++ if (irdma_spin_lock(&iwucq->lock)) + return; + + if (iwucq->skip_arm) +@@ -1195,7 +1530,7 @@ + else + iwucq->is_armed = false; + +- pthread_spin_unlock(&iwucq->lock); ++ irdma_spin_unlock(&iwucq->lock); + } + + void *irdma_mmap(int fd, off_t offset) +@@ -1234,9 +1569,9 @@ + return ret; + + if (iwuqp->qp.push_db) +- irdma_munmap(iwuqp->qp.push_db); ++ irdma_munmap(iwuqp->qp.push_db_map); + if (iwuqp->qp.push_wqe) +- irdma_munmap(iwuqp->qp.push_wqe); ++ irdma_munmap(iwuqp->qp.push_wqe_map); + + ibv_cmd_dereg_mr(&iwuqp->vmr); + +@@ -1249,7 +1584,7 @@ + * @pd: pd for the qp + * @attr: attributes of qp passed + * @resp: response back from create qp +- * @info: info for initializing user level qp ++ * @info: uk info for initializing user level qp + * @abi_ver: abi version of the create qp command + */ + static int irdma_vmapped_qp(struct irdma_uqp *iwuqp, struct ibv_pd *pd, +@@ -1262,18 +1597,29 @@ + struct irdma_ucreate_qp_resp resp = {}; + struct irdma_ureg_mr reg_mr_cmd = {}; + struct ib_uverbs_reg_mr_resp reg_mr_resp = {}; ++ struct irdma_uvcontext *iwvctx; + int ret; ++ long os_pgsz = IRDMA_HW_PAGE_SIZE; + + sqsize = roundup(info->sq_depth * IRDMA_QP_WQE_MIN_SIZE, IRDMA_HW_PAGE_SIZE); + rqsize = roundup(info->rq_depth * IRDMA_QP_WQE_MIN_SIZE, IRDMA_HW_PAGE_SIZE); + totalqpsize = rqsize + sqsize + IRDMA_DB_SHADOW_AREA_SIZE; +- info->sq = irdma_alloc_hw_buf(totalqpsize); +- iwuqp->buf_size = totalqpsize; + ++ iwvctx = container_of(pd->context, struct irdma_uvcontext, ++ ibv_ctx.context); ++ /* adjust alignment for iwarp */ ++ if (iwvctx->ibv_ctx.context.device->transport_type == ++ IBV_TRANSPORT_IWARP) { ++ long pgsz = sysconf(_SC_PAGESIZE); ++ ++ if (pgsz > 0) ++ os_pgsz = pgsz; ++ } ++ info->sq = irdma_calloc_hw_buf_sz(totalqpsize, os_pgsz); + if (!info->sq) + return ENOMEM; + +- memset(info->sq, 0, totalqpsize); ++ iwuqp->buf_size = totalqpsize; + info->rq = &info->sq[sqsize / IRDMA_QP_WQE_MIN_SIZE]; + info->shadow_area = info->rq[rqsize / IRDMA_QP_WQE_MIN_SIZE].elem; + +@@ -1291,6 +1637,8 @@ + + cmd.user_wqe_bufs = (__u64)((uintptr_t)info->sq); + cmd.user_compl_ctx = (__u64)(uintptr_t)&iwuqp->qp; ++ cmd.comp_mask |= IRDMA_CREATE_QP_USE_START_WQE_IDX; ++ + ret = ibv_cmd_create_qp(pd, &iwuqp->ibv_qp, attr, &cmd.ibv_cmd, + sizeof(cmd), &resp.ibv_resp, + sizeof(struct irdma_ucreate_qp_resp)); +@@ -1300,6 +1648,8 @@ + info->sq_size = resp.actual_sq_size; + info->rq_size = resp.actual_rq_size; + info->first_sq_wq = legacy_mode ? 1 : resp.lsmm; ++ if (resp.comp_mask & IRDMA_CREATE_QP_USE_START_WQE_IDX) ++ info->start_wqe_idx = resp.start_wqe_idx; + info->qp_caps = resp.qp_caps; + info->qp_id = resp.qp_id; + iwuqp->irdma_drv_opt = resp.irdma_drv_opt; +@@ -1316,6 +1666,7 @@ + err_qp: + ibv_cmd_dereg_mr(&iwuqp->vmr); + err_dereg_mr: ++ fprintf(stderr, PFX "%s: failed to create QP, status %d\n", __func__, ret); + irdma_free_hw_buf(info->sq, iwuqp->buf_size); + return ret; + } +@@ -1334,7 +1685,15 @@ + struct irdma_uqp *iwuqp; + int status; + ++ status = irdma_validate_pd(pd); ++ if (status) { ++ errno = status; ++ return NULL; ++ } ++ + if (attr->qp_type != IBV_QPT_RC && attr->qp_type != IBV_QPT_UD) { ++ fprintf(stderr, PFX "%s: failed to create QP, unsupported QP type: 0x%x\n", ++ __func__, attr->qp_type); + errno = EOPNOTSUPP; + return NULL; + } +@@ -1343,6 +1702,17 @@ + ibv_ctx.context); + uk_attrs = &iwvctx->uk_attrs; + ++ if (attr->srq) { ++ struct irdma_usrq *iwusrq; ++ struct verbs_srq *vsrq; ++ ++ vsrq = container_of(attr->srq, struct verbs_srq, srq); ++ iwusrq = container_of(vsrq, struct irdma_usrq, v_srq); ++ attr->cap.max_recv_sge = uk_attrs->max_hw_wq_frags; ++ attr->cap.max_recv_wr = 1; ++ info.srq_uk = &iwusrq->srq; ++ } ++ + if (attr->cap.max_send_sge > uk_attrs->max_hw_wq_frags || + attr->cap.max_recv_sge > uk_attrs->max_hw_wq_frags || + attr->cap.max_send_wr > uk_attrs->max_hw_wq_quanta || +@@ -1362,12 +1732,17 @@ + + status = irdma_uk_calc_depth_shift_sq(&info, &info.sq_depth, &info.sq_shift); + if (status) { ++ fprintf(stderr, PFX "%s: invalid SQ attributes, max_send_wr=%d max_send_sge=%d max_inline=%d\n", ++ __func__, attr->cap.max_send_wr, attr->cap.max_send_sge, ++ attr->cap.max_inline_data); + errno = status; + return NULL; + } + + status = irdma_uk_calc_depth_shift_rq(&info, &info.rq_depth, &info.rq_shift); + if (status) { ++ fprintf(stderr, PFX "%s: invalid RQ attributes, recv_wr=%d recv_sge=%d\n", ++ __func__, attr->cap.max_recv_wr, attr->cap.max_recv_sge); + errno = status; + return NULL; + } +@@ -1378,7 +1753,8 @@ + + memset(iwuqp, 0, sizeof(*iwuqp)); + +- if (pthread_spin_init(&iwuqp->lock, PTHREAD_PROCESS_PRIVATE)) ++ status = irdma_spin_init_pd(&iwuqp->lock, pd); ++ if (status) + goto err_free_qp; + + info.sq_size = info.sq_depth >> info.sq_shift; +@@ -1393,35 +1769,47 @@ + } + + info.wqe_alloc_db = (__u32 *)iwvctx->db; ++ info.sq_sigwrtrk_array = calloc(info.sq_depth, sizeof(struct irdma_sig_wr_trk_info)); ++ if (!info.sq_sigwrtrk_array) { ++ status = errno; /* preserve errno */ ++ goto err_destroy_lock; ++ } ++ + info.legacy_mode = iwvctx->legacy_mode; + info.sq_wrtrk_array = calloc(info.sq_depth, sizeof(*info.sq_wrtrk_array)); +- if (!info.sq_wrtrk_array) +- goto err_destroy_lock; ++ if (!info.sq_wrtrk_array) { ++ status = errno; /* preserve errno */ ++ goto err_free_sq_sigwrtrk; ++ } + + info.rq_wrid_array = calloc(info.rq_depth, sizeof(*info.rq_wrid_array)); +- if (!info.rq_wrid_array) ++ if (!info.rq_wrid_array) { ++ status = errno; /* preserve errno */ + goto err_free_sq_wrtrk; ++ } + + iwuqp->sq_sig_all = attr->sq_sig_all; + iwuqp->qp_type = attr->qp_type; + status = irdma_vmapped_qp(iwuqp, pd, attr, &info, iwvctx->legacy_mode); +- if (status) { +- errno = status; ++ if (status) + goto err_free_rq_wrid; +- } + + iwuqp->qp.back_qp = iwuqp; +- iwuqp->qp.lock = &iwuqp->lock; ++ iwuqp->qp.lock = &iwuqp->lock.lock; + + status = irdma_uk_qp_init(&iwuqp->qp, &info); +- if (status) { +- errno = EINVAL; ++ if (status) + goto err_free_vmap_qp; +- } + + attr->cap.max_send_wr = (info.sq_depth - IRDMA_SQ_RSVD) >> info.sq_shift; + attr->cap.max_recv_wr = (info.rq_depth - IRDMA_RQ_RSVD) >> info.rq_shift; + ++ iwuqp->qp.sq_ring.user_size = attr->cap.max_send_wr; ++ ++ pthread_mutex_lock(&sigusr1_wait_mutex); ++ list_add(&dbg_uqp_list, &iwuqp->dbg_entry); ++ pthread_mutex_unlock(&sigusr1_wait_mutex); ++ + return &iwuqp->ibv_qp; + + err_free_vmap_qp: +@@ -1431,11 +1819,15 @@ + free(info.rq_wrid_array); + err_free_sq_wrtrk: + free(info.sq_wrtrk_array); ++err_free_sq_sigwrtrk: ++ free(info.sq_sigwrtrk_array); + err_destroy_lock: +- pthread_spin_destroy(&iwuqp->lock); ++ irdma_spin_destroy(&iwuqp->lock); + err_free_qp: ++ fprintf(stderr, PFX "%s: failed to create QP\n", __func__); + free(iwuqp); + ++ errno = status; + return NULL; + } + +@@ -1465,22 +1857,23 @@ + { + struct irdma_umodify_qp_resp resp = {}; + struct ibv_modify_qp cmd = {}; +- struct irdma_umodify_qp cmd_ex = {}; +- struct irdma_uvcontext *iwctx; ++ struct irdma_modify_qp_cmd cmd_ex = {}; ++ struct irdma_uvcontext *iwvctx; + struct irdma_uqp *iwuqp; + + iwuqp = container_of(qp, struct irdma_uqp, ibv_qp); +- iwctx = container_of(qp->context, struct irdma_uvcontext, +- ibv_ctx.context); ++ iwvctx = container_of(qp->context, struct irdma_uvcontext, ++ ibv_ctx.context); + +- if (iwuqp->qp.qp_caps & IRDMA_PUSH_MODE && +- attr_mask & IBV_QP_STATE && iwctx->uk_attrs.hw_rev > IRDMA_GEN_1) { ++ if (iwuqp->qp.qp_caps & IRDMA_PUSH_MODE && attr_mask & IBV_QP_STATE && ++ iwvctx->uk_attrs.hw_rev > IRDMA_GEN_1) { + __u64 offset; +- void *map; + int ret; + + ret = ibv_cmd_modify_qp_ex(qp, attr, attr_mask, &cmd_ex.ibv_cmd, + sizeof(cmd_ex), &resp.ibv_resp, sizeof(resp)); ++ if (!ret) ++ iwuqp->qp.rd_fence_rate = resp.rd_fence_rate; + if (ret || !resp.push_valid) + return ret; + +@@ -1488,21 +1881,19 @@ + return ret; + + offset = resp.push_wqe_mmap_key; +- map = irdma_mmap(qp->context->cmd_fd, offset); +- if (map == MAP_FAILED) ++ iwuqp->qp.push_wqe_map = irdma_mmap(qp->context->cmd_fd, offset); ++ if (iwuqp->qp.push_wqe_map == MAP_FAILED) + return ret; + +- iwuqp->qp.push_wqe = map; +- + offset = resp.push_db_mmap_key; +- map = irdma_mmap(qp->context->cmd_fd, offset); +- if (map == MAP_FAILED) { +- irdma_munmap(iwuqp->qp.push_wqe); +- iwuqp->qp.push_wqe = NULL; ++ iwuqp->qp.push_db_map = irdma_mmap(qp->context->cmd_fd, offset); ++ if (iwuqp->qp.push_db_map == MAP_FAILED) { ++ irdma_munmap(iwuqp->qp.push_wqe_map); ++ fprintf(stderr, PFX "failed to map push page, errno %d\n", errno); + return ret; + } +- iwuqp->qp.push_wqe += resp.push_offset; +- iwuqp->qp.push_db = map + resp.push_offset; ++ iwuqp->qp.push_wqe = iwuqp->qp.push_wqe_map + resp.push_offset; ++ iwuqp->qp.push_db = iwuqp->qp.push_db_map + resp.push_offset; + + return ret; + } else { +@@ -1513,16 +1904,15 @@ + static void irdma_issue_flush(struct ibv_qp *qp, bool sq_flush, bool rq_flush) + { + struct ib_uverbs_ex_modify_qp_resp resp = {}; +- struct irdma_umodify_qp cmd_ex = {}; ++ struct irdma_modify_qp_cmd cmd_ex = {}; + struct ibv_qp_attr attr = {}; + + attr.qp_state = IBV_QPS_ERR; + cmd_ex.sq_flush = sq_flush; + cmd_ex.rq_flush = rq_flush; + +- ibv_cmd_modify_qp_ex(qp, &attr, IBV_QP_STATE, +- &cmd_ex.ibv_cmd, sizeof(cmd_ex), +- &resp, sizeof(resp)); ++ ibv_cmd_modify_qp_ex(qp, &attr, IBV_QP_STATE, &cmd_ex.ibv_cmd, ++ sizeof(cmd_ex), &resp, sizeof(resp)); + } + + /** +@@ -1535,12 +1925,12 @@ + struct irdma_cq_uk *ukcq = &iwucq->cq; + int ret; + +- ret = pthread_spin_lock(&iwucq->lock); ++ ret = irdma_spin_lock(&iwucq->lock); + if (ret) + return; + + irdma_uk_clean_cq(qp, ukcq); +- pthread_spin_unlock(&iwucq->lock); ++ irdma_spin_unlock(&iwucq->lock); + } + + /** +@@ -1553,7 +1943,10 @@ + int ret; + + iwuqp = container_of(qp, struct irdma_uqp, ibv_qp); +- ret = pthread_spin_destroy(&iwuqp->lock); ++ pthread_mutex_lock(&sigusr1_wait_mutex); ++ list_del(&iwuqp->dbg_entry); ++ pthread_mutex_unlock(&sigusr1_wait_mutex); ++ ret = irdma_spin_destroy(&iwuqp->lock); + if (ret) + goto err; + +@@ -1568,6 +1961,8 @@ + if (iwuqp->recv_cq && iwuqp->recv_cq != iwuqp->send_cq) + irdma_clean_cqes(&iwuqp->qp, iwuqp->recv_cq); + ++ if (iwuqp->qp.sq_sigwrtrk_array) ++ free(iwuqp->qp.sq_sigwrtrk_array); + if (iwuqp->qp.sq_wrtrk_array) + free(iwuqp->qp.sq_wrtrk_array); + if (iwuqp->qp.rq_wrid_array) +@@ -1578,10 +1973,27 @@ + return 0; + + err: ++ fprintf(stderr, PFX "%s: failed to destroy QP, status %d\n", ++ __func__, ret); + return ret; + } + + /** ++ * calc_type2_mw_stag - calculate type 2 MW stag ++ * @rkey: desired rkey of the MW ++ * @mw_rkey: type2 memory window rkey ++ * ++ * compute type2 memory window stag by taking lower 8 bits ++ * of the desired rkey and leaving 24 bits if mw->rkey unchanged ++ */ ++static inline __u32 calc_type2_mw_stag(__u32 rkey, __u32 mw_rkey) ++{ ++ const __u32 mask = 0xff; ++ ++ return (rkey & mask) | (mw_rkey & ~mask); ++} ++ ++/** + * irdma_post_send - post send wr for user application + * @ib_qp: qp to post wr + * @ib_wr: work request ptr +@@ -1595,14 +2007,14 @@ + struct irdma_uk_attrs *uk_attrs; + struct irdma_uqp *iwuqp; + bool reflush = false; +- int err; ++ int err = 0; + + iwuqp = container_of(ib_qp, struct irdma_uqp, ibv_qp); + iwvctx = container_of(ib_qp->context, struct irdma_uvcontext, + ibv_ctx.context); + uk_attrs = &iwvctx->uk_attrs; + +- err = pthread_spin_lock(&iwuqp->lock); ++ err = irdma_spin_lock(&iwuqp->lock); + if (err) + return err; + +@@ -1618,10 +2030,32 @@ + info.signaled = true; + if (ib_wr->send_flags & IBV_SEND_FENCE) + info.read_fence = true; +- if (iwuqp->send_cq->report_rtt) +- info.report_rtt = true; + + switch (ib_wr->opcode) { ++ case IBV_WR_ATOMIC_CMP_AND_SWP: ++ info.op_type = IRDMA_OP_TYPE_ATOMIC_COMPARE_AND_SWAP; ++ info.op.atomic_compare_swap.tagged_offset = ib_wr->sg_list[0].addr; ++ info.op.atomic_compare_swap.remote_tagged_offset = ++ ib_wr->wr.atomic.remote_addr; ++ info.op.atomic_compare_swap.swap_data_bytes = ++ ib_wr->wr.atomic.swap; ++ info.op.atomic_compare_swap.compare_data_bytes = ++ ib_wr->wr.atomic.compare_add; ++ info.op.atomic_compare_swap.stag = ib_wr->sg_list[0].lkey; ++ info.op.atomic_compare_swap.remote_stag = ib_wr->wr.atomic.rkey; ++ err = irdma_uk_atomic_compare_swap(&iwuqp->qp, &info, false); ++ break; ++ case IBV_WR_ATOMIC_FETCH_AND_ADD: ++ info.op_type = IRDMA_OP_TYPE_ATOMIC_FETCH_AND_ADD; ++ info.op.atomic_fetch_add.tagged_offset = ib_wr->sg_list[0].addr; ++ info.op.atomic_fetch_add.remote_tagged_offset = ++ ib_wr->wr.atomic.remote_addr; ++ info.op.atomic_fetch_add.fetch_add_data_bytes = ++ ib_wr->wr.atomic.compare_add; ++ info.op.atomic_fetch_add.stag = ib_wr->sg_list[0].lkey; ++ info.op.atomic_fetch_add.remote_stag = ib_wr->wr.atomic.rkey; ++ err = irdma_uk_atomic_fetch_add(&iwuqp->qp, &info, false); ++ break; + case IBV_WR_SEND_WITH_IMM: + if (iwuqp->qp.qp_caps & IRDMA_SEND_WITH_IMM) { + info.imm_data_valid = true; +@@ -1706,22 +2140,36 @@ + } + info.op_type = IRDMA_OP_TYPE_BIND_MW; + info.op.bind_window.mr_stag = ib_wr->bind_mw.bind_info.mr->rkey; +- info.op.bind_window.mem_window_type_1 = true; +- info.op.bind_window.mw_stag = ib_wr->bind_mw.rkey; ++ if (ib_wr->bind_mw.mw->type == IBV_MW_TYPE_1) { ++ info.op.bind_window.mem_window_type_1 = true; ++ info.op.bind_window.mw_stag = ib_wr->bind_mw.rkey; ++ } else { ++ struct verbs_mr *vmr = verbs_get_mr(ib_wr->bind_mw.bind_info.mr); ++ ++ if (vmr->access & IBV_ACCESS_ZERO_BASED) { ++ err = EINVAL; ++ break; ++ } ++ info.op.bind_window.mw_stag = ++ calc_type2_mw_stag(ib_wr->bind_mw.rkey, ib_wr->bind_mw.mw->rkey); ++ ib_wr->bind_mw.mw->rkey = info.op.bind_window.mw_stag; ++ ++ } + + if (ib_wr->bind_mw.bind_info.mw_access_flags & IBV_ACCESS_ZERO_BASED) { + info.op.bind_window.addressing_type = IRDMA_ADDR_TYPE_ZERO_BASED; + info.op.bind_window.va = NULL; + } else { + info.op.bind_window.addressing_type = IRDMA_ADDR_TYPE_VA_BASED; +- info.op.bind_window.va = +- (void *)(uintptr_t)ib_wr->bind_mw.bind_info.addr; ++ info.op.bind_window.va = (void *)(uintptr_t)ib_wr->bind_mw.bind_info.addr; + } + info.op.bind_window.bind_len = ib_wr->bind_mw.bind_info.length; + info.op.bind_window.ena_reads = + (ib_wr->bind_mw.bind_info.mw_access_flags & IBV_ACCESS_REMOTE_READ) ? 1 : 0; + info.op.bind_window.ena_writes = + (ib_wr->bind_mw.bind_info.mw_access_flags & IBV_ACCESS_REMOTE_WRITE) ? 1 : 0; ++ info.op.bind_window.remote_atomics_en = ++ (ib_wr->bind_mw.bind_info.mw_access_flags & IBV_ACCESS_REMOTE_ATOMIC) ? 1 : 0; + + err = irdma_uk_mw_bind(&iwuqp->qp, &info, false); + break; +@@ -1733,6 +2181,8 @@ + default: + /* error */ + err = EINVAL; ++ fprintf(stderr, PFX "%s: post work request failed, invalid opcode: 0x%x\n", ++ __func__, ib_wr->opcode); + break; + } + if (err) +@@ -1744,11 +2194,57 @@ + if (err) + *bad_wr = ib_wr; + +- irdma_uk_qp_post_wr(&iwuqp->qp); ++ if (!iwuqp->qp.push_db) ++ irdma_uk_qp_post_wr(&iwuqp->qp); + if (reflush) + irdma_issue_flush(ib_qp, 1, 0); + +- pthread_spin_unlock(&iwuqp->lock); ++ irdma_spin_unlock(&iwuqp->lock); ++ ++ return err; ++} ++ ++/** ++ * irdma_upost_srq - post receive wr for user application ++ * @ib_wr: work request for receive ++ * @bad_wr: bad wr caused an error ++ */ ++int irdma_upost_srq(struct ibv_srq *ibsrq, struct ibv_recv_wr *ib_wr, ++ struct ibv_recv_wr **bad_wr) ++{ ++ struct irdma_post_rq_info post_recv = {}; ++ struct irdma_usrq *iwusrq; ++ struct irdma_srq_uk *srq; ++ struct verbs_srq *vsrq; ++ int err; ++ ++ vsrq = container_of(ibsrq, struct verbs_srq, srq); ++ iwusrq = container_of(vsrq, struct irdma_usrq, v_srq); ++ srq = &iwusrq->srq; ++ ++ err = irdma_spin_lock(&iwusrq->lock); ++ if (err) ++ return err; ++ ++ while (ib_wr) { ++ if (ib_wr->num_sge > srq->max_srq_frag_cnt) { ++ *bad_wr = ib_wr; ++ err = EINVAL; ++ goto error; ++ } ++ post_recv.num_sges = ib_wr->num_sge; ++ post_recv.wr_id = ib_wr->wr_id; ++ post_recv.sg_list = ib_wr->sg_list; ++ err = irdma_uk_srq_post_receive(srq, &post_recv); ++ if (err) { ++ *bad_wr = ib_wr; ++ goto error; ++ } ++ ++ ib_wr = ib_wr->next; ++ } ++error: ++ irdma_spin_unlock(&iwusrq->lock); + + return err; + } +@@ -1767,8 +2263,12 @@ + int err; + + iwuqp = container_of(ib_qp, struct irdma_uqp, ibv_qp); ++ if (iwuqp->qp.srq_uk) { ++ *bad_wr = ib_wr; ++ return EINVAL; ++ } + +- err = pthread_spin_lock(&iwuqp->lock); ++ err = irdma_spin_lock(&iwuqp->lock); + if (err) + return err; + +@@ -1797,7 +2297,7 @@ + ib_wr = ib_wr->next; + } + error: +- pthread_spin_unlock(&iwuqp->lock); ++ irdma_spin_unlock(&iwuqp->lock); + + return err; + } +@@ -1811,13 +2311,13 @@ + { + struct irdma_uah *ah; + union ibv_gid sgid; +- struct irdma_ucreate_ah_resp resp; ++ struct irdma_ucreate_ah_resp resp = {}; + int err; + +- err = ibv_query_gid(ibpd->context, attr->port_num, attr->grh.sgid_index, +- &sgid); +- if (err) { +- errno = err; ++ if (ibv_query_gid(ibpd->context, attr->port_num, attr->grh.sgid_index, ++ &sgid)) { ++ fprintf(stderr, "irdma: Error from ibv_query_gid.\n"); ++ errno = ENOENT; + return NULL; + } + +@@ -1899,6 +2399,7 @@ + struct irdma_cqe *cq_base = NULL; + struct verbs_mr new_mr = {}; + struct irdma_ucq *iwucq; ++ bool cqe_64byte_ena; + size_t cq_size; + __u32 cq_pages; + int cqe_needed; +@@ -1912,27 +2413,21 @@ + if (!(uk_attrs->feature_flags & IRDMA_FEATURE_CQ_RESIZE)) + return EOPNOTSUPP; + +- if (cqe > IRDMA_MAX_CQ_SIZE) ++ if (cqe < uk_attrs->min_hw_cq_size || cqe > uk_attrs->max_hw_cq_size - 1) + return EINVAL; + +- cqe_needed = cqe + 1; +- if (uk_attrs->hw_rev > IRDMA_GEN_1) +- cqe_needed *= 2; +- +- if (cqe_needed < IRDMA_U_MINCQ_SIZE) +- cqe_needed = IRDMA_U_MINCQ_SIZE; ++ cqe_64byte_ena = uk_attrs->feature_flags & IRDMA_FEATURE_64_BYTE_CQE ? true : false; + ++ cqe_needed = get_cq_size(cqe, uk_attrs->hw_rev, cqe_64byte_ena); + if (cqe_needed == iwucq->cq.cq_size) + return 0; + +- cq_size = get_cq_total_bytes(cqe_needed); ++ cq_size = get_cq_total_bytes(cqe_needed, cqe_64byte_ena); + cq_pages = cq_size >> IRDMA_HW_PAGE_SHIFT; +- cq_base = irdma_alloc_hw_buf(cq_size); ++ cq_base = irdma_calloc_hw_buf(cq_size); + if (!cq_base) + return ENOMEM; + +- memset(cq_base, 0, cq_size); +- + cq_buf = malloc(sizeof(*cq_buf)); + if (!cq_buf) { + ret = ENOMEM; +@@ -1950,7 +2445,7 @@ + if (ret) + goto err_dereg_mr; + +- ret = pthread_spin_lock(&iwucq->lock); ++ ret = irdma_spin_lock(&iwucq->lock); + if (ret) + goto err_lock; + +@@ -1961,23 +2456,58 @@ + goto err_resize; + + memcpy(&cq_buf->cq, &iwucq->cq, sizeof(cq_buf->cq)); ++ cq_buf->buf_size = cq_size; + cq_buf->vmr = iwucq->vmr; + iwucq->vmr = new_mr; + irdma_uk_cq_resize(&iwucq->cq, cq_base, cqe_needed); + iwucq->verbs_cq.cq.cqe = cqe; + list_add_tail(&iwucq->resize_list, &cq_buf->list); + +- pthread_spin_unlock(&iwucq->lock); ++ irdma_spin_unlock(&iwucq->lock); + + return ret; + + err_resize: +- pthread_spin_unlock(&iwucq->lock); ++ irdma_spin_unlock(&iwucq->lock); + err_lock: + ibv_cmd_dereg_mr(&new_mr); + err_dereg_mr: + free(cq_buf); + err_buf: ++ fprintf(stderr, "failed to resize CQ cq_id=%d ret=%d\n", iwucq->cq.cq_id, ret); + irdma_free_hw_buf(cq_base, cq_size); + return ret; + } ++ ++struct ibv_td *irdma_ualloc_td(struct ibv_context *context, struct ibv_td_init_attr *init_attr) ++{ ++ struct irdma_utd *iwutd; ++ ++ if (init_attr->comp_mask) { ++ errno = EINVAL; ++ return NULL; ++ } ++ ++ iwutd = calloc(1, sizeof(*iwutd)); ++ if (!iwutd) ++ return NULL; ++ ++ iwutd->ibv_td.context = context; ++ atomic_init(&iwutd->refcount, 1); ++ ++ return &iwutd->ibv_td; ++} ++ ++int irdma_udealloc_td(struct ibv_td *ibv_td) ++{ ++ struct irdma_utd *iwutd; ++ ++ iwutd = container_of(ibv_td, struct irdma_utd, ibv_td); ++ ++ if (atomic_load(&iwutd->refcount) > 1) ++ return EBUSY; ++ ++ free(iwutd); ++ ++ return 0; ++} diff --git a/drivers/intel/irdma-1.14.33/readmefirst.txt b/drivers/intel/irdma-1.14.33/readmefirst.txt new file mode 100644 index 000000000..9343da164 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/readmefirst.txt @@ -0,0 +1,14 @@ +This release includes RDMA Linux* Drivers for Intel(R) Ethernet Network +Connections. + +The irdma driver supports devices based on the following controllers: + * Intel(R) Ethernet Network Connection X722 + * Intel(R) Ethernet Controller E810-C + * Intel(R) Ethernet Controller E810-XXV + * Intel(R) Ethernet Controllers E823 (ICX-D LCC/HCC) + +irdma-x.x.x.tgz + +Due to the continuous development of the Linux kernel, the drivers are updated +more often than the bundled releases. The latest driver can be found on +http://downloadcenter.intel.com. diff --git a/drivers/intel/irdma-1.14.33/src/irdma/Kbuild b/drivers/intel/irdma-1.14.33/src/irdma/Kbuild new file mode 100644 index 000000000..00962ac27 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/Kbuild @@ -0,0 +1,39 @@ +# SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +# Copyright (c) 2015 - 2023 Intel Corporation +# Makefile for the Intel(R) Ethernet Protocol Driver for RDMA +# +ifneq (${LINUXINCLUDE},) +LINUXINCLUDE := \ + ${INCLUDE_KCONF_HDR} \ + ${INCLUDE_AUTOCONF_HDR} \ + ${INCLUDE_COMPAT_HDR} \ + ${UTSRELEASE_HDR} \ + ${LINUXINCLUDE} +endif + +ccflags-y := -Werror -Wall -Wno-cast-function-type +obj-m += irdma.o + +irdma-objs := main.o \ + hw.o \ + cm.o \ + ctrl.o \ + hmc.o \ + pble.o \ + puda.o \ + uk.o \ + utils.o \ + verbs.o \ + uda.o \ + ws.o \ + trace.o \ + i40iw_if.o \ + i40iw_hw.o \ + ig3rdma_hw.o \ + icrdma_hw.o \ + configfs.o \ + virtchnl.o \ + irdma_kcompat.o \ + debugfs.o + +CFLAGS_trace.o = -I$(src) diff --git a/drivers/intel/irdma-1.14.33/src/irdma/cm.c b/drivers/intel/irdma-1.14.33/src/irdma/cm.c new file mode 100644 index 000000000..c1e18842c --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/cm.c @@ -0,0 +1,4500 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "main.h" +#include "trace.h" + +static void irdma_cm_post_event(struct irdma_cm_event *event); +static void irdma_disconnect_worker(struct work_struct *work); + +/** + * irdma_free_sqbuf - put back puda buffer if refcount is 0 + * @vsi: The VSI structure of the device + * @bufp: puda buffer to free + */ +void irdma_free_sqbuf(struct irdma_sc_vsi *vsi, void *bufp) +{ + struct irdma_puda_buf *buf = bufp; + struct irdma_puda_rsrc *ilq = vsi->ilq; + + if (refcount_dec_and_test(&buf->refcount)) + irdma_puda_ret_bufpool(ilq, buf); +} + +/** + * irdma_record_ird_ord - Record IRD/ORD passed in + * @cm_node: connection's node + * @conn_ird: connection IRD + * @conn_ord: connection ORD + */ +static void irdma_record_ird_ord(struct irdma_cm_node *cm_node, u32 conn_ird, + u32 conn_ord) +{ + if (conn_ird > cm_node->dev->hw_attrs.max_hw_ird) + conn_ird = cm_node->dev->hw_attrs.max_hw_ird; + + if (conn_ord > cm_node->dev->hw_attrs.max_hw_ord) + conn_ord = cm_node->dev->hw_attrs.max_hw_ord; + else if (!conn_ord && cm_node->send_rdma0_op == SEND_RDMA_READ_ZERO) + conn_ord = 1; + cm_node->ird_size = conn_ird; + cm_node->ord_size = conn_ord; +} + +/** + * irdma_copy_ip_ntohl - copy IP address from network to host + * @dst: IP address in host order + * @src: IP address in network order (big endian) + */ +void irdma_copy_ip_ntohl(u32 *dst, __be32 *src) +{ + *dst++ = ntohl(*src++); + *dst++ = ntohl(*src++); + *dst++ = ntohl(*src++); + *dst = ntohl(*src); +} + +/** + * irdma_copy_ip_htonl - copy IP address from host to network order + * @dst: IP address in network order (big endian) + * @src: IP address in host order + */ +void irdma_copy_ip_htonl(__be32 *dst, u32 *src) +{ + *dst++ = htonl(*src++); + *dst++ = htonl(*src++); + *dst++ = htonl(*src++); + *dst = htonl(*src); +} + +/** + * irdma_get_addr_info + * @cm_node: contains ip/tcp info + * @cm_info: to get a copy of the cm_node ip/tcp info + */ +static void irdma_get_addr_info(struct irdma_cm_node *cm_node, + struct irdma_cm_info *cm_info) +{ + memset(cm_info, 0, sizeof(*cm_info)); + cm_info->ipv4 = cm_node->ipv4; + cm_info->vlan_id = cm_node->vlan_id; + memcpy(cm_info->loc_addr, cm_node->loc_addr, sizeof(cm_info->loc_addr)); + memcpy(cm_info->rem_addr, cm_node->rem_addr, sizeof(cm_info->rem_addr)); + cm_info->loc_port = cm_node->loc_port; + cm_info->rem_port = cm_node->rem_port; +} + +/** + * irdma_fill_sockaddr4 - fill in addr info for IPv4 connection + * @cm_node: connection's node + * @event: upper layer's cm event + */ +static inline void irdma_fill_sockaddr4(struct irdma_cm_node *cm_node, + struct iw_cm_event *event) +{ + struct sockaddr_in *laddr = (struct sockaddr_in *)&event->local_addr; + struct sockaddr_in *raddr = (struct sockaddr_in *)&event->remote_addr; + + laddr->sin_family = AF_INET; + raddr->sin_family = AF_INET; + + laddr->sin_port = htons(cm_node->loc_port); + raddr->sin_port = htons(cm_node->rem_port); + + laddr->sin_addr.s_addr = htonl(cm_node->loc_addr[0]); + raddr->sin_addr.s_addr = htonl(cm_node->rem_addr[0]); +} + +/** + * irdma_fill_sockaddr6 - fill in addr info for IPv6 connection + * @cm_node: connection's node + * @event: upper layer's cm event + */ +static inline void irdma_fill_sockaddr6(struct irdma_cm_node *cm_node, + struct iw_cm_event *event) +{ + struct sockaddr_in6 *laddr6 = (struct sockaddr_in6 *)&event->local_addr; + struct sockaddr_in6 *raddr6 = (struct sockaddr_in6 *)&event->remote_addr; + + laddr6->sin6_family = AF_INET6; + raddr6->sin6_family = AF_INET6; + + laddr6->sin6_port = htons(cm_node->loc_port); + raddr6->sin6_port = htons(cm_node->rem_port); + + irdma_copy_ip_htonl(laddr6->sin6_addr.in6_u.u6_addr32, + cm_node->loc_addr); + irdma_copy_ip_htonl(raddr6->sin6_addr.in6_u.u6_addr32, + cm_node->rem_addr); +} + +/** + * irdma_get_cmevent_info - for cm event upcall + * @cm_node: connection's node + * @cm_id: upper layers cm struct for the event + * @event: upper layer's cm event + */ +static inline void irdma_get_cmevent_info(struct irdma_cm_node *cm_node, + struct iw_cm_id *cm_id, + struct iw_cm_event *event) +{ + memcpy(&event->local_addr, &cm_id->m_local_addr, + sizeof(event->local_addr)); + memcpy(&event->remote_addr, &cm_id->m_remote_addr, + sizeof(event->remote_addr)); + if (cm_node) { + event->private_data = cm_node->pdata_buf; + event->private_data_len = (u8)cm_node->pdata.size; + event->ird = cm_node->ird_size; + event->ord = cm_node->ord_size; + } +} + +/** + * irdma_send_cm_event - upcall cm's event handler + * @cm_node: connection's node + * @cm_id: upper layer's cm info struct + * @type: Event type to indicate + * @status: status for the event type + */ +static int irdma_send_cm_event(struct irdma_cm_node *cm_node, + struct iw_cm_id *cm_id, + enum iw_cm_event_type type, int status) +{ + struct iw_cm_event event = {}; + + event.event = type; + event.status = status; + trace_irdma_send_cm_event(cm_node, cm_id, type, status, + __builtin_return_address(0)); + + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: cm_node %p cm_id=%p state=%d accel=%d event_type=%d status=%d\n", + cm_node, cm_id, cm_node->accelerated, cm_node->state, type, + status); + + switch (type) { + case IW_CM_EVENT_CONNECT_REQUEST: + if (cm_node->ipv4) + irdma_fill_sockaddr4(cm_node, &event); + else + irdma_fill_sockaddr6(cm_node, &event); + event.provider_data = cm_node; + event.private_data = cm_node->pdata_buf; + event.private_data_len = (u8)cm_node->pdata.size; + event.ird = cm_node->ird_size; + break; + case IW_CM_EVENT_CONNECT_REPLY: + irdma_get_cmevent_info(cm_node, cm_id, &event); + break; + case IW_CM_EVENT_ESTABLISHED: + event.ird = cm_node->ird_size; + event.ord = cm_node->ord_size; + break; + case IW_CM_EVENT_DISCONNECT: + case IW_CM_EVENT_CLOSE: + /* Wait if we are in RTS but havent issued the iwcm event upcall */ + if (!cm_node->accelerated) + wait_for_completion(&cm_node->establish_comp); + break; + default: + return -EINVAL; + } + + return cm_id->event_handler(cm_id, &event); +} + +/** + * irdma_timer_list_prep - add connection nodes to a list to perform timer tasks + * @cm_core: cm's core + * @timer_list: a timer list to which cm_node will be selected + */ +static void irdma_timer_list_prep(struct irdma_cm_core *cm_core, + struct list_head *timer_list) +{ + struct irdma_cm_node *cm_node; + int bkt; + + hash_for_each_rcu(cm_core->cm_hash_tbl, bkt, cm_node, list) { + if ((cm_node->close_entry || cm_node->send_entry) && + refcount_inc_not_zero(&cm_node->refcnt)) + list_add(&cm_node->timer_entry, timer_list); + } +} + +/** + * irdma_create_event - create cm event + * @cm_node: connection's node + * @type: Event type to generate + */ +static struct irdma_cm_event *irdma_create_event(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type) +{ + struct irdma_cm_event *event; + + if (!cm_node->cm_id) + return NULL; + + event = kzalloc(sizeof(*event), GFP_ATOMIC); + + if (!event) + return NULL; + + event->type = type; + event->cm_node = cm_node; + memcpy(event->cm_info.rem_addr, cm_node->rem_addr, + sizeof(event->cm_info.rem_addr)); + memcpy(event->cm_info.loc_addr, cm_node->loc_addr, + sizeof(event->cm_info.loc_addr)); + event->cm_info.rem_port = cm_node->rem_port; + event->cm_info.loc_port = cm_node->loc_port; + event->cm_info.cm_id = cm_node->cm_id; + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: node=%p event=%p type=%u dst=%pI4 src=%pI4\n", cm_node, + event, type, event->cm_info.loc_addr, + event->cm_info.rem_addr); + trace_irdma_create_event(cm_node, type, __builtin_return_address(0)); + irdma_cm_post_event(event); + + return event; +} + +/** + * irdma_free_retrans_entry - free send entry + * @cm_node: connection's node + */ +static void irdma_free_retrans_entry(struct irdma_cm_node *cm_node) +{ + struct irdma_device *iwdev = cm_node->iwdev; + struct irdma_timer_entry *send_entry; + + send_entry = cm_node->send_entry; + if (!send_entry) + return; + + cm_node->send_entry = NULL; + irdma_free_sqbuf(&iwdev->vsi, send_entry->sqbuf); + kfree(send_entry); + refcount_dec(&cm_node->refcnt); +} + +/** + * irdma_cleanup_retrans_entry - free send entry with lock + * @cm_node: connection's node + */ +static void irdma_cleanup_retrans_entry(struct irdma_cm_node *cm_node) +{ + unsigned long flags; + + spin_lock_irqsave(&cm_node->retrans_list_lock, flags); + irdma_free_retrans_entry(cm_node); + spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags); +} + +/** + * irdma_form_ah_cm_frame - get a free packet and build frame with address handle + * @cm_node: connection's node ionfo to use in frame + * @options: pointer to options info + * @hdr: pointer mpa header + * @pdata: pointer to private data + * @flags: indicates FIN or ACK + */ +static struct irdma_puda_buf *irdma_form_ah_cm_frame(struct irdma_cm_node *cm_node, + struct irdma_kmem_info *options, + struct irdma_kmem_info *hdr, + struct irdma_mpa_priv_info *pdata, + u8 flags) +{ + struct irdma_puda_buf *sqbuf; + struct irdma_sc_vsi *vsi = &cm_node->iwdev->vsi; + u8 *buf; + struct tcphdr *tcph; + u16 pktsize; + u32 opts_len = 0; + u32 pd_len = 0; + u32 hdr_len = 0; + + if (!cm_node->ah || !cm_node->ah->ah_info.ah_valid) { + ibdev_dbg(&cm_node->iwdev->ibdev, "CM: AH invalid\n"); + return NULL; + } + + sqbuf = irdma_puda_get_bufpool(vsi->ilq); + if (!sqbuf) { + ibdev_dbg(&cm_node->iwdev->ibdev, "CM: SQ buf NULL\n"); + return NULL; + } + + sqbuf->ah_id = cm_node->ah->ah_info.ah_idx; + buf = sqbuf->mem.va; + if (options) + opts_len = (u32)options->size; + + if (hdr) + hdr_len = hdr->size; + + if (pdata) + pd_len = pdata->size; + + pktsize = sizeof(*tcph) + opts_len + hdr_len + pd_len; + + memset(buf, 0, pktsize); + + sqbuf->totallen = pktsize; + sqbuf->tcphlen = sizeof(*tcph) + opts_len; + sqbuf->scratch = cm_node; + + tcph = (struct tcphdr *)buf; + buf += sizeof(*tcph); + + tcph->source = htons(cm_node->loc_port); + tcph->dest = htons(cm_node->rem_port); + tcph->seq = htonl(cm_node->tcp_cntxt.loc_seq_num); + + if (flags & SET_ACK) { + cm_node->tcp_cntxt.loc_ack_num = cm_node->tcp_cntxt.rcv_nxt; + tcph->ack_seq = htonl(cm_node->tcp_cntxt.loc_ack_num); + tcph->ack = 1; + } else { + tcph->ack_seq = 0; + } + + if (flags & SET_SYN) { + cm_node->tcp_cntxt.loc_seq_num++; + tcph->syn = 1; + } else { + cm_node->tcp_cntxt.loc_seq_num += hdr_len + pd_len; + } + + if (flags & SET_FIN) { + cm_node->tcp_cntxt.loc_seq_num++; + tcph->fin = 1; + } + + if (flags & SET_RST) + tcph->rst = 1; + + tcph->doff = (u16)((sizeof(*tcph) + opts_len + 3) >> 2); + sqbuf->tcphlen = tcph->doff << 2; + tcph->window = htons(cm_node->tcp_cntxt.rcv_wnd); + tcph->urg_ptr = 0; + + if (opts_len) { + memcpy(buf, options->addr, opts_len); + buf += opts_len; + } + + if (hdr_len) { + memcpy(buf, hdr->addr, hdr_len); + buf += hdr_len; + } + + if (pdata && pdata->addr) + memcpy(buf, pdata->addr, pdata->size); + + refcount_set(&sqbuf->refcount, 1); + + print_hex_dump_debug("ILQ: TRANSMIT ILQ BUFFER", DUMP_PREFIX_OFFSET, + 16, 8, sqbuf->mem.va, sqbuf->totallen, false); + + return sqbuf; +} + +/** + * irdma_form_uda_cm_frame - get a free packet and build frame full tcpip packet + * @cm_node: connection's node ionfo to use in frame + * @options: pointer to options info + * @hdr: pointer mpa header + * @pdata: pointer to private data + * @flags: indicates FIN or ACK + */ +static struct irdma_puda_buf *irdma_form_uda_cm_frame(struct irdma_cm_node *cm_node, + struct irdma_kmem_info *options, + struct irdma_kmem_info *hdr, + struct irdma_mpa_priv_info *pdata, + u8 flags) +{ + struct irdma_puda_buf *sqbuf; + struct irdma_sc_vsi *vsi = &cm_node->iwdev->vsi; + u8 *buf; + + struct tcphdr *tcph; + struct iphdr *iph; + struct ipv6hdr *ip6h; + struct ethhdr *ethh; + u16 pktsize; + u16 eth_hlen = ETH_HLEN; + u32 opts_len = 0; + u32 pd_len = 0; + u32 hdr_len = 0; + + u16 vtag; + + sqbuf = irdma_puda_get_bufpool(vsi->ilq); + if (!sqbuf) + return NULL; + + buf = sqbuf->mem.va; + + if (options) + opts_len = (u32)options->size; + + if (hdr) + hdr_len = hdr->size; + + if (pdata) + pd_len = pdata->size; + + if (cm_node->vlan_id < VLAN_N_VID) + eth_hlen += 4; + + if (cm_node->ipv4) + pktsize = sizeof(*iph) + sizeof(*tcph); + else + pktsize = sizeof(*ip6h) + sizeof(*tcph); + pktsize += opts_len + hdr_len + pd_len; + + memset(buf, 0, eth_hlen + pktsize); + + sqbuf->totallen = pktsize + eth_hlen; + sqbuf->maclen = eth_hlen; + sqbuf->tcphlen = sizeof(*tcph) + opts_len; + sqbuf->scratch = cm_node; + + ethh = (struct ethhdr *)buf; + buf += eth_hlen; + + if (cm_node->do_lpb) + sqbuf->do_lpb = true; + + if (cm_node->ipv4) { + sqbuf->ipv4 = true; + + iph = (struct iphdr *)buf; + buf += sizeof(*iph); + tcph = (struct tcphdr *)buf; + buf += sizeof(*tcph); + + ether_addr_copy(ethh->h_dest, cm_node->rem_mac); + ether_addr_copy(ethh->h_source, cm_node->loc_mac); + if (cm_node->vlan_id < VLAN_N_VID) { + ((struct vlan_ethhdr *)ethh)->h_vlan_proto = + htons(ETH_P_8021Q); + vtag = (cm_node->user_pri << VLAN_PRIO_SHIFT) | + cm_node->vlan_id; + ((struct vlan_ethhdr *)ethh)->h_vlan_TCI = htons(vtag); + + ((struct vlan_ethhdr *)ethh)->h_vlan_encapsulated_proto = + htons(ETH_P_IP); + } else { + ethh->h_proto = htons(ETH_P_IP); + } + + iph->version = IPVERSION; + iph->ihl = 5; /* 5 * 4Byte words, IP headr len */ + iph->tos = cm_node->tos; + iph->tot_len = htons(pktsize); + iph->id = htons(++cm_node->tcp_cntxt.loc_id); + + iph->frag_off = htons(0x4000); + iph->ttl = 0x40; + iph->protocol = IPPROTO_TCP; + iph->saddr = htonl(cm_node->loc_addr[0]); + iph->daddr = htonl(cm_node->rem_addr[0]); + } else { + sqbuf->ipv4 = false; + ip6h = (struct ipv6hdr *)buf; + buf += sizeof(*ip6h); + tcph = (struct tcphdr *)buf; + buf += sizeof(*tcph); + + ether_addr_copy(ethh->h_dest, cm_node->rem_mac); + ether_addr_copy(ethh->h_source, cm_node->loc_mac); + if (cm_node->vlan_id < VLAN_N_VID) { + ((struct vlan_ethhdr *)ethh)->h_vlan_proto = + htons(ETH_P_8021Q); + vtag = (cm_node->user_pri << VLAN_PRIO_SHIFT) | + cm_node->vlan_id; + ((struct vlan_ethhdr *)ethh)->h_vlan_TCI = htons(vtag); + ((struct vlan_ethhdr *)ethh)->h_vlan_encapsulated_proto = + htons(ETH_P_IPV6); + } else { + ethh->h_proto = htons(ETH_P_IPV6); + } + ip6h->version = 6; + ip6h->priority = cm_node->tos >> 4; + ip6h->flow_lbl[0] = cm_node->tos << 4; + ip6h->flow_lbl[1] = 0; + ip6h->flow_lbl[2] = 0; + ip6h->payload_len = htons(pktsize - sizeof(*ip6h)); + ip6h->nexthdr = 6; + ip6h->hop_limit = 128; + irdma_copy_ip_htonl(ip6h->saddr.in6_u.u6_addr32, + cm_node->loc_addr); + irdma_copy_ip_htonl(ip6h->daddr.in6_u.u6_addr32, + cm_node->rem_addr); + } + + tcph->source = htons(cm_node->loc_port); + tcph->dest = htons(cm_node->rem_port); + tcph->seq = htonl(cm_node->tcp_cntxt.loc_seq_num); + + if (flags & SET_ACK) { + cm_node->tcp_cntxt.loc_ack_num = cm_node->tcp_cntxt.rcv_nxt; + tcph->ack_seq = htonl(cm_node->tcp_cntxt.loc_ack_num); + tcph->ack = 1; + } else { + tcph->ack_seq = 0; + } + + if (flags & SET_SYN) { + cm_node->tcp_cntxt.loc_seq_num++; + tcph->syn = 1; + } else { + cm_node->tcp_cntxt.loc_seq_num += hdr_len + pd_len; + } + + if (flags & SET_FIN) { + cm_node->tcp_cntxt.loc_seq_num++; + tcph->fin = 1; + } + + if (flags & SET_RST) + tcph->rst = 1; + + tcph->doff = (u16)((sizeof(*tcph) + opts_len + 3) >> 2); + sqbuf->tcphlen = tcph->doff << 2; + tcph->window = htons(cm_node->tcp_cntxt.rcv_wnd); + tcph->urg_ptr = 0; + + if (opts_len) { + memcpy(buf, options->addr, opts_len); + buf += opts_len; + } + + if (hdr_len) { + memcpy(buf, hdr->addr, hdr_len); + buf += hdr_len; + } + + if (pdata && pdata->addr) + memcpy(buf, pdata->addr, pdata->size); + + refcount_set(&sqbuf->refcount, 1); + + print_hex_dump_debug("ILQ: TRANSMIT ILQ BUFFER", DUMP_PREFIX_OFFSET, + 16, 8, sqbuf->mem.va, sqbuf->totallen, false); + return sqbuf; +} + +/** + * irdma_send_reset - Send RST packet + * @cm_node: connection's node + */ +int irdma_send_reset(struct irdma_cm_node *cm_node) +{ + struct irdma_puda_buf *sqbuf; + int flags = SET_RST | SET_ACK; + + trace_irdma_send_reset(cm_node, 0, __builtin_return_address(0)); + sqbuf = cm_node->cm_core->form_cm_frame(cm_node, NULL, NULL, NULL, + flags); + if (!sqbuf) + return -ENOMEM; + + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: caller: %pS cm_node %p cm_id=%p accel=%d state=%d rem_port=0x%04x, loc_port=0x%04x rem_addr=%pI4 loc_addr=%pI4\n", + __builtin_return_address(0), cm_node, cm_node->cm_id, + cm_node->accelerated, cm_node->state, cm_node->rem_port, + cm_node->loc_port, cm_node->rem_addr, cm_node->loc_addr); + + return irdma_schedule_cm_timer(cm_node, sqbuf, IRDMA_TIMER_TYPE_SEND, 0, + 1); +} + +/** + * irdma_active_open_err - send event for active side cm error + * @cm_node: connection's node + * @reset: Flag to send reset or not + */ +static void irdma_active_open_err(struct irdma_cm_node *cm_node, bool reset) +{ + trace_irdma_active_open_err(cm_node, reset, + __builtin_return_address(0)); + irdma_cleanup_retrans_entry(cm_node); + cm_node->cm_core->stats_connect_errs++; + if (reset) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: cm_node=%p state=%d\n", cm_node, + cm_node->state); + refcount_inc(&cm_node->refcnt); + irdma_send_reset(cm_node); + } + + cm_node->state = IRDMA_CM_STATE_CLOSED; + irdma_create_event(cm_node, IRDMA_CM_EVENT_ABORTED); +} + +/** + * irdma_passive_open_err - handle passive side cm error + * @cm_node: connection's node + * @reset: send reset or just free cm_node + */ +static void irdma_passive_open_err(struct irdma_cm_node *cm_node, bool reset) +{ + irdma_cleanup_retrans_entry(cm_node); + cm_node->cm_core->stats_passive_errs++; + cm_node->state = IRDMA_CM_STATE_CLOSED; + ibdev_dbg(&cm_node->iwdev->ibdev, "CM: cm_node=%p state=%d\n", + cm_node, cm_node->state); + trace_irdma_passive_open_err(cm_node, reset, + __builtin_return_address(0)); + if (reset) + irdma_send_reset(cm_node); + else + irdma_rem_ref_cm_node(cm_node); +} + +/** + * irdma_event_connect_error - to create connect error event + * @event: cm information for connect event + */ +static void irdma_event_connect_error(struct irdma_cm_event *event) +{ + struct irdma_qp *iwqp; + struct iw_cm_id *cm_id; + + cm_id = event->cm_node->cm_id; + if (!cm_id) + return; + + iwqp = cm_id->provider_data; + + if (!iwqp || !iwqp->iwdev) + return; + + iwqp->cm_id = NULL; + cm_id->provider_data = NULL; + irdma_send_cm_event(event->cm_node, cm_id, IW_CM_EVENT_CONNECT_REPLY, + -ECONNRESET); + irdma_rem_ref_cm_node(event->cm_node); +} + +/** + * irdma_process_options - process options from TCP header + * @cm_node: connection's node + * @optionsloc: point to start of options + * @optionsize: size of all options + * @syn_pkt: flag if syn packet + */ +static int irdma_process_options(struct irdma_cm_node *cm_node, u8 *optionsloc, + u32 optionsize, u32 syn_pkt) +{ + u32 tmp; + u32 offset = 0; + union all_known_options *all_options; + char got_mss_option = 0; + + while (offset < optionsize) { + all_options = (union all_known_options *)(optionsloc + offset); + switch (all_options->base.optionnum) { + case OPTION_NUM_EOL: + offset = optionsize; + break; + case OPTION_NUM_NONE: + offset += 1; + continue; + case OPTION_NUM_MSS: + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: MSS Length: %d Offset: %d Size: %d\n", + all_options->mss.len, offset, optionsize); + got_mss_option = 1; + if (all_options->mss.len != 4) + return -EINVAL; + tmp = ntohs(all_options->mss.mss); + if ((cm_node->ipv4 && + (tmp + IRDMA_MTU_TO_MSS_IPV4) < IRDMA_MIN_MTU_IPV4) || + (!cm_node->ipv4 && + (tmp + IRDMA_MTU_TO_MSS_IPV6) < IRDMA_MIN_MTU_IPV6)) + return -EINVAL; + if (tmp < cm_node->tcp_cntxt.mss) + cm_node->tcp_cntxt.mss = tmp; + break; + case OPTION_NUM_WINDOW_SCALE: + cm_node->tcp_cntxt.snd_wscale = + all_options->windowscale.shiftcount; + break; + default: + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: Unsupported TCP Option: %x\n", + all_options->base.optionnum); + break; + } + offset += all_options->base.len; + } + if (!got_mss_option && syn_pkt) + cm_node->tcp_cntxt.mss = IRDMA_CM_DEFAULT_MSS; + + return 0; +} + +/** + * irdma_handle_tcp_options - setup TCP context info after parsing TCP options + * @cm_node: connection's node + * @tcph: pointer tcp header + * @optionsize: size of options rcvd + * @passive: active or passive flag + */ +static int irdma_handle_tcp_options(struct irdma_cm_node *cm_node, + struct tcphdr *tcph, int optionsize, + int passive) +{ + u8 *optionsloc = (u8 *)&tcph[1]; + int ret; + + if (optionsize) { + ret = irdma_process_options(cm_node, optionsloc, optionsize, + (u32)tcph->syn); + if (ret) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: Node %p, Sending Reset\n", cm_node); + if (passive) + irdma_passive_open_err(cm_node, true); + else + irdma_active_open_err(cm_node, true); + return ret; + } + } + + cm_node->tcp_cntxt.snd_wnd = ntohs(tcph->window) + << cm_node->tcp_cntxt.snd_wscale; + + if (cm_node->tcp_cntxt.snd_wnd > cm_node->tcp_cntxt.max_snd_wnd) + cm_node->tcp_cntxt.max_snd_wnd = cm_node->tcp_cntxt.snd_wnd; + + return 0; +} + +/** + * irdma_build_mpa_v1 - build a MPA V1 frame + * @cm_node: connection's node + * @start_addr: address where to build frame + * @mpa_key: to do read0 or write0 + */ +static void irdma_build_mpa_v1(struct irdma_cm_node *cm_node, void *start_addr, + u8 mpa_key) +{ + struct ietf_mpa_v1 *mpa_frame = start_addr; + + switch (mpa_key) { + case MPA_KEY_REQUEST: + memcpy(mpa_frame->key, IEFT_MPA_KEY_REQ, IETF_MPA_KEY_SIZE); + break; + case MPA_KEY_REPLY: + memcpy(mpa_frame->key, IEFT_MPA_KEY_REP, IETF_MPA_KEY_SIZE); + break; + default: + break; + } + mpa_frame->flags = IETF_MPA_FLAGS_CRC; + mpa_frame->rev = cm_node->mpa_frame_rev; + mpa_frame->priv_data_len = htons(cm_node->pdata.size); +} + +/** + * irdma_build_mpa_v2 - build a MPA V2 frame + * @cm_node: connection's node + * @start_addr: buffer start address + * @mpa_key: to do read0 or write0 + */ +static void irdma_build_mpa_v2(struct irdma_cm_node *cm_node, void *start_addr, + u8 mpa_key) +{ + struct ietf_mpa_v2 *mpa_frame = start_addr; + struct ietf_rtr_msg *rtr_msg = &mpa_frame->rtr_msg; + u16 ctrl_ird, ctrl_ord; + + /* initialize the upper 5 bytes of the frame */ + irdma_build_mpa_v1(cm_node, start_addr, mpa_key); + mpa_frame->flags |= IETF_MPA_V2_FLAG; + if (cm_node->iwdev->iw_ooo) { + mpa_frame->flags |= IETF_MPA_FLAGS_MARKERS; + cm_node->rcv_mark_en = true; + } + mpa_frame->priv_data_len = cpu_to_be16(be16_to_cpu(mpa_frame->priv_data_len) + + IETF_RTR_MSG_SIZE); + + /* initialize RTR msg */ + if (cm_node->mpav2_ird_ord == IETF_NO_IRD_ORD) { + ctrl_ird = IETF_NO_IRD_ORD; + ctrl_ord = IETF_NO_IRD_ORD; + } else { + ctrl_ird = (cm_node->ird_size > IETF_NO_IRD_ORD) ? + IETF_NO_IRD_ORD : + cm_node->ird_size; + ctrl_ord = (cm_node->ord_size > IETF_NO_IRD_ORD) ? + IETF_NO_IRD_ORD : + cm_node->ord_size; + } + ctrl_ird |= IETF_PEER_TO_PEER; + + switch (mpa_key) { + case MPA_KEY_REQUEST: + ctrl_ord |= IETF_RDMA0_WRITE; + ctrl_ord |= IETF_RDMA0_READ; + break; + case MPA_KEY_REPLY: + switch (cm_node->send_rdma0_op) { + case SEND_RDMA_WRITE_ZERO: + ctrl_ord |= IETF_RDMA0_WRITE; + break; + case SEND_RDMA_READ_ZERO: + ctrl_ord |= IETF_RDMA0_READ; + break; + } + break; + default: + break; + } + rtr_msg->ctrl_ird = htons(ctrl_ird); + rtr_msg->ctrl_ord = htons(ctrl_ord); +} + +/** + * irdma_cm_build_mpa_frame - build mpa frame for mpa version 1 or version 2 + * @cm_node: connection's node + * @mpa: mpa: data buffer + * @mpa_key: to do read0 or write0 + */ +static int irdma_cm_build_mpa_frame(struct irdma_cm_node *cm_node, + struct irdma_kmem_info *mpa, u8 mpa_key) +{ + int hdr_len = 0; + + switch (cm_node->mpa_frame_rev) { + case IETF_MPA_V1: + hdr_len = sizeof(struct ietf_mpa_v1); + irdma_build_mpa_v1(cm_node, mpa->addr, mpa_key); + break; + case IETF_MPA_V2: + hdr_len = sizeof(struct ietf_mpa_v2); + irdma_build_mpa_v2(cm_node, mpa->addr, mpa_key); + break; + default: + break; + } + + return hdr_len; +} + +/** + * irdma_send_mpa_request - active node send mpa request to passive node + * @cm_node: connection's node + */ +static int irdma_send_mpa_request(struct irdma_cm_node *cm_node) +{ + struct irdma_puda_buf *sqbuf; + + cm_node->mpa_hdr.addr = &cm_node->mpa_v2_frame; + cm_node->mpa_hdr.size = irdma_cm_build_mpa_frame(cm_node, + &cm_node->mpa_hdr, + MPA_KEY_REQUEST); + if (!cm_node->mpa_hdr.size) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: mpa size = %d\n", cm_node->mpa_hdr.size); + return -EINVAL; + } + + sqbuf = cm_node->cm_core->form_cm_frame(cm_node, NULL, + &cm_node->mpa_hdr, + &cm_node->pdata, SET_ACK); + if (!sqbuf) + return -ENOMEM; + + return irdma_schedule_cm_timer(cm_node, sqbuf, IRDMA_TIMER_TYPE_SEND, 1, + 0); +} + +/** + * irdma_send_mpa_reject - + * @cm_node: connection's node + * @pdata: reject data for connection + * @plen: length of reject data + */ +static int irdma_send_mpa_reject(struct irdma_cm_node *cm_node, + const void *pdata, u8 plen) +{ + struct irdma_puda_buf *sqbuf; + struct irdma_mpa_priv_info priv_info; + + cm_node->mpa_hdr.addr = &cm_node->mpa_v2_frame; + cm_node->mpa_hdr.size = irdma_cm_build_mpa_frame(cm_node, + &cm_node->mpa_hdr, + MPA_KEY_REPLY); + + cm_node->mpa_v2_frame.flags |= IETF_MPA_FLAGS_REJECT; + priv_info.addr = pdata; + priv_info.size = plen; + + sqbuf = cm_node->cm_core->form_cm_frame(cm_node, NULL, + &cm_node->mpa_hdr, &priv_info, + SET_ACK | SET_FIN); + if (!sqbuf) + return -ENOMEM; + + cm_node->state = IRDMA_CM_STATE_FIN_WAIT1; + + return irdma_schedule_cm_timer(cm_node, sqbuf, IRDMA_TIMER_TYPE_SEND, 1, + 0); +} + +/** + * irdma_negotiate_mpa_v2_ird_ord - negotiate MPAv2 IRD/ORD + * @cm_node: connection's node + * @buf: Data pointer + */ +static int irdma_negotiate_mpa_v2_ird_ord(struct irdma_cm_node *cm_node, + u8 *buf) +{ + struct ietf_mpa_v2 *mpa_v2_frame; + struct ietf_rtr_msg *rtr_msg; + u16 ird_size; + u16 ord_size; + u16 ctrl_ord; + u16 ctrl_ird; + + mpa_v2_frame = (struct ietf_mpa_v2 *)buf; + rtr_msg = &mpa_v2_frame->rtr_msg; + + /* parse rtr message */ + ctrl_ord = ntohs(rtr_msg->ctrl_ord); + ctrl_ird = ntohs(rtr_msg->ctrl_ird); + ird_size = ctrl_ird & IETF_NO_IRD_ORD; + ord_size = ctrl_ord & IETF_NO_IRD_ORD; + + if (!(ctrl_ird & IETF_PEER_TO_PEER)) + return -EOPNOTSUPP; + + if (ird_size == IETF_NO_IRD_ORD || ord_size == IETF_NO_IRD_ORD) { + cm_node->mpav2_ird_ord = IETF_NO_IRD_ORD; + goto negotiate_done; + } + + if (cm_node->state != IRDMA_CM_STATE_MPAREQ_SENT) { + /* responder */ + if (!ord_size && (ctrl_ord & IETF_RDMA0_READ)) + cm_node->ird_size = 1; + if (cm_node->ord_size > ird_size) + cm_node->ord_size = ird_size; + } else { + /* initiator */ + if (!ird_size && (ctrl_ord & IETF_RDMA0_READ)) + /* Remote peer doesn't support RDMA0_READ */ + return -EOPNOTSUPP; + + if (cm_node->ord_size > ird_size) + cm_node->ord_size = ird_size; + + if (cm_node->ird_size < ord_size) + /* no resources available */ + return -EINVAL; + } + +negotiate_done: + if (ctrl_ord & IETF_RDMA0_READ) + cm_node->send_rdma0_op = SEND_RDMA_READ_ZERO; + else if (ctrl_ord & IETF_RDMA0_WRITE) + cm_node->send_rdma0_op = SEND_RDMA_WRITE_ZERO; + else + /* Not supported RDMA0 operation */ + return -EOPNOTSUPP; + + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: MPAV2 Negotiated ORD: %d, IRD: %d\n", + cm_node->ord_size, cm_node->ird_size); + trace_irdma_negotiate_mpa_v2(cm_node); + return 0; +} + +/** + * irdma_parse_mpa - process an IETF MPA frame + * @cm_node: connection's node + * @buf: Data pointer + * @type: to return accept or reject + * @len: Len of mpa buffer + */ +static int irdma_parse_mpa(struct irdma_cm_node *cm_node, u8 *buf, u32 *type, + u32 len) +{ + struct ietf_mpa_v1 *mpa_frame; + int mpa_hdr_len, priv_data_len, ret; + + *type = IRDMA_MPA_REQUEST_ACCEPT; + + if (len < sizeof(*mpa_frame)) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: ietf buffer small (%x)\n", len); + return -EINVAL; + } + + mpa_frame = (struct ietf_mpa_v1 *)buf; + mpa_hdr_len = sizeof(*mpa_frame); + priv_data_len = ntohs(mpa_frame->priv_data_len); + + if (priv_data_len > IETF_MAX_PRIV_DATA_LEN) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: private_data too big %d\n", priv_data_len); + return -EOVERFLOW; + } + + if (mpa_frame->rev != IETF_MPA_V1 && mpa_frame->rev != IETF_MPA_V2) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: unsupported mpa rev = %d\n", mpa_frame->rev); + return -EINVAL; + } + + if (mpa_frame->rev > cm_node->mpa_frame_rev) { + ibdev_dbg(&cm_node->iwdev->ibdev, "CM: rev %d\n", + mpa_frame->rev); + return -EINVAL; + } + + cm_node->mpa_frame_rev = mpa_frame->rev; + if (cm_node->state != IRDMA_CM_STATE_MPAREQ_SENT) { + if (memcmp(mpa_frame->key, IEFT_MPA_KEY_REQ, + IETF_MPA_KEY_SIZE)) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: Unexpected MPA Key received\n"); + return -EINVAL; + } + } else { + if (memcmp(mpa_frame->key, IEFT_MPA_KEY_REP, + IETF_MPA_KEY_SIZE)) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: Unexpected MPA Key received\n"); + return -EINVAL; + } + } + + if (priv_data_len + mpa_hdr_len > len) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: ietf buffer len(%x + %x != %x)\n", + priv_data_len, mpa_hdr_len, len); + return -EOVERFLOW; + } + + if (len > IRDMA_MAX_CM_BUF) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: ietf buffer large len = %d\n", len); + return -EOVERFLOW; + } + + switch (mpa_frame->rev) { + case IETF_MPA_V2: + mpa_hdr_len += IETF_RTR_MSG_SIZE; + ret = irdma_negotiate_mpa_v2_ird_ord(cm_node, buf); + if (ret) + return ret; + break; + case IETF_MPA_V1: + default: + break; + } + + memcpy(cm_node->pdata_buf, buf + mpa_hdr_len, priv_data_len); + cm_node->pdata.size = priv_data_len; + + if (mpa_frame->flags & IETF_MPA_FLAGS_REJECT) + *type = IRDMA_MPA_REQUEST_REJECT; + + if (mpa_frame->flags & IETF_MPA_FLAGS_MARKERS) + cm_node->snd_mark_en = true; + + return 0; +} + +/** + * irdma_schedule_cm_timer + * @cm_node: connection's node + * @sqbuf: buffer to send + * @type: if it is send or close + * @send_retrans: if rexmits to be done + * @close_when_complete: is cm_node to be removed + * + * note - cm_node needs to be protected before calling this. Encase in: + * irdma_rem_ref_cm_node(cm_core, cm_node); + * irdma_schedule_cm_timer(...) + * refcount_inc(&cm_node->refcnt); + */ +int irdma_schedule_cm_timer(struct irdma_cm_node *cm_node, + struct irdma_puda_buf *sqbuf, + enum irdma_timer_type type, int send_retrans, + int close_when_complete) +{ + struct irdma_sc_vsi *vsi = &cm_node->iwdev->vsi; + struct irdma_cm_core *cm_core = cm_node->cm_core; + struct irdma_timer_entry *new_send; + u32 was_timer_set; + unsigned long flags; + + new_send = kzalloc(sizeof(*new_send), GFP_ATOMIC); + if (!new_send) { + if (type != IRDMA_TIMER_TYPE_CLOSE) + irdma_free_sqbuf(vsi, sqbuf); + return -ENOMEM; + } + + new_send->retrycount = IRDMA_DEFAULT_RETRYS; + new_send->retranscount = IRDMA_DEFAULT_RETRANS; + new_send->sqbuf = sqbuf; + new_send->timetosend = jiffies; + new_send->type = type; + new_send->send_retrans = send_retrans; + new_send->close_when_complete = close_when_complete; + + if (type == IRDMA_TIMER_TYPE_CLOSE) { + new_send->timetosend += (HZ / 10); + if (cm_node->close_entry) { + kfree(new_send); + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: already close entry\n"); + return -EINVAL; + } + + cm_node->close_entry = new_send; + } else { /* type == IRDMA_TIMER_TYPE_SEND */ + spin_lock_irqsave(&cm_node->retrans_list_lock, flags); + cm_node->send_entry = new_send; + refcount_inc(&cm_node->refcnt); + spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags); + new_send->timetosend = jiffies + IRDMA_RETRY_TIMEOUT; + + refcount_inc(&sqbuf->refcount); + irdma_puda_send_buf(vsi->ilq, sqbuf); + if (!send_retrans) { + irdma_cleanup_retrans_entry(cm_node); + if (close_when_complete) + irdma_rem_ref_cm_node(cm_node); + return 0; + } + } + + spin_lock_irqsave(&cm_core->ht_lock, flags); + was_timer_set = timer_pending(&cm_core->tcp_timer); + + if (!was_timer_set) { + cm_core->tcp_timer.expires = new_send->timetosend; + add_timer(&cm_core->tcp_timer); + } + spin_unlock_irqrestore(&cm_core->ht_lock, flags); + + return 0; +} + +/** + * irdma_retrans_expired - Could not rexmit the packet + * @cm_node: connection's node + */ +static void irdma_retrans_expired(struct irdma_cm_node *cm_node) +{ + enum irdma_cm_node_state state = cm_node->state; + + cm_node->state = IRDMA_CM_STATE_CLOSED; + switch (state) { + case IRDMA_CM_STATE_SYN_RCVD: + case IRDMA_CM_STATE_CLOSING: + irdma_rem_ref_cm_node(cm_node); + break; + case IRDMA_CM_STATE_FIN_WAIT1: + case IRDMA_CM_STATE_LAST_ACK: + irdma_send_reset(cm_node); + break; + default: + refcount_inc(&cm_node->refcnt); + irdma_send_reset(cm_node); + irdma_create_event(cm_node, IRDMA_CM_EVENT_ABORTED); + break; + } +} + +/** + * irdma_handle_close_entry - for handling retry/timeouts + * @cm_node: connection's node + * @rem_node: flag for remove cm_node + */ +static void irdma_handle_close_entry(struct irdma_cm_node *cm_node, + u32 rem_node) +{ + struct irdma_timer_entry *close_entry = cm_node->close_entry; + struct irdma_qp *iwqp; + unsigned long flags; + + if (!close_entry) + return; + iwqp = (struct irdma_qp *)close_entry->sqbuf; + if (iwqp) { + spin_lock_irqsave(&iwqp->lock, flags); + if (iwqp->cm_id) { + iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSED; + iwqp->hw_iwarp_state = IRDMA_QP_STATE_ERROR; + iwqp->last_aeq = IRDMA_AE_RESET_SENT; + iwqp->ibqp_state = IB_QPS_ERR; + spin_unlock_irqrestore(&iwqp->lock, flags); + irdma_cm_disconn(iwqp); + } else { + spin_unlock_irqrestore(&iwqp->lock, flags); + } + } else if (rem_node) { + /* TIME_WAIT state */ + irdma_rem_ref_cm_node(cm_node); + } + + kfree(close_entry); + cm_node->close_entry = NULL; +} + +/** + * irdma_cm_timer_tick - system's timer expired callback + * @t: Pointer to timer_list + */ +static void irdma_cm_timer_tick(struct timer_list *t) +{ + unsigned long nexttimeout = jiffies + IRDMA_LONG_TIME; + struct irdma_cm_node *cm_node; + struct irdma_timer_entry *send_entry, *close_entry; + struct list_head *list_core_temp; + struct list_head *list_node; + struct irdma_cm_core *cm_core = from_timer(cm_core, t, tcp_timer); + struct irdma_sc_vsi *vsi; + u32 settimer = 0; + unsigned long timetosend; + unsigned long flags; + struct list_head timer_list; + + INIT_LIST_HEAD(&timer_list); + + rcu_read_lock(); + irdma_timer_list_prep(cm_core, &timer_list); + rcu_read_unlock(); + + list_for_each_safe (list_node, list_core_temp, &timer_list) { + cm_node = container_of(list_node, struct irdma_cm_node, + timer_entry); + close_entry = cm_node->close_entry; + + if (close_entry) { + if (time_after(close_entry->timetosend, jiffies)) { + if (nexttimeout > close_entry->timetosend || + !settimer) { + nexttimeout = close_entry->timetosend; + settimer = 1; + } + } else { + irdma_handle_close_entry(cm_node, 1); + } + } + + spin_lock_irqsave(&cm_node->retrans_list_lock, flags); + + send_entry = cm_node->send_entry; + if (!send_entry) + goto done; + if (time_after(send_entry->timetosend, jiffies)) { + if (cm_node->state != IRDMA_CM_STATE_OFFLOADED) { + if (nexttimeout > send_entry->timetosend || + !settimer) { + nexttimeout = send_entry->timetosend; + settimer = 1; + } + } else { + irdma_free_retrans_entry(cm_node); + } + goto done; + } + + if (cm_node->state == IRDMA_CM_STATE_OFFLOADED || + cm_node->state == IRDMA_CM_STATE_CLOSED) { + irdma_free_retrans_entry(cm_node); + goto done; + } + + if (!send_entry->retranscount || !send_entry->retrycount) { + irdma_free_retrans_entry(cm_node); + + spin_unlock_irqrestore(&cm_node->retrans_list_lock, + flags); + irdma_retrans_expired(cm_node); + cm_node->state = IRDMA_CM_STATE_CLOSED; + spin_lock_irqsave(&cm_node->retrans_list_lock, flags); + goto done; + } + spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags); + + vsi = &cm_node->iwdev->vsi; + if (!cm_node->ack_rcvd) { + refcount_inc(&send_entry->sqbuf->refcount); + irdma_puda_send_buf(vsi->ilq, send_entry->sqbuf); + cm_node->cm_core->stats_pkt_retrans++; + } + + spin_lock_irqsave(&cm_node->retrans_list_lock, flags); + if (send_entry->send_retrans) { + send_entry->retranscount--; + timetosend = (IRDMA_RETRY_TIMEOUT << + (IRDMA_DEFAULT_RETRANS - + send_entry->retranscount)); + + send_entry->timetosend = jiffies + + min(timetosend, IRDMA_MAX_TIMEOUT); + if (nexttimeout > send_entry->timetosend || !settimer) { + nexttimeout = send_entry->timetosend; + settimer = 1; + } + } else { + int close_when_complete; + + close_when_complete = send_entry->close_when_complete; + irdma_free_retrans_entry(cm_node); + if (close_when_complete) + irdma_rem_ref_cm_node(cm_node); + } +done: + spin_unlock_irqrestore(&cm_node->retrans_list_lock, flags); + irdma_rem_ref_cm_node(cm_node); + } + + if (settimer) { + spin_lock_irqsave(&cm_core->ht_lock, flags); + if (!timer_pending(&cm_core->tcp_timer)) { + cm_core->tcp_timer.expires = nexttimeout; + add_timer(&cm_core->tcp_timer); + } + spin_unlock_irqrestore(&cm_core->ht_lock, flags); + } +} + +/** + * irdma_send_syn - send SYN packet + * @cm_node: connection's node + * @sendack: flag to set ACK bit or not + */ +int irdma_send_syn(struct irdma_cm_node *cm_node, u32 sendack) +{ + struct irdma_puda_buf *sqbuf; + int flags = SET_SYN; + char optionsbuf[sizeof(struct option_mss) + + sizeof(struct option_windowscale) + + sizeof(struct option_base) + TCP_OPTIONS_PADDING]; + struct irdma_kmem_info opts; + int optionssize = 0; + /* Sending MSS option */ + union all_known_options *options; + + opts.addr = optionsbuf; + if (!cm_node) + return -EINVAL; + + options = (union all_known_options *)&optionsbuf[optionssize]; + options->mss.optionnum = OPTION_NUM_MSS; + options->mss.len = sizeof(struct option_mss); + options->mss.mss = htons(cm_node->tcp_cntxt.mss); + optionssize += sizeof(struct option_mss); + + options = (union all_known_options *)&optionsbuf[optionssize]; + options->windowscale.optionnum = OPTION_NUM_WINDOW_SCALE; + options->windowscale.len = sizeof(struct option_windowscale); + options->windowscale.shiftcount = cm_node->tcp_cntxt.rcv_wscale; + optionssize += sizeof(struct option_windowscale); + options = (union all_known_options *)&optionsbuf[optionssize]; + options->eol = OPTION_NUM_EOL; + optionssize += 1; + + if (sendack) + flags |= SET_ACK; + + opts.size = optionssize; + + sqbuf = cm_node->cm_core->form_cm_frame(cm_node, &opts, NULL, NULL, + flags); + if (!sqbuf) + return -ENOMEM; + + return irdma_schedule_cm_timer(cm_node, sqbuf, IRDMA_TIMER_TYPE_SEND, 1, + 0); +} + +/** + * irdma_send_ack - Send ACK packet + * @cm_node: connection's node + */ +void irdma_send_ack(struct irdma_cm_node *cm_node) +{ + struct irdma_puda_buf *sqbuf; + struct irdma_sc_vsi *vsi = &cm_node->iwdev->vsi; + + sqbuf = cm_node->cm_core->form_cm_frame(cm_node, NULL, NULL, NULL, + SET_ACK); + if (sqbuf) + irdma_puda_send_buf(vsi->ilq, sqbuf); +} + +/** + * irdma_send_fin - Send FIN pkt + * @cm_node: connection's node + */ +static int irdma_send_fin(struct irdma_cm_node *cm_node) +{ + struct irdma_puda_buf *sqbuf; + + sqbuf = cm_node->cm_core->form_cm_frame(cm_node, NULL, NULL, NULL, + SET_ACK | SET_FIN); + if (!sqbuf) + return -ENOMEM; + + return irdma_schedule_cm_timer(cm_node, sqbuf, IRDMA_TIMER_TYPE_SEND, 1, + 0); +} + +/** + * irdma_find_listener - find a cm node listening on this addr-port pair + * @cm_core: cm's core + * @dst_addr: listener ip addr + * @ipv4: flag indicating IPv4 when true + * @dst_port: listener tcp port num + * @vlan_id: virtual LAN ID + * @listener_state: state to match with listen node's + */ +static struct irdma_cm_listener * +irdma_find_listener(struct irdma_cm_core *cm_core, u32 *dst_addr, bool ipv4, u16 dst_port, + u16 vlan_id, enum irdma_cm_listener_state listener_state) +{ + struct irdma_cm_listener *listen_node; + static const u32 ip_zero[4] = { 0, 0, 0, 0 }; + u32 listen_addr[4]; + u16 listen_port; + unsigned long flags; + + /* walk list and find cm_node associated with this session ID */ + spin_lock_irqsave(&cm_core->listen_list_lock, flags); + list_for_each_entry(listen_node, &cm_core->listen_list, list) { + memcpy(listen_addr, listen_node->loc_addr, sizeof(listen_addr)); + listen_port = listen_node->loc_port; + if (listen_node->ipv4 != ipv4 || listen_port != dst_port || + !(listener_state & listen_node->listener_state)) + continue; + /* compare node pair, return node handle if a match */ + if (!memcmp(listen_addr, ip_zero, sizeof(listen_addr)) || + (!memcmp(listen_addr, dst_addr, sizeof(listen_addr)) && + vlan_id == listen_node->vlan_id)) { + refcount_inc(&listen_node->refcnt); + spin_unlock_irqrestore(&cm_core->listen_list_lock, + flags); + trace_irdma_find_listener(listen_node); + return listen_node; + } + } + spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); + + return NULL; +} + +/** + * irdma_del_multiple_qhash - Remove qhash and child listens + * @iwdev: iWarp device + * @cm_info: CM info for parent listen node + * @cm_parent_listen_node: The parent listen node + */ +static int irdma_del_multiple_qhash(struct irdma_device *iwdev, + struct irdma_cm_info *cm_info, + struct irdma_cm_listener *cm_parent_listen_node) +{ + struct irdma_cm_listener *child_listen_node; + struct list_head *pos, *tpos; + unsigned long flags; + int ret = -EINVAL; + + spin_lock_irqsave(&iwdev->cm_core.listen_list_lock, flags); + list_for_each_safe (pos, tpos, + &cm_parent_listen_node->child_listen_list) { + child_listen_node = list_entry(pos, struct irdma_cm_listener, + child_listen_list); + if (child_listen_node->ipv4) + ibdev_dbg(&iwdev->ibdev, + "CM: removing child listen for IP=%pI4, port=%d, vlan=%d\n", + child_listen_node->loc_addr, + child_listen_node->loc_port, + child_listen_node->vlan_id); + else + ibdev_dbg(&iwdev->ibdev, + "CM: removing child listen for IP=%pI6, port=%d, vlan=%d\n", + child_listen_node->loc_addr, + child_listen_node->loc_port, + child_listen_node->vlan_id); + trace_irdma_del_multiple_qhash(child_listen_node); + list_del(pos); + memcpy(cm_info->loc_addr, child_listen_node->loc_addr, + sizeof(cm_info->loc_addr)); + cm_info->vlan_id = child_listen_node->vlan_id; + if (child_listen_node->qhash_set) { + ret = irdma_manage_qhash(iwdev, cm_info, + IRDMA_QHASH_TYPE_TCP_SYN, + IRDMA_QHASH_MANAGE_TYPE_DELETE, + NULL, false); + child_listen_node->qhash_set = false; + } else { + ret = 0; + } + ibdev_dbg(&iwdev->ibdev, + "CM: Child listen node freed = %p\n", + child_listen_node); + kfree(child_listen_node); + cm_parent_listen_node->cm_core->stats_listen_nodes_destroyed++; + } + spin_unlock_irqrestore(&iwdev->cm_core.listen_list_lock, flags); + + return ret; +} + +static u8 irdma_iw_get_vlan_prio(u32 *loc_addr, u8 prio, bool ipv4) +{ + struct net_device *ndev = NULL; + + rcu_read_lock(); + if (ipv4) { + ndev = ip_dev_find(&init_net, htonl(loc_addr[0])); + } else { + struct net_device *ip_dev; + struct in6_addr laddr6; + + irdma_copy_ip_htonl(laddr6.in6_u.u6_addr32, loc_addr); + + for_each_netdev_rcu (&init_net, ip_dev) { + if (ipv6_chk_addr(&init_net, &laddr6, ip_dev, 1)) { + ndev = ip_dev; + break; + } + } + } + + if (!ndev) + goto done; + if (is_vlan_dev(ndev)) + prio = (vlan_dev_get_egress_qos_mask(ndev, prio) & VLAN_PRIO_MASK) + >> VLAN_PRIO_SHIFT; + if (ipv4) + dev_put(ndev); +done: + rcu_read_unlock(); + return prio; +} + +/** + * irdma_get_vlan_mac_ipv6 - Get the vlan and mac for an IPv6 + * address + * @addr: local IPv6 address + * @vlan_id: vlan id for the given IPv6 address + * @mac: mac address for the given IPv6 address + * + * Returns the net_device of the IPv6 address and also sets the + * vlan id and mac for that address. + */ +void irdma_get_vlan_mac_ipv6(u32 *addr, u16 *vlan_id, u8 *mac) +{ + struct net_device *ip_dev = NULL; + struct in6_addr laddr6; + + irdma_copy_ip_htonl(laddr6.in6_u.u6_addr32, addr); + if (vlan_id) + *vlan_id = 0xFFFF; /* Match rdma_vlan_dev_vlan_id() */ + if (mac) + eth_zero_addr(mac); + + rcu_read_lock(); + for_each_netdev_rcu (&init_net, ip_dev) { + if (ipv6_chk_addr(&init_net, &laddr6, ip_dev, 1)) { + if (vlan_id) + *vlan_id = rdma_vlan_dev_vlan_id(ip_dev); + if (ip_dev->dev_addr && mac) + ether_addr_copy(mac, ip_dev->dev_addr); + break; + } + } + rcu_read_unlock(); +} + +/** + * irdma_get_vlan_ipv4 - Returns the vlan_id for IPv4 address + * @addr: local IPv4 address + */ +u16 irdma_get_vlan_ipv4(u32 *addr) +{ + struct net_device *netdev; + u16 vlan_id = 0xFFFF; + + netdev = ip_dev_find(&init_net, htonl(addr[0])); + if (netdev) { + vlan_id = rdma_vlan_dev_vlan_id(netdev); + dev_put(netdev); + } + + return vlan_id; +} + +/** + * irdma_add_mqh_6 - Adds multiple qhashes for IPv6 + * @iwdev: iWarp device + * @cm_info: CM info for parent listen node + * @cm_parent_listen_node: The parent listen node + * + * Adds a qhash and a child listen node for every IPv6 address + * on the adapter and adds the associated qhash filter + */ +static int irdma_add_mqh_6(struct irdma_device *iwdev, + struct irdma_cm_info *cm_info, + struct irdma_cm_listener *cm_parent_listen_node) +{ + struct net_device *ip_dev; + struct inet6_dev *idev; + struct inet6_ifaddr *ifp, *tmp; + struct irdma_cm_listener *child_listen_node; + unsigned long flags; + int ret = 0; + + rtnl_lock(); + for_each_netdev(&init_net, ip_dev) { + if (!(ip_dev->flags & IFF_UP)) + continue; + + if (((rdma_vlan_dev_vlan_id(ip_dev) >= VLAN_N_VID) || + (rdma_vlan_dev_real_dev(ip_dev) != iwdev->netdev)) && + ip_dev != iwdev->netdev) + continue; + + idev = __in6_dev_get(ip_dev); + if (!idev) { + ibdev_dbg(&iwdev->ibdev, "CM: idev == NULL\n"); + break; + } + list_for_each_entry_safe (ifp, tmp, &idev->addr_list, if_list) { + ibdev_dbg(&iwdev->ibdev, "CM: IP=%pI6, vlan_id=%d, MAC=%pM\n", + &ifp->addr, rdma_vlan_dev_vlan_id(ip_dev), + ip_dev->dev_addr); + child_listen_node = kzalloc(sizeof(*child_listen_node), GFP_KERNEL); + if (!child_listen_node) { + ibdev_dbg(&iwdev->ibdev, "CM: listener memory allocation\n"); + ret = -ENOMEM; + goto exit; + } + + memcpy(child_listen_node, cm_parent_listen_node, + sizeof(*child_listen_node)); + cm_info->vlan_id = rdma_vlan_dev_vlan_id(ip_dev); + child_listen_node->vlan_id = cm_info->vlan_id; + irdma_copy_ip_ntohl(child_listen_node->loc_addr, + ifp->addr.in6_u.u6_addr32); + memcpy(cm_info->loc_addr, child_listen_node->loc_addr, + sizeof(cm_info->loc_addr)); + if (!iwdev->vsi.dscp_mode) + cm_info->user_pri = + irdma_iw_get_vlan_prio(child_listen_node->loc_addr, + cm_info->user_pri, + false); + ret = irdma_manage_qhash(iwdev, cm_info, + IRDMA_QHASH_TYPE_TCP_SYN, + IRDMA_QHASH_MANAGE_TYPE_ADD, + NULL, true); + if (ret) { + kfree(child_listen_node); + continue; + } + + trace_irdma_add_mqh_6(iwdev, child_listen_node, + ip_dev->dev_addr); + + child_listen_node->qhash_set = true; + spin_lock_irqsave(&iwdev->cm_core.listen_list_lock, flags); + list_add(&child_listen_node->child_listen_list, + &cm_parent_listen_node->child_listen_list); + spin_unlock_irqrestore(&iwdev->cm_core.listen_list_lock, flags); + cm_parent_listen_node->cm_core->stats_listen_nodes_created++; + } + } +exit: + rtnl_unlock(); + + return ret; +} + +/** + * irdma_add_mqh_4 - Adds multiple qhashes for IPv4 + * @iwdev: iWarp device + * @cm_info: CM info for parent listen node + * @cm_parent_listen_node: The parent listen node + * + * Adds a qhash and a child listen node for every IPv4 address + * on the adapter and adds the associated qhash filter + */ +static int irdma_add_mqh_4(struct irdma_device *iwdev, + struct irdma_cm_info *cm_info, + struct irdma_cm_listener *cm_parent_listen_node) +{ + struct net_device *ip_dev; + struct in_device *idev; + struct irdma_cm_listener *child_listen_node; + unsigned long flags; +#ifdef IN_IFADDR + const struct in_ifaddr *ifa; +#endif + int ret = 0; + + rtnl_lock(); + for_each_netdev(&init_net, ip_dev) { + if (!(ip_dev->flags & IFF_UP)) + continue; + + if (((rdma_vlan_dev_vlan_id(ip_dev) >= VLAN_N_VID) || + (rdma_vlan_dev_real_dev(ip_dev) != iwdev->netdev)) && + ip_dev != iwdev->netdev) + continue; + + idev = in_dev_get(ip_dev); + if (!idev) + continue; +#ifdef IN_IFADDR + in_dev_for_each_ifa_rtnl(ifa, idev) { +#elif defined(FOR_IFA) + for_ifa(idev) { +#endif + ibdev_dbg(&iwdev->ibdev, + "CM: Allocating child CM Listener forIP=%pI4, vlan_id=%d, MAC=%pM\n", + &ifa->ifa_address, rdma_vlan_dev_vlan_id(ip_dev), + ip_dev->dev_addr); + child_listen_node = kzalloc(sizeof(*child_listen_node), GFP_KERNEL); + cm_parent_listen_node->cm_core->stats_listen_nodes_created++; + if (!child_listen_node) { + ibdev_dbg(&iwdev->ibdev, "CM: listener memory allocation\n"); + in_dev_put(idev); + ret = -ENOMEM; + goto exit; + } + + memcpy(child_listen_node, cm_parent_listen_node, + sizeof(*child_listen_node)); + child_listen_node->vlan_id = rdma_vlan_dev_vlan_id(ip_dev); + cm_info->vlan_id = child_listen_node->vlan_id; + child_listen_node->loc_addr[0] = + ntohl(ifa->ifa_address); + memcpy(cm_info->loc_addr, child_listen_node->loc_addr, + sizeof(cm_info->loc_addr)); + if (!iwdev->vsi.dscp_mode) + cm_info->user_pri = + irdma_iw_get_vlan_prio(child_listen_node->loc_addr, + cm_info->user_pri, + true); + ret = irdma_manage_qhash(iwdev, cm_info, + IRDMA_QHASH_TYPE_TCP_SYN, + IRDMA_QHASH_MANAGE_TYPE_ADD, + NULL, true); + if (ret) { + kfree(child_listen_node); + cm_parent_listen_node->cm_core + ->stats_listen_nodes_created--; + continue; + } + + trace_irdma_add_mqh_4(iwdev, child_listen_node, + ip_dev->dev_addr); + + child_listen_node->qhash_set = true; + spin_lock_irqsave(&iwdev->cm_core.listen_list_lock, + flags); + list_add(&child_listen_node->child_listen_list, + &cm_parent_listen_node->child_listen_list); + spin_unlock_irqrestore(&iwdev->cm_core.listen_list_lock, flags); + } +#ifdef FOR_IFA + endfor_ifa(idev); +#endif + in_dev_put(idev); + } +exit: + rtnl_unlock(); + + return ret; +} + +/** + * irdma_add_mqh - Adds multiple qhashes + * @iwdev: iWarp device + * @cm_info: CM info for parent listen node + * @cm_listen_node: The parent listen node + */ +static int irdma_add_mqh(struct irdma_device *iwdev, + struct irdma_cm_info *cm_info, + struct irdma_cm_listener *cm_listen_node) +{ + if (cm_info->ipv4) + return irdma_add_mqh_4(iwdev, cm_info, cm_listen_node); + else + return irdma_add_mqh_6(iwdev, cm_info, cm_listen_node); +} + +/** + * irdma_reset_list_prep - add connection nodes slated for reset to list + * @cm_core: cm's core + * @listener: pointer to listener node + * @reset_list: a list to which cm_node will be selected + */ +static void irdma_reset_list_prep(struct irdma_cm_core *cm_core, + struct irdma_cm_listener *listener, + struct list_head *reset_list) +{ + struct irdma_cm_node *cm_node; + int bkt; + + hash_for_each_rcu(cm_core->cm_hash_tbl, bkt, cm_node, list) { + if (cm_node->listener == listener && + !cm_node->accelerated && + refcount_inc_not_zero(&cm_node->refcnt)) + list_add(&cm_node->reset_entry, reset_list); + } +} + +/** + * irdma_dec_refcnt_listen - delete listener and associated cm nodes + * @cm_core: cm's core + * @listener: pointer to listener node + * @free_hanging_nodes: to free associated cm_nodes + * @apbvt_del: flag to delete the apbvt + */ +static int irdma_dec_refcnt_listen(struct irdma_cm_core *cm_core, + struct irdma_cm_listener *listener, + int free_hanging_nodes, bool apbvt_del) +{ + struct list_head *list_pos; + struct list_head *list_temp; + struct irdma_cm_node *cm_node; + struct list_head reset_list; + struct irdma_cm_info nfo; + enum irdma_cm_node_state old_state; + unsigned long flags; + int err; + + trace_irdma_dec_refcnt_listen(listener, __builtin_return_address(0)); + /* free non-accelerated child nodes for this listener */ + INIT_LIST_HEAD(&reset_list); + if (free_hanging_nodes) { + rcu_read_lock(); + irdma_reset_list_prep(cm_core, listener, &reset_list); + rcu_read_unlock(); + } + + list_for_each_safe (list_pos, list_temp, &reset_list) { + cm_node = container_of(list_pos, struct irdma_cm_node, + reset_entry); + if (cm_node->state >= IRDMA_CM_STATE_FIN_WAIT1) { + irdma_rem_ref_cm_node(cm_node); + continue; + } + + irdma_cleanup_retrans_entry(cm_node); + err = irdma_send_reset(cm_node); + if (err) { + cm_node->state = IRDMA_CM_STATE_CLOSED; + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: send reset failed\n"); + } else { + old_state = cm_node->state; + cm_node->state = IRDMA_CM_STATE_LISTENER_DESTROYED; + if (old_state != IRDMA_CM_STATE_MPAREQ_RCVD) + irdma_rem_ref_cm_node(cm_node); + } + } + + if (refcount_dec_and_test(&listener->refcnt)) { + spin_lock_irqsave(&cm_core->listen_list_lock, flags); + list_del(&listener->list); + spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); + + if (apbvt_del) + irdma_del_apbvt(listener->iwdev, + listener->apbvt_entry); + memcpy(nfo.loc_addr, listener->loc_addr, sizeof(nfo.loc_addr)); + nfo.loc_port = listener->loc_port; + nfo.ipv4 = listener->ipv4; + nfo.vlan_id = listener->vlan_id; + nfo.user_pri = listener->user_pri; + nfo.qh_qpid = listener->iwdev->vsi.ilq->qp_id; + + if (!list_empty(&listener->child_listen_list)) { + irdma_del_multiple_qhash(listener->iwdev, &nfo, + listener); + } else { + if (listener->qhash_set) + irdma_manage_qhash(listener->iwdev, + &nfo, + IRDMA_QHASH_TYPE_TCP_SYN, + IRDMA_QHASH_MANAGE_TYPE_DELETE, + NULL, false); + } + + cm_core->stats_listen_destroyed++; + cm_core->stats_listen_nodes_destroyed++; + ibdev_dbg(&listener->iwdev->ibdev, + "CM: loc_port=0x%04x loc_addr=%pI4 cm_listen_node=%p cm_id=%p qhash_set=%d vlan_id=%d apbvt_del=%d\n", + listener->loc_port, listener->loc_addr, listener, + listener->cm_id, listener->qhash_set, + listener->vlan_id, apbvt_del); + kfree(listener); + listener = NULL; + return 0; + } + + return -EINVAL; +} + +/** + * irdma_cm_del_listen - delete a listener + * @cm_core: cm's core + * @listener: passive connection's listener + * @apbvt_del: flag to delete apbvt + */ +static int irdma_cm_del_listen(struct irdma_cm_core *cm_core, + struct irdma_cm_listener *listener, + bool apbvt_del) +{ + listener->listener_state = IRDMA_CM_LISTENER_PASSIVE_STATE; + listener->cm_id = NULL; + + return irdma_dec_refcnt_listen(cm_core, listener, 1, apbvt_del); +} + +/** + * irdma_addr_resolve_neigh - resolve neighbor address + * @iwdev: iwarp device structure + * @src_ip: local ip address + * @dst_ip: remote ip address + * @arpindex: if there is an arp entry + */ +static int irdma_addr_resolve_neigh(struct irdma_device *iwdev, u32 src_ip, + u32 dst_ip, int arpindex) +{ + struct rtable *rt; + struct neighbour *neigh; + int rc = arpindex; + int ip[4] = {}; + __be32 dst_ipaddr = htonl(dst_ip); + __be32 src_ipaddr = htonl(src_ip); + + rt = ip_route_output(&init_net, dst_ipaddr, src_ipaddr, 0, 0); + if (IS_ERR(rt)) { + ibdev_dbg(&iwdev->ibdev, "CM: ip_route_output fail\n"); + return -EINVAL; + } + + neigh = dst_neigh_lookup(&rt->dst, &dst_ipaddr); + if (!neigh) + goto exit; + + if (neigh->nud_state & NUD_VALID) { + ip[0] = dst_ip; + rc = irdma_add_arp(iwdev->rf, ip, neigh->ha); + } else { + neigh_event_send(neigh, NULL); + } + if (neigh) + neigh_release(neigh); +exit: + ip_rt_put(rt); + + return rc; +} + +/** + * irdma_get_dst_ipv6 - get destination cache entry via ipv6 lookup + * @src_addr: local ipv6 sock address + * @dst_addr: destination ipv6 sock address + */ +static struct dst_entry *irdma_get_dst_ipv6(struct sockaddr_in6 *src_addr, + struct sockaddr_in6 *dst_addr) +{ + struct dst_entry *dst = NULL; + + if ((IS_ENABLED(CONFIG_IPV6))) { + struct flowi6 fl6 = {}; + + fl6.daddr = dst_addr->sin6_addr; + fl6.saddr = src_addr->sin6_addr; + if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL) + fl6.flowi6_oif = dst_addr->sin6_scope_id; + + dst = ip6_route_output(&init_net, NULL, &fl6); + } + + return dst; +} + +/** + * irdma_addr_resolve_neigh_ipv6 - resolve neighbor ipv6 address + * @iwdev: iwarp device structure + * @src: local ip address + * @dest: remote ip address + * @arpindex: if there is an arp entry + */ +static int irdma_addr_resolve_neigh_ipv6(struct irdma_device *iwdev, u32 *src, + u32 *dest, int arpindex) +{ + struct neighbour *neigh; + int rc = arpindex; + struct dst_entry *dst; + struct sockaddr_in6 dst_addr = {}; + struct sockaddr_in6 src_addr = {}; + + dst_addr.sin6_family = AF_INET6; + irdma_copy_ip_htonl(dst_addr.sin6_addr.in6_u.u6_addr32, dest); + src_addr.sin6_family = AF_INET6; + irdma_copy_ip_htonl(src_addr.sin6_addr.in6_u.u6_addr32, src); + dst = irdma_get_dst_ipv6(&src_addr, &dst_addr); + if (!dst || dst->error) { + if (dst) { + dst_release(dst); + ibdev_dbg(&iwdev->ibdev, + "CM: ip6_route_output returned dst->error = %d\n", + dst->error); + } + return -EINVAL; + } + + neigh = dst_neigh_lookup(dst, dst_addr.sin6_addr.in6_u.u6_addr32); + if (!neigh) + goto exit; + + ibdev_dbg(&iwdev->ibdev, "CM: dst_neigh_lookup MAC=%pM\n", + neigh->ha); + + trace_irdma_addr_resolve(iwdev, neigh->ha); + + if (neigh->nud_state & NUD_VALID) + rc = irdma_add_arp(iwdev->rf, dest, neigh->ha); + else + neigh_event_send(neigh, NULL); + if (neigh) + neigh_release(neigh); +exit: + dst_release(dst); + + return rc; +} + +/** + * irdma_find_node - find a cm node that matches the reference cm node + * @cm_core: cm's core + * @rem_port: remote tcp port num + * @rem_addr: remote ip addr + * @loc_port: local tcp port num + * @loc_addr: local ip addr + * @vlan_id: local VLAN ID + */ +struct irdma_cm_node *irdma_find_node(struct irdma_cm_core *cm_core, + u16 rem_port, u32 *rem_addr, u16 loc_port, + u32 *loc_addr, u16 vlan_id) +{ + struct irdma_cm_node *cm_node; + u32 key = (rem_port << 16) | loc_port; + + rcu_read_lock(); + hash_for_each_possible_rcu(cm_core->cm_hash_tbl, cm_node, list, key) { + if (cm_node->vlan_id == vlan_id && + cm_node->loc_port == loc_port && cm_node->rem_port == rem_port && + !memcmp(cm_node->loc_addr, loc_addr, sizeof(cm_node->loc_addr)) && + !memcmp(cm_node->rem_addr, rem_addr, sizeof(cm_node->rem_addr))) { + if (!refcount_inc_not_zero(&cm_node->refcnt)) + goto exit; + rcu_read_unlock(); + trace_irdma_find_node(cm_node, 0, NULL); + return cm_node; + } + } + +exit: + rcu_read_unlock(); + + /* no owner node */ + return NULL; +} + +/** + * irdma_add_hte_node - add a cm node to the hash table + * @cm_core: cm's core + * @cm_node: connection's node + */ +static void irdma_add_hte_node(struct irdma_cm_core *cm_core, + struct irdma_cm_node *cm_node) +{ + unsigned long flags; + u32 key = (cm_node->rem_port << 16) | cm_node->loc_port; + + spin_lock_irqsave(&cm_core->ht_lock, flags); + hash_add_rcu(cm_core->cm_hash_tbl, &cm_node->list, key); + spin_unlock_irqrestore(&cm_core->ht_lock, flags); +} + +/** + * irdma_ipv4_is_lpb - check if loopback + * @loc_addr: local addr to compare + * @rem_addr: remote address + */ +bool irdma_ipv4_is_lpb(u32 loc_addr, u32 rem_addr) +{ + return ipv4_is_loopback(htonl(rem_addr)) || (loc_addr == rem_addr); +} + +/** + * irdma_ipv6_is_lpb - check if loopback + * @loc_addr: local addr to compare + * @rem_addr: remote address + */ +bool irdma_ipv6_is_lpb(u32 *loc_addr, u32 *rem_addr) +{ + struct in6_addr raddr6; + + irdma_copy_ip_htonl(raddr6.in6_u.u6_addr32, rem_addr); + + return !memcmp(loc_addr, rem_addr, 16) || ipv6_addr_loopback(&raddr6); +} + +/** + * irdma_cm_create_ah - create a cm address handle + * @cm_node: The connection manager node to create AH for + * @wait: Provides option to wait for ah creation or not + */ +static int irdma_cm_create_ah(struct irdma_cm_node *cm_node, bool wait) +{ + struct irdma_ah_info ah_info = {}; + struct irdma_device *iwdev = cm_node->iwdev; + + ether_addr_copy(ah_info.mac_addr, iwdev->netdev->dev_addr); + + ah_info.hop_ttl = 0x40; + ah_info.tc_tos = cm_node->tos; + ah_info.vsi = &iwdev->vsi; + + if (cm_node->ipv4) { + ah_info.ipv4_valid = true; + ah_info.dest_ip_addr[0] = cm_node->rem_addr[0]; + ah_info.src_ip_addr[0] = cm_node->loc_addr[0]; + ah_info.do_lpbk = irdma_ipv4_is_lpb(ah_info.src_ip_addr[0], + ah_info.dest_ip_addr[0]); + } else { + memcpy(ah_info.dest_ip_addr, cm_node->rem_addr, + sizeof(ah_info.dest_ip_addr)); + memcpy(ah_info.src_ip_addr, cm_node->loc_addr, + sizeof(ah_info.src_ip_addr)); + ah_info.do_lpbk = irdma_ipv6_is_lpb(ah_info.src_ip_addr, + ah_info.dest_ip_addr); + } + + ah_info.vlan_tag = cm_node->vlan_id; + if (cm_node->vlan_id < VLAN_N_VID) { + ah_info.insert_vlan_tag = 1; + ah_info.vlan_tag |= cm_node->user_pri << VLAN_PRIO_SHIFT; + } + + ah_info.dst_arpindex = + irdma_arp_table(iwdev->rf, ah_info.dest_ip_addr, + NULL, IRDMA_ARP_RESOLVE); + + if (irdma_puda_create_ah(&iwdev->rf->sc_dev, &ah_info, wait, + IRDMA_PUDA_RSRC_TYPE_ILQ, cm_node, + &cm_node->ah)) + return -ENOMEM; + + trace_irdma_create_ah(cm_node); + return 0; +} + +/** + * irdma_cm_free_ah - free a cm address handle + * @cm_node: The connection manager node to create AH for + */ +static void irdma_cm_free_ah(struct irdma_cm_node *cm_node) +{ + struct irdma_device *iwdev = cm_node->iwdev; + + trace_irdma_cm_free_ah(cm_node); + irdma_puda_free_ah(&iwdev->rf->sc_dev, cm_node->ah); + cm_node->ah = NULL; +} + +/** + * irdma_make_cm_node - create a new instance of a cm node + * @cm_core: cm's core + * @iwdev: iwarp device structure + * @cm_info: quad info for connection + * @listener: passive connection's listener + */ +static struct irdma_cm_node * +irdma_make_cm_node(struct irdma_cm_core *cm_core, struct irdma_device *iwdev, + struct irdma_cm_info *cm_info, + struct irdma_cm_listener *listener) +{ + struct irdma_cm_node *cm_node; + int oldarpindex; + int arpindex; + struct net_device *netdev = iwdev->netdev; + + /* create an hte and cm_node for this instance */ + cm_node = kzalloc(sizeof(*cm_node), GFP_ATOMIC); + if (!cm_node) + return NULL; + + /* set our node specific transport info */ + cm_node->ipv4 = cm_info->ipv4; + cm_node->vlan_id = cm_info->vlan_id; + if (cm_node->vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode) + cm_node->vlan_id = 0; + cm_node->tos = cm_info->tos; + cm_node->user_pri = cm_info->user_pri; + if (listener) { + if (listener->tos != cm_info->tos) + ibdev_warn(&iwdev->ibdev, + "application TOS[%d] and remote client TOS[%d] mismatch\n", + listener->tos, cm_info->tos); + if (iwdev->vsi.dscp_mode) { + cm_node->user_pri = listener->user_pri; + } else { + cm_node->tos = max(listener->tos, cm_info->tos); + cm_node->user_pri = rt_tos2priority(cm_node->tos); + cm_node->user_pri = + irdma_iw_get_vlan_prio(cm_info->loc_addr, + cm_node->user_pri, + cm_info->ipv4); + } + ibdev_dbg(&iwdev->ibdev, + "DCB: listener: TOS:[%d] UP:[%d]\n", cm_node->tos, + cm_node->user_pri); + trace_irdma_listener_tos(iwdev, cm_node->tos, + cm_node->user_pri); + } + memcpy(cm_node->loc_addr, cm_info->loc_addr, sizeof(cm_node->loc_addr)); + memcpy(cm_node->rem_addr, cm_info->rem_addr, sizeof(cm_node->rem_addr)); + cm_node->loc_port = cm_info->loc_port; + cm_node->rem_port = cm_info->rem_port; + + cm_node->mpa_frame_rev = IRDMA_CM_DEFAULT_MPA_VER; + cm_node->send_rdma0_op = SEND_RDMA_READ_ZERO; + cm_node->iwdev = iwdev; + cm_node->dev = &iwdev->rf->sc_dev; + + cm_node->ird_size = cm_node->dev->hw_attrs.max_hw_ird; + cm_node->ord_size = cm_node->dev->hw_attrs.max_hw_ord; + + cm_node->listener = listener; + cm_node->cm_id = cm_info->cm_id; + ether_addr_copy(cm_node->loc_mac, netdev->dev_addr); + spin_lock_init(&cm_node->retrans_list_lock); + cm_node->ack_rcvd = false; + + init_completion(&cm_node->establish_comp); + refcount_set(&cm_node->refcnt, 1); + /* associate our parent CM core */ + cm_node->cm_core = cm_core; + cm_node->tcp_cntxt.loc_id = IRDMA_CM_DEFAULT_LOCAL_ID; + cm_node->tcp_cntxt.rcv_wscale = iwdev->rcv_wscale; + cm_node->tcp_cntxt.rcv_wnd = iwdev->rcv_wnd >> cm_node->tcp_cntxt.rcv_wscale; + kc_set_loc_seq_num_mss(cm_node); + + if ((cm_node->ipv4 && + irdma_ipv4_is_lpb(cm_node->loc_addr[0], cm_node->rem_addr[0])) || + (!cm_node->ipv4 && + irdma_ipv6_is_lpb(cm_node->loc_addr, cm_node->rem_addr))) { + cm_node->do_lpb = true; + arpindex = irdma_arp_table(iwdev->rf, cm_node->rem_addr, + NULL, IRDMA_ARP_RESOLVE); + } else { + oldarpindex = irdma_arp_table(iwdev->rf, cm_node->rem_addr, + NULL, IRDMA_ARP_RESOLVE); + if (cm_node->ipv4) + arpindex = irdma_addr_resolve_neigh(iwdev, + cm_info->loc_addr[0], + cm_info->rem_addr[0], + oldarpindex); + else if (IS_ENABLED(CONFIG_IPV6)) + arpindex = irdma_addr_resolve_neigh_ipv6(iwdev, + cm_info->loc_addr, + cm_info->rem_addr, + oldarpindex); + else + arpindex = -EINVAL; + } + if (arpindex < 0) + goto err; + + ether_addr_copy(cm_node->rem_mac, + iwdev->rf->arp_table[arpindex].mac_addr); + irdma_add_hte_node(cm_core, cm_node); + cm_core->stats_nodes_created++; + return cm_node; + +err: + kfree(cm_node); + + return NULL; +} + +static void irdma_destroy_connection(struct irdma_cm_node *cm_node) +{ + struct irdma_cm_core *cm_core = cm_node->cm_core; + struct irdma_qp *iwqp; + struct irdma_cm_info nfo; + + /* if the node is destroyed before connection was accelerated */ + if (!cm_node->accelerated && cm_node->accept_pend) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: node destroyed before established\n"); + atomic_dec(&cm_node->listener->pend_accepts_cnt); + } + if (cm_node->close_entry) + irdma_handle_close_entry(cm_node, 0); + if (cm_node->listener) { + irdma_dec_refcnt_listen(cm_core, cm_node->listener, 0, true); + } else { + if (cm_node->apbvt_set) { + irdma_del_apbvt(cm_node->iwdev, cm_node->apbvt_entry); + cm_node->apbvt_set = 0; + } + irdma_get_addr_info(cm_node, &nfo); + if (cm_node->qhash_set) { + nfo.qh_qpid = cm_node->iwdev->vsi.ilq->qp_id; + irdma_manage_qhash(cm_node->iwdev, &nfo, + IRDMA_QHASH_TYPE_TCP_ESTABLISHED, + IRDMA_QHASH_MANAGE_TYPE_DELETE, NULL, + false); + cm_node->qhash_set = 0; + } + } + + iwqp = cm_node->iwqp; + if (iwqp) { + cm_node->cm_id->rem_ref(cm_node->cm_id); + cm_node->cm_id = NULL; + iwqp->cm_id = NULL; + irdma_qp_rem_ref(&iwqp->ibqp); + cm_node->iwqp = NULL; + } else if (cm_node->qhash_set) { + irdma_get_addr_info(cm_node, &nfo); + nfo.qh_qpid = cm_node->iwdev->vsi.ilq->qp_id; + irdma_manage_qhash(cm_node->iwdev, &nfo, + IRDMA_QHASH_TYPE_TCP_ESTABLISHED, + IRDMA_QHASH_MANAGE_TYPE_DELETE, NULL, false); + cm_node->qhash_set = 0; + } + + cm_core->cm_free_ah(cm_node); +} + +/** + * irdma_rem_ref_cm_node - destroy an instance of a cm node + * @cm_node: connection's node + */ +void irdma_rem_ref_cm_node(struct irdma_cm_node *cm_node) +{ + struct irdma_cm_core *cm_core = cm_node->cm_core; + unsigned long flags; + + trace_irdma_rem_ref_cm_node(cm_node, 0, __builtin_return_address(0)); + spin_lock_irqsave(&cm_core->ht_lock, flags); + + if (!refcount_dec_and_test(&cm_node->refcnt)) { + spin_unlock_irqrestore(&cm_core->ht_lock, flags); + return; + } + if (cm_node->iwqp) { + cm_node->iwqp->cm_node = NULL; + cm_node->iwqp->cm_id = NULL; + } + hash_del_rcu(&cm_node->list); + cm_node->cm_core->stats_nodes_destroyed++; + + spin_unlock_irqrestore(&cm_core->ht_lock, flags); + + irdma_destroy_connection(cm_node); + + kfree_rcu(cm_node, rcu_head); +} + +/** + * irdma_handle_fin_pkt - FIN packet received + * @cm_node: connection's node + */ +static void irdma_handle_fin_pkt(struct irdma_cm_node *cm_node) +{ + switch (cm_node->state) { + case IRDMA_CM_STATE_SYN_RCVD: + case IRDMA_CM_STATE_SYN_SENT: + case IRDMA_CM_STATE_ESTABLISHED: + case IRDMA_CM_STATE_MPAREJ_RCVD: + cm_node->tcp_cntxt.rcv_nxt++; + irdma_cleanup_retrans_entry(cm_node); + cm_node->state = IRDMA_CM_STATE_LAST_ACK; + irdma_send_fin(cm_node); + break; + case IRDMA_CM_STATE_MPAREQ_SENT: + irdma_create_event(cm_node, IRDMA_CM_EVENT_ABORTED); + cm_node->tcp_cntxt.rcv_nxt++; + irdma_cleanup_retrans_entry(cm_node); + cm_node->state = IRDMA_CM_STATE_CLOSED; + refcount_inc(&cm_node->refcnt); + irdma_send_reset(cm_node); + break; + case IRDMA_CM_STATE_FIN_WAIT1: + cm_node->tcp_cntxt.rcv_nxt++; + irdma_cleanup_retrans_entry(cm_node); + cm_node->state = IRDMA_CM_STATE_CLOSING; + irdma_send_ack(cm_node); + /* + * Wait for ACK as this is simultaneous close. + * After we receive ACK, do not send anything. + * Just rm the node. + */ + break; + case IRDMA_CM_STATE_FIN_WAIT2: + cm_node->tcp_cntxt.rcv_nxt++; + irdma_cleanup_retrans_entry(cm_node); + cm_node->state = IRDMA_CM_STATE_TIME_WAIT; + irdma_send_ack(cm_node); + irdma_schedule_cm_timer(cm_node, NULL, IRDMA_TIMER_TYPE_CLOSE, + 1, 0); + break; + case IRDMA_CM_STATE_TIME_WAIT: + cm_node->tcp_cntxt.rcv_nxt++; + irdma_cleanup_retrans_entry(cm_node); + cm_node->state = IRDMA_CM_STATE_CLOSED; + irdma_rem_ref_cm_node(cm_node); + break; + case IRDMA_CM_STATE_OFFLOADED: + default: + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: bad state node state = %d\n", cm_node->state); + break; + } +} + +/** + * irdma_handle_rst_pkt - process received RST packet + * @cm_node: connection's node + * @rbuf: receive buffer + */ +static void irdma_handle_rst_pkt(struct irdma_cm_node *cm_node, + struct irdma_puda_buf *rbuf) +{ + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: caller: %pS cm_node=%p state=%d rem_port=0x%04x loc_port=0x%04x rem_addr=%pI4 loc_addr=%pI4\n", + __builtin_return_address(0), cm_node, cm_node->state, + cm_node->rem_port, cm_node->loc_port, cm_node->rem_addr, + cm_node->loc_addr); + + irdma_cleanup_retrans_entry(cm_node); + switch (cm_node->state) { + case IRDMA_CM_STATE_SYN_SENT: + case IRDMA_CM_STATE_MPAREQ_SENT: + switch (cm_node->mpa_frame_rev) { + case IETF_MPA_V2: + /* Drop down to MPA_V1*/ + cm_node->mpa_frame_rev = IETF_MPA_V1; + /* send a syn and goto syn sent state */ + cm_node->state = IRDMA_CM_STATE_SYN_SENT; + if (irdma_send_syn(cm_node, 0)) + irdma_active_open_err(cm_node, false); + break; + case IETF_MPA_V1: + default: + irdma_active_open_err(cm_node, false); + break; + } + break; + case IRDMA_CM_STATE_MPAREQ_RCVD: + atomic_inc(&cm_node->passive_state); + break; + case IRDMA_CM_STATE_ESTABLISHED: + case IRDMA_CM_STATE_SYN_RCVD: + case IRDMA_CM_STATE_LISTENING: + irdma_passive_open_err(cm_node, false); + break; + case IRDMA_CM_STATE_OFFLOADED: + irdma_active_open_err(cm_node, false); + break; + case IRDMA_CM_STATE_CLOSED: + break; + case IRDMA_CM_STATE_FIN_WAIT2: + case IRDMA_CM_STATE_FIN_WAIT1: + case IRDMA_CM_STATE_LAST_ACK: + case IRDMA_CM_STATE_TIME_WAIT: + cm_node->state = IRDMA_CM_STATE_CLOSED; + irdma_rem_ref_cm_node(cm_node); + break; + default: + break; + } +} + +/** + * irdma_handle_rcv_mpa - Process a recv'd mpa buffer + * @cm_node: connection's node + * @rbuf: receive buffer + */ +static void irdma_handle_rcv_mpa(struct irdma_cm_node *cm_node, + struct irdma_puda_buf *rbuf) +{ + int err; + int datasize = rbuf->datalen; + u8 *dataloc = rbuf->data; + + enum irdma_cm_event_type type = IRDMA_CM_EVENT_UNKNOWN; + u32 res_type; + + err = irdma_parse_mpa(cm_node, dataloc, &res_type, datasize); + if (err) { + if (cm_node->state == IRDMA_CM_STATE_MPAREQ_SENT) + irdma_active_open_err(cm_node, true); + else + irdma_passive_open_err(cm_node, true); + return; + } + + switch (cm_node->state) { + case IRDMA_CM_STATE_ESTABLISHED: + if (res_type == IRDMA_MPA_REQUEST_REJECT) + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: state for reject\n"); + cm_node->state = IRDMA_CM_STATE_MPAREQ_RCVD; + type = IRDMA_CM_EVENT_MPA_REQ; + irdma_send_ack(cm_node); /* ACK received MPA request */ + atomic_set(&cm_node->passive_state, + IRDMA_PASSIVE_STATE_INDICATED); + break; + case IRDMA_CM_STATE_MPAREQ_SENT: + irdma_cleanup_retrans_entry(cm_node); + if (res_type == IRDMA_MPA_REQUEST_REJECT) { + type = IRDMA_CM_EVENT_MPA_REJECT; + cm_node->state = IRDMA_CM_STATE_MPAREJ_RCVD; + } else { + type = IRDMA_CM_EVENT_CONNECTED; + cm_node->state = IRDMA_CM_STATE_OFFLOADED; + } + irdma_send_ack(cm_node); + break; + default: + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: wrong cm_node state=%d\n", cm_node->state); + break; + } + irdma_create_event(cm_node, type); +} + +/** + * irdma_check_syn - Check for error on received syn ack + * @cm_node: connection's node + * @tcph: pointer tcp header + */ +static int irdma_check_syn(struct irdma_cm_node *cm_node, struct tcphdr *tcph) +{ + if (ntohl(tcph->ack_seq) != cm_node->tcp_cntxt.loc_seq_num) { + irdma_active_open_err(cm_node, true); + return 1; + } + + return 0; +} + +/** + * irdma_check_seq - check seq numbers if OK + * @cm_node: connection's node + * @tcph: pointer tcp header + */ +static int irdma_check_seq(struct irdma_cm_node *cm_node, struct tcphdr *tcph) +{ + u32 seq; + u32 ack_seq; + u32 loc_seq_num = cm_node->tcp_cntxt.loc_seq_num; + u32 rcv_nxt = cm_node->tcp_cntxt.rcv_nxt; + u32 rcv_wnd; + int err = 0; + + seq = ntohl(tcph->seq); + ack_seq = ntohl(tcph->ack_seq); + rcv_wnd = cm_node->tcp_cntxt.rcv_wnd; + if (ack_seq != loc_seq_num || + !between(seq, rcv_nxt, (rcv_nxt + rcv_wnd))) + err = -1; + if (err) + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: seq number err\n"); + + return err; +} + +void irdma_add_conn_est_qh(struct irdma_cm_node *cm_node) +{ + struct irdma_cm_info nfo; + + irdma_get_addr_info(cm_node, &nfo); + nfo.qh_qpid = cm_node->iwdev->vsi.ilq->qp_id; + irdma_manage_qhash(cm_node->iwdev, &nfo, + IRDMA_QHASH_TYPE_TCP_ESTABLISHED, + IRDMA_QHASH_MANAGE_TYPE_ADD, + cm_node, false); + cm_node->qhash_set = true; +} + +/** + * irdma_handle_syn_pkt - is for Passive node + * @cm_node: connection's node + * @rbuf: receive buffer + */ +static void irdma_handle_syn_pkt(struct irdma_cm_node *cm_node, + struct irdma_puda_buf *rbuf) +{ + struct tcphdr *tcph = (struct tcphdr *)rbuf->tcph; + int err; + u32 inc_sequence; + int optionsize; + + optionsize = (tcph->doff << 2) - sizeof(*tcph); + inc_sequence = ntohl(tcph->seq); + + switch (cm_node->state) { + case IRDMA_CM_STATE_SYN_SENT: + case IRDMA_CM_STATE_MPAREQ_SENT: + /* Rcvd syn on active open connection */ + irdma_active_open_err(cm_node, 1); + break; + case IRDMA_CM_STATE_LISTENING: + /* Passive OPEN */ + if (atomic_read(&cm_node->listener->pend_accepts_cnt) > + cm_node->listener->backlog) { + cm_node->cm_core->stats_backlog_drops++; + irdma_passive_open_err(cm_node, false); + break; + } + err = irdma_handle_tcp_options(cm_node, tcph, optionsize, 1); + if (err) { + irdma_passive_open_err(cm_node, false); + /* drop pkt */ + break; + } + err = cm_node->cm_core->cm_create_ah(cm_node, false); + if (err) { + irdma_passive_open_err(cm_node, false); + /* drop pkt */ + break; + } + cm_node->tcp_cntxt.rcv_nxt = inc_sequence + 1; + cm_node->accept_pend = 1; + atomic_inc(&cm_node->listener->pend_accepts_cnt); + + cm_node->state = IRDMA_CM_STATE_SYN_RCVD; + break; + case IRDMA_CM_STATE_CLOSED: + irdma_cleanup_retrans_entry(cm_node); + refcount_inc(&cm_node->refcnt); + irdma_send_reset(cm_node); + break; + case IRDMA_CM_STATE_OFFLOADED: + case IRDMA_CM_STATE_ESTABLISHED: + case IRDMA_CM_STATE_FIN_WAIT1: + case IRDMA_CM_STATE_FIN_WAIT2: + case IRDMA_CM_STATE_MPAREQ_RCVD: + case IRDMA_CM_STATE_LAST_ACK: + case IRDMA_CM_STATE_CLOSING: + case IRDMA_CM_STATE_UNKNOWN: + default: + break; + } +} + +/** + * irdma_handle_synack_pkt - Process SYN+ACK packet (active side) + * @cm_node: connection's node + * @rbuf: receive buffer + */ +static void irdma_handle_synack_pkt(struct irdma_cm_node *cm_node, + struct irdma_puda_buf *rbuf) +{ + struct tcphdr *tcph = (struct tcphdr *)rbuf->tcph; + int err; + u32 inc_sequence; + int optionsize; + + optionsize = (tcph->doff << 2) - sizeof(*tcph); + inc_sequence = ntohl(tcph->seq); + switch (cm_node->state) { + case IRDMA_CM_STATE_SYN_SENT: + irdma_cleanup_retrans_entry(cm_node); + /* active open */ + if (irdma_check_syn(cm_node, tcph)) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: check syn fail\n"); + return; + } + cm_node->tcp_cntxt.rem_ack_num = ntohl(tcph->ack_seq); + /* setup options */ + err = irdma_handle_tcp_options(cm_node, tcph, optionsize, 0); + if (err) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: cm_node=%p tcp_options failed\n", + cm_node); + break; + } + irdma_cleanup_retrans_entry(cm_node); + cm_node->tcp_cntxt.rcv_nxt = inc_sequence + 1; + irdma_send_ack(cm_node); /* ACK for the syn_ack */ + err = irdma_send_mpa_request(cm_node); + if (err) { + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: cm_node=%p irdma_send_mpa_request failed\n", + cm_node); + break; + } + cm_node->state = IRDMA_CM_STATE_MPAREQ_SENT; + break; + case IRDMA_CM_STATE_MPAREQ_RCVD: + irdma_passive_open_err(cm_node, true); + break; + case IRDMA_CM_STATE_LISTENING: + cm_node->tcp_cntxt.loc_seq_num = ntohl(tcph->ack_seq); + irdma_cleanup_retrans_entry(cm_node); + cm_node->state = IRDMA_CM_STATE_CLOSED; + irdma_send_reset(cm_node); + break; + case IRDMA_CM_STATE_CLOSED: + cm_node->tcp_cntxt.loc_seq_num = ntohl(tcph->ack_seq); + irdma_cleanup_retrans_entry(cm_node); + refcount_inc(&cm_node->refcnt); + irdma_send_reset(cm_node); + break; + case IRDMA_CM_STATE_ESTABLISHED: + case IRDMA_CM_STATE_FIN_WAIT1: + case IRDMA_CM_STATE_FIN_WAIT2: + case IRDMA_CM_STATE_LAST_ACK: + case IRDMA_CM_STATE_OFFLOADED: + case IRDMA_CM_STATE_CLOSING: + case IRDMA_CM_STATE_UNKNOWN: + case IRDMA_CM_STATE_MPAREQ_SENT: + default: + break; + } +} + +/** + * irdma_handle_ack_pkt - process packet with ACK + * @cm_node: connection's node + * @rbuf: receive buffer + */ +static int irdma_handle_ack_pkt(struct irdma_cm_node *cm_node, + struct irdma_puda_buf *rbuf) +{ + struct tcphdr *tcph = (struct tcphdr *)rbuf->tcph; + u32 inc_sequence; + int ret; + int optionsize; + u32 datasize = rbuf->datalen; + + optionsize = (tcph->doff << 2) - sizeof(*tcph); + + if (irdma_check_seq(cm_node, tcph)) + return -EINVAL; + + inc_sequence = ntohl(tcph->seq); + switch (cm_node->state) { + case IRDMA_CM_STATE_SYN_RCVD: + irdma_cleanup_retrans_entry(cm_node); + ret = irdma_handle_tcp_options(cm_node, tcph, optionsize, 1); + if (ret) + return ret; + cm_node->tcp_cntxt.rem_ack_num = ntohl(tcph->ack_seq); + cm_node->state = IRDMA_CM_STATE_ESTABLISHED; + if (datasize) { + cm_node->tcp_cntxt.rcv_nxt = inc_sequence + datasize; + irdma_handle_rcv_mpa(cm_node, rbuf); + } + break; + case IRDMA_CM_STATE_ESTABLISHED: + irdma_cleanup_retrans_entry(cm_node); + if (datasize) { + cm_node->tcp_cntxt.rcv_nxt = inc_sequence + datasize; + irdma_handle_rcv_mpa(cm_node, rbuf); + } + break; + case IRDMA_CM_STATE_MPAREQ_SENT: + cm_node->tcp_cntxt.rem_ack_num = ntohl(tcph->ack_seq); + if (datasize) { + cm_node->tcp_cntxt.rcv_nxt = inc_sequence + datasize; + cm_node->ack_rcvd = false; + irdma_handle_rcv_mpa(cm_node, rbuf); + } else { + cm_node->ack_rcvd = true; + } + break; + case IRDMA_CM_STATE_LISTENING: + irdma_cleanup_retrans_entry(cm_node); + cm_node->state = IRDMA_CM_STATE_CLOSED; + irdma_send_reset(cm_node); + break; + case IRDMA_CM_STATE_CLOSED: + irdma_cleanup_retrans_entry(cm_node); + refcount_inc(&cm_node->refcnt); + irdma_send_reset(cm_node); + break; + case IRDMA_CM_STATE_LAST_ACK: + case IRDMA_CM_STATE_CLOSING: + irdma_cleanup_retrans_entry(cm_node); + cm_node->state = IRDMA_CM_STATE_CLOSED; + irdma_rem_ref_cm_node(cm_node); + break; + case IRDMA_CM_STATE_FIN_WAIT1: + irdma_cleanup_retrans_entry(cm_node); + cm_node->state = IRDMA_CM_STATE_FIN_WAIT2; + break; + case IRDMA_CM_STATE_SYN_SENT: + case IRDMA_CM_STATE_FIN_WAIT2: + case IRDMA_CM_STATE_OFFLOADED: + case IRDMA_CM_STATE_MPAREQ_RCVD: + case IRDMA_CM_STATE_UNKNOWN: + default: + irdma_cleanup_retrans_entry(cm_node); + break; + } + + return 0; +} + +/** + * irdma_process_pkt - process cm packet + * @cm_node: connection's node + * @rbuf: receive buffer + */ +static void irdma_process_pkt(struct irdma_cm_node *cm_node, + struct irdma_puda_buf *rbuf) +{ + enum irdma_tcpip_pkt_type pkt_type = IRDMA_PKT_TYPE_UNKNOWN; + struct tcphdr *tcph = (struct tcphdr *)rbuf->tcph; + u32 fin_set = 0; + int err; + + if (tcph->rst) { + pkt_type = IRDMA_PKT_TYPE_RST; + } else if (tcph->syn) { + pkt_type = IRDMA_PKT_TYPE_SYN; + if (tcph->ack) + pkt_type = IRDMA_PKT_TYPE_SYNACK; + } else if (tcph->ack) { + pkt_type = IRDMA_PKT_TYPE_ACK; + } + if (tcph->fin) + fin_set = 1; + + switch (pkt_type) { + case IRDMA_PKT_TYPE_SYN: + irdma_handle_syn_pkt(cm_node, rbuf); + break; + case IRDMA_PKT_TYPE_SYNACK: + irdma_handle_synack_pkt(cm_node, rbuf); + break; + case IRDMA_PKT_TYPE_ACK: + err = irdma_handle_ack_pkt(cm_node, rbuf); + if (fin_set && !err) + irdma_handle_fin_pkt(cm_node); + break; + case IRDMA_PKT_TYPE_RST: + irdma_handle_rst_pkt(cm_node, rbuf); + break; + default: + if (fin_set && + (!irdma_check_seq(cm_node, (struct tcphdr *)rbuf->tcph))) + irdma_handle_fin_pkt(cm_node); + break; + } +} + +/** + * irdma_make_listen_node - create a listen node with params + * @cm_core: cm's core + * @iwdev: iwarp device structure + * @cm_info: quad info for connection + */ +static struct irdma_cm_listener * +irdma_make_listen_node(struct irdma_cm_core *cm_core, + struct irdma_device *iwdev, + struct irdma_cm_info *cm_info) +{ + struct irdma_cm_listener *listener; + unsigned long flags; + + /* cannot have multiple matching listeners */ + listener = irdma_find_listener(cm_core, cm_info->loc_addr, cm_info->ipv4, + cm_info->loc_port, cm_info->vlan_id, + IRDMA_CM_LISTENER_EITHER_STATE); + if (listener && + listener->listener_state == IRDMA_CM_LISTENER_ACTIVE_STATE) { + refcount_dec(&listener->refcnt); + return NULL; + } + + if (!listener) { + /* create a CM listen node + * 1/2 node to compare incoming traffic to + */ + listener = kzalloc(sizeof(*listener), GFP_KERNEL); + if (!listener) + return NULL; + cm_core->stats_listen_nodes_created++; + memcpy(listener->loc_addr, cm_info->loc_addr, + sizeof(listener->loc_addr)); + listener->loc_port = cm_info->loc_port; + + INIT_LIST_HEAD(&listener->child_listen_list); + + refcount_set(&listener->refcnt, 1); + } else { + listener->reused_node = 1; + } + + listener->cm_id = cm_info->cm_id; + listener->ipv4 = cm_info->ipv4; + listener->vlan_id = cm_info->vlan_id; + atomic_set(&listener->pend_accepts_cnt, 0); + listener->cm_core = cm_core; + listener->iwdev = iwdev; + + listener->backlog = cm_info->backlog; + listener->listener_state = IRDMA_CM_LISTENER_ACTIVE_STATE; + + if (!listener->reused_node) { + spin_lock_irqsave(&cm_core->listen_list_lock, flags); + list_add(&listener->list, &cm_core->listen_list); + spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); + } + + return listener; +} + +/** + * irdma_create_cm_node - make a connection node with params + * @cm_core: cm's core + * @iwdev: iwarp device structure + * @conn_param: connection parameters + * @cm_info: quad info for connection + * @caller_cm_node: pointer to cm_node structure to return + */ +static int irdma_create_cm_node(struct irdma_cm_core *cm_core, + struct irdma_device *iwdev, + struct iw_cm_conn_param *conn_param, + struct irdma_cm_info *cm_info, + struct irdma_cm_node **caller_cm_node) +{ + struct irdma_cm_node *cm_node; + u16 private_data_len = conn_param->private_data_len; + const void *private_data = conn_param->private_data; + + /* create a CM connection node */ + cm_node = irdma_make_cm_node(cm_core, iwdev, cm_info, NULL); + if (!cm_node) + return -ENOMEM; + + /* set our node side to client (active) side */ + cm_node->tcp_cntxt.client = 1; + cm_node->tcp_cntxt.rcv_wscale = IRDMA_CM_DEFAULT_RCV_WND_SCALE; + + irdma_record_ird_ord(cm_node, conn_param->ird, conn_param->ord); + + cm_node->pdata.size = private_data_len; + cm_node->pdata.addr = cm_node->pdata_buf; + + memcpy(cm_node->pdata_buf, private_data, private_data_len); + *caller_cm_node = cm_node; + + return 0; +} + +/** + * irdma_cm_reject - reject and teardown a connection + * @cm_node: connection's node + * @pdata: ptr to private data for reject + * @plen: size of private data + */ +static int irdma_cm_reject(struct irdma_cm_node *cm_node, const void *pdata, + u8 plen) +{ + int ret; + int passive_state; + + if (cm_node->tcp_cntxt.client) + return 0; + + irdma_cleanup_retrans_entry(cm_node); + + passive_state = atomic_add_return(1, &cm_node->passive_state); + if (passive_state == IRDMA_SEND_RESET_EVENT) { + cm_node->state = IRDMA_CM_STATE_CLOSED; + irdma_rem_ref_cm_node(cm_node); + return 0; + } + + if (cm_node->state == IRDMA_CM_STATE_LISTENER_DESTROYED) { + irdma_rem_ref_cm_node(cm_node); + return 0; + } + + ret = irdma_send_mpa_reject(cm_node, pdata, plen); + if (!ret) + return 0; + + cm_node->state = IRDMA_CM_STATE_CLOSED; + if (irdma_send_reset(cm_node)) + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: send reset failed\n"); + + return ret; +} + +/** + * irdma_cm_close - close of cm connection + * @cm_node: connection's node + */ +static int irdma_cm_close(struct irdma_cm_node *cm_node) +{ + switch (cm_node->state) { + case IRDMA_CM_STATE_SYN_RCVD: + case IRDMA_CM_STATE_SYN_SENT: + case IRDMA_CM_STATE_ONE_SIDE_ESTABLISHED: + case IRDMA_CM_STATE_ESTABLISHED: + case IRDMA_CM_STATE_ACCEPTING: + case IRDMA_CM_STATE_MPAREQ_SENT: + case IRDMA_CM_STATE_MPAREQ_RCVD: + irdma_cleanup_retrans_entry(cm_node); + irdma_send_reset(cm_node); + break; + case IRDMA_CM_STATE_CLOSE_WAIT: + cm_node->state = IRDMA_CM_STATE_LAST_ACK; + irdma_send_fin(cm_node); + break; + case IRDMA_CM_STATE_FIN_WAIT1: + case IRDMA_CM_STATE_FIN_WAIT2: + case IRDMA_CM_STATE_LAST_ACK: + case IRDMA_CM_STATE_TIME_WAIT: + case IRDMA_CM_STATE_CLOSING: + return -EINVAL; + case IRDMA_CM_STATE_LISTENING: + irdma_cleanup_retrans_entry(cm_node); + irdma_send_reset(cm_node); + break; + case IRDMA_CM_STATE_MPAREJ_RCVD: + case IRDMA_CM_STATE_UNKNOWN: + case IRDMA_CM_STATE_INITED: + case IRDMA_CM_STATE_CLOSED: + case IRDMA_CM_STATE_LISTENER_DESTROYED: + irdma_rem_ref_cm_node(cm_node); + break; + case IRDMA_CM_STATE_OFFLOADED: + if (cm_node->send_entry) + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: CM send_entry in OFFLOADED state\n"); + irdma_rem_ref_cm_node(cm_node); + break; + } + + return 0; +} + +/** + * irdma_receive_ilq - recv an ETHERNET packet, and process it + * through CM + * @vsi: VSI structure of dev + * @rbuf: receive buffer + */ +void irdma_receive_ilq(struct irdma_sc_vsi *vsi, struct irdma_puda_buf *rbuf) +{ + struct irdma_cm_node *cm_node; + struct irdma_cm_listener *listener; + struct iphdr *iph; + struct ipv6hdr *ip6h; + struct tcphdr *tcph; + struct irdma_cm_info cm_info = {}; + struct irdma_device *iwdev = vsi->back_vsi; + struct irdma_cm_core *cm_core = &iwdev->cm_core; + struct vlan_ethhdr *ethh; + u16 vtag; + + /* if vlan, then maclen = 18 else 14 */ + iph = (struct iphdr *)rbuf->iph; + print_hex_dump_debug("ILQ: RECEIVE ILQ BUFFER", DUMP_PREFIX_OFFSET, + 16, 8, rbuf->mem.va, rbuf->totallen, false); + if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + if (rbuf->vlan_valid && iwdev->rf->vlan_parse_en) { + vtag = rbuf->vlan_id; + cm_info.user_pri = (vtag & VLAN_PRIO_MASK) >> + VLAN_PRIO_SHIFT; + cm_info.vlan_id = vtag & VLAN_VID_MASK; + } else { + cm_info.vlan_id = 0xFFFF; + } + } else { + ethh = rbuf->mem.va; + + if (ethh->h_vlan_proto == htons(ETH_P_8021Q)) { + vtag = ntohs(ethh->h_vlan_TCI); + cm_info.user_pri = (vtag & VLAN_PRIO_MASK) >> + VLAN_PRIO_SHIFT; + cm_info.vlan_id = vtag & VLAN_VID_MASK; + ibdev_dbg(&cm_core->iwdev->ibdev, + "CM: vlan_id=%d\n", cm_info.vlan_id); + } else { + cm_info.vlan_id = 0xFFFF; + } + } + tcph = (struct tcphdr *)rbuf->tcph; + + if (rbuf->ipv4) { + cm_info.loc_addr[0] = ntohl(iph->daddr); + cm_info.rem_addr[0] = ntohl(iph->saddr); + cm_info.ipv4 = true; + cm_info.tos = iph->tos; + } else { + ip6h = (struct ipv6hdr *)rbuf->iph; + irdma_copy_ip_ntohl(cm_info.loc_addr, + ip6h->daddr.in6_u.u6_addr32); + irdma_copy_ip_ntohl(cm_info.rem_addr, + ip6h->saddr.in6_u.u6_addr32); + cm_info.ipv4 = false; + cm_info.tos = (ip6h->priority << 4) | (ip6h->flow_lbl[0] >> 4); + } + cm_info.loc_port = ntohs(tcph->dest); + cm_info.rem_port = ntohs(tcph->source); + cm_node = irdma_find_node(cm_core, cm_info.rem_port, cm_info.rem_addr, + cm_info.loc_port, cm_info.loc_addr, cm_info.vlan_id); + + if (!cm_node) { + /* Only type of packet accepted are for the + * PASSIVE open (syn only) + */ + if (!tcph->syn || tcph->ack) + return; + + listener = irdma_find_listener(cm_core, + cm_info.loc_addr, + cm_info.ipv4, + cm_info.loc_port, + cm_info.vlan_id, + IRDMA_CM_LISTENER_ACTIVE_STATE); + if (!listener) { + cm_info.cm_id = NULL; + ibdev_dbg(&cm_core->iwdev->ibdev, + "CM: no listener found\n"); + return; + } + + cm_info.cm_id = listener->cm_id; + cm_node = irdma_make_cm_node(cm_core, iwdev, &cm_info, + listener); + if (!cm_node) { + ibdev_dbg(&cm_core->iwdev->ibdev, + "CM: allocate node failed\n"); + refcount_dec(&listener->refcnt); + return; + } + + if (!tcph->rst && !tcph->fin) { + cm_node->state = IRDMA_CM_STATE_LISTENING; + } else { + irdma_rem_ref_cm_node(cm_node); + return; + } + + refcount_inc(&cm_node->refcnt); + } else if (cm_node->state == IRDMA_CM_STATE_OFFLOADED) { + irdma_rem_ref_cm_node(cm_node); + return; + } + + irdma_process_pkt(cm_node, rbuf); + irdma_rem_ref_cm_node(cm_node); +} + +static int irdma_add_qh(struct irdma_cm_node *cm_node, bool active) +{ + if (!active) + irdma_add_conn_est_qh(cm_node); + return 0; +} + +static void irdma_cm_free_ah_nop(struct irdma_cm_node *cm_node) +{ +} + +/** + * irdma_setup_cm_core - setup top level instance of a cm core + * @iwdev: iwarp device structure + * @rdma_ver: HW version + */ +int irdma_setup_cm_core(struct irdma_device *iwdev, u8 rdma_ver) +{ + struct irdma_cm_core *cm_core = &iwdev->cm_core; + + cm_core->iwdev = iwdev; + cm_core->dev = &iwdev->rf->sc_dev; + + /* Handles CM event work items send to Iwarp core */ + cm_core->event_wq = alloc_ordered_workqueue("iwarp-event-wq", 0); + if (!cm_core->event_wq) + return -ENOMEM; + + INIT_LIST_HEAD(&cm_core->listen_list); + + timer_setup(&cm_core->tcp_timer, irdma_cm_timer_tick, 0); + + spin_lock_init(&cm_core->ht_lock); + spin_lock_init(&cm_core->listen_list_lock); + spin_lock_init(&cm_core->apbvt_lock); + switch (rdma_ver) { + case IRDMA_GEN_1: + cm_core->form_cm_frame = irdma_form_uda_cm_frame; + cm_core->cm_create_ah = irdma_add_qh; + cm_core->cm_free_ah = irdma_cm_free_ah_nop; + break; + case IRDMA_GEN_2: + default: + cm_core->form_cm_frame = irdma_form_ah_cm_frame; + cm_core->cm_create_ah = irdma_cm_create_ah; + cm_core->cm_free_ah = irdma_cm_free_ah; + } + + return 0; +} + +/** + * irdma_cleanup_cm_core - deallocate a top level instance of a + * cm core + * @cm_core: cm's core + */ +void irdma_cleanup_cm_core(struct irdma_cm_core *cm_core) +{ + if (!cm_core) + return; + + del_timer_sync(&cm_core->tcp_timer); + + destroy_workqueue(cm_core->event_wq); + cm_core->dev->ws_reset(&cm_core->iwdev->vsi); +} + +/** + * irdma_init_tcp_ctx - setup qp context + * @cm_node: connection's node + * @tcp_info: offload info for tcp + * @iwqp: associate qp for the connection + */ +static void irdma_init_tcp_ctx(struct irdma_cm_node *cm_node, + struct irdma_tcp_offload_info *tcp_info, + struct irdma_qp *iwqp) +{ + tcp_info->ipv4 = cm_node->ipv4; + tcp_info->drop_ooo_seg = !iwqp->iwdev->iw_ooo; + tcp_info->wscale = true; + tcp_info->ignore_tcp_opt = true; + tcp_info->ignore_tcp_uns_opt = true; + tcp_info->no_nagle = false; + + tcp_info->ttl = IRDMA_DEFAULT_TTL; + tcp_info->rtt_var = IRDMA_DEFAULT_RTT_VAR; + tcp_info->ss_thresh = IRDMA_DEFAULT_SS_THRESH; + tcp_info->rexmit_thresh = IRDMA_DEFAULT_REXMIT_THRESH; + + tcp_info->tcp_state = IRDMA_TCP_STATE_ESTABLISHED; + tcp_info->snd_wscale = cm_node->tcp_cntxt.snd_wscale; + tcp_info->rcv_wscale = cm_node->tcp_cntxt.rcv_wscale; + + tcp_info->snd_nxt = cm_node->tcp_cntxt.loc_seq_num; + tcp_info->snd_wnd = cm_node->tcp_cntxt.snd_wnd; + tcp_info->rcv_nxt = cm_node->tcp_cntxt.rcv_nxt; + tcp_info->snd_max = cm_node->tcp_cntxt.loc_seq_num; + + tcp_info->snd_una = cm_node->tcp_cntxt.loc_seq_num; + tcp_info->cwnd = 2 * cm_node->tcp_cntxt.mss; + tcp_info->snd_wl1 = cm_node->tcp_cntxt.rcv_nxt; + tcp_info->snd_wl2 = cm_node->tcp_cntxt.loc_seq_num; + tcp_info->max_snd_window = cm_node->tcp_cntxt.max_snd_wnd; + tcp_info->rcv_wnd = cm_node->tcp_cntxt.rcv_wnd + << cm_node->tcp_cntxt.rcv_wscale; + + tcp_info->flow_label = 0; + tcp_info->snd_mss = (u32)cm_node->tcp_cntxt.mss; + tcp_info->tos = cm_node->tos; + if (cm_node->vlan_id < VLAN_N_VID) { + tcp_info->insert_vlan_tag = true; + tcp_info->vlan_tag = cm_node->vlan_id; + tcp_info->vlan_tag |= cm_node->user_pri << VLAN_PRIO_SHIFT; + } + tcp_info->src_port = cm_node->loc_port; + tcp_info->dst_port = cm_node->rem_port; + tcp_info->arp_idx = (u16)irdma_arp_table(iwqp->iwdev->rf, + cm_node->rem_addr, NULL, + IRDMA_ARP_RESOLVE); + if (cm_node->ipv4) { + tcp_info->dest_ip_addr[3] = cm_node->rem_addr[0]; + tcp_info->local_ipaddr[3] = cm_node->loc_addr[0]; + } else { + memcpy(tcp_info->dest_ip_addr, cm_node->rem_addr, + sizeof(tcp_info->dest_ip_addr)); + memcpy(tcp_info->local_ipaddr, cm_node->loc_addr, + sizeof(tcp_info->local_ipaddr)); + } +} + +/** + * irdma_cm_init_tsa_conn - setup qp for RTS + * @iwqp: associate qp for the connection + * @cm_node: connection's node + */ +static void irdma_cm_init_tsa_conn(struct irdma_qp *iwqp, + struct irdma_cm_node *cm_node) +{ + struct irdma_iwarp_offload_info *iwarp_info; + struct irdma_qp_host_ctx_info *ctx_info; + + iwarp_info = &iwqp->iwarp_info; + ctx_info = &iwqp->ctx_info; + + ctx_info->tcp_info = &iwqp->tcp_info; + ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id; + ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id; + + iwarp_info->ord_size = cm_node->ord_size; + iwarp_info->ird_size = cm_node->ird_size; + iwarp_info->rd_en = true; + iwarp_info->rdmap_ver = 1; + iwarp_info->ddp_ver = 1; + iwarp_info->pd_id = iwqp->iwpd->sc_pd.pd_id; + + ctx_info->tcp_info_valid = true; + ctx_info->iwarp_info_valid = true; + ctx_info->user_pri = cm_node->user_pri; + + irdma_init_tcp_ctx(cm_node, &iwqp->tcp_info, iwqp); + if (cm_node->snd_mark_en) { + iwarp_info->snd_mark_en = true; + iwarp_info->snd_mark_offset = (iwqp->tcp_info.snd_nxt & SNDMARKER_SEQNMASK) + + cm_node->lsmm_size; + } + + cm_node->state = IRDMA_CM_STATE_OFFLOADED; + iwqp->tcp_info.tcp_state = IRDMA_TCP_STATE_ESTABLISHED; + iwqp->tcp_info.src_mac_addr_idx = iwqp->iwdev->mac_ip_table_idx; + + if (cm_node->rcv_mark_en) { + iwarp_info->rcv_mark_en = true; + iwarp_info->align_hdrs = true; + } + + irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info); + + /* once tcp_info is set, no need to do it again */ + ctx_info->tcp_info_valid = false; + ctx_info->iwarp_info_valid = false; +} + +/** + * irdma_cm_disconn - when a connection is being closed + * @iwqp: associated qp for the connection + */ +void irdma_cm_disconn(struct irdma_qp *iwqp) +{ + struct irdma_device *iwdev = iwqp->iwdev; + struct disconn_work *work; + unsigned long flags; + + work = kzalloc(sizeof(*work), GFP_ATOMIC); + if (!work) + return; + + spin_lock_irqsave(&iwdev->rf->qptable_lock, flags); + if (!iwdev->rf->qp_table[iwqp->ibqp.qp_num]) { + spin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags); + ibdev_dbg(&iwdev->ibdev, + "CM: qp_id %d is already freed\n", + iwqp->ibqp.qp_num); + kfree(work); + return; + } + irdma_qp_add_ref(&iwqp->ibqp); + spin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags); + + work->iwqp = iwqp; + INIT_WORK(&work->work, irdma_disconnect_worker); + queue_work(iwdev->cleanup_wq, &work->work); +} + +/** + * irdma_qp_disconnect - free qp and close cm + * @iwqp: associate qp for the connection + */ +static void irdma_qp_disconnect(struct irdma_qp *iwqp) +{ + struct irdma_device *iwdev = iwqp->iwdev; + + iwqp->active_conn = 0; + /* close the CM node down if it is still active */ + ibdev_dbg(&iwdev->ibdev, "CM: Call close API\n"); + irdma_cm_close(iwqp->cm_node); +} + +/** + * irdma_cm_disconn_true - called by worker thread to disconnect qp + * @iwqp: associate qp for the connection + */ +static void irdma_cm_disconn_true(struct irdma_qp *iwqp) +{ + struct iw_cm_id *cm_id; + struct irdma_device *iwdev; + struct irdma_sc_qp *qp = &iwqp->sc_qp; + u16 last_ae; + u8 original_hw_tcp_state; + u8 original_ibqp_state; + int disconn_status = 0; + int issue_disconn = 0; + int issue_close = 0; + int issue_flush = 0; + unsigned long flags; + int err; + + iwdev = iwqp->iwdev; + spin_lock_irqsave(&iwqp->lock, flags); + if (rdma_protocol_roce(&iwdev->ibdev, 1)) { + struct ib_qp_attr attr; + + if (iwqp->flush_issued || iwqp->sc_qp.qp_uk.destroy_pending) { + spin_unlock_irqrestore(&iwqp->lock, flags); + return; + } + + spin_unlock_irqrestore(&iwqp->lock, flags); + + attr.qp_state = IB_QPS_ERR; + irdma_modify_qp_roce(&iwqp->ibqp, &attr, IB_QP_STATE, NULL); + irdma_ib_qp_event(iwqp, qp->event_type); + return; + } + + cm_id = iwqp->cm_id; + original_hw_tcp_state = iwqp->hw_tcp_state; + original_ibqp_state = iwqp->ibqp_state; + last_ae = iwqp->last_aeq; + + if (qp->term_flags) { + issue_disconn = 1; + issue_close = 1; + iwqp->cm_id = NULL; + irdma_terminate_del_timer(qp); + if (!iwqp->flush_issued) { + iwqp->flush_issued = 1; + issue_flush = 1; + } + } else if ((original_hw_tcp_state == IRDMA_TCP_STATE_CLOSE_WAIT) || + ((original_ibqp_state == IB_QPS_RTS) && + (last_ae == IRDMA_AE_LLP_CONNECTION_RESET))) { + issue_disconn = 1; + if (last_ae == IRDMA_AE_LLP_CONNECTION_RESET) + disconn_status = -ECONNRESET; + } + + if (original_hw_tcp_state == IRDMA_TCP_STATE_CLOSED || + original_hw_tcp_state == IRDMA_TCP_STATE_TIME_WAIT || + last_ae == IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE || + last_ae == IRDMA_AE_BAD_CLOSE || + last_ae == IRDMA_AE_LLP_CONNECTION_RESET || iwdev->rf->reset || !cm_id) { + issue_close = 1; + iwqp->cm_id = NULL; + qp->term_flags = 0; + if (!iwqp->flush_issued) { + iwqp->flush_issued = 1; + issue_flush = 1; + } + } + + spin_unlock_irqrestore(&iwqp->lock, flags); + if (issue_flush && !iwqp->sc_qp.qp_uk.destroy_pending) { + irdma_flush_wqes(iwqp, IRDMA_FLUSH_SQ | IRDMA_FLUSH_RQ | + IRDMA_FLUSH_WAIT); + + if (qp->term_flags) + irdma_ib_qp_event(iwqp, qp->event_type); + } + + if (!cm_id || !cm_id->event_handler) + return; + + spin_lock_irqsave(&iwdev->cm_core.ht_lock, flags); + if (!iwqp->cm_node) { + spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags); + return; + } + refcount_inc(&iwqp->cm_node->refcnt); + + spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags); + + if (issue_disconn) { + err = irdma_send_cm_event(iwqp->cm_node, cm_id, + IW_CM_EVENT_DISCONNECT, + disconn_status); + if (err) + ibdev_dbg(&iwdev->ibdev, + "CM: disconnect event failed: - cm_id = %p\n", + cm_id); + } + if (issue_close) { + cm_id->provider_data = iwqp; + err = irdma_send_cm_event(iwqp->cm_node, cm_id, + IW_CM_EVENT_CLOSE, 0); + if (err) + ibdev_dbg(&iwdev->ibdev, + "CM: close event failed: - cm_id = %p\n", + cm_id); + irdma_qp_disconnect(iwqp); + } + irdma_rem_ref_cm_node(iwqp->cm_node); +} + +/** + * irdma_disconnect_worker - worker for connection close + * @work: points or disconn structure + */ +static void irdma_disconnect_worker(struct work_struct *work) +{ + struct disconn_work *dwork = container_of(work, struct disconn_work, work); + struct irdma_qp *iwqp = dwork->iwqp; + + kfree(dwork); + irdma_cm_disconn_true(iwqp); + irdma_qp_rem_ref(&iwqp->ibqp); +} + +/** + * irdma_free_lsmm_rsrc - free lsmm memory and deregister + * @iwqp: associate qp for the connection + */ +void irdma_free_lsmm_rsrc(struct irdma_qp *iwqp) +{ + struct irdma_device *iwdev; + + iwdev = iwqp->iwdev; + + if (iwqp->ietf_mem.va) { + if (iwqp->lsmm_mr) + kc_free_lsmm_dereg_mr(iwdev, iwqp); + dma_free_coherent(iwdev->rf->sc_dev.hw->device, + iwqp->ietf_mem.size, iwqp->ietf_mem.va, + iwqp->ietf_mem.pa); + iwqp->ietf_mem.va = NULL; + iwqp->ietf_mem.va = NULL; + } +} + +/** + * irdma_accept - registered call for connection to be accepted + * @cm_id: cm information for passive connection + * @conn_param: accpet parameters + */ +int irdma_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param) +{ + struct ib_qp *ibqp; + struct irdma_qp *iwqp; + struct irdma_device *iwdev; + struct irdma_sc_dev *dev; + struct irdma_cm_node *cm_node; + struct ib_qp_attr attr = {}; + int passive_state; + struct ib_mr *ibmr; + struct irdma_pd *iwpd; + u16 buf_len = 0; + struct irdma_kmem_info accept; + u64 tagged_offset; + int wait_ret; + int ret = 0; + + ibqp = irdma_get_qp(cm_id->device, conn_param->qpn); + if (!ibqp) + return -EINVAL; + + iwqp = to_iwqp(ibqp); + iwdev = iwqp->iwdev; + dev = &iwdev->rf->sc_dev; + cm_node = cm_id->provider_data; + + if (((struct sockaddr_in *)&cm_id->local_addr)->sin_family == AF_INET) { + cm_node->ipv4 = true; + cm_node->vlan_id = irdma_get_vlan_ipv4(cm_node->loc_addr); + } else { + cm_node->ipv4 = false; + irdma_get_vlan_mac_ipv6(cm_node->loc_addr, &cm_node->vlan_id, + NULL); + } + ibdev_dbg(&iwdev->ibdev, "CM: Accept vlan_id=%d\n", + cm_node->vlan_id); + + trace_irdma_accept(cm_node, 0, NULL); + + if (cm_node->state == IRDMA_CM_STATE_LISTENER_DESTROYED) { + ret = -EINVAL; + goto error; + } + + passive_state = atomic_add_return(1, &cm_node->passive_state); + if (passive_state == IRDMA_SEND_RESET_EVENT) { + ret = -ECONNRESET; + goto error; + } + + buf_len = conn_param->private_data_len + IRDMA_MAX_IETF_SIZE; + iwqp->ietf_mem.size = ALIGN(buf_len, 1); + iwqp->ietf_mem.va = dma_alloc_coherent(dev->hw->device, + iwqp->ietf_mem.size, + &iwqp->ietf_mem.pa, GFP_KERNEL); + if (!iwqp->ietf_mem.va) { + ret = -ENOMEM; + goto error; + } + + cm_node->pdata.size = conn_param->private_data_len; + accept.addr = iwqp->ietf_mem.va; + accept.size = irdma_cm_build_mpa_frame(cm_node, &accept, MPA_KEY_REPLY); + memcpy((u8 *)accept.addr + accept.size, conn_param->private_data, + conn_param->private_data_len); + + if (cm_node->dev->ws_add(iwqp->sc_qp.vsi, cm_node->user_pri)) { + ret = -ENOMEM; + goto error; + } + iwqp->sc_qp.user_pri = cm_node->user_pri; + irdma_qp_add_qos(&iwqp->sc_qp); + if (cm_node->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2 && + dev->privileged) + iwdev->rf->check_fc(&iwdev->vsi, &iwqp->sc_qp); + /* setup our first outgoing iWarp send WQE (the IETF frame response) */ + iwpd = iwqp->iwpd; + tagged_offset = (uintptr_t)iwqp->ietf_mem.va; + ibmr = irdma_reg_phys_mr(&iwpd->ibpd, iwqp->ietf_mem.pa, buf_len, + IB_ACCESS_LOCAL_WRITE, &tagged_offset); + if (IS_ERR(ibmr)) { + ret = -ENOMEM; + goto error; + } + + ibmr->pd = &iwpd->ibpd; + ibmr->device = iwpd->ibpd.device; + iwqp->lsmm_mr = ibmr; + if (iwqp->page) + iwqp->sc_qp.qp_uk.sq_base = kmap_local_page(iwqp->page); + + cm_node->lsmm_size = accept.size + conn_param->private_data_len; + irdma_sc_send_lsmm(&iwqp->sc_qp, iwqp->ietf_mem.va, cm_node->lsmm_size, + ibmr->lkey); + + if (iwqp->page) + kunmap_local(iwqp->sc_qp.qp_uk.sq_base); + + iwqp->cm_id = cm_id; + cm_node->cm_id = cm_id; + + cm_id->provider_data = iwqp; + iwqp->active_conn = 0; + iwqp->cm_node = cm_node; + cm_node->iwqp = iwqp; + irdma_cm_init_tsa_conn(iwqp, cm_node); + irdma_qp_add_ref(&iwqp->ibqp); + cm_id->add_ref(cm_id); + + attr.qp_state = IB_QPS_RTS; + cm_node->qhash_set = false; + cm_node->cm_core->cm_free_ah(cm_node); + + irdma_modify_qp(&iwqp->ibqp, &attr, IB_QP_STATE, NULL); + if (dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) { + wait_ret = wait_event_interruptible_timeout(iwqp->waitq, + iwqp->rts_ae_rcvd, + IRDMA_MAX_TIMEOUT); + if (!wait_ret) { + ibdev_dbg(&iwdev->ibdev, + "CM: Slow Connection: cm_node=%p, loc_port=%d, rem_port=%d, cm_id=%p\n", + cm_node, cm_node->loc_port, + cm_node->rem_port, cm_node->cm_id); + ret = -ECONNRESET; + goto error; + } + } + + irdma_send_cm_event(cm_node, cm_id, IW_CM_EVENT_ESTABLISHED, 0); + cm_node->accelerated = true; + complete(&cm_node->establish_comp); + + if (cm_node->accept_pend) { + atomic_dec(&cm_node->listener->pend_accepts_cnt); + cm_node->accept_pend = 0; + } + + ibdev_dbg(&iwdev->ibdev, + "CM: rem_port=0x%04x, loc_port=0x%04x rem_addr=%pI4 loc_addr=%pI4 cm_node=%p cm_id=%p qp_id=%d\n\n", + cm_node->rem_port, cm_node->loc_port, cm_node->rem_addr, + cm_node->loc_addr, cm_node, cm_id, ibqp->qp_num); + cm_node->cm_core->stats_accepts++; + + return 0; +error: + irdma_free_lsmm_rsrc(iwqp); + irdma_rem_ref_cm_node(cm_node); + + return ret; +} + +/** + * irdma_reject - registered call for connection to be rejected + * @cm_id: cm information for passive connection + * @pdata: private data to be sent + * @pdata_len: private data length + */ +int irdma_reject(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len) +{ + struct irdma_device *iwdev; + struct irdma_cm_node *cm_node; + + cm_node = cm_id->provider_data; + cm_node->pdata.size = pdata_len; + + trace_irdma_reject(cm_node, 0, NULL); + + iwdev = to_iwdev(cm_id->device); + if (!iwdev) + return -EINVAL; + + cm_node->cm_core->stats_rejects++; + + if (pdata_len + sizeof(struct ietf_mpa_v2) > IRDMA_MAX_CM_BUF) + return -EINVAL; + + return irdma_cm_reject(cm_node, pdata, pdata_len); +} + +/** + * irdma_connect - registered call for connection to be established + * @cm_id: cm information for passive connection + * @conn_param: Information about the connection + */ +int irdma_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param) +{ + struct ib_qp *ibqp; + struct irdma_qp *iwqp; + struct irdma_device *iwdev; + struct irdma_cm_node *cm_node; + struct irdma_cm_info cm_info; + struct sockaddr_in *laddr; + struct sockaddr_in *raddr; + struct sockaddr_in6 *laddr6; + struct sockaddr_in6 *raddr6; + int ret = 0; + + ibqp = irdma_get_qp(cm_id->device, conn_param->qpn); + if (!ibqp) + return -EINVAL; + iwqp = to_iwqp(ibqp); + if (!iwqp) + return -EINVAL; + iwdev = iwqp->iwdev; + if (!iwdev) + return -EINVAL; + + laddr = (struct sockaddr_in *)&cm_id->m_local_addr; + raddr = (struct sockaddr_in *)&cm_id->m_remote_addr; + laddr6 = (struct sockaddr_in6 *)&cm_id->m_local_addr; + raddr6 = (struct sockaddr_in6 *)&cm_id->m_remote_addr; + + if (!(laddr->sin_port) || !(raddr->sin_port)) + return -EINVAL; + + iwqp->active_conn = 1; + iwqp->cm_id = NULL; + cm_id->provider_data = iwqp; + + /* set up the connection params for the node */ + if (cm_id->remote_addr.ss_family == AF_INET) { + if (iwdev->vsi.mtu < IRDMA_MIN_MTU_IPV4) + return -EINVAL; + + cm_info.ipv4 = true; + memset(cm_info.loc_addr, 0, sizeof(cm_info.loc_addr)); + memset(cm_info.rem_addr, 0, sizeof(cm_info.rem_addr)); + cm_info.loc_addr[0] = ntohl(laddr->sin_addr.s_addr); + cm_info.rem_addr[0] = ntohl(raddr->sin_addr.s_addr); + cm_info.loc_port = ntohs(laddr->sin_port); + cm_info.rem_port = ntohs(raddr->sin_port); + cm_info.vlan_id = irdma_get_vlan_ipv4(cm_info.loc_addr); + } else { + if (iwdev->vsi.mtu < IRDMA_MIN_MTU_IPV6) + return -EINVAL; + + cm_info.ipv4 = false; + irdma_copy_ip_ntohl(cm_info.loc_addr, + laddr6->sin6_addr.in6_u.u6_addr32); + irdma_copy_ip_ntohl(cm_info.rem_addr, + raddr6->sin6_addr.in6_u.u6_addr32); + cm_info.loc_port = ntohs(laddr6->sin6_port); + cm_info.rem_port = ntohs(raddr6->sin6_port); + irdma_get_vlan_mac_ipv6(cm_info.loc_addr, &cm_info.vlan_id, NULL); + } + cm_info.cm_id = cm_id; + cm_info.qh_qpid = iwdev->vsi.ilq->qp_id; + cm_info.tos = cm_id->tos; + if (iwdev->vsi.dscp_mode) { + cm_info.user_pri = + iwqp->sc_qp.vsi->dscp_map[irdma_tos2dscp(cm_info.tos)]; + } else { + cm_info.user_pri = rt_tos2priority(cm_id->tos); + cm_info.user_pri = + irdma_iw_get_vlan_prio(cm_info.loc_addr, + cm_info.user_pri, + cm_info.ipv4); + } + + if (iwqp->sc_qp.dev->ws_add(iwqp->sc_qp.vsi, cm_info.user_pri)) + return -ENOMEM; + iwqp->sc_qp.user_pri = cm_info.user_pri; + irdma_qp_add_qos(&iwqp->sc_qp); + if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2 && + iwdev->rf->sc_dev.privileged) + iwdev->rf->check_fc(&iwdev->vsi, &iwqp->sc_qp); + ibdev_dbg(&iwdev->ibdev, "DCB: TOS:[%d] UP:[%d]\n", cm_id->tos, + cm_info.user_pri); + + trace_irdma_dcb_tos(iwdev, cm_id->tos, cm_info.user_pri); + + ret = irdma_create_cm_node(&iwdev->cm_core, iwdev, conn_param, &cm_info, + &cm_node); + if (ret) + return ret; + ret = cm_node->cm_core->cm_create_ah(cm_node, true); + if (ret) + goto err; + if (irdma_manage_qhash(iwdev, &cm_info, + IRDMA_QHASH_TYPE_TCP_ESTABLISHED, + IRDMA_QHASH_MANAGE_TYPE_ADD, NULL, true)) { + ret = -EINVAL; + goto err; + } + cm_node->qhash_set = true; + + cm_node->apbvt_entry = irdma_add_apbvt(iwdev, cm_info.loc_port); + if (!cm_node->apbvt_entry) { + ret = -EINVAL; + goto err; + } + + cm_node->apbvt_set = true; + iwqp->cm_node = cm_node; + cm_node->iwqp = iwqp; + iwqp->cm_id = cm_id; + irdma_qp_add_ref(&iwqp->ibqp); + cm_id->add_ref(cm_id); + + if (cm_node->state != IRDMA_CM_STATE_OFFLOADED) { + cm_node->state = IRDMA_CM_STATE_SYN_SENT; + ret = irdma_send_syn(cm_node, 0); + if (ret) + goto err; + } + + ibdev_dbg(&iwdev->ibdev, + "CM: rem_port=0x%04x, loc_port=0x%04x rem_addr=%pI4 loc_addr=%pI4 cm_node=%p cm_id=%p qp_id = %d\n\n", + cm_node->rem_port, cm_node->loc_port, cm_node->rem_addr, + cm_node->loc_addr, cm_node, cm_id, ibqp->qp_num); + + trace_irdma_connect(cm_node, 0, NULL); + + return 0; + +err: + if (cm_info.ipv4) + ibdev_dbg(&iwdev->ibdev, + "CM: connect() FAILED: dest addr=%pI4", + cm_info.rem_addr); + else + ibdev_dbg(&iwdev->ibdev, + "CM: connect() FAILED: dest addr=%pI6", + cm_info.rem_addr); + irdma_rem_ref_cm_node(cm_node); + iwdev->cm_core.stats_connect_errs++; + + return ret; +} + +/** + * irdma_create_listen - registered call creating listener + * @cm_id: cm information for passive connection + * @backlog: to max accept pending count + */ +int irdma_create_listen(struct iw_cm_id *cm_id, int backlog) +{ + struct irdma_device *iwdev; + struct irdma_cm_listener *cm_listen_node; + struct irdma_cm_info cm_info = {}; + struct sockaddr_in *laddr; + struct sockaddr_in6 *laddr6; + bool wildcard = false; + int err; + + iwdev = to_iwdev(cm_id->device); + if (!iwdev) + return -EINVAL; + + laddr = (struct sockaddr_in *)&cm_id->m_local_addr; + laddr6 = (struct sockaddr_in6 *)&cm_id->m_local_addr; + cm_info.qh_qpid = iwdev->vsi.ilq->qp_id; + + if (laddr->sin_family == AF_INET) { + if (iwdev->vsi.mtu < IRDMA_MIN_MTU_IPV4) + return -EINVAL; + + cm_info.ipv4 = true; + cm_info.loc_addr[0] = ntohl(laddr->sin_addr.s_addr); + cm_info.loc_port = ntohs(laddr->sin_port); + + if (laddr->sin_addr.s_addr != htonl(INADDR_ANY)) { + cm_info.vlan_id = irdma_get_vlan_ipv4(cm_info.loc_addr); + } else { + cm_info.vlan_id = 0xFFFF; + wildcard = true; + } + } else { + if (iwdev->vsi.mtu < IRDMA_MIN_MTU_IPV6) + return -EINVAL; + + cm_info.ipv4 = false; + irdma_copy_ip_ntohl(cm_info.loc_addr, + laddr6->sin6_addr.in6_u.u6_addr32); + cm_info.loc_port = ntohs(laddr6->sin6_port); + if (ipv6_addr_type(&laddr6->sin6_addr) != IPV6_ADDR_ANY) { + irdma_get_vlan_mac_ipv6(cm_info.loc_addr, + &cm_info.vlan_id, NULL); + } else { + cm_info.vlan_id = 0xFFFF; + wildcard = true; + } + } + + if (cm_info.vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode) + cm_info.vlan_id = 0; + cm_info.backlog = backlog; + cm_info.cm_id = cm_id; + + trace_irdma_create_listen(iwdev, &cm_info); + + cm_listen_node = irdma_make_listen_node(&iwdev->cm_core, iwdev, + &cm_info); + if (!cm_listen_node) { + ibdev_dbg(&iwdev->ibdev, + "CM: cm_listen_node == NULL\n"); + return -ENOMEM; + } + + cm_id->provider_data = cm_listen_node; + + cm_listen_node->tos = cm_id->tos; + if (iwdev->vsi.dscp_mode) + cm_listen_node->user_pri = + iwdev->vsi.dscp_map[irdma_tos2dscp(cm_id->tos)]; + else + cm_listen_node->user_pri = rt_tos2priority(cm_id->tos); + cm_info.user_pri = cm_listen_node->user_pri; + if (!cm_listen_node->reused_node) { + if (wildcard) { + err = irdma_add_mqh(iwdev, &cm_info, cm_listen_node); + if (err) + goto error; + } else { + if (!iwdev->vsi.dscp_mode) + cm_info.user_pri = cm_listen_node->user_pri = + irdma_iw_get_vlan_prio(cm_info.loc_addr, + cm_info.user_pri, + cm_info.ipv4); + err = irdma_manage_qhash(iwdev, &cm_info, + IRDMA_QHASH_TYPE_TCP_SYN, + IRDMA_QHASH_MANAGE_TYPE_ADD, + NULL, true); + if (err) + goto error; + + cm_listen_node->qhash_set = true; + } + + cm_listen_node->apbvt_entry = irdma_add_apbvt(iwdev, + cm_info.loc_port); + if (!cm_listen_node->apbvt_entry) + goto error; + } + cm_id->add_ref(cm_id); + cm_listen_node->cm_core->stats_listen_created++; + ibdev_dbg(&iwdev->ibdev, + "CM: loc_port=0x%04x loc_addr=%pI4 cm_listen_node=%p cm_id=%p qhash_set=%d vlan_id=%d\n", + cm_listen_node->loc_port, cm_listen_node->loc_addr, + cm_listen_node, cm_listen_node->cm_id, + cm_listen_node->qhash_set, cm_listen_node->vlan_id); + + return 0; + +error: + + irdma_cm_del_listen(&iwdev->cm_core, cm_listen_node, false); + + return -EINVAL; +} + +/** + * irdma_destroy_listen - registered call to destroy listener + * @cm_id: cm information for passive connection + */ +int irdma_destroy_listen(struct iw_cm_id *cm_id) +{ + struct irdma_device *iwdev; + + iwdev = to_iwdev(cm_id->device); + if (cm_id->provider_data) + irdma_cm_del_listen(&iwdev->cm_core, cm_id->provider_data, + true); + else + ibdev_dbg(&iwdev->ibdev, + "CM: cm_id->provider_data was NULL\n"); + + cm_id->rem_ref(cm_id); + + return 0; +} + +/** + * irdma_iw_teardown_list_prep - add conn nodes slated for tear + * down to list + * @cm_core: cm's core + * @teardown_list: a list to which cm_node will be selected + * @ipaddr: pointer to ip address + * @nfo: pointer to cm_info structure instance + * @disconnect_all: flag indicating disconnect all QPs + */ +static void irdma_iw_teardown_list_prep(struct irdma_cm_core *cm_core, + struct list_head *teardown_list, + u32 *ipaddr, + struct irdma_cm_info *nfo, + bool disconnect_all) +{ + struct irdma_cm_node *cm_node; + int bkt; + + hash_for_each_rcu(cm_core->cm_hash_tbl, bkt, cm_node, list) { + if ((disconnect_all || + (nfo->vlan_id == cm_node->vlan_id && + !memcmp(cm_node->loc_addr, ipaddr, nfo->ipv4 ? 4 : 16))) && + refcount_inc_not_zero(&cm_node->refcnt)) + list_add(&cm_node->teardown_entry, teardown_list); + } +} + +static inline bool irdma_ip_vlan_match(u32 *ip1, u16 vlan_id1, + bool check_vlan, u32 *ip2, + u16 vlan_id2, bool ipv4) +{ + return (!check_vlan || vlan_id1 == vlan_id2) && + !memcmp(ip1, ip2, ipv4 ? 4 : 16); +} + +/** + * irdma_roce_teardown_list_prep - add conn nodes slated for + * tear down to list + * @iwdev: RDMA device + * @teardown_list: a list to which cm_node will be selected + * @ipaddr: pointer to ip address + * @nfo: pointer to cm_info structure instance + * @disconnect_all: flag indicating disconnect all QPs + */ +static void irdma_roce_teardown_list_prep(struct irdma_device *iwdev, + struct list_head *teardown_list, + u32 *ipaddr, + struct irdma_cm_info *nfo, + bool disconnect_all) +{ + struct irdma_sc_vsi *vsi = &iwdev->vsi; + struct irdma_sc_qp *sc_qp; + struct list_head *list_node; + struct irdma_qp *qp; + unsigned long flags; + int i; + + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + mutex_lock(&vsi->qos[i].qos_mutex); + list_for_each (list_node, &vsi->qos[i].qplist) { + u32 qp_ip[4]; + + sc_qp = container_of(list_node, struct irdma_sc_qp, + list); + if (sc_qp->qp_uk.qp_type != IRDMA_QP_TYPE_ROCE_RC) + continue; + + qp = sc_qp->qp_uk.back_qp; + if (!disconnect_all) { + if (nfo->ipv4) + qp_ip[0] = qp->udp_info.local_ipaddr[3]; + else + memcpy(qp_ip, + &qp->udp_info.local_ipaddr[0], + sizeof(qp_ip)); + } + + if (disconnect_all || + irdma_ip_vlan_match(qp_ip, + qp->udp_info.vlan_tag & VLAN_VID_MASK, + qp->udp_info.insert_vlan_tag, + ipaddr, nfo->vlan_id, nfo->ipv4)) { + spin_lock_irqsave(&iwdev->rf->qptable_lock, flags); + if (iwdev->rf->qp_table[sc_qp->qp_uk.qp_id]) { + irdma_qp_add_ref(&qp->ibqp); + list_add(&qp->teardown_entry, teardown_list); + } + spin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags); + } + } + mutex_unlock(&vsi->qos[i].qos_mutex); + } +} + +/** + * irdma_cm_event_connected - handle connected active node + * @event: the info for cm_node of connection + */ +static void irdma_cm_event_connected(struct irdma_cm_event *event) +{ + struct irdma_qp *iwqp; + struct irdma_device *iwdev; + struct irdma_cm_node *cm_node; + struct irdma_sc_dev *dev; + struct ib_qp_attr attr = {}; + struct iw_cm_id *cm_id; + int status; + bool read0; + int wait_ret = 0; + + cm_node = event->cm_node; + cm_id = cm_node->cm_id; + iwqp = cm_id->provider_data; + iwdev = iwqp->iwdev; + dev = &iwdev->rf->sc_dev; + if (iwqp->sc_qp.qp_uk.destroy_pending) { + status = -ETIMEDOUT; + goto error; + } + + irdma_cm_init_tsa_conn(iwqp, cm_node); + read0 = (cm_node->send_rdma0_op == SEND_RDMA_READ_ZERO); + if (iwqp->page) + iwqp->sc_qp.qp_uk.sq_base = kmap_local_page(iwqp->page); + irdma_sc_send_rtt(&iwqp->sc_qp, read0); + if (iwqp->page) + kunmap_local(iwqp->sc_qp.qp_uk.sq_base); + + attr.qp_state = IB_QPS_RTS; + cm_node->qhash_set = false; + irdma_modify_qp(&iwqp->ibqp, &attr, IB_QP_STATE, NULL); + if (dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) { + wait_ret = wait_event_interruptible_timeout(iwqp->waitq, + iwqp->rts_ae_rcvd, + IRDMA_MAX_TIMEOUT); + if (!wait_ret) + ibdev_dbg(&iwdev->ibdev, + "CM: Slow Connection: cm_node=%p, loc_port=%d, rem_port=%d, cm_id=%p\n", + cm_node, cm_node->loc_port, + cm_node->rem_port, cm_node->cm_id); + } + + irdma_send_cm_event(cm_node, cm_id, IW_CM_EVENT_CONNECT_REPLY, 0); + cm_node->accelerated = true; + complete(&cm_node->establish_comp); + cm_node->cm_core->cm_free_ah(cm_node); + return; + +error: + iwqp->cm_id = NULL; + cm_id->provider_data = NULL; + irdma_send_cm_event(event->cm_node, cm_id, IW_CM_EVENT_CONNECT_REPLY, + status); + irdma_rem_ref_cm_node(event->cm_node); +} + +/** + * irdma_cm_event_reset - handle reset + * @event: the info for cm_node of connection + */ +static void irdma_cm_event_reset(struct irdma_cm_event *event) +{ + struct irdma_cm_node *cm_node = event->cm_node; + struct iw_cm_id *cm_id = cm_node->cm_id; + struct irdma_qp *iwqp; + + if (!cm_id) + return; + + iwqp = cm_id->provider_data; + if (!iwqp) + return; + + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: reset event %p - cm_id = %p\n", event->cm_node, cm_id); + iwqp->cm_id = NULL; + + irdma_send_cm_event(cm_node, cm_node->cm_id, IW_CM_EVENT_DISCONNECT, + -ECONNRESET); + irdma_send_cm_event(cm_node, cm_node->cm_id, IW_CM_EVENT_CLOSE, 0); +} + +/** + * irdma_cm_event_handler - send event to cm upper layer + * @work: pointer of cm event info. + */ +static void irdma_cm_event_handler(struct work_struct *work) +{ + struct irdma_cm_event *event = container_of(work, struct irdma_cm_event, event_work); + struct irdma_cm_node *cm_node; + + if (!event || !event->cm_node || !event->cm_node->cm_core) + return; + + cm_node = event->cm_node; + trace_irdma_cm_event_handler(cm_node, event->type, NULL); + + switch (event->type) { + case IRDMA_CM_EVENT_MPA_REQ: + irdma_send_cm_event(cm_node, cm_node->cm_id, + IW_CM_EVENT_CONNECT_REQUEST, 0); + break; + case IRDMA_CM_EVENT_RESET: + irdma_cm_event_reset(event); + break; + case IRDMA_CM_EVENT_CONNECTED: + if (!event->cm_node->cm_id || + event->cm_node->state != IRDMA_CM_STATE_OFFLOADED) + break; + irdma_cm_event_connected(event); + break; + case IRDMA_CM_EVENT_MPA_REJECT: + if (!event->cm_node->cm_id || + cm_node->state == IRDMA_CM_STATE_OFFLOADED) + break; + irdma_send_cm_event(cm_node, cm_node->cm_id, + IW_CM_EVENT_CONNECT_REPLY, -ECONNREFUSED); + break; + case IRDMA_CM_EVENT_ABORTED: + if (!event->cm_node->cm_id || + event->cm_node->state == IRDMA_CM_STATE_OFFLOADED) + break; + irdma_event_connect_error(event); + break; + default: + ibdev_dbg(&cm_node->iwdev->ibdev, + "CM: bad event type = %d\n", event->type); + break; + } + + irdma_rem_ref_cm_node(event->cm_node); + kfree(event); +} + +/** + * irdma_cm_post_event - queue event request for worker thread + * @event: cm node's info for up event call + */ +static void irdma_cm_post_event(struct irdma_cm_event *event) +{ + refcount_inc(&event->cm_node->refcnt); + INIT_WORK(&event->event_work, irdma_cm_event_handler); + queue_work(event->cm_node->cm_core->event_wq, &event->event_work); +} + +/** + * irdma_cm_teardown_connections - teardown QPs + * @iwdev: device pointer + * @ipaddr: Pointer to IPv4 or IPv6 address + * @nfo: Connection info + * @disconnect_all: flag indicating disconnect all QPs + * + * teardown QPs where source or destination addr matches ip addr + */ +static void irdma_cm_teardown_connections(struct irdma_device *iwdev, + u32 *ipaddr, + struct irdma_cm_info *nfo, + bool disconnect_all) +{ + struct irdma_cm_core *cm_core = &iwdev->cm_core; + struct list_head *list_core_temp; + struct list_head *list_node; + struct irdma_cm_node *cm_node; + struct list_head teardown_list; + struct ib_qp_attr attr; + struct irdma_qp *qp; + + INIT_LIST_HEAD(&teardown_list); + + rcu_read_lock(); + irdma_iw_teardown_list_prep(cm_core, &teardown_list, ipaddr, nfo, disconnect_all); + rcu_read_unlock(); + + attr.qp_state = IB_QPS_ERR; + list_for_each_safe (list_node, list_core_temp, &teardown_list) { + cm_node = container_of(list_node, struct irdma_cm_node, + teardown_entry); + irdma_modify_qp(&cm_node->iwqp->ibqp, &attr, IB_QP_STATE, NULL); + if (iwdev->rf->reset) + irdma_cm_disconn(cm_node->iwqp); + irdma_rem_ref_cm_node(cm_node); + } + + if (!rdma_protocol_roce(&iwdev->ibdev, 1)) + return; + + INIT_LIST_HEAD(&teardown_list); + irdma_roce_teardown_list_prep(iwdev, &teardown_list, ipaddr, nfo, disconnect_all); + + list_for_each_safe (list_node, list_core_temp, &teardown_list) { + qp = container_of(list_node, struct irdma_qp, teardown_entry); + irdma_modify_qp_roce(&qp->ibqp, &attr, IB_QP_STATE, NULL); + irdma_ib_qp_event(qp, IRDMA_QP_EVENT_CATASTROPHIC); + irdma_qp_rem_ref(&qp->ibqp); + } +} + +/** + * irdma_qhash_ctrl - enable/disable qhash for list + * @iwdev: device pointer + * @parent_listen_node: parent listen node + * @nfo: cm info node + * @ipaddr: Pointer to IPv4 or IPv6 address + * @ipv4: flag indicating IPv4 when true + * @ifup: flag indicating interface up when true + * + * Enables or disables the qhash for the node in the child + * listen list that matches ipaddr. If no matching IP was found + * it will allocate and add a new child listen node to the + * parent listen node. The listen_list_lock is assumed to be + * held when called. + */ +static void irdma_qhash_ctrl(struct irdma_device *iwdev, + struct irdma_cm_listener *parent_listen_node, + struct irdma_cm_info *nfo, u32 *ipaddr, bool ipv4, + bool ifup) +{ + struct list_head *child_listen_list = &parent_listen_node->child_listen_list; + struct irdma_cm_listener *child_listen_node; + struct list_head *pos, *tpos; + bool node_allocated = false; + enum irdma_quad_hash_manage_type op = ifup ? + IRDMA_QHASH_MANAGE_TYPE_ADD : + IRDMA_QHASH_MANAGE_TYPE_DELETE; + int err; + + list_for_each_safe (pos, tpos, child_listen_list) { + child_listen_node = list_entry(pos, struct irdma_cm_listener, + child_listen_list); + if (!memcmp(child_listen_node->loc_addr, ipaddr, ipv4 ? 4 : 16)) + goto set_qhash; + } + + /* if not found then add a child listener if interface is going up */ + if (!ifup) + return; + child_listen_node = kmemdup(parent_listen_node, + sizeof(*child_listen_node), GFP_ATOMIC); + if (!child_listen_node) + return; + + node_allocated = true; + memcpy(child_listen_node->loc_addr, ipaddr, ipv4 ? 4 : 16); + +set_qhash: + memcpy(nfo->loc_addr, child_listen_node->loc_addr, + sizeof(nfo->loc_addr)); + nfo->vlan_id = child_listen_node->vlan_id; + err = irdma_manage_qhash(iwdev, nfo, IRDMA_QHASH_TYPE_TCP_SYN, op, NULL, + false); + if (!err) { + child_listen_node->qhash_set = ifup; + if (node_allocated) + list_add(&child_listen_node->child_listen_list, + &parent_listen_node->child_listen_list); + } else if (node_allocated) { + kfree(child_listen_node); + } +} + +/** + * irdma_if_notify - process an ifdown on an interface + * @iwdev: device pointer + * @vlan_id: VLAN ID of the netdev + * @ipaddr: Pointer to IPv4 or IPv6 address + * @ipv4: flag indicating IPv4 when true + * @ifup: flag indicating interface up when true + */ +static void irdma_if_notify(struct irdma_device *iwdev, u16 vlan_id, + u32 *ipaddr, bool ipv4, bool ifup) +{ + struct irdma_cm_core *cm_core = &iwdev->cm_core; + unsigned long flags; + struct irdma_cm_listener *listen_node; + static const u32 ip_zero[4] = { 0, 0, 0, 0 }; + struct irdma_cm_info nfo = {}; + enum irdma_quad_hash_manage_type op = ifup ? + IRDMA_QHASH_MANAGE_TYPE_ADD : + IRDMA_QHASH_MANAGE_TYPE_DELETE; + + nfo.vlan_id = vlan_id; + nfo.ipv4 = ipv4; + nfo.qh_qpid = 1; + + /* Disable or enable qhash for listeners */ + spin_lock_irqsave(&cm_core->listen_list_lock, flags); + list_for_each_entry (listen_node, &cm_core->listen_list, list) { + if (vlan_id != listen_node->vlan_id || + (memcmp(listen_node->loc_addr, ipaddr, ipv4 ? 4 : 16) && + memcmp(listen_node->loc_addr, ip_zero, ipv4 ? 4 : 16))) + continue; + + memcpy(nfo.loc_addr, listen_node->loc_addr, + sizeof(nfo.loc_addr)); + nfo.loc_port = listen_node->loc_port; + nfo.user_pri = listen_node->user_pri; + if (!list_empty(&listen_node->child_listen_list)) { + irdma_qhash_ctrl(iwdev, listen_node, &nfo, ipaddr, ipv4, + ifup); + } else if (memcmp(listen_node->loc_addr, ip_zero, + ipv4 ? 4 : 16)) { + if (!irdma_manage_qhash(iwdev, &nfo, + IRDMA_QHASH_TYPE_TCP_SYN, op, + NULL, false)) + listen_node->qhash_set = ifup; + } + } + spin_unlock_irqrestore(&cm_core->listen_list_lock, flags); + + /* disconnect any connected qp's on ifdown */ + if (!ifup) + irdma_cm_teardown_connections(iwdev, ipaddr, &nfo, false); +} + +void irdma_if_notify_worker(struct work_struct *work) +{ + struct if_notify_work *iwork = + container_of(work, struct if_notify_work, work); + + irdma_if_notify(iwork->iwdev, iwork->vlan_id, iwork->ipaddr, iwork->ipv4, + iwork->ifup); + kfree(iwork); +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/cm.h b/drivers/intel/irdma-1.14.33/src/irdma/cm.h new file mode 100644 index 000000000..943362cac --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/cm.h @@ -0,0 +1,410 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef IRDMA_CM_H +#define IRDMA_CM_H + +#define IRDMA_MPA_REQUEST_ACCEPT 1 +#define IRDMA_MPA_REQUEST_REJECT 2 + +/* IETF MPA -- defines */ +#define IEFT_MPA_KEY_REQ "MPA ID Req Frame" +#define IEFT_MPA_KEY_REP "MPA ID Rep Frame" +#define IETF_MPA_KEY_SIZE 16 +#define IETF_MPA_VER 1 +#define IETF_MAX_PRIV_DATA_LEN 512 +#define IETF_MPA_FRAME_SIZE 20 +#define IETF_RTR_MSG_SIZE 4 +#define IETF_MPA_V2_FLAG 0x10 +#define SNDMARKER_SEQNMASK 0x000001ff +#define IRDMA_MAX_IETF_SIZE 32 + +/* IETF RTR MSG Fields */ +#define IETF_PEER_TO_PEER 0x8000 +#define IETF_FLPDU_ZERO_LEN 0x4000 +#define IETF_RDMA0_WRITE 0x8000 +#define IETF_RDMA0_READ 0x4000 +#define IETF_NO_IRD_ORD 0x3fff + +#define MAX_PORTS 65536 + +#define IRDMA_PASSIVE_STATE_INDICATED 0 +#define IRDMA_DO_NOT_SEND_RESET_EVENT 1 +#define IRDMA_SEND_RESET_EVENT 2 + +#define MAX_IRDMA_IFS 4 + +#define SET_ACK 1 +#define SET_SYN 2 +#define SET_FIN 4 +#define SET_RST 8 + +#define TCP_OPTIONS_PADDING 3 + +#define IRDMA_DEFAULT_RETRYS 64 +#define IRDMA_DEFAULT_RETRANS 32 +#define IRDMA_DEFAULT_TTL 0x40 +#define IRDMA_DEFAULT_RTT_VAR 6 +#define IRDMA_DEFAULT_SS_THRESH 0x3fffffff +#define IRDMA_DEFAULT_REXMIT_THRESH 8 + +#define IRDMA_RETRY_TIMEOUT HZ +#define IRDMA_SHORT_TIME 10 +#define IRDMA_LONG_TIME (2 * HZ) +#define IRDMA_MAX_TIMEOUT ((unsigned long)(12 * HZ)) + +#define IRDMA_CM_HASHTABLE_SIZE 1024 +#define IRDMA_CM_TCP_TIMER_INTERVAL 3000 +#define IRDMA_CM_DEFAULT_MTU 1540 +#define IRDMA_CM_DEFAULT_FRAME_CNT 10 +#define IRDMA_CM_THREAD_STACK_SIZE 256 +#define IRDMA_CM_DEFAULT_RCV_WND 64240 +#define IRDMA_CM_DEFAULT_RCV_WND_SCALED 0x3FFFC +#define IRDMA_CM_DEFAULT_RCV_WND_SCALE 2 +#define IRDMA_CM_DEFAULT_FREE_PKTS 10 +#define IRDMA_CM_FREE_PKT_LO_WATERMARK 2 +#define IRDMA_CM_DEFAULT_MSS 536 +#define IRDMA_CM_DEFAULT_MPA_VER 2 +#define IRDMA_CM_DEFAULT_SEQ 0x159bf75f +#define IRDMA_CM_DEFAULT_LOCAL_ID 0x3b47 +#define IRDMA_CM_DEFAULT_SEQ2 0x18ed5740 +#define IRDMA_CM_DEFAULT_LOCAL_ID2 0xb807 +#define IRDMA_MAX_CM_BUF (IRDMA_MAX_IETF_SIZE + IETF_MAX_PRIV_DATA_LEN) + +enum ietf_mpa_flags { + IETF_MPA_FLAGS_REJECT = 0x20, + IETF_MPA_FLAGS_CRC = 0x40, + IETF_MPA_FLAGS_MARKERS = 0x80, +}; + +enum irdma_timer_type { + IRDMA_TIMER_TYPE_SEND, + IRDMA_TIMER_TYPE_CLOSE, +}; + +enum option_nums { + OPTION_NUM_EOL, + OPTION_NUM_NONE, + OPTION_NUM_MSS, + OPTION_NUM_WINDOW_SCALE, + OPTION_NUM_SACK_PERM, + OPTION_NUM_SACK, + OPTION_NUM_WRITE0 = 0xbc, +}; + +/* cm node transition states */ +enum irdma_cm_node_state { + IRDMA_CM_STATE_UNKNOWN, + IRDMA_CM_STATE_INITED, + IRDMA_CM_STATE_LISTENING, + IRDMA_CM_STATE_SYN_RCVD, + IRDMA_CM_STATE_SYN_SENT, + IRDMA_CM_STATE_ONE_SIDE_ESTABLISHED, + IRDMA_CM_STATE_ESTABLISHED, + IRDMA_CM_STATE_ACCEPTING, + IRDMA_CM_STATE_MPAREQ_SENT, + IRDMA_CM_STATE_MPAREQ_RCVD, + IRDMA_CM_STATE_MPAREJ_RCVD, + IRDMA_CM_STATE_OFFLOADED, + IRDMA_CM_STATE_FIN_WAIT1, + IRDMA_CM_STATE_FIN_WAIT2, + IRDMA_CM_STATE_CLOSE_WAIT, + IRDMA_CM_STATE_TIME_WAIT, + IRDMA_CM_STATE_LAST_ACK, + IRDMA_CM_STATE_CLOSING, + IRDMA_CM_STATE_LISTENER_DESTROYED, + IRDMA_CM_STATE_CLOSED, +}; + +enum mpa_frame_ver { + IETF_MPA_V1 = 1, + IETF_MPA_V2 = 2, +}; + +enum mpa_frame_key { + MPA_KEY_REQUEST, + MPA_KEY_REPLY, +}; + +enum send_rdma0 { + SEND_RDMA_READ_ZERO = 1, + SEND_RDMA_WRITE_ZERO = 2, +}; + +enum irdma_tcpip_pkt_type { + IRDMA_PKT_TYPE_UNKNOWN, + IRDMA_PKT_TYPE_SYN, + IRDMA_PKT_TYPE_SYNACK, + IRDMA_PKT_TYPE_ACK, + IRDMA_PKT_TYPE_FIN, + IRDMA_PKT_TYPE_RST, +}; + +enum irdma_cm_listener_state { + IRDMA_CM_LISTENER_PASSIVE_STATE = 1, + IRDMA_CM_LISTENER_ACTIVE_STATE = 2, + IRDMA_CM_LISTENER_EITHER_STATE = 3, +}; + +/* CM event codes */ +enum irdma_cm_event_type { + IRDMA_CM_EVENT_UNKNOWN, + IRDMA_CM_EVENT_ESTABLISHED, + IRDMA_CM_EVENT_MPA_REQ, + IRDMA_CM_EVENT_MPA_CONNECT, + IRDMA_CM_EVENT_MPA_ACCEPT, + IRDMA_CM_EVENT_MPA_REJECT, + IRDMA_CM_EVENT_MPA_ESTABLISHED, + IRDMA_CM_EVENT_CONNECTED, + IRDMA_CM_EVENT_RESET, + IRDMA_CM_EVENT_ABORTED, +}; + +struct ietf_mpa_v1 { + u8 key[IETF_MPA_KEY_SIZE]; + u8 flags; + u8 rev; + __be16 priv_data_len; + u8 priv_data[]; +}; + +struct ietf_rtr_msg { + __be16 ctrl_ird; + __be16 ctrl_ord; +}; + +struct ietf_mpa_v2 { + u8 key[IETF_MPA_KEY_SIZE]; + u8 flags; + u8 rev; + __be16 priv_data_len; + struct ietf_rtr_msg rtr_msg; + u8 priv_data[]; +}; + +struct option_base { + u8 optionnum; + u8 len; +}; + +struct option_mss { + u8 optionnum; + u8 len; + __be16 mss; +}; + +struct option_windowscale { + u8 optionnum; + u8 len; + u8 shiftcount; +}; + +union all_known_options { + char eol; + struct option_base base; + struct option_mss mss; + struct option_windowscale windowscale; +}; + +struct irdma_timer_entry { + struct list_head list; + unsigned long timetosend; /* jiffies */ + struct irdma_puda_buf *sqbuf; + u32 type; + u32 retrycount; + u32 retranscount; + u32 context; + u32 send_retrans; + int close_when_complete; +}; + +/* CM context params */ +struct irdma_cm_tcp_context { + u8 client; + u32 loc_seq_num; + u32 loc_ack_num; + u32 rem_ack_num; + u32 rcv_nxt; + u32 loc_id; + u32 rem_id; + u32 snd_wnd; + u32 max_snd_wnd; + u32 rcv_wnd; + u32 mss; + u8 snd_wscale; + u8 rcv_wscale; +}; + +struct irdma_apbvt_entry { + struct hlist_node hlist; + u32 use_cnt; + u16 port; +}; + +struct irdma_cm_listener { + struct list_head list; + struct iw_cm_id *cm_id; + struct irdma_cm_core *cm_core; + struct irdma_device *iwdev; + struct list_head child_listen_list; + struct irdma_apbvt_entry *apbvt_entry; + enum irdma_cm_listener_state listener_state; + refcount_t refcnt; + atomic_t pend_accepts_cnt; + u32 loc_addr[4]; + u32 reused_node; + int backlog; + u16 loc_port; + u16 vlan_id; + u8 loc_mac[ETH_ALEN]; + u8 user_pri; + u8 tos; + bool qhash_set:1; + bool ipv4:1; +}; + +struct irdma_kmem_info { + void *addr; + u32 size; +}; + +struct irdma_mpa_priv_info { + const void *addr; + u32 size; +}; + +struct irdma_cm_node { + struct irdma_qp *iwqp; + struct irdma_device *iwdev; + struct irdma_sc_dev *dev; + struct irdma_cm_tcp_context tcp_cntxt; + struct irdma_cm_core *cm_core; + struct irdma_timer_entry *send_entry; + struct irdma_timer_entry *close_entry; + struct irdma_cm_listener *listener; + struct list_head timer_entry; + struct list_head reset_entry; + struct list_head teardown_entry; + struct irdma_apbvt_entry *apbvt_entry; + struct rcu_head rcu_head; + struct irdma_mpa_priv_info pdata; + struct irdma_sc_ah *ah; + struct ietf_mpa_v2 mpa_v2_frame; + struct irdma_kmem_info mpa_hdr; + struct iw_cm_id *cm_id; + struct hlist_node list; + struct completion establish_comp; + spinlock_t retrans_list_lock; /* protect CM node rexmit updates*/ + atomic_t passive_state; + refcount_t refcnt; + enum irdma_cm_node_state state; + enum send_rdma0 send_rdma0_op; + enum mpa_frame_ver mpa_frame_rev; + u32 loc_addr[4], rem_addr[4]; + u16 loc_port, rem_port; + int apbvt_set; + int accept_pend; + u16 vlan_id; + u16 ird_size; + u16 ord_size; + u16 mpav2_ird_ord; + u16 lsmm_size; + u8 pdata_buf[IETF_MAX_PRIV_DATA_LEN]; + u8 loc_mac[ETH_ALEN]; + u8 rem_mac[ETH_ALEN]; + u8 user_pri; + u8 tos; + bool ack_rcvd:1; + bool qhash_set:1; + bool ipv4:1; + bool snd_mark_en:1; + bool rcv_mark_en:1; + bool do_lpb:1; + bool accelerated:1; +}; + +/* Used by internal CM APIs to pass CM information*/ +struct irdma_cm_info { + struct iw_cm_id *cm_id; + u16 loc_port; + u16 rem_port; + u32 loc_addr[4]; + u32 rem_addr[4]; + u32 qh_qpid; + u16 vlan_id; + int backlog; + u8 user_pri; + u8 tos; + bool ipv4; +}; + +struct irdma_cm_event { + enum irdma_cm_event_type type; + struct irdma_cm_info cm_info; + struct work_struct event_work; + struct irdma_cm_node *cm_node; +}; + +struct irdma_cm_core { + struct irdma_device *iwdev; + struct irdma_sc_dev *dev; + struct list_head listen_list; + DECLARE_HASHTABLE(cm_hash_tbl, 8); + DECLARE_HASHTABLE(apbvt_hash_tbl, 8); + struct timer_list tcp_timer; + struct workqueue_struct *event_wq; + spinlock_t ht_lock; /* protect CM node (active side) list */ + spinlock_t listen_list_lock; /* protect listener list */ + spinlock_t apbvt_lock; /*serialize apbvt add/del entries*/ + u64 stats_nodes_created; + u64 stats_nodes_destroyed; + u64 stats_listen_created; + u64 stats_listen_destroyed; + u64 stats_listen_nodes_created; + u64 stats_listen_nodes_destroyed; + u64 stats_lpbs; + u64 stats_accepts; + u64 stats_rejects; + u64 stats_connect_errs; + u64 stats_passive_errs; + u64 stats_pkt_retrans; + u64 stats_backlog_drops; + struct irdma_puda_buf *(*form_cm_frame)(struct irdma_cm_node *cm_node, + struct irdma_kmem_info *options, + struct irdma_kmem_info *hdr, + struct irdma_mpa_priv_info *pdata, + u8 flags); + int (*cm_create_ah)(struct irdma_cm_node *cm_node, bool wait); + void (*cm_free_ah)(struct irdma_cm_node *cm_node); +}; + +int irdma_schedule_cm_timer(struct irdma_cm_node *cm_node, + struct irdma_puda_buf *sqbuf, + enum irdma_timer_type type, int send_retrans, + int close_when_complete); + +static inline u8 irdma_tos2dscp(u8 tos) +{ +#define IRDMA_DSCP_S 2 +#define IRDMA_DSCP GENMASK(7, 2) + return FIELD_GET(IRDMA_DSCP, tos); +} + +int irdma_accept(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); +int irdma_reject(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len); +int irdma_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param); +int irdma_create_listen(struct iw_cm_id *cm_id, int backlog); +int irdma_destroy_listen(struct iw_cm_id *cm_id); +int irdma_add_arp(struct irdma_pci_f *rf, u32 *ip, const u8 *mac); +int irdma_cm_start(struct irdma_device *dev); +int irdma_cm_stop(struct irdma_device *dev); +bool irdma_ipv4_is_lpb(u32 loc_addr, u32 rem_addr); +bool irdma_ipv6_is_lpb(u32 *loc_addr, u32 *rem_addr); +int irdma_arp_table(struct irdma_pci_f *rf, u32 *ip_addr, + const u8 *mac_addr, u32 action); +void irdma_if_notify_worker(struct work_struct *work); +bool irdma_port_in_use(struct irdma_cm_core *cm_core, u16 port); +void irdma_send_ack(struct irdma_cm_node *cm_node); +void irdma_lpb_nop(struct irdma_sc_qp *qp); +void irdma_rem_ref_cm_node(struct irdma_cm_node *cm_node); +void irdma_add_conn_est_qh(struct irdma_cm_node *cm_node); +#endif /* IRDMA_CM_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/configfs.c b/drivers/intel/irdma-1.14.33/src/irdma/configfs.c new file mode 100644 index 000000000..3efc1fbb9 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/configfs.c @@ -0,0 +1,1559 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2018 - 2023 Intel Corporation */ +#include +#include +#include +#include +#include "main.h" +#ifdef __OFED_4_8__ +#include +#include +#endif + +#if IS_ENABLED(CONFIG_CONFIGFS_FS) +enum irdma_configfs_attr_type { + IRDMA_ATTR_IW_DCTCP, + IRDMA_ATTR_IW_TIMELY, + IRDMA_ATTR_IW_ECN, + IRDMA_ATTR_ROCE_TIMELY, + IRDMA_ATTR_ROCE_DCQCN, + IRDMA_ATTR_ROCE_DCTCP, + IRDMA_ATTR_ROCE_ENABLE, + IRDMA_ATTR_IW_OOO, + IRDMA_ATTR_ROCE_NO_ICRC, + IRDMA_ATTR_ENABLE_UP_MAP, +}; + +struct irdma_vsi_grp { + struct config_group group; + struct irdma_device *iwdev; +}; + +/** + * irdma_find_device_by_name - find a vsi device given a name + * @name: name of iwdev + */ +static struct irdma_device *irdma_find_device_by_name(const char *name) +{ + struct irdma_handler *hdl; + struct irdma_device *iwdev; + unsigned long flags; + + spin_lock_irqsave(&irdma_handler_lock, flags); + list_for_each_entry(hdl, &irdma_handlers, list) { + iwdev = hdl->iwdev; + if (!strcmp(name, iwdev->ibdev.name)) { + spin_unlock_irqrestore(&irdma_handler_lock, flags); + return iwdev; + } + } + spin_unlock_irqrestore(&irdma_handler_lock, flags); + + return NULL; +} + +#ifdef __OFED_4_8__ +static int irdma_configfs_set_vsi_attr(struct irdma_vsi_grp *grp, + const char *buf, + enum irdma_configfs_attr_type attr_type) +{ +#else +/* + * irdma_configfs_set_vsi_attr - set vsi configfs attribute + * @item_name: config item name + * @buf: buffer + * @irdma_configfs_type_attr: vsi attribute type to set + */ +static int irdma_configfs_set_vsi_attr(struct config_item *item, + const char *buf, + enum irdma_configfs_attr_type attr_type) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + struct irdma_up_info up_map_info = {}; + bool enable; + int ret = 0; + + if (kstrtobool(buf, &enable)) { + ret = -EINVAL; + goto done; + } + + switch (attr_type) { + case IRDMA_ATTR_IW_DCTCP: + iwdev->iwarp_dctcp_en = enable; + iwdev->iwarp_ecn_en = !enable; + break; + case IRDMA_ATTR_IW_TIMELY: + iwdev->iwarp_timely_en = enable; + break; + case IRDMA_ATTR_IW_ECN: + iwdev->iwarp_ecn_en = enable; + break; + case IRDMA_ATTR_ENABLE_UP_MAP: + iwdev->up_map_en = enable; + if (enable) { + *((u64 *)up_map_info.map) = iwdev->up_up_map; + up_map_info.use_cnp_up_override = true; + up_map_info.cnp_up_override = iwdev->cnp_up_override; + } else { + *((u64 *)up_map_info.map) = IRDMA_DEFAULT_UP_UP_MAP; + up_map_info.use_cnp_up_override = false; + } + up_map_info.hmc_fcn_idx = iwdev->rf->sc_dev.hmc_fn_id; + irdma_cqp_up_map_cmd(&iwdev->rf->sc_dev, IRDMA_OP_SET_UP_MAP, + &up_map_info); + break; + case IRDMA_ATTR_ROCE_NO_ICRC: + iwdev->roce_no_icrc_en = enable; + break; + case IRDMA_ATTR_ROCE_TIMELY: + iwdev->roce_timely_en = enable; + break; + case IRDMA_ATTR_ROCE_DCQCN: + iwdev->roce_dcqcn_en = enable; + break; + case IRDMA_ATTR_ROCE_DCTCP: + iwdev->roce_dctcp_en = enable; + break; + case IRDMA_ATTR_ROCE_ENABLE: + //rf->roce_en = enable; FIXME: Add when roce/iwarp in configFS + break; + case IRDMA_ATTR_IW_OOO: + iwdev->iw_ooo = enable; + iwdev->override_ooo = true; + break; + default: + ret = -EINVAL; + } + +done: + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_push_mode(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * push_mode_show - Show the value of push_mode for device + * @item: config item + * @buf: buffer to write to + */ +static ssize_t push_mode_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->push_mode); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_push_mode(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * push_mode_store - Store value for push_mode + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t push_mode_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + bool enable; + + if (kstrtobool(buf, &enable)) + return -EINVAL; + + iwdev->push_mode = enable; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_roce_cwnd(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * roce_cwnd_show - Show the value of RoCE cwnd + * @item: config item + * @buf: buffer to write to + */ +static ssize_t roce_cwnd_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->roce_cwnd); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_roce_cwnd(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * roce_cwnd_store - Store value for roce_cwnd + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t roce_cwnd_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u32 rsrc_cwnd; + + if (kstrtou32(buf, 0, &rsrc_cwnd)) + return -EINVAL; + + if (!rsrc_cwnd || rsrc_cwnd > 0x400) + return -EINVAL; + + iwdev->roce_cwnd = rsrc_cwnd; + iwdev->override_cwnd = true; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_roce_rd_fence_rate(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/* + * roce_rd_fence_rate_show - Show RoCE read fence rate + * @item: config item + * @buf: buffer to write to + */ +static ssize_t roce_rd_fence_rate_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->rd_fence_rate); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_roce_rd_fence_rate(struct irdma_vsi_grp *grp, + const char *buf, size_t count) +{ +#else +/** + * roce_rd_fence_rate_store - Store RoCE read fence rate + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t roce_rd_fence_rate_store(struct config_item *item, + const char *buf, size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u32 rd_fence_rate; + + if (kstrtou32(buf, 0, &rd_fence_rate)) + return -EINVAL; + + if (rd_fence_rate > 256) + return -EINVAL; + + iwdev->rd_fence_rate = rd_fence_rate; + iwdev->override_rd_fence_rate = true; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_roce_ackcreds(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * roce_ackcreds_show - Show the value of RoCE ack_creds + * @item: config item + * @buf: buffer to write to + */ +static ssize_t roce_ackcreds_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->roce_ackcreds); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_roce_ackcreds(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * roce_ackcreds_store - Store value for roce_ackcreds + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t roce_ackcreds_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u32 rsrc_ackcreds; + + if (kstrtou32(buf, 0, &rsrc_ackcreds)) + return -EINVAL; + + if (!rsrc_ackcreds || rsrc_ackcreds > 0x1E) + return -EINVAL; + + iwdev->roce_ackcreds = rsrc_ackcreds; + iwdev->override_ackcreds = true; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_cnp_up_override(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * cnp_up_override_store - Store value for CNP override + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t cnp_up_override_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u8 cnp_override; + + if (kstrtou8(buf, 0, &cnp_override)) + return -EINVAL; + + if (cnp_override > 0x3F) + return -EINVAL; + + iwdev->cnp_up_override = cnp_override; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_cnp_up_override(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * cnp_up_override_show - Show value of CNP UP override + * @item: config item + * @buf: buffer to write to + */ +static ssize_t cnp_up_override_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->cnp_up_override); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_ceq_itr(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * ceq_itr_store - Set interrupt Throttling(ITR) value + * @item: config item + * @buf: buffer to read from + * @count: size of buffer + */ +static ssize_t ceq_itr_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u32 itr; + + if (kstrtou32(buf, 0, &itr)) + return -EINVAL; + +#define IRDMA_MAX_ITR 8160 + if (itr > 8160) { + return -EINVAL; + } + + iwdev->rf->sc_dev.ceq_itr = itr; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_ceq_itr(struct irdma_vsi_grp *grp, + char *buf) +{ +#else +/** + * ceq_itr_show - Show interrupt Throttling(ITR) value + * @item: config item + * @buf: buffer to write to + */ +static ssize_t ceq_itr_show(struct config_item *item, + char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->rf->sc_dev.ceq_itr); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_ceq_intrl(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * ceq_intrl_store - Set the interrupt rate limit value + * @item: config item + * @buf: buffer to read from + * @count: size of buffer + */ +static ssize_t ceq_intrl_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + struct irdma_msix_vector *msix_vec; + u32 intrl, interval = 0; + int i; + + if (kstrtou32(buf, 0, &intrl)) + return -EINVAL; + +#define IRDMA_MIN_INT_RATE_LIMIT 4237 +#define IRDMA_MAX_INT_RATE_LIMIT 250000 +#define IRDMA_USECS_PER_SEC 1000000 +#define IRDMA_USECS_PER_UNIT 4 +#define IRDMA_MAX_SUPPORTED_INT_RATE_INTERVAL 59 /* 59 * 4 = 236 us */ + + if (intrl && intrl < IRDMA_MIN_INT_RATE_LIMIT) + intrl = IRDMA_MIN_INT_RATE_LIMIT; + if (intrl > IRDMA_MAX_INT_RATE_LIMIT) + intrl = IRDMA_MAX_INT_RATE_LIMIT; + + iwdev->ceq_intrl = intrl; + if (intrl) { + interval = (IRDMA_USECS_PER_SEC / intrl) / IRDMA_USECS_PER_UNIT; + + ibdev_info(&iwdev->ibdev, "CEQ Interrupt rate Limit enabled with interval = %d\n", interval); + } else { + ibdev_info(&iwdev->ibdev, "CEQ Interrupt rate Limit disabled\n"); + } + + if (iwdev->rf->msix_shared) + msix_vec = &iwdev->rf->iw_msixtbl[1]; + else + msix_vec = &iwdev->rf->iw_msixtbl[2]; + for (i = 1; i < iwdev->rf->ceqs_count; i++, msix_vec++) + irdma_set_irq_rate_limit(&iwdev->rf->sc_dev, msix_vec->idx, interval); + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_ceq_intrl(struct irdma_vsi_grp *grp, + char *buf) +{ +#else +/** + * ceq_intrl_show - Show the interrupt rate limit value + * @item: config item + * @buf: buffer to write to + */ +static ssize_t ceq_intrl_show(struct config_item *item, + char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->ceq_intrl); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_up_up_map(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * up_up_map_store - Store value for UP-UP map + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t up_up_map_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u64 up_map; + + if (kstrtou64(buf, 0, &up_map)) + return -EINVAL; + + iwdev->up_up_map = up_map; + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_up_up_map(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * up_up_map_show - Show value of IP-UP map + * @item: config item + * @buf: buffer to write to + */ +static ssize_t up_up_map_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "0x%llx\n", iwdev->up_up_map); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_rcv_wnd(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * rcv_wnd_show - Show the value of TCP receive window + * @item: config item + * @buf: buffer to write to + */ +static ssize_t rcv_wnd_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->rcv_wnd); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_rcv_wnd(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * rcv_wnd_store - Store value for rcv_wnd + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t rcv_wnd_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u32 rsrc_rcv_wnd; + + if (kstrtou32(buf, 0, &rsrc_rcv_wnd)) + return -EINVAL; + + if (rsrc_rcv_wnd < 65536) + return -EINVAL; + + iwdev->rcv_wnd = rsrc_rcv_wnd; + iwdev->override_rcv_wnd = true; + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_rcv_wscale(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * rcv_wscale_show - Show value of TCP receive window scale + * @item: config item + * @buf: buffer to write to + */ +static ssize_t rcv_wscale_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->rcv_wscale); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_rcv_wscale(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * rcv_wscale_store - Store value for recv_wscale + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t rcv_wscale_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u8 rsrc_rcv_wscale; + + if (kstrtou8(buf, 0, &rsrc_rcv_wscale)) + return -EINVAL; + + if (rsrc_rcv_wscale > 16) + return -EINVAL; + + iwdev->rcv_wscale = rsrc_rcv_wscale; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_iw_dctcp_enable(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * iw_dctcp_enable_show - Show the value of dctcp_enable for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t iw_dctcp_enable_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->iwarp_dctcp_en); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_iw_dctcp_enable(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +#else +/** + * iw_dctcp_enable_store - Store value of dctcp_enable for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t iw_dctcp_enable_store(struct config_item *item, + const char *buf, + size_t count) +#endif +{ + int ret; + +#ifdef __OFED_4_8__ + ret = irdma_configfs_set_vsi_attr(grp, buf, IRDMA_ATTR_IW_DCTCP); +#else + ret = irdma_configfs_set_vsi_attr(item, buf, IRDMA_ATTR_IW_DCTCP); +#endif + + if (ret) + return ret; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_iw_ecn_enable(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * iw_ecn_enable_show - Show the value of ecn_enable for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t iw_ecn_enable_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->iwarp_ecn_en); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_iw_ecn_enable(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +#else +/** + * iw_ecn_enable_store - Store value of ecn_enable for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t iw_ecn_enable_store(struct config_item *item, + const char *buf, + size_t count) +#endif +{ + int ret; + +#ifdef __OFED_4_8__ + ret = irdma_configfs_set_vsi_attr(grp, buf, IRDMA_ATTR_IW_ECN); +#else + ret = irdma_configfs_set_vsi_attr(item, buf, IRDMA_ATTR_IW_ECN); +#endif + + if (ret) + return ret; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_iw_timely_enable(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * iw_timely_enable_show - Show value of iwarp_timely_enable for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t iw_timely_enable_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->iwarp_timely_en); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_iw_timely_enable(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +#else +/** + * iw_timely_enable_store - Store value of iwarp_timely_enable for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t iw_timely_enable_store(struct config_item *item, + const char *buf, + size_t count) +#endif +{ + int ret; + +#ifdef __OFED_4_8__ + ret = irdma_configfs_set_vsi_attr(grp, buf, IRDMA_ATTR_IW_TIMELY); +#else + ret = irdma_configfs_set_vsi_attr(item, buf, IRDMA_ATTR_IW_TIMELY); +#endif + + if (ret) + return ret; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_iw_rtomin(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * iw_rtomin_show - Show the value of rtomin for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t iw_rtomin_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->iwarp_rtomin); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_iw_rtomin(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * iw_rtomin_store - Store value of iwarp_rtomin for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t iw_rtomin_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u8 rtomin; + + if (kstrtou8(buf, 0, &rtomin)) + return -EINVAL; + + iwdev->iwarp_rtomin = rtomin; + iwdev->override_rtomin = true; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_roce_rtomin(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * roce_rtomin_show - Show the value of roce_rtomin for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t roce_rtomin_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->roce_rtomin); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_roce_rtomin(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +{ +#else +/** + * roce_rtomin_store - Store value of roce_rtomin for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t roce_rtomin_store(struct config_item *item, + const char *buf, + size_t count) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + u8 rtomin; + + if (kstrtou8(buf, 0, &rtomin)) + return -EINVAL; + + iwdev->roce_rtomin = rtomin; + iwdev->override_rtomin = true; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_roce_timely_enable(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * roce_timely_enable_show - Show value of roce_timely_enable for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t roce_timely_enable_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->roce_timely_en); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_roce_timely_enable(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +#else +/** + * roce_timely_enable_store - Store value of roce_timely_enable for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t roce_timely_enable_store(struct config_item *item, + const char *buf, + size_t count) +#endif +{ + int ret; + +#ifdef __OFED_4_8__ + ret = irdma_configfs_set_vsi_attr(grp, buf, IRDMA_ATTR_ROCE_TIMELY); +#else + ret = irdma_configfs_set_vsi_attr(item, buf, IRDMA_ATTR_ROCE_TIMELY); +#endif + + if (ret) + return ret; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_roce_no_icrc_enable(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * roce_no_icrc_enable_show - Show value of no_icrc for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t roce_no_icrc_enable_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->roce_no_icrc_en); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_roce_no_icrc_enable(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +#else +/** + * roce_no_icrc_enable_store - Store value of roce_no_icrc for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t roce_no_icrc_enable_store(struct config_item *item, + const char *buf, + size_t count) +#endif +{ + int ret; + +#ifdef __OFED_4_8__ + ret = irdma_configfs_set_vsi_attr(grp, buf, IRDMA_ATTR_ROCE_NO_ICRC); +#else + ret = irdma_configfs_set_vsi_attr(item, buf, IRDMA_ATTR_ROCE_NO_ICRC); +#endif + + if (ret) + return ret; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_up_map_enable(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * up_map_enable_show - Show value of up_map_enable for PF + * @item: config item + * @buf: buffer to write to + */ +static ssize_t up_map_enable_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->up_map_en); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_up_map_enable(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +#else +/** + * up_map_enable_store - Store value of up_map_enable for PF + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t up_map_enable_store(struct config_item *item, + const char *buf, + size_t count) +#endif +{ + int ret; + +#ifdef __OFED_4_8__ + ret = irdma_configfs_set_vsi_attr(grp, buf, IRDMA_ATTR_ENABLE_UP_MAP); +#else + ret = irdma_configfs_set_vsi_attr(item, buf, IRDMA_ATTR_ENABLE_UP_MAP); +#endif + + if (ret) + return ret; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_iw_ooo_enable(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * iw_ooo_enable_show - Show the value of iw_ooo_enable for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t iw_ooo_enable_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->iw_ooo); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_iw_ooo_enable(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +#else +/** + * iw_ooo_enable_store - Store value of iw_ooo_enable for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t iw_ooo_enable_store(struct config_item *item, + const char *buf, + size_t count) +#endif +{ + int ret; + +#ifdef __OFED_4_8__ + ret = irdma_configfs_set_vsi_attr(grp, buf, IRDMA_ATTR_IW_OOO); +#else + ret = irdma_configfs_set_vsi_attr(item, buf, IRDMA_ATTR_IW_OOO); +#endif + + if (ret) + return ret; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_roce_dcqcn_enable(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/** + * roce_dcqcn_enable_show - Show the value of roce_dcqcn_enable for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t roce_dcqcn_enable_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->roce_dcqcn_en); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_roce_dcqcn_enable(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +#else +/** + * roce_dcqcn_enable_store - Store value of roce_dcqcn_enable for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t roce_dcqcn_enable_store(struct config_item *item, + const char *buf, + size_t count) +#endif +{ + int ret; + +#ifdef __OFED_4_8__ + ret = irdma_configfs_set_vsi_attr(grp, buf, IRDMA_ATTR_ROCE_DCQCN); +#else + ret = irdma_configfs_set_vsi_attr(item, buf, IRDMA_ATTR_ROCE_DCQCN); +#endif + + if (ret) + return ret; + + return count; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_show_attr_roce_dctcp_enable(struct irdma_vsi_grp *grp, char *buf) +{ +#else +/* roce_dctcp_enable_show - Show the value of roce_dctcp_enable for vsi + * @item: config item + * @buf: buffer to write to + */ +static ssize_t roce_dctcp_enable_show(struct config_item *item, char *buf) +{ + struct irdma_vsi_grp *grp = container_of(to_config_group(item), + struct irdma_vsi_grp, + group); +#endif + struct irdma_device *iwdev = grp->iwdev; + ssize_t ret; + + ret = sprintf(buf, "%d\n", iwdev->roce_dctcp_en); + + return ret; +} + +#ifdef __OFED_4_8__ +static ssize_t irdma_store_attr_roce_dctcp_enable(struct irdma_vsi_grp *grp, + const char *buf, + size_t count) +#else +/** + * roce_dctcp_enable_store - Store value of roce_dctcp_enable for vsi + * @item: config item + * @buf: buf to read from + * @count: size of buf + */ +static ssize_t roce_dctcp_enable_store(struct config_item *item, + const char *buf, + size_t count) +#endif +{ + int ret; + +#ifdef __OFED_4_8__ + ret = irdma_configfs_set_vsi_attr(grp, buf, IRDMA_ATTR_ROCE_DCTCP); +#else + ret = irdma_configfs_set_vsi_attr(item, buf, IRDMA_ATTR_ROCE_DCTCP); +#endif + + if (ret) + return ret; + + return count; +} + +#ifdef __OFED_4_8__ +CONFIGFS_EATTR_STRUCT(irdma, irdma_vsi_grp); +#define CFG_CONFIG_DESC_ITEM_ATTR(name) \ + static struct irdma_attribute name = \ + __CONFIGFS_EATTR(name, 0644, \ + irdma_show_attr_##name, \ + irdma_store_attr_##name) + +CFG_CONFIG_DESC_ITEM_ATTR(iw_dctcp_enable); +CFG_CONFIG_DESC_ITEM_ATTR(push_mode); +CFG_CONFIG_DESC_ITEM_ATTR(iw_timely_enable); +CFG_CONFIG_DESC_ITEM_ATTR(iw_ecn_enable); +CFG_CONFIG_DESC_ITEM_ATTR(iw_rtomin); +CFG_CONFIG_DESC_ITEM_ATTR(rcv_wnd); +CFG_CONFIG_DESC_ITEM_ATTR(rcv_wscale); +CFG_CONFIG_DESC_ITEM_ATTR(iw_ooo_enable); +CFG_CONFIG_DESC_ITEM_ATTR(cnp_up_override); +CFG_CONFIG_DESC_ITEM_ATTR(up_map_enable); +CFG_CONFIG_DESC_ITEM_ATTR(up_up_map); +CFG_CONFIG_DESC_ITEM_ATTR(ceq_itr); +CFG_CONFIG_DESC_ITEM_ATTR(ceq_intrl); +CFG_CONFIG_DESC_ITEM_ATTR(roce_cwnd); +CFG_CONFIG_DESC_ITEM_ATTR(roce_rd_fence_rate); +CFG_CONFIG_DESC_ITEM_ATTR(roce_ackcreds); +CFG_CONFIG_DESC_ITEM_ATTR(roce_timely_enable); +CFG_CONFIG_DESC_ITEM_ATTR(roce_no_icrc_enable); +CFG_CONFIG_DESC_ITEM_ATTR(roce_dcqcn_enable); +CFG_CONFIG_DESC_ITEM_ATTR(roce_dctcp_enable); +CFG_CONFIG_DESC_ITEM_ATTR(roce_rtomin); + +CONFIGFS_EATTR_OPS(irdma, irdma_vsi_grp, group); + +static struct configfs_attribute *irdma_gen1_iw_vsi_attrs[] = { + &rcv_wnd.attr, + &rcv_wscale.attr, + NULL, +}; + +static struct configfs_attribute *irdma_iw_vsi_attrs[] = { + &push_mode.attr, + &iw_dctcp_enable.attr, + &iw_timely_enable.attr, + &iw_ecn_enable.attr, + &iw_rtomin.attr, + &rcv_wnd.attr, + &rcv_wscale.attr, + &iw_ooo_enable.attr, + &cnp_up_override.attr, + &up_map_enable.attr, + &up_up_map.attr, + &ceq_itr.attr, + &ceq_intrl.attr, + NULL, +}; + +static struct configfs_attribute *irdma_roce_vsi_attrs[] = { + &push_mode.attr, + &roce_cwnd.attr, + &roce_rd_fence_rate.attr, + &roce_ackcreds.attr, + &roce_timely_enable.attr, + &roce_no_icrc_enable.attr, + &roce_dcqcn_enable.attr, + &roce_dctcp_enable.attr, + &roce_rtomin.attr, + &cnp_up_override.attr, + &up_map_enable.attr, + &up_up_map.attr, + &ceq_itr.attr, + &ceq_intrl.attr, + NULL, +}; +#else /* OFED_4_8 */ +CONFIGFS_ATTR(, push_mode); +CONFIGFS_ATTR(, iw_dctcp_enable); +CONFIGFS_ATTR(, iw_timely_enable); +CONFIGFS_ATTR(, iw_ecn_enable); +CONFIGFS_ATTR(, iw_rtomin); +CONFIGFS_ATTR(, rcv_wnd); +CONFIGFS_ATTR(, rcv_wscale); +CONFIGFS_ATTR(, iw_ooo_enable); +CONFIGFS_ATTR(, up_map_enable); +CONFIGFS_ATTR(, cnp_up_override); +CONFIGFS_ATTR(, up_up_map); +CONFIGFS_ATTR(, ceq_itr); +CONFIGFS_ATTR(, ceq_intrl); +CONFIGFS_ATTR(, roce_timely_enable); +CONFIGFS_ATTR(, roce_no_icrc_enable); +CONFIGFS_ATTR(, roce_dcqcn_enable); +CONFIGFS_ATTR(, roce_dctcp_enable); +CONFIGFS_ATTR(, roce_cwnd); +CONFIGFS_ATTR(, roce_rd_fence_rate); +CONFIGFS_ATTR(, roce_ackcreds); +CONFIGFS_ATTR(, roce_rtomin); + +static struct configfs_attribute *irdma_gen1_iw_vsi_attrs[] = { + &attr_rcv_wnd, + &attr_rcv_wscale, + NULL, +}; + +static struct configfs_attribute *irdma_iw_vsi_attrs[] = { + &attr_push_mode, + &attr_iw_dctcp_enable, + &attr_iw_timely_enable, + &attr_iw_ecn_enable, + &attr_iw_rtomin, + &attr_rcv_wnd, + &attr_rcv_wscale, + &attr_iw_ooo_enable, + &attr_cnp_up_override, + &attr_up_map_enable, + &attr_up_up_map, + &attr_ceq_itr, + &attr_ceq_intrl, + NULL, +}; + +static struct configfs_attribute *irdma_roce_vsi_attrs[] = { + &attr_push_mode, + &attr_roce_cwnd, + &attr_roce_rd_fence_rate, + &attr_roce_ackcreds, + &attr_roce_timely_enable, + &attr_roce_no_icrc_enable, + &attr_roce_dcqcn_enable, + &attr_roce_dctcp_enable, + &attr_roce_rtomin, + &attr_cnp_up_override, + &attr_up_map_enable, + &attr_up_up_map, + &attr_ceq_itr, + &attr_ceq_intrl, + NULL, +}; +#endif /* OFED_4_8 */ + +static void irdma_release_vsi_grp(struct config_item *item) +{ + struct config_group *group = container_of(item, struct config_group, + cg_item); + struct irdma_vsi_grp *vsi_grp = container_of(group, + struct irdma_vsi_grp, + group); + + kfree(vsi_grp); +} + +static struct configfs_item_operations irdma_vsi_ops = { +#ifdef __OFED_4_8__ + .show_attribute = irdma_attr_show, + .store_attribute = irdma_attr_store, +#endif + .release = irdma_release_vsi_grp +}; + +static struct config_item_type irdma_iw_vsi_type = { + .ct_attrs = irdma_iw_vsi_attrs, + .ct_item_ops = &irdma_vsi_ops, + .ct_owner = THIS_MODULE, +}; + +static struct config_item_type irdma_roce_vsi_type = { + .ct_attrs = irdma_roce_vsi_attrs, + .ct_item_ops = &irdma_vsi_ops, + .ct_owner = THIS_MODULE, +}; + +static struct config_item_type irdma_gen1_iw_vsi_type = { + .ct_attrs = irdma_gen1_iw_vsi_attrs, + .ct_item_ops = &irdma_vsi_ops, + .ct_owner = THIS_MODULE, +}; + +/** + * irdma_vsi_make_group - Creation of subsystem groups + * @group: config group + * @name: name of the group + */ +static struct config_group *irdma_vsi_make_group(struct config_group *group, + const char *name) +{ + struct irdma_vsi_grp *vsi_grp; + struct irdma_device *iwdev; + u8 hw_ver; + + iwdev = irdma_find_device_by_name(name); + if (!iwdev) + return ERR_PTR(-ENODEV); + + hw_ver = iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev; + + vsi_grp = kzalloc(sizeof(*vsi_grp), GFP_KERNEL); + if (!vsi_grp) + return ERR_PTR(-ENOMEM); + + vsi_grp->iwdev = iwdev; + + config_group_init(&vsi_grp->group); + + if (hw_ver == IRDMA_GEN_1) { + config_group_init_type_name(&vsi_grp->group, name, + &irdma_gen1_iw_vsi_type); + } else { + if (iwdev->rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) + config_group_init_type_name(&vsi_grp->group, name, &irdma_iw_vsi_type); + else + config_group_init_type_name(&vsi_grp->group, name, &irdma_roce_vsi_type); + } + + return &vsi_grp->group; +} + +static struct configfs_group_operations irdma_vsi_group_ops = { + .make_group = irdma_vsi_make_group, +}; + +static struct config_item_type irdma_subsys_type = { + .ct_group_ops = &irdma_vsi_group_ops, + .ct_owner = THIS_MODULE, +}; + +static struct configfs_subsystem cfs_subsys = { + .su_group = { + .cg_item = { + .ci_namebuf = "irdma", + .ci_type = &irdma_subsys_type, + }, + }, +}; + +int irdma_configfs_init(void) +{ + config_group_init(&cfs_subsys.su_group); + mutex_init(&cfs_subsys.su_mutex); + return configfs_register_subsystem(&cfs_subsys); +} + +void irdma_configfs_exit(void) +{ + configfs_unregister_subsystem(&cfs_subsys); +} +#endif /* CONFIG_CONFIGFS_FS */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ctrl.c b/drivers/intel/irdma-1.14.33/src/irdma/ctrl.c new file mode 100644 index 000000000..e11a86c26 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ctrl.c @@ -0,0 +1,6903 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "osdep.h" +#include "hmc.h" +#include "defs.h" +#include "type.h" +#include "ws.h" +#include "protos.h" +#include "virtchnl.h" + +/** + * irdma_get_qp_from_list - get next qp from a list + * @head: Listhead of qp's + * @qp: current qp + */ +struct irdma_sc_qp *irdma_get_qp_from_list(struct list_head *head, + struct irdma_sc_qp *qp) +{ + struct list_head *lastentry; + struct list_head *entry = NULL; + + if (list_empty(head)) + return NULL; + + if (!qp) { + entry = head->next; + } else { + lastentry = &qp->list; + entry = lastentry->next; + if (entry == head) + return NULL; + } + + return container_of(entry, struct irdma_sc_qp, list); +} + +/** + * irdma_sc_suspend_resume_qps - suspend/resume all qp's on VSI + * @vsi: the VSI struct pointer + * @op: Set to IRDMA_OP_RESUME or IRDMA_OP_SUSPEND + */ +void irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 op) +{ + struct irdma_sc_qp *qp = NULL; + u8 i; + + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + mutex_lock(&vsi->qos[i].qos_mutex); + qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); + while (qp) { + if (op == IRDMA_OP_RESUME) { + if (!qp->dev->ws_add(vsi, i)) { + qp->qs_handle = + vsi->qos[qp->user_pri].qs_handle[qp->qs_idx]; + irdma_cqp_qp_suspend_resume(qp, op); + } else { + irdma_cqp_qp_suspend_resume(qp, op); + irdma_modify_qp_to_err(qp); + } + } else if (op == IRDMA_OP_SUSPEND) { + /* issue cqp suspend command */ + if (!irdma_cqp_qp_suspend_resume(qp, op)) + atomic_inc(&vsi->qp_suspend_reqs); + } + qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); + } + mutex_unlock(&vsi->qos[i].qos_mutex); + } +} + +static void irdma_set_qos_info(struct irdma_sc_vsi *vsi, struct irdma_l2params *l2p) +{ + u8 i; + + if (vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + vsi->qos[i].qs_handle[0] = + vsi->dev->qos[i].qs_handle[0]; + vsi->qos[i].valid = true; + } + + return; + } + vsi->qos_rel_bw = l2p->vsi_rel_bw; + vsi->qos_prio_type = l2p->vsi_prio_type; + vsi->dscp_mode = l2p->dscp_mode; + if (l2p->dscp_mode) { + memcpy(vsi->dscp_map, l2p->dscp_map, sizeof(vsi->dscp_map)); + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) + l2p->up2tc[i] = i; + } + for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) + vsi->tc_print_warning[i] = true; + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + vsi->qos[i].qs_handle[IRDMA_LAG_PRIMARY_IDX] = + l2p->qs_handle_list[i]; + if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) + irdma_init_config_check(&vsi->cfg_check[i], + l2p->up2tc[i], + l2p->qs_handle_list[i]); + vsi->qos[i].traffic_class = l2p->up2tc[i]; + vsi->qos[i].rel_bw = + l2p->tc_info[vsi->qos[i].traffic_class].rel_bw; + vsi->qos[i].prio_type = + l2p->tc_info[vsi->qos[i].traffic_class].prio_type; + vsi->qos[i].valid = false; + } +} + +/** + * irdma_change_l2params - given the new l2 parameters, change all qp + * @vsi: RDMA VSI pointer + * @l2params: New parameters from l2 + */ +void irdma_change_l2params(struct irdma_sc_vsi *vsi, + struct irdma_l2params *l2params) +{ + if (l2params->tc_changed) { + vsi->tc_change_pending = false; + irdma_set_qos_info(vsi, l2params); + irdma_sc_suspend_resume_qps(vsi, IRDMA_OP_RESUME); + } + if (l2params->mtu_changed) { + vsi->mtu = l2params->mtu; + if (vsi->ieq) + irdma_reinitialize_ieq(vsi); + } +} + +/** + * irdma_qp_rem_qos - remove qp from qos lists during destroy qp + * @qp: qp to be removed from qos + */ +void irdma_qp_rem_qos(struct irdma_sc_qp *qp) +{ + struct irdma_sc_vsi *vsi = qp->vsi; + + ibdev_dbg(to_ibdev(qp->dev), + "DCB: DCB: Remove qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", + qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, + qp->on_qoslist); + mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); + if (qp->vsi->lag_aa) + qp->qs_idx ? atomic_dec(&vsi->port2_qp_cnt) : + atomic_dec(&vsi->port1_qp_cnt); + if (qp->on_qoslist) { + qp->on_qoslist = false; + list_del(&qp->list); + } + mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); +} + +/** + * irdma_qp_add_qos - called during setctx for qp to be added to qos + * @qp: qp to be added to qos + */ +void irdma_qp_add_qos(struct irdma_sc_qp *qp) +{ + struct irdma_sc_vsi *vsi = qp->vsi; + + mutex_lock(&vsi->qos[qp->user_pri].qos_mutex); + if (!qp->on_qoslist) { + list_add(&qp->list, &vsi->qos[qp->user_pri].qplist); + qp->on_qoslist = true; + if (vsi->lag_aa) { + if (atomic_read(&vsi->port1_qp_cnt) <= + atomic_read(&vsi->port2_qp_cnt)) { + qp->qs_idx = IRDMA_LAG_PRIMARY_IDX; + atomic_inc(&vsi->port1_qp_cnt); + } else { + qp->qs_idx = IRDMA_LAG_SECONDARY_IDX; + atomic_inc(&vsi->port2_qp_cnt); + } + } + qp->qs_handle = vsi->qos[qp->user_pri].qs_handle[qp->qs_idx]; + ibdev_dbg(to_ibdev(qp->dev), + "DCB: DCB: Add qp[%d] UP[%d] qset[%d] on_qoslist[%d]\n", + qp->qp_uk.qp_id, qp->user_pri, qp->qs_handle, + qp->on_qoslist); + + } + mutex_unlock(&vsi->qos[qp->user_pri].qos_mutex); +} + +/** + * irdma_sc_pd_init - initialize sc pd struct + * @dev: sc device struct + * @pd: sc pd ptr + * @pd_id: pd_id for allocated pd + * @abi_ver: User/Kernel ABI version + */ +void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id, + int abi_ver) +{ + pd->pd_id = pd_id; + pd->abi_ver = abi_ver; + pd->dev = dev; +} + +/** + * irdma_sc_add_arp_cache_entry - cqp wqe add arp cache entry + * @cqp: struct for cqp hw + * @info: arp entry information + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int +irdma_sc_add_arp_cache_entry(struct irdma_sc_cqp *cqp, + struct irdma_add_arp_cache_entry_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + u64 hdr; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + set_64bit_val(wqe, 8, info->reach_max); + + set_64bit_val(wqe, 16, ether_addr_to_u64(info->mac_addr)); + + hdr = info->arp_index | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | + FIELD_PREP(IRDMA_CQPSQ_MAT_PERMANENT, info->permanent) | + FIELD_PREP(IRDMA_CQPSQ_MAT_ENTRYVALID, true) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: ARP_CACHE_ENTRY WQE", DUMP_PREFIX_OFFSET, + 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_del_arp_cache_entry - dele arp cache entry + * @cqp: struct for cqp hw + * @scratch: u64 saved to be used during cqp completion + * @arp_index: arp index to delete arp entry + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_del_arp_cache_entry(struct irdma_sc_cqp *cqp, u64 scratch, + u16 arp_index, bool post_sq) +{ + __le64 *wqe; + u64 hdr; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + hdr = arp_index | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_ARP) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: ARP_CACHE_DEL_ENTRY WQE", + DUMP_PREFIX_OFFSET, 16, 8, wqe, + IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_manage_apbvt_entry - for adding and deleting apbvt entries + * @cqp: struct for cqp hw + * @info: info for apbvt entry to add or delete + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_manage_apbvt_entry(struct irdma_sc_cqp *cqp, + struct irdma_apbvt_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + u64 hdr; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, info->port); + + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_APBVT) | + FIELD_PREP(IRDMA_CQPSQ_MAPT_ADDPORT, info->add) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: MANAGE_APBVT WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_manage_qhash_table_entry - manage quad hash entries + * @cqp: struct for cqp hw + * @info: info for quad hash to manage + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + * + * This is called before connection establishment is started. + * For passive connections, when listener is created, it will + * call with entry type of IRDMA_QHASH_TYPE_TCP_SYN with local + * ip address and tcp port. When SYN is received (passive + * connections) or sent (active connections), this routine is + * called with entry type of IRDMA_QHASH_TYPE_TCP_ESTABLISHED + * and quad is passed in info. + * + * When iwarp connection is done and its state moves to RTS, the + * quad hash entry in the hardware will point to iwarp's qp + * number and requires no calls from the driver. + */ +static int +irdma_sc_manage_qhash_table_entry(struct irdma_sc_cqp *cqp, + struct irdma_qhash_table_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + u64 qw1 = 0; + u64 qw2 = 0; + u64 temp; + struct irdma_sc_vsi *vsi = info->vsi; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + set_64bit_val(wqe, 0, ether_addr_to_u64(info->mac_addr)); + + qw1 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QPN, info->qp_num) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_DEST_PORT, info->dest_port); + if (info->ipv4_valid) { + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[0])); + } else { + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->dest_ip[0]) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->dest_ip[1])); + + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->dest_ip[2]) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->dest_ip[3])); + } + qw2 = FIELD_PREP(IRDMA_CQPSQ_QHASH_QS_HANDLE, + vsi->qos[info->user_pri].qs_handle[IRDMA_LAG_PRIMARY_IDX]); + if (info->vlan_valid) + qw2 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANID, info->vlan_id); + set_64bit_val(wqe, 16, qw2); + if (info->entry_type == IRDMA_QHASH_TYPE_TCP_ESTABLISHED) { + qw1 |= FIELD_PREP(IRDMA_CQPSQ_QHASH_SRC_PORT, info->src_port); + if (!info->ipv4_valid) { + set_64bit_val(wqe, 40, + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR0, info->src_ip[0]) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR1, info->src_ip[1])); + set_64bit_val(wqe, 32, + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR2, info->src_ip[2]) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[3])); + } else { + set_64bit_val(wqe, 32, + FIELD_PREP(IRDMA_CQPSQ_QHASH_ADDR3, info->src_ip[0])); + } + } + + set_64bit_val(wqe, 8, qw1); + temp = FIELD_PREP(IRDMA_CQPSQ_QHASH_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_OPCODE, + IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_MANAGE, info->manage) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_IPV4VALID, info->ipv4_valid) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_VLANVALID, info->vlan_valid) | + FIELD_PREP(IRDMA_CQPSQ_QHASH_ENTRYTYPE, info->entry_type); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, temp); + + print_hex_dump_debug("WQE: MANAGE_QHASH WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_qp_init - initialize qp + * @qp: sc qp + * @info: initialization qp info + */ +int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info) +{ + int ret_code; + u32 pble_obj_cnt; + u16 wqe_size; + + if (info->qp_uk_init_info.max_sq_frag_cnt > + info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags || + info->qp_uk_init_info.max_rq_frag_cnt > + info->pd->dev->hw_attrs.uk_attrs.max_hw_wq_frags) + return -EINVAL; + + qp->dev = info->pd->dev; + qp->vsi = info->vsi; + qp->ieq_qp = info->vsi->exception_lan_q; + qp->sq_pa = info->sq_pa; + qp->rq_pa = info->rq_pa; + qp->hw_host_ctx_pa = info->host_ctx_pa; + qp->q2_pa = info->q2_pa; + qp->shadow_area_pa = info->shadow_area_pa; + qp->q2_buf = info->q2; + qp->pd = info->pd; + qp->hw_host_ctx = info->host_ctx; + info->qp_uk_init_info.wqe_alloc_db = qp->pd->dev->wqe_alloc_db; + ret_code = irdma_uk_qp_init(&qp->qp_uk, &info->qp_uk_init_info); + if (ret_code) + return ret_code; + + qp->virtual_map = info->virtual_map; + pble_obj_cnt = info->pd->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; + + if ((info->virtual_map && info->sq_pa >= pble_obj_cnt) || + (!info->qp_uk_init_info.srq_uk && info->virtual_map && info->rq_pa >= pble_obj_cnt)) + return -EINVAL; + + qp->llp_stream_handle = (void *)(-1); + qp->hw_sq_size = irdma_get_encoded_wqe_size(qp->qp_uk.sq_ring.size, + IRDMA_QUEUE_TYPE_SQ_RQ); + ibdev_dbg(to_ibdev(qp->dev), + "WQE: hw_sq_size[%04d] sq_ring.size[%04d]\n", + qp->hw_sq_size, qp->qp_uk.sq_ring.size); + if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1 && qp->pd->abi_ver > 4) + wqe_size = IRDMA_WQE_SIZE_128; + else + ret_code = irdma_fragcnt_to_wqesize_rq(qp->qp_uk.max_rq_frag_cnt, + &wqe_size); + if (ret_code) + return ret_code; + + qp->hw_rq_size = + irdma_get_encoded_wqe_size(qp->qp_uk.rq_size * + (wqe_size / IRDMA_QP_WQE_MIN_SIZE), + IRDMA_QUEUE_TYPE_SQ_RQ); + ibdev_dbg(to_ibdev(qp->dev), + "WQE: hw_rq_size[%04d] qp_uk.rq_size[%04d] wqe_size[%04d]\n", + qp->hw_rq_size, qp->qp_uk.rq_size, wqe_size); + + qp->sq_tph_val = info->sq_tph_val; + qp->rq_tph_val = info->rq_tph_val; + qp->sq_tph_en = info->sq_tph_en; + qp->rq_tph_en = info->rq_tph_en; + qp->rcv_tph_en = info->rcv_tph_en; + qp->xmit_tph_en = info->xmit_tph_en; + qp->qp_uk.first_sq_wq = info->qp_uk_init_info.first_sq_wq; + qp->qs_handle = + qp->vsi->qos[qp->user_pri].qs_handle[IRDMA_LAG_PRIMARY_IDX]; + + return 0; +} + +/** + * irdma_sc_srq_init - init sc_srq structure + * @srq: srq sc struct + * @info: parameters for srq init + */ +int irdma_sc_srq_init(struct irdma_sc_srq *srq, + struct irdma_srq_init_info *info) +{ + u32 srq_size_quanta; + int ret_code; + + ret_code = irdma_uk_srq_init(&srq->srq_uk, &info->srq_uk_init_info); + if (ret_code) + return ret_code; + + srq->dev = info->pd->dev; + srq->pd = info->pd; + srq->vsi = info->vsi; + srq->srq_pa = info->srq_pa; + srq->first_pm_pbl_idx = info->first_pm_pbl_idx; + srq->pasid = info->pasid; + srq->pasid_valid = info->pasid_valid; + srq->srq_limit = info->srq_limit; + srq->leaf_pbl_size = info->leaf_pbl_size; + srq->virtual_map = info->virtual_map; + srq->tph_en = info->tph_en; + srq->arm_limit_event = info->arm_limit_event; + srq->tph_val = info->tph_value; + srq->shadow_area_pa = info->shadow_area_pa; + + /* Smallest SRQ size is 256B i.e. 8 quanta */ + srq_size_quanta = max((u32)IRDMA_SRQ_MIN_QUANTA, + srq->srq_uk.srq_size * srq->srq_uk.wqe_size_multiplier); + srq->hw_srq_size = irdma_get_encoded_wqe_size(srq_size_quanta, IRDMA_QUEUE_TYPE_SRQ); + + return 0; +} + +/** + * irdma_sc_srq_create - send srq create CQP WQE + * @srq: srq sc struct + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_srq_create(struct irdma_sc_srq *srq, u64 scratch, + bool post_sq) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + + cqp = srq->pd->dev->cqp; + if (srq->srq_uk.srq_id < cqp->dev->hw_attrs.min_hw_srq_id || + srq->srq_uk.srq_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].max_cnt - 1)) + return -EINVAL; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, + FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQ_LIMIT, srq->srq_limit) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_RQSIZE, srq->hw_srq_size) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE, srq->srq_uk.wqe_size)); + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQCTX, srq->srq_uk.srq_id)); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_SRQ_PD_ID, srq->pd->pd_id)); + set_64bit_val(wqe, 32, + FIELD_PREP(IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR, + srq->srq_pa >> IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S)); + set_64bit_val(wqe, 40, + FIELD_PREP(IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR, + srq->shadow_area_pa >> IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S)); + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX, srq->first_pm_pbl_idx)); + + hdr = srq->srq_uk.srq_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_SRQ) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE, srq->leaf_pbl_size) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_VIRTMAP, srq->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT, + srq->arm_limit_event) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: SRQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_srq_modify - send modify_srq CQP WQE + * @srq: srq sc struct + * @info: parameters for srq modification + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_srq_modify(struct irdma_sc_srq *srq, + struct irdma_modify_srq_info *info, u64 scratch, + bool post_sq) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + + cqp = srq->dev->cqp; + if (srq->srq_uk.srq_id < cqp->dev->hw_attrs.min_hw_srq_id || + srq->srq_uk.srq_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].max_cnt - 1)) + return -EINVAL; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, + FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQ_LIMIT, info->srq_limit) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_RQSIZE, srq->hw_srq_size) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE, srq->srq_uk.wqe_size)); + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMA_CQPSQ_SRQ_SRQCTX, srq->srq_uk.srq_id)); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_SRQ_PD_ID, srq->pd->pd_id)); + set_64bit_val(wqe, 32, + FIELD_PREP(IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR, + srq->srq_pa >> IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S)); + set_64bit_val(wqe, 40, + FIELD_PREP(IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR, + srq->shadow_area_pa >> IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S)); + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX, srq->first_pm_pbl_idx)); + + hdr = srq->srq_uk.srq_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_SRQ) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE, srq->leaf_pbl_size) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_VIRTMAP, srq->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT, + info->arm_limit_event) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: SRQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_srq_destroy - send srq_destroy CQP WQE + * @srq: srq sc struct + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_srq_destroy(struct irdma_sc_srq *srq, u64 scratch, + bool post_sq) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + + cqp = srq->dev->cqp; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 8, (u64)srq); + + hdr = srq->srq_uk.srq_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_SRQ) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: SRQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_qp_create - create qp + * @qp: sc qp + * @info: qp create info + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_qp_create(struct irdma_sc_qp *qp, struct irdma_create_qp_info *info, + u64 scratch, bool post_sq) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + + cqp = qp->dev->cqp; + if (qp->qp_uk.qp_id < cqp->dev->hw_attrs.min_hw_qp_id || + qp->qp_uk.qp_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt - 1)) + return -EINVAL; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); + set_64bit_val(wqe, 40, qp->shadow_area_pa); + + hdr = qp->qp_uk.qp_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | + FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | + FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | + FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, + info->arp_cache_idx_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: QP_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_qp_modify - modify qp cqp wqe + * @qp: sc qp + * @info: modify qp info + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_qp_modify(struct irdma_sc_qp *qp, struct irdma_modify_qp_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + struct irdma_sc_cqp *cqp; + u64 hdr; + u8 term_actions = 0; + u8 term_len = 0; + + cqp = qp->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + if (info->next_iwarp_state == IRDMA_QP_STATE_TERMINATE) { + if (info->dont_send_fin) + term_actions += IRDMAQP_TERM_SEND_TERM_ONLY; + if (info->dont_send_term) + term_actions += IRDMAQP_TERM_SEND_FIN_ONLY; + if (term_actions == IRDMAQP_TERM_SEND_TERM_AND_FIN || + term_actions == IRDMAQP_TERM_SEND_TERM_ONLY) + term_len = info->termlen; + } + + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMA_CQPSQ_QP_NEWMSS, info->new_mss) | + FIELD_PREP(IRDMA_CQPSQ_QP_TERMLEN, term_len)); + set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); + set_64bit_val(wqe, 40, qp->shadow_area_pa); + + hdr = qp->qp_uk.qp_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_QP) | + FIELD_PREP(IRDMA_CQPSQ_QP_ORDVALID, info->ord_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_TOECTXVALID, info->tcp_ctx_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_CACHEDVARVALID, + info->cached_var_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_VQ, qp->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_QP_FORCELOOPBACK, info->force_lpb) | + FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, info->cq_num_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_MACVALID, info->mac_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | + FIELD_PREP(IRDMA_CQPSQ_QP_MSSCHANGE, info->mss_change) | + FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, + info->remove_hash_idx) | + FIELD_PREP(IRDMA_CQPSQ_QP_TERMACT, term_actions) | + FIELD_PREP(IRDMA_CQPSQ_QP_RESETCON, info->reset_tcp_conn) | + FIELD_PREP(IRDMA_CQPSQ_QP_ARPTABIDXVALID, + info->arp_cache_idx_valid) | + FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, info->next_iwarp_state) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: QP_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_qp_destroy - cqp destroy qp + * @qp: sc qp + * @scratch: u64 saved to be used during cqp completion + * @remove_hash_idx: flag if to remove hash idx + * @ignore_mw_bnd: memory window bind flag + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch, + bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq) +{ + __le64 *wqe; + struct irdma_sc_cqp *cqp; + u64 hdr; + + cqp = qp->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); + set_64bit_val(wqe, 40, qp->shadow_area_pa); + + hdr = qp->qp_uk.qp_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_QP) | + FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, qp->qp_uk.qp_type) | + FIELD_PREP(IRDMA_CQPSQ_QP_IGNOREMWBOUND, ignore_mw_bnd) | + FIELD_PREP(IRDMA_CQPSQ_QP_REMOVEHASHENTRY, remove_hash_idx) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: QP_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_get_encoded_ird_size - + * @ird_size: IRD size + * The ird from the connection is rounded to a supported HW setting and then encoded + * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based + * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input + */ +static u8 irdma_sc_get_encoded_ird_size(u16 ird_size) +{ + switch (ird_size ? + roundup_pow_of_two(2 * ird_size) : 4) { + case 256: + return IRDMA_IRD_HW_SIZE_256; + case 128: + return IRDMA_IRD_HW_SIZE_128; + case 64: + case 32: + return IRDMA_IRD_HW_SIZE_64; + case 16: + case 8: + return IRDMA_IRD_HW_SIZE_16; + case 4: + default: + break; + } + + return IRDMA_IRD_HW_SIZE_4; +} + +/** + * irdma_sc_qp_setctx_roce_gen_2 - set qp's context + * @qp: sc qp + * @qp_ctx: context ptr + * @info: ctx info + */ +static void irdma_sc_qp_setctx_roce_gen_2(struct irdma_sc_qp *qp, __le64 *qp_ctx, + struct irdma_qp_host_ctx_info *info) +{ + struct irdma_roce_offload_info *roce_info; + struct irdma_udp_offload_info *udp; + u8 push_mode_en; + u32 push_idx; + + roce_info = info->roce_info; + udp = info->udp_info; + + qp->user_pri = info->user_pri; + if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { + push_mode_en = 0; + push_idx = 0; + } else { + push_mode_en = 1; + push_idx = qp->push_idx; + } + set_64bit_val(qp_ctx, 0, + FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | + FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | + FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | + FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | + FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | + FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | + FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) | + FIELD_PREP(IRDMAQPC_PDIDXHI, roce_info->pd_id >> 16) | + FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) | + FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, roce_info->err_rq_idx_valid) | + FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) | + FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) | + FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) | + FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag)); + set_64bit_val(qp_ctx, 8, qp->sq_pa); + set_64bit_val(qp_ctx, 16, qp->rq_pa); + if (roce_info->dcqcn_en || roce_info->dctcp_en) { + udp->tos &= ~ECN_CODE_PT_MASK; + udp->tos |= ECN_CODE_PT_VAL; + } + + set_64bit_val(qp_ctx, 24, + FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | + FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) | + FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | FIELD_PREP(IRDMAQPC_TOS, udp->tos) | + FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) | + FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port)); + set_64bit_val(qp_ctx, 32, + FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) | + FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3])); + set_64bit_val(qp_ctx, 40, + FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) | + FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1])); + set_64bit_val(qp_ctx, 48, + FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) | + FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) | + FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx)); + set_64bit_val(qp_ctx, 56, + FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) | + FIELD_PREP(IRDMAQPC_PDIDX, roce_info->pd_id) | + FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) | + FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label)); + set_64bit_val(qp_ctx, 64, + FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) | + FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp)); + set_64bit_val(qp_ctx, 80, + FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) | + FIELD_PREP(IRDMAQPC_LSN, udp->lsn)); + set_64bit_val(qp_ctx, 88, + FIELD_PREP(IRDMAQPC_EPSN, udp->epsn)); + set_64bit_val(qp_ctx, 96, + FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) | + FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una)); + set_64bit_val(qp_ctx, 112, + FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd)); + set_64bit_val(qp_ctx, 128, + FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, roce_info->err_rq_idx) | + FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) | + FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) | + FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin)); + set_64bit_val(qp_ctx, 136, + FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | + FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); + set_64bit_val(qp_ctx, 144, + FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); + set_64bit_val(qp_ctx, 152, + FIELD_PREP(IRDMAQPC_MACADDRESS, + ether_addr_to_u64(roce_info->mac_addr))); + set_64bit_val(qp_ctx, 160, + FIELD_PREP(IRDMAQPC_ORDSIZE, roce_info->ord_size) | + FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(roce_info->ird_size)) | + FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) | + FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) | + FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | + FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) | + FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) | + FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) | + FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, roce_info->fw_cc_enable) | + FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, roce_info->udprivcq_en) | + FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) | + FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en)); + set_64bit_val(qp_ctx, 168, + FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); + set_64bit_val(qp_ctx, 176, + FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | + FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | + FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); + set_64bit_val(qp_ctx, 184, + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) | + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2])); + set_64bit_val(qp_ctx, 192, + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) | + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0])); + set_64bit_val(qp_ctx, 200, + FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) | + FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low)); + set_64bit_val(qp_ctx, 208, + FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); + + print_hex_dump_debug("WQE: QP_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16, + 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); +} + +/** + * irdma_sc_get_encoded_ird_size_gen_3 - get encoded IRD size for GEN 3 + * @ird_size: IRD size + * The ird from the connection is rounded to a supported HW setting and then encoded + * for ird_size field of qp_ctx. Consumers are expected to provide valid ird size based + * on hardware attributes. IRD size defaults to a value of 4 in case of invalid input. + */ +static u8 irdma_sc_get_encoded_ird_size_gen_3(u16 ird_size) +{ + + switch (ird_size ? + roundup_pow_of_two(2 * ird_size) : 4) { + case 4096: + return IRDMA_IRD_HW_SIZE_4096_GEN3; + case 2048: + return IRDMA_IRD_HW_SIZE_2048_GEN3; + case 1024: + return IRDMA_IRD_HW_SIZE_1024_GEN3; + case 512: + return IRDMA_IRD_HW_SIZE_512_GEN3; + case 256: + return IRDMA_IRD_HW_SIZE_256_GEN3; + case 128: + return IRDMA_IRD_HW_SIZE_128_GEN3; + case 64: + return IRDMA_IRD_HW_SIZE_64_GEN3; + case 32: + return IRDMA_IRD_HW_SIZE_32_GEN3; + case 16: + return IRDMA_IRD_HW_SIZE_16_GEN3; + case 8: + return IRDMA_IRD_HW_SIZE_8_GEN3; + case 4: + default: + break; + } + + return IRDMA_IRD_HW_SIZE_4_GEN3; +} + +/** + * irdma_sc_qp_setctx_roce_gen_3 - set qp's context + * @qp: sc qp + * @qp_ctx: context ptr + * @info: ctx info + */ +static void irdma_sc_qp_setctx_roce_gen_3(struct irdma_sc_qp *qp, __le64 *qp_ctx, + struct irdma_qp_host_ctx_info *info) +{ + struct irdma_roce_offload_info *roce_info = info->roce_info; + struct irdma_udp_offload_info *udp = info->udp_info; + u64 qw0, qw3, qw7 = 0, qw8 = 0; + u8 push_mode_en; + u32 push_idx; + + qp->user_pri = info->user_pri; + if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { + push_mode_en = 0; + push_idx = 0; + } else { + push_mode_en = 1; + push_idx = qp->push_idx; + } + + qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | + FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | + FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | + FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | + FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | + FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | + FIELD_PREP(IRDMAQPC_PMENA, push_mode_en) | + FIELD_PREP(IRDMAQPSQ_FLUSH_MR, roce_info->flush_mr) | + FIELD_PREP(IRDMAQPC_DC_TCP_EN, roce_info->dctcp_en) | + FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, + roce_info->err_rq_idx_valid) | + FIELD_PREP(IRDMAQPC_ISQP1, roce_info->is_qp1) | + FIELD_PREP(IRDMAQPC_ROCE_TVER, roce_info->roce_tver) | + FIELD_PREP(IRDMAQPC_IPV4, udp->ipv4) | + FIELD_PREP(IRDMAQPC_USE_SRQ, !qp->qp_uk.srq_uk ? 0 : 1) | + FIELD_PREP(IRDMAQPC_INSERTVLANTAG, udp->insert_vlan_tag); + set_64bit_val(qp_ctx, 0, qw0); + set_64bit_val(qp_ctx, 8, qp->sq_pa); + set_64bit_val(qp_ctx, 16, qp->rq_pa); + qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | + FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size) | + FIELD_PREP(IRDMAQPC_TTL, udp->ttl) | + FIELD_PREP(IRDMAQPC_TOS, udp->tos) | + FIELD_PREP(IRDMAQPC_SRCPORTNUM, udp->src_port) | + FIELD_PREP(IRDMAQPC_DESTPORTNUM, udp->dst_port); + set_64bit_val(qp_ctx, 24, qw3); + set_64bit_val(qp_ctx, 32, + FIELD_PREP(IRDMAQPC_DESTIPADDR2, udp->dest_ip_addr[2]) | + FIELD_PREP(IRDMAQPC_DESTIPADDR3, udp->dest_ip_addr[3])); + set_64bit_val(qp_ctx, 40, + FIELD_PREP(IRDMAQPC_DESTIPADDR0, udp->dest_ip_addr[0]) | + FIELD_PREP(IRDMAQPC_DESTIPADDR1, udp->dest_ip_addr[1])); + set_64bit_val(qp_ctx, 48, + FIELD_PREP(IRDMAQPC_SNDMSS, udp->snd_mss) | + FIELD_PREP(IRDMAQPC_VLANTAG, udp->vlan_tag) | + FIELD_PREP(IRDMAQPC_ARPIDX, udp->arp_idx)); + qw7 = FIELD_PREP(IRDMAQPC_PKEY, roce_info->p_key) | + FIELD_PREP(IRDMAQPC_ACKCREDITS, roce_info->ack_credits) | + FIELD_PREP(IRDMAQPC_FLOWLABEL, udp->flow_label); + set_64bit_val(qp_ctx, 56, qw7); + qw8 = FIELD_PREP(IRDMAQPC_QKEY, roce_info->qkey) | + FIELD_PREP(IRDMAQPC_DESTQP, roce_info->dest_qp); + set_64bit_val(qp_ctx, 64, qw8); + set_64bit_val(qp_ctx, 80, + FIELD_PREP(IRDMAQPC_PSNNXT, udp->psn_nxt) | + FIELD_PREP(IRDMAQPC_LSN, udp->lsn)); + set_64bit_val(qp_ctx, 88, + FIELD_PREP(IRDMAQPC_EPSN, udp->epsn)); + set_64bit_val(qp_ctx, 96, + FIELD_PREP(IRDMAQPC_PSNMAX, udp->psn_max) | + FIELD_PREP(IRDMAQPC_PSNUNA, udp->psn_una)); + set_64bit_val(qp_ctx, 112, + FIELD_PREP(IRDMAQPC_CWNDROCE, udp->cwnd)); + set_64bit_val(qp_ctx, 128, + FIELD_PREP(IRDMAQPC_MINRNR_TIMER, udp->min_rnr_timer) | + FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, roce_info->err_rq_idx) | + FIELD_PREP(IRDMAQPC_RNRNAK_THRESH, udp->rnr_nak_thresh) | + FIELD_PREP(IRDMAQPC_REXMIT_THRESH, udp->rexmit_thresh) | + FIELD_PREP(IRDMAQPC_RNRNAK_TMR, udp->rnr_nak_tmr) | + FIELD_PREP(IRDMAQPC_RTOMIN, roce_info->rtomin)); + set_64bit_val(qp_ctx, 136, + FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | + FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); + set_64bit_val(qp_ctx, 152, + FIELD_PREP(IRDMAQPC_MACADDRESS, + ether_addr_to_u64(roce_info->mac_addr)) | + FIELD_PREP(IRDMAQPC_LOCALACKTIMEOUT, + roce_info->local_ack_timeout)); + set_64bit_val(qp_ctx, 160, + FIELD_PREP(IRDMAQPC_ORDSIZE_GEN3, roce_info->ord_size) | + FIELD_PREP(IRDMAQPC_IRDSIZE_GEN3, + irdma_sc_get_encoded_ird_size_gen_3(roce_info->ird_size)) | + FIELD_PREP(IRDMAQPC_WRRDRSPOK, roce_info->wr_rdresp_en) | + FIELD_PREP(IRDMAQPC_RDOK, roce_info->rd_en) | + FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, + info->stats_idx_valid) | + FIELD_PREP(IRDMAQPC_BINDEN, roce_info->bind_en) | + FIELD_PREP(IRDMAQPC_FASTREGEN, roce_info->fast_reg_en) | + FIELD_PREP(IRDMAQPC_DCQCNENABLE, roce_info->dcqcn_en) | + FIELD_PREP(IRDMAQPC_RCVNOICRC, roce_info->rcv_no_icrc) | + FIELD_PREP(IRDMAQPC_FW_CC_ENABLE, + roce_info->fw_cc_enable) | + FIELD_PREP(IRDMAQPC_UDPRIVCQENABLE, + roce_info->udprivcq_en) | + FIELD_PREP(IRDMAQPC_PRIVEN, roce_info->priv_mode_en) | + FIELD_PREP(IRDMAQPC_REMOTE_ATOMIC_EN, + info->remote_atomics_en) | + FIELD_PREP(IRDMAQPC_TIMELYENABLE, roce_info->timely_en)); + set_64bit_val(qp_ctx, 168, + FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); + set_64bit_val(qp_ctx, 176, + FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | + FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | + FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); + set_64bit_val(qp_ctx, 184, + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, udp->local_ipaddr[3]) | + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, udp->local_ipaddr[2])); + set_64bit_val(qp_ctx, 192, + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, udp->local_ipaddr[1]) | + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, udp->local_ipaddr[0])); + set_64bit_val(qp_ctx, 200, + FIELD_PREP(IRDMAQPC_THIGH, roce_info->t_high) | + FIELD_PREP(IRDMAQPC_SRQ_ID, + !qp->qp_uk.srq_uk ? 0 : qp->qp_uk.srq_uk->srq_id) | + FIELD_PREP(IRDMAQPC_TLOW, roce_info->t_low)); + set_64bit_val(qp_ctx, 208, roce_info->pd_id | + FIELD_PREP(IRDMAQPC_STAT_INDEX_GEN3, info->stats_idx) | + FIELD_PREP(IRDMAQPC_PKT_LIMIT, qp->pkt_limit)); + + print_hex_dump_debug("WQE: QP_HOST ROCE CTX WQE", DUMP_PREFIX_OFFSET, + 16, 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); +} + +void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx, + struct irdma_qp_host_ctx_info *info) +{ + if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) + irdma_sc_qp_setctx_roce_gen_2(qp, qp_ctx, info); + else + irdma_sc_qp_setctx_roce_gen_3(qp, qp_ctx, info); +} + +/* irdma_sc_alloc_local_mac_entry - allocate a mac entry + * @cqp: struct for cqp hw + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_alloc_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, + bool post_sq) +{ + __le64 *wqe; + u64 hdr; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, + IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: ALLOCATE_LOCAL_MAC WQE", + DUMP_PREFIX_OFFSET, 16, 8, wqe, + IRDMA_CQP_WQE_SIZE * 8, false); + + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + return 0; +} + +/** + * irdma_sc_add_local_mac_entry - add mac enry + * @cqp: struct for cqp hw + * @info:mac addr info + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_add_local_mac_entry(struct irdma_sc_cqp *cqp, + struct irdma_local_mac_entry_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + u64 header; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 32, ether_addr_to_u64(info->mac_addr)); + + header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, info->entry_idx) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, + IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, header); + + print_hex_dump_debug("WQE: ADD_LOCAL_MAC WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + return 0; +} + +/** + * irdma_sc_del_local_mac_entry - cqp wqe to dele local mac + * @cqp: struct for cqp hw + * @scratch: u64 saved to be used during cqp completion + * @entry_idx: index of mac entry + * @ignore_ref_count: to force mac adde delete + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_del_local_mac_entry(struct irdma_sc_cqp *cqp, u64 scratch, + u16 entry_idx, u8 ignore_ref_count, + bool post_sq) +{ + __le64 *wqe; + u64 header; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + header = FIELD_PREP(IRDMA_CQPSQ_MLM_TABLEIDX, entry_idx) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, + IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE) | + FIELD_PREP(IRDMA_CQPSQ_MLM_FREEENTRY, 1) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_MLM_IGNORE_REF_CNT, ignore_ref_count); + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, header); + + print_hex_dump_debug("WQE: DEL_LOCAL_MAC_IPADDR WQE", + DUMP_PREFIX_OFFSET, 16, 8, wqe, + IRDMA_CQP_WQE_SIZE * 8, false); + + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + return 0; +} + +/** + * irdma_sc_qp_setctx - set qp's context + * @qp: sc qp + * @qp_ctx: context ptr + * @info: ctx info + */ +void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx, + struct irdma_qp_host_ctx_info *info) +{ + struct irdma_iwarp_offload_info *iw; + struct irdma_tcp_offload_info *tcp; + struct irdma_sc_dev *dev; + u8 push_mode_en; + u32 push_idx; + u64 qw0, qw3, qw7 = 0, qw16 = 0; + u64 mac = 0; + + iw = info->iwarp_info; + tcp = info->tcp_info; + dev = qp->dev; + if (iw->rcv_mark_en) { + qp->pfpdu.marker_len = 4; + qp->pfpdu.rcv_start_seq = tcp->rcv_nxt; + } + qp->user_pri = info->user_pri; + if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { + push_mode_en = 0; + push_idx = 0; + } else { + push_mode_en = 1; + push_idx = qp->push_idx; + } + qw0 = FIELD_PREP(IRDMAQPC_RQWQESIZE, qp->qp_uk.rq_wqe_size) | + FIELD_PREP(IRDMAQPC_RCVTPHEN, qp->rcv_tph_en) | + FIELD_PREP(IRDMAQPC_XMITTPHEN, qp->xmit_tph_en) | + FIELD_PREP(IRDMAQPC_RQTPHEN, qp->rq_tph_en) | + FIELD_PREP(IRDMAQPC_SQTPHEN, qp->sq_tph_en) | + FIELD_PREP(IRDMAQPC_PPIDX, push_idx) | + FIELD_PREP(IRDMAQPC_PMENA, push_mode_en); + + set_64bit_val(qp_ctx, 8, qp->sq_pa); + set_64bit_val(qp_ctx, 16, qp->rq_pa); + + qw3 = FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | + FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size); + if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, + qp->src_mac_addr_idx); + set_64bit_val(qp_ctx, 136, + FIELD_PREP(IRDMAQPC_TXCQNUM, info->send_cq_num) | + FIELD_PREP(IRDMAQPC_RXCQNUM, info->rcv_cq_num)); + set_64bit_val(qp_ctx, 168, + FIELD_PREP(IRDMAQPC_QPCOMPCTX, info->qp_compl_ctx)); + set_64bit_val(qp_ctx, 176, + FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | + FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | + FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle) | + FIELD_PREP(IRDMAQPC_EXCEPTION_LAN_QUEUE, qp->ieq_qp)); + if (info->iwarp_info_valid) { + qw0 |= FIELD_PREP(IRDMAQPC_DDP_VER, iw->ddp_ver) | + FIELD_PREP(IRDMAQPC_RDMAP_VER, iw->rdmap_ver) | + FIELD_PREP(IRDMAQPC_DC_TCP_EN, iw->dctcp_en) | + FIELD_PREP(IRDMAQPC_ECN_EN, iw->ecn_en) | + FIELD_PREP(IRDMAQPC_IBRDENABLE, iw->ib_rd_en) | + FIELD_PREP(IRDMAQPC_PDIDXHI, iw->pd_id >> 16) | + FIELD_PREP(IRDMAQPC_ERR_RQ_IDX_VALID, + iw->err_rq_idx_valid); + qw7 |= FIELD_PREP(IRDMAQPC_PDIDX, iw->pd_id); + qw16 |= FIELD_PREP(IRDMAQPC_ERR_RQ_IDX, iw->err_rq_idx) | + FIELD_PREP(IRDMAQPC_RTOMIN, iw->rtomin); + set_64bit_val(qp_ctx, 144, + FIELD_PREP(IRDMAQPC_Q2ADDR, qp->q2_pa >> 8) | + FIELD_PREP(IRDMAQPC_STAT_INDEX, info->stats_idx)); + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) + mac = FIELD_PREP(IRDMAQPC_MACADDRESS, + ether_addr_to_u64(iw->mac_addr)); + + set_64bit_val(qp_ctx, 152, + mac | FIELD_PREP(IRDMAQPC_LASTBYTESENT, iw->last_byte_sent)); + set_64bit_val(qp_ctx, 160, + FIELD_PREP(IRDMAQPC_ORDSIZE, iw->ord_size) | + FIELD_PREP(IRDMAQPC_IRDSIZE, irdma_sc_get_encoded_ird_size(iw->ird_size)) | + FIELD_PREP(IRDMAQPC_WRRDRSPOK, iw->wr_rdresp_en) | + FIELD_PREP(IRDMAQPC_RDOK, iw->rd_en) | + FIELD_PREP(IRDMAQPC_SNDMARKERS, iw->snd_mark_en) | + FIELD_PREP(IRDMAQPC_FASTREGEN, iw->fast_reg_en) | + FIELD_PREP(IRDMAQPC_PRIVEN, iw->priv_mode_en) | + FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, info->stats_idx_valid) | + FIELD_PREP(IRDMAQPC_IWARPMODE, 1) | + FIELD_PREP(IRDMAQPC_RCVMARKERS, iw->rcv_mark_en) | + FIELD_PREP(IRDMAQPC_ALIGNHDRS, iw->align_hdrs) | + FIELD_PREP(IRDMAQPC_RCVNOMPACRC, iw->rcv_no_mpa_crc) | + FIELD_PREP(IRDMAQPC_RCVMARKOFFSET, iw->rcv_mark_offset || !tcp ? iw->rcv_mark_offset : tcp->rcv_nxt) | + FIELD_PREP(IRDMAQPC_SNDMARKOFFSET, iw->snd_mark_offset || !tcp ? iw->snd_mark_offset : tcp->snd_nxt) | + FIELD_PREP(IRDMAQPC_TIMELYENABLE, iw->timely_en)); + } + if (info->tcp_info_valid) { + qw0 |= FIELD_PREP(IRDMAQPC_IPV4, tcp->ipv4) | + FIELD_PREP(IRDMAQPC_NONAGLE, tcp->no_nagle) | + FIELD_PREP(IRDMAQPC_INSERTVLANTAG, + tcp->insert_vlan_tag) | + FIELD_PREP(IRDMAQPC_TIMESTAMP, tcp->time_stamp) | + FIELD_PREP(IRDMAQPC_LIMIT, tcp->cwnd_inc_limit) | + FIELD_PREP(IRDMAQPC_DROPOOOSEG, tcp->drop_ooo_seg) | + FIELD_PREP(IRDMAQPC_DUPACK_THRESH, tcp->dup_ack_thresh); + + if (iw->ecn_en || iw->dctcp_en) { + tcp->tos &= ~ECN_CODE_PT_MASK; + tcp->tos |= ECN_CODE_PT_VAL; + } + + qw3 |= FIELD_PREP(IRDMAQPC_TTL, tcp->ttl) | + FIELD_PREP(IRDMAQPC_AVOIDSTRETCHACK, tcp->avoid_stretch_ack) | + FIELD_PREP(IRDMAQPC_TOS, tcp->tos) | + FIELD_PREP(IRDMAQPC_SRCPORTNUM, tcp->src_port) | + FIELD_PREP(IRDMAQPC_DESTPORTNUM, tcp->dst_port); + if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { + qw3 |= FIELD_PREP(IRDMAQPC_GEN1_SRCMACADDRIDX, tcp->src_mac_addr_idx); + + qp->src_mac_addr_idx = tcp->src_mac_addr_idx; + } + set_64bit_val(qp_ctx, 32, + FIELD_PREP(IRDMAQPC_DESTIPADDR2, tcp->dest_ip_addr[2]) | + FIELD_PREP(IRDMAQPC_DESTIPADDR3, tcp->dest_ip_addr[3])); + set_64bit_val(qp_ctx, 40, + FIELD_PREP(IRDMAQPC_DESTIPADDR0, tcp->dest_ip_addr[0]) | + FIELD_PREP(IRDMAQPC_DESTIPADDR1, tcp->dest_ip_addr[1])); + set_64bit_val(qp_ctx, 48, + FIELD_PREP(IRDMAQPC_SNDMSS, tcp->snd_mss) | + FIELD_PREP(IRDMAQPC_SYN_RST_HANDLING, tcp->syn_rst_handling) | + FIELD_PREP(IRDMAQPC_VLANTAG, tcp->vlan_tag) | + FIELD_PREP(IRDMAQPC_ARPIDX, tcp->arp_idx)); + qw7 |= FIELD_PREP(IRDMAQPC_FLOWLABEL, tcp->flow_label) | + FIELD_PREP(IRDMAQPC_WSCALE, tcp->wscale) | + FIELD_PREP(IRDMAQPC_IGNORE_TCP_OPT, + tcp->ignore_tcp_opt) | + FIELD_PREP(IRDMAQPC_IGNORE_TCP_UNS_OPT, + tcp->ignore_tcp_uns_opt) | + FIELD_PREP(IRDMAQPC_TCPSTATE, tcp->tcp_state) | + FIELD_PREP(IRDMAQPC_RCVSCALE, tcp->rcv_wscale) | + FIELD_PREP(IRDMAQPC_SNDSCALE, tcp->snd_wscale); + set_64bit_val(qp_ctx, 72, + FIELD_PREP(IRDMAQPC_TIMESTAMP_RECENT, tcp->time_stamp_recent) | + FIELD_PREP(IRDMAQPC_TIMESTAMP_AGE, tcp->time_stamp_age)); + set_64bit_val(qp_ctx, 80, + FIELD_PREP(IRDMAQPC_SNDNXT, tcp->snd_nxt) | + FIELD_PREP(IRDMAQPC_SNDWND, tcp->snd_wnd)); + set_64bit_val(qp_ctx, 88, + FIELD_PREP(IRDMAQPC_RCVNXT, tcp->rcv_nxt) | + FIELD_PREP(IRDMAQPC_RCVWND, tcp->rcv_wnd)); + set_64bit_val(qp_ctx, 96, + FIELD_PREP(IRDMAQPC_SNDMAX, tcp->snd_max) | + FIELD_PREP(IRDMAQPC_SNDUNA, tcp->snd_una)); + set_64bit_val(qp_ctx, 104, + FIELD_PREP(IRDMAQPC_SRTT, tcp->srtt) | + FIELD_PREP(IRDMAQPC_RTTVAR, tcp->rtt_var)); + set_64bit_val(qp_ctx, 112, + FIELD_PREP(IRDMAQPC_SSTHRESH, tcp->ss_thresh) | + FIELD_PREP(IRDMAQPC_CWND, tcp->cwnd)); + set_64bit_val(qp_ctx, 120, + FIELD_PREP(IRDMAQPC_SNDWL1, tcp->snd_wl1) | + FIELD_PREP(IRDMAQPC_SNDWL2, tcp->snd_wl2)); + qw16 |= FIELD_PREP(IRDMAQPC_MAXSNDWND, tcp->max_snd_window) | + FIELD_PREP(IRDMAQPC_REXMIT_THRESH, tcp->rexmit_thresh); + set_64bit_val(qp_ctx, 184, + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR3, tcp->local_ipaddr[3]) | + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR2, tcp->local_ipaddr[2])); + set_64bit_val(qp_ctx, 192, + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR1, tcp->local_ipaddr[1]) | + FIELD_PREP(IRDMAQPC_LOCAL_IPADDR0, tcp->local_ipaddr[0])); + set_64bit_val(qp_ctx, 200, + FIELD_PREP(IRDMAQPC_THIGH, iw->t_high) | + FIELD_PREP(IRDMAQPC_TLOW, iw->t_low)); + set_64bit_val(qp_ctx, 208, + FIELD_PREP(IRDMAQPC_REMENDPOINTIDX, info->rem_endpoint_idx)); + } + + set_64bit_val(qp_ctx, 0, qw0); + set_64bit_val(qp_ctx, 24, qw3); + set_64bit_val(qp_ctx, 56, qw7); + set_64bit_val(qp_ctx, 128, qw16); + + print_hex_dump_debug("WQE: QP_HOST CTX", DUMP_PREFIX_OFFSET, 16, 8, + qp_ctx, IRDMA_QP_CTX_SIZE, false); +} + +/** + * irdma_sc_alloc_stag - mr stag alloc + * @dev: sc device struct + * @info: stag info + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_alloc_stag(struct irdma_sc_dev *dev, + struct irdma_allocate_stag_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + struct irdma_sc_cqp *cqp; + u64 hdr; + enum irdma_page_size page_size; + + if (!info->total_len && !info->all_memory) + return -EINVAL; + + if (info->page_size == 0x40000000) + page_size = IRDMA_PAGE_SIZE_1G; + else if (info->page_size == 0x200000) + page_size = IRDMA_PAGE_SIZE_2M; + else + page_size = IRDMA_PAGE_SIZE_4K; + + cqp = dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 8, + FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID) | + FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len)); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx) | + FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18)); + set_64bit_val(wqe, 40, + FIELD_PREP(IRDMA_CQPSQ_STAG_HMCFNIDX, info->hmc_fcn_index) | + FIELD_PREP(IRDMA_CQPSQ_STAG_NON_CACHED, info->non_cached) | + FIELD_PREP(IRDMA_CQPSQ_STAG_USE_ASO, info->use_aso) | + FIELD_PREP(IRDMA_CQPSQ_STAG_ASO_HOST_ID, info->aso_host_id) | + FIELD_PREP(IRDMA_CQPSQ_STAG_ASO_VM_VF_TYPE, info->aso_vm_vf_type) | + FIELD_PREP(IRDMA_CQPSQ_STAG_ASO_VM_VF_NUM, info->aso_vm_vf_num) | + FIELD_PREP(IRDMA_CQPSQ_STAG_ASO_PF_NUM, info->aso_pf_num)); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_PASID, info->pasid)); + + if (info->chunk_size) + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_idx)); + + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | + FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | + FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | + FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | + FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | + FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, info->remote_access) | + FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | + FIELD_PREP(IRDMA_CQPSQ_STAG_PLACEMENTTYPE, info->placement_type) | + FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | + FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, info->pasid_valid) | + FIELD_PREP(IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN, info->remote_atomics_en) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: ALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_mr_reg_non_shared - non-shared mr registration + * @dev: sc device struct + * @info: mr info + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_mr_reg_non_shared(struct irdma_sc_dev *dev, + struct irdma_reg_ns_stag_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + u64 fbo; + struct irdma_sc_cqp *cqp; + u64 hdr; + u32 pble_obj_cnt; + bool remote_access; + u8 addr_type; + enum irdma_page_size page_size; + + if (!info->total_len && !info->all_memory) + return -EINVAL; + + if (info->page_size == 0x40000000) + page_size = IRDMA_PAGE_SIZE_1G; + else if (info->page_size == 0x200000) + page_size = IRDMA_PAGE_SIZE_2M; + else if (info->page_size == 0x1000) + page_size = IRDMA_PAGE_SIZE_4K; + else + return -EINVAL; + + if (info->access_rights & (IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY | + IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY)) + remote_access = true; + else + remote_access = false; + + pble_obj_cnt = dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; + if (info->chunk_size && info->first_pm_pbl_index >= pble_obj_cnt) + return -EINVAL; + + cqp = dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + fbo = info->va & (info->page_size - 1); + + set_64bit_val(wqe, 0, + (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED ? + info->va : fbo)); + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMA_CQPSQ_STAG_STAGLEN, info->total_len) | + FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_STAG_KEY, info->stag_key) | + FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18) | + FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx)); + if (!info->chunk_size) + set_64bit_val(wqe, 32, info->reg_addr_pa); + else + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX, info->first_pm_pbl_index)); + set_64bit_val(wqe, 40, FIELD_PREP(IRDMA_CQPSQ_STAG_NON_CACHED, info->non_cached) | + info->hmc_fcn_index); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_PASID, info->pasid)); + + addr_type = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? 1 : 0; + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_REG_MR) | + FIELD_PREP(IRDMA_CQPSQ_STAG_MR, 1) | + FIELD_PREP(IRDMA_CQPSQ_STAG_LPBLSIZE, info->chunk_size) | + FIELD_PREP(IRDMA_CQPSQ_STAG_HPAGESIZE, page_size) | + FIELD_PREP(IRDMA_CQPSQ_STAG_ARIGHTS, info->access_rights) | + FIELD_PREP(IRDMA_CQPSQ_STAG_REMACCENABLED, remote_access) | + FIELD_PREP(IRDMA_CQPSQ_STAG_VABASEDTO, addr_type) | + FIELD_PREP(IRDMA_CQPSQ_STAG_USEHMCFNIDX, info->use_hmc_fcn_index) | + FIELD_PREP(IRDMA_CQPSQ_STAG_PLACEMENTTYPE, info->placement_type) | + FIELD_PREP(IRDMA_CQPSQ_STAG_USEPFRID, info->use_pf_rid) | + FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, info->pasid_valid) | + FIELD_PREP(IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN, + info->remote_atomics_en) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: MR_REG_NS WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_dealloc_stag - deallocate stag + * @dev: sc device struct + * @info: dealloc stag info + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_dealloc_stag(struct irdma_sc_dev *dev, + struct irdma_dealloc_stag_info *info, + u64 scratch, bool post_sq) +{ + u64 hdr; + __le64 *wqe; + struct irdma_sc_cqp *cqp; + + cqp = dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 8, + FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->stag_idx) | + FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18)); + + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DEALLOC_STAG) | + FIELD_PREP(IRDMA_CQPSQ_STAG_MR, info->mr) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: DEALLOC_STAG WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_mw_alloc - mw allocate + * @dev: sc device struct + * @info: memory window allocation information + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_mw_alloc(struct irdma_sc_dev *dev, + struct irdma_mw_alloc_info *info, u64 scratch, + bool post_sq) +{ + u64 hdr; + struct irdma_sc_cqp *cqp; + __le64 *wqe; + + cqp = dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 8, + FLD_LS_64(dev, info->pd_id, IRDMA_CQPSQ_STAG_PDID)); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_STAG_IDX, info->mw_stag_index) | + FIELD_PREP(IRDMA_CQPSQ_STAG_PDID_HI, info->pd_id >> 18)); + + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_ALLOC_STAG) | + FIELD_PREP(IRDMA_CQPSQ_STAG_MWTYPE, info->mw_wide) | + FIELD_PREP(IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY, + info->mw1_bind_dont_vldt_key) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: MW_ALLOC WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_mr_fast_register - Posts RDMA fast register mr WR to iwarp qp + * @qp: sc qp struct + * @info: fast mr info + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_mr_fast_register(struct irdma_sc_qp *qp, + struct irdma_fast_reg_stag_info *info, + bool post_sq) +{ + u64 temp, hdr; + __le64 *wqe; + u32 wqe_idx; + u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; + enum irdma_page_size page_size; + struct irdma_post_sq_info sq_info = {}; + + if (info->page_size == 0x40000000) + page_size = IRDMA_PAGE_SIZE_1G; + else if (info->page_size == 0x200000) + page_size = IRDMA_PAGE_SIZE_2M; + else + page_size = IRDMA_PAGE_SIZE_4K; + + sq_info.wr_id = info->wr_id; + sq_info.signaled = info->signaled; + sq_info.push_wqe = info->push_wqe; + + wqe = irdma_qp_get_next_send_wqe(&qp->qp_uk, &wqe_idx, &quanta, 0, &sq_info); + if (!wqe) + return -ENOMEM; + + ibdev_dbg(to_ibdev(qp->dev), + "MR: wr_id[%llxh] wqe_idx[%04d] location[%p]\n", + info->wr_id, wqe_idx, + &qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid); + + temp = (info->addr_type == IRDMA_ADDR_TYPE_VA_BASED) ? + (uintptr_t)info->va : info->fbo; + set_64bit_val(wqe, 0, temp); + + temp = FIELD_GET(IRDMAQPSQ_FIRSTPMPBLIDXHI, + info->first_pm_pbl_index >> 16); + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXHI, temp) | + FIELD_PREP(IRDMAQPSQ_PBLADDR, info->reg_addr_pa >> IRDMA_HW_PAGE_SHIFT)); + set_64bit_val(wqe, 16, + info->total_len | + FIELD_PREP(IRDMAQPSQ_FIRSTPMPBLIDXLO, info->first_pm_pbl_index)); + + hdr = FIELD_PREP(IRDMAQPSQ_STAGKEY, info->stag_key) | + FIELD_PREP(IRDMAQPSQ_STAGINDEX, info->stag_idx) | + FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FAST_REGISTER) | + FIELD_PREP(IRDMAQPSQ_LPBLSIZE, info->chunk_size) | + FIELD_PREP(IRDMAQPSQ_HPAGESIZE, page_size) | + FIELD_PREP(IRDMAQPSQ_STAGRIGHTS, info->access_rights) | + FIELD_PREP(IRDMAQPSQ_VABASEDTO, info->addr_type) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, (sq_info.push_wqe ? 1 : 0)) | + FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_REMOTE_ATOMICS_EN, info->remote_atomics_en) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: FAST_REG WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_QP_WQE_MIN_SIZE, false); + if (sq_info.push_wqe) + irdma_qp_push_wqe(&qp->qp_uk, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(&qp->qp_uk); + + return 0; +} + +/** + * irdma_sc_gen_rts_ae - request AE generated after RTS + * @qp: sc qp struct + */ +static void irdma_sc_gen_rts_ae(struct irdma_sc_qp *qp) +{ + __le64 *wqe; + u64 hdr; + struct irdma_qp_uk *qp_uk; + + qp_uk = &qp->qp_uk; + + wqe = qp_uk->sq_base[1].elem; + + hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + print_hex_dump_debug("QP: NOP W/LOCAL FENCE WQE", DUMP_PREFIX_OFFSET, + 16, 8, wqe, IRDMA_QP_WQE_MIN_SIZE, false); + + wqe = qp_uk->sq_base[2].elem; + hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_GEN_RTS_AE) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + print_hex_dump_debug("QP: CONN EST WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_QP_WQE_MIN_SIZE, false); + if (qp->qp_uk.start_wqe_idx) { + wqe = qp_uk->sq_base[3].elem; + hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, 1) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + } +} + +/** + * irdma_sc_send_lsmm - send last streaming mode message + * @qp: sc qp struct + * @lsmm_buf: buffer with lsmm message + * @size: size of lsmm buffer + * @stag: stag of lsmm buffer + */ +void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size, + irdma_stag stag) +{ + __le64 *wqe; + u64 hdr; + struct irdma_qp_uk *qp_uk; + + qp_uk = &qp->qp_uk; + wqe = qp_uk->sq_base->elem; + + set_64bit_val(wqe, 0, (uintptr_t)lsmm_buf); + if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, size) | + FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, stag)); + } else { + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_FRAG_LEN, size) | + FIELD_PREP(IRDMAQPSQ_FRAG_STAG, stag) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); + } + set_64bit_val(wqe, 16, 0); + + hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_SEND) | + FIELD_PREP(IRDMAQPSQ_STREAMMODE, 1) | + FIELD_PREP(IRDMAQPSQ_WAITFORRCVPDU, 1) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: SEND_LSMM WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_QP_WQE_MIN_SIZE, false); + + if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) + irdma_sc_gen_rts_ae(qp); +} + +/** + * irdma_sc_send_rtt - send last read0 or write0 + * @qp: sc qp struct + * @read: Do read0 or write0 + */ +void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read) +{ + __le64 *wqe; + u64 hdr; + struct irdma_qp_uk *qp_uk; + + qp_uk = &qp->qp_uk; + wqe = qp_uk->sq_base->elem; + + set_64bit_val(wqe, 0, 0); + set_64bit_val(wqe, 16, 0); + if (read) { + if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, 0xabcd)); + } else { + set_64bit_val(wqe, 8, + (u64)0xabcd | FIELD_PREP(IRDMAQPSQ_VALID, + qp->qp_uk.swqe_polarity)); + } + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, 0x1234) | + FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_READ) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); + + } else { + if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { + set_64bit_val(wqe, 8, 0); + } else { + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity)); + } + hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_RDMA_WRITE) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->qp_uk.swqe_polarity); + } + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: RTR WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, + IRDMA_QP_WQE_MIN_SIZE, false); + + if (qp->dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) + irdma_sc_gen_rts_ae(qp); +} + +/** + * irdma_iwarp_opcode - determine if incoming is rdma layer + * @info: aeq info for the packet + * @pkt: packet for error + */ +static u32 irdma_iwarp_opcode(struct irdma_aeqe_info *info, u8 *pkt) +{ + __be16 *mpa; + u32 opcode = 0xffffffff; + + if (info->q2_data_written) { + mpa = (__be16 *)pkt; + opcode = ntohs(mpa[1]) & 0xf; + } + + return opcode; +} + +/** + * irdma_locate_mpa - return pointer to mpa in the pkt + * @pkt: packet with data + */ +static u8 *irdma_locate_mpa(u8 *pkt) +{ + /* skip over ethernet header */ + pkt += IRDMA_MAC_HLEN; + + /* Skip over IP and TCP headers */ + pkt += 4 * (pkt[0] & 0x0f); + pkt += 4 * ((pkt[12] >> 4) & 0x0f); + + return pkt; +} + +/** + * irdma_bld_termhdr_ctrl - setup terminate hdr control fields + * @qp: sc qp ptr for pkt + * @hdr: term hdr + * @opcode: flush opcode for termhdr + * @layer_etype: error layer + error type + * @err: error cod ein the header + */ +static void irdma_bld_termhdr_ctrl(struct irdma_sc_qp *qp, + struct irdma_terminate_hdr *hdr, + enum irdma_flush_opcode opcode, + u8 layer_etype, u8 err) +{ + qp->flush_code = opcode; + hdr->layer_etype = layer_etype; + hdr->error_code = err; +} + +/** + * irdma_bld_termhdr_ddp_rdma - setup ddp and rdma hdrs in terminate hdr + * @pkt: ptr to mpa in offending pkt + * @hdr: term hdr + * @copy_len: offending pkt length to be copied to term hdr + * @is_tagged: DDP tagged or untagged + */ +static void irdma_bld_termhdr_ddp_rdma(u8 *pkt, struct irdma_terminate_hdr *hdr, + int *copy_len, u8 *is_tagged) +{ + u16 ddp_seg_len; + + ddp_seg_len = ntohs(*(__be16 *)pkt); + if (ddp_seg_len) { + *copy_len = 2; + hdr->hdrct = DDP_LEN_FLAG; + if (pkt[2] & 0x80) { + *is_tagged = 1; + if (ddp_seg_len >= TERM_DDP_LEN_TAGGED) { + *copy_len += TERM_DDP_LEN_TAGGED; + hdr->hdrct |= DDP_HDR_FLAG; + } + } else { + if (ddp_seg_len >= TERM_DDP_LEN_UNTAGGED) { + *copy_len += TERM_DDP_LEN_UNTAGGED; + hdr->hdrct |= DDP_HDR_FLAG; + } + if (ddp_seg_len >= (TERM_DDP_LEN_UNTAGGED + TERM_RDMA_LEN) && + ((pkt[3] & RDMA_OPCODE_M) == RDMA_READ_REQ_OPCODE)) { + *copy_len += TERM_RDMA_LEN; + hdr->hdrct |= RDMA_HDR_FLAG; + } + } + } +} + +/** + * irdma_bld_terminate_hdr - build terminate message header + * @qp: qp associated with received terminate AE + * @info: the struct contiaing AE information + */ +static int irdma_bld_terminate_hdr(struct irdma_sc_qp *qp, + struct irdma_aeqe_info *info) +{ + u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; + int copy_len = 0; + u8 is_tagged = 0; + u32 opcode; + struct irdma_terminate_hdr *termhdr; + + termhdr = (struct irdma_terminate_hdr *)qp->q2_buf; + memset(termhdr, 0, Q2_BAD_FRAME_OFFSET); + + if (info->q2_data_written) { + pkt = irdma_locate_mpa(pkt); + irdma_bld_termhdr_ddp_rdma(pkt, termhdr, ©_len, &is_tagged); + } + + opcode = irdma_iwarp_opcode(info, pkt); + qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; + qp->sq_flush_code = info->sq; + qp->rq_flush_code = info->rq; + + switch (info->ae_id) { + case IRDMA_AE_AMP_UNALLOCATED_STAG: + qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; + if (opcode == IRDMA_OP_TYPE_RDMA_WRITE) + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, + (LAYER_DDP << 4) | DDP_TAGGED_BUF, + DDP_TAGGED_INV_STAG); + else + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, + RDMAP_INV_STAG); + break; + case IRDMA_AE_AMP_BOUNDS_VIOLATION: + qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; + if (info->q2_data_written) + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, + (LAYER_DDP << 4) | DDP_TAGGED_BUF, + DDP_TAGGED_BOUNDS); + else + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, + RDMAP_INV_BOUNDS); + break; + case IRDMA_AE_AMP_BAD_PD: + switch (opcode) { + case IRDMA_OP_TYPE_RDMA_WRITE: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_PROT_ERR, + (LAYER_DDP << 4) | DDP_TAGGED_BUF, + DDP_TAGGED_UNASSOC_STAG); + break; + case IRDMA_OP_TYPE_SEND_INV: + case IRDMA_OP_TYPE_SEND_SOL_INV: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, + RDMAP_CANT_INV_STAG); + break; + default: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, + RDMAP_UNASSOC_STAG); + } + break; + case IRDMA_AE_AMP_INVALID_STAG: + qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, + RDMAP_INV_STAG); + break; + case IRDMA_AE_AMP_BAD_QP: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_QP_OP_ERR, + (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, + DDP_UNTAGGED_INV_QN); + break; + case IRDMA_AE_AMP_BAD_STAG_KEY: + case IRDMA_AE_AMP_BAD_STAG_INDEX: + qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; + switch (opcode) { + case IRDMA_OP_TYPE_SEND_INV: + case IRDMA_OP_TYPE_SEND_SOL_INV: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, + RDMAP_CANT_INV_STAG); + break; + default: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, + RDMAP_INV_STAG); + } + break; + case IRDMA_AE_AMP_RIGHTS_VIOLATION: + case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: + case IRDMA_AE_PRIV_OPERATION_DENIED: + qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, + RDMAP_ACCESS); + break; + case IRDMA_AE_AMP_TO_WRAP: + qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_ACCESS_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_PROT, + RDMAP_TO_WRAP); + break; + case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, + (LAYER_MPA << 4) | DDP_LLP, MPA_CRC); + break; + case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, + (LAYER_DDP << 4) | DDP_CATASTROPHIC, + DDP_CATASTROPHIC_LOCAL); + break; + case IRDMA_AE_LCE_QP_CATASTROPHIC: + case IRDMA_AE_DDP_NO_L_BIT: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, + (LAYER_DDP << 4) | DDP_CATASTROPHIC, + DDP_CATASTROPHIC_LOCAL); + break; + case IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, + (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, + DDP_UNTAGGED_INV_MSN_RANGE); + break; + case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: + qp->event_type = IRDMA_QP_EVENT_ACCESS_ERR; + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_LOC_LEN_ERR, + (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, + DDP_UNTAGGED_INV_TOO_LONG); + break; + case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: + if (is_tagged) + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, + (LAYER_DDP << 4) | DDP_TAGGED_BUF, + DDP_TAGGED_INV_DDP_VER); + else + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, + (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, + DDP_UNTAGGED_INV_DDP_VER); + break; + case IRDMA_AE_DDP_UBE_INVALID_MO: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, + (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, + DDP_UNTAGGED_INV_MO); + break; + case IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_REM_OP_ERR, + (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, + DDP_UNTAGGED_INV_MSN_NO_BUF); + break; + case IRDMA_AE_DDP_UBE_INVALID_QN: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, + (LAYER_DDP << 4) | DDP_UNTAGGED_BUF, + DDP_UNTAGGED_INV_QN); + break; + case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_GENERAL_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, + RDMAP_INV_RDMAP_VER); + break; + default: + irdma_bld_termhdr_ctrl(qp, termhdr, FLUSH_FATAL_ERR, + (LAYER_RDMA << 4) | RDMAP_REMOTE_OP, + RDMAP_UNSPECIFIED); + break; + } + + if (copy_len) + memcpy(termhdr + 1, pkt, copy_len); + + return sizeof(*termhdr) + copy_len; +} + +/** + * irdma_terminate_send_fin() - Send fin for terminate message + * @qp: qp associated with received terminate AE + */ +void irdma_terminate_send_fin(struct irdma_sc_qp *qp) +{ + irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, + IRDMAQP_TERM_SEND_FIN_ONLY, 0); +} + +/** + * irdma_terminate_connection() - Bad AE and send terminate to remote QP + * @qp: qp associated with received terminate AE + * @info: the struct contiaing AE information + */ +void irdma_terminate_connection(struct irdma_sc_qp *qp, + struct irdma_aeqe_info *info) +{ + u8 termlen = 0; + + if (qp->term_flags & IRDMA_TERM_SENT) + return; + + termlen = irdma_bld_terminate_hdr(qp, info); + irdma_terminate_start_timer(qp); + qp->term_flags |= IRDMA_TERM_SENT; + irdma_term_modify_qp(qp, IRDMA_QP_STATE_TERMINATE, + IRDMAQP_TERM_SEND_TERM_ONLY, termlen); +} + +/** + * irdma_terminate_received - handle terminate received AE + * @qp: qp associated with received terminate AE + * @info: the struct contiaing AE information + */ +void irdma_terminate_received(struct irdma_sc_qp *qp, + struct irdma_aeqe_info *info) +{ + u8 *pkt = qp->q2_buf + Q2_BAD_FRAME_OFFSET; + __be32 *mpa; + u8 ddp_ctl; + u8 rdma_ctl; + u16 aeq_id = 0; + struct irdma_terminate_hdr *termhdr; + + mpa = (__be32 *)irdma_locate_mpa(pkt); + if (info->q2_data_written) { + /* did not validate the frame - do it now */ + ddp_ctl = (ntohl(mpa[0]) >> 8) & 0xff; + rdma_ctl = ntohl(mpa[0]) & 0xff; + if ((ddp_ctl & 0xc0) != 0x40) + aeq_id = IRDMA_AE_LCE_QP_CATASTROPHIC; + else if ((ddp_ctl & 0x03) != 1) + aeq_id = IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION; + else if (ntohl(mpa[2]) != 2) + aeq_id = IRDMA_AE_DDP_UBE_INVALID_QN; + else if (ntohl(mpa[3]) != 1) + aeq_id = IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN; + else if (ntohl(mpa[4]) != 0) + aeq_id = IRDMA_AE_DDP_UBE_INVALID_MO; + else if ((rdma_ctl & 0xc0) != 0x40) + aeq_id = IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION; + + info->ae_id = aeq_id; + if (info->ae_id) { + /* Bad terminate recvd - send back a terminate */ + irdma_terminate_connection(qp, info); + return; + } + } + + qp->term_flags |= IRDMA_TERM_RCVD; + qp->event_type = IRDMA_QP_EVENT_CATASTROPHIC; + termhdr = (struct irdma_terminate_hdr *)&mpa[5]; + if (termhdr->layer_etype == RDMAP_REMOTE_PROT || + termhdr->layer_etype == RDMAP_REMOTE_OP) { + irdma_terminate_done(qp, 0); + } else { + irdma_terminate_start_timer(qp); + irdma_terminate_send_fin(qp); + } +} + +static int irdma_null_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri) +{ + return 0; +} + +static void irdma_null_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri) +{ + /* do nothing */ +} + +static void irdma_null_ws_reset(struct irdma_sc_vsi *vsi) +{ + /* do nothing */ +} + +/** + * irdma_sc_vsi_init - Init the vsi structure + * @vsi: pointer to vsi structure to initialize + * @info: the info used to initialize the vsi struct + */ +void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi, + struct irdma_vsi_init_info *info) +{ + u8 i; + + vsi->dev = info->dev; + vsi->back_vsi = info->back_vsi; + vsi->register_qset = info->register_qset; + vsi->unregister_qset = info->unregister_qset; + vsi->mtu = info->params->mtu; + vsi->exception_lan_q = info->exception_lan_q; + vsi->vsi_idx = info->pf_data_vsi_num; + vsi->lag_aa = info->lag_aa; + vsi->vm_vf_type = info->vm_vf_type; + + irdma_set_qos_info(vsi, info->params); + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + mutex_init(&vsi->qos[i].qos_mutex); + INIT_LIST_HEAD(&vsi->qos[i].qplist); + } + if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) { + vsi->dev->ws_add = irdma_ws_add; + vsi->dev->ws_remove = irdma_ws_remove; + vsi->dev->ws_reset = irdma_ws_reset; + } else { + vsi->dev->ws_add = irdma_null_ws_add; + vsi->dev->ws_remove = irdma_null_ws_remove; + vsi->dev->ws_reset = irdma_null_ws_reset; + } +} + +/** + * irdma_get_stats_idx - Return stats index + * @vsi: pointer to the vsi + */ +static u16 irdma_get_stats_idx(struct irdma_sc_vsi *vsi) +{ + struct irdma_stats_inst_info stats_info = {}; + struct irdma_sc_dev *dev = vsi->dev; + u8 i; + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + if (!irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_ALLOCATE, + &stats_info)) + return stats_info.stats_idx; + } + + for (i = 0; i < IRDMA_MAX_STATS_COUNT_GEN1; i++) { + if (!dev->stats_idx_array[i]) { + dev->stats_idx_array[i] = true; + return i; + } + } + + return IRDMA_INVALID_STATS_IDX; +} + +/** + * irdma_hw_stats_init_gen1 - Initialize stat reg table used for gen1 + * @vsi: vsi structure where hw_regs are set + * + * Populate the HW stats table + */ +static void irdma_hw_stats_init_gen1(struct irdma_sc_vsi *vsi) +{ + struct irdma_sc_dev *dev = vsi->dev; + const struct irdma_hw_stat_map *map; + u64 *stat_reg = vsi->hw_stats_regs; + u64 *regs = dev->hw_stats_regs; + u16 i, stats_reg_set = vsi->stats_idx; + + map = dev->hw_stats_map; + + /* First 4 stat instances are reserved for port level statistics. */ + stats_reg_set += vsi->stats_inst_alloc ? IRDMA_FIRST_NON_PF_STAT : 0; + + for (i = 0; i < dev->hw_attrs.max_stat_idx; i++) { + if (map[i].bitmask <= IRDMA_MAX_STATS_32) { + stat_reg[i] = regs[i] + + stats_reg_set * sizeof(u32); + } else { + stat_reg[i] = regs[i] + + stats_reg_set * sizeof(u64); + } + } +} + +/** + * irdma_vsi_stats_init - Initialize the vsi statistics + * @vsi: pointer to the vsi structure + * @info: The info structure used for initialization + */ +int irdma_vsi_stats_init(struct irdma_sc_vsi *vsi, + struct irdma_vsi_stats_info *info) +{ + struct irdma_dma_mem *stats_buff_mem; + + vsi->pestat = info->pestat; + vsi->pestat->hw = vsi->dev->hw; + vsi->pestat->vsi = vsi; + + stats_buff_mem = &vsi->pestat->gather_info.stats_buff_mem; + stats_buff_mem->size = ALIGN(IRDMA_GATHER_STATS_BUF_SIZE * 2, 1); + stats_buff_mem->va = dma_alloc_coherent(vsi->pestat->hw->device, + stats_buff_mem->size, + &stats_buff_mem->pa, + GFP_KERNEL); + if (!stats_buff_mem->va) + return -ENOMEM; + + vsi->pestat->gather_info.gather_stats_va = stats_buff_mem->va; + vsi->pestat->gather_info.last_gather_stats_va = + (void *)((uintptr_t)stats_buff_mem->va + + IRDMA_GATHER_STATS_BUF_SIZE); + + if (vsi->dev->hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_3) + irdma_hw_stats_start_timer(vsi); + + /* when stat allocation is not required default to fcn_id. */ + vsi->stats_idx = info->fcn_id; + if (info->alloc_stats_inst) { + u16 stats_idx = irdma_get_stats_idx(vsi); + + if (stats_idx != IRDMA_INVALID_STATS_IDX) { + vsi->stats_inst_alloc = true; + vsi->stats_idx = stats_idx; + vsi->pestat->gather_info.use_stats_inst = true; + vsi->pestat->gather_info.stats_inst_index = stats_idx; + } + } + + if (vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + irdma_hw_stats_init_gen1(vsi); + + return 0; +} + +/** + * irdma_vsi_stats_free - Free the vsi stats + * @vsi: pointer to the vsi structure + */ +void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi) +{ + struct irdma_stats_inst_info stats_info = {}; + struct irdma_sc_dev *dev = vsi->dev; + u16 stats_idx = vsi->stats_idx; + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + if (vsi->stats_inst_alloc) { + stats_info.stats_idx = vsi->stats_idx; + irdma_cqp_stats_inst_cmd(vsi, IRDMA_OP_STATS_FREE, + &stats_info); + } + } else { + if (vsi->stats_inst_alloc && + stats_idx < vsi->dev->hw_attrs.max_stat_inst) + vsi->dev->stats_idx_array[stats_idx] = false; + } + + if (!vsi->pestat) + return; + + if (dev->hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_3) + irdma_hw_stats_stop_timer(vsi); + dma_free_coherent(vsi->pestat->hw->device, + vsi->pestat->gather_info.stats_buff_mem.size, + vsi->pestat->gather_info.stats_buff_mem.va, + vsi->pestat->gather_info.stats_buff_mem.pa); + vsi->pestat->gather_info.stats_buff_mem.va = NULL; +} + +/** + * irdma_get_encoded_wqe_size - given wq size, returns hardware encoded size + * @wqsize: size of the wq (sq, rq) to encoded_size + * @queue_type: queue type selected for the calculation algorithm + */ +u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type) +{ + u8 encoded_size = 0; + + if (queue_type == IRDMA_QUEUE_TYPE_SRQ) { + /* Smallest SRQ size is 256B (8 quanta) that gets encoded to 0 */ + encoded_size = ilog2(wqsize) - 3; + + return encoded_size; + } + /* cqp sq's hw coded value starts from 1 for size of 4 + * while it starts from 0 for qp' wq's. + */ + if (queue_type == IRDMA_QUEUE_TYPE_CQP) + encoded_size = 1; + wqsize >>= 2; + while (wqsize >>= 1) + encoded_size++; + + return encoded_size; +} + +/** + * irdma_sc_gather_stats - collect the statistics + * @cqp: struct for cqp hw + * @info: gather stats info structure + * @scratch: u64 saved to be used during cqp completion + */ +static int irdma_sc_gather_stats(struct irdma_sc_cqp *cqp, + struct irdma_stats_gather_info *info, + u64 scratch) +{ + __le64 *wqe; + u64 temp; + + if (info->stats_buff_mem.size < IRDMA_GATHER_STATS_BUF_SIZE) + return -ENOMEM; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 40, + FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fcn_index)); + set_64bit_val(wqe, 32, info->stats_buff_mem.pa); + + temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_STATS_USE_INST, info->use_stats_inst) | + FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, + info->stats_inst_index) | + FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, + info->use_hmc_fcn_index) | + FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_GATHER_STATS); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, temp); + + print_hex_dump_debug("STATS: GATHER_STATS WQE", DUMP_PREFIX_OFFSET, + 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + + irdma_sc_cqp_post_sq(cqp); + return 0; +} + +/** + * irdma_sc_manage_stats_inst - allocate or free stats instance + * @cqp: struct for cqp hw + * @info: stats info structure + * @alloc: alloc vs. delete flag + * @scratch: u64 saved to be used during cqp completion + */ +static int irdma_sc_manage_stats_inst(struct irdma_sc_cqp *cqp, + struct irdma_stats_inst_info *info, + bool alloc, u64 scratch) +{ + __le64 *wqe; + u64 temp; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 40, + FIELD_PREP(IRDMA_CQPSQ_STATS_HMC_FCN_INDEX, info->hmc_fn_id)); + temp = FIELD_PREP(IRDMA_CQPSQ_STATS_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_STATS_ALLOC_INST, alloc) | + FIELD_PREP(IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX, + info->use_hmc_fcn_index) | + FIELD_PREP(IRDMA_CQPSQ_STATS_INST_INDEX, info->stats_idx) | + FIELD_PREP(IRDMA_CQPSQ_STATS_OP, IRDMA_CQP_OP_MANAGE_STATS); + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, temp); + + print_hex_dump_debug("WQE: MANAGE_STATS WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + + irdma_sc_cqp_post_sq(cqp); + return 0; +} + +/** + * irdma_sc_set_up_map - set the up map table + * @cqp: struct for cqp hw + * @info: User priority map info + * @scratch: u64 saved to be used during cqp completion + */ +static int irdma_sc_set_up_map(struct irdma_sc_cqp *cqp, + struct irdma_up_info *info, u64 scratch) +{ + __le64 *wqe; + u64 temp = 0; + int i; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) + temp |= (u64)info->map[i] << (i * 8); + + set_64bit_val(wqe, 0, temp); + set_64bit_val(wqe, 40, + FIELD_PREP(IRDMA_CQPSQ_UP_CNPOVERRIDE, info->cnp_up_override) | + FIELD_PREP(IRDMA_CQPSQ_UP_HMCFCNIDX, info->hmc_fcn_idx)); + + temp = FIELD_PREP(IRDMA_CQPSQ_UP_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_UP_USEVLAN, info->use_vlan) | + FIELD_PREP(IRDMA_CQPSQ_UP_USEOVERRIDE, + info->use_cnp_up_override) | + FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_UP_MAP); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, temp); + + print_hex_dump_debug("WQE: UPMAP WQE", DUMP_PREFIX_OFFSET, 16, 8, wqe, + IRDMA_CQP_WQE_SIZE * 8, false); + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_ws_move_node - Move WS node + * @cqp: struct for cqp hw + * @info: move node info structure + * @scratch: u64 saved to be used during cqp completion + */ +static int irdma_sc_ws_move_node(struct irdma_sc_cqp *cqp, + struct irdma_ws_move_node_info *info, + u64 scratch) +{ + __le64 *wqe; + u64 temp; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + temp = (u64)info->node_id[0] | LS_64_1(info->node_id[1], 16) | + LS_64_1(info->node_id[2], 32) | LS_64_1(info->node_id[3], 48); + set_64bit_val(wqe, 32, temp); + temp = (u64)info->node_id[4] | LS_64_1(info->node_id[5], 16) | + LS_64_1(info->node_id[6], 32) | LS_64_1(info->node_id[7], 48); + set_64bit_val(wqe, 40, temp); + temp = (u64)info->node_id[8] | LS_64_1(info->node_id[9], 16) | + LS_64_1(info->node_id[10], 32) | LS_64_1(info->node_id[11], 48); + set_64bit_val(wqe, 48, temp); + temp = (u64)info->node_id[12] | LS_64_1(info->node_id[13], 16) | + LS_64_1(info->node_id[14], 32) | LS_64_1(info->node_id[15], 48); + set_64bit_val(wqe, 56, temp); + + temp = FIELD_PREP(IRDMA_CQPSQ_WS_MOVE_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_WS_MOVE_NUM_NODES, info->num_nodes) | + FIELD_PREP(IRDMA_CQPSQ_WS_MOVE_OP, IRDMA_CQP_OP_MOVE_WS_NODES) | + FIELD_PREP(IRDMA_CQPSQ_WS_MOVE_RESUME_TRAFFIC, info->resume_traffic) | + FIELD_PREP(IRDMA_CQPSQ_WS_MOVE_TARGET_PORT, info->target_port); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, temp); + + print_hex_dump_debug("WQE: MOVE_WS WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_manage_ws_node - create/modify/destroy WS node + * @cqp: struct for cqp hw + * @info: node info structure + * @node_op: 0 for add 1 for modify, 2 for delete + * @scratch: u64 saved to be used during cqp completion + */ +static int irdma_sc_manage_ws_node(struct irdma_sc_cqp *cqp, + struct irdma_ws_node_info *info, + enum irdma_ws_node_op node_op, u64 scratch) +{ + __le64 *wqe; + u64 temp = 0; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 32, + FIELD_PREP(IRDMA_CQPSQ_WS_VSI, info->vsi) | + FIELD_PREP(IRDMA_CQPSQ_WS_FAILING_PORT, + info->failing_port) | + FIELD_PREP(IRDMA_CQPSQ_WS_ACTIVE_PORT, + info->active_port) | + FIELD_PREP(IRDMA_CQPSQ_WS_ASSIGN_TO_ACTIVE_PORT, + info->assign_to_active_port) | + FIELD_PREP(IRDMA_CQPSQ_WS_WEIGHT, info->weight)); + + temp = FIELD_PREP(IRDMA_CQPSQ_WS_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_WS_NODEOP, node_op) | + FIELD_PREP(IRDMA_CQPSQ_WS_ENABLENODE, info->enable) | + FIELD_PREP(IRDMA_CQPSQ_WS_NODETYPE, info->type_leaf) | + FIELD_PREP(IRDMA_CQPSQ_WS_PRIOTYPE, info->prio_type) | + FIELD_PREP(IRDMA_CQPSQ_WS_TC, info->tc) | + FIELD_PREP(IRDMA_CQPSQ_WS_OP, IRDMA_CQP_OP_WORK_SCHED_NODE) | + FIELD_PREP(IRDMA_CQPSQ_WS_PARENTID, info->parent_id) | + FIELD_PREP(IRDMA_CQPSQ_WS_NODEID, info->id); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, temp); + + print_hex_dump_debug("WQE: MANAGE_WS WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_qp_flush_wqes - flush qp's wqe + * @qp: sc qp + * @info: dlush information + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp, + struct irdma_qp_flush_info *info, u64 scratch, + bool post_sq) +{ + u64 temp = 0; + __le64 *wqe; + struct irdma_sc_cqp *cqp; + u64 hdr; + bool flush_sq = false, flush_rq = false; + + if (info->rq && !qp->flush_rq) + flush_rq = true; + if (info->sq && !qp->flush_sq) + flush_sq = true; + qp->flush_sq |= flush_sq; + qp->flush_rq |= flush_rq; + + if (!flush_sq && !flush_rq) { + ibdev_dbg(to_ibdev(qp->dev), + "CQP: Additional flush request ignored for qp %x\n", + qp->qp_uk.qp_id); + return -EALREADY; + } + + cqp = qp->pd->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + if (info->userflushcode) { + if (flush_rq) + temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMNERR, + info->rq_minor_code) | + FIELD_PREP(IRDMA_CQPSQ_FWQE_RQMJERR, + info->rq_major_code); + if (flush_sq) + temp |= FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMNERR, + info->sq_minor_code) | + FIELD_PREP(IRDMA_CQPSQ_FWQE_SQMJERR, + info->sq_major_code); + } + set_64bit_val(wqe, 16, temp); + + temp = (info->generate_ae) ? + info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, + info->ae_src) : 0; + set_64bit_val(wqe, 8, temp); + set_64bit_val(wqe, 40, + FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_SQ_IDX, info->err_sq_idx)); + + hdr = qp->qp_uk.qp_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_FLUSH_WQES) | + FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, info->generate_ae) | + FIELD_PREP(IRDMA_CQPSQ_FWQE_ERR_SQ_IDX_VALID, info->err_sq_idx_valid) | + FIELD_PREP(IRDMA_CQPSQ_FWQE_USERFLCODE, info->userflushcode) | + FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHSQ, flush_sq) | + FIELD_PREP(IRDMA_CQPSQ_FWQE_FLUSHRQ, flush_rq) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: QP_FLUSH WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_gen_ae - generate AE, uses flush WQE CQP OP + * @qp: sc qp + * @info: gen ae information + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_gen_ae(struct irdma_sc_qp *qp, + struct irdma_gen_ae_info *info, u64 scratch, + bool post_sq) +{ + u64 temp; + __le64 *wqe; + struct irdma_sc_cqp *cqp; + u64 hdr; + + cqp = qp->pd->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + temp = info->ae_code | FIELD_PREP(IRDMA_CQPSQ_FWQE_AESOURCE, + info->ae_src); + set_64bit_val(wqe, 8, temp); + + hdr = qp->qp_uk.qp_id | FIELD_PREP(IRDMA_CQPSQ_OPCODE, + IRDMA_CQP_OP_GEN_AE) | + FIELD_PREP(IRDMA_CQPSQ_FWQE_GENERATE_AE, 1) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: GEN_AE WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/*** irdma_sc_qp_upload_context - upload qp's context + * @dev: sc device struct + * @info: upload context info ptr for return + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_qp_upload_context(struct irdma_sc_dev *dev, + struct irdma_upload_context_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + struct irdma_sc_cqp *cqp; + u64 hdr; + + cqp = dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, info->buf_pa); + + hdr = FIELD_PREP(IRDMA_CQPSQ_UCTX_QPID, info->qp_id) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPLOAD_CONTEXT) | + FIELD_PREP(IRDMA_CQPSQ_UCTX_QPTYPE, info->qp_type) | + FIELD_PREP(IRDMA_CQPSQ_UCTX_RAWFORMAT, info->raw_format) | + FIELD_PREP(IRDMA_CQPSQ_UCTX_FREEZEQP, info->freeze_qp) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: QP_UPLOAD_CTX WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_manage_push_page - Handle push page + * @cqp: struct for cqp hw + * @info: push page info + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int +irdma_sc_manage_push_page(struct irdma_sc_cqp *cqp, + struct irdma_cqp_manage_push_page_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + u64 hdr; + + if (info->free_page && + info->push_idx >= cqp->dev->hw_attrs.max_hw_device_pages) + return -EINVAL; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, info->qs_handle); + hdr = FIELD_PREP(IRDMA_CQPSQ_MPP_PPIDX, info->push_idx) | + FIELD_PREP(IRDMA_CQPSQ_MPP_PPTYPE, info->push_page_type) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_PUSH_PAGES) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_MPP_FREE_PAGE, info->free_page); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: MANAGE_PUSH_PAGES WQE", DUMP_PREFIX_OFFSET, + 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_suspend_qp - suspend qp for param change + * @cqp: struct for cqp hw + * @qp: sc qp struct + * @scratch: u64 saved to be used during cqp completion + */ +static int irdma_sc_suspend_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp, + u64 scratch) +{ + u64 hdr; + __le64 *wqe; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + hdr = FIELD_PREP(IRDMA_CQPSQ_SUSPENDQP_QPID, qp->qp_uk.qp_id) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_SUSPEND_QP) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: SUSPEND_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_resume_qp - resume qp after suspend + * @cqp: struct for cqp hw + * @qp: sc qp struct + * @scratch: u64 saved to be used during cqp completion + */ +static int irdma_sc_resume_qp(struct irdma_sc_cqp *cqp, struct irdma_sc_qp *qp, + u64 scratch) +{ + u64 hdr; + __le64 *wqe; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QSHANDLE, qp->qs_handle)); + + hdr = FIELD_PREP(IRDMA_CQPSQ_RESUMEQP_QPID, qp->qp_uk.qp_id) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_RESUME_QP) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: RESUME_QP WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_manage_pble_bp - manage pble + * @cqp: cqp for cqp' sq wqe + * @info: pble info + * @scratch: pointer for completion + * @post_sq: to post and ring + */ +static int irdma_sc_manage_pble_bp(struct irdma_sc_cqp *cqp, + struct irdma_manage_pble_info *info, + u64 scratch, bool post_sq) +{ + u64 temp, hdr, pd_pl_pba; + __le64 *wqe; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + temp = FIELD_PREP(IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT, info->pd_entry_cnt) | + FIELD_PREP(IRDMA_CQPSQ_MVPBP_FIRST_PD_INX, + info->first_pd_index) | + FIELD_PREP(IRDMA_CQPSQ_MVPBP_SD_INX, info->sd_index); + set_64bit_val(wqe, 16, temp); + + pd_pl_pba = + FIELD_PREP(IRDMA_CQPSQ_MVPBP_PD_PLPBA, info->pd_pl_pba >> 3); + set_64bit_val(wqe, 32, pd_pl_pba); + + hdr = FIELD_PREP(IRDMA_CQPSQ_MVPBP_INV_PD_ENT, info->inv_pd_ent ? 1 : 0) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MANAGE_PBLE_BP) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: MANAGE PBLE_BP WQE", DUMP_PREFIX_OFFSET, + 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + return 0; +} + +/** + * irdma_sc_cq_ack - acknowledge completion q + * @cq: cq struct + */ +static inline void irdma_sc_cq_ack(struct irdma_sc_cq *cq) +{ + writel(cq->cq_uk.cq_id, cq->cq_uk.cq_ack_db); +} + +/** + * irdma_sc_cq_init - initialize completion q + * @cq: cq struct + * @info: cq initialization info + */ +int irdma_sc_cq_init(struct irdma_sc_cq *cq, struct irdma_cq_init_info *info) +{ + int ret_code; + u32 pble_obj_cnt; + + pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; + if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) + return -EINVAL; + + cq->cq_pa = info->cq_base_pa; + cq->dev = info->dev; + cq->ceq_id = info->ceq_id; + info->cq_uk_init_info.cqe_alloc_db = cq->dev->cq_arm_db; + info->cq_uk_init_info.cq_ack_db = cq->dev->cq_ack_db; + ret_code = irdma_uk_cq_init(&cq->cq_uk, &info->cq_uk_init_info); + if (ret_code) + return ret_code; + + cq->virtual_map = info->virtual_map; + cq->pbl_chunk_size = info->pbl_chunk_size; + cq->ceqe_mask = info->ceqe_mask; + cq->cq_type = (info->type) ? info->type : IRDMA_CQ_TYPE_IWARP; + cq->shadow_area_pa = info->shadow_area_pa; + cq->shadow_read_threshold = info->shadow_read_threshold; + cq->ceq_id_valid = info->ceq_id_valid; + cq->tph_en = info->tph_en; + cq->tph_val = info->tph_val; + cq->first_pm_pbl_idx = info->first_pm_pbl_idx; + cq->vsi = info->vsi; + cq->pasid = info->pasid; + cq->pasid_valid = info->pasid_valid; + + return 0; +} + +/** + * irdma_sc_cq_create - create completion q + * @cq: cq struct + * @scratch: u64 saved to be used during cqp completion + * @check_overflow: flag for overflow check + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_cq_create(struct irdma_sc_cq *cq, u64 scratch, + bool check_overflow, bool post_sq) +{ + __le64 *wqe; + struct irdma_sc_cqp *cqp; + u64 hdr; + + cqp = cq->dev->cqp; + if (cq->cq_uk.cq_id > (cqp->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt - 1)) + return -EINVAL; + + if (cq->ceq_id > (cq->dev->hmc_fpm_misc.max_ceqs - 1)) + return -EINVAL; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) { + return -ENOMEM; + } + + set_64bit_val(wqe, 0, cq->cq_uk.cq_size); + set_64bit_val(wqe, 8, RS_64_1(cq, 1)); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, + cq->shadow_read_threshold)); + set_64bit_val(wqe, 32, cq->virtual_map ? 0 : cq->cq_pa); + set_64bit_val(wqe, 40, cq->shadow_area_pa); + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX, + cq->virtual_map ? cq->first_pm_pbl_idx : 0)); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | + FIELD_PREP(IRDMA_CQPSQ_PASID, cq->pasid) | + FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); + hdr = FLD_LS_64(cq->dev, cq->cq_uk.cq_id, IRDMA_CQPSQ_CQ_CQID) | + FLD_LS_64(cq->dev, cq->ceq_id_valid ? cq->ceq_id : 0, + IRDMA_CQPSQ_CQ_CEQID) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | + FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, check_overflow) | + FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CQID_HIGH, cq->cq_uk.cq_id >> 22) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CEQID_HIGH, + (cq->ceq_id_valid ? cq->ceq_id : 0) >> 10) | + FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, cq->pasid_valid) | + FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | + FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | + FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, + cq->cq_uk.avoid_mem_cflct) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: CQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_cq_destroy - destroy completion q + * @cq: cq struct + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + + cqp = cq->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, cq->cq_uk.cq_size); + set_64bit_val(wqe, 8, RS_64_1(cq, 1)); + set_64bit_val(wqe, 40, cq->shadow_area_pa); + set_64bit_val(wqe, 48, + (cq->virtual_map ? cq->first_pm_pbl_idx : 0)); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_PASID, cq->pasid)); + + hdr = cq->cq_uk.cq_id | + FLD_LS_64(cq->dev, (cq->ceq_id_valid ? cq->ceq_id : 0), + IRDMA_CQPSQ_CQ_CEQID) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | + FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, cq->pbl_chunk_size) | + FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, cq->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, cq->ceq_id_valid) | + FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | + FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, cq->cq_uk.avoid_mem_cflct) | + FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, cq->pasid_valid) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: CQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_cq_resize - set resized cq buffer info + * @cq: resized cq + * @info: resized cq buffer info + */ +void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info) +{ + cq->virtual_map = info->virtual_map; + cq->cq_pa = info->cq_pa; + cq->first_pm_pbl_idx = info->first_pm_pbl_idx; + cq->pbl_chunk_size = info->pbl_chunk_size; + irdma_uk_cq_resize(&cq->cq_uk, info->cq_base, info->cq_size); +} + +/** + * irdma_sc_cq_modify - modify a Completion Queue + * @cq: cq struct + * @info: modification info struct + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag to post to sq + */ +static int irdma_sc_cq_modify(struct irdma_sc_cq *cq, + struct irdma_modify_cq_info *info, u64 scratch, + bool post_sq) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + u32 pble_obj_cnt; + + pble_obj_cnt = cq->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; + if (info->cq_resize && info->virtual_map && + info->first_pm_pbl_idx >= pble_obj_cnt) + return -EINVAL; + + cqp = cq->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, info->cq_size); + set_64bit_val(wqe, 8, RS_64_1(cq, 1)); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, info->shadow_read_threshold)); + set_64bit_val(wqe, 32, info->cq_pa); + set_64bit_val(wqe, 40, cq->shadow_area_pa); + set_64bit_val(wqe, 48, info->first_pm_pbl_idx); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | + FIELD_PREP(IRDMA_CQPSQ_PASID, cq->pasid) | + FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); + + hdr = cq->cq_uk.cq_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_MODIFY_CQ) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CQRESIZE, info->cq_resize) | + FIELD_PREP(IRDMA_CQPSQ_CQ_LPBLSIZE, info->pbl_chunk_size) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, info->check_overflow) | + FIELD_PREP(IRDMA_CQPSQ_CQ_VIRTMAP, info->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, cq->ceqe_mask) | + FIELD_PREP(IRDMA_CQPSQ_TPHEN, cq->tph_en) | + FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, + cq->cq_uk.avoid_mem_cflct) | + FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, cq->pasid_valid) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: CQ_MODIFY WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_check_cqp_progress - check cqp processing progress + * @timeout: timeout info struct + * @dev: sc device struct + */ +void irdma_check_cqp_progress(struct irdma_cqp_timeout *timeout, + struct irdma_sc_dev *dev) +{ + u64 completed_ops = atomic64_read(&dev->cqp->completed_ops); + + if (timeout->compl_cqp_cmds != completed_ops) { + timeout->compl_cqp_cmds = completed_ops; + timeout->count = 0; + } else if (timeout->compl_cqp_cmds != dev->cqp->requested_ops) { + timeout->count++; + } +} + +/** + * irdma_get_cqp_reg_info - get head and tail for cqp using registers + * @cqp: struct for cqp hw + * @val: cqp tail register value + * @tail: wqtail register value + * @error: cqp processing err + */ +static inline void irdma_get_cqp_reg_info(struct irdma_sc_cqp *cqp, u32 *val, + u32 *tail, u32 *error) +{ + *val = readl(cqp->dev->hw_regs[IRDMA_CQPTAIL]); + *tail = FIELD_GET(IRDMA_CQPTAIL_WQTAIL, *val); + *error = FIELD_GET(IRDMA_CQPTAIL_CQP_OP_ERR, *val); +} + +/** + * irdma_sc_cqp_advance_effctv_sq_tail - update CQP SQ tail + * @cqp: CQP HW structure + * + * If there are no pending/deferred completions, simply move tail by 1 + * or catch up with 'true' SQ tail. + * Otherwise, SQ tail cannot move beyond wqe_idx of the first (oldest) pending + * completion on the list. + * SQ tail is advanced on each _final_ completion of any CQP op request. + * + * This function must be called with cqp->ooo_list_lock held. + */ +static void irdma_sc_cqp_advance_effctv_sq_tail(struct irdma_sc_cqp *cqp) +{ + if (!list_empty(&cqp->ooo_pnd)) { + struct irdma_ooo_cqp_op *ooo_op; + + ooo_op = (struct irdma_ooo_cqp_op *) + list_entry(cqp->ooo_pnd.next, + struct irdma_ooo_cqp_op, list_entry); + + /* set tail to the oldest pending CQP op wqe idx */ + IRDMA_RING_SET_TAIL(cqp->sq_ring, ooo_op->wqe_idx); + + return; + } + + /* no pending completions - catch up with the true tail position */ + IRDMA_RING_SET_TAIL(cqp->sq_ring, + IRDMA_RING_CURRENT_TRUE_TAIL(cqp->sq_ring)); +} + +/** + * irdma_sc_cqp_def_cmpl_ae_handler - remove completed requests from pending list + * @dev: sc device struct + * @info: AE entry info + * @first: true if this is the first call to this handler for given AEQE + * @scratch: (out) scratch entry pointer + * @sw_def_info: (in/out) SW ticket value for this AE + * + * In case of AE_DEF_CMPL event, this function should be called in a loop + * until it returns NULL-ptr via scratch. + * For each call, it looks for a matching CQP request on pending list, + * removes it from the list and returns the pointer to the associated scratch + * entry. + * If this is the first call to this function for given AEQE, sw_def_info + * value is not used to find matching requests. Instead, it is populated + * with the value from the first matching cqp_request on the list. + * For subsequent calls, ooo_op->sw_def_info need to match the value passed + * by a caller. + * + * Return: scratch entry pointer for cqp_request to be released or NULL + * if no matching request is found. + */ +void irdma_sc_cqp_def_cmpl_ae_handler(struct irdma_sc_dev *dev, + struct irdma_aeqe_info *info, + bool first, u64 *scratch, + u32 *sw_def_info) +{ + struct irdma_ooo_cqp_op *ooo_op; + unsigned long flags; + + *scratch = 0; + + spin_lock_irqsave(&dev->cqp->ooo_list_lock, flags); + list_for_each_entry(ooo_op, &dev->cqp->ooo_pnd, list_entry) { + if (ooo_op->deferred && + ((first && ooo_op->def_info == info->def_info) || + (!first && ooo_op->sw_def_info == *sw_def_info))) { + *sw_def_info = ooo_op->sw_def_info; + *scratch = ooo_op->scratch; + + list_del(&ooo_op->list_entry); + list_add(&ooo_op->list_entry, &dev->cqp->ooo_avail); + irdma_sc_cqp_advance_effctv_sq_tail(dev->cqp); + atomic64_inc(&dev->cqp->completed_ops); + + break; + } + } + spin_unlock_irqrestore(&dev->cqp->ooo_list_lock, flags); + if (first && !*scratch) + ibdev_dbg(to_ibdev(dev), + "AEQ: deferred completion with unknown ticket: def_info 0x%x\n", + info->def_info); +} + +/** + * irdma_sc_cqp_cleanup_handler - remove requests from pending list + * @dev: sc device struct + * + * This function should be called in a loop from irdma_cleanup_pending_cqp_op. + * For each call, it returns first CQP request on pending list, removes it + * from the list and returns the pointer to the associated scratch entry. + * + * Return: scratch entry pointer for cqp_request to be released or NULL + * if pending list is empty. + */ +u64 irdma_sc_cqp_cleanup_handler(struct irdma_sc_dev *dev) +{ + struct irdma_ooo_cqp_op *ooo_op; + u64 scratch = 0; + + list_for_each_entry(ooo_op, &dev->cqp->ooo_pnd, list_entry) { + scratch = ooo_op->scratch; + + list_del(&ooo_op->list_entry); + list_add(&ooo_op->list_entry, &dev->cqp->ooo_avail); + irdma_sc_cqp_advance_effctv_sq_tail(dev->cqp); + atomic64_inc(&dev->cqp->completed_ops); + + break; + } + + return scratch; +} + +/** + * irdma_cqp_poll_registers - poll cqp registers + * @cqp: struct for cqp hw + * @tail: wqtail register value + * @count: how many times to try for completion + */ +static int irdma_cqp_poll_registers(struct irdma_sc_cqp *cqp, u32 tail, + u32 count) +{ + u32 i = 0; + u32 newtail, error, val; + + while (i++ < count) { + irdma_get_cqp_reg_info(cqp, &val, &newtail, &error); + if (error) { + error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); + ibdev_dbg(to_ibdev(cqp->dev), + "CQP: CQPERRCODES error_code[x%08X]\n", + error); + return -EIO; + } + if (newtail != tail) { + /* SUCCESS */ + if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + IRDMA_RING_MOVE_TRUE_TAIL(cqp->sq_ring); + irdma_sc_cqp_advance_effctv_sq_tail(cqp); + } else { + IRDMA_RING_MOVE_TAIL(cqp->sq_ring); + } + atomic64_inc(&cqp->completed_ops); + return 0; + } + udelay(cqp->dev->hw_attrs.max_sleep_count); + } + + return -ETIMEDOUT; +} + +/** + * irdma_sc_decode_fpm_commit - decode a 64 bit value into count and base + * @dev: sc device struct + * @buf: pointer to commit buffer + * @buf_idx: buffer index + * @obj_info: object info pointer + * @rsrc_idx: indexs of memory resource + */ +static u64 irdma_sc_decode_fpm_commit(struct irdma_sc_dev *dev, __le64 *buf, + u32 buf_idx, struct irdma_hmc_obj_info *obj_info, + u32 rsrc_idx) +{ + u64 temp; + + get_64bit_val(buf, buf_idx, &temp); + + switch (rsrc_idx) { + case IRDMA_HMC_IW_QP: + obj_info[rsrc_idx].cnt = (u32)FIELD_GET(IRDMA_COMMIT_FPM_QPCNT, temp); + break; + case IRDMA_HMC_IW_CQ: + obj_info[rsrc_idx].cnt = (u32)FLD_RS_64(dev, temp, IRDMA_COMMIT_FPM_CQCNT); + break; + case IRDMA_HMC_IW_APBVT_ENTRY: + if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) + obj_info[rsrc_idx].cnt = 1; + else + obj_info[rsrc_idx].cnt = 0; + break; + default: + obj_info[rsrc_idx].cnt = (u32)temp; + break; + } + + obj_info[rsrc_idx].base = (u64)RS_64_1(temp, IRDMA_COMMIT_FPM_BASE_S) * 512; + + return temp; +} + +/** + * irdma_sc_parse_fpm_commit_buf - parse fpm commit buffer + * @dev: pointer to dev struct + * @buf: ptr to fpm commit buffer + * @info: ptr to irdma_hmc_obj_info struct + * @sd: number of SDs for HMC objects + * + * parses fpm commit info and copy base value + * of hmc objects in hmc_info + */ +static void irdma_sc_parse_fpm_commit_buf(struct irdma_sc_dev *dev, __le64 *buf, + struct irdma_hmc_obj_info *info, + u32 *sd) +{ + u64 size; + u32 i; + u64 max_base = 0; + u32 last_hmc_obj = 0; + + irdma_sc_decode_fpm_commit(dev, buf, 0, info, + IRDMA_HMC_IW_QP); + irdma_sc_decode_fpm_commit(dev, buf, 8, info, + IRDMA_HMC_IW_CQ); + irdma_sc_decode_fpm_commit(dev, buf, 16, info, + IRDMA_HMC_IW_SRQ); + irdma_sc_decode_fpm_commit(dev, buf, 24, info, + IRDMA_HMC_IW_HTE); + irdma_sc_decode_fpm_commit(dev, buf, 32, info, + IRDMA_HMC_IW_ARP); + irdma_sc_decode_fpm_commit(dev, buf, 40, info, + IRDMA_HMC_IW_APBVT_ENTRY); + irdma_sc_decode_fpm_commit(dev, buf, 48, info, + IRDMA_HMC_IW_MR); + irdma_sc_decode_fpm_commit(dev, buf, 56, info, + IRDMA_HMC_IW_XF); + irdma_sc_decode_fpm_commit(dev, buf, 64, info, + IRDMA_HMC_IW_XFFL); + irdma_sc_decode_fpm_commit(dev, buf, 72, info, + IRDMA_HMC_IW_Q1); + irdma_sc_decode_fpm_commit(dev, buf, 80, info, + IRDMA_HMC_IW_Q1FL); + irdma_sc_decode_fpm_commit(dev, buf, 88, info, + IRDMA_HMC_IW_TIMER); + irdma_sc_decode_fpm_commit(dev, buf, 112, info, + IRDMA_HMC_IW_PBLE); + /* skipping RSVD. */ + if (dev->hw_attrs.uk_attrs.hw_rev != IRDMA_GEN_1) { + irdma_sc_decode_fpm_commit(dev, buf, 96, info, + IRDMA_HMC_IW_FSIMC); + irdma_sc_decode_fpm_commit(dev, buf, 104, info, + IRDMA_HMC_IW_FSIAV); + irdma_sc_decode_fpm_commit(dev, buf, 128, info, + IRDMA_HMC_IW_RRF); + irdma_sc_decode_fpm_commit(dev, buf, 136, info, + IRDMA_HMC_IW_RRFFL); + irdma_sc_decode_fpm_commit(dev, buf, 144, info, + IRDMA_HMC_IW_HDR); + irdma_sc_decode_fpm_commit(dev, buf, 152, info, + IRDMA_HMC_IW_MD); + if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) { + irdma_sc_decode_fpm_commit(dev, buf, 160, info, + IRDMA_HMC_IW_OOISC); + irdma_sc_decode_fpm_commit(dev, buf, 168, info, + IRDMA_HMC_IW_OOISCFFL); + } + } + + /* searching for the last object in HMC to find the size of the HMC area. */ + for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) { + if (info[i].base > max_base && info[i].cnt) { + max_base = info[i].base; + last_hmc_obj = i; + } + } + + size = info[last_hmc_obj].cnt * info[last_hmc_obj].size + + info[last_hmc_obj].base; + + if (size & 0x1FFFFF) + *sd = (u32)((size >> 21) + 1); /* add 1 for remainder */ + else + *sd = (u32)(size >> 21); + +} + +/** + * irdma_sc_decode_fpm_query() - Decode a 64 bit value into max count and size + * @buf: ptr to fpm query buffer + * @buf_idx: index into buf + * @obj_info: ptr to irdma_hmc_obj_info struct + * @rsrc_idx: resource index into info + * + * Decode a 64 bit value from fpm query buffer into max count and size + */ +static u64 irdma_sc_decode_fpm_query(__le64 *buf, u32 buf_idx, + struct irdma_hmc_obj_info *obj_info, + u32 rsrc_idx) +{ + u64 temp; + u32 size; + + get_64bit_val(buf, buf_idx, &temp); + obj_info[rsrc_idx].max_cnt = (u32)temp; + size = (u32)RS_64_1(temp, 32); + obj_info[rsrc_idx].size = LS_64_1(1, size); + + return temp; +} + +/** + * irdma_sc_parse_fpm_query_buf() - parses fpm query buffer + * @dev: ptr to shared code device + * @buf: ptr to fpm query buffer + * @hmc_info: ptr to irdma_hmc_obj_info struct + * @hmc_fpm_misc: ptr to fpm data + * + * parses fpm query buffer and copy max_cnt and + * size value of hmc objects in hmc_info + */ +static int irdma_sc_parse_fpm_query_buf(struct irdma_sc_dev *dev, __le64 *buf, + struct irdma_hmc_info *hmc_info, + struct irdma_hmc_fpm_misc *hmc_fpm_misc) +{ + struct irdma_hmc_obj_info *obj_info; + u64 temp; + u32 size; + u16 max_pe_sds; + + obj_info = hmc_info->hmc_obj; + + get_64bit_val(buf, 0, &temp); + hmc_info->first_sd_index = (u16)FIELD_GET(IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX, temp); + max_pe_sds = (u16)FIELD_GET(IRDMA_QUERY_FPM_MAX_PE_SDS, temp); + + /* Reduce SD count for unprivleged functions by 1 to account for PBLE + * backing page rounding + */ + if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2 && + (hmc_info->hmc_fn_id >= dev->hw_attrs.first_hw_vf_fpm_id || + !dev->privileged)) + max_pe_sds--; + hmc_fpm_misc->max_sds = max_pe_sds; + hmc_info->sd_table.sd_cnt = max_pe_sds + hmc_info->first_sd_index; + get_64bit_val(buf, 8, &temp); + obj_info[IRDMA_HMC_IW_QP].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_QPS, temp); + size = (u32)RS_64_1(temp, 32); + obj_info[IRDMA_HMC_IW_QP].size = LS_64_1(1, size); + + get_64bit_val(buf, 16, &temp); + obj_info[IRDMA_HMC_IW_CQ].max_cnt = (u32)FIELD_GET(IRDMA_QUERY_FPM_MAX_CQS, temp); + size = (u32)RS_64_1(temp, 32); + obj_info[IRDMA_HMC_IW_CQ].size = LS_64_1(1, size); + + if (dev->hw_attrs.uk_attrs.hw_rev > IRDMA_GEN_3) { + get_64bit_val(buf, 176, &temp); + hmc_fpm_misc->loc_mem_pages = (u32)FIELD_GET(IRDMA_QUERY_FPM_LOC_MEM_PAGES, temp); + if (!hmc_fpm_misc->loc_mem_pages) + return -EINVAL; + } + + irdma_sc_decode_fpm_query(buf, 24, obj_info, IRDMA_HMC_IW_SRQ); + irdma_sc_decode_fpm_query(buf, 32, obj_info, IRDMA_HMC_IW_HTE); + irdma_sc_decode_fpm_query(buf, 40, obj_info, IRDMA_HMC_IW_ARP); + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 0; + obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 0; + } else { + obj_info[IRDMA_HMC_IW_APBVT_ENTRY].size = 8192; + obj_info[IRDMA_HMC_IW_APBVT_ENTRY].max_cnt = 1; + } + + irdma_sc_decode_fpm_query(buf, 48, obj_info, IRDMA_HMC_IW_MR); + irdma_sc_decode_fpm_query(buf, 56, obj_info, IRDMA_HMC_IW_XF); + + get_64bit_val(buf, 64, &temp); + obj_info[IRDMA_HMC_IW_XFFL].max_cnt = (u32)temp; + obj_info[IRDMA_HMC_IW_XFFL].size = 4; + hmc_fpm_misc->xf_block_size = FIELD_GET(IRDMA_QUERY_FPM_XFBLOCKSIZE, temp); + if (!hmc_fpm_misc->xf_block_size) + return -EINVAL; + + irdma_sc_decode_fpm_query(buf, 72, obj_info, IRDMA_HMC_IW_Q1); + get_64bit_val(buf, 80, &temp); + obj_info[IRDMA_HMC_IW_Q1FL].max_cnt = (u32)temp; + obj_info[IRDMA_HMC_IW_Q1FL].size = 4; + + hmc_fpm_misc->q1_block_size = FIELD_GET(IRDMA_QUERY_FPM_Q1BLOCKSIZE, temp); + if (!hmc_fpm_misc->q1_block_size) + return -EINVAL; + + irdma_sc_decode_fpm_query(buf, 88, obj_info, IRDMA_HMC_IW_TIMER); + + get_64bit_val(buf, 112, &temp); + obj_info[IRDMA_HMC_IW_PBLE].max_cnt = (u32)temp; + obj_info[IRDMA_HMC_IW_PBLE].size = 8; + + get_64bit_val(buf, 120, &temp); + hmc_fpm_misc->max_ceqs = FIELD_GET(IRDMA_QUERY_FPM_MAX_CEQS, temp); + hmc_fpm_misc->ht_multiplier = FIELD_GET(IRDMA_QUERY_FPM_HTMULTIPLIER, temp); + hmc_fpm_misc->timer_bucket = FIELD_GET(IRDMA_QUERY_FPM_TIMERBUCKET, temp); + if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + return 0; + irdma_sc_decode_fpm_query(buf, 96, obj_info, IRDMA_HMC_IW_FSIMC); + irdma_sc_decode_fpm_query(buf, 104, obj_info, IRDMA_HMC_IW_FSIAV); + irdma_sc_decode_fpm_query(buf, 128, obj_info, IRDMA_HMC_IW_RRF); + + get_64bit_val(buf, 136, &temp); + obj_info[IRDMA_HMC_IW_RRFFL].max_cnt = (u32)temp; + obj_info[IRDMA_HMC_IW_RRFFL].size = 4; + hmc_fpm_misc->rrf_block_size = FIELD_GET(IRDMA_QUERY_FPM_RRFBLOCKSIZE, temp); + if (!hmc_fpm_misc->rrf_block_size && + obj_info[IRDMA_HMC_IW_RRFFL].max_cnt) + return -EINVAL; + + irdma_sc_decode_fpm_query(buf, 144, obj_info, IRDMA_HMC_IW_HDR); + irdma_sc_decode_fpm_query(buf, 152, obj_info, IRDMA_HMC_IW_MD); + + if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) { + irdma_sc_decode_fpm_query(buf, 160, obj_info, IRDMA_HMC_IW_OOISC); + + get_64bit_val(buf, 168, &temp); + obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt = (u32)temp; + obj_info[IRDMA_HMC_IW_OOISCFFL].size = 4; + hmc_fpm_misc->ooiscf_block_size = FIELD_GET(IRDMA_QUERY_FPM_OOISCFBLOCKSIZE, temp); + if (!hmc_fpm_misc->ooiscf_block_size && + obj_info[IRDMA_HMC_IW_OOISCFFL].max_cnt) + return -EINVAL; + } + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + get_64bit_val(buf, 176, &temp); + hmc_fpm_misc->loc_mem_pages = (u32)FIELD_GET(IRDMA_QUERY_FPM_LOC_MEM_PAGES, temp); + if (!hmc_fpm_misc->loc_mem_pages) + return -EINVAL; + } + + return 0; +} + +/** + * irdma_sc_cqp_init - Initialize buffers for a control Queue Pair + * @cqp: IWARP control queue pair pointer + * @info: IWARP control queue pair init info pointer + * + * Initializes the object and context buffers for a control Queue Pair. + */ +int irdma_sc_cqp_init(struct irdma_sc_cqp *cqp, + struct irdma_cqp_init_info *info) +{ + struct irdma_ooo_cqp_op *ooo_op; + u32 num_ooo_ops; + u8 hw_sq_size; + + if (info->sq_size > IRDMA_CQP_SW_SQSIZE_2048 || + info->sq_size < IRDMA_CQP_SW_SQSIZE_4 || + ((info->sq_size & (info->sq_size - 1)))) + return -EINVAL; + + hw_sq_size = irdma_get_encoded_wqe_size(info->sq_size, + IRDMA_QUEUE_TYPE_CQP); + cqp->size = sizeof(*cqp); + cqp->sq_size = info->sq_size; + cqp->hw_sq_size = hw_sq_size; + cqp->sq_base = info->sq; + cqp->host_ctx = info->host_ctx; + cqp->sq_pa = info->sq_pa; + cqp->host_ctx_pa = info->host_ctx_pa; + cqp->dev = info->dev; + cqp->struct_ver = info->struct_ver; + cqp->hw_maj_ver = info->hw_maj_ver; + cqp->hw_min_ver = info->hw_min_ver; + cqp->scratch_array = info->scratch_array; + cqp->polarity = 0; + cqp->en_datacenter_tcp = info->en_datacenter_tcp; + cqp->ena_vf_count = info->ena_vf_count; + cqp->hmc_profile = info->hmc_profile; + cqp->ceqs_per_vf = info->ceqs_per_vf; + cqp->disable_packed = info->disable_packed; + cqp->rocev2_rto_policy = info->rocev2_rto_policy; + cqp->protocol_used = info->protocol_used; + memcpy(&cqp->dcqcn_params, &info->dcqcn_params, sizeof(cqp->dcqcn_params)); + cqp->en_rem_endpoint_trk = info->en_rem_endpoint_trk; + if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + cqp->ooisc_blksize = info->ooisc_blksize; + cqp->rrsp_blksize = info->rrsp_blksize; + cqp->q1_blksize = info->q1_blksize; + cqp->xmit_blksize = info->xmit_blksize; + cqp->blksizes_valid = info->blksizes_valid; + cqp->ts_shift = info->ts_shift; + cqp->ts_override = info->ts_override; + cqp->en_fine_grained_timers = info->en_fine_grained_timers; + cqp->pe_en_vf_cnt = info->pe_en_vf_cnt; + cqp->ooo_op_array = info->ooo_op_array; + /* initialize the OOO lists */ + INIT_LIST_HEAD(&cqp->ooo_avail); + INIT_LIST_HEAD(&cqp->ooo_pnd); + if (cqp->ooo_op_array) { + /* Populate avail list entries */ + for (num_ooo_ops = 0, ooo_op = info->ooo_op_array; + num_ooo_ops < cqp->sq_size; + num_ooo_ops++, ooo_op++) + list_add(&ooo_op->list_entry, &cqp->ooo_avail); + } + } + info->dev->cqp = cqp; + + IRDMA_RING_INIT(cqp->sq_ring, cqp->sq_size); + cqp->last_def_cmpl_ticket = 0; + cqp->sw_def_cmpl_ticket = 0; + cqp->requested_ops = 0; + atomic64_set(&cqp->completed_ops, 0); + /* for the cqp commands backlog. */ + INIT_LIST_HEAD(&cqp->dev->cqp_cmd_head); + + writel(0, cqp->dev->hw_regs[IRDMA_CQPTAIL]); + if (cqp->dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) { + writel(0, cqp->dev->hw_regs[IRDMA_CQPDB]); + writel(0, cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); + } + + ibdev_dbg(to_ibdev(cqp->dev), + "WQE: sq_size[%04d] hw_sq_size[%04d] sq_base[%p] sq_pa[%pK] cqp[%p] polarity[x%04x]\n", + cqp->sq_size, cqp->hw_sq_size, cqp->sq_base, + (u64 *)(uintptr_t)cqp->sq_pa, cqp, cqp->polarity); + return 0; +} + +/** + * irdma_sc_cqp_create - create cqp during bringup + * @cqp: struct for cqp hw + * @maj_err: If error, major err number + * @min_err: If error, minor err number + */ +int irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, u16 *min_err) +{ + u64 temp; + u8 hw_rev; + u32 cnt = 0, p1, p2, val = 0, err_code; + int ret_code; + + hw_rev = cqp->dev->hw_attrs.uk_attrs.hw_rev; + cqp->sdbuf.size = ALIGN(IRDMA_UPDATE_SD_BUFF_SIZE * cqp->sq_size, + IRDMA_SD_BUF_ALIGNMENT); + cqp->sdbuf.va = dma_alloc_coherent(cqp->dev->hw->device, + cqp->sdbuf.size, &cqp->sdbuf.pa, + GFP_KERNEL); + if (!cqp->sdbuf.va) + return -ENOMEM; + + spin_lock_init(&cqp->dev->cqp_lock); + spin_lock_init(&cqp->ooo_list_lock); + + temp = FIELD_PREP(IRDMA_CQPHC_SQSIZE, cqp->hw_sq_size) | + FIELD_PREP(IRDMA_CQPHC_SVER, cqp->struct_ver) | + FIELD_PREP(IRDMA_CQPHC_DISABLE_PFPDUS, cqp->disable_packed) | + FIELD_PREP(IRDMA_CQPHC_CEQPERVF, cqp->ceqs_per_vf); + if (hw_rev >= IRDMA_GEN_2) { + temp |= FIELD_PREP(IRDMA_CQPHC_ROCEV2_RTO_POLICY, + cqp->rocev2_rto_policy) | + FIELD_PREP(IRDMA_CQPHC_PROTOCOL_USED, + cqp->protocol_used); + } + if (hw_rev >= IRDMA_GEN_3) + temp |= FIELD_PREP(IRDMA_CQPHC_EN_FINE_GRAINED_TIMERS, + cqp->en_fine_grained_timers); + + set_64bit_val(cqp->host_ctx, 0, temp); + set_64bit_val(cqp->host_ctx, 8, cqp->sq_pa); + + temp = FIELD_PREP(IRDMA_CQPHC_ENABLED_VFS, cqp->ena_vf_count) | + FIELD_PREP(IRDMA_CQPHC_HMC_PROFILE, cqp->hmc_profile); + + if (hw_rev >= IRDMA_GEN_2) + temp |= FIELD_PREP(IRDMA_CQPHC_EN_REM_ENDPOINT_TRK, + cqp->en_rem_endpoint_trk); + if (hw_rev >= IRDMA_GEN_3) + temp |= FIELD_PREP(IRDMA_CQPHC_OOISC_BLKSIZE, cqp->ooisc_blksize) | + FIELD_PREP(IRDMA_CQPHC_RRSP_BLKSIZE, cqp->rrsp_blksize) | + FIELD_PREP(IRDMA_CQPHC_Q1_BLKSIZE, cqp->q1_blksize) | + FIELD_PREP(IRDMA_CQPHC_XMIT_BLKSIZE, cqp->xmit_blksize) | + FIELD_PREP(IRDMA_CQPHC_BLKSIZES_VALID, cqp->blksizes_valid) | + FIELD_PREP(IRDMA_CQPHC_TIMESTAMP_OVERRIDE, cqp->ts_override) | + FIELD_PREP(IRDMA_CQPHC_TS_SHIFT, cqp->ts_shift); + set_64bit_val(cqp->host_ctx, 16, temp); + set_64bit_val(cqp->host_ctx, 24, (uintptr_t)cqp); + temp = FIELD_PREP(IRDMA_CQPHC_HW_MAJVER, cqp->hw_maj_ver) | + FIELD_PREP(IRDMA_CQPHC_HW_MINVER, cqp->hw_min_ver); + if (hw_rev >= IRDMA_GEN_2) { + temp |= FIELD_PREP(IRDMA_CQPHC_MIN_RATE, cqp->dcqcn_params.min_rate) | + FIELD_PREP(IRDMA_CQPHC_MIN_DEC_FACTOR, cqp->dcqcn_params.min_dec_factor); + } + set_64bit_val(cqp->host_ctx, 32, temp); + set_64bit_val(cqp->host_ctx, 40, 0); + temp = 0; + if (hw_rev >= IRDMA_GEN_2) { + temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_T, cqp->dcqcn_params.dcqcn_t) | + FIELD_PREP(IRDMA_CQPHC_RAI_FACTOR, cqp->dcqcn_params.rai_factor) | + FIELD_PREP(IRDMA_CQPHC_HAI_FACTOR, cqp->dcqcn_params.hai_factor); + } + set_64bit_val(cqp->host_ctx, 48, temp); + temp = 0; + if (hw_rev >= IRDMA_GEN_2) { + temp |= FIELD_PREP(IRDMA_CQPHC_DCQCN_B, cqp->dcqcn_params.dcqcn_b) | + FIELD_PREP(IRDMA_CQPHC_DCQCN_F, cqp->dcqcn_params.dcqcn_f) | + FIELD_PREP(IRDMA_CQPHC_CC_CFG_VALID, cqp->dcqcn_params.cc_cfg_valid) | + FIELD_PREP(IRDMA_CQPHC_RREDUCE_MPERIOD, cqp->dcqcn_params.rreduce_mperiod); + } + set_64bit_val(cqp->host_ctx, 56, temp); + print_hex_dump_debug("WQE: CQP_HOST_CTX WQE", DUMP_PREFIX_OFFSET, 16, + 8, cqp->host_ctx, IRDMA_CQP_CTX_SIZE * 8, false); + p1 = RS_32_1(cqp->host_ctx_pa, 32); + p2 = (u32)cqp->host_ctx_pa; + + writel(p1, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); + writel(p2, cqp->dev->hw_regs[IRDMA_CCQPLOW]); + + do { + if (cnt++ > cqp->dev->hw_attrs.max_done_count) { + ret_code = -ETIMEDOUT; + goto err; + } + udelay(cqp->dev->hw_attrs.max_sleep_count); + val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); + } while (!val); + + if (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_ERR)) { + ret_code = -EOPNOTSUPP; + goto err; + } + + cqp->process_cqp_sds = irdma_update_sds_noccq; + return 0; + +err: + dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, + cqp->sdbuf.va, cqp->sdbuf.pa); + cqp->sdbuf.va = NULL; + err_code = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); + *min_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MINOR_CODE, err_code); + *maj_err = FIELD_GET(IRDMA_CQPERRCODES_CQP_MAJOR_CODE, err_code); + return ret_code; +} + +/** + * irdma_sc_cqp_post_sq - post of cqp's sq + * @cqp: struct for cqp hw + */ +void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp) +{ + writel(IRDMA_RING_CURRENT_HEAD(cqp->sq_ring), cqp->dev->cqp_db); + + ibdev_dbg(to_ibdev(cqp->dev), + "WQE: CQP SQ head 0x%x tail 0x%x size 0x%x\n", + cqp->sq_ring.head, cqp->sq_ring.tail, cqp->sq_ring.size); +} + +/** + * irdma_sc_cqp_get_next_send_wqe_idx - get next wqe on cqp sq + * and pass back index + * @cqp: CQP HW structure + * @scratch: private data for CQP WQE + * @wqe_idx: WQE index of CQP SQ + */ +__le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch, + u32 *wqe_idx) +{ + __le64 *wqe = NULL; + int ret_code; + + if (IRDMA_RING_FULL_ERR(cqp->sq_ring)) { + ibdev_dbg(to_ibdev(cqp->dev), + "WQE: CQP SQ is full, head 0x%x tail 0x%x size 0x%x\n", + cqp->sq_ring.head, cqp->sq_ring.tail, + cqp->sq_ring.size); + return NULL; + } + IRDMA_ATOMIC_RING_MOVE_HEAD(cqp->sq_ring, *wqe_idx, ret_code); + if (ret_code) + return NULL; + + cqp->requested_ops++; + if (!*wqe_idx) + cqp->polarity = !cqp->polarity; + wqe = cqp->sq_base[*wqe_idx].elem; + cqp->scratch_array[*wqe_idx] = scratch; + + memset(&wqe[0], 0, 24); + memset(&wqe[4], 0, 32); + + return wqe; +} + +/** + * irdma_sc_cqp_destroy - destroy cqp during close + * @cqp: struct for cqp hw + * @free_hwcqp: true for regular cqp destroy; false for reset path + */ +int irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp, bool free_hwcqp) +{ + u32 cnt = 0, val; + int ret_code = 0; + + if (free_hwcqp) { + writel(0, cqp->dev->hw_regs[IRDMA_CCQPHIGH]); + writel(0, cqp->dev->hw_regs[IRDMA_CCQPLOW]); + do { + if (cnt++ > cqp->dev->hw_attrs.max_done_count) { + ret_code = -ETIMEDOUT; + break; + } + udelay(cqp->dev->hw_attrs.max_sleep_count); + val = readl(cqp->dev->hw_regs[IRDMA_CCQPSTATUS]); + } while (FLD_RS_32(cqp->dev, val, IRDMA_CCQPSTATUS_CCQP_DONE)); + } + dma_free_coherent(cqp->dev->hw->device, cqp->sdbuf.size, + cqp->sdbuf.va, cqp->sdbuf.pa); + cqp->sdbuf.va = NULL; + return ret_code; +} + +/** + * irdma_sc_ccq_arm - enable intr for control cq + * @ccq: ccq sc struct + */ +void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq) +{ + unsigned long flags; + u64 temp_val; + u16 sw_cq_sel; + u8 arm_next_se; + u8 arm_seq_num; + + spin_lock_irqsave(&ccq->dev->cqp_lock, flags); + get_64bit_val(ccq->cq_uk.shadow_area, 32, &temp_val); + sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); + arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); + arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); + arm_seq_num++; + temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | + FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | + FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | + FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, 1); + set_64bit_val(ccq->cq_uk.shadow_area, 32, temp_val); + spin_unlock_irqrestore(&ccq->dev->cqp_lock, flags); + + dma_wmb(); /* make sure shadow area is updated before arming */ + + writel(ccq->cq_uk.cq_id, ccq->dev->cq_arm_db); +} + +/** + * irdma_sc_update_cqp_tail_stats - advance CQP SQ tail + * @cqp: CQP sc struct + * @move_true_tail: whether to advance SQ tail + * @move_effctv_tail: whether to advance effective SQ tail and update + * completed cmds stat + */ +static inline void irdma_sc_update_cqp_tail_stats(struct irdma_sc_cqp *cqp, + bool move_true_tail, + bool move_effctv_tail) +{ + unsigned long flags; + + if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + spin_lock_irqsave(&cqp->ooo_list_lock, flags); + + if (move_true_tail) + IRDMA_RING_MOVE_TRUE_TAIL(cqp->sq_ring); + + if (move_effctv_tail) { + irdma_sc_cqp_advance_effctv_sq_tail(cqp); + atomic64_inc(&cqp->completed_ops); + } + + spin_unlock_irqrestore(&cqp->ooo_list_lock, flags); + } else { + IRDMA_RING_MOVE_TAIL(cqp->sq_ring); + atomic64_inc(&cqp->completed_ops); + } +} + +/** + * irdma_sc_process_def_cmpl - process deferred or pending completion + * @cqp: CQP sc struct + * @info: CQP CQE info + * @wqe_idx: CQP WQE descriptor index + * @def_info: deferred op ticket value or out-of-order completion id + * @def_cmpl: true for deferred completion, false for pending (RCA) + */ +static void irdma_sc_process_def_cmpl(struct irdma_sc_cqp *cqp, + struct irdma_ccq_cqe_info *info, + u32 wqe_idx, u32 def_info, bool def_cmpl) +{ + struct irdma_ooo_cqp_op *ooo_op; + unsigned long flags; + + /* Deferred and out-of-order completions share the same list of pending + * completions. Since the list can be also accessed from AE handler, + * it must be protected by a lock. + */ + spin_lock_irqsave(&cqp->ooo_list_lock, flags); + + /* For deferred completions bump up SW completion ticket value. */ + if (def_cmpl) { + cqp->last_def_cmpl_ticket = def_info; + cqp->sw_def_cmpl_ticket++; + } + if (!list_empty(&cqp->ooo_avail)) { + ooo_op = (struct irdma_ooo_cqp_op *) + list_entry(cqp->ooo_avail.next, + struct irdma_ooo_cqp_op, list_entry); + + list_del(&ooo_op->list_entry); + ooo_op->scratch = info->scratch; + ooo_op->def_info = def_info; + ooo_op->sw_def_info = cqp->sw_def_cmpl_ticket; + ooo_op->deferred = def_cmpl; + ooo_op->wqe_idx = wqe_idx; + /* Pending completions must be chronologically ordered, + * so adding at the end of list. + */ + list_add_tail(&ooo_op->list_entry, &cqp->ooo_pnd); + } else { + /* something went wrong - avail list is empty */ + ibdev_dbg(to_ibdev(cqp->dev), + "CQP: DEBUG_FW_OOO ERROR: no space on pending list\n"); + } + spin_unlock_irqrestore(&cqp->ooo_list_lock, flags); + + info->pending = true; +} + +/** + * irdma_sc_process_ooo_cmpl - process out-of-order (final) completion + * @cqp: CQP sc struct + * @info: CQP CQE info + * @def_info: out-of-order completion id + */ +static void irdma_sc_process_ooo_cmpl(struct irdma_sc_cqp *cqp, + struct irdma_ccq_cqe_info *info, + u32 def_info) +{ + struct irdma_ooo_cqp_op *ooo_op_tmp; + struct irdma_ooo_cqp_op *ooo_op; + unsigned long flags; + + info->scratch = 0; + + spin_lock_irqsave(&cqp->ooo_list_lock, flags); + list_for_each_entry_safe(ooo_op, ooo_op_tmp, &cqp->ooo_pnd, + list_entry) { + if (!ooo_op->deferred && ooo_op->def_info == def_info) { + list_del(&ooo_op->list_entry); + info->scratch = ooo_op->scratch; + list_add(&ooo_op->list_entry, &cqp->ooo_avail); + break; + } + } + spin_unlock_irqrestore(&cqp->ooo_list_lock, flags); + + if (!info->scratch) + /* something went wrong - OOO completion with unknown def_info */ + ibdev_dbg(to_ibdev(cqp->dev), + "CQP: DEBUG_FW_OOO out-of-order completion with unknown def_info = 0x%x\n", + def_info); +} + +/** + * irdma_sc_ccq_get_cqe_info - get ccq's cq entry + * @ccq: ccq sc struct + * @info: completion q entry to return + */ +int irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq, + struct irdma_ccq_cqe_info *info) +{ + u32 def_info; + bool def_cmpl = false; + bool pend_cmpl = false; + bool ooo_final_cmpl = false; + u64 qp_ctx, temp, temp1; + __le64 *cqe; + struct irdma_sc_cqp *cqp; + u32 wqe_idx; + u32 error; + u8 polarity; + int ret_code = 0; + unsigned long flags; + + if (ccq->cq_uk.avoid_mem_cflct) + cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(&ccq->cq_uk); + else + cqe = IRDMA_GET_CURRENT_CQ_ELEM(&ccq->cq_uk); + + get_64bit_val(cqe, 24, &temp); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, temp); + if (polarity != ccq->cq_uk.polarity) + return -ENOENT; + + /* Ensure CEQE contents are read after valid bit is checked */ + dma_rmb(); + + get_64bit_val(cqe, 8, &qp_ctx); + cqp = (struct irdma_sc_cqp *)(unsigned long)qp_ctx; + info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, temp); + info->maj_err_code = IRDMA_CQPSQ_MAJ_NO_ERROR; + info->min_err_code = (u16)FIELD_GET(IRDMA_CQ_MINERR, temp); + if (info->error) { + info->maj_err_code = (u16)FIELD_GET(IRDMA_CQ_MAJERR, temp); + error = readl(cqp->dev->hw_regs[IRDMA_CQPERRCODES]); + ibdev_dbg(to_ibdev(cqp->dev), + "CQP: CQPERRCODES error_code[x%08X]\n", error); + } + + wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, temp); + info->scratch = cqp->scratch_array[wqe_idx]; + + get_64bit_val(cqe, 16, &temp1); + info->op_ret_val = (u32)FIELD_GET(IRDMA_CCQ_OPRETVAL, temp1); + if (cqp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + def_cmpl = info->maj_err_code == IRDMA_CQPSQ_MAJ_NO_ERROR && + info->min_err_code == IRDMA_CQPSQ_MIN_DEF_CMPL; + def_info = (u32)FIELD_GET(IRDMA_CCQ_DEFINFO, temp1); + + pend_cmpl = info->maj_err_code == IRDMA_CQPSQ_MAJ_NO_ERROR && + info->min_err_code == IRDMA_CQPSQ_MIN_OOO_CMPL; + + ooo_final_cmpl = (bool)FIELD_GET(IRDMA_OOO_CMPL, temp); + + if (def_cmpl || pend_cmpl || ooo_final_cmpl) { + + if (ooo_final_cmpl) + /* this is final completion for an earlier pending one */ + irdma_sc_process_ooo_cmpl(cqp, info, def_info); + else + irdma_sc_process_def_cmpl(cqp, info, wqe_idx, + def_info, def_cmpl); + } + } + + get_64bit_val(cqp->sq_base[wqe_idx].elem, 24, &temp1); + info->op_code = (u8)FIELD_GET(IRDMA_CQPSQ_OPCODE, temp1); + info->cqp = cqp; + + /* move the head for cq */ + IRDMA_RING_MOVE_HEAD(ccq->cq_uk.cq_ring, ret_code); + if (!IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)) + ccq->cq_uk.polarity ^= 1; + + /* update cq tail in cq shadow memory also */ + IRDMA_RING_MOVE_TAIL(ccq->cq_uk.cq_ring); + set_64bit_val(ccq->cq_uk.shadow_area, 0, + IRDMA_RING_CURRENT_HEAD(ccq->cq_uk.cq_ring)); + + dma_wmb(); /* make sure shadow area is updated before moving tail */ + + spin_lock_irqsave(&cqp->dev->cqp_lock, flags); + irdma_sc_update_cqp_tail_stats(cqp, !ooo_final_cmpl, + !def_cmpl && !pend_cmpl); + spin_unlock_irqrestore(&cqp->dev->cqp_lock, flags); + if (ooo_final_cmpl || def_cmpl) + return ret_code; + + return ret_code; +} + +/** + * irdma_sc_poll_for_cqp_op_done - Waits for last write to complete in CQP SQ + * @cqp: struct for cqp hw + * @op_code: cqp opcode for completion + * @compl_info: completion q entry to return + */ +int irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 op_code, + struct irdma_ccq_cqe_info *compl_info) +{ + struct irdma_ccq_cqe_info info = {}; + struct irdma_sc_cq *ccq; + int ret_code = 0; + u32 cnt = 0; + + ccq = cqp->dev->ccq; + while (1) { + if (cnt++ > 100 * cqp->dev->hw_attrs.max_done_count) + return -ETIMEDOUT; + + if (irdma_sc_ccq_get_cqe_info(ccq, &info)) { + udelay(cqp->dev->hw_attrs.max_sleep_count); + continue; + } + if (info.error && info.op_code != IRDMA_CQP_OP_QUERY_STAG) { + ret_code = -EIO; + break; + } + /* make sure op code matches*/ + if (op_code == info.op_code) + break; + ibdev_dbg(to_ibdev(cqp->dev), + "WQE: opcode mismatch for my op code 0x%x, returned opcode %x\n", + op_code, info.op_code); + } + + if (compl_info) + memcpy(compl_info, &info, sizeof(*compl_info)); + + return ret_code; +} + +/** + * irdma_sc_manage_hmc_pm_func_table - manage of function table + * @cqp: struct for cqp hw + * @scratch: u64 saved to be used during cqp completion + * @info: info for the manage function table operation + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_manage_hmc_pm_func_table(struct irdma_sc_cqp *cqp, + struct irdma_hmc_fcn_info *info, + u64 scratch, bool post_sq) +{ + __le64 *wqe; + u64 hdr; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + hdr = FIELD_PREP(IRDMA_CQPSQ_MHMC_VFIDX, info->vf_id) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, + IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE) | + FIELD_PREP(IRDMA_CQPSQ_MHMC_FREEPMFN, info->free_fcn) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: MANAGE_HMC_PM_FUNC_TABLE WQE", + DUMP_PREFIX_OFFSET, 16, 8, wqe, + IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_commit_fpm_val_done - wait for cqp eqe completion + * for fpm commit + * @cqp: struct for cqp hw + */ +static int irdma_sc_commit_fpm_val_done(struct irdma_sc_cqp *cqp) +{ + return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_COMMIT_FPM_VAL, + NULL); +} + +/** + * irdma_sc_commit_fpm_val - cqp wqe for commit fpm values + * @cqp: struct for cqp hw + * @scratch: u64 saved to be used during cqp completion + * @hmc_fn_id: hmc function id + * @commit_fpm_mem: Memory for fpm values + * @post_sq: flag for cqp db to ring + * @wait_type: poll ccq or cqp registers for cqp completion + */ +static int irdma_sc_commit_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, + u16 hmc_fn_id, + struct irdma_dma_mem *commit_fpm_mem, + bool post_sq, u8 wait_type) +{ + __le64 *wqe; + u64 hdr; + u32 tail, val, error; + int ret_code = 0; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, hmc_fn_id); + set_64bit_val(wqe, 32, commit_fpm_mem->pa); + + hdr = FIELD_PREP(IRDMA_CQPSQ_BUFSIZE, IRDMA_COMMIT_FPM_BUF_SIZE) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_COMMIT_FPM_VAL) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: COMMIT_FPM_VAL WQE", DUMP_PREFIX_OFFSET, + 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_get_cqp_reg_info(cqp, &val, &tail, &error); + + if (post_sq) { + irdma_sc_cqp_post_sq(cqp); + if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) + ret_code = irdma_cqp_poll_registers(cqp, tail, + cqp->dev->hw_attrs.max_done_count); + else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) + ret_code = irdma_sc_commit_fpm_val_done(cqp); + } + + return ret_code; +} + +/** + * irdma_sc_query_fpm_val_done - poll for cqp wqe completion for + * query fpm + * @cqp: struct for cqp hw + */ +static int irdma_sc_query_fpm_val_done(struct irdma_sc_cqp *cqp) +{ + return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_QUERY_FPM_VAL, + NULL); +} + +/** + * irdma_sc_query_fpm_val - cqp wqe query fpm values + * @cqp: struct for cqp hw + * @scratch: u64 saved to be used during cqp completion + * @hmc_fn_id: hmc function id + * @query_fpm_mem: memory for return fpm values + * @post_sq: flag for cqp db to ring + * @wait_type: poll ccq or cqp registers for cqp completion + */ +static int irdma_sc_query_fpm_val(struct irdma_sc_cqp *cqp, u64 scratch, + u16 hmc_fn_id, + struct irdma_dma_mem *query_fpm_mem, + bool post_sq, u8 wait_type) +{ + __le64 *wqe; + u64 hdr; + u32 tail, val, error; + int ret_code = 0; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, hmc_fn_id); + set_64bit_val(wqe, 32, query_fpm_mem->pa); + + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_QUERY_FPM_VAL) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: QUERY_FPM WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_get_cqp_reg_info(cqp, &val, &tail, &error); + + if (post_sq) { + irdma_sc_cqp_post_sq(cqp); + if (wait_type == IRDMA_CQP_WAIT_POLL_REGS) + ret_code = irdma_cqp_poll_registers(cqp, tail, + cqp->dev->hw_attrs.max_done_count); + else if (wait_type == IRDMA_CQP_WAIT_POLL_CQ) + ret_code = irdma_sc_query_fpm_val_done(cqp); + } + + return ret_code; +} + +/** + * irdma_sc_ceq_init - initialize ceq + * @ceq: ceq sc structure + * @info: ceq initialization info + */ +int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq, + struct irdma_ceq_init_info *info) +{ + u32 pble_obj_cnt; + + if (info->elem_cnt < info->dev->hw_attrs.min_hw_ceq_size || + info->elem_cnt > info->dev->hw_attrs.max_hw_ceq_size) + return -EINVAL; + + if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1)) + return -EINVAL; + pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; + + if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) + return -EINVAL; + + ceq->size = sizeof(*ceq); + ceq->ceqe_base = (struct irdma_ceqe *)info->ceqe_base; + ceq->ceq_id = info->ceq_id; + ceq->dev = info->dev; + ceq->elem_cnt = info->elem_cnt; + ceq->ceq_elem_pa = info->ceqe_pa; + ceq->virtual_map = info->virtual_map; + ceq->itr_no_expire = info->itr_no_expire; + ceq->pbl_chunk_size = (ceq->virtual_map ? info->pbl_chunk_size : 0); + ceq->first_pm_pbl_idx = (ceq->virtual_map ? info->first_pm_pbl_idx : 0); + ceq->pbl_list = (ceq->virtual_map ? info->pbl_list : NULL); + ceq->tph_en = info->tph_en; + ceq->tph_val = info->tph_val; + ceq->vsi = info->vsi; + ceq->polarity = 1; + IRDMA_RING_INIT(ceq->ceq_ring, ceq->elem_cnt); + ceq->dev->ceq[info->ceq_id] = ceq; + + return 0; +} + +/** + * irdma_sc_ceq_create - create ceq wqe + * @ceq: ceq sc structure + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_ceq_create(struct irdma_sc_ceq *ceq, u64 scratch, + bool post_sq) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + + cqp = ceq->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + set_64bit_val(wqe, 16, ceq->elem_cnt); + set_64bit_val(wqe, 32, + (ceq->virtual_map ? 0 : ceq->ceq_elem_pa)); + set_64bit_val(wqe, 48, + (ceq->virtual_map ? ceq->first_pm_pbl_idx : 0)); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_TPHVAL, ceq->tph_val) | + FIELD_PREP(IRDMA_CQPSQ_PASID, ceq->pasid) | + FIELD_PREP(IRDMA_CQPSQ_VSIIDX, ceq->vsi->vsi_idx)); + hdr = FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID, ceq->ceq_id) | + FIELD_PREP(IRDMA_CQPSQ_CEQ_CEQID_HIGH, ceq->ceq_id >> 10) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CEQ) | + FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | + FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_CEQ_ITRNOEXPIRE, ceq->itr_no_expire) | + FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | + FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, ceq->pasid_valid) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: CEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_cceq_create_done - poll for control ceq wqe to complete + * @ceq: ceq sc structure + */ +static int irdma_sc_cceq_create_done(struct irdma_sc_ceq *ceq) +{ + struct irdma_sc_cqp *cqp; + + cqp = ceq->dev->cqp; + return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CEQ, + NULL); +} + +/** + * irdma_sc_cceq_destroy_done - poll for destroy cceq to complete + * @ceq: ceq sc structure + */ +int irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq) +{ + struct irdma_sc_cqp *cqp; + + cqp = ceq->dev->cqp; + cqp->process_cqp_sds = irdma_update_sds_noccq; + + return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_DESTROY_CEQ, + NULL); +} + +/** + * irdma_sc_cceq_create - create cceq + * @ceq: ceq sc structure + */ +int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq) +{ + int ret_code; + struct irdma_sc_dev *dev = ceq->dev; + + dev->ccq->vsi = ceq->vsi; + ret_code = irdma_sc_ceq_create(ceq, 0, true); + if (!ret_code) + return irdma_sc_cceq_create_done(ceq); + + return ret_code; +} + +/** + * irdma_sc_ceq_destroy - destroy ceq + * @ceq: ceq sc structure + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + + cqp = ceq->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, ceq->elem_cnt); + set_64bit_val(wqe, 48, ceq->first_pm_pbl_idx); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_PASID, ceq->pasid)); + hdr = ceq->ceq_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CEQ) | + FIELD_PREP(IRDMA_CQPSQ_CEQ_LPBLSIZE, ceq->pbl_chunk_size) | + FIELD_PREP(IRDMA_CQPSQ_CEQ_VMAP, ceq->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_TPHEN, ceq->tph_en) | + FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, ceq->pasid_valid) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: CEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_process_ceq - process ceq + * @dev: sc device struct + * @ceq: ceq sc structure + * + * It is expected caller serializes this function with cleanup_ceqes() + * because these functions manipulate the same ceq + */ +void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq) +{ + u64 temp; + __le64 *ceqe; + struct irdma_sc_cq *cq = NULL; + struct irdma_sc_cq *temp_cq; + u8 polarity; + u32 cq_idx; + + do { + cq_idx = 0; + ceqe = IRDMA_GET_CURRENT_CEQ_ELEM(ceq); + get_64bit_val(ceqe, 0, &temp); + polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); + if (polarity != ceq->polarity) + return NULL; + + temp_cq = (struct irdma_sc_cq *)(unsigned long)LS_64_1(temp, 1); + if (!temp_cq) { + cq_idx = IRDMA_INVALID_CQ_IDX; + IRDMA_RING_MOVE_TAIL(ceq->ceq_ring); + + if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring)) + ceq->polarity ^= 1; + continue; + } + + cq = temp_cq; + IRDMA_RING_MOVE_TAIL(ceq->ceq_ring); + if (!IRDMA_RING_CURRENT_TAIL(ceq->ceq_ring)) + ceq->polarity ^= 1; + } while (cq_idx == IRDMA_INVALID_CQ_IDX); + + if (cq) + irdma_sc_cq_ack(cq); + return cq; +} + +/** + * irdma_sc_cleanup_ceqes - clear the valid ceqes ctx matching the cq + * @cq: cq for which the ceqes need to be cleaned up + * @ceq: ceq ptr + * + * The function is called after the cq is destroyed to cleanup + * its pending ceqe entries. It is expected caller serializes this + * function with process_ceq() in interrupt context. + */ +void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq) +{ + struct irdma_sc_cq *next_cq; + u8 ceq_polarity = ceq->polarity; + __le64 *ceqe; + u8 polarity; + u64 temp; + int next; + u32 i; + + next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, 0); + + for (i = 1; i <= IRDMA_RING_SIZE(*ceq); i++) { + ceqe = IRDMA_GET_CEQ_ELEM_AT_POS(ceq, next); + + get_64bit_val(ceqe, 0, &temp); + polarity = (u8)FIELD_GET(IRDMA_CEQE_VALID, temp); + if (polarity != ceq_polarity) + return; + + next_cq = (struct irdma_sc_cq *)(unsigned long)LS_64_1(temp, 1); + if (cq == next_cq) + set_64bit_val(ceqe, 0, temp & IRDMA_CEQE_VALID); + + next = IRDMA_RING_GET_NEXT_TAIL(ceq->ceq_ring, i); + if (!next) + ceq_polarity ^= 1; + } +} + +/** + * irdma_sc_aeq_init - initialize aeq + * @aeq: aeq structure ptr + * @info: aeq initialization info + */ +int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq, + struct irdma_aeq_init_info *info) +{ + u32 pble_obj_cnt; + + if (info->elem_cnt < info->dev->hw_attrs.min_hw_aeq_size || + info->elem_cnt > info->dev->hw_attrs.max_hw_aeq_size) + return -EINVAL; + + pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; + + if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) + return -EINVAL; + + aeq->size = sizeof(*aeq); + aeq->polarity = 1; + aeq->aeqe_base = (struct irdma_sc_aeqe *)info->aeqe_base; + aeq->dev = info->dev; + aeq->elem_cnt = info->elem_cnt; + aeq->aeq_elem_pa = info->aeq_elem_pa; + IRDMA_RING_INIT(aeq->aeq_ring, aeq->elem_cnt); + aeq->virtual_map = info->virtual_map; + aeq->pbl_list = (aeq->virtual_map ? info->pbl_list : NULL); + aeq->pbl_chunk_size = (aeq->virtual_map ? info->pbl_chunk_size : 0); + aeq->first_pm_pbl_idx = (aeq->virtual_map ? info->first_pm_pbl_idx : 0); + aeq->msix_idx = info->msix_idx; + info->dev->aeq = aeq; + + return 0; +} + +/** + * irdma_sc_aeq_create - create aeq + * @aeq: aeq structure ptr + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +static int irdma_sc_aeq_create(struct irdma_sc_aeq *aeq, u64 scratch, + bool post_sq) +{ + __le64 *wqe; + struct irdma_sc_cqp *cqp; + u64 hdr; + + cqp = aeq->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + set_64bit_val(wqe, 16, aeq->elem_cnt); + set_64bit_val(wqe, 32, + (aeq->virtual_map ? 0 : aeq->aeq_elem_pa)); + set_64bit_val(wqe, 48, + (aeq->virtual_map ? aeq->first_pm_pbl_idx : 0)); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_PASID, aeq->pasid)); + + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_AEQ) | + FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | + FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, aeq->pasid_valid) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: AEQ_CREATE WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_sc_aeq_destroy - destroy aeq during close + * @aeq: aeq structure ptr + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch, bool post_sq) +{ + __le64 *wqe; + struct irdma_sc_cqp *cqp; + struct irdma_sc_dev *dev; + u64 hdr; + + dev = aeq->dev; + if (dev->privileged) + writel(0, dev->hw_regs[IRDMA_PFINT_AEQCTL]); + + cqp = dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + set_64bit_val(wqe, 16, aeq->elem_cnt); + set_64bit_val(wqe, 48, aeq->first_pm_pbl_idx); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_PASID, aeq->pasid)); + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_AEQ) | + FIELD_PREP(IRDMA_CQPSQ_AEQ_LPBLSIZE, aeq->pbl_chunk_size) | + FIELD_PREP(IRDMA_CQPSQ_AEQ_VMAP, aeq->virtual_map) | + FIELD_PREP(IRDMA_CQPSQ_PASID_VALID, aeq->pasid_valid) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: AEQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + if (post_sq) + irdma_sc_cqp_post_sq(cqp); + return 0; +} + +/** + * irdma_sc_get_next_aeqe - get next aeq entry + * @aeq: aeq structure ptr + * @info: aeqe info to be returned + */ +int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, + struct irdma_aeqe_info *info) +{ + u64 temp, compl_ctx; + __le64 *aeqe; + u8 ae_src; + u8 polarity; + + aeqe = IRDMA_GET_CURRENT_AEQ_ELEM(aeq); + get_64bit_val(aeqe, 8, &temp); + polarity = (u8)FIELD_GET(IRDMA_AEQE_VALID, temp); + + if (aeq->polarity != polarity) + return -ENOENT; + + /* Ensure AEQE contents are read after valid bit is checked */ + dma_rmb(); + + get_64bit_val(aeqe, 0, &compl_ctx); + + print_hex_dump_debug("WQE: AEQ_ENTRY WQE", DUMP_PREFIX_OFFSET, 16, 8, + aeqe, 16, false); + + if (aeq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC_GEN_3, temp); + info->wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX_GEN_3, temp); + info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_GEN_3, temp); + info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE_GEN_3, temp); + info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE_GEN_3, compl_ctx); + info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE_GEN_3, temp); + info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA_GEN_3, compl_ctx); + info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW_GEN_3, temp); + info->compl_ctx = FIELD_GET(IRDMA_AEQE_CMPL_CTXT, compl_ctx); + compl_ctx = FIELD_GET(IRDMA_AEQE_CMPL_CTXT, compl_ctx) << IRDMA_AEQE_CMPL_CTXT_S; + } else { + ae_src = (u8)FIELD_GET(IRDMA_AEQE_AESRC, temp); + info->wqe_idx = (u16)FIELD_GET(IRDMA_AEQE_WQDESCIDX, temp); + info->qp_cq_id = (u32)FIELD_GET(IRDMA_AEQE_QPCQID_LOW, temp) | + ((u32)FIELD_GET(IRDMA_AEQE_QPCQID_HI, temp) << 18); + info->ae_id = (u16)FIELD_GET(IRDMA_AEQE_AECODE, temp); + info->tcp_state = (u8)FIELD_GET(IRDMA_AEQE_TCPSTATE, temp); + info->iwarp_state = (u8)FIELD_GET(IRDMA_AEQE_IWSTATE, temp); + info->q2_data_written = (u8)FIELD_GET(IRDMA_AEQE_Q2DATA, temp); + info->aeqe_overflow = (bool)FIELD_GET(IRDMA_AEQE_OVERFLOW, + temp); + } + + info->ae_src = ae_src; + switch (info->ae_id) { + case IRDMA_AE_SRQ_LIMIT: + info->srq = true; + /* Bits [63:6] of CMPL_CTX are treated as SRQ_ID. */ + info->compl_ctx = compl_ctx >> IRDMA_AEQE_CMPL_CTXT_S; + ae_src = IRDMA_AE_SOURCE_RSVD; + break; + case IRDMA_AE_PRIV_OPERATION_DENIED: + case IRDMA_AE_AMP_INVALIDATE_TYPE1_MW: + case IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW: + case IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG: + case IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH: + case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: + case IRDMA_AE_UDA_XMIT_BAD_PD: + case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: + case IRDMA_AE_BAD_CLOSE: + case IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO: + case IRDMA_AE_STAG_ZERO_INVALID: + case IRDMA_AE_IB_RREQ_AND_Q1_FULL: + case IRDMA_AE_IB_INVALID_REQUEST: + case IRDMA_AE_WQE_UNEXPECTED_OPCODE: + case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: + case IRDMA_AE_IB_REMOTE_OP_ERROR: + case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: + case IRDMA_AE_DDP_UBE_INVALID_MO: + case IRDMA_AE_DDP_UBE_INVALID_QN: + case IRDMA_AE_DDP_NO_L_BIT: + case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: + case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: + case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: + case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: + case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: + case IRDMA_AE_ROCE_REQ_LENGTH_ERROR: + case IRDMA_AE_INVALID_ARP_ENTRY: + case IRDMA_AE_INVALID_TCP_OPTION_RCVD: + case IRDMA_AE_STALE_ARP_ENTRY: + case IRDMA_AE_INVALID_AH_ENTRY: + case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: + case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: + case IRDMA_AE_LLP_TOO_MANY_RETRIES: + case IRDMA_AE_LCE_QP_CATASTROPHIC: + case IRDMA_AE_LLP_TOO_MANY_RNRS: + case IRDMA_AE_REMOTE_QP_CATASTROPHIC: + case IRDMA_AE_LOCAL_QP_CATASTROPHIC: + case IRDMA_AE_RCE_QP_CATASTROPHIC: + case IRDMA_AE_LLP_DOUBT_REACHABILITY: + case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: + case IRDMA_AE_RESET_SENT: + case IRDMA_AE_TERMINATE_SENT: + case IRDMA_AE_RESET_NOT_SENT: + case IRDMA_AE_QP_SUSPEND_COMPLETE: + case IRDMA_AE_UDA_L4LEN_INVALID: + info->qp = true; + info->compl_ctx = compl_ctx; + break; + case IRDMA_AE_LCE_CQ_CATASTROPHIC: + info->cq = true; + info->compl_ctx = LS_64_1(compl_ctx, 1); + ae_src = IRDMA_AE_SOURCE_RSVD; + break; + case IRDMA_AE_CQP_DEFERRED_COMPLETE: + info->def_info = info->wqe_idx; + ae_src = IRDMA_AE_SOURCE_RSVD; + break; + case IRDMA_AE_ROCE_EMPTY_MCG: + case IRDMA_AE_ROCE_BAD_MC_IP_ADDR: + case IRDMA_AE_ROCE_BAD_MC_QPID: + case IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH: + fallthrough; + case IRDMA_AE_LLP_CONNECTION_RESET: + case IRDMA_AE_LLP_SYN_RECEIVED: + case IRDMA_AE_LLP_FIN_RECEIVED: + case IRDMA_AE_LLP_CLOSE_COMPLETE: + case IRDMA_AE_LLP_TERMINATE_RECEIVED: + case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: + ae_src = IRDMA_AE_SOURCE_RSVD; + info->qp = true; + info->compl_ctx = compl_ctx; + break; + case IRDMA_AE_RESOURCE_EXHAUSTION: + /* ae_src contains the exhausted resource with a unique decoding. + * Set RSVD here to prevent matching with a CQ or QP. + */ + ae_src = IRDMA_AE_SOURCE_RSVD; + break; + default: + break; + } + + switch (ae_src) { + case IRDMA_AE_SOURCE_RQ: + case IRDMA_AE_SOURCE_RQ_0011: + info->qp = true; + info->rq = true; + info->compl_ctx = compl_ctx; + info->err_rq_idx_valid = true; + break; + case IRDMA_AE_SOURCE_CQ: + case IRDMA_AE_SOURCE_CQ_0110: + case IRDMA_AE_SOURCE_CQ_1010: + case IRDMA_AE_SOURCE_CQ_1110: + info->cq = true; + info->compl_ctx = LS_64_1(compl_ctx, 1); + break; + case IRDMA_AE_SOURCE_SQ: + case IRDMA_AE_SOURCE_SQ_0111: + info->qp = true; + info->sq = true; + info->compl_ctx = compl_ctx; + break; + case IRDMA_AE_SOURCE_IN_WR: + info->qp = true; + if (aeq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) + info->err_rq_idx_valid = true; + info->compl_ctx = compl_ctx; + info->in_rdrsp_wr = true; + break; + case IRDMA_AE_SOURCE_IN_RR: + info->qp = true; + if (aeq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + info->sq = true; + info->err_rq_idx_valid = true; + } + info->compl_ctx = compl_ctx; + info->in_rdrsp_wr = true; + break; + case IRDMA_AE_SOURCE_OUT_RR: + case IRDMA_AE_SOURCE_OUT_RR_1111: + info->qp = true; + info->compl_ctx = compl_ctx; + info->out_rdrsp = true; + break; + case IRDMA_AE_SOURCE_RSVD: + default: + break; + } + + IRDMA_RING_MOVE_TAIL(aeq->aeq_ring); + if (!IRDMA_RING_CURRENT_TAIL(aeq->aeq_ring)) + aeq->polarity ^= 1; + + return 0; +} + +/** + * irdma_sc_repost_aeq_entries - repost completed aeq entries + * @dev: sc device struct + * @count: allocate count + */ +void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count) +{ + writel(count, dev->aeq_alloc_db); + +} + +/** + * irdma_sc_ccq_init - initialize control cq + * @cq: sc's cq ctruct + * @info: info for control cq initialization + */ +int irdma_sc_ccq_init(struct irdma_sc_cq *cq, struct irdma_ccq_init_info *info) +{ + u32 pble_obj_cnt; + + if (info->num_elem < info->dev->hw_attrs.uk_attrs.min_hw_cq_size || + info->num_elem > info->dev->hw_attrs.uk_attrs.max_hw_cq_size) + return -EINVAL; + + if (info->ceq_id > (info->dev->hmc_fpm_misc.max_ceqs - 1)) + return -EINVAL; + + pble_obj_cnt = info->dev->hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt; + + if (info->virtual_map && info->first_pm_pbl_idx >= pble_obj_cnt) + return -EINVAL; + + cq->cq_pa = info->cq_pa; + cq->cq_uk.cq_base = info->cq_base; + cq->shadow_area_pa = info->shadow_area_pa; + cq->cq_uk.shadow_area = info->shadow_area; + cq->shadow_read_threshold = info->shadow_read_threshold; + cq->dev = info->dev; + cq->ceq_id = info->ceq_id; + cq->cq_uk.cq_size = info->num_elem; + cq->cq_type = IRDMA_CQ_TYPE_CQP; + cq->ceqe_mask = info->ceqe_mask; + IRDMA_RING_INIT(cq->cq_uk.cq_ring, info->num_elem); + cq->cq_uk.cq_id = 0; /* control cq is id 0 always */ + cq->ceq_id_valid = info->ceq_id_valid; + cq->tph_en = info->tph_en; + cq->tph_val = info->tph_val; + cq->cq_uk.avoid_mem_cflct = info->avoid_mem_cflct; + cq->pbl_list = info->pbl_list; + cq->virtual_map = info->virtual_map; + cq->pbl_chunk_size = info->pbl_chunk_size; + cq->first_pm_pbl_idx = info->first_pm_pbl_idx; + cq->cq_uk.polarity = true; + cq->vsi = info->vsi; + cq->cq_uk.cq_ack_db = cq->dev->cq_ack_db; + + /* Only applicable to CQs other than CCQ so initialize to zero */ + cq->cq_uk.cqe_alloc_db = NULL; + + info->dev->ccq = cq; + return 0; +} + +/** + * irdma_sc_ccq_create_done - poll cqp for ccq create + * @ccq: ccq sc struct + */ +static inline int irdma_sc_ccq_create_done(struct irdma_sc_cq *ccq) +{ + struct irdma_sc_cqp *cqp; + + cqp = ccq->dev->cqp; + + return irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_CREATE_CQ, NULL); +} + +/** + * irdma_sc_ccq_create - create control cq + * @ccq: ccq sc struct + * @scratch: u64 saved to be used during cqp completion + * @check_overflow: overlow flag for ccq + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch, + bool check_overflow, bool post_sq) +{ + int ret_code; + + ret_code = irdma_sc_cq_create(ccq, scratch, check_overflow, post_sq); + if (ret_code) + return ret_code; + + if (post_sq) { + ret_code = irdma_sc_ccq_create_done(ccq); + if (ret_code) + return ret_code; + } + ccq->dev->cqp->process_cqp_sds = irdma_cqp_sds_cmd; + + return 0; +} + +/** + * irdma_sc_ccq_destroy - destroy ccq during close + * @ccq: ccq sc struct + * @scratch: u64 saved to be used during cqp completion + * @post_sq: flag for cqp db to ring + */ +int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + int ret_code = 0; + u32 tail, val, error; + + cqp = ccq->dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, ccq->cq_uk.cq_size); + set_64bit_val(wqe, 8, RS_64_1(ccq, 1)); + set_64bit_val(wqe, 40, ccq->shadow_area_pa); + + hdr = ccq->cq_uk.cq_id | + FLD_LS_64(ccq->dev, (ccq->ceq_id_valid ? ccq->ceq_id : 0), + IRDMA_CQPSQ_CQ_CEQID) | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_DESTROY_CQ) | + FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, ccq->ceqe_mask) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, ccq->ceq_id_valid) | + FIELD_PREP(IRDMA_CQPSQ_TPHEN, ccq->tph_en) | + FIELD_PREP(IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT, ccq->cq_uk.avoid_mem_cflct) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: CCQ_DESTROY WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_get_cqp_reg_info(cqp, &val, &tail, &error); + + if (post_sq) { + irdma_sc_cqp_post_sq(cqp); + ret_code = irdma_cqp_poll_registers(cqp, tail, + cqp->dev->hw_attrs.max_done_count); + } + + cqp->process_cqp_sds = irdma_update_sds_noccq; + + return ret_code; +} + +/** + * irdma_sc_init_iw_hmc() - queries fpm values using cqp and populates hmc_info + * @dev : ptr to irdma_dev struct + * @hmc_fn_id: hmc function id + */ +int irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, u16 hmc_fn_id) +{ + struct irdma_hmc_info *hmc_info; + struct irdma_hmc_fpm_misc *hmc_fpm_misc; + struct irdma_dma_mem query_fpm_mem; + struct irdma_virt_mem virt_mem; + struct irdma_vchnl_dev *vc_dev = NULL; + bool poll_registers = true; + u16 iw_vf_idx; + u32 mem_size; + int ret_code = 0; + u8 wait_type; + + if ((dev->privileged && hmc_fn_id > dev->hw_attrs.max_hw_vf_fpm_id) || + (dev->hmc_fn_id != hmc_fn_id && + hmc_fn_id < dev->hw_attrs.first_hw_vf_fpm_id)) + return -EINVAL; + + ibdev_dbg(to_ibdev(dev), "HMC: hmc_fn_id %u, dev->hmc_fn_id %u\n", + hmc_fn_id, dev->hmc_fn_id); + if (hmc_fn_id == dev->hmc_fn_id) { + hmc_info = dev->hmc_info; + hmc_fpm_misc = &dev->hmc_fpm_misc; + query_fpm_mem.pa = dev->fpm_query_buf_pa; + query_fpm_mem.va = dev->fpm_query_buf; + } else { + vc_dev = irdma_vchnl_dev_from_fpm(dev, hmc_fn_id); + if (!vc_dev) + return -EINVAL; + + hmc_info = &vc_dev->hmc_info; + hmc_fpm_misc = &vc_dev->hmc_fpm_misc; + iw_vf_idx = vc_dev->iw_vf_idx; + ibdev_dbg(to_ibdev(dev), + "HMC: vc_dev %p, hmc_info %p, hmc_obj %p\n", vc_dev, + hmc_info, hmc_info->hmc_obj); + if (!vc_dev->fpm_query_buf) { + if (!dev->vf_fpm_query_buf[iw_vf_idx].va) { + ret_code = irdma_alloc_query_fpm_buf( + dev, &dev->vf_fpm_query_buf[iw_vf_idx]); + if (ret_code) + return ret_code; + } + vc_dev->fpm_query_buf = + dev->vf_fpm_query_buf[iw_vf_idx].va; + vc_dev->fpm_query_buf_pa = + dev->vf_fpm_query_buf[iw_vf_idx].pa; + } + query_fpm_mem.pa = vc_dev->fpm_query_buf_pa; + query_fpm_mem.va = vc_dev->fpm_query_buf; + poll_registers = false; + } + hmc_info->hmc_fn_id = hmc_fn_id; + + if (hmc_fn_id != dev->hmc_fn_id) { + ret_code = irdma_cqp_query_fpm_val_cmd(dev, &query_fpm_mem, + hmc_fn_id); + } else { + wait_type = poll_registers ? (u8)IRDMA_CQP_WAIT_POLL_REGS : + (u8)IRDMA_CQP_WAIT_POLL_CQ; + + ret_code = irdma_sc_query_fpm_val(dev->cqp, 0, + hmc_info->hmc_fn_id, + &query_fpm_mem, true, + wait_type); + } + if (ret_code) + return ret_code; + + /* parse the fpm_query_buf and fill hmc obj info */ + ret_code = irdma_sc_parse_fpm_query_buf(dev, query_fpm_mem.va, hmc_info, + hmc_fpm_misc); + + print_hex_dump_debug("HMC: QUERY FPM BUFFER", DUMP_PREFIX_OFFSET, 16, + 8, query_fpm_mem.va, IRDMA_QUERY_FPM_BUF_SIZE, + false); + + if (ret_code) + return ret_code; + + if (hmc_fn_id != dev->hmc_fn_id) { + irdma_cqp_commit_fpm_val_cmd(dev, &query_fpm_mem, hmc_fn_id); + /* parse the fpm_commit_buf and fill hmc obj info */ + irdma_sc_parse_fpm_commit_buf(dev, query_fpm_mem.va, + hmc_info->hmc_obj, + &hmc_info->sd_table.sd_cnt); + + print_hex_dump_debug("HMC: COMMIT FPM BUFFER", + DUMP_PREFIX_OFFSET, 16, 8, + query_fpm_mem.va, + IRDMA_COMMIT_FPM_BUF_SIZE, false); + mem_size = + sizeof(struct irdma_hmc_sd_entry) * + (hmc_info->sd_table.sd_cnt + hmc_info->first_sd_index); + virt_mem.size = mem_size; + virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL); + if (!virt_mem.va) + return -ENOMEM; + + hmc_info->sd_table.sd_entry = virt_mem.va; + } + return ret_code; +} + +/** + * irdma_set_loc_mem() - set a local memory bit field + * @buf: ptr to a buffer where local memory gets enabled + */ +static void irdma_set_loc_mem(__le64 *buf) +{ + u64 loc_mem_en = BIT_ULL(ENABLE_LOC_MEM); + u32 offset; + u64 temp; + + for (offset = 0; offset < IRDMA_COMMIT_FPM_BUF_SIZE; + offset += sizeof(__le64)) { + if (offset == IRDMA_PBLE_COMMIT_OFFSET) + continue; + get_64bit_val(buf, offset, &temp); + /* + * On MMG EMU due to a fw bug, we need to set local memory + * for QP in config FPM (although it is with 0 count) + * TODO - Remove this WA once FW is fixed + */ + set_64bit_val(buf, offset, temp | loc_mem_en); + } +} + +/** + * irdma_sc_cfg_iw_fpm() - commits hmc obj cnt values using cqp + * command and populates fpm base address in hmc_info + * @dev : ptr to irdma_dev struct + * @hmc_fn_id: hmc function id + */ +static int irdma_sc_cfg_iw_fpm(struct irdma_sc_dev *dev, u16 hmc_fn_id) +{ + struct irdma_hmc_obj_info *obj_info; + __le64 *buf; + struct irdma_hmc_info *hmc_info; + struct irdma_dma_mem commit_fpm_mem; + bool poll_registers = true; + int ret_code = 0; + u8 wait_type; + + if ((dev->privileged && hmc_fn_id > dev->hw_attrs.max_hw_vf_fpm_id) || + (dev->hmc_fn_id != hmc_fn_id && + hmc_fn_id < dev->hw_attrs.first_hw_vf_fpm_id)) + return -EINVAL; + + if (hmc_fn_id == dev->hmc_fn_id) { + hmc_info = dev->hmc_info; + } else { + hmc_info = irdma_vf_hmcinfo_from_fpm(dev, hmc_fn_id); + poll_registers = false; + } + if (!hmc_info) + return -EFAULT; + obj_info = hmc_info->hmc_obj; + buf = dev->fpm_commit_buf; + + set_64bit_val(buf, 0, (u64)obj_info[IRDMA_HMC_IW_QP].cnt); + set_64bit_val(buf, 8, (u64)obj_info[IRDMA_HMC_IW_CQ].cnt); + set_64bit_val(buf, 16, (u64)obj_info[IRDMA_HMC_IW_SRQ].cnt); + set_64bit_val(buf, 24, (u64)obj_info[IRDMA_HMC_IW_HTE].cnt); + set_64bit_val(buf, 32, (u64)obj_info[IRDMA_HMC_IW_ARP].cnt); + set_64bit_val(buf, 40, (u64)0); /* RSVD */ + set_64bit_val(buf, 48, (u64)obj_info[IRDMA_HMC_IW_MR].cnt); + set_64bit_val(buf, 56, (u64)obj_info[IRDMA_HMC_IW_XF].cnt); + set_64bit_val(buf, 64, (u64)obj_info[IRDMA_HMC_IW_XFFL].cnt); + set_64bit_val(buf, 72, (u64)obj_info[IRDMA_HMC_IW_Q1].cnt); + set_64bit_val(buf, 80, (u64)obj_info[IRDMA_HMC_IW_Q1FL].cnt); + set_64bit_val(buf, 88, + (u64)obj_info[IRDMA_HMC_IW_TIMER].cnt); + set_64bit_val(buf, 96, + (u64)obj_info[IRDMA_HMC_IW_FSIMC].cnt); + set_64bit_val(buf, 104, + (u64)obj_info[IRDMA_HMC_IW_FSIAV].cnt); + set_64bit_val(buf, 112, + (u64)obj_info[IRDMA_HMC_IW_PBLE].cnt); + set_64bit_val(buf, 120, (u64)0); /* RSVD */ + set_64bit_val(buf, 128, (u64)obj_info[IRDMA_HMC_IW_RRF].cnt); + set_64bit_val(buf, 136, + (u64)obj_info[IRDMA_HMC_IW_RRFFL].cnt); + set_64bit_val(buf, 144, (u64)obj_info[IRDMA_HMC_IW_HDR].cnt); + set_64bit_val(buf, 152, (u64)obj_info[IRDMA_HMC_IW_MD].cnt); + set_64bit_val(buf, 160, + (u64)obj_info[IRDMA_HMC_IW_OOISC].cnt); + set_64bit_val(buf, 168, + (u64)obj_info[IRDMA_HMC_IW_OOISCFFL].cnt); + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3 && + dev->hmc_fpm_misc.loc_mem_pages) + irdma_set_loc_mem(buf); + commit_fpm_mem.pa = dev->fpm_commit_buf_pa; + commit_fpm_mem.va = dev->fpm_commit_buf; + + wait_type = poll_registers ? (u8)IRDMA_CQP_WAIT_POLL_REGS : + (u8)IRDMA_CQP_WAIT_POLL_CQ; + print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, + 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, + false); + ret_code = irdma_sc_commit_fpm_val(dev->cqp, 0, hmc_info->hmc_fn_id, + &commit_fpm_mem, true, wait_type); + if (!ret_code) + irdma_sc_parse_fpm_commit_buf(dev, dev->fpm_commit_buf, + hmc_info->hmc_obj, + &hmc_info->sd_table.sd_cnt); + print_hex_dump_debug("HMC: COMMIT FPM BUFFER", DUMP_PREFIX_OFFSET, 16, + 8, commit_fpm_mem.va, IRDMA_COMMIT_FPM_BUF_SIZE, + false); + + return ret_code; +} + +/** + * cqp_sds_wqe_fill - fill cqp wqe doe sd + * @cqp: struct for cqp hw + * @info: sd info for wqe + * @scratch: u64 saved to be used during cqp completion + */ +static int cqp_sds_wqe_fill(struct irdma_sc_cqp *cqp, + struct irdma_update_sds_info *info, u64 scratch) +{ + u64 data; + u64 hdr; + __le64 *wqe; + int mem_entries, wqe_entries; + struct irdma_dma_mem *sdbuf = &cqp->sdbuf; + u64 offset = 0; + u32 wqe_idx; + + wqe = irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); + if (!wqe) + return -ENOMEM; + + wqe_entries = (info->cnt > 3) ? 3 : info->cnt; + mem_entries = info->cnt - wqe_entries; + + if (mem_entries) { + offset = wqe_idx * IRDMA_UPDATE_SD_BUFF_SIZE; + memcpy(((char *)sdbuf->va + offset), &info->entry[3], mem_entries << 4); + + data = (u64)sdbuf->pa + offset; + } else { + data = 0; + } + data |= FLD_LS_64(cqp->dev, info->hmc_fn_id, IRDMA_CQPSQ_UPESD_HMCFNID); + set_64bit_val(wqe, 16, data); + + switch (wqe_entries) { + case 3: + set_64bit_val(wqe, 48, + (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[2].cmd) | + FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); + + set_64bit_val(wqe, 56, info->entry[2].data); + fallthrough; + case 2: + set_64bit_val(wqe, 32, + (FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[1].cmd) | + FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_VALID, 1))); + + set_64bit_val(wqe, 40, info->entry[1].data); + fallthrough; + case 1: + set_64bit_val(wqe, 0, + FIELD_PREP(IRDMA_CQPSQ_UPESD_SDCMD, info->entry[0].cmd)); + + set_64bit_val(wqe, 8, info->entry[0].data); + break; + default: + break; + } + + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_UPDATE_PE_SDS) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_UPESD_ENTRY_COUNT, mem_entries); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + if (mem_entries) + print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE Buffer", + DUMP_PREFIX_OFFSET, 16, 8, + (char *)sdbuf->va + offset, + mem_entries << 4, false); + + print_hex_dump_debug("WQE: UPDATE_PE_SDS WQE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + + return 0; +} + +/** + * irdma_update_pe_sds - cqp wqe for sd + * @dev: ptr to irdma_dev struct + * @info: sd info for sd's + * @scratch: u64 saved to be used during cqp completion + */ +static int irdma_update_pe_sds(struct irdma_sc_dev *dev, + struct irdma_update_sds_info *info, u64 scratch) +{ + struct irdma_sc_cqp *cqp = dev->cqp; + int ret_code; + + ret_code = cqp_sds_wqe_fill(cqp, info, scratch); + if (!ret_code) + irdma_sc_cqp_post_sq(cqp); + + return ret_code; +} + +/** + * irdma_update_sds_noccq - update sd before ccq created + * @dev: sc device struct + * @info: sd info for sd's + */ +int irdma_update_sds_noccq(struct irdma_sc_dev *dev, + struct irdma_update_sds_info *info) +{ + u32 error, val, tail; + struct irdma_sc_cqp *cqp = dev->cqp; + int ret_code; + + ret_code = cqp_sds_wqe_fill(cqp, info, 0); + if (ret_code) + return ret_code; + + irdma_get_cqp_reg_info(cqp, &val, &tail, &error); + + irdma_sc_cqp_post_sq(cqp); + return irdma_cqp_poll_registers(cqp, tail, + cqp->dev->hw_attrs.max_done_count); +} + +/** + * irdma_sc_static_hmc_pages_allocated - cqp wqe to allocate hmc pages + * @cqp: struct for cqp hw + * @scratch: u64 saved to be used during cqp completion + * @hmc_fn_id: hmc function id + * @post_sq: flag for cqp db to ring + * @poll_registers: flag to poll register for cqp completion + */ +int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch, + u16 hmc_fn_id, bool post_sq, + bool poll_registers) +{ + u64 hdr; + __le64 *wqe; + u32 tail, val, error; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID, hmc_fn_id)); + + hdr = FIELD_PREP(IRDMA_CQPSQ_OPCODE, + IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("WQE: SHMC_PAGES_ALLOCATED WQE", + DUMP_PREFIX_OFFSET, 16, 8, wqe, + IRDMA_CQP_WQE_SIZE * 8, false); + irdma_get_cqp_reg_info(cqp, &val, &tail, &error); + + if (post_sq) { + irdma_sc_cqp_post_sq(cqp); + if (poll_registers) + /* check for cqp sq tail update */ + return irdma_cqp_poll_registers(cqp, tail, + cqp->dev->hw_attrs.max_done_count); + else + return irdma_sc_poll_for_cqp_op_done(cqp, + IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED, + NULL); + } + + return 0; +} + +/** + * irdma_cqp_ring_full - check if cqp ring is full + * @cqp: struct for cqp hw + */ +static bool irdma_cqp_ring_full(struct irdma_sc_cqp *cqp) +{ + return IRDMA_RING_FULL_ERR(cqp->sq_ring); +} + +/** + * irdma_est_sd - returns approximate number of SDs for HMC + * @dev: sc device struct + * @hmc_info: hmc structure, size and count for HMC objects + */ +static u32 irdma_est_sd(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info) +{ + struct irdma_hmc_obj_info *pble_info; + u64 size = 0; + u64 sd; + int i; + + for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) { + if (i != IRDMA_HMC_IW_PBLE) + size += round_up(hmc_info->hmc_obj[i].cnt * + hmc_info->hmc_obj[i].size, 512); + } + + pble_info = &hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE]; + if (dev->privileged) + size += round_up(pble_info->cnt * pble_info->size, 512); + if (size & 0x1FFFFF) + sd = (size >> 21) + 1; /* add 1 for remainder */ + else + sd = size >> 21; + if (!dev->privileged && !dev->hmc_fpm_misc.loc_mem_pages) { + /* 2MB alignment for VF PBLE HMC */ + size = pble_info->cnt * pble_info->size; + if (size & 0x1FFFFF) + sd += (size >> 21) + 1; /* add 1 for remainder */ + else + sd += size >> 21; + } + if (sd > 0xFFFFFFFF) { + ibdev_dbg(to_ibdev(dev), "HMC: sd overflow[%lld]\n", sd); + sd = 0xFFFFFFFE; + } + + return (u32)sd; +} + +/** + * irdma_sc_query_rdma_features - query RDMA features and FW ver + * @cqp: struct for cqp hw + * @buf: buffer to hold query info + * @scratch: u64 saved to be used during cqp completion + */ +static int irdma_sc_query_rdma_features(struct irdma_sc_cqp *cqp, + struct irdma_dma_mem *buf, u64 scratch) +{ + __le64 *wqe; + u64 temp; + u32 tail, val, error; + int status; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + temp = buf->pa; + set_64bit_val(wqe, 32, temp); + + temp = FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID, + cqp->polarity) | + FIELD_PREP(IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN, buf->size) | + FIELD_PREP(IRDMA_CQPSQ_UP_OP, IRDMA_CQP_OP_QUERY_RDMA_FEATURES); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, temp); + + print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, + 16, 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_get_cqp_reg_info(cqp, &val, &tail, &error); + + irdma_sc_cqp_post_sq(cqp); + status = irdma_cqp_poll_registers(cqp, tail, + cqp->dev->hw_attrs.max_done_count); + if (error || status) + status = -EIO; + + return status; +} + +/** + * irdma_get_rdma_features - get RDMA features + * @dev: sc device struct + */ +int irdma_get_rdma_features(struct irdma_sc_dev *dev) +{ + int ret_code, byte_idx, feat_type, feat_cnt, feat_idx; + struct irdma_dma_mem feat_buf; + u64 temp; + + feat_buf.size = ALIGN(IRDMA_FEATURE_BUF_SIZE, + IRDMA_FEATURE_BUF_ALIGNMENT); + feat_buf.va = dma_alloc_coherent(dev->hw->device, feat_buf.size, + &feat_buf.pa, GFP_KERNEL); + if (!feat_buf.va) + return -ENOMEM; + + ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); + if (ret_code) + goto exit; + + get_64bit_val(feat_buf.va, 0, &temp); + feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); + if (feat_cnt < IRDMA_MIN_FEATURES) { + ret_code = -EINVAL; + goto exit; + } else if (feat_cnt > IRDMA_MAX_FEATURES) { + ibdev_dbg(to_ibdev(dev), + "DEV: feature buf size insufficient, retrying with larger buffer\n"); + dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, + feat_buf.pa); + feat_buf.va = NULL; + feat_buf.size = ALIGN(8 * feat_cnt, + IRDMA_FEATURE_BUF_ALIGNMENT); + feat_buf.va = dma_alloc_coherent(dev->hw->device, + feat_buf.size, &feat_buf.pa, + GFP_KERNEL); + if (!feat_buf.va) + return -ENOMEM; + + ret_code = irdma_sc_query_rdma_features(dev->cqp, &feat_buf, 0); + if (ret_code) + goto exit; + + get_64bit_val(feat_buf.va, 0, &temp); + feat_cnt = (u16)FIELD_GET(IRDMA_FEATURE_CNT, temp); + if (feat_cnt < IRDMA_MIN_FEATURES) { + ret_code = -EINVAL; + goto exit; + } + } + + print_hex_dump_debug("WQE: QUERY RDMA FEATURES", DUMP_PREFIX_OFFSET, + 16, 8, feat_buf.va, feat_cnt * 8, false); + + for (byte_idx = 0, feat_idx = 0; feat_idx < min(feat_cnt, IRDMA_MAX_FEATURES); + feat_idx++, byte_idx += 8) { + get_64bit_val(feat_buf.va, byte_idx, &temp); + feat_type = FIELD_GET(IRDMA_FEATURE_TYPE, temp); + dev->feature_info[feat_type] = temp; + } +exit: + dma_free_coherent(dev->hw->device, feat_buf.size, feat_buf.va, + feat_buf.pa); + feat_buf.va = NULL; + return ret_code; +} + +/** + * irdma_get_rsrc_mem_config - configure resources if local memory or host + * @dev: sc device struct + * @is_mrte_loc_mem: if true, MR's to be in local memory because sd=loc pages + * + * Only mr can be configured host or local memory if qp's are in local memory. + * If qp is in local memory, then all resource object will be in local memory except + * mr which can be either host or local memory. The only exception is pble's which are always + * in host memory. + */ +static void irdma_get_rsrc_mem_config(struct irdma_sc_dev *dev, bool is_mrte_loc_mem) +{ + struct irdma_hmc_fpm_misc *hmc_fpm_misc = &dev->hmc_fpm_misc; + struct irdma_hmc_info *hmc_info = dev->hmc_info; + enum irdma_hmc_obj_mem mem_loc; + int i; + + mem_loc = hmc_fpm_misc->loc_mem_pages ? IRDMA_LOC_MEM : IRDMA_HOST_MEM; + + for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) + hmc_info->hmc_obj[i].mem_loc = mem_loc; + + if (dev->feature_info[IRDMA_OBJ_1] && !is_mrte_loc_mem) { + u8 mem_type; + + mem_type = (u8)FIELD_GET(IRDMA_MR_MEM_LOC, dev->feature_info[IRDMA_OBJ_1]); + + hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc = + (mem_type & IRDMA_OBJ_LOC_MEM_BIT) ? + IRDMA_LOC_MEM : IRDMA_HOST_MEM; + } else { + hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc = IRDMA_LOC_MEM; + } + + hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].mem_loc = IRDMA_HOST_MEM; + + ibdev_dbg(to_ibdev(dev), "HMC: INFO: mrte_mem_loc = %d pble = %d\n", + hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc, + hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].mem_loc); +} + +static u32 irdma_q1_cnt(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, u32 qpwanted) +{ + u32 q1_cnt; + + if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { + q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted); + } else { + if (dev->cqp->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY) + q1_cnt = roundup_pow_of_two(dev->hw_attrs.max_hw_ird * 2 * qpwanted + 512); + else + q1_cnt = dev->hw_attrs.max_hw_ird * 2 * qpwanted; + } + + return q1_cnt; +} + +static void cfg_fpm_value_gen_1(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, u32 qpwanted) +{ + hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = roundup_pow_of_two(qpwanted * dev->hw_attrs.max_hw_wqes); +} + +static void cfg_fpm_value_gen_2(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, u32 qpwanted) +{ + struct irdma_hmc_fpm_misc *hmc_fpm_misc = &dev->hmc_fpm_misc; + + hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = + 4 * hmc_fpm_misc->xf_block_size * qpwanted; + + hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; + + if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt) + hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = 32 * qpwanted; + if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) + hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt = + hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / + hmc_fpm_misc->rrf_block_size; + if (dev->cqp->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) { + if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt) + hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt = 32 * qpwanted; + if (hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt) + hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].cnt = + hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].cnt / + hmc_fpm_misc->ooiscf_block_size; + } +} + +/** + * irdma_cfg_sd_mem - allocate sd memory + * @dev: sc device struct + * @hmc_info: ptr to irdma_hmc_obj_info struct + */ +static int irdma_cfg_sd_mem(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info) +{ + struct irdma_virt_mem virt_mem; + u32 mem_size; + + mem_size = sizeof(struct irdma_hmc_sd_entry) * hmc_info->sd_table.sd_cnt; + virt_mem.size = mem_size; + virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL); + if (!virt_mem.va) + return -ENOMEM; + hmc_info->sd_table.sd_entry = virt_mem.va; + + return 0; +} + +/** + * irdma_get_objs_pages - get number of 2M pages needed + * @dev: sc device struct + * @hmc_info: pointer to the HMC configuration information struct + * @mem_loc: pages for local or host memory + */ +static u32 irdma_get_objs_pages(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, + enum irdma_hmc_obj_mem mem_loc) +{ + u64 size = 0; + int i; + + for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) { + if (hmc_info->hmc_obj[i].mem_loc == mem_loc) { + size += round_up(hmc_info->hmc_obj[i].cnt * + hmc_info->hmc_obj[i].size, 512); + } + } + + return (u32)DIV_ROUND_UP(size, IRDMA_HMC_PAGE_SIZE); +} + +/** + * irdma_set_host_hmc_rsrc_gen_3 - calculate host hmc resources for gen 3 + * @dev: sc device struct + */ +static void irdma_set_host_hmc_rsrc_gen_3(struct irdma_sc_dev *dev) +{ + struct irdma_hmc_fpm_misc *hmc_fpm_misc; + struct irdma_hmc_info *hmc_info; + enum irdma_hmc_obj_mem mrte_loc; + u32 mrwanted, pblewanted; + u32 avail_sds, mr_sds; + + hmc_info = dev->hmc_info; + hmc_fpm_misc = &dev->hmc_fpm_misc; + avail_sds = hmc_fpm_misc->max_sds; + mrte_loc = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc; + mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; + pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt; + + if (mrte_loc == IRDMA_HOST_MEM && avail_sds > IRDMA_MIN_PBLE_PAGES) { + mr_sds = avail_sds - IRDMA_MIN_PBLE_PAGES; + mrwanted = min(mrwanted, mr_sds * MAX_MR_PER_SD); + hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted; + avail_sds -= DIV_ROUND_UP(mrwanted, MAX_MR_PER_SD); + } + + pblewanted = min(pblewanted, avail_sds * MAX_PBLE_PER_SD); + hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; +} + +/** + * irdma_set_loc_hmc_rsrc_gen_3 - calculate hmc resources for gen 3 + * @dev: sc device struct + * @max_pages: max local memory available + * @qpwanted: number of qp's wanted + */ +static int irdma_set_loc_hmc_rsrc_gen_3(struct irdma_sc_dev *dev, + u32 max_pages, + u32 qpwanted) +{ + struct irdma_hmc_fpm_misc *hmc_fpm_misc; + u32 xf_cnt, timer_cnt, pages_needed; + struct irdma_hmc_info *hmc_info; + u8 ird, ord; + + hmc_info = dev->hmc_info; + hmc_fpm_misc = &dev->hmc_fpm_misc; + ird = dev->hw_attrs.max_hw_ird; + ord = dev->hw_attrs.max_hw_ord; + + hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; + hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted; + + hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt = + min(hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, qpwanted * 2); + + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt = min(qpwanted * 8, + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt); + + hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt = + min(hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].max_cnt, IRDMA_RRF_MULTIPLIER * qpwanted); + + if (hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].max_cnt) + hmc_info->hmc_obj[IRDMA_HMC_IW_RRFFL].cnt = + hmc_info->hmc_obj[IRDMA_HMC_IW_RRF].cnt / + hmc_fpm_misc->rrf_block_size; + + xf_cnt = IRDMA_XF_MULTIPLIER * qpwanted; + xf_cnt = min(hmc_info->hmc_obj[IRDMA_HMC_IW_XF].max_cnt, xf_cnt); + hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt = xf_cnt; + + if (xf_cnt) + hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt = + xf_cnt / hmc_fpm_misc->xf_block_size; + + timer_cnt = (round_up(qpwanted, 512) / 512 + 1) * + hmc_fpm_misc->timer_bucket; + hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt = + min(timer_cnt, hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt); + + do { + hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = ird * 2 * qpwanted; + hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt = + hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; + + pages_needed = irdma_get_objs_pages(dev, hmc_info, IRDMA_LOC_MEM); + if (pages_needed <= max_pages) + break; + + ird /= 2; + ord /= 2; + } while (ird >= IRDMA_MIN_IRD); + + if (ird < IRDMA_MIN_IRD) { + ibdev_dbg(to_ibdev(dev), "HMC: FAIL: IRD=%u Q1 CNT = %u\n", + ird, hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt); + + return -EINVAL; + } + + dev->hw_attrs.max_hw_ird = ird; + dev->hw_attrs.max_hw_ord = ord; + hmc_fpm_misc->max_sds -= pages_needed; + hmc_fpm_misc->loc_mem_pages -= pages_needed; + + return 0; +} + +/** + * cfg_fpm_value_gen_3 - configure fpm for gen 3 + * @dev: sc device struct + * @hmc_info: ptr to irdma_hmc_obj_info struct + * @hmc_fpm_misc: ptr to fpm data + */ +static int cfg_fpm_value_gen_3(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, + struct irdma_hmc_fpm_misc *hmc_fpm_misc) +{ + enum irdma_hmc_obj_mem mrte_loc; + u32 mrwanted, qpwanted; + int i, ret_code = 0; + u32 loc_mem_pages; + bool is_mrte_loc_mem; + + loc_mem_pages = hmc_fpm_misc->loc_mem_pages; + is_mrte_loc_mem = hmc_fpm_misc->loc_mem_pages == hmc_fpm_misc->max_sds ? + true : false; + + irdma_get_rsrc_mem_config(dev, is_mrte_loc_mem); + mrte_loc = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc; + + if (is_mrte_loc_mem) + loc_mem_pages -= IRDMA_MIN_PBLE_PAGES; + + ibdev_dbg(to_ibdev(dev), + "HMC: mrte_loc %d loc_mem %u fpm max sds %u host_obj %d\n", + hmc_info->hmc_obj[IRDMA_HMC_IW_MR].mem_loc, + hmc_fpm_misc->loc_mem_pages, hmc_fpm_misc->max_sds, + is_mrte_loc_mem); + + mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt; + qpwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt; + hmc_info->hmc_obj[IRDMA_HMC_IW_HDR].cnt = qpwanted; + + hmc_info->hmc_obj[IRDMA_HMC_IW_OOISC].max_cnt = 0; + hmc_info->hmc_obj[IRDMA_HMC_IW_OOISCFFL].max_cnt = 0; + hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].max_cnt = 0; + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt = 0; + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt = + min(hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt, + (u32)IRDMA_FSIAV_CNT_MAX); + for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) + hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; + + while (qpwanted >= IRDMA_MIN_QP_CNT) { + if (!irdma_set_loc_hmc_rsrc_gen_3(dev, loc_mem_pages, qpwanted)) + break; + + qpwanted /= 2; + if (mrte_loc == IRDMA_LOC_MEM) { + mrwanted = qpwanted * IRDMA_MIN_MR_PER_QP; + hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = + min(hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt, mrwanted); + } + } + + if (qpwanted < IRDMA_MIN_QP_CNT) { + ibdev_dbg(to_ibdev(dev), + "HMC: Could not allocate fpm resources.\n"); + + return -EINVAL; + } + + irdma_set_host_hmc_rsrc_gen_3(dev); + ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id); + if (ret_code) { + ibdev_dbg(to_ibdev(dev), + "HMC: cfg_iw_fpm returned error_code[x%08X]\n", + readl(dev->hw_regs[IRDMA_CQPERRCODES])); + + return ret_code; + } + + return irdma_cfg_sd_mem(dev, hmc_info); +} + +/** + * irdma_cfg_fpm_val - configure HMC objects + * @dev: sc device struct + * @qp_count: desired qp count + */ +int irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count) +{ + u32 qpwanted, mrwanted, pblewanted; + u32 powerof2, hte, i; + u32 sd_needed; + u32 sd_diff; + u32 loop_count = 0; + struct irdma_hmc_info *hmc_info; + struct irdma_hmc_fpm_misc *hmc_fpm_misc; + int ret_code = 0; + u32 max_sds; + + hmc_info = dev->hmc_info; + hmc_fpm_misc = &dev->hmc_fpm_misc; + ret_code = irdma_sc_init_iw_hmc(dev, dev->hmc_fn_id); + if (ret_code) { + ibdev_dbg(to_ibdev(dev), + "HMC: irdma_sc_init_iw_hmc returned error_code = %d\n", + ret_code); + return ret_code; + } + + max_sds = hmc_fpm_misc->max_sds; + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) + return cfg_fpm_value_gen_3(dev, hmc_info, hmc_fpm_misc); + + for (i = IRDMA_HMC_IW_QP; i < IRDMA_HMC_IW_MAX; i++) + hmc_info->hmc_obj[i].cnt = hmc_info->hmc_obj[i].max_cnt; + + sd_needed = irdma_est_sd(dev, hmc_info); + ibdev_dbg(to_ibdev(dev), "HMC: sd count %u where max sd is %u\n", + hmc_info->sd_table.sd_cnt, max_sds); + + qpwanted = min(qp_count, hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt); + + powerof2 = 1; + while (powerof2 <= qpwanted) + powerof2 *= 2; + powerof2 /= 2; + qpwanted = powerof2; + + mrwanted = hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt; + pblewanted = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt; + + ibdev_dbg(to_ibdev(dev), + "HMC: req_qp=%d max_sd=%u, max_qp = %u, max_cq=%u, max_mr=%u, max_pble=%u, mc=%d, av=%u\n", + qp_count, max_sds, + hmc_info->hmc_obj[IRDMA_HMC_IW_QP].max_cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_MR].max_cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].max_cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt); + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt = + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].max_cnt; + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt = + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].max_cnt; + hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt = + hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].max_cnt; + hmc_info->hmc_obj[IRDMA_HMC_IW_APBVT_ENTRY].cnt = 1; + + while (irdma_q1_cnt(dev, hmc_info, qpwanted) > hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].max_cnt) + qpwanted /= 2; + + if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { + cfg_fpm_value_gen_1(dev, hmc_info, qpwanted); + while (hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt > hmc_info->hmc_obj[IRDMA_HMC_IW_XF].max_cnt) { + qpwanted /= 2; + cfg_fpm_value_gen_1(dev, hmc_info, qpwanted); + } + } + + do { + ++loop_count; + hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt = qpwanted; + hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt = + min(2 * qpwanted, hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt); + hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].cnt = 0; /* Reserved */ + hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt = mrwanted; + + hte = round_up(qpwanted + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, 512); + powerof2 = 1; + while (powerof2 < hte) + powerof2 *= 2; + hmc_info->hmc_obj[IRDMA_HMC_IW_HTE].cnt = + powerof2 * hmc_fpm_misc->ht_multiplier; + if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + cfg_fpm_value_gen_1(dev, hmc_info, qpwanted); + else + cfg_fpm_value_gen_2(dev, hmc_info, qpwanted); + + hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt = irdma_q1_cnt(dev, hmc_info, qpwanted); + hmc_info->hmc_obj[IRDMA_HMC_IW_XFFL].cnt = + hmc_info->hmc_obj[IRDMA_HMC_IW_XF].cnt / hmc_fpm_misc->xf_block_size; + hmc_info->hmc_obj[IRDMA_HMC_IW_Q1FL].cnt = + hmc_info->hmc_obj[IRDMA_HMC_IW_Q1].cnt / hmc_fpm_misc->q1_block_size; + hmc_info->hmc_obj[IRDMA_HMC_IW_TIMER].cnt = + (round_up(qpwanted, 512) / 512 + 1) * hmc_fpm_misc->timer_bucket; + + hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; + sd_needed = irdma_est_sd(dev, hmc_info); + ibdev_dbg(to_ibdev(dev), + "HMC: sd_needed = %d, max_sds=%d, mrwanted=%d, pblewanted=%d qpwanted=%d\n", + sd_needed, max_sds, mrwanted, pblewanted, qpwanted); + + /* Do not reduce resources further. All objects fit with max SDs */ + if (sd_needed <= max_sds) + break; + + sd_diff = sd_needed - max_sds; + if (sd_diff > 128) { + if (!(loop_count % 2) && qpwanted > 128) { + qpwanted /= 2; + } else { + pblewanted /= 2; + mrwanted /= 2; + } + continue; + } + + if (dev->cqp->hmc_profile != IRDMA_HMC_PROFILE_FAVOR_VF && + pblewanted > (512 * FPM_MULTIPLIER * sd_diff)) { + pblewanted -= 256 * FPM_MULTIPLIER * sd_diff; + continue; + } else if (pblewanted > 100 * FPM_MULTIPLIER) { + pblewanted -= 10 * FPM_MULTIPLIER; + } else if (pblewanted > 16 * FPM_MULTIPLIER) { + pblewanted -= FPM_MULTIPLIER; + } else if (qpwanted <= 128) { + if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt > 256) + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt /= 2; + if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; + } + if (mrwanted > FPM_MULTIPLIER) + mrwanted -= FPM_MULTIPLIER; + if (!(loop_count % 10) && qpwanted > 128) { + qpwanted /= 2; + if (hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt > 256) + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt /= 2; + } + } while (loop_count < 2000); + + if (sd_needed > max_sds) { + ibdev_dbg(to_ibdev(dev), + "HMC: cfg_fpm failed loop_cnt=%u, sd_needed=%u, max sd count %u\n", + loop_count, sd_needed, hmc_info->sd_table.sd_cnt); + return -EINVAL; + } + + if (loop_count > 1 && sd_needed < max_sds) { + pblewanted += (max_sds - sd_needed) * 256 * FPM_MULTIPLIER; + hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt = pblewanted; + sd_needed = irdma_est_sd(dev, hmc_info); + } + + ibdev_dbg(to_ibdev(dev), + "HMC: loop_cnt=%d, sd_needed=%d, qpcnt = %d, cqcnt=%d, mrcnt=%d, pblecnt=%d, mc=%d, ah=%d, max sd count %d, first sd index %d\n", + loop_count, sd_needed, + hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIMC].cnt, + hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt, + hmc_info->sd_table.sd_cnt, hmc_info->first_sd_index); + + ret_code = irdma_sc_cfg_iw_fpm(dev, dev->hmc_fn_id); + if (ret_code) { + ibdev_dbg(to_ibdev(dev), + "HMC: cfg_iw_fpm returned error_code[x%08X]\n", + readl(dev->hw_regs[IRDMA_CQPERRCODES])); + return ret_code; + } + + return irdma_cfg_sd_mem(dev, hmc_info); +} + +/** + * irdma_exec_cqp_cmd - execute cqp cmd when wqe are available + * @dev: rdma device + * @pcmdinfo: cqp command info + */ +static int irdma_exec_cqp_cmd(struct irdma_sc_dev *dev, + struct cqp_cmds_info *pcmdinfo) +{ + int status; + struct irdma_dma_mem val_mem; + bool alloc = false; + + dev->cqp_cmd_stats[pcmdinfo->cqp_cmd]++; + switch (pcmdinfo->cqp_cmd) { + case IRDMA_OP_CEQ_DESTROY: + status = irdma_sc_ceq_destroy(pcmdinfo->in.u.ceq_destroy.ceq, + pcmdinfo->in.u.ceq_destroy.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_AEQ_DESTROY: + status = irdma_sc_aeq_destroy(pcmdinfo->in.u.aeq_destroy.aeq, + pcmdinfo->in.u.aeq_destroy.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_CEQ_CREATE: + status = irdma_sc_ceq_create(pcmdinfo->in.u.ceq_create.ceq, + pcmdinfo->in.u.ceq_create.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_AEQ_CREATE: + status = irdma_sc_aeq_create(pcmdinfo->in.u.aeq_create.aeq, + pcmdinfo->in.u.aeq_create.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_QP_UPLOAD_CONTEXT: + status = irdma_sc_qp_upload_context(pcmdinfo->in.u.qp_upload_context.dev, + &pcmdinfo->in.u.qp_upload_context.info, + pcmdinfo->in.u.qp_upload_context.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_CQ_CREATE: + status = irdma_sc_cq_create(pcmdinfo->in.u.cq_create.cq, + pcmdinfo->in.u.cq_create.scratch, + pcmdinfo->in.u.cq_create.check_overflow, + pcmdinfo->post_sq); + break; + case IRDMA_OP_CQ_MODIFY: + status = irdma_sc_cq_modify(pcmdinfo->in.u.cq_modify.cq, + &pcmdinfo->in.u.cq_modify.info, + pcmdinfo->in.u.cq_modify.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_CQ_DESTROY: + status = irdma_sc_cq_destroy(pcmdinfo->in.u.cq_destroy.cq, + pcmdinfo->in.u.cq_destroy.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_QP_FLUSH_WQES: + status = irdma_sc_qp_flush_wqes(pcmdinfo->in.u.qp_flush_wqes.qp, + &pcmdinfo->in.u.qp_flush_wqes.info, + pcmdinfo->in.u.qp_flush_wqes.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_GEN_AE: + status = irdma_sc_gen_ae(pcmdinfo->in.u.gen_ae.qp, + &pcmdinfo->in.u.gen_ae.info, + pcmdinfo->in.u.gen_ae.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_MANAGE_PUSH_PAGE: + status = irdma_sc_manage_push_page(pcmdinfo->in.u.manage_push_page.cqp, + &pcmdinfo->in.u.manage_push_page.info, + pcmdinfo->in.u.manage_push_page.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_UPDATE_PE_SDS: + status = irdma_update_pe_sds(pcmdinfo->in.u.update_pe_sds.dev, + &pcmdinfo->in.u.update_pe_sds.info, + pcmdinfo->in.u.update_pe_sds.scratch); + break; + case IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE: + /* switch to calling through the call table */ + status = + irdma_sc_manage_hmc_pm_func_table(pcmdinfo->in.u.manage_hmc_pm.dev->cqp, + &pcmdinfo->in.u.manage_hmc_pm.info, + pcmdinfo->in.u.manage_hmc_pm.scratch, + true); + break; + case IRDMA_OP_SUSPEND: + status = irdma_sc_suspend_qp(pcmdinfo->in.u.suspend_resume.cqp, + pcmdinfo->in.u.suspend_resume.qp, + pcmdinfo->in.u.suspend_resume.scratch); + break; + case IRDMA_OP_RESUME: + status = irdma_sc_resume_qp(pcmdinfo->in.u.suspend_resume.cqp, + pcmdinfo->in.u.suspend_resume.qp, + pcmdinfo->in.u.suspend_resume.scratch); + break; + case IRDMA_OP_MANAGE_PBLE_BP: + status = irdma_sc_manage_pble_bp(pcmdinfo->in.u.manage_pble_bp.cqp, + &pcmdinfo->in.u.manage_pble_bp.info, + pcmdinfo->in.u.manage_pble_bp.scratch, + true); + break; + case IRDMA_OP_QUERY_FPM_VAL: + val_mem.pa = pcmdinfo->in.u.query_fpm_val.fpm_val_pa; + val_mem.va = pcmdinfo->in.u.query_fpm_val.fpm_val_va; + status = irdma_sc_query_fpm_val(pcmdinfo->in.u.query_fpm_val.cqp, + pcmdinfo->in.u.query_fpm_val.scratch, + pcmdinfo->in.u.query_fpm_val.hmc_fn_id, + &val_mem, true, IRDMA_CQP_WAIT_EVENT); + break; + case IRDMA_OP_COMMIT_FPM_VAL: + val_mem.pa = pcmdinfo->in.u.commit_fpm_val.fpm_val_pa; + val_mem.va = pcmdinfo->in.u.commit_fpm_val.fpm_val_va; + status = irdma_sc_commit_fpm_val(pcmdinfo->in.u.commit_fpm_val.cqp, + pcmdinfo->in.u.commit_fpm_val.scratch, + pcmdinfo->in.u.commit_fpm_val.hmc_fn_id, + &val_mem, + true, + IRDMA_CQP_WAIT_EVENT); + break; + case IRDMA_OP_STATS_ALLOCATE: + alloc = true; + fallthrough; + case IRDMA_OP_STATS_FREE: + status = irdma_sc_manage_stats_inst(pcmdinfo->in.u.stats_manage.cqp, + &pcmdinfo->in.u.stats_manage.info, + alloc, + pcmdinfo->in.u.stats_manage.scratch); + break; + case IRDMA_OP_STATS_GATHER: + status = irdma_sc_gather_stats(pcmdinfo->in.u.stats_gather.cqp, + &pcmdinfo->in.u.stats_gather.info, + pcmdinfo->in.u.stats_gather.scratch); + break; + case IRDMA_OP_WS_MOVE: + status = irdma_sc_ws_move_node(pcmdinfo->in.u.ws_move_node.cqp, + &pcmdinfo->in.u.ws_move_node.info, + pcmdinfo->in.u.ws_move_node.scratch); + break; + case IRDMA_OP_WS_MODIFY_NODE: + status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, + &pcmdinfo->in.u.ws_node.info, + IRDMA_MODIFY_NODE, + pcmdinfo->in.u.ws_node.scratch); + break; + case IRDMA_OP_WS_DELETE_NODE: + status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, + &pcmdinfo->in.u.ws_node.info, + IRDMA_DEL_NODE, + pcmdinfo->in.u.ws_node.scratch); + break; + case IRDMA_OP_WS_ADD_NODE: + status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, + &pcmdinfo->in.u.ws_node.info, + IRDMA_ADD_NODE, + pcmdinfo->in.u.ws_node.scratch); + break; + case IRDMA_OP_WS_FAILOVER_START: + status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, + &pcmdinfo->in.u.ws_node.info, + IRDMA_FAILOVER_START, + pcmdinfo->in.u.ws_node.scratch); + break; + case IRDMA_OP_WS_FAILOVER_COMPLETE: + status = irdma_sc_manage_ws_node(pcmdinfo->in.u.ws_node.cqp, + &pcmdinfo->in.u.ws_node.info, + IRDMA_FAILOVER_COMPLETE, + pcmdinfo->in.u.ws_node.scratch); + break; + case IRDMA_OP_SET_UP_MAP: + status = irdma_sc_set_up_map(pcmdinfo->in.u.up_map.cqp, + &pcmdinfo->in.u.up_map.info, + pcmdinfo->in.u.up_map.scratch); + break; + case IRDMA_OP_QUERY_RDMA_FEATURES: + status = irdma_sc_query_rdma_features(pcmdinfo->in.u.query_rdma.cqp, + &pcmdinfo->in.u.query_rdma.query_buff_mem, + pcmdinfo->in.u.query_rdma.scratch); + break; + case IRDMA_OP_DELETE_ARP_CACHE_ENTRY: + status = irdma_sc_del_arp_cache_entry(pcmdinfo->in.u.del_arp_cache_entry.cqp, + pcmdinfo->in.u.del_arp_cache_entry.scratch, + pcmdinfo->in.u.del_arp_cache_entry.arp_index, + pcmdinfo->post_sq); + break; + case IRDMA_OP_MANAGE_APBVT_ENTRY: + status = irdma_sc_manage_apbvt_entry(pcmdinfo->in.u.manage_apbvt_entry.cqp, + &pcmdinfo->in.u.manage_apbvt_entry.info, + pcmdinfo->in.u.manage_apbvt_entry.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY: + status = irdma_sc_manage_qhash_table_entry(pcmdinfo->in.u.manage_qhash_table_entry.cqp, + &pcmdinfo->in.u.manage_qhash_table_entry.info, + pcmdinfo->in.u.manage_qhash_table_entry.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_QP_MODIFY: + status = irdma_sc_qp_modify(pcmdinfo->in.u.qp_modify.qp, + &pcmdinfo->in.u.qp_modify.info, + pcmdinfo->in.u.qp_modify.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_QP_CREATE: + status = irdma_sc_qp_create(pcmdinfo->in.u.qp_create.qp, + &pcmdinfo->in.u.qp_create.info, + pcmdinfo->in.u.qp_create.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_QP_DESTROY: + status = irdma_sc_qp_destroy(pcmdinfo->in.u.qp_destroy.qp, + pcmdinfo->in.u.qp_destroy.scratch, + pcmdinfo->in.u.qp_destroy.remove_hash_idx, + pcmdinfo->in.u.qp_destroy.ignore_mw_bnd, + pcmdinfo->post_sq); + break; + case IRDMA_OP_ALLOC_STAG: + status = irdma_sc_alloc_stag(pcmdinfo->in.u.alloc_stag.dev, + &pcmdinfo->in.u.alloc_stag.info, + pcmdinfo->in.u.alloc_stag.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_MR_REG_NON_SHARED: + status = irdma_sc_mr_reg_non_shared(pcmdinfo->in.u.mr_reg_non_shared.dev, + &pcmdinfo->in.u.mr_reg_non_shared.info, + pcmdinfo->in.u.mr_reg_non_shared.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_DEALLOC_STAG: + status = irdma_sc_dealloc_stag(pcmdinfo->in.u.dealloc_stag.dev, + &pcmdinfo->in.u.dealloc_stag.info, + pcmdinfo->in.u.dealloc_stag.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_MW_ALLOC: + status = irdma_sc_mw_alloc(pcmdinfo->in.u.mw_alloc.dev, + &pcmdinfo->in.u.mw_alloc.info, + pcmdinfo->in.u.mw_alloc.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_ADD_ARP_CACHE_ENTRY: + status = irdma_sc_add_arp_cache_entry(pcmdinfo->in.u.add_arp_cache_entry.cqp, + &pcmdinfo->in.u.add_arp_cache_entry.info, + pcmdinfo->in.u.add_arp_cache_entry.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY: + status = irdma_sc_alloc_local_mac_entry(pcmdinfo->in.u.alloc_local_mac_entry.cqp, + pcmdinfo->in.u.alloc_local_mac_entry.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_ADD_LOCAL_MAC_ENTRY: + status = irdma_sc_add_local_mac_entry(pcmdinfo->in.u.add_local_mac_entry.cqp, + &pcmdinfo->in.u.add_local_mac_entry.info, + pcmdinfo->in.u.add_local_mac_entry.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_DELETE_LOCAL_MAC_ENTRY: + status = irdma_sc_del_local_mac_entry(pcmdinfo->in.u.del_local_mac_entry.cqp, + pcmdinfo->in.u.del_local_mac_entry.scratch, + pcmdinfo->in.u.del_local_mac_entry.entry_idx, + pcmdinfo->in.u.del_local_mac_entry.ignore_ref_count, + pcmdinfo->post_sq); + break; + case IRDMA_OP_AH_CREATE: + status = irdma_sc_create_ah(pcmdinfo->in.u.ah_create.cqp, + &pcmdinfo->in.u.ah_create.info, + pcmdinfo->in.u.ah_create.scratch); + break; + case IRDMA_OP_AH_DESTROY: + status = irdma_sc_destroy_ah(pcmdinfo->in.u.ah_destroy.cqp, + &pcmdinfo->in.u.ah_destroy.info, + pcmdinfo->in.u.ah_destroy.scratch); + break; + case IRDMA_OP_MC_CREATE: + status = irdma_sc_create_mcast_grp(pcmdinfo->in.u.mc_create.cqp, + &pcmdinfo->in.u.mc_create.info, + pcmdinfo->in.u.mc_create.scratch); + break; + case IRDMA_OP_MC_DESTROY: + status = irdma_sc_destroy_mcast_grp(pcmdinfo->in.u.mc_destroy.cqp, + &pcmdinfo->in.u.mc_destroy.info, + pcmdinfo->in.u.mc_destroy.scratch); + break; + case IRDMA_OP_MC_MODIFY: + status = irdma_sc_modify_mcast_grp(pcmdinfo->in.u.mc_modify.cqp, + &pcmdinfo->in.u.mc_modify.info, + pcmdinfo->in.u.mc_modify.scratch); + break; + case IRDMA_OP_SRQ_CREATE: + status = irdma_sc_srq_create(pcmdinfo->in.u.srq_create.srq, + pcmdinfo->in.u.srq_create.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_SRQ_MODIFY: + status = irdma_sc_srq_modify(pcmdinfo->in.u.srq_modify.srq, + &pcmdinfo->in.u.srq_modify.info, + pcmdinfo->in.u.srq_modify.scratch, + pcmdinfo->post_sq); + break; + case IRDMA_OP_SRQ_DESTROY: + status = irdma_sc_srq_destroy(pcmdinfo->in.u.srq_destroy.srq, + pcmdinfo->in.u.srq_destroy.scratch, + pcmdinfo->post_sq); + break; + default: + status = -EOPNOTSUPP; + break; + } + + return status; +} + +/** + * irdma_process_cqp_cmd - process all cqp commands + * @dev: sc device struct + * @pcmdinfo: cqp command info + */ +int irdma_process_cqp_cmd(struct irdma_sc_dev *dev, + struct cqp_cmds_info *pcmdinfo) +{ + int status = 0; + unsigned long flags; + + spin_lock_irqsave(&dev->cqp_lock, flags); + if (list_empty(&dev->cqp_cmd_head) && !irdma_cqp_ring_full(dev->cqp)) + status = irdma_exec_cqp_cmd(dev, pcmdinfo); + else + list_add_tail(&pcmdinfo->cqp_cmd_entry, &dev->cqp_cmd_head); + spin_unlock_irqrestore(&dev->cqp_lock, flags); + return status; +} + +/** + * irdma_process_bh - called from tasklet for cqp list + * @dev: sc device struct + */ +int irdma_process_bh(struct irdma_sc_dev *dev) +{ + int status = 0; + struct cqp_cmds_info *pcmdinfo; + unsigned long flags; + + spin_lock_irqsave(&dev->cqp_lock, flags); + while (!list_empty(&dev->cqp_cmd_head) && + !irdma_cqp_ring_full(dev->cqp)) { + pcmdinfo = (struct cqp_cmds_info *)irdma_remove_cqp_head(dev); + status = irdma_exec_cqp_cmd(dev, pcmdinfo); + if (status) + break; + } + spin_unlock_irqrestore(&dev->cqp_lock, flags); + return status; +} + +#if IS_ENABLED(CONFIG_CONFIGFS_FS) +/** + * irdma_set_irq_rate_limit- Configure interrupt rate limit + * @dev: pointer to the device structure + * @idx: vector index + * @interval: Time interval in 4 usec units. Zero for no limit. + */ +void irdma_set_irq_rate_limit(struct irdma_sc_dev *dev, u32 idx, u32 interval) +{ + u32 reg_val = 0; + + if (interval) { +#define IRDMA_MAX_SUPPORTED_INT_RATE_INTERVAL 59 /* 59 * 4 = 236 us */ + if (interval > IRDMA_MAX_SUPPORTED_INT_RATE_INTERVAL) + interval = IRDMA_MAX_SUPPORTED_INT_RATE_INTERVAL; + reg_val = interval & IRDMA_GLINT_RATE_INTERVAL; + reg_val |= FIELD_PREP(IRDMA_GLINT_RATE_INTRL_ENA, 1); + } + writel(reg_val, dev->hw_regs[IRDMA_GLINT_RATE] + idx); +} + +#endif +/** + * irdma_cfg_aeq- Configure AEQ interrupt + * @dev: pointer to the device structure + * @idx: vector index + * @enable: True to enable, False disables + */ +void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable) +{ + u32 reg_val; + + reg_val = FIELD_PREP(IRDMA_PFINT_AEQCTL_CAUSE_ENA, enable) | + FIELD_PREP(IRDMA_PFINT_AEQCTL_MSIX_INDX, idx) | + FIELD_PREP(IRDMA_PFINT_AEQCTL_ITR_INDX, IRDMA_IDX_NOITR); + + writel(reg_val, dev->hw_regs[IRDMA_PFINT_AEQCTL]); +} + +/** + * sc_vsi_update_stats - Update statistics + * @vsi: sc_vsi instance to update + */ +void sc_vsi_update_stats(struct irdma_sc_vsi *vsi) +{ + struct irdma_dev_hw_stats *hw_stats = &vsi->pestat->hw_stats; + struct irdma_gather_stats *gather_stats = + vsi->pestat->gather_info.gather_stats_va; + struct irdma_gather_stats *last_gather_stats = + vsi->pestat->gather_info.last_gather_stats_va; + const struct irdma_hw_stat_map *map = vsi->dev->hw_stats_map; + u16 max_stat_idx = vsi->dev->hw_attrs.max_stat_idx; + u16 i; + + if (vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + for (i = 0; i < max_stat_idx; i++) { + u16 idx = map[i].byteoff / sizeof(u64); + + hw_stats->stats_val[i] = gather_stats->val[idx]; + } + return; + } + + irdma_update_stats(hw_stats, gather_stats, last_gather_stats, + map, max_stat_idx); +} + +/** + * irdma_wait_pe_ready - Check if firmware is ready + * @dev: provides access to registers + */ +static int irdma_wait_pe_ready(struct irdma_sc_dev *dev) +{ + u32 statuscpu0; + u32 statuscpu1; + u32 statuscpu2; + u32 retrycount = 0; + + do { + statuscpu0 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS0]); + statuscpu1 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS1]); + statuscpu2 = readl(dev->hw_regs[IRDMA_GLPE_CPUSTATUS2]); + if (statuscpu0 == 0x80 && statuscpu1 == 0x80 && + statuscpu2 == 0x80) + return 0; + mdelay(1000); + } while (retrycount++ < dev->hw_attrs.max_pe_ready_count); + return -1; +} + +/** + * irdma_set_attr_from_fragcnt + * @dev: Device pointer + * @max_fragcnt: maximum fragment count + * + * configure device attributes given a fragment count limit + */ +int irdma_set_attr_from_fragcnt(struct irdma_sc_dev *dev, u8 max_fragcnt) +{ + int ret; + u32 max_inline; + u16 max_wqesz, max_quanta_per_wr; + + if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + return -EOPNOTSUPP; + + /* Compute the max wqe block size applicable to both queues */ + ret = irdma_fragcnt_to_wqesize_rq(max_fragcnt + 1, &max_wqesz); + if (ret) + return ret; + + /* auto-correct max inline we support to fit in the computed max wqe block */ + max_inline = dev->hw_attrs.uk_attrs.max_hw_inline; + switch (max_wqesz) { + case 32: + if (max_inline > 8) + max_inline = 8; + break; + case 64: + if (max_inline > 39) + max_inline = 39; + break; + case 128: + if (max_inline > 101) + max_inline = 101; + break; + case 256: + default: + break; + } + + max_quanta_per_wr = max_wqesz / IRDMA_QP_WQE_MIN_SIZE; + dev->hw_attrs.uk_attrs.max_hw_wq_frags = max_fragcnt; + dev->hw_attrs.uk_attrs.max_hw_read_sges = max_fragcnt; + dev->hw_attrs.uk_attrs.max_hw_inline = max_inline; + dev->hw_attrs.max_qp_wr = IRDMA_MAX_QP_WRS(max_quanta_per_wr); + + return 0; +} + +static inline void irdma_sc_init_hw(struct irdma_sc_dev *dev) +{ + switch (dev->hw_attrs.uk_attrs.hw_rev) { + case IRDMA_GEN_1: + i40iw_init_hw(dev); + break; + case IRDMA_GEN_2: + icrdma_init_hw(dev); + break; + case IRDMA_GEN_3: + case IRDMA_GEN_4: + ig3rdma_init_hw(dev); + break; + } +} + +/** + * irdma_sc_dev_init - Initialize control part of device + * @dev: Device pointer + * @info: Device init info + */ +int irdma_sc_dev_init(struct irdma_sc_dev *dev, struct irdma_device_init_info *info) +{ + u32 val; + int ret_code = 0; + u8 db_size; + + INIT_LIST_HEAD(&dev->cqp_cmd_head); /* for CQP command backlog */ + mutex_init(&dev->ws_mutex); + dev->hmc_fn_id = info->hmc_fn_id; + dev->num_vfs = info->max_vfs; + dev->fpm_query_buf_pa = info->fpm_query_buf_pa; + dev->fpm_query_buf = info->fpm_query_buf; + dev->fpm_commit_buf_pa = info->fpm_commit_buf_pa; + dev->fpm_commit_buf = info->fpm_commit_buf; + dev->hw = info->hw; + dev->hw->hw_addr = info->bar0; + dev->protocol_used = info->protocol_used; + /* Setup the hardware limits, hmc may limit further */ + dev->hw_attrs.min_hw_qp_id = IRDMA_MIN_IW_QP_ID; + dev->hw_attrs.min_hw_srq_id = IRDMA_MIN_IW_SRQ_ID; + dev->hw_attrs.min_hw_aeq_size = IRDMA_MIN_AEQ_ENTRIES; + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) + dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES_GEN_3; + else + dev->hw_attrs.max_hw_aeq_size = IRDMA_MAX_AEQ_ENTRIES; + dev->hw_attrs.min_hw_ceq_size = IRDMA_MIN_CEQ_ENTRIES; + dev->hw_attrs.max_hw_ceq_size = IRDMA_MAX_CEQ_ENTRIES; + dev->hw_attrs.uk_attrs.min_hw_cq_size = IRDMA_MIN_CQ_SIZE; + dev->hw_attrs.uk_attrs.max_hw_cq_size = IRDMA_MAX_CQ_SIZE; + dev->hw_attrs.max_hw_outbound_msg_size = IRDMA_MAX_OUTBOUND_MSG_SIZE; + dev->hw_attrs.max_mr_size = IRDMA_MAX_MR_SIZE; + dev->hw_attrs.max_hw_inbound_msg_size = IRDMA_MAX_INBOUND_MSG_SIZE; + dev->hw_attrs.uk_attrs.max_hw_inline = IRDMA_MAX_INLINE_DATA_SIZE; + dev->hw_attrs.max_hw_wqes = IRDMA_MAX_WQ_ENTRIES; + dev->hw_attrs.max_qp_wr = IRDMA_MAX_QP_WRS(IRDMA_MAX_QUANTA_PER_WR); + + dev->hw_attrs.uk_attrs.max_hw_rq_quanta = IRDMA_QP_SW_MAX_RQ_QUANTA; + dev->hw_attrs.uk_attrs.max_hw_wq_quanta = IRDMA_QP_SW_MAX_WQ_QUANTA; + dev->hw_attrs.max_hw_pds = IRDMA_MAX_PDS; + dev->hw_attrs.max_hw_ena_vf_count = IRDMA_MAX_PE_ENA_VF_COUNT; + + dev->hw_attrs.max_pe_ready_count = 14; + dev->hw_attrs.max_done_count = IRDMA_DONE_COUNT; + dev->hw_attrs.max_sleep_count = IRDMA_SLEEP_COUNT; + dev->hw_attrs.max_cqp_compl_wait_time_ms = CQP_COMPL_WAIT_TIME_MS; + + if (!dev->privileged) { + ret_code = irdma_vchnl_req_get_hmc_fcn(dev); + if (ret_code) { + ibdev_dbg(to_ibdev(dev), + "DEV: Get HMC function ret = %d\n", + ret_code); + + return ret_code; + } + } + + spin_lock_init(&dev->vc_dev_lock); + irdma_sc_init_hw(dev); + + if (dev->privileged) { + if (irdma_wait_pe_ready(dev)) + return -ETIMEDOUT; + + val = readl(dev->hw_regs[IRDMA_GLPCI_LBARCTRL]); + db_size = (u8)FIELD_GET(IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE, val); + if (db_size != IRDMA_PE_DB_SIZE_4M && + db_size != IRDMA_PE_DB_SIZE_8M) { + ibdev_dbg(to_ibdev(dev), + "DEV: RDMA PE doorbell is not enabled in CSR val 0x%x db_size=%d\n", + val, db_size); + return -ENODEV; + } + } else if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + ret_code = irdma_vchnl_req_get_reg_layout(dev); + if (ret_code) + ibdev_dbg(to_ibdev(dev), + "DEV: Get Register layout failed ret = %d\n", + ret_code); + } + + return ret_code; +} + +/** + * irdma_stat_val - Extract HW counter value from statistics buffer + * @stats_val: pointer to statistics buffer + * @byteoff: byte offset of counter value in the buffer (8B-aligned) + * @bitoff: bit offset of counter value within 8B entry + * @bitmask: maximum counter value (e.g. 0xffffff for 24-bit counter) + */ +static inline u64 irdma_stat_val(const u64 *stats_val, u16 byteoff, + u8 bitoff, u64 bitmask) +{ + u16 idx = byteoff / sizeof(*stats_val); + + return (stats_val[idx] >> bitoff) & bitmask; +} + +/** + * irdma_stat_delta - Calculate counter delta + * @new_val: updated counter value + * @old_val: last counter value + * @max_val: maximum counter value (e.g. 0xffffff for 24-bit counter) + */ +static inline u64 irdma_stat_delta(u64 new_val, u64 old_val, u64 max_val) +{ + if (new_val >= old_val) + return new_val - old_val; + else + /* roll-over case */ + return max_val - old_val + new_val + 1; +} + +/** + * irdma_update_stats - Update statistics + * @hw_stats: hw_stats instance to update + * @gather_stats: updated stat counters + * @last_gather_stats: last stat counters + * @map: HW stat map (hw_stats => gather_stats) + * @max_stat_idx: number of HW stats + */ +void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats, + struct irdma_gather_stats *gather_stats, + struct irdma_gather_stats *last_gather_stats, + const struct irdma_hw_stat_map *map, + u16 max_stat_idx) +{ + u64 *stats_val = hw_stats->stats_val; + u16 i; + + for (i = 0; i < max_stat_idx; i++) { + u64 new_val = irdma_stat_val(gather_stats->val, + map[i].byteoff, map[i].bitoff, + map[i].bitmask); + u64 last_val = irdma_stat_val(last_gather_stats->val, + map[i].byteoff, map[i].bitoff, + map[i].bitmask); + + stats_val[i] += irdma_stat_delta(new_val, last_val, + map[i].bitmask); + } + + memcpy(last_gather_stats, gather_stats, + sizeof(*last_gather_stats)); +} + diff --git a/drivers/intel/irdma-1.14.33/src/irdma/debugfs.c b/drivers/intel/irdma-1.14.33/src/irdma/debugfs.c new file mode 100644 index 000000000..dd9c143f0 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/debugfs.c @@ -0,0 +1,1353 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include +#include +#include + +#include "main.h" + +#ifdef CONFIG_DEBUG_FS +static const char irdma_driver_name[] = "irdma"; +static struct dentry *irdma_dbg_root; +static char cmd_buf[64]; + +/* QP subcommand */ +#define QP_ACTIVE 1 +#define QP_INFO 2 +#define QP_Q2 3 +#define QP_HOST_CTX 4 +#define QP_CHIP_CTX 5 +#define QP_CHIP_RAW 6 +#define QP_CHIP_REG 7 + +#define DUMP_HMC_INFO 1 +#define DUMP_HMC_INDEXES 2 +#define DUMP_HMC_OBJ_INFO 4 +#define DUMP_HMC_SD 8 +#define DUMP_HMC_ALL 0xf + +#define OFFSET_MASK_4K 0x0000000000000fffl + +static char *irdma_dbg_dump_buf; +static size_t irdma_dbg_dump_data_len; +static size_t irdma_dbg_dump_buf_len; +static u32 cmdnew; +static u32 cmddone; +#define BUF_ADDR_SIZE 17 /* address plus space */ +#define BUF_DATA_ASCII_SIZE (32 * 3 + 2 + 32 + 1) /* data plus ASCII */ +#define IRDMA_DUMP_BUF_SIZE 16384 +#define IRDMA_DUMP_BUF_HALF_FULL (IRDMA_DUMP_BUF_SIZE / 2) + +struct hmc_find { + dma_addr_t paddr; + bool fnd; + dma_addr_t bp_pa; + bool in_vf; + u32 vf_id; + int sd_indx; + bool paged; + bool in_pd_itself; + int pd_indx; + u64 hmc_addr; + bool obj_info_fnd; + enum irdma_hmc_rsrc_type obj_type; + int obj_indx; +}; + +/** + * dbg_vsnprintf - + * @fmt: print formatting string + */ +static void dbg_vsnprintf(char *fmt, ...) __attribute__ ((format(gnu_printf, 1, 2))); +static void dbg_vsnprintf(char *fmt, ...) +{ + int cnt; + va_list argp; + + va_start(argp, fmt); + cnt = vsnprintf(irdma_dbg_dump_buf + irdma_dbg_dump_data_len, + irdma_dbg_dump_buf_len - irdma_dbg_dump_data_len, + fmt, argp); + va_end(argp); + + irdma_dbg_dump_data_len += cnt; +} + +/** + * dump_help - + */ +static void dump_help(void) +{ + dbg_vsnprintf("Dump commands:\n"); + dbg_vsnprintf(" sw-stats\n"); + dbg_vsnprintf(" hw-stats\n"); + dbg_vsnprintf(" qp chip_ctx\n"); + dbg_vsnprintf(" qp chip_raw\n"); + dbg_vsnprintf(" qp active is a qp number or 'all'\n"); + dbg_vsnprintf(" qp info\n"); + dbg_vsnprintf(" cq is a cq number or 'all'\n"); + cmddone = true; +} + +/** + * irdma_dbg_save_ucontext - + * @iwdev: device + * @ucontext: user context + */ +void irdma_dbg_save_ucontext(struct irdma_device *iwdev, + struct irdma_ucontext *ucontext) +{ + struct irdma_handler *hdl; + unsigned long flags; + + hdl = iwdev->hdl; + + spin_lock_irqsave(&hdl->uctx_list_lock, flags); + list_add_tail(&ucontext->uctx_list, &hdl->ucontext_list); + spin_unlock_irqrestore(&hdl->uctx_list_lock, flags); +} + +/** + * irdma_dbg_free_ucontext - + * @ucontext: user context + */ +void irdma_dbg_free_ucontext(struct irdma_ucontext *ucontext) +{ + struct irdma_handler *hdl; + unsigned long flags; + + hdl = ucontext->iwdev->hdl; + + spin_lock_irqsave(&hdl->uctx_list_lock, flags); + list_del(&ucontext->uctx_list); + spin_unlock_irqrestore(&hdl->uctx_list_lock, flags); +} + +/** + * find_next_rsrc - Find next free resource ID + * @rf: RDMA PCI function + * @rsrc_array: resource array + * @max_rsrc: max num resources + * @next: next id to search + */ +static int find_next_rsrc(struct irdma_pci_f *rf, + unsigned long *rsrc_array, + u32 max_rsrc, + u32 next) +{ + u32 rsrc_num; + unsigned long flags; + + spin_lock_irqsave(&rf->rsrc_lock, flags); + rsrc_num = find_next_bit(rsrc_array, max_rsrc, next); + spin_unlock_irqrestore(&rf->rsrc_lock, flags); + return (rsrc_num < max_rsrc) ? rsrc_num : -2; +} + +/** + * find_next_qp_num - + * @rf: RDMA PCI function + * @qp_id: QP ID + */ +static int find_next_qp_num(struct irdma_pci_f *rf, int qp_id) +{ + do { + ++qp_id; + if ((qp_id == 0) || (qp_id == 1)) + qp_id = 2; + qp_id = find_next_rsrc(rf, rf->allocated_qps, + rf->max_qp, qp_id); + if (qp_id < 0) + break; + } while (!rf->qp_table[qp_id]); + + return qp_id; +} + +/** + * find_next_cq_num - + * @rf: RDMA PCI function + * @cq_id: CQ ID + */ +static long find_next_cq_num(struct irdma_pci_f *rf, long cq_id) +{ + do { + ++cq_id; + if (cq_id < 3 || + cq_id >= rf->cqp.sc_cqp.dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt) + cq_id = 3; + cq_id = find_next_rsrc(rf, rf->allocated_cqs, + rf->max_cq, cq_id); + if (cq_id < 0) + break; + + } while (!rf->cq_table[cq_id]); + + return cq_id; +} + +/** + * dump_qp_shared - + * @qp: QP pointer + */ +static void dump_qp_shared(struct irdma_qp *qp) +{ + struct irdma_sc_qp *qpsh = &qp->sc_qp; + struct irdma_qp_uk *qpuk = &qpsh->qp_uk; + + dbg_vsnprintf(" sq_ring.head: 0x%x tail: 0x%x size: 0x%x\n", + qpuk->sq_ring.head, qpuk->sq_ring.tail, + qpuk->sq_ring.size); + dbg_vsnprintf(" rq_ring.head: 0x%x tail: 0x%x size: 0x%x\n", + qpuk->rq_ring.head, qpuk->rq_ring.tail, + qpuk->rq_ring.size); + dbg_vsnprintf(" qp_id: 0x%x\n", qpuk->qp_id); + dbg_vsnprintf(" sq_size: 0x%x\n", qpuk->sq_size); + dbg_vsnprintf(" rq_size: 0x%x\n", qpuk->rq_size); + dbg_vsnprintf(" swqe_polarity: 0x%x\n", qpuk->swqe_polarity); + dbg_vsnprintf(" rwqe_polarity: 0x%x\n", qpuk->rwqe_polarity); + dbg_vsnprintf(" rq_wqe_size: 0x%x\n", qpuk->rq_wqe_size); + dbg_vsnprintf(" rq_wqe_size_multiplier: 0x%x\n", + qpuk->rq_wqe_size_multiplier); + dbg_vsnprintf(" max_sq_frag_cnt: 0x%x\n", qpuk->max_sq_frag_cnt); + dbg_vsnprintf(" max_rq_frag_cnt: 0x%x\n", qpuk->max_rq_frag_cnt); + + dbg_vsnprintf(" qs_handle: 0x%x\n", qpsh->qs_handle); + dbg_vsnprintf(" exception_lan_q: 0x%x\n", + qp->iwdev->vsi.exception_lan_q); + dbg_vsnprintf(" sq_tph_val: 0x%x\n", qpsh->sq_tph_val); + dbg_vsnprintf(" rq_tph_val: 0x%x\n", qpsh->rq_tph_val); + dbg_vsnprintf(" sq_tph_en: 0x%x\n", qpsh->sq_tph_en); + dbg_vsnprintf(" rq_tph_en: 0x%x\n", qpsh->rq_tph_en); + dbg_vsnprintf(" rcv_tph_en: 0x%x\n", qpsh->rcv_tph_en); + dbg_vsnprintf(" xmit_tph_en: 0x%x\n", qpsh->xmit_tph_en); + + dbg_vsnprintf(" virtual_map: 0x%x\n", qpsh->virtual_map); + dbg_vsnprintf(" flush_sq: 0x%x\n", qpsh->flush_sq); + dbg_vsnprintf(" flush_rq: 0x%x\n", qpsh->flush_rq); + dbg_vsnprintf(" qp_type: 0x%x\n", qpsh->qp_uk.qp_type); + dbg_vsnprintf(" hw_sq_size: 0x%x\n", qpsh->hw_sq_size); + dbg_vsnprintf(" hw_rq_size: 0x%x\n", qpsh->hw_rq_size); +} + +/** + * dump_qp_info - + * @qp: QP pointer + */ +static void dump_qp_info(struct irdma_qp *qp) +{ + dbg_vsnprintf("struct irdma_qp\n"); + + dump_qp_shared(qp); + + dbg_vsnprintf(" refcount: 0x%x\n", refcount_read(&qp->refcnt)); + dbg_vsnprintf(" ibqp_state: 0x%x\n", qp->ibqp_state); + dbg_vsnprintf(" iwarp_state: 0x%x\n", qp->iwarp_state); + dbg_vsnprintf(" qp_mem_size: 0x%x\n", qp->qp_mem_size); + dbg_vsnprintf(" last_aeq: 0x%x\n", qp->last_aeq); + dbg_vsnprintf(" close_timer_started: 0x%x\n", + qp->close_timer_started.counter); + dbg_vsnprintf(" qp_mem_size: 0x%x\n", qp->qp_mem_size); + dbg_vsnprintf(" active_conn: %d\n", qp->active_conn); + dbg_vsnprintf(" user_mode: %d\n", qp->user_mode); + dbg_vsnprintf(" hte_added: %d\n", qp->hte_added); + dbg_vsnprintf(" flush_issued: %d\n", qp->flush_issued); + dbg_vsnprintf(" destroy_pending: %d\n", qp->sc_qp.qp_uk.destroy_pending); + dbg_vsnprintf(" sig_all: %d\n", qp->sig_all); + dbg_vsnprintf(" pau_mode: %d\n", qp->pau_mode); + dbg_vsnprintf(" term_sq_flush_code: 0x%x\n", qp->term_sq_flush_code); + dbg_vsnprintf(" term_rq_flush_code: 0x%x\n", qp->term_rq_flush_code); + dbg_vsnprintf(" hw_iwarp_state: %d\n", qp->hw_iwarp_state); + dbg_vsnprintf(" hw_tcp_state: %d\n", qp->hw_tcp_state); +} + +#if 0 +/** + * dump_qp_ctx - + * @qp: QP pointer + */ +static void dump_qp_ctx(struct irdma_qp *qp) +{ + u64 *hwctx = qp->sc_qp.hw_host_ctx; + size_t lendumped = 0; + u32 val; + u64 val64; + u8 qp_type = qp->sc_qp.qp_type; + + dump_to_buf((char *)qp->sc_qp.hw_host_ctx, 256, 0, 32, 8, + false, &lendumped); + + dbg_vsnprintf("host_context 0x%p\n", qp->sc_qp.hw_host_ctx); + if (qp_type == IRDMA_CQ_TYPE_IWARP) + dbg_vsnprintf(" iwarp_rdmap_ver: 0x%llx\n", RS_64(hwctx[0], IRDMAQPC_RDMAP_VER)); + else + dbg_vsnprintf(" roce_tver_ver: 0x%llx\n", RS_64(hwctx[0], IRDMAQPC_ROCE_TVER)); + dbg_vsnprintf(" push_mode_ena: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_PMENA)); + dbg_vsnprintf(" push_page_index: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_PPIDX)); + dbg_vsnprintf(" SQ_THP_en: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_SQTPHEN)); + dbg_vsnprintf(" RQ_THP_en: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_RQTPHEN)); + if (qp_type == IRDMA_CQ_TYPE_IWARP) { + dbg_vsnprintf(" XMIT_THP_en: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_XMITTPHEN)); + dbg_vsnprintf(" RCV_THP_en: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_RCVTPHEN)); + dbg_vsnprintf(" dupack_thresh: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_DUPACK_THRESH)); + dbg_vsnprintf(" drop_out_of_order_seg: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_DROPOOOSEG)); + dbg_vsnprintf(" ECN_ena: no constants defined\n"); + dbg_vsnprintf(" limit: 0x%llx\n", RS_64(hwctx[0], IRDMAQPC_LIMIT)); + } + dbg_vsnprintf(" RQ_WQE_Size: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_RQWQESIZE)); + dbg_vsnprintf(" timestamp: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_TIMESTAMP)); + dbg_vsnprintf(" use_srq: 0x%llx\n", RS_64(hwctx[0], IRDMAQPC_USESRQ)); + dbg_vsnprintf(" Insert VLAN Tag: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_INSERTVLANTAG)); + if (qp_type == IRDMA_CQ_TYPE_IWARP) { + dbg_vsnprintf(" NoNagle: 0x%llx\n", RS_64(hwctx[0], IRDMAQPC_NONAGLE)); + dbg_vsnprintf(" iwarp_ddp_ver: 0x%llx\n", + RS_64(hwctx[0], IRDMAQPC_DDP_VER)); + } + dbg_vsnprintf(" IPv4: 0x%llx\n", RS_64(hwctx[0], IRDMAQPC_IPV4)); + + /* Offset 8 */ + dbg_vsnprintf(" SQ_Address: 0x%llx\n", + RS_64(hwctx[1], IRDMAQPC_SQADDR)); + + /* Offset 16 */ + dbg_vsnprintf(" RQ_Address: 0x%llx\n", + RS_64(hwctx[2], IRDMAQPC_RQADDR)); + + /* Offset 24 */ + dbg_vsnprintf(" Dest Port Number: 0x%llx (%lld)\n", + RS_64(hwctx[3], IRDMAQPC_DESTPORTNUM), + RS_64(hwctx[3], IRDMAQPC_DESTPORTNUM)); + dbg_vsnprintf(" Source Port Number: 0x%llx (%lld)\n", + RS_64(hwctx[3], IRDMAQPC_SRCPORTNUM), + RS_64(hwctx[3], IRDMAQPC_SRCPORTNUM)); + dbg_vsnprintf(" Traffic Class or TOS: 0x%llx\n", + RS_64(hwctx[3], IRDMAQPC_TOS)); + dbg_vsnprintf(" avoid_stretch_ack: 0x%llx\n", + RS_64(hwctx[3], IRDMAQPC_AVOIDSTRETCHACK)); + dbg_vsnprintf(" SQ Size: 0x%llx\n", RS_64(hwctx[3], IRDMAQPC_SQSIZE)); + dbg_vsnprintf(" RQ Size: 0x%llx\n", RS_64(hwctx[3], IRDMAQPC_RQSIZE)); + dbg_vsnprintf(" Hop Limit or TTL: 0x%llx\n", + RS_64(hwctx[3], IRDMAQPC_TTL)); + + /* Offset 32 */ + val = be32_to_cpu(RS_64(hwctx[4], IRDMAQPC_DESTIPADDR2)); + dbg_vsnprintf(" Dest_IP_Address_2: %pI4\n", &val); + + val = be32_to_cpu(RS_64(hwctx[4], IRDMAQPC_DESTIPADDR3)); + dbg_vsnprintf(" Dest_IP_Address_3: %pI4\n", &val); + + /* Offset 40 */ + val = be32_to_cpu(RS_64(hwctx[5], IRDMAQPC_DESTIPADDR0)); + dbg_vsnprintf(" Dest_IP_Address_0: %pI4\n", &val); + + val = be32_to_cpu(RS_64(hwctx[5], IRDMAQPC_DESTIPADDR1)); + dbg_vsnprintf(" Dest_IP_Address_1: %pI4\n", &val); + + /* Offset 48 */ + dbg_vsnprintf(" ARP Index: 0x%llx\n", + RS_64(hwctx[6], IRDMAQPC_ARPIDX)); + dbg_vsnprintf(" VLAN Tag: 0x%llx\n", + RS_64(hwctx[6], IRDMAQPC_VLANTAG)); + dbg_vsnprintf(" snd_mss: 0x%llx\n", RS_64(hwctx[6], IRDMAQPC_SNDMSS)); + + /* Offset 56 */ + dbg_vsnprintf(" pd_index: 0x%llx\n", + RS_64(hwctx[7], IRDMAQPC_PDIDX) | RS_64(hwctx[0], + IRDMAQPC_PDIDXHI)); + + if (qp_type == IRDMA_CQ_TYPE_IWARP) { + dbg_vsnprintf(" Snd_wscale: 0x%llx\n", + RS_64(hwctx[7], IRDMAQPC_SNDSCALE)); + dbg_vsnprintf(" Rcv_wscale: 0x%llx\n", + RS_64(hwctx[7], IRDMAQPC_RCVSCALE)); + dbg_vsnprintf(" TCP_state: 0x%llx\n", + RS_64(hwctx[7], IRDMAQPC_TCPSTATE)); + dbg_vsnprintf(" ignore_tcp_uns_options: 0x%llx\n", + RS_64(hwctx[7], IRDMAQPC_IGNORE_TCP_UNS_OPT)); + dbg_vsnprintf(" ignore_tcp_options: 0x%llx\n", + RS_64(hwctx[7], IRDMAQPC_IGNORE_TCP_OPT)); + dbg_vsnprintf(" Flow Label: 0x%llx\n", + RS_64(hwctx[7], IRDMAQPC_FLOWLABEL)); + + /* Offset 72 */ + dbg_vsnprintf(" timestamp_age: 0x%llx\n", + RS_64(hwctx[9], IRDMAQPC_TIMESTAMP_AGE)); + dbg_vsnprintf(" timestamp_recent: 0x%llx\n", + RS_64(hwctx[9], IRDMAQPC_TIMESTAMP_RECENT)); + + /* Offset 80 */ + dbg_vsnprintf(" snd_wnd: 0x%llx\n", RS_64(hwctx[10], IRDMAQPC_SNDWND)); + dbg_vsnprintf(" snd_nxt: 0x%llx\n", RS_64(hwctx[10], IRDMAQPC_SNDNXT)); + + /* Offset 88 */ + dbg_vsnprintf(" rcv_wnd: 0x%llx\n", RS_64(hwctx[11], IRDMAQPC_RCVWND)); + dbg_vsnprintf(" rcv_nxt: 0x%llx\n", RS_64(hwctx[11], IRDMAQPC_RCVNXT)); + + /* Offset 96 */ + dbg_vsnprintf(" snd_una: 0x%llx\n", RS_64(hwctx[12], IRDMAQPC_SNDUNA)); + dbg_vsnprintf(" snd_max: 0x%llx\n", RS_64(hwctx[12], IRDMAQPC_SNDMAX)); + + /* Offset 104 */ + dbg_vsnprintf(" rtt_var: 0x%llx\n", RS_64(hwctx[13], IRDMAQPC_RTTVAR)); + dbg_vsnprintf(" srtt: 0x%llx\n", RS_64(hwctx[13], IRDMAQPC_SRTT)); + } else { + dbg_vsnprintf(" pkey: 0x%llx\n", RS_64(hwctx[7], IRDMAQPC_PKEY)); + dbg_vsnprintf(" ack_credits: 0x%llx\n", RS_64(hwctx[7], IRDMAQPC_ACKCREDITS)); + dbg_vsnprintf(" qkey: 0x%llx\n", RS_64(hwctx[8], IRDMAQPC_QKEY)); + dbg_vsnprintf(" Dest_QPN: 0x%llx\n", RS_64(hwctx[8], IRDMAQPC_DESTQP)); + dbg_vsnprintf(" Isn: 0x%llx\n", RS_64(hwctx[10], IRDMAQPC_ISN)); + dbg_vsnprintf(" psn_nxt: 0x%llx\n", RS_64(hwctx[10], IRDMAQPC_QKEY)); + dbg_vsnprintf(" epsn: 0x%llx\n", RS_64(hwctx[11], IRDMAQPC_EPSN)); + dbg_vsnprintf(" psn_una: 0x%llx\n", RS_64(hwctx[12], IRDMAQPC_PSNUNA)); + dbg_vsnprintf(" psn_max: 0x%llx\n", RS_64(hwctx[12], IRDMAQPC_PSNMAX)); + dbg_vsnprintf(" ss_thresh: 0x%llx\n", RS_64(hwctx[14], IRDMAQPC_SSTHRESH)); + } + /* Offset 112 */ + dbg_vsnprintf(" cwnd: 0x%llx\n", RS_64(hwctx[14], IRDMAQPC_CWND)); + + if (qp_type == IRDMA_CQ_TYPE_IWARP) { + /* Offset 120 */ + dbg_vsnprintf(" snd_wl2: 0x%llx\n", RS_64(hwctx[15], IRDMAQPC_SNDWL2)); + dbg_vsnprintf(" snd_wl1: 0x%llx\n", RS_64(hwctx[15], IRDMAQPC_SNDWL1)); + + /* Offset 128 */ + dbg_vsnprintf(" rexmit_thresh: 0x%llx\n", + RS_64(hwctx[16], IRDMAQPC_REXMIT_THRESH)); + dbg_vsnprintf(" max_snd_window: 0x%llx\n", + RS_64(hwctx[16], IRDMAQPC_MAXSNDWND)); + } + /* Offset 136 */ + dbg_vsnprintf(" RxCmpQueueNum: 0x%llx\n", + RS_64(hwctx[17], IRDMAQPC_RXCQNUM)); + dbg_vsnprintf(" TxCmpQueueNum: 0x%llx\n", + RS_64(hwctx[17], IRDMAQPC_TXCQNUM)); + + /* Offset 144 */ + if (qp_type == IRDMA_CQ_TYPE_IWARP) + dbg_vsnprintf(" Q2_Address: 0x%llx\n", RS_64(hwctx[18], IRDMAQPC_Q2ADDR); + dbg_vsnprintf(" Stats_instance_Index: 0x%llx\n", RS_64(hwctx[18], IRDMAQPC_STAT_INDEX)); + + /* Offset 152 */ + dbg_vsnprintf(" L2TAG2: no constants defined\n"); + dbg_vsnprintf(" last_byte_sent: 0x%llx\n", RS_64(hwctx[19], IRDMAQPC_LASTBYTESENT)); + val64 = RS_64(hwctx[19], IRDMAQPC_MACADDRESS); + dbg_vsnprintf(" src_MAC_Address: 0x%pM\n", &val64); + + if (qp_type == IRDMA_CQ_TYPE_IWARP) { + /* Offset 160 */ + dbg_vsnprintf(" snd_mrk_offset: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_SNDMARKOFFSET)); + dbg_vsnprintf(" rcv_mrk_offset: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_RCVMARKOFFSET)); + + dbg_vsnprintf(" rcv_no_mpa_crc: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_RCVNOMPACRC)); + dbg_vsnprintf(" assume_aligned_hdrs: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_ALIGNHDRS)); + dbg_vsnprintf(" Receive Markers: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_RCVMARKERS)); + dbg_vsnprintf(" iWARP Mode: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_IWARPMODE)); + } + dbg_vsnprintf(" AdjustForLSMM: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_ADJUSTFORLSMM)); + dbg_vsnprintf(" PrivilegedEnable: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_PRIVEN)); + dbg_vsnprintf(" FastRegisterEnable: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_FASTREGEN)); + dbg_vsnprintf(" BindEnable: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_BINDEN)); + dbg_vsnprintf(" Send Markers: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_SNDMARKERS)); + dbg_vsnprintf(" rdmard_ok: 0x%llx\n", RS_64(hwctx[20], IRDMAQPC_RDOK)); + dbg_vsnprintf(" rdmawr_rdresp_ok: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_WRRDRSPOK)); + dbg_vsnprintf(" IRD_Size: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_IRDSIZE)); + dbg_vsnprintf(" ORD_Size: 0x%llx\n", + RS_64(hwctx[20], IRDMAQPC_ORDSIZE)); + + /* Offset 168 */ + dbg_vsnprintf(" Queue Pair Completion Context: 0x%llx\n", + RS_64(hwctx[21], IRDMAQPC_QPCOMPCTX)); + + /* Offset 176 */ + if (qp_type == IRDMA_CQ_TYPE_IWARP) + dbg_vsnprintf(" Exception_LAN_Queue: 0x%llx\n", RS_64(hwctx[22], IRDMAQPC_EXCEPTION_LAN_QUEUE)); + dbg_vsnprintf(" QS_Handle: 0x%llx\n", + RS_64(hwctx[22], IRDMAQPC_QSHANDLE)); + dbg_vsnprintf(" RQ_TPH_val: 0x%llx\n", + RS_64(hwctx[22], IRDMAQPC_RQTPHVAL)); + dbg_vsnprintf(" SQ_TPH_val: 0x%llx\n", + RS_64(hwctx[22], IRDMAQPC_SQTPHVAL)); + + /* Offset 184 */ + val = be32_to_cpu(RS_64(hwctx[23], IRDMAQPC_LOCAL_IPADDR2)); + dbg_vsnprintf(" Local_IP_Address_2: %pI4\n", &val); + + val = be32_to_cpu(RS_64(hwctx[23], IRDMAQPC_LOCAL_IPADDR3)); + dbg_vsnprintf(" Local_IP_Address_3: %pI4\n", &val); + + /* Offset 192 */ + val = be32_to_cpu(RS_64(hwctx[24], IRDMAQPC_LOCAL_IPADDR0)); + dbg_vsnprintf(" Local_IP_Address_0: %pI4\n", &val); + + val = be32_to_cpu(RS_64(hwctx[24], IRDMAQPC_LOCAL_IPADDR1)); + dbg_vsnprintf(" Local_IP_Address_1: %pI4\n", &val); +} +#endif + +/** + * dump_qp - + * @rf: RDMA PCI function + * @qp_id: QP ID + * @subtype: QP info type + */ +static void dump_qp(struct irdma_pci_f *rf, u32 qp_id, u32 subtype) +{ + struct irdma_qp *iwqp = NULL; + + if ((qp_id >= 2) && (qp_id < rf->max_qp)) + iwqp = rf->qp_table[qp_id]; + + if (!iwqp) { + dbg_vsnprintf("QP %d is not valid\n", qp_id); + return; + } + + dbg_vsnprintf("QP %d ibqp_state=0x%x warp_state=0x%x\n", qp_id, + iwqp->ibqp_state, iwqp->iwarp_state); + + switch (subtype) { + case QP_INFO: + dump_qp_info(iwqp); + break; + case QP_CHIP_CTX: + dbg_vsnprintf + ("QP %d context will be dumped to /var/log/messages\n", + qp_id); + irdma_upload_qp_context(iwqp, 0, 0); + break; + case QP_CHIP_RAW: + dbg_vsnprintf + ("QP %d context will be dumped using regs (no CQP ops) to /var/log/messages\n", + qp_id); + irdma_upload_qp_context(iwqp, 0, 1); + break; + case QP_ACTIVE: + if (!iwqp->user_mode) { + unsigned long flags; + + spin_lock_irqsave(&iwqp->lock, flags); + irdma_print_sq_wqes(&iwqp->sc_qp.qp_uk); + spin_unlock_irqrestore(&iwqp->lock, flags); + } + break; + } +} + +/** + * dump_qp_cmd - + * @rf: RDMA PCI function + * @cbuf: character buffer to dump to + */ +static void dump_qp_cmd(struct irdma_pci_f *rf, char *cbuf) +{ + static int qp_id; + static u32 all; + static u32 subtype = QP_ACTIVE; + char stype[9]; + char qpstr[11]; + int offset; + int rc; + + if (cmdnew) { + if (sscanf(cbuf, "%10s%n", qpstr, &offset) == 0) + return; + + if (strncasecmp(qpstr, "all", 3) == 0) { + all = true; + qp_id = find_next_qp_num(rf, -1); + } else { + all = false; + rc = kstrtoul(qpstr, 10, (long *)&qp_id); + if (rc) + return; + + if ((qp_id == 0) || (qp_id == 1)) + qp_id = -1; + } + + if (sscanf(cbuf + offset, "%8s", stype) == 1) { + if (strncasecmp(stype, "active", 6) == 0) + subtype = QP_ACTIVE; + if (strncasecmp(stype, "info", 5) == 0) + subtype = QP_INFO; + else if (strncasecmp(stype, "q2", 2) == 0) + subtype = QP_Q2; + else if (strncasecmp(stype, "chip_ctx", 8) == 0) + subtype = QP_CHIP_CTX; + else if (strncasecmp(stype, "chip_raw", 8) == 0) + subtype = QP_CHIP_RAW; + else if (strncasecmp(stype, "chip_reg", 8) == 0) + subtype = QP_CHIP_REG; + } + } else { + if (!all) + return; + + qp_id = find_next_qp_num(rf, qp_id); + } + + if (qp_id >= 0) + dump_qp(rf, qp_id, subtype); + else + cmddone = true; +} + +/** + * dump_cq_cmd - + * @rf: RDMA PCI function + * @cbuf: character buffer to read the cmd from + */ +static void dump_cq_cmd(struct irdma_pci_f *rf, const char *cbuf) +{ + static long cq_id; + static bool all; + char cqstr[11]; + int offset; + int rc; + + if (cmdnew) { + if (sscanf(cbuf, "%10s%n", cqstr, &offset) == 0) + return; + + if (strncasecmp(cqstr, "all", 3) == 0) { + all = true; + cq_id = find_next_cq_num(rf, 1); + } else { + all = false; + rc = kstrtoul(cqstr, 0, &cq_id); + if (rc) + return; + + if (cq_id < 3 || + cq_id >= rf->cqp.sc_cqp.dev->hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].max_cnt) { + dbg_vsnprintf("CQ %ld is not valid\n", cq_id); + return; + } + } + } else { + if (!all) + return; + + cq_id = find_next_cq_num(rf, cq_id); + } + + if (cq_id > 2) { + struct irdma_cq *iwcq = rf->cq_table[cq_id]; + + if (iwcq && !iwcq->user_mode) { + unsigned long flags; + + spin_lock_irqsave(&iwcq->lock, flags); + irdma_print_cqes(&iwcq->sc_cq.cq_uk); + spin_unlock_irqrestore(&iwcq->lock, flags); + } + } else { + cmddone = true; + } +} + +/** + * dump_stats_cmd - Dump statistics + * @iwdev: device + */ +static void dump_stats_cmd(struct irdma_device *iwdev) +{ + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_cm_core *cm_core = &iwdev->cm_core; + struct irdma_hmc_pble_rsrc *pble = iwdev->rf->pble_rsrc; + struct irdma_puda_rsrc *ilq = iwdev->vsi.ilq; + struct irdma_puda_rsrc *ieq = iwdev->vsi.ieq; + + dbg_vsnprintf("cm nodes created %lld\n", + cm_core->stats_nodes_created); + dbg_vsnprintf("cm nodes destroyed %lld\n", + cm_core->stats_nodes_destroyed); + dbg_vsnprintf("cm listen called %lld\n", + cm_core->stats_listen_created); + dbg_vsnprintf("cm listen removed %lld\n", + cm_core->stats_listen_destroyed); + dbg_vsnprintf("cm listen nodes created %lld\n", + cm_core->stats_listen_nodes_created); + dbg_vsnprintf("cm listen nodes destroyed %lld\n", + cm_core->stats_listen_nodes_destroyed); + dbg_vsnprintf("cm accepts %lld\n", + cm_core->stats_accepts); + dbg_vsnprintf("cm rejects %lld\n", + cm_core->stats_rejects); + dbg_vsnprintf("cm loopbacks %lld\n", + cm_core->stats_lpbs); + dbg_vsnprintf("cm connect errors %lld\n", + cm_core->stats_connect_errs); + dbg_vsnprintf("cm passive errors %lld\n", + cm_core->stats_passive_errs); + dbg_vsnprintf("cm pkts retrans %lld\n", + cm_core->stats_pkt_retrans); + dbg_vsnprintf("cm backlog drops %lld\n", + cm_core->stats_backlog_drops); + + dbg_vsnprintf("pble direct sds %d\n", + pble->stats_direct_sds); + dbg_vsnprintf("pble paged sds %d\n", + pble->stats_paged_sds); + dbg_vsnprintf("pble alloc ok %lld\n", + pble->stats_alloc_ok); + dbg_vsnprintf("pble alloc fail %lld\n", + pble->stats_alloc_fail); + dbg_vsnprintf("pble alloc freed %lld\n", + pble->stats_alloc_freed); + dbg_vsnprintf("pble lvl1 alloc %lld\n", + pble->stats_lvl1); + dbg_vsnprintf("pble lvl2 alloc %lld\n", + pble->stats_lvl2); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) + dbg_vsnprintf("hugepages registered %d\n", + iwdev->hugepgcnt); +#endif + if (ilq) { + dbg_vsnprintf("ilq packet sent %lld\n", + ilq->stats_pkt_sent); + dbg_vsnprintf("ilq avail buffs %d\n", + ilq->avail_buf_count); + dbg_vsnprintf("ilq alloc buffs %d\n", + ilq->alloc_buf_count); + dbg_vsnprintf("ilq buf alloc fail %lld\n", + ilq->stats_buf_alloc_fail); + dbg_vsnprintf("ilq packet rcvd %lld\n", + ilq->stats_pkt_rcvd); + dbg_vsnprintf("ilq packet rcv error %lld\n", + ilq->stats_rcvd_pkt_err); + } + + if (ieq) { + dbg_vsnprintf("ieq fpdu_processed %lld\n", + ieq->fpdu_processed); + dbg_vsnprintf("ieq bad_seq_num %lld\n", + ieq->bad_seq_num); + dbg_vsnprintf("ieq crc_err %lld\n", + ieq->crc_err); + dbg_vsnprintf("ieq pmode_count %lld\n", + ieq->pmode_count); + dbg_vsnprintf("ieq bad_qp_id(or RoCE pkts) %lld\n\n", + ieq->stats_bad_qp_id); + } + + dbg_vsnprintf("cqp requested ops %llu\n", + dev->cqp->requested_ops); + dbg_vsnprintf("cqp completed ops %llu\n\n", + (u64)atomic64_read(&dev->cqp->completed_ops)); + + /* sorted by cqp op type */ + dbg_vsnprintf("cqp OP_CEQ_DESTROY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_CEQ_DESTROY]); + dbg_vsnprintf("cqp OP_AEQ_DESTROY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_AEQ_DESTROY]); + dbg_vsnprintf("cqp OP_DELETE_ARP_CACHE_ENTRY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_DELETE_ARP_CACHE_ENTRY]); + dbg_vsnprintf("cqp OP_MANAGE_APBVT_ENTRY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MANAGE_APBVT_ENTRY]); + dbg_vsnprintf("cqp OP_CEQ_CREATE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_CEQ_CREATE]); + dbg_vsnprintf("cqp OP_AEQ_CREATE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_AEQ_CREATE]); + dbg_vsnprintf("cqp OP_MANAGE_QHASH_TABLE_ENTRY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY]); + dbg_vsnprintf("cqp OP_QP_MODIFY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_QP_MODIFY]); + dbg_vsnprintf("cqp OP_QP_UPLOAD_CONTEXT %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_QP_UPLOAD_CONTEXT]); + dbg_vsnprintf("cqp OP_CQ_CREATE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_CQ_CREATE]); + dbg_vsnprintf("cqp OP_CQ_DESTROY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_CQ_DESTROY]); + dbg_vsnprintf("cqp OP_QP_CREATE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_QP_CREATE]); + dbg_vsnprintf("cqp OP_QP_DESTROY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_QP_DESTROY]); + dbg_vsnprintf("cqp OP_ALLOC_STAG %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_ALLOC_STAG]); + dbg_vsnprintf("cqp OP_MR_REG_NON_SHARED %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MR_REG_NON_SHARED]); + dbg_vsnprintf("cqp OP_DEALLOC_STAG %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_DEALLOC_STAG]); + dbg_vsnprintf("cqp OP_MW_ALLOC %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MW_ALLOC]); + dbg_vsnprintf("cqp OP_QP_FLUSH_WQES %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_QP_FLUSH_WQES]); + dbg_vsnprintf("cqp OP_ADD_ARP_CACHE_ENTRY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_ADD_ARP_CACHE_ENTRY]); + dbg_vsnprintf("cqp OP_MANAGE_PUSH_PAGE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MANAGE_PUSH_PAGE]); + dbg_vsnprintf("cqp OP_UPDATE_PE_SDS %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_UPDATE_PE_SDS]); + dbg_vsnprintf("cqp OP_MANAGE_HMC_PM_FUNC_TABLE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE]); + dbg_vsnprintf("cqp OP_SUSPEND %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_SUSPEND]); + dbg_vsnprintf("cqp OP_RESUME %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_RESUME]); + dbg_vsnprintf("cqp OP_MANAGE_PBLE_BP %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MANAGE_PBLE_BP]); + dbg_vsnprintf("cqp OP_QUERY_FPM_VAL %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_QUERY_FPM_VAL]); + dbg_vsnprintf("cqp OP_COMMIT_FPM_VAL %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_COMMIT_FPM_VAL]); + dbg_vsnprintf("cqp OP_AH_CREATE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_AH_CREATE]); + dbg_vsnprintf("cqp OP_AH_MODIFY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_AH_MODIFY]); + dbg_vsnprintf("cqp OP_AH_DESTROY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_AH_DESTROY]); + dbg_vsnprintf("cqp OP_MC_CREATE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MC_CREATE]); + dbg_vsnprintf("cqp OP_MC_DESTROY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MC_DESTROY]); + dbg_vsnprintf("cqp OP_MC_MODIFY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_MC_MODIFY]); + dbg_vsnprintf("cqp OP_STATS_ALLOCATE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_STATS_ALLOCATE]); + dbg_vsnprintf("cqp OP_STATS_FREE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_STATS_FREE]); + dbg_vsnprintf("cqp OP_STATS_GATHER %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_STATS_GATHER]); + dbg_vsnprintf("cqp OP_WS_ADD_NODE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_WS_ADD_NODE]); + dbg_vsnprintf("cqp OP_WS_MODIFY_NODE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_WS_MODIFY_NODE]); + dbg_vsnprintf("cqp OP_WS_DELETE_NODE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_WS_DELETE_NODE]); + dbg_vsnprintf("cqp OP_WS_FAILOVER_START %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_WS_FAILOVER_START]); + dbg_vsnprintf("cqp OP_WS_FAILOVER_COMPLETE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_WS_FAILOVER_COMPLETE]); + dbg_vsnprintf("cqp OP_SET_UP_MAP %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_SET_UP_MAP]); + dbg_vsnprintf("cqp OP_GEN_AE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_GEN_AE]); + dbg_vsnprintf("cqp OP_QUERY_RDMA_FEATURES %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_QUERY_RDMA_FEATURES]); + dbg_vsnprintf("cqp OP_ALLOC_LOCAL_MAC_ENTRY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY]); + dbg_vsnprintf("cqp OP_ADD_LOCAL_MAC_ENTRY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_ADD_LOCAL_MAC_ENTRY]); + dbg_vsnprintf("cqp OP_DELETE_LOCAL_MAC_ENTRY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_DELETE_LOCAL_MAC_ENTRY]); + dbg_vsnprintf("cqp OP_CQ_MODIFY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_CQ_MODIFY]); + dbg_vsnprintf("cqp OP_SRQ_CREATE %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_SRQ_CREATE]); + dbg_vsnprintf("cqp OP_SRQ_MODIFY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_SRQ_MODIFY]); + dbg_vsnprintf("cqp OP_SRQ_DESTROY %lld\n", + dev->cqp_cmd_stats[IRDMA_OP_SRQ_DESTROY]); + + dbg_vsnprintf("AH Reused Count %lld\n", + iwdev->ah_reused); + dbg_vsnprintf("AH Current List Count %d\n", + iwdev->ah_list_cnt); + dbg_vsnprintf("AH list cnt HWM %d\n", + iwdev->ah_list_hwm); + +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + if (iwdev->roce_mode) { + dbg_vsnprintf("roce rtomin = %d\n", iwdev->roce_rtomin); + dbg_vsnprintf("roce cwnd = %d\n", iwdev->roce_cwnd); + } else { + dbg_vsnprintf("iwarp rtomin = %d\n", iwdev->iwarp_rtomin); + dbg_vsnprintf("iwarp rcvwnd = %d\n", iwdev->rcv_wnd); + } +#endif /* CONFIG_CONFIGFS_FS */ +#if 0 + irdma_dump_cm_nodes(iwdev); +#endif + cmddone = true; +} + +/** + * dump_hw_stats_cmd - + * @iwdev: iwarp device + */ +static void dump_hw_stats_cmd(struct irdma_device *iwdev) +{ + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_vsi_pestat *devstat = iwdev->vsi.pestat; + struct irdma_dev_hw_stats *hw_stats = &devstat->hw_stats; + + if (iwdev->rf->rdma_ver >= IRDMA_GEN_2) + irdma_cqp_gather_stats_cmd(dev, devstat, true); + else + irdma_cqp_gather_stats_gen1(dev, devstat); + + dbg_vsnprintf("IPV4 octs recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4RXOCTS]); + dbg_vsnprintf("IPV6 octs recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6RXOCTS]); + dbg_vsnprintf("IPV4 pkts recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4RXPKTS]); + dbg_vsnprintf("IPV6 pkts recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6RXPKTS]); + dbg_vsnprintf("IPV4 frag recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4RXFRAGS]); + dbg_vsnprintf("IPV6 frag recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6RXFRAGS]); + + if (iwdev->rf->rdma_ver >= IRDMA_GEN_2) { + dbg_vsnprintf("IPV4 multicast pkts recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4RXMCPKTS]); + dbg_vsnprintf("IPV6 multicast pkts recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6RXMCPKTS]); + dbg_vsnprintf("IPV4 multicast octs recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4RXMCOCTS]); + dbg_vsnprintf("IPV6 multicast octs recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6RXMCOCTS]); + } + + dbg_vsnprintf("IPV4 octs trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4TXOCTS]); + dbg_vsnprintf("IPV6 octs trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6TXOCTS]); + dbg_vsnprintf("IPV4 pkts trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4TXPKTS]); + dbg_vsnprintf("IPV6 pkts trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6TXPKTS]); + dbg_vsnprintf("IPV4 frag trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4TXFRAGS]); + dbg_vsnprintf("IPV6 frag trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6TXFRAGS]); + dbg_vsnprintf("IPV4 multicast pkts trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4TXMCPKTS]); + dbg_vsnprintf("IPV6 multicast pkts trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6TXMCPKTS]); + dbg_vsnprintf("IPV4 multicast octs trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4TXMCOCTS]); + dbg_vsnprintf("IPV6 multicast octs trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6TXMCOCTS]); + dbg_vsnprintf("IPV4 pkts recvd & discarded %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4RXDISCARD]); + dbg_vsnprintf("IPV6 pkts recvd & discarded %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6RXDISCARD]); + dbg_vsnprintf("IPV4 pkts recvd & truncated %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4RXTRUNC]); + dbg_vsnprintf("IPV6 pkts recvd & truncated %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6RXTRUNC]); + dbg_vsnprintf("IPV4 dtgms discarded (no ARP hit) %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP4TXNOROUTE]); + dbg_vsnprintf("IPV6 dtgms discarded (no ARP hit) %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_IP6TXNOROUTE]); + dbg_vsnprintf("Rx VLAN err %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RXVLANERR]); + + dbg_vsnprintf("TCP sgmnts recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_TCPRXSEGS]); + dbg_vsnprintf("TCP sgmnts trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_TCPTXSEG]); + dbg_vsnprintf("TCP sgmnts retrans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_TCPRTXSEG]); + dbg_vsnprintf("TCP sgmnts recvd w/ err %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_TCPRXOPTERR]); + dbg_vsnprintf("TCP sgmnts recvd w/ protocol-err %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_TCPRXPROTOERR]); + + if (iwdev->rf->rdma_ver >= IRDMA_GEN_2) { + dbg_vsnprintf("Rx CNP HANDLED %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED]); + dbg_vsnprintf("Rx CNP IGNORED %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED]); + dbg_vsnprintf("Tx CNP SENT %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_TXNPCNPSENT]); + } + + dbg_vsnprintf("RDMA read-req msgs recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMARXRDS]); + dbg_vsnprintf("RDMA send-type msgs recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMARXSNDS]); + dbg_vsnprintf("RDMA write msgs recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMARXWRS]); + dbg_vsnprintf("RDMA read-req msgs sent %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMATXRDS]); + dbg_vsnprintf("RDMA send-type msgs sent %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMATXSNDS]); + dbg_vsnprintf("RDMA write msgs sent %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMATXWRS]); + dbg_vsnprintf("RDMA verb-bind ops %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMAVBND]); + dbg_vsnprintf("RDMA verb-inv ops %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMAVINV]); + + if (iwdev->rf->rdma_ver >= IRDMA_GEN_2) { + dbg_vsnprintf("UDP recvd %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_UDPRXPKTS]); + dbg_vsnprintf("UDP trans %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_UDPTXPKTS]); + } + + if (iwdev->rf->rdma_ver >= IRDMA_GEN_2 && iwdev->roce_mode) { + dbg_vsnprintf("RX ECN MARKED PKTS %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS]); + } + + if (iwdev->rf->rdma_ver >= IRDMA_GEN_3) { + dbg_vsnprintf("RNR sent %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RNR_SENT]); + dbg_vsnprintf("RNR received %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RNR_RCVD]); + dbg_vsnprintf("ord limit count %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMAORDLMTCNT]); + dbg_vsnprintf("ird limit count %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMAIRDLMTCNT]); + dbg_vsnprintf("Rx ATS %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMARXATS]); + dbg_vsnprintf("Tx ATS %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RDMATXATS]); + dbg_vsnprintf("Nak Sequence Error %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_NAKSEQERR]); + dbg_vsnprintf("Nak Sequence Error Implied %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_NAKSEQERR_IMPLIED]); + dbg_vsnprintf("RTO %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RTO]); + dbg_vsnprintf("Rcvd Out of order packets %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_RXOOOPKTS]); + dbg_vsnprintf("CRC errors %llu\n", + hw_stats->stats_val[IRDMA_HW_STAT_INDEX_ICRCERR]); + } + + cmddone = true; +} + +#if 0 +/** + * dump_mem_cmd - + * @rf: RDMA PCI function + * @cbuf: character buffer + */ +static void dump_mem_cmd(struct irdma_pci_f *rf, char *cbuf) +{ + static char *addr; + static int offset; + static int groupsize; + static size_t dumpsize; + static size_t lendumped; + static int ascii; + int delta = 0; + int ret; + + if (cmdnew) { + if (sscanf(cbuf, "%llx%n", (u64 *)&addr, &delta) == 0) + return; + + cbuf += delta; + if (sscanf(cbuf, "%zu%n", &dumpsize, &delta) == 0) + return; + + cbuf += delta; + ret = kstrtoint(cbuf, 10, &groupsize); + if (ret < 0) + groupsize = 4; + + if (dumpsize == 0 || (dumpsize & 0x80000000)) + dumpsize = 32; + + switch (groupsize) { + case 1: + ascii = true; + break; + case 8: + break; + default: + groupsize = 4; + } + offset = 0; + } + + dump_to_buf(addr, dumpsize, offset, 16, groupsize, ascii, + &lendumped); + + addr += lendumped; + offset += lendumped; + dumpsize -= lendumped; + if (dumpsize == 0) + cmddone = true; +} + +/** + * dump_pmem_cmd - + * @rf: RDMA PCI function + * @cbuf: char buffer + */ +static void dump_pmem_cmd(struct irdma_pci_f *rf, char *cbuf) +{ + static ulong paddr; + static char *addr; + static int offset; + static int groupsize; + static size_t dumpsize; + static size_t lendumped; + static int ascii; + int delta = 0; + int ret; + + if (cmdnew) { + if (sscanf(cbuf, "%llx%n", (u64 *)&paddr, &delta) == 0) + return; + + cbuf += delta; + if (sscanf(cbuf, "%zu%n", &dumpsize, &delta) == 0) + return; + + cbuf += delta; + ret = kstrtoint(cbuf, 10, &groupsize); + if (ret < 0) + groupsize = 4; + + if (dumpsize == 0 || (dumpsize & 0x80000000)) + dumpsize = 32; + + switch (grpsize) { + case 1: + ascii = true; + break; + case 8: + break; + default: + groupsize = 4; + } + offset = 0; + } + + addr = ioremap(paddr, dumpsize); + if (addr) { + dump_to_buf(addr, dumpsize, offset, 16, groupsize, ascii, + &lendumped); + iounmap(addr); + } + + paddr += lendumped; + offset += lendumped; + dumpsize -= lendumped; + if (dumpsize == 0) + cmddone = true; +} + +#endif +/** + * irdma_dbg_dump_read - read the dump data + * @filp: the opened file + * @buf: where to write the data for the user to read + * @count: the size of the user's buffer + * @ppos: file position offset + * + * When a read happens, the file system will keep calling this routine + * until it returns with no data. This is because the buffers may be too + * small to contain all the data at once. Some of the cmds count on being + * able to return the results in pieces. + */ +static ssize_t irdma_dbg_dump_read(struct file *filp, + char __user *buf, + size_t count, + loff_t *ppos) +{ + struct irdma_handler *hdl = filp->private_data; + struct irdma_device *iwdev = hdl->iwdev; + struct irdma_pci_f *rf; + int bytes_not_copied; + int len; + + rf = iwdev->rf; + if (cmddone) { + cmdnew = true; + cmddone = false; + } else { + if (cmdnew) + dbg_vsnprintf("cmd: %s", cmd_buf); + + if (strncasecmp(cmd_buf, "qp ", 3) == 0) + dump_qp_cmd(rf, &cmd_buf[3]); + else if (strncasecmp(cmd_buf, "cq ", 3) == 0) + dump_cq_cmd(rf, &cmd_buf[3]); + else if (strncasecmp(cmd_buf, "sw-stats", 8) == 0) + dump_stats_cmd(iwdev); + else if (strncasecmp(cmd_buf, "hw-stats", 8) == 0) + dump_hw_stats_cmd(iwdev); + else + dump_help(); + cmdnew = false; + } + + len = min_t(int, count, (irdma_dbg_dump_data_len - *ppos)); + if (len == 0) { + *ppos = 0; + irdma_dbg_dump_data_len = 0; + return 0; + } + + bytes_not_copied = + copy_to_user(buf, &irdma_dbg_dump_buf[*ppos], len); + if (bytes_not_copied) { + dev_warn(iwdev->ibdev.dma_device, + "copy_to_user returned 0x%x\n", bytes_not_copied); + } + + *ppos += len; + if (*ppos >= irdma_dbg_dump_data_len) { + *ppos = 0; + irdma_dbg_dump_data_len = 0; + } + + return len; +} + +/** + * irdma_dbg_dump_write - trigger a datadump snapshot + * @filp: the opened file + * @buf: where to find the user's data + * @count: the length of the user's data + * @ppos: file position offset + */ +static ssize_t irdma_dbg_dump_write(struct file *filp, + const char __user *buf, + size_t count, + loff_t *ppos) +{ + int bytes_not_copied; + + /* don't allow partial writes */ + if (*ppos != 0) + return 0; + if (count >= sizeof(cmd_buf)) + return -ENOSPC; + + bytes_not_copied = copy_from_user(cmd_buf, buf, count); + if (bytes_not_copied < 0) + return bytes_not_copied; + if (bytes_not_copied > 0) + count -= bytes_not_copied; + + cmd_buf[count] = '\0'; + cmdnew = true; + cmddone = false; + *ppos = 0; + irdma_dbg_dump_data_len = 0; + return count; +} + +/** + * irdma_dbg_prep_dump_buf + * @hdl: the iWARP handler we're working with + * @buflen: the desired buffer length + * + * Return positive if success, 0 if failed + */ +static int irdma_dbg_prep_dump_buf(struct irdma_handler *hdl, int buflen) +{ + if (irdma_dbg_dump_buf_len && irdma_dbg_dump_buf_len < buflen) { + kfree(irdma_dbg_dump_buf); + irdma_dbg_dump_buf_len = 0; + irdma_dbg_dump_buf = NULL; + } + + if (!irdma_dbg_dump_buf) { + irdma_dbg_dump_buf = kzalloc(buflen, GFP_KERNEL); + if (!irdma_dbg_dump_buf) { + irdma_dbg_dump_buf_len = 0; + pr_err("%s: memory alloc for snapshot failed\n", + __func__); + } else { + irdma_dbg_dump_buf_len = buflen; + pr_err("%s: irdma_dbg_dump_buf_len = %d\n", + __func__, (int)irdma_dbg_dump_buf_len); + } + } + + return irdma_dbg_dump_buf_len; +} + +static const struct file_operations irdma_dbg_dump_fops = { + .owner = THIS_MODULE, + .open = simple_open, + .read = irdma_dbg_dump_read, + .write = irdma_dbg_dump_write, +}; + +/** + * irdma_dbg_pf_init - setup the debugfs directory for the pf + * @hdl: the iWARP handler that is starting up + */ +void irdma_dbg_pf_init(struct irdma_handler *hdl) +{ + const char *name = pci_name(hdl->iwdev->rf->pcidev); + struct dentry *pfile __attribute__ ((unused)); + + spin_lock_init(&hdl->uctx_list_lock); + INIT_LIST_HEAD(&hdl->ucontext_list); + if (irdma_dbg_prep_dump_buf(hdl, IRDMA_DUMP_BUF_SIZE) == 0) { + pr_err("irdma_dbg_pf_init: unable to allocate debugfs dump buffer\n"); + return; + } + + hdl->irdma_dbg_dentry = debugfs_create_dir(name, irdma_dbg_root); + if (hdl->irdma_dbg_dentry) + pfile = + debugfs_create_file("dump", 0600, hdl->irdma_dbg_dentry, + hdl, &irdma_dbg_dump_fops); + else + pr_err("%s: debugfs entry for %s failed\n", __func__, name); +} + +/** + * irdma_dbg_pf_exit - clear out the pf's debugfs entries + * @hdl: the iWARP handler that is stopping + */ +void irdma_dbg_pf_exit(struct irdma_handler *hdl) +{ + if (hdl) { + pr_err("%s: removing debugfs entries\n", __func__); + debugfs_remove_recursive(hdl->irdma_dbg_dentry); + hdl->irdma_dbg_dentry = NULL; + } +} + +/** + * irdma_dbg_init - start up debugfs for the driver + */ +void irdma_dbg_init(void) +{ + irdma_dbg_root = debugfs_create_dir(irdma_driver_name, NULL); + if (!irdma_dbg_root) + pr_err("%s: init of debugfs failed\n", __func__); +} + +/** + * irdma_dbg_exit - clean out the driver's debugfs entries + */ +void irdma_dbg_exit(void) +{ + kfree(irdma_dbg_dump_buf); + irdma_dbg_dump_buf_len = 0; + irdma_dbg_dump_buf = NULL; + debugfs_remove_recursive(irdma_dbg_root); +} + +#endif /* CONFIG_DEBUG_FS */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/defs.h b/drivers/intel/irdma-1.14.33/src/irdma/defs.h new file mode 100644 index 000000000..52f4acfbf --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/defs.h @@ -0,0 +1,1841 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef IRDMA_DEFS_H +#define IRDMA_DEFS_H + +#define IRDMA_FIRST_USER_QP_ID 3 + +#define ECN_CODE_PT_MASK 3 +#define ECN_CODE_PT_VAL 2 + +#define IRDMA_PUSH_OFFSET (8 * 1024 * 1024) +#define IRDMA_PF_FIRST_PUSH_PAGE_INDEX 16 +#define IRDMA_PF_BAR_RSVD (60 * 1024) +#define IRDMA_VF_PUSH_OFFSET ((8 + 64) * 1024) +#define IRDMA_VF_FIRST_PUSH_PAGE_INDEX 2 +#define IRDMA_VF_BAR_RSVD 4096 + +#define IRDMA_PE_DB_SIZE_4M 1 +#define IRDMA_PE_DB_SIZE_8M 2 + +#define IRDMA_IRD_HW_SIZE_4_GEN3 0 +#define IRDMA_IRD_HW_SIZE_8_GEN3 1 +#define IRDMA_IRD_HW_SIZE_16_GEN3 2 +#define IRDMA_IRD_HW_SIZE_32_GEN3 3 +#define IRDMA_IRD_HW_SIZE_64_GEN3 4 +#define IRDMA_IRD_HW_SIZE_128_GEN3 5 +#define IRDMA_IRD_HW_SIZE_256_GEN3 6 +#define IRDMA_IRD_HW_SIZE_512_GEN3 7 +#define IRDMA_IRD_HW_SIZE_1024_GEN3 8 +#define IRDMA_IRD_HW_SIZE_2048_GEN3 9 +#define IRDMA_IRD_HW_SIZE_4096_GEN3 10 + +#define IRDMA_IRD_HW_SIZE_4 0 +#define IRDMA_IRD_HW_SIZE_16 1 +#define IRDMA_IRD_HW_SIZE_64 2 +#define IRDMA_IRD_HW_SIZE_128 3 +#define IRDMA_IRD_HW_SIZE_256 4 + +#define IRDMA_QP_STATE_INVALID 0 +#define IRDMA_QP_STATE_IDLE 1 +#define IRDMA_QP_STATE_RTS 2 +#define IRDMA_QP_STATE_CLOSING 3 +#define IRDMA_QP_STATE_SQD 3 +#define IRDMA_QP_STATE_RTR 4 +#define IRDMA_QP_STATE_TERMINATE 5 +#define IRDMA_QP_STATE_ERROR 6 + +#define IRDMA_MAX_USER_PRIORITY 8 +#define IRDMA_DSCP_NUM_VAL 64 +#define IEEE_8021QAZ_MAX_TCS 8 +#define IRDMA_MAX_STATS_COUNT_GEN1 12 +#define IRDMA_MAX_STATS_COUNT 128 +#define IRDMA_FIRST_NON_PF_STAT 4 + +#define IRDMA_MIN_MTU_IPV4 576 +#define IRDMA_MIN_MTU_IPV6 1280 +#define IRDMA_MTU_TO_MSS_IPV4 40 +#define IRDMA_MTU_TO_MSS_IPV6 60 +#define IRDMA_DEFAULT_MTU 1500 + +#define Q2_FPSN_OFFSET 64 +#define TERM_DDP_LEN_TAGGED 14 +#define TERM_DDP_LEN_UNTAGGED 18 +#define TERM_RDMA_LEN 28 +#define RDMA_OPCODE_M 0x0f +#define RDMA_READ_REQ_OPCODE 1 +#define Q2_BAD_FRAME_OFFSET 72 +#define CQE_MAJOR_DRV 0x8000 + +#define IRDMA_TERM_SENT 1 +#define IRDMA_TERM_RCVD 2 +#define IRDMA_TERM_DONE 4 +#define IRDMA_MAC_HLEN 14 + +#define IRDMA_CQP_WAIT_POLL_REGS 1 +#define IRDMA_CQP_WAIT_POLL_CQ 2 +#define IRDMA_CQP_WAIT_EVENT 3 + +#define IRDMA_AE_SOURCE_RSVD 0x0 +#define IRDMA_AE_SOURCE_RQ 0x1 +#define IRDMA_AE_SOURCE_RQ_0011 0x3 + +#define IRDMA_AE_SOURCE_CQ 0x2 +#define IRDMA_AE_SOURCE_CQ_0110 0x6 +#define IRDMA_AE_SOURCE_CQ_1010 0xa +#define IRDMA_AE_SOURCE_CQ_1110 0xe + +#define IRDMA_AE_SOURCE_SQ 0x5 +#define IRDMA_AE_SOURCE_SQ_0111 0x7 + +#define IRDMA_AE_SOURCE_IN_WR 0x9 +#define IRDMA_AE_SOURCE_IN_RR 0xb +#define IRDMA_AE_SOURCE_OUT_RR 0xd +#define IRDMA_AE_SOURCE_OUT_RR_1111 0xf + +#define IRDMA_AE_SOURCE_RSRC_EXHT_Q1 0x1 +#define IRDMA_AE_SOURCE_RSRC_EXHT_XT_RR 0x5 + +#define IRDMA_TCP_STATE_NON_EXISTENT 0 +#define IRDMA_TCP_STATE_CLOSED 1 +#define IRDMA_TCP_STATE_LISTEN 2 +#define IRDMA_STATE_SYN_SEND 3 +#define IRDMA_TCP_STATE_SYN_RECEIVED 4 +#define IRDMA_TCP_STATE_ESTABLISHED 5 +#define IRDMA_TCP_STATE_CLOSE_WAIT 6 +#define IRDMA_TCP_STATE_FIN_WAIT_1 7 +#define IRDMA_TCP_STATE_CLOSING 8 +#define IRDMA_TCP_STATE_LAST_ACK 9 +#define IRDMA_TCP_STATE_FIN_WAIT_2 10 +#define IRDMA_TCP_STATE_TIME_WAIT 11 +#define IRDMA_TCP_STATE_RESERVED_1 12 +#define IRDMA_TCP_STATE_RESERVED_2 13 +#define IRDMA_TCP_STATE_RESERVED_3 14 +#define IRDMA_TCP_STATE_RESERVED_4 15 + +#define IRDMA_CQP_SW_SQSIZE_4 4 +#define IRDMA_CQP_SW_SQSIZE_2048 2048 + +#define IRDMA_CQ_TYPE_IWARP 1 +#define IRDMA_CQ_TYPE_ILQ 2 +#define IRDMA_CQ_TYPE_IEQ 3 +#define IRDMA_CQ_TYPE_CQP 4 + +#define IRDMA_DONE_COUNT 1000 +#define IRDMA_SLEEP_COUNT 10 + +#define IRDMA_UPDATE_SD_BUFF_SIZE 128 +#define IRDMA_FEATURE_BUF_SIZE (8 * IRDMA_MAX_FEATURES) + +#define ENABLE_LOC_MEM 63 +#define IRDMA_ATOMICS_ALLOWED_BIT 1 +#define MAX_PBLE_PER_SD 0x40000 +#define MAX_PBLE_SD_PER_FCN 0x400 +#define MAX_MR_PER_SD 0x8000 +#define MAX_MR_SD_PER_FCN 0x80 +#define IRDMA_PBLE_COMMIT_OFFSET 112 +#define IRDMA_MAX_QUANTA_PER_WR 8 + +#define IRDMA_QP_SW_MAX_WQ_QUANTA 32768 +#define IRDMA_QP_SW_MAX_SQ_QUANTA 32768 +#define IRDMA_QP_SW_MAX_RQ_QUANTA 32768 + +#define IRDMA_MAX_QP_WRS(max_quanta_per_wr) \ + ((IRDMA_QP_SW_MAX_WQ_QUANTA - IRDMA_SQ_RSVD) / (max_quanta_per_wr)) +#define IRDMA_SRQ_MIN_QUANTA 8 +#define IRDMA_SRQ_MAX_QUANTA 262144 +#define IRDMA_MAX_SRQ_WRS \ + ((IRDMA_SRQ_MAX_QUANTA - IRDMA_RQ_RSVD) / IRDMA_MAX_QUANTA_PER_WR) + +#define IRDMAQP_TERM_SEND_TERM_AND_FIN 0 +#define IRDMAQP_TERM_SEND_TERM_ONLY 1 +#define IRDMAQP_TERM_SEND_FIN_ONLY 2 +#define IRDMAQP_TERM_DONOT_SEND_TERM_OR_FIN 3 + +#define IRDMA_QP_TYPE_IWARP 1 +#define IRDMA_QP_TYPE_UDA 2 +#define IRDMA_QP_TYPE_ROCE_RC 3 +#define IRDMA_QP_TYPE_ROCE_UD 4 + +#define IRDMA_HW_PAGE_SIZE 4096 +#define IRDMA_HW_PAGE_SHIFT 12 +#define IRDMA_CQE_QTYPE_RQ 0 +#define IRDMA_CQE_QTYPE_SQ 1 + +#define IRDMA_QP_SW_MIN_WQSIZE 8 /* in WRs*/ +#define IRDMA_QP_WQE_MIN_SIZE 32 +#define IRDMA_QP_WQE_MAX_SIZE 256 +#define IRDMA_QP_WQE_MIN_QUANTA 1 +#define IRDMA_MAX_RQ_WQE_SHIFT_GEN1 2 +#define IRDMA_MAX_RQ_WQE_SHIFT_GEN2 3 + +#define IRDMA_DEFAULT_MAX_PUSH_LEN 8192 + +#define IRDMA_SQ_RSVD 258 +#define IRDMA_RQ_RSVD 1 +#define IRDMAQP_ATOMIC_WRITE_FRAG_LEN 0x8 + +#define IRDMA_FEATURE_RTS_AE BIT_ULL(0) +#define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1) +#define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5) +#define IRDMA_FEATURE_ATOMIC_OPS BIT_ULL(6) +#define IRDMA_FEATURE_SRQ BIT_ULL(7) +#define IRDMA_FEATURE_CQE_TIMESTAMPING BIT_ULL(8) + +#define IRDMAQP_OP_RDMA_WRITE 0x00 +#define IRDMAQP_OP_RDMA_READ 0x01 +#define IRDMAQP_OP_RDMA_SEND 0x03 +#define IRDMAQP_OP_RDMA_SEND_INV 0x04 +#define IRDMAQP_OP_RDMA_SEND_SOL_EVENT 0x05 +#define IRDMAQP_OP_RDMA_SEND_SOL_EVENT_INV 0x06 +#define IRDMAQP_OP_BIND_MW 0x08 +#define IRDMAQP_OP_FAST_REGISTER 0x09 +#define IRDMAQP_OP_LOCAL_INVALIDATE 0x0a +#define IRDMAQP_OP_RDMA_READ_LOC_INV 0x0b +#define IRDMAQP_OP_NOP 0x0c +#define IRDMAQP_OP_RDMA_WRITE_SOL 0x0d +#define IRDMAQP_OP_ATOMIC_FETCH_ADD 0x0f +#define IRDMAQP_OP_ATOMIC_COMPARE_SWAP_ADD 0x11 +#define IRDMAQP_OP_ATOMIC_WRITE 0x12 +#define IRDMAQP_OP_FLUSH_MEM_REGION 0x13 + +#define IRDMAQP_OP_GEN_RTS_AE 0x30 + +enum irdma_cqp_op_type { + IRDMA_OP_CEQ_DESTROY = 1, + IRDMA_OP_AEQ_DESTROY = 2, + IRDMA_OP_DELETE_ARP_CACHE_ENTRY = 3, + IRDMA_OP_MANAGE_APBVT_ENTRY = 4, + IRDMA_OP_CEQ_CREATE = 5, + IRDMA_OP_AEQ_CREATE = 6, + IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY = 7, + IRDMA_OP_QP_MODIFY = 8, + IRDMA_OP_QP_UPLOAD_CONTEXT = 9, + IRDMA_OP_CQ_CREATE = 10, + IRDMA_OP_CQ_DESTROY = 11, + IRDMA_OP_QP_CREATE = 12, + IRDMA_OP_QP_DESTROY = 13, + IRDMA_OP_ALLOC_STAG = 14, + IRDMA_OP_MR_REG_NON_SHARED = 15, + IRDMA_OP_DEALLOC_STAG = 16, + IRDMA_OP_MW_ALLOC = 17, + IRDMA_OP_QP_FLUSH_WQES = 18, + IRDMA_OP_ADD_ARP_CACHE_ENTRY = 19, + IRDMA_OP_MANAGE_PUSH_PAGE = 20, + IRDMA_OP_UPDATE_PE_SDS = 21, + IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE = 22, + IRDMA_OP_SUSPEND = 23, + IRDMA_OP_RESUME = 24, + IRDMA_OP_MANAGE_PBLE_BP = 25, + IRDMA_OP_QUERY_FPM_VAL = 26, + IRDMA_OP_COMMIT_FPM_VAL = 27, + IRDMA_OP_AH_CREATE = 28, + IRDMA_OP_AH_MODIFY = 29, + IRDMA_OP_AH_DESTROY = 30, + IRDMA_OP_MC_CREATE = 31, + IRDMA_OP_MC_DESTROY = 32, + IRDMA_OP_MC_MODIFY = 33, + IRDMA_OP_STATS_ALLOCATE = 34, + IRDMA_OP_STATS_FREE = 35, + IRDMA_OP_STATS_GATHER = 36, + IRDMA_OP_WS_ADD_NODE = 37, + IRDMA_OP_WS_MODIFY_NODE = 38, + IRDMA_OP_WS_DELETE_NODE = 39, + IRDMA_OP_WS_FAILOVER_START = 40, + IRDMA_OP_WS_FAILOVER_COMPLETE = 41, + IRDMA_OP_SET_UP_MAP = 42, + IRDMA_OP_GEN_AE = 43, + IRDMA_OP_QUERY_RDMA_FEATURES = 44, + IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY = 45, + IRDMA_OP_ADD_LOCAL_MAC_ENTRY = 46, + IRDMA_OP_DELETE_LOCAL_MAC_ENTRY = 47, + IRDMA_OP_CQ_MODIFY = 48, + IRDMA_OP_WS_MOVE = 49, + IRDMA_OP_SRQ_CREATE = 52, + IRDMA_OP_SRQ_MODIFY = 53, + IRDMA_OP_SRQ_DESTROY = 54, + /* Must be last entry */ + IRDMA_MAX_CQP_OPS = 55, +}; + +/* CQP SQ WQES */ +#define IRDMA_CQP_OP_CREATE_QP 0x00 +#define IRDMA_CQP_OP_MODIFY_QP 0x01 +#define IRDMA_CQP_OP_DESTROY_QP 0x02 +#define IRDMA_CQP_OP_CREATE_CQ 0x03 +#define IRDMA_CQP_OP_MODIFY_CQ 0x04 +#define IRDMA_CQP_OP_DESTROY_CQ 0x05 +#define IRDMA_CQP_OP_CREATE_SRQ 0x06 +#define IRDMA_CQP_OP_MODIFY_SRQ 0x07 +#define IRDMA_CQP_OP_DESTROY_SRQ 0x08 +#define IRDMA_CQP_OP_ALLOC_STAG 0x09 +#define IRDMA_CQP_OP_REG_MR 0x0a +#define IRDMA_CQP_OP_QUERY_STAG 0x0b +#define IRDMA_CQP_OP_REG_SMR 0x0c +#define IRDMA_CQP_OP_DEALLOC_STAG 0x0d +#define IRDMA_CQP_OP_MANAGE_LOC_MAC_TABLE 0x0e +#define IRDMA_CQP_OP_MANAGE_ARP 0x0f +#define IRDMA_CQP_OP_MANAGE_PBLE_BP 0x10 +#define IRDMA_CQP_OP_MANAGE_PUSH_PAGES 0x11 +#define IRDMA_CQP_OP_QUERY_RDMA_FEATURES 0x12 +#define IRDMA_CQP_OP_UPLOAD_CONTEXT 0x13 +#define IRDMA_CQP_OP_ALLOCATE_LOC_MAC_TABLE_ENTRY 0x14 +#define IRDMA_CQP_OP_MANAGE_HMC_PM_FUNC_TABLE 0x15 +#define IRDMA_CQP_OP_CREATE_CEQ 0x16 +#define IRDMA_CQP_OP_DESTROY_CEQ 0x18 +#define IRDMA_CQP_OP_CREATE_AEQ 0x19 +#define IRDMA_CQP_OP_DESTROY_AEQ 0x1b +#define IRDMA_CQP_OP_CREATE_ADDR_HANDLE 0x1c +#define IRDMA_CQP_OP_MODIFY_ADDR_HANDLE 0x1d +#define IRDMA_CQP_OP_DESTROY_ADDR_HANDLE 0x1e +#define IRDMA_CQP_OP_UPDATE_PE_SDS 0x1f +#define IRDMA_CQP_OP_QUERY_FPM_VAL 0x20 +#define IRDMA_CQP_OP_COMMIT_FPM_VAL 0x21 +#define IRDMA_CQP_OP_FLUSH_WQES 0x22 +/* IRDMA_CQP_OP_GEN_AE is the same value as IRDMA_CQP_OP_FLUSH_WQES */ +#define IRDMA_CQP_OP_GEN_AE 0x22 +#define IRDMA_CQP_OP_MANAGE_APBVT 0x23 +#define IRDMA_CQP_OP_NOP 0x24 +#define IRDMA_CQP_OP_MANAGE_QUAD_HASH_TABLE_ENTRY 0x25 +#define IRDMA_CQP_OP_CREATE_MCAST_GRP 0x26 +#define IRDMA_CQP_OP_MODIFY_MCAST_GRP 0x27 +#define IRDMA_CQP_OP_DESTROY_MCAST_GRP 0x28 +#define IRDMA_CQP_OP_SUSPEND_QP 0x29 +#define IRDMA_CQP_OP_RESUME_QP 0x2a +#define IRDMA_CQP_OP_SHMC_PAGES_ALLOCATED 0x2b +#define IRDMA_CQP_OP_WORK_SCHED_NODE 0x2c +#define IRDMA_CQP_OP_MANAGE_STATS 0x2d +#define IRDMA_CQP_OP_GATHER_STATS 0x2e +#define IRDMA_CQP_OP_UP_MAP 0x2f +#define IRDMA_CQP_OP_MOVE_WS_NODES 0x34 + +#define LS_64_1(val, bits) ((u64)(uintptr_t)(val) << (bits)) +#define RS_64_1(val, bits) ((u64)(uintptr_t)(val) >> (bits)) +#define LS_32_1(val, bits) ((u32)((val) << (bits))) +#define RS_32_1(val, bits) ((u32)((val) >> (bits))) + +#define FLD_LS_64(dev, val, field) \ + (((u64)(val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M]) +#define FLD_RS_64(dev, val, field) \ + ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S]) +#define FLD_LS_32(dev, val, field) \ + (((val) << (dev)->hw_shifts[field ## _S]) & (dev)->hw_masks[field ## _M]) +#define FLD_RS_32(dev, val, field) \ + ((u64)((val) & (dev)->hw_masks[field ## _M]) >> (dev)->hw_shifts[field ## _S]) + +#define IRDMA_MAX_STATS_16 0xffffULL +#define IRDMA_MAX_STATS_24 0xffffffULL +#define IRDMA_MAX_STATS_32 0xffffffffULL +#define IRDMA_MAX_STATS_48 0xffffffffffffULL +#define IRDMA_MAX_STATS_56 0xffffffffffffffULL +#define IRDMA_MAX_STATS_64 0xffffffffffffffffULL + +#define IRDMA_MAX_CQ_READ_THRESH 0x3FFFF +#define IRDMA_CQPSQ_QHASH_VLANID_S 32 +#define IRDMA_CQPSQ_QHASH_VLANID GENMASK_ULL(43, 32) +#define IRDMA_CQPSQ_QHASH_QPN_S 32 +#define IRDMA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32) +#define IRDMA_CQPSQ_QHASH_QS_HANDLE_S 0 +#define IRDMA_CQPSQ_QHASH_QS_HANDLE GENMASK_ULL(9, 0) +#define IRDMA_CQPSQ_QHASH_SRC_PORT_S 16 +#define IRDMA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16) +#define IRDMA_CQPSQ_QHASH_DEST_PORT_S 0 +#define IRDMA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_QHASH_ADDR0_S 32 +#define IRDMA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32) +#define IRDMA_CQPSQ_QHASH_ADDR1_S 0 +#define IRDMA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0) +#define IRDMA_CQPSQ_QHASH_ADDR2_S 32 +#define IRDMA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32) +#define IRDMA_CQPSQ_QHASH_ADDR3_S 0 +#define IRDMA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0) +#define IRDMA_CQPSQ_QHASH_WQEVALID_S 63 +#define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63) +#define IRDMA_CQPSQ_QHASH_OPCODE_S 32 +#define IRDMA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_QHASH_MANAGE_S 61 +#define IRDMA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61) +#define IRDMA_CQPSQ_QHASH_IPV4VALID_S 60 +#define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60) +#define IRDMA_CQPSQ_QHASH_VLANVALID_S 59 +#define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59) +#define IRDMA_CQPSQ_QHASH_ENTRYTYPE_S 42 +#define IRDMA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42) +#define IRDMA_CQPSQ_STATS_WQEVALID_S 63 +#define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63) +#define IRDMA_CQPSQ_STATS_ALLOC_INST_S 62 +#define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62) +#define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX_S 60 +#define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60) +#define IRDMA_CQPSQ_STATS_USE_INST_S 61 +#define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61) +#define IRDMA_CQPSQ_STATS_OP_S 32 +#define IRDMA_CQPSQ_STATS_OP GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_STATS_INST_INDEX_S 0 +#define IRDMA_CQPSQ_STATS_INST_INDEX GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX_S 0 +#define IRDMA_CQPSQ_STATS_HMC_FCN_INDEX GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_WS_WQEVALID_S 63 +#define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63) +#define IRDMA_CQPSQ_WS_NODEOP_S 52 +#define IRDMA_CQPSQ_WS_NODEOP GENMASK_ULL(55, 52) +#define IRDMA_CQPSQ_WS_MOVE_WQEVALID_S 63 +#define IRDMA_CQPSQ_WS_MOVE_WQEVALID BIT_ULL(63) +#define IRDMA_CQPSQ_WS_MOVE_NUM_NODES_S 8 +#define IRDMA_CQPSQ_WS_MOVE_NUM_NODES GENMASK_ULL(12, 8) +#define IRDMA_CQPSQ_WS_MOVE_RESUME_TRAFFIC_S 4 +#define IRDMA_CQPSQ_WS_MOVE_RESUME_TRAFFIC BIT_ULL(4) +#define IRDMA_CQPSQ_WS_MOVE_TARGET_PORT_S 0 +#define IRDMA_CQPSQ_WS_MOVE_TARGET_PORT GENMASK_ULL(3, 0) + +#define IRDMA_CQPSQ_WS_WS_OP_TYPE_S 60 +#define IRDMA_CQPSQ_WS_WS_OP_TYPE GENMASK_ULL(61, 60) +#define IRDMA_CQPSQ_WS_LNG_ID_S 32 +#define IRDMA_CQPSQ_WS_LNG_ID GENMASK_ULL(44, 32) +#define IRDMA_CQPSQ_WS_RATE_LIMIT_FLAGS_S 24 +#define IRDMA_CQPSQ_WS_RATE_LIMIT_FLAGS GENMASK_ULL(28, 24) +#define IRDMA_CQPSQ_WS_RATE_S 0 +#define IRDMA_CQPSQ_WS_RATE GENMASK_ULL(19, 0) +#define IRDMA_SD_MAX_S 0 +#define IRDMA_SD_MAX GENMASK_ULL(15, 0) +#define IRDMA_MEM_MAX_S 0 +#define IRDMA_MEM_MAX GENMASK_ULL(15, 0) +#define IRDMA_QP_MEM_LOC_S 44 +#define IRDMA_QP_MEM_LOC GENMASK_ULL(47, 44) +#define IRDMA_MR_MEM_LOC_S 24 +#define IRDMA_MR_MEM_LOC GENMASK_ULL(27, 24) + +#define IRDMA_CQPSQ_WS_ENABLENODE_S 62 +#define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62) +#define IRDMA_CQPSQ_WS_NODETYPE_S 61 +#define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61) +#define IRDMA_CQPSQ_WS_PRIOTYPE_S 59 +#define IRDMA_CQPSQ_WS_PRIOTYPE GENMASK_ULL(60, 59) +#define IRDMA_CQPSQ_WS_TC_S 56 +#define IRDMA_CQPSQ_WS_TC GENMASK_ULL(58, 56) +#define IRDMA_CQPSQ_WS_VMVFTYPE_S 54 +#define IRDMA_CQPSQ_WS_VMVFTYPE GENMASK_ULL(55, 54) +#define IRDMA_CQPSQ_WS_VMVFNUM_S 42 +#define IRDMA_CQPSQ_WS_VMVFNUM GENMASK_ULL(51, 42) +#define IRDMA_CQPSQ_WS_OP_S 32 +#define IRDMA_CQPSQ_WS_OP GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_WS_MOVE_OP GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_WS_PARENTID_S 16 +#define IRDMA_CQPSQ_WS_PARENTID GENMASK_ULL(29, 16) +#define IRDMA_CQPSQ_WS_NODEID_S 0 +#define IRDMA_CQPSQ_WS_NODEID GENMASK_ULL(13, 0) +#define IRDMA_CQPSQ_WS_VSI_S 48 +#define IRDMA_CQPSQ_WS_VSI GENMASK_ULL(63, 48) +#define IRDMA_CQPSQ_WS_WEIGHT_S 32 +#define IRDMA_CQPSQ_WS_WEIGHT GENMASK_ULL(38, 32) + +#define IRDMA_CQPSQ_WS_FAILING_PORT_S 44 +#define IRDMA_CQPSQ_WS_FAILING_PORT GENMASK_ULL(46, 44) +#define IRDMA_CQPSQ_WS_ACTIVE_PORT_S 40 +#define IRDMA_CQPSQ_WS_ACTIVE_PORT GENMASK_ULL(42, 40) +#define IRDMA_CQPSQ_WS_ACTIVE_PORT GENMASK_ULL(42, 40) +#define IRDMA_CQPSQ_WS_ASSIGN_TO_ACTIVE_PORT_S 0 +#define IRDMA_CQPSQ_WS_ASSIGN_TO_ACTIVE_PORT BIT_ULL(0) + +#define IRDMA_CQPSQ_UP_WQEVALID_S 63 +#define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63) +#define IRDMA_CQPSQ_UP_USEVLAN_S 62 +#define IRDMA_CQPSQ_UP_USEVLAN BIT_ULL(62) +#define IRDMA_CQPSQ_UP_USEOVERRIDE_S 61 +#define IRDMA_CQPSQ_UP_USEOVERRIDE BIT_ULL(61) +#define IRDMA_CQPSQ_UP_OP_S 32 +#define IRDMA_CQPSQ_UP_OP GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_UP_HMCFCNIDX_S 0 +#define IRDMA_CQPSQ_UP_HMCFCNIDX GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_UP_CNPOVERRIDE_S 32 +#define IRDMA_CQPSQ_UP_CNPOVERRIDE GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID_S 63 +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63) +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN_S 0 +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_BUF_LEN GENMASK_ULL(31, 0) +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP_S 32 +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_OP GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED_S 32 +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MODEL_USED GENMASK_ULL(47, 32) +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION_S 16 +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MAJOR_VERSION GENMASK_ULL(23, 16) +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION_S 0 +#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_HW_MINOR_VERSION GENMASK_ULL(7, 0) +#define IRDMA_CQPHC_SQSIZE_S 8 +#define IRDMA_CQPHC_SQSIZE GENMASK_ULL(11, 8) +#define IRDMA_CQPHC_DISABLE_PFPDUS_S 1 +#define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1) +#define IRDMA_CQPHC_ROCEV2_RTO_POLICY_S 2 +#define IRDMA_CQPHC_ROCEV2_RTO_POLICY BIT_ULL(2) +#define IRDMA_CQPHC_PROTOCOL_USED_S 3 +#define IRDMA_CQPHC_PROTOCOL_USED GENMASK_ULL(4, 3) +#define IRDMA_CQPHC_MIN_RATE_S 48 +#define IRDMA_CQPHC_MIN_RATE GENMASK_ULL(51, 48) +#define IRDMA_CQPHC_MIN_DEC_FACTOR_S 56 +#define IRDMA_CQPHC_MIN_DEC_FACTOR GENMASK_ULL(59, 56) +#define IRDMA_CQPHC_DCQCN_T_S 0 +#define IRDMA_CQPHC_DCQCN_T GENMASK_ULL(15, 0) +#define IRDMA_CQPHC_HAI_FACTOR_S 32 +#define IRDMA_CQPHC_HAI_FACTOR GENMASK_ULL(47, 32) +#define IRDMA_CQPHC_RAI_FACTOR_S 48 +#define IRDMA_CQPHC_RAI_FACTOR GENMASK_ULL(63, 48) +#define IRDMA_CQPHC_DCQCN_B_S 0 +#define IRDMA_CQPHC_DCQCN_B GENMASK_ULL(24, 0) +#define IRDMA_CQPHC_DCQCN_F_S 25 +#define IRDMA_CQPHC_DCQCN_F GENMASK_ULL(27, 25) +#define IRDMA_CQPHC_CC_CFG_VALID_S 31 +#define IRDMA_CQPHC_CC_CFG_VALID BIT_ULL(31) +#define IRDMA_CQPHC_RREDUCE_MPERIOD_S 32 +#define IRDMA_CQPHC_RREDUCE_MPERIOD GENMASK_ULL(63, 32) +#define IRDMA_CQPHC_HW_MINVER_S 0 +#define IRDMA_CQPHC_HW_MINVER GENMASK_ULL(15, 0) + +#define IRDMA_CQPHC_HW_MAJVER_GEN_1 0 +#define IRDMA_CQPHC_HW_MAJVER_GEN_2 1 +#define IRDMA_CQPHC_HW_MAJVER_GEN_3 2 +#define IRDMA_CQPHC_HW_MAJVER_S 16 +#define IRDMA_CQPHC_HW_MAJVER GENMASK_ULL(31, 16) +#define IRDMA_CQPHC_CEQPERVF_S 32 +#define IRDMA_CQPHC_CEQPERVF GENMASK_ULL(39, 32) + +#define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK_S 3 +#define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK BIT_ULL(3) + +#define IRDMA_CQPHC_ENABLED_VFS_S 32 +#define IRDMA_CQPHC_ENABLED_VFS GENMASK_ULL(37, 32) + +#define IRDMA_CQPHC_HMC_PROFILE_S 0 +#define IRDMA_CQPHC_HMC_PROFILE GENMASK_ULL(2, 0) +#define IRDMA_CQPHC_SVER_S 24 +#define IRDMA_CQPHC_SVER GENMASK_ULL(31, 24) +#define IRDMA_CQPHC_SQBASE_S 9 +#define IRDMA_CQPHC_SQBASE GENMASK_ULL(63, 9) + +#define IRDMA_CQPHC_TIMESTAMP_OVERRIDE_S 5 +#define IRDMA_CQPHC_TIMESTAMP_OVERRIDE BIT_ULL(5) +#define IRDMA_CQPHC_TS_SHIFT_S 8 +#define IRDMA_CQPHC_TS_SHIFT GENMASK_ULL(12, 8) +#define IRDMA_CQPHC_EN_FINE_GRAINED_TIMERS_S 0 +#define IRDMA_CQPHC_EN_FINE_GRAINED_TIMERS BIT_ULL(0) + +#define IRDMA_CQPHC_OOISC_BLKSIZE_S 60 +#define IRDMA_CQPHC_OOISC_BLKSIZE GENMASK_ULL(63, 60) +#define IRDMA_CQPHC_RRSP_BLKSIZE_S 56 +#define IRDMA_CQPHC_RRSP_BLKSIZE GENMASK_ULL(59, 56) +#define IRDMA_CQPHC_Q1_BLKSIZE_S 52 +#define IRDMA_CQPHC_Q1_BLKSIZE GENMASK_ULL(55, 52) +#define IRDMA_CQPHC_XMIT_BLKSIZE_S 48 +#define IRDMA_CQPHC_XMIT_BLKSIZE GENMASK_ULL(51, 48) +#define IRDMA_CQPHC_BLKSIZES_VALID_S 4 +#define IRDMA_CQPHC_BLKSIZES_VALID BIT_ULL(4) + +#define IRDMA_CQPHC_QPCTX_S 0 +#define IRDMA_CQPHC_QPCTX GENMASK_ULL(63, 0) +#define IRDMA_QP_DBSA_HW_SQ_TAIL_S 0 +#define IRDMA_QP_DBSA_HW_SQ_TAIL GENMASK_ULL(14, 0) +#define IRDMA_CQ_DBSA_CQEIDX_S 0 +#define IRDMA_CQ_DBSA_CQEIDX GENMASK_ULL(19, 0) +#define IRDMA_CQ_DBSA_SW_CQ_SELECT_S 0 +#define IRDMA_CQ_DBSA_SW_CQ_SELECT GENMASK_ULL(13, 0) +#define IRDMA_CQ_DBSA_ARM_NEXT_S 14 +#define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14) +#define IRDMA_CQ_DBSA_ARM_NEXT_SE_S 15 +#define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15) +#define IRDMA_CQ_DBSA_ARM_SEQ_NUM_S 16 +#define IRDMA_CQ_DBSA_ARM_SEQ_NUM GENMASK_ULL(17, 16) + +/* CQP and iWARP Completion Queue */ +#define IRDMA_CQ_QPCTX_S IRDMA_CQPHC_QPCTX_S +#define IRDMA_CQ_QPCTX IRDMA_CQPHC_QPCTX + +#define IRDMA_CCQ_OPRETVAL_S 0 +#define IRDMA_CCQ_OPRETVAL GENMASK_ULL(31, 0) + +#define IRDMA_CCQ_DEFINFO_S 32 +#define IRDMA_CCQ_DEFINFO GENMASK_ULL(63, 32) + +#define IRDMA_CQ_MINERR_S 0 +#define IRDMA_CQ_MINERR GENMASK_ULL(15, 0) +#define IRDMA_CQ_MAJERR_S 16 +#define IRDMA_CQ_MAJERR GENMASK_ULL(31, 16) +#define IRDMA_CQ_WQEIDX_S 32 +#define IRDMA_CQ_WQEIDX GENMASK_ULL(46, 32) +#define IRDMA_CQ_EXTCQE_S 50 +#define IRDMA_CQ_EXTCQE BIT_ULL(50) +#define IRDMA_OOO_CMPL_S 54 +#define IRDMA_OOO_CMPL BIT_ULL(54) +#define IRDMA_CQ_ERROR_S 55 +#define IRDMA_CQ_ERROR BIT_ULL(55) +#define IRDMA_CQ_SQ_S 62 +#define IRDMA_CQ_SQ BIT_ULL(62) + +#define IRDMA_CQ_SRQ_S 52 +#define IRDMA_CQ_SRQ BIT_ULL(52) +#define IRDMA_CQ_VALID_S 63 +#define IRDMA_CQ_VALID BIT_ULL(63) +#define IRDMA_CQ_IMMVALID BIT_ULL(62) +#define IRDMA_CQ_UDSMACVALID_S 61 +#define IRDMA_CQ_UDSMACVALID BIT_ULL(61) +#define IRDMA_CQ_UDVLANVALID_S 60 +#define IRDMA_CQ_UDVLANVALID BIT_ULL(60) +#define IRDMA_CQ_UDSMAC_S 0 +#define IRDMA_CQ_UDSMAC GENMASK_ULL(47, 0) +#define IRDMA_CQ_UDVLAN_S 48 +#define IRDMA_CQ_UDVLAN GENMASK_ULL(63, 48) + +#define IRDMA_CQ_IMMDATA_S 0 +#define IRDMA_CQ_IMMVALID_S 62 +#define IRDMA_CQ_IMMDATA GENMASK_ULL(125, 62) +#define IRDMA_CQ_IMMDATALOW32_S 0 +#define IRDMA_CQ_IMMDATALOW32 GENMASK_ULL(31, 0) +#define IRDMA_CQ_IMMDATAUP32_S 32 +#define IRDMA_CQ_IMMDATAUP32 GENMASK_ULL(63, 32) +#define IRDMACQ_PAYLDLEN_S 0 +#define IRDMACQ_PAYLDLEN GENMASK_ULL(31, 0) +#define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS_S 32 +#define IRDMACQ_TCPSQN_ROCEPSN_RTT_TS GENMASK_ULL(63, 32) +#define IRDMACQ_INVSTAG_S 0 +#define IRDMACQ_INVSTAG GENMASK_ULL(31, 0) +#define IRDMACQ_QPID_S 32 +#define IRDMACQ_QPID GENMASK_ULL(55, 32) + +#define IRDMACQ_UDSRCQPN_S 0 +#define IRDMACQ_UDSRCQPN GENMASK_ULL(31, 0) +#define IRDMACQ_PSHDROP_S 51 +#define IRDMACQ_PSHDROP BIT_ULL(51) +#define IRDMACQ_STAG_S 53 +#define IRDMACQ_STAG BIT_ULL(53) +#define IRDMACQ_IPV4_S 53 +#define IRDMACQ_IPV4 BIT_ULL(53) +#define IRDMACQ_SOEVENT_S 54 +#define IRDMACQ_SOEVENT BIT_ULL(54) +#define IRDMACQ_OP_S 56 +#define IRDMACQ_OP GENMASK_ULL(61, 56) + +#define IRDMA_CEQE_CQCTX_S 0 +#define IRDMA_CEQE_CQCTX GENMASK_ULL(62, 0) +#define IRDMA_CEQE_VALID_S 63 +#define IRDMA_CEQE_VALID BIT_ULL(63) + +/* AEQE format */ +#define IRDMA_AEQE_COMPCTX_S IRDMA_CQPHC_QPCTX_S +#define IRDMA_AEQE_COMPCTX IRDMA_CQPHC_QPCTX +#define IRDMA_AEQE_QPCQID_LOW_S 0 +#define IRDMA_AEQE_QPCQID_LOW GENMASK_ULL(17, 0) +#define IRDMA_AEQE_QPCQID_HI_S 46 +#define IRDMA_AEQE_QPCQID_HI BIT_ULL(46) +#define IRDMA_AEQE_WQDESCIDX_S 18 +#define IRDMA_AEQE_WQDESCIDX GENMASK_ULL(32, 18) +#define IRDMA_AEQE_OVERFLOW_S 33 +#define IRDMA_AEQE_OVERFLOW BIT_ULL(33) +#define IRDMA_AEQE_AECODE_S 34 +#define IRDMA_AEQE_AECODE GENMASK_ULL(45, 34) +#define IRDMA_AEQE_AESRC_S 50 +#define IRDMA_AEQE_AESRC GENMASK_ULL(53, 50) +#define IRDMA_AEQE_IWSTATE_S 54 +#define IRDMA_AEQE_IWSTATE GENMASK_ULL(56, 54) +#define IRDMA_AEQE_TCPSTATE_S 57 +#define IRDMA_AEQE_TCPSTATE GENMASK_ULL(60, 57) +#define IRDMA_AEQE_Q2DATA_S 61 +#define IRDMA_AEQE_Q2DATA GENMASK_ULL(62, 61) +#define IRDMA_AEQE_VALID_S 63 +#define IRDMA_AEQE_VALID BIT_ULL(63) + +#define IRDMA_AEQE_Q2DATA_GEN_3_S 4 +#define IRDMA_AEQE_Q2DATA_GEN_3 GENMASK_ULL(5, 4) +#define IRDMA_AEQE_TCPSTATE_GEN_3_S 0 +#define IRDMA_AEQE_TCPSTATE_GEN_3 GENMASK_ULL(3, 0) +#define IRDMA_AEQE_QPCQID_GEN_3_S 0 +#define IRDMA_AEQE_QPCQID_GEN_3 GENMASK_ULL(24, 0) +#define IRDMA_AEQE_AECODE_GEN_3_S 50 +#define IRDMA_AEQE_AECODE_GEN_3 GENMASK_ULL(61, 50) +#define IRDMA_AEQE_OVERFLOW_GEN_3_S 62 +#define IRDMA_AEQE_OVERFLOW_GEN_3 BIT_ULL(62) +#define IRDMA_AEQE_WQDESCIDX_GEN_3_S 32 +#define IRDMA_AEQE_WQDESCIDX_GEN_3 GENMASK_ULL(49, 32) +#define IRDMA_AEQE_IWSTATE_GEN_3_S 29 +#define IRDMA_AEQE_IWSTATE_GEN_3 GENMASK_ULL(31, 29) +#define IRDMA_AEQE_AESRC_GEN_3_S 25 +#define IRDMA_AEQE_AESRC_GEN_3 GENMASK_ULL(28, 25) +#define IRDMA_AEQE_CMPL_CTXT_S 6 +#define IRDMA_AEQE_CMPL_CTXT GENMASK_ULL(63, 6) + +#define IRDMA_UDA_QPSQ_NEXT_HDR_S 16 +#define IRDMA_UDA_QPSQ_NEXT_HDR GENMASK_ULL(23, 16) +#define IRDMA_UDA_QPSQ_OPCODE_S 32 +#define IRDMA_UDA_QPSQ_OPCODE GENMASK_ULL(37, 32) +#define IRDMA_UDA_QPSQ_L4LEN_S 42 +#define IRDMA_UDA_QPSQ_L4LEN GENMASK_ULL(45, 42) +#define IRDMA_GEN1_UDA_QPSQ_L4LEN_S 24 +#define IRDMA_GEN1_UDA_QPSQ_L4LEN GENMASK_ULL(27, 24) +#define IRDMA_UDA_QPSQ_AHIDX_S 0 +#define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0) +#define IRDMA_UDA_QPSQ_VALID_S 63 +#define IRDMA_UDA_QPSQ_VALID BIT_ULL(63) +#define IRDMA_UDA_QPSQ_SIGCOMPL_S 62 +#define IRDMA_UDA_QPSQ_SIGCOMPL BIT_ULL(62) +#define IRDMA_UDA_QPSQ_MACLEN_S 56 +#define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56) +#define IRDMA_UDA_QPSQ_IPLEN_S 48 +#define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48) +#define IRDMA_UDA_QPSQ_L4T_S 30 +#define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30) +#define IRDMA_UDA_QPSQ_IIPT_S 28 +#define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28) +#define IRDMA_UDA_PAYLOADLEN_S 0 +#define IRDMA_UDA_PAYLOADLEN GENMASK_ULL(13, 0) +#define IRDMA_UDA_HDRLEN_S 16 +#define IRDMA_UDA_HDRLEN GENMASK_ULL(24, 16) +#define IRDMA_VLAN_TAG_VALID_S 50 +#define IRDMA_VLAN_TAG_VALID BIT_ULL(50) +#define IRDMA_UDA_L3PROTO_S 0 +#define IRDMA_UDA_L3PROTO GENMASK_ULL(1, 0) +#define IRDMA_UDA_L4PROTO_S 16 +#define IRDMA_UDA_L4PROTO GENMASK_ULL(17, 16) +#define IRDMA_UDA_QPSQ_DOLOOPBACK_S 44 +#define IRDMA_UDA_QPSQ_DOLOOPBACK BIT_ULL(44) +#define IRDMA_CQPSQ_BUFSIZE_S 0 +#define IRDMA_CQPSQ_BUFSIZE GENMASK_ULL(31, 0) +#define IRDMA_CQPSQ_OPCODE_S 32 +#define IRDMA_CQPSQ_OPCODE GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_WQEVALID_S 63 +#define IRDMA_CQPSQ_WQEVALID BIT_ULL(63) +#define IRDMA_CQPSQ_TPHVAL_S 0 +#define IRDMA_CQPSQ_TPHVAL GENMASK_ULL(7, 0) + +#define IRDMA_CQPSQ_VSIIDX_S 8 +#define IRDMA_CQPSQ_VSIIDX GENMASK_ULL(23, 8) +#define IRDMA_CQPSQ_TPHEN_S 60 +#define IRDMA_CQPSQ_TPHEN BIT_ULL(60) + +#define IRDMA_CQPSQ_PBUFADDR_S IRDMA_CQPHC_QPCTX_S +#define IRDMA_CQPSQ_PBUFADDR IRDMA_CQPHC_QPCTX + +#define IRDMA_CQPSQ_PASID_S 32 +#define IRDMA_CQPSQ_PASID GENMASK_ULL(51, 32) +#define IRDMA_CQPSQ_PASID_VALID_S 62 +#define IRDMA_CQPSQ_PASID_VALID BIT_ULL(62) + +/* Create/Modify/Destroy QP */ + +#define IRDMA_CQPSQ_QP_NEWMSS_S 32 +#define IRDMA_CQPSQ_QP_NEWMSS GENMASK_ULL(45, 32) +#define IRDMA_CQPSQ_QP_TERMLEN_S 48 +#define IRDMA_CQPSQ_QP_TERMLEN GENMASK_ULL(51, 48) + +#define IRDMA_CQPSQ_QP_QPCTX_S IRDMA_CQPHC_QPCTX_S +#define IRDMA_CQPSQ_QP_QPCTX IRDMA_CQPHC_QPCTX + +#define IRDMA_CQPSQ_QP_QPID_S 0 +#define IRDMA_CQPSQ_QP_QPID_M (0xFFFFFFUL) + +#define IRDMA_CQPSQ_QP_OP_S 32 +#define IRDMA_CQPSQ_QP_OP_M IRDMACQ_OP_M +#define IRDMA_CQPSQ_QP_ORDVALID_S 42 +#define IRDMA_CQPSQ_QP_ORDVALID BIT_ULL(42) +#define IRDMA_CQPSQ_QP_TOECTXVALID_S 43 +#define IRDMA_CQPSQ_QP_TOECTXVALID BIT_ULL(43) +#define IRDMA_CQPSQ_QP_CACHEDVARVALID_S 44 +#define IRDMA_CQPSQ_QP_CACHEDVARVALID BIT_ULL(44) +#define IRDMA_CQPSQ_QP_VQ_S 45 +#define IRDMA_CQPSQ_QP_VQ BIT_ULL(45) +#define IRDMA_CQPSQ_QP_FORCELOOPBACK_S 46 +#define IRDMA_CQPSQ_QP_FORCELOOPBACK BIT_ULL(46) +#define IRDMA_CQPSQ_QP_CQNUMVALID_S 47 +#define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47) +#define IRDMA_CQPSQ_QP_QPTYPE_S 48 +#define IRDMA_CQPSQ_QP_QPTYPE GENMASK_ULL(50, 48) +#define IRDMA_CQPSQ_QP_MACVALID_S 51 +#define IRDMA_CQPSQ_QP_MACVALID BIT_ULL(51) +#define IRDMA_CQPSQ_QP_MSSCHANGE_S 52 +#define IRDMA_CQPSQ_QP_MSSCHANGE BIT_ULL(52) +#define IRDMA_CQPSQ_QP_IGNOREMWBOUND_S 54 +#define IRDMA_CQPSQ_QP_IGNOREMWBOUND BIT_ULL(54) +#define IRDMA_CQPSQ_QP_REMOVEHASHENTRY_S 55 +#define IRDMA_CQPSQ_QP_REMOVEHASHENTRY BIT_ULL(55) +#define IRDMA_CQPSQ_QP_TERMACT_S 56 +#define IRDMA_CQPSQ_QP_TERMACT GENMASK_ULL(57, 56) +#define IRDMA_CQPSQ_QP_RESETCON_S 58 +#define IRDMA_CQPSQ_QP_RESETCON BIT_ULL(58) +#define IRDMA_CQPSQ_QP_ARPTABIDXVALID_S 59 +#define IRDMA_CQPSQ_QP_ARPTABIDXVALID BIT_ULL(59) +#define IRDMA_CQPSQ_QP_NEXTIWSTATE_S 60 +#define IRDMA_CQPSQ_QP_NEXTIWSTATE GENMASK_ULL(62, 60) + +#define IRDMA_CQPSQ_QP_DBSHADOWADDR_S IRDMA_CQPHC_QPCTX_S +#define IRDMA_CQPSQ_QP_DBSHADOWADDR IRDMA_CQPHC_QPCTX + +#define IRDMA_CQPSQ_SRQ_RQSIZE_S 0 +#define IRDMA_CQPSQ_SRQ_RQSIZE GENMASK_ULL(3, 0) +#define IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE_S 4 +#define IRDMA_CQPSQ_SRQ_RQ_WQE_SIZE GENMASK_ULL(5, 4) +#define IRDMA_CQPSQ_SRQ_SRQ_LIMIT_S 32 +#define IRDMA_CQPSQ_SRQ_SRQ_LIMIT GENMASK_ULL(43, 32) +#define IRDMA_CQPSQ_SRQ_SRQCTX_S 6 +#define IRDMA_CQPSQ_SRQ_SRQCTX GENMASK_ULL(63, 6) +#define IRDMA_CQPSQ_SRQ_PD_ID_S 16 +#define IRDMA_CQPSQ_SRQ_PD_ID GENMASK_ULL(39, 16) +#define IRDMA_CQPSQ_SRQ_SRQ_ID_S 0 +#define IRDMA_CQPSQ_SRQ_SRQ_ID GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_SRQ_OP_S 32 +#define IRDMA_CQPSQ_SRQ_OP GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE_S 44 +#define IRDMA_CQPSQ_SRQ_LEAF_PBL_SIZE GENMASK_ULL(45, 44) +#define IRDMA_CQPSQ_SRQ_VIRTMAP_S 47 +#define IRDMA_CQPSQ_SRQ_VIRTMAP BIT_ULL(47) +#define IRDMA_CQPSQ_SRQ_TPH_EN_S 60 +#define IRDMA_CQPSQ_SRQ_TPH_EN BIT_ULL(60) +#define IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT_S 61 +#define IRDMA_CQPSQ_SRQ_ARM_LIMIT_EVENT BIT_ULL(61) +#define IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX_S 0 +#define IRDMA_CQPSQ_SRQ_FIRST_PM_PBL_IDX GENMASK_ULL(27, 0) +#define IRDMA_CQPSQ_SRQ_TPH_VALUE_S 0 +#define IRDMA_CQPSQ_SRQ_TPH_VALUE GENMASK_ULL(7, 0) +#define IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR_S 8 +#define IRDMA_CQPSQ_SRQ_PHYSICAL_BUFFER_ADDR GENMASK_ULL(63, 8) +#define IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR_S 6 +#define IRDMA_CQPSQ_SRQ_DB_SHADOW_ADDR GENMASK_ULL(63, 6) +#define IRDMA_CQPSQ_CQ_CQSIZE_S 0 +#define IRDMA_CQPSQ_CQ_CQSIZE GENMASK_ULL(20, 0) +#define IRDMA_CQPSQ_CQ_CQCTX_S 0 +#define IRDMA_CQPSQ_CQ_CQCTX GENMASK_ULL(62, 0) +#define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD_S 0 +#define IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD GENMASK(17, 0) + +#define IRDMA_CQPSQ_CQ_CQID_HIGH_S 50 +#define IRDMA_CQPSQ_CQ_CQID_HIGH GENMASK_ULL(52, 50) +#define IRDMA_CQPSQ_CQ_CEQID_HIGH_S 54 +#define IRDMA_CQPSQ_CQ_CEQID_HIGH GENMASK_ULL(59, 54) +#define IRDMA_CQPSQ_CQ_OP_S 32 +#define IRDMA_CQPSQ_CQ_OP GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_CQ_CQRESIZE_S 43 +#define IRDMA_CQPSQ_CQ_CQRESIZE BIT_ULL(43) +#define IRDMA_CQPSQ_CQ_LPBLSIZE_S 44 +#define IRDMA_CQPSQ_CQ_LPBLSIZE GENMASK_ULL(45, 44) +#define IRDMA_CQPSQ_CQ_CHKOVERFLOW_S 46 +#define IRDMA_CQPSQ_CQ_CHKOVERFLOW BIT_ULL(46) +#define IRDMA_CQPSQ_CQ_VIRTMAP_S 47 +#define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47) +#define IRDMA_CQPSQ_CQ_ENCEQEMASK_S 48 +#define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48) +#define IRDMA_CQPSQ_CQ_CEQIDVALID_S 49 +#define IRDMA_CQPSQ_CQ_CEQIDVALID BIT_ULL(49) +#define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT_S 61 +#define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT BIT_ULL(61) +#define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX_S 0 +#define IRDMA_CQPSQ_CQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0) + +/* Allocate/Register/Register Shared/Deallocate Stag */ +#define IRDMA_CQPSQ_STAG_PDID_HI_S 54 +#define IRDMA_CQPSQ_STAG_PDID_HI GENMASK_ULL(59, 54) + +#define IRDMA_CQPSQ_STAG_VA_FBO_S IRDMA_CQPHC_QPCTX_S +#define IRDMA_CQPSQ_STAG_VA_FBO IRDMA_CQPHC_QPCTX +#define IRDMA_CQPSQ_STAG_STAGLEN_S 0 +#define IRDMA_CQPSQ_STAG_STAGLEN GENMASK_ULL(45, 0) +#define IRDMA_CQPSQ_STAG_KEY_S 0 +#define IRDMA_CQPSQ_STAG_KEY GENMASK_ULL(7, 0) +#define IRDMA_CQPSQ_STAG_IDX_S 8 +#define IRDMA_CQPSQ_STAG_IDX GENMASK_ULL(31, 8) +#define IRDMA_CQPSQ_STAG_PARENTSTAGIDX_S 32 +#define IRDMA_CQPSQ_STAG_PARENTSTAGIDX GENMASK_ULL(55, 32) +#define IRDMA_CQPSQ_STAG_MR_S 43 +#define IRDMA_CQPSQ_STAG_MR BIT_ULL(43) +#define IRDMA_CQPSQ_STAG_MWTYPE_S 42 +#define IRDMA_CQPSQ_STAG_MWTYPE BIT_ULL(42) +#define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY_S 58 +#define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY BIT_ULL(58) + +#define IRDMA_CQPSQ_STAG_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S +#define IRDMA_CQPSQ_STAG_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M +#define IRDMA_CQPSQ_STAG_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE +#define IRDMA_CQPSQ_STAG_HPAGESIZE_S 46 +#define IRDMA_CQPSQ_STAG_HPAGESIZE GENMASK_ULL(47, 46) +#define IRDMA_CQPSQ_STAG_ARIGHTS_S 48 +#define IRDMA_CQPSQ_STAG_ARIGHTS GENMASK_ULL(52, 48) +#define IRDMA_CQPSQ_STAG_REMACCENABLED_S 53 +#define IRDMA_CQPSQ_STAG_REMACCENABLED BIT_ULL(53) +#define IRDMA_CQPSQ_STAG_VABASEDTO_S 59 +#define IRDMA_CQPSQ_STAG_VABASEDTO BIT_ULL(59) +#define IRDMA_CQPSQ_STAG_USEHMCFNIDX_S 60 +#define IRDMA_CQPSQ_STAG_USEHMCFNIDX BIT_ULL(60) +#define IRDMA_CQPSQ_STAG_USEPFRID_S 61 +#define IRDMA_CQPSQ_STAG_USEPFRID BIT_ULL(61) +#define IRDMA_CQPSQ_STAG_PLACEMENTTYPE_S 54 +#define IRDMA_CQPSQ_STAG_PLACEMENTTYPE GENMASK_ULL(57, 54) +#define IRDMA_CQPSQ_STAG_NON_CACHED_S 55 +#define IRDMA_CQPSQ_STAG_NON_CACHED BIT_ULL(55) + +#define IRDMA_CQPSQ_STAG_PBA_S IRDMA_CQPHC_QPCTX_S +#define IRDMA_CQPSQ_STAG_PBA IRDMA_CQPHC_QPCTX +#define IRDMA_CQPSQ_STAG_HMCFNIDX_S 0 +#define IRDMA_CQPSQ_STAG_HMCFNIDX GENMASK_ULL(15, 0) + +#define IRDMA_CQPSQ_STAG_PASID_S 32 +#define IRDMA_CQPSQ_STAG_PASID GENMASK_ULL(51, 32) +#define IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN_S 61 +#define IRDMA_CQPSQ_STAG_REMOTE_ATOMIC_EN BIT_ULL(61) + +#define IRDMA_CQPSQ_STAG_USE_ASO_S 54 +#define IRDMA_CQPSQ_STAG_USE_ASO BIT_ULL(54) +#define IRDMA_CQPSQ_STAG_ASO_HOST_ID_S 51 +#define IRDMA_CQPSQ_STAG_ASO_HOST_ID GENMASK_ULL(53, 51) +#define IRDMA_CQPSQ_STAG_ASO_VM_VF_TYPE_S 49 +#define IRDMA_CQPSQ_STAG_ASO_VM_VF_TYPE GENMASK_ULL(50, 49) +#define IRDMA_CQPSQ_STAG_ASO_VM_VF_NUM_S 38 +#define IRDMA_CQPSQ_STAG_ASO_VM_VF_NUM GENMASK_ULL(48, 38) +#define IRDMA_CQPSQ_STAG_ASO_PF_NUM_S 32 +#define IRDMA_CQPSQ_STAG_ASO_PF_NUM GENMASK_ULL(37, 32) + +#define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX_S 0 +#define IRDMA_CQPSQ_STAG_FIRSTPMPBLIDX GENMASK_ULL(27, 0) + +#define IRDMA_CQPSQ_QUERYSTAG_IDX_S IRDMA_CQPSQ_STAG_IDX_S +#define IRDMA_CQPSQ_QUERYSTAG_IDX IRDMA_CQPSQ_STAG_IDX +#define IRDMA_CQPSQ_MLM_TABLEIDX_S 0 +#define IRDMA_CQPSQ_MLM_TABLEIDX GENMASK_ULL(5, 0) +#define IRDMA_CQPSQ_MLM_FREEENTRY_S 62 +#define IRDMA_CQPSQ_MLM_FREEENTRY BIT_ULL(62) +#define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT_S 61 +#define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT BIT_ULL(61) +#define IRDMA_CQPSQ_MLM_MAC0_S 0 +#define IRDMA_CQPSQ_MLM_MAC0 GENMASK_ULL(7, 0) +#define IRDMA_CQPSQ_MLM_MAC1_S 8 +#define IRDMA_CQPSQ_MLM_MAC1 GENMASK_ULL(15, 8) +#define IRDMA_CQPSQ_MLM_MAC2_S 16 +#define IRDMA_CQPSQ_MLM_MAC2 GENMASK_ULL(23, 16) +#define IRDMA_CQPSQ_MLM_MAC3_S 24 +#define IRDMA_CQPSQ_MLM_MAC3 GENMASK_ULL(31, 24) +#define IRDMA_CQPSQ_MLM_MAC4_S 32 +#define IRDMA_CQPSQ_MLM_MAC4 GENMASK_ULL(39, 32) +#define IRDMA_CQPSQ_MLM_MAC5_S 40 +#define IRDMA_CQPSQ_MLM_MAC5 GENMASK_ULL(47, 40) +#define IRDMA_CQPSQ_MAT_REACHMAX_S 0 +#define IRDMA_CQPSQ_MAT_REACHMAX GENMASK_ULL(31, 0) +#define IRDMA_CQPSQ_MAT_MACADDR_S 0 +#define IRDMA_CQPSQ_MAT_MACADDR GENMASK_ULL(47, 0) +#define IRDMA_CQPSQ_MAT_ARPENTRYIDX_S 0 +#define IRDMA_CQPSQ_MAT_ARPENTRYIDX GENMASK_ULL(11, 0) +#define IRDMA_CQPSQ_MAT_ENTRYVALID_S 42 +#define IRDMA_CQPSQ_MAT_ENTRYVALID BIT_ULL(42) +#define IRDMA_CQPSQ_MAT_PERMANENT_S 43 +#define IRDMA_CQPSQ_MAT_PERMANENT BIT_ULL(43) +#define IRDMA_CQPSQ_MAT_QUERY_S 44 +#define IRDMA_CQPSQ_MAT_QUERY BIT_ULL(44) +#define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT_S 0 +#define IRDMA_CQPSQ_MVPBP_PD_ENTRY_CNT GENMASK_ULL(9, 0) +#define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX_S 16 +#define IRDMA_CQPSQ_MVPBP_FIRST_PD_INX GENMASK_ULL(24, 16) +#define IRDMA_CQPSQ_MVPBP_SD_INX_S 32 +#define IRDMA_CQPSQ_MVPBP_SD_INX GENMASK_ULL(43, 32) +#define IRDMA_CQPSQ_MVPBP_INV_PD_ENT_S 62 +#define IRDMA_CQPSQ_MVPBP_INV_PD_ENT BIT_ULL(62) +#define IRDMA_CQPSQ_MVPBP_PD_PLPBA_S 3 +#define IRDMA_CQPSQ_MVPBP_PD_PLPBA GENMASK_ULL(63, 3) + +/* Manage Push Page - MPP */ +#define IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1 0xffff +#define IRDMA_INVALID_PUSH_PAGE_INDEX 0xffffffff + +#define IRDMA_CQPSQ_MPP_QS_HANDLE_S 0 +#define IRDMA_CQPSQ_MPP_QS_HANDLE GENMASK_ULL(12, 0) +#define IRDMA_CQPSQ_MPP_PPIDX_S 0 +#define IRDMA_CQPSQ_MPP_PPIDX GENMASK_ULL(31, 0) +#define IRDMA_CQPSQ_MPP_PPTYPE_S 60 +#define IRDMA_CQPSQ_MPP_PPTYPE GENMASK_ULL(61, 60) + +#define IRDMA_CQPSQ_MPP_HMC_FN_ID_S 0 +#define IRDMA_CQPSQ_MPP_HMC_FN_ID GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_MPP_USE_HMC_FN_ID_S 55 +#define IRDMA_CQPSQ_MPP_USE_HMC_FN_ID BIT_ULL(55) +#define IRDMA_CQPSQ_MPP_PAGE_TYPE_S 56 +#define IRDMA_CQPSQ_MPP_PAGE_TYPE GENMASK_ULL(59, 56) + +#define IRDMA_CQPSQ_MPP_FREE_PAGE_S 62 +#define IRDMA_CQPSQ_MPP_FREE_PAGE BIT_ULL(62) + +/* Upload Context - UCTX */ +#define IRDMA_CQPSQ_UCTX_QPCTXADDR_S IRDMA_CQPHC_QPCTX_S +#define IRDMA_CQPSQ_UCTX_QPCTXADDR IRDMA_CQPHC_QPCTX +#define IRDMA_CQPSQ_UCTX_QPID_S 0 +#define IRDMA_CQPSQ_UCTX_QPID GENMASK_ULL(23, 0) +#define IRDMA_CQPSQ_UCTX_QPTYPE_S 48 +#define IRDMA_CQPSQ_UCTX_QPTYPE GENMASK_ULL(51, 48) + +#define IRDMA_CQPSQ_UCTX_RAWFORMAT_S 61 +#define IRDMA_CQPSQ_UCTX_RAWFORMAT BIT_ULL(61) +#define IRDMA_CQPSQ_UCTX_FREEZEQP_S 62 +#define IRDMA_CQPSQ_UCTX_FREEZEQP BIT_ULL(62) +#define IRDMA_CQPSQ_MHMC_VFIDX_S 0 +#define IRDMA_CQPSQ_MHMC_VFIDX GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_MHMC_FREEPMFN_S 62 +#define IRDMA_CQPSQ_MHMC_FREEPMFN BIT_ULL(62) + +#define IRDMA_CQPSQ_MHMC_SADOMAIN_S 16 +#define IRDMA_CQPSQ_MHMC_SADOMAIN GENMASK_ULL(31, 16) +#define IRDMA_CQPSQ_MHMC_LOCALFENCE_S 41 +#define IRDMA_CQPSQ_MHMC_LOCALFENCE BIT_ULL(41) +#define IRDMA_CQPSQ_MHMC_IGNOREPASIDCEQ_S 42 +#define IRDMA_CQPSQ_MHMC_IGNOREPASIDCEQ BIT_ULL(42) +#define IRDMA_CQPSQ_MHMC_RDMABEHAVIOR_S 47 +#define IRDMA_CQPSQ_MHMC_RDMABEHAVIOR BIT_ULL(47) +#define IRDMA_CQPSQ_MHMC_PASIDVALID_S 52 +#define IRDMA_CQPSQ_MHMC_PASIDVALID BIT_ULL(52) +#define IRDMA_CQPSQ_MHMC_PROTFAM_S 48 +#define IRDMA_CQPSQ_MHMC_PROTFAM GENMASK_ULL(51, 48) +#define IRDMA_CQPSQ_MHMC_PASID_S 0 +#define IRDMA_CQPSQ_MHMC_PASID GENMASK_ULL(19, 0) +#define IRDMA_CQPSQ_MHMC_PFNUM_S 0 +#define IRDMA_CQPSQ_MHMC_PFNUM GENMASK_ULL(5, 0) +#define IRDMA_CQPSQ_MHMC_HOST_ID_S 13 +#define IRDMA_CQPSQ_MHMC_HOST_ID GENMASK_ULL(15, 13) + +#define IRDMA_CQPSQ_MHMC_VMVFTYPE_VF 0 +#define IRDMA_CQPSQ_MHMC_VMVFTYPE_VM 1 +#define IRDMA_CQPSQ_MHMC_VMVFTYPE_PF 2 +#define IRDMA_CQPSQ_MHMC_VMVFTYPE_S 8 +#define IRDMA_CQPSQ_MHMC_VMVFTYPE GENMASK_ULL(9, 8) + +#define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE_S 0 +#define IRDMA_CQPSQ_SHMCRP_HMC_PROFILE GENMASK_ULL(2, 0) +#define IRDMA_CQPSQ_SHMCRP_VFNUM_S 32 +#define IRDMA_CQPSQ_SHMCRP_VFNUM GENMASK_ULL(37, 32) +#define IRDMA_CQPSQ_CEQ_CEQSIZE_S 0 +#define IRDMA_CQPSQ_CEQ_CEQSIZE GENMASK_ULL(21, 0) +#define IRDMA_CQPSQ_CEQ_CEQID_S 0 +#define IRDMA_CQPSQ_CEQ_CEQID GENMASK_ULL(9, 0) + +#define IRDMA_CQPSQ_CEQ_CEQID_HIGH_S 10 +#define IRDMA_CQPSQ_CEQ_CEQID_HIGH GENMASK_ULL(15, 10) + +#define IRDMA_CQPSQ_CEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S +#define IRDMA_CQPSQ_CEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M +#define IRDMA_CQPSQ_CEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE +#define IRDMA_CQPSQ_CEQ_VMAP_S 47 +#define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47) +#define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE_S 46 +#define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE BIT_ULL(46) +#define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX_S 0 +#define IRDMA_CQPSQ_CEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0) +#define IRDMA_CQPSQ_AEQ_AEQECNT_S 0 +#define IRDMA_CQPSQ_AEQ_AEQECNT GENMASK_ULL(18, 0) + +#define IRDMA_CQPSQ_AEQ_LPBLSIZE_S IRDMA_CQPSQ_CQ_LPBLSIZE_S +#define IRDMA_CQPSQ_AEQ_LPBLSIZE_M IRDMA_CQPSQ_CQ_LPBLSIZE_M +#define IRDMA_CQPSQ_AEQ_LPBLSIZE IRDMA_CQPSQ_CQ_LPBLSIZE +#define IRDMA_CQPSQ_AEQ_VMAP_S 47 +#define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47) +#define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX_S 0 +#define IRDMA_CQPSQ_AEQ_FIRSTPMPBLIDX GENMASK_ULL(27, 0) + +#define IRDMA_COMMIT_FPM_QPCNT_S 0 +#define IRDMA_COMMIT_FPM_QPCNT GENMASK_ULL(18, 0) + +#define IRDMA_COMMIT_FPM_BASE_S 32 +#define IRDMA_CQPSQ_CFPM_HMCFNID_S 0 +#define IRDMA_CQPSQ_CFPM_HMCFNID GENMASK_ULL(15, 0) + +#define IRDMA_CQPSQ_FWQE_AECODE_S 0 +#define IRDMA_CQPSQ_FWQE_AECODE GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_FWQE_AESOURCE_S 16 +#define IRDMA_CQPSQ_FWQE_AESOURCE GENMASK_ULL(19, 16) +#define IRDMA_CQPSQ_FWQE_RQMNERR_S 0 +#define IRDMA_CQPSQ_FWQE_RQMNERR GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_FWQE_RQMJERR_S 16 +#define IRDMA_CQPSQ_FWQE_RQMJERR GENMASK_ULL(31, 16) +#define IRDMA_CQPSQ_FWQE_SQMNERR_S 32 +#define IRDMA_CQPSQ_FWQE_SQMNERR GENMASK_ULL(47, 32) +#define IRDMA_CQPSQ_FWQE_SQMJERR_S 48 +#define IRDMA_CQPSQ_FWQE_SQMJERR GENMASK_ULL(63, 48) +#define IRDMA_CQPSQ_FWQE_QPID_S 0 +#define IRDMA_CQPSQ_FWQE_QPID GENMASK_ULL(23, 0) +#define IRDMA_CQPSQ_FWQE_GENERATE_AE_S 59 +#define IRDMA_CQPSQ_FWQE_GENERATE_AE BIT_ULL(59) +#define IRDMA_CQPSQ_FWQE_USERFLCODE_S 60 +#define IRDMA_CQPSQ_FWQE_USERFLCODE BIT_ULL(60) +#define IRDMA_CQPSQ_FWQE_FLUSHSQ_S 61 +#define IRDMA_CQPSQ_FWQE_FLUSHSQ BIT_ULL(61) +#define IRDMA_CQPSQ_FWQE_FLUSHRQ_S 62 +#define IRDMA_CQPSQ_FWQE_FLUSHRQ BIT_ULL(62) +#define IRDMA_CQPSQ_FWQE_ERR_SQ_IDX_VALID_S 42 +#define IRDMA_CQPSQ_FWQE_ERR_SQ_IDX_VALID BIT_ULL(42) +#define IRDMA_CQPSQ_FWQE_ERR_SQ_IDX_S 32 +#define IRDMA_CQPSQ_FWQE_ERR_SQ_IDX GENMASK_ULL(49, 32) +#define IRDMA_CQPSQ_MAPT_PORT_S 0 +#define IRDMA_CQPSQ_MAPT_PORT GENMASK_ULL(15, 0) +#define IRDMA_CQPSQ_MAPT_ADDPORT_S 62 +#define IRDMA_CQPSQ_MAPT_ADDPORT BIT_ULL(62) +#define IRDMA_CQPSQ_UPESD_SDCMD_S 0 +#define IRDMA_CQPSQ_UPESD_SDCMD GENMASK_ULL(31, 0) +#define IRDMA_CQPSQ_UPESD_SDDATALOW_S 0 +#define IRDMA_CQPSQ_UPESD_SDDATALOW GENMASK_ULL(31, 0) +#define IRDMA_CQPSQ_UPESD_SDDATAHI_S 32 +#define IRDMA_CQPSQ_UPESD_SDDATAHI GENMASK_ULL(63, 32) +#define IRDMA_CQPSQ_UPESD_ENTRY_VALID_S 63 +#define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63) + +#define IRDMA_CQPSQ_UPESD_BM_PF 0 +#define IRDMA_CQPSQ_UPESD_BM_CP_LM 1 +#define IRDMA_CQPSQ_UPESD_BM_AXF 2 +#define IRDMA_CQPSQ_UPESD_BM_LM 4 +#define IRDMA_CQPSQ_UPESD_BM_S 32 +#define IRDMA_CQPSQ_UPESD_BM GENMASK_ULL(34, 32) +#define IRDMA_CQPSQ_UPESD_ENTRY_COUNT_S 0 +#define IRDMA_CQPSQ_UPESD_ENTRY_COUNT GENMASK_ULL(3, 0) +#define IRDMA_CQPSQ_UPESD_SKIP_ENTRY_S 7 +#define IRDMA_CQPSQ_UPESD_SKIP_ENTRY BIT_ULL(7) + +/* Suspend QP */ +#define IRDMA_CQPSQ_SUSPENDQP_QPID_S 0 +#define IRDMA_CQPSQ_SUSPENDQP_QPID GENMASK_ULL(23, 0) +#define IRDMA_CQPSQ_RESUMEQP_QSHANDLE_S 0 +#define IRDMA_CQPSQ_RESUMEQP_QSHANDLE GENMASK_ULL(31, 0) + +#define IRDMA_CQPSQ_RESUMEQP_QPID_S IRDMA_CQPSQ_SUSPENDQP_QPID_S +#define IRDMA_CQPSQ_RESUMEQP_QPID_M IRDMA_CQPSQ_SUSPENDQP_QPID_M +#define IRDMA_CQPSQ_RESUMEQP_QPID IRDMA_CQPSQ_SUSPENDQP_QPID + +#define IRDMA_CQPSQ_MIN_STAG_INVALID 0x0001 +#define IRDMA_CQPSQ_MIN_SUSPEND_PND 0x0005 +#define IRDMA_CQPSQ_MIN_DEF_CMPL 0x0006 +#define IRDMA_CQPSQ_MIN_OOO_CMPL 0x0007 + +#define IRDMA_CQPSQ_MAJ_NO_ERROR 0x0000 +#define IRDMA_CQPSQ_MAJ_OBJCACHE_ERROR 0xF000 +#define IRDMA_CQPSQ_MAJ_CNTXTCACHE_ERROR 0xF001 +#define IRDMA_CQPSQ_MAJ_ERROR 0xFFFF + +#define IRDMAQPC_DDP_VER_S 0 +#define IRDMAQPC_DDP_VER GENMASK_ULL(1, 0) +#define IRDMAQPC_IBRDENABLE_S 2 +#define IRDMAQPC_IBRDENABLE BIT_ULL(2) +#define IRDMAQPC_IPV4_S 3 +#define IRDMAQPC_IPV4 BIT_ULL(3) +#define IRDMAQPC_NONAGLE_S 4 +#define IRDMAQPC_NONAGLE BIT_ULL(4) +#define IRDMAQPC_INSERTVLANTAG_S 5 +#define IRDMAQPC_INSERTVLANTAG BIT_ULL(5) +#define IRDMAQPC_ISQP1_S 6 +#define IRDMAQPC_ISQP1 BIT_ULL(6) +#define IRDMAQPC_TIMESTAMP_S 7 +#define IRDMAQPC_TIMESTAMP BIT_ULL(7) +#define IRDMAQPC_RQWQESIZE_S 8 +#define IRDMAQPC_RQWQESIZE GENMASK_ULL(9, 8) +#define IRDMAQPC_INSERTL2TAG2_S 11 +#define IRDMAQPC_INSERTL2TAG2 BIT_ULL(11) +#define IRDMAQPC_LIMIT_S 12 +#define IRDMAQPC_LIMIT GENMASK_ULL(13, 12) + +#define IRDMAQPC_USE_SRQ_S 10 +#define IRDMAQPC_USE_SRQ BIT_ULL(10) +#define IRDMAQPC_SRQ_ID_S 0 +#define IRDMAQPC_SRQ_ID GENMASK_ULL(15, 0) +#define IRDMAQPC_PASID_S 0 +#define IRDMAQPC_PASID GENMASK_ULL(19, 0) +#define IRDMAQPC_PASID_VALID_S 11 +#define IRDMAQPC_PASID_VALID BIT_ULL(11) + +#define IRDMAQPC_ECN_EN_S 14 +#define IRDMAQPC_ECN_EN BIT_ULL(14) +#define IRDMAQPC_DROPOOOSEG_S 15 +#define IRDMAQPC_DROPOOOSEG BIT_ULL(15) +#define IRDMAQPC_DUPACK_THRESH_S 16 +#define IRDMAQPC_DUPACK_THRESH GENMASK_ULL(18, 16) +#define IRDMAQPC_ERR_RQ_IDX_VALID_S 19 +#define IRDMAQPC_ERR_RQ_IDX_VALID BIT_ULL(19) +#define IRDMAQPC_DIS_VLAN_CHECKS_S 19 +#define IRDMAQPC_DIS_VLAN_CHECKS GENMASK_ULL(21, 19) +#define IRDMAQPC_DC_TCP_EN_S 25 +#define IRDMAQPC_DC_TCP_EN BIT_ULL(25) +#define IRDMAQPC_RCVTPHEN_S 28 +#define IRDMAQPC_RCVTPHEN BIT_ULL(28) +#define IRDMAQPC_XMITTPHEN_S 29 +#define IRDMAQPC_XMITTPHEN BIT_ULL(29) +#define IRDMAQPC_RQTPHEN_S 30 +#define IRDMAQPC_RQTPHEN BIT_ULL(30) +#define IRDMAQPC_SQTPHEN_S 31 +#define IRDMAQPC_SQTPHEN BIT_ULL(31) +#define IRDMAQPC_PPIDX_S 32 +#define IRDMAQPC_PPIDX GENMASK_ULL(41, 32) +#define IRDMAQPC_PMENA_S 47 +#define IRDMAQPC_PMENA BIT_ULL(47) +#define IRDMAQPC_RDMAP_VER_S 62 +#define IRDMAQPC_RDMAP_VER GENMASK_ULL(63, 62) +#define IRDMAQPC_ROCE_TVER_S 60 +#define IRDMAQPC_ROCE_TVER GENMASK_ULL(63, 60) + +#define IRDMAQPC_SQADDR_S IRDMA_CQPHC_QPCTX_S +#define IRDMAQPC_SQADDR IRDMA_CQPHC_QPCTX + +#define IRDMAQPC_RQADDR_S IRDMA_CQPHC_QPCTX_S +#define IRDMAQPC_RQADDR IRDMA_CQPHC_QPCTX +#define IRDMAQPC_TTL_S 0 +#define IRDMAQPC_TTL GENMASK_ULL(7, 0) +#define IRDMAQPC_RQSIZE_S 8 +#define IRDMAQPC_RQSIZE GENMASK_ULL(11, 8) +#define IRDMAQPC_SQSIZE_S 12 +#define IRDMAQPC_SQSIZE GENMASK_ULL(15, 12) +#define IRDMAQPC_GEN1_SRCMACADDRIDX_S 16 +#define IRDMAQPC_GEN1_SRCMACADDRIDX GENMASK(21, 16) +#define IRDMAQPC_AVOIDSTRETCHACK_S 23 +#define IRDMAQPC_AVOIDSTRETCHACK BIT_ULL(23) +#define IRDMAQPC_TOS_S 24 +#define IRDMAQPC_TOS GENMASK_ULL(31, 24) +#define IRDMAQPC_SRCPORTNUM_S 32 +#define IRDMAQPC_SRCPORTNUM GENMASK_ULL(47, 32) +#define IRDMAQPC_DESTPORTNUM_S 48 +#define IRDMAQPC_DESTPORTNUM GENMASK_ULL(63, 48) +#define IRDMAQPC_DESTIPADDR0_S 32 +#define IRDMAQPC_DESTIPADDR0 GENMASK_ULL(63, 32) +#define IRDMAQPC_DESTIPADDR1_S 0 +#define IRDMAQPC_DESTIPADDR1 GENMASK_ULL(31, 0) +#define IRDMAQPC_DESTIPADDR2_S 32 +#define IRDMAQPC_DESTIPADDR2 GENMASK_ULL(63, 32) +#define IRDMAQPC_DESTIPADDR3_S 0 +#define IRDMAQPC_DESTIPADDR3 GENMASK_ULL(31, 0) +#define IRDMAQPC_SNDMSS_S 16 +#define IRDMAQPC_SNDMSS GENMASK_ULL(29, 16) +#define IRDMAQPC_SYN_RST_HANDLING_S 30 +#define IRDMAQPC_SYN_RST_HANDLING GENMASK_ULL(31, 30) +#define IRDMAQPC_VLANTAG_S 32 +#define IRDMAQPC_VLANTAG GENMASK_ULL(47, 32) +#define IRDMAQPC_ARPIDX_S 48 +#define IRDMAQPC_ARPIDX GENMASK_ULL(63, 48) +#define IRDMAQPC_FLOWLABEL_S 0 +#define IRDMAQPC_FLOWLABEL GENMASK_ULL(19, 0) +#define IRDMAQPC_WSCALE_S 20 +#define IRDMAQPC_WSCALE BIT_ULL(20) +#define IRDMAQPC_KEEPALIVE_S 21 +#define IRDMAQPC_KEEPALIVE BIT_ULL(21) +#define IRDMAQPC_IGNORE_TCP_OPT_S 22 +#define IRDMAQPC_IGNORE_TCP_OPT BIT_ULL(22) +#define IRDMAQPC_IGNORE_TCP_UNS_OPT_S 23 +#define IRDMAQPC_IGNORE_TCP_UNS_OPT BIT_ULL(23) +#define IRDMAQPC_TCPSTATE_S 28 +#define IRDMAQPC_TCPSTATE GENMASK_ULL(31, 28) +#define IRDMAQPC_RCVSCALE_S 32 +#define IRDMAQPC_RCVSCALE GENMASK_ULL(35, 32) +#define IRDMAQPC_SNDSCALE_S 40 +#define IRDMAQPC_SNDSCALE GENMASK_ULL(43, 40) +#define IRDMAQPC_PDIDX_S 48 +#define IRDMAQPC_PDIDX GENMASK_ULL(63, 48) +#define IRDMAQPC_PDIDXHI_S 20 +#define IRDMAQPC_PDIDXHI GENMASK_ULL(21, 20) +#define IRDMAQPC_PKEY_S 32 +#define IRDMAQPC_PKEY GENMASK_ULL(47, 32) +#define IRDMAQPC_ACKCREDITS_S 20 +#define IRDMAQPC_ACKCREDITS GENMASK_ULL(24, 20) +#define IRDMAQPC_QKEY_S 32 +#define IRDMAQPC_QKEY GENMASK_ULL(63, 32) +#define IRDMAQPC_DESTQP_S 0 +#define IRDMAQPC_DESTQP GENMASK_ULL(23, 0) +#define IRDMAQPC_KALIVE_TIMER_MAX_PROBES_S 16 +#define IRDMAQPC_KALIVE_TIMER_MAX_PROBES GENMASK_ULL(23, 16) +#define IRDMAQPC_KEEPALIVE_INTERVAL_S 24 +#define IRDMAQPC_KEEPALIVE_INTERVAL GENMASK_ULL(31, 24) +#define IRDMAQPC_TIMESTAMP_RECENT_S 0 +#define IRDMAQPC_TIMESTAMP_RECENT GENMASK_ULL(31, 0) +#define IRDMAQPC_TIMESTAMP_AGE_S 32 +#define IRDMAQPC_TIMESTAMP_AGE GENMASK_ULL(63, 32) +#define IRDMAQPC_SNDNXT_S 0 +#define IRDMAQPC_SNDNXT GENMASK_ULL(31, 0) +#define IRDMAQPC_ISN_S 32 +#define IRDMAQPC_ISN GENMASK_ULL(55, 32) +#define IRDMAQPC_PSNNXT_S 0 +#define IRDMAQPC_PSNNXT GENMASK_ULL(23, 0) +#define IRDMAQPC_LSN_S 32 +#define IRDMAQPC_LSN GENMASK_ULL(55, 32) +#define IRDMAQPC_SNDWND_S 32 +#define IRDMAQPC_SNDWND GENMASK_ULL(63, 32) +#define IRDMAQPC_RCVNXT_S 0 +#define IRDMAQPC_RCVNXT GENMASK_ULL(31, 0) +#define IRDMAQPC_EPSN_S 0 +#define IRDMAQPC_EPSN GENMASK_ULL(23, 0) +#define IRDMAQPC_RCVWND_S 32 +#define IRDMAQPC_RCVWND GENMASK_ULL(63, 32) +#define IRDMAQPC_SNDMAX_S 0 +#define IRDMAQPC_SNDMAX GENMASK_ULL(31, 0) +#define IRDMAQPC_SNDUNA_S 32 +#define IRDMAQPC_SNDUNA GENMASK_ULL(63, 32) +#define IRDMAQPC_PSNMAX_S 0 +#define IRDMAQPC_PSNMAX GENMASK_ULL(23, 0) +#define IRDMAQPC_PSNUNA_S 32 +#define IRDMAQPC_PSNUNA GENMASK_ULL(55, 32) +#define IRDMAQPC_SRTT_S 0 +#define IRDMAQPC_SRTT GENMASK_ULL(31, 0) +#define IRDMAQPC_RTTVAR_S 32 +#define IRDMAQPC_RTTVAR GENMASK_ULL(63, 32) +#define IRDMAQPC_SSTHRESH_S 0 +#define IRDMAQPC_SSTHRESH GENMASK_ULL(31, 0) +#define IRDMAQPC_CWND_S 32 +#define IRDMAQPC_CWND GENMASK_ULL(63, 32) +#define IRDMAQPC_CWNDROCE_S 32 +#define IRDMAQPC_CWNDROCE GENMASK_ULL(55, 32) +#define IRDMAQPC_SNDWL1_S 0 +#define IRDMAQPC_SNDWL1 GENMASK_ULL(31, 0) +#define IRDMAQPC_SNDWL2_S 32 +#define IRDMAQPC_SNDWL2 GENMASK_ULL(63, 32) +#define IRDMAQPC_MINRNR_TIMER_S 0 +#define IRDMAQPC_MINRNR_TIMER GENMASK_ULL(4, 0) +#define IRDMAQPC_ERR_RQ_IDX_S 32 +#define IRDMAQPC_ERR_RQ_IDX GENMASK_ULL(46, 32) +#define IRDMAQPC_RTOMIN_S 57 +#define IRDMAQPC_RTOMIN GENMASK_ULL(63, 57) +#define IRDMAQPC_MAXSNDWND_S 0 +#define IRDMAQPC_MAXSNDWND GENMASK_ULL(31, 0) +#define IRDMAQPC_REXMIT_THRESH_S 48 +#define IRDMAQPC_REXMIT_THRESH GENMASK_ULL(53, 48) +#define IRDMAQPC_RNRNAK_THRESH_S 54 +#define IRDMAQPC_RNRNAK_THRESH GENMASK_ULL(56, 54) +#define IRDMAQPC_TXCQNUM_S 0 +#define IRDMAQPC_TXCQNUM GENMASK_ULL(18, 0) +#define IRDMAQPC_RXCQNUM_S 32 +#define IRDMAQPC_RXCQNUM GENMASK_ULL(50, 32) +#define IRDMAQPC_STAT_INDEX_S 0 +#define IRDMAQPC_STAT_INDEX GENMASK_ULL(6, 0) +#define IRDMAQPC_Q2ADDR_S 8 +#define IRDMAQPC_Q2ADDR GENMASK_ULL(63, 8) +#define IRDMAQPC_LASTBYTESENT_S 0 +#define IRDMAQPC_LASTBYTESENT GENMASK_ULL(7, 0) +#define IRDMAQPC_MACADDRESS_S 16 +#define IRDMAQPC_MACADDRESS GENMASK_ULL(63, 16) +#define IRDMAQPC_ORDSIZE_S 0 +#define IRDMAQPC_ORDSIZE GENMASK_ULL(7, 0) + +#define IRDMAQPC_LOCALACKTIMEOUT_S 8 +#define IRDMAQPC_LOCALACKTIMEOUT GENMASK_ULL(12, 8) +#define IRDMAQPC_RNRNAK_TMR_S 0 +#define IRDMAQPC_RNRNAK_TMR GENMASK_ULL(4, 0) +#define IRDMAQPC_ORDSIZE_GEN3_S 0 +#define IRDMAQPC_ORDSIZE_GEN3 GENMASK_ULL(10, 0) +#define IRDMAQPC_REMOTE_ATOMIC_EN_S 18 +#define IRDMAQPC_REMOTE_ATOMIC_EN BIT_ULL(18) +#define IRDMAQPC_STAT_INDEX_GEN3_S 32 +#define IRDMAQPC_STAT_INDEX_GEN3 GENMASK_ULL(47, 32) +#define IRDMAQPC_PKT_LIMIT_S 48 +#define IRDMAQPC_PKT_LIMIT GENMASK_ULL(55, 48) + +#define IRDMAQPC_IRDSIZE_S 16 +#define IRDMAQPC_IRDSIZE GENMASK_ULL(18, 16) + +#define IRDMAQPC_IRDSIZE_GEN3_S 14 +#define IRDMAQPC_IRDSIZE_GEN3 GENMASK_ULL(17, 14) + +#define IRDMAQPC_UDPRIVCQENABLE_S 19 +#define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19) +#define IRDMAQPC_WRRDRSPOK_S 20 +#define IRDMAQPC_WRRDRSPOK BIT_ULL(20) +#define IRDMAQPC_RDOK_S 21 +#define IRDMAQPC_RDOK BIT_ULL(21) +#define IRDMAQPC_SNDMARKERS_S 22 +#define IRDMAQPC_SNDMARKERS BIT_ULL(22) +#define IRDMAQPC_DCQCNENABLE_S 22 +#define IRDMAQPC_DCQCNENABLE BIT_ULL(22) +#define IRDMAQPC_FW_CC_ENABLE_S 28 +#define IRDMAQPC_FW_CC_ENABLE BIT_ULL(28) +#define IRDMAQPC_RCVNOICRC_S 31 +#define IRDMAQPC_RCVNOICRC BIT_ULL(31) +#define IRDMAQPC_BINDEN_S 23 +#define IRDMAQPC_BINDEN BIT_ULL(23) +#define IRDMAQPC_FASTREGEN_S 24 +#define IRDMAQPC_FASTREGEN BIT_ULL(24) +#define IRDMAQPC_PRIVEN_S 25 +#define IRDMAQPC_PRIVEN BIT_ULL(25) +#define IRDMAQPC_TIMELYENABLE_S 27 +#define IRDMAQPC_TIMELYENABLE BIT_ULL(27) +#define IRDMAQPC_THIGH_S 52 +#define IRDMAQPC_THIGH GENMASK_ULL(63, 52) +#define IRDMAQPC_TLOW_S 32 +#define IRDMAQPC_TLOW GENMASK_ULL(39, 32) +#define IRDMAQPC_REMENDPOINTIDX_S 0 +#define IRDMAQPC_REMENDPOINTIDX GENMASK_ULL(16, 0) +#define IRDMAQPC_USESTATSINSTANCE_S 26 +#define IRDMAQPC_USESTATSINSTANCE BIT_ULL(26) +#define IRDMAQPC_IWARPMODE_S 28 +#define IRDMAQPC_IWARPMODE BIT_ULL(28) +#define IRDMAQPC_RCVMARKERS_S 29 +#define IRDMAQPC_RCVMARKERS BIT_ULL(29) +#define IRDMAQPC_ALIGNHDRS_S 30 +#define IRDMAQPC_ALIGNHDRS BIT_ULL(30) +#define IRDMAQPC_RCVNOMPACRC_S 31 +#define IRDMAQPC_RCVNOMPACRC BIT_ULL(31) +#define IRDMAQPC_RCVMARKOFFSET_S 32 +#define IRDMAQPC_RCVMARKOFFSET GENMASK_ULL(40, 32) +#define IRDMAQPC_SNDMARKOFFSET_S 48 +#define IRDMAQPC_SNDMARKOFFSET GENMASK_ULL(56, 48) + +#define IRDMAQPC_QPCOMPCTX_S IRDMA_CQPHC_QPCTX_S +#define IRDMAQPC_QPCOMPCTX IRDMA_CQPHC_QPCTX +#define IRDMAQPC_SQTPHVAL_S 0 +#define IRDMAQPC_SQTPHVAL GENMASK_ULL(7, 0) +#define IRDMAQPC_RQTPHVAL_S 8 +#define IRDMAQPC_RQTPHVAL GENMASK_ULL(15, 8) +#define IRDMAQPC_QSHANDLE_S 16 +#define IRDMAQPC_QSHANDLE GENMASK_ULL(25, 16) +#define IRDMAQPC_EXCEPTION_LAN_QUEUE_S 32 +#define IRDMAQPC_EXCEPTION_LAN_QUEUE GENMASK_ULL(43, 32) +#define IRDMAQPC_LOCAL_IPADDR3_S 0 +#define IRDMAQPC_LOCAL_IPADDR3 GENMASK_ULL(31, 0) +#define IRDMAQPC_LOCAL_IPADDR2_S 32 +#define IRDMAQPC_LOCAL_IPADDR2 GENMASK_ULL(63, 32) +#define IRDMAQPC_LOCAL_IPADDR1_S 0 +#define IRDMAQPC_LOCAL_IPADDR1 GENMASK_ULL(31, 0) +#define IRDMAQPC_LOCAL_IPADDR0_S 32 +#define IRDMAQPC_LOCAL_IPADDR0 GENMASK_ULL(63, 32) +#define IRDMA_FW_VER_MINOR_S 0 +#define IRDMA_FW_VER_MINOR GENMASK_ULL(15, 0) +#define IRDMA_FW_VER_MAJOR_S 16 +#define IRDMA_FW_VER_MAJOR GENMASK_ULL(31, 16) +#define IRDMA_FEATURE_INFO_S 0 +#define IRDMA_FEATURE_INFO GENMASK_ULL(47, 0) +#define IRDMA_FEATURE_CNT_S 32 +#define IRDMA_FEATURE_CNT GENMASK_ULL(47, 32) +#define IRDMA_FEATURE_TYPE_S 48 +#define IRDMA_FEATURE_TYPE GENMASK_ULL(63, 48) +#define IRDMA_RSVD_S 41 +#define IRDMA_RSVD GENMASK_ULL(55, 41) + +#define IRDMAQPSQ_OPCODE_S 32 +#define IRDMAQPSQ_OPCODE GENMASK_ULL(37, 32) +#define IRDMAQPSQ_COPY_HOST_PBL_S 43 +#define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43) +#define IRDMAQPSQ_ADDFRAGCNT_S 38 +#define IRDMAQPSQ_ADDFRAGCNT GENMASK_ULL(41, 38) +#define IRDMAQPSQ_PUSHWQE_S 56 +#define IRDMAQPSQ_PUSHWQE BIT_ULL(56) +#define IRDMAQPSQ_STREAMMODE_S 58 +#define IRDMAQPSQ_STREAMMODE BIT_ULL(58) +#define IRDMAQPSQ_WAITFORRCVPDU_S 59 +#define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59) +#define IRDMAQPSQ_READFENCE_S 60 +#define IRDMAQPSQ_READFENCE BIT_ULL(60) +#define IRDMAQPSQ_LOCALFENCE_S 61 +#define IRDMAQPSQ_LOCALFENCE BIT_ULL(61) +#define IRDMAQPSQ_UDPHEADER_S 61 +#define IRDMAQPSQ_UDPHEADER BIT_ULL(61) +#define IRDMAQPSQ_L4LEN_S 42 +#define IRDMAQPSQ_L4LEN GENMASK_ULL(45, 42) +#define IRDMAQPSQ_SIGCOMPL_S 62 +#define IRDMAQPSQ_SIGCOMPL BIT_ULL(62) +#define IRDMAQPSQ_VALID_S 63 +#define IRDMAQPSQ_VALID BIT_ULL(63) + +#define IRDMAQPSQ_FRAG_TO_S IRDMA_CQPHC_QPCTX_S +#define IRDMAQPSQ_FRAG_TO IRDMA_CQPHC_QPCTX +#define IRDMAQPSQ_FRAG_VALID_S 63 +#define IRDMAQPSQ_FRAG_VALID BIT_ULL(63) +#define IRDMAQPSQ_FRAG_LEN_S 32 +#define IRDMAQPSQ_FRAG_LEN GENMASK_ULL(62, 32) +#define IRDMAQPSQ_FRAG_STAG_S 0 +#define IRDMAQPSQ_FRAG_STAG GENMASK_ULL(31, 0) +#define IRDMAQPSQ_GEN1_FRAG_LEN_S 0 +#define IRDMAQPSQ_GEN1_FRAG_LEN GENMASK_ULL(31, 0) +#define IRDMAQPSQ_GEN1_FRAG_STAG_S 32 +#define IRDMAQPSQ_GEN1_FRAG_STAG GENMASK_ULL(63, 32) +#define IRDMAQPSQ_REMSTAGINV_S 0 +#define IRDMAQPSQ_REMSTAGINV GENMASK_ULL(31, 0) +#define IRDMAQPSQ_DESTQKEY_S 0 +#define IRDMAQPSQ_DESTQKEY GENMASK_ULL(31, 0) +#define IRDMAQPSQ_DESTQPN_S 32 +#define IRDMAQPSQ_DESTQPN GENMASK_ULL(55, 32) +#define IRDMAQPSQ_AHID_S 0 +#define IRDMAQPSQ_AHID GENMASK_ULL(24, 0) +#define IRDMAQPSQ_INLINEDATAFLAG_S 57 +#define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57) + +#define IRDMA_INLINE_VALID_S 7 +#define IRDMAQPSQ_INLINEDATALEN_S 48 +#define IRDMAQPSQ_INLINEDATALEN GENMASK_ULL(55, 48) +#define IRDMAQPSQ_IMMDATAFLAG_S 47 +#define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47) +#define IRDMAQPSQ_REPORTRTT_S 46 +#define IRDMAQPSQ_REPORTRTT BIT_ULL(46) + +#define IRDMAQPSQ_COMBINED_SGE_INLINE_RELIABLE_S 45 +#define IRDMAQPSQ_COMBINED_SGE_INLINE_RELIABLE BIT_ULL(45) +#define IRDMAQPSQ_COMBINED_SGE_INLINE_UNRELIABLE_S 63 +#define IRDMAQPSQ_COMBINED_SGE_INLINE_UNRELIABLE BIT_ULL(63) + +#define IRDMAQPSQ_FLUSH_MEM_LEN_S 0 +#define IRDMAQPSQ_FLUSH_MEM_LEN GENMASK_ULL(31, 0) +#define IRDMAQPSQ_SELECTIVITY_S 52 +#define IRDMAQPSQ_SELECTIVITY GENMASK_ULL(53, 52) +#define IRDMAQPSQ_PLACEMENT_TYPE_S 48 +#define IRDMAQPSQ_PLACEMENT_TYPE GENMASK_ULL(51, 48) +#define IRDMAQPSQ_IMMDATA_S 0 +#define IRDMAQPSQ_IMMDATA GENMASK_ULL(63, 0) +#define IRDMAQPSQ_REMSTAG_S 0 +#define IRDMAQPSQ_REMSTAG GENMASK_ULL(31, 0) + +#define IRDMAQPSQ_REMTO_S IRDMA_CQPHC_QPCTX_S +#define IRDMAQPSQ_REMTO IRDMA_CQPHC_QPCTX + +#define IRDMAQPSQ_STAGRIGHTS_S 48 +#define IRDMAQPSQ_STAGRIGHTS GENMASK_ULL(52, 48) +#define IRDMAQPSQ_VABASEDTO_S 53 +#define IRDMAQPSQ_VABASEDTO BIT_ULL(53) +#define IRDMAQPSQ_MEMWINDOWTYPE_S 54 +#define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54) + +#define IRDMAQPSQ_MWLEN_S IRDMA_CQPHC_QPCTX_S +#define IRDMAQPSQ_MWLEN IRDMA_CQPHC_QPCTX +#define IRDMAQPSQ_PARENTMRSTAG_S 32 +#define IRDMAQPSQ_PARENTMRSTAG GENMASK_ULL(63, 32) +#define IRDMAQPSQ_MWSTAG_S 0 +#define IRDMAQPSQ_MWSTAG GENMASK_ULL(31, 0) + +#define IRDMAQPSQ_BASEVA_TO_FBO_S IRDMA_CQPHC_QPCTX_S +#define IRDMAQPSQ_BASEVA_TO_FBO IRDMA_CQPHC_QPCTX + +#define IRDMAQPSQ_FLUSH_MR_S 20 +#define IRDMAQPSQ_FLUSH_MR BIT_ULL(20) +#define IRDMAQPSQ_REMOTE_ATOMICS_EN_S 55 +#define IRDMAQPSQ_REMOTE_ATOMICS_EN BIT_ULL(55) + +#define IRDMAQPSQ_LOCSTAG_S 0 +#define IRDMAQPSQ_LOCSTAG GENMASK_ULL(31, 0) + +#define IRDMAQPSQ_STAGKEY_S 0 +#define IRDMAQPSQ_STAGKEY GENMASK_ULL(7, 0) +#define IRDMAQPSQ_STAGINDEX_S 8 +#define IRDMAQPSQ_STAGINDEX GENMASK_ULL(31, 8) +#define IRDMAQPSQ_COPYHOSTPBLS_S 43 +#define IRDMAQPSQ_COPYHOSTPBLS BIT_ULL(43) +#define IRDMAQPSQ_LPBLSIZE_S 44 +#define IRDMAQPSQ_LPBLSIZE GENMASK_ULL(45, 44) +#define IRDMAQPSQ_HPAGESIZE_S 46 +#define IRDMAQPSQ_HPAGESIZE GENMASK_ULL(47, 46) +#define IRDMAQPSQ_STAGLEN_S 0 +#define IRDMAQPSQ_STAGLEN GENMASK_ULL(40, 0) +#define IRDMAQPSQ_FIRSTPMPBLIDXLO_S 48 +#define IRDMAQPSQ_FIRSTPMPBLIDXLO GENMASK_ULL(63, 48) +#define IRDMAQPSQ_FIRSTPMPBLIDXHI_S 0 +#define IRDMAQPSQ_FIRSTPMPBLIDXHI GENMASK_ULL(11, 0) +#define IRDMAQPSQ_PBLADDR_S 12 +#define IRDMAQPSQ_PBLADDR GENMASK_ULL(63, 12) + +/* iwarp QP RQ WQE common fields */ +#define IRDMAQPRQ_ADDFRAGCNT_S IRDMAQPSQ_ADDFRAGCNT_S +#define IRDMAQPRQ_ADDFRAGCNT IRDMAQPSQ_ADDFRAGCNT + +#define IRDMAQPRQ_VALID_S IRDMAQPSQ_VALID_S +#define IRDMAQPRQ_VALID IRDMAQPSQ_VALID + +#define IRDMAQPRQ_COMPLCTX_S IRDMA_CQPHC_QPCTX_S +#define IRDMAQPRQ_COMPLCTX IRDMA_CQPHC_QPCTX + +#define IRDMAQPRQ_FRAG_LEN_S IRDMAQPSQ_FRAG_LEN_S +#define IRDMAQPRQ_FRAG_LEN IRDMAQPSQ_FRAG_LEN + +#define IRDMAQPRQ_STAG_S IRDMAQPSQ_FRAG_STAG_S +#define IRDMAQPRQ_STAG IRDMAQPSQ_FRAG_STAG + +#define IRDMAQPRQ_TO_S IRDMAQPSQ_FRAG_TO_S +#define IRDMAQPRQ_TO IRDMAQPSQ_FRAG_TO + +#define IRDMAPFINT_OICR_HMC_ERR_M BIT(26) +#define IRDMAPFINT_OICR_PE_PUSH_M BIT(27) +#define IRDMAPFINT_OICR_PE_CRITERR_M BIT(28) + +#define IRDMA_QUERY_FPM_LOC_MEM_PAGES_S 32 +#define IRDMA_QUERY_FPM_LOC_MEM_PAGES GENMASK_ULL(63, 32) +#define IRDMA_QUERY_FPM_MAX_QPS_S 0 +#define IRDMA_QUERY_FPM_MAX_QPS GENMASK_ULL(31, 0) +#define IRDMA_QUERY_FPM_MAX_CQS_S 0 +#define IRDMA_QUERY_FPM_MAX_CQS GENMASK_ULL(31, 0) +#define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX_S 0 +#define IRDMA_QUERY_FPM_FIRST_PE_SD_INDEX GENMASK_ULL(13, 0) +#define IRDMA_QUERY_FPM_MAX_PE_SDS_S 32 +#define IRDMA_QUERY_FPM_MAX_PE_SDS GENMASK_ULL(44, 32) + +#define IRDMA_QUERY_FPM_MAX_CEQS_S 0 +#define IRDMA_QUERY_FPM_MAX_CEQS GENMASK_ULL(9, 0) +#define IRDMA_QUERY_FPM_XFBLOCKSIZE_S 32 +#define IRDMA_QUERY_FPM_XFBLOCKSIZE GENMASK_ULL(63, 32) +#define IRDMA_QUERY_FPM_Q1BLOCKSIZE_S 32 +#define IRDMA_QUERY_FPM_Q1BLOCKSIZE GENMASK_ULL(63, 32) +#define IRDMA_QUERY_FPM_HTMULTIPLIER_S 16 +#define IRDMA_QUERY_FPM_HTMULTIPLIER GENMASK_ULL(19, 16) +#define IRDMA_QUERY_FPM_TIMERBUCKET_S 32 +#define IRDMA_QUERY_FPM_TIMERBUCKET GENMASK_ULL(47, 32) +#define IRDMA_QUERY_FPM_RRFBLOCKSIZE_S 32 +#define IRDMA_QUERY_FPM_RRFBLOCKSIZE GENMASK_ULL(63, 32) +#define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE_S 32 +#define IRDMA_QUERY_FPM_RRFFLBLOCKSIZE GENMASK_ULL(63, 32) +#define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE_S 32 +#define IRDMA_QUERY_FPM_OOISCFBLOCKSIZE GENMASK_ULL(63, 32) +#define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID_S 0 +#define IRDMA_SHMC_PAGE_ALLOCATED_HMC_FN_ID GENMASK_ULL(15, 0) + +#define IRDMA_GET_CURRENT_AEQ_ELEM(_aeq) \ + ( \ + (_aeq)->aeqe_base[IRDMA_RING_CURRENT_TAIL((_aeq)->aeq_ring)].buf \ + ) + +#define IRDMA_GET_CURRENT_CEQ_ELEM(_ceq) \ + ( \ + (_ceq)->ceqe_base[IRDMA_RING_CURRENT_TAIL((_ceq)->ceq_ring)].buf \ + ) + +#define IRDMA_GET_CEQ_ELEM_AT_POS(_ceq, _pos) \ + ( \ + (_ceq)->ceqe_base[_pos].buf \ + ) + +#define IRDMA_RING_GET_NEXT_TAIL(_ring, _idx) \ + ( \ + ((_ring).tail + (_idx)) % (_ring).size \ + ) + +#define IRDMA_GET_RING_OFFSET(_ring, _i) \ + ( \ + ((_ring).head + (_i)) % (_ring).size \ + ) + +#define IRDMA_GET_CQ_ELEM_AT_OFFSET(_cq, _i, _cqe) \ + { \ + __u32 offset; \ + offset = IRDMA_GET_RING_OFFSET((_cq)->cq_ring, _i); \ + (_cqe) = (_cq)->cq_base[offset].buf; \ + } +#define IRDMA_GET_CURRENT_CQ_ELEM(_cq) \ + ( \ + (_cq)->cq_base[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \ + ) +#define IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(_cq) \ + ( \ + ((struct irdma_extended_cqe *) \ + ((_cq)->cq_base))[IRDMA_RING_CURRENT_HEAD((_cq)->cq_ring)].buf \ + ) + +#define IRDMA_RING_INIT(_ring, _size) \ + { \ + (_ring).head = 0; \ + (_ring).tail = 0; \ + (_ring).true_tail = 0; \ + (_ring).size = (_size); \ + } +#define IRDMA_RING_SIZE(_ring) ((_ring).size) +#define IRDMA_RING_CURRENT_HEAD(_ring) ((_ring).head) +#define IRDMA_RING_CURRENT_TAIL(_ring) ((_ring).tail) +#define IRDMA_RING_CURRENT_TRUE_TAIL(_ring) ((_ring).true_tail) + +#define IRDMA_RING_MOVE_HEAD(_ring, _retcode) \ + { \ + u32 size; \ + size = (_ring).size; \ + if (!IRDMA_RING_FULL_ERR(_ring)) { \ + (_ring).head = ((_ring).head + 1) % size; \ + (_retcode) = 0; \ + } else { \ + (_retcode) = -ENOMEM; \ + } \ + } +#define IRDMA_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ + { \ + u32 size; \ + size = (_ring).size; \ + if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < size) { \ + (_ring).head = ((_ring).head + (_count)) % size; \ + (_retcode) = 0; \ + } else { \ + (_retcode) = -ENOMEM; \ + } \ + } +#define IRDMA_SQ_RING_MOVE_HEAD(_ring, _retcode) \ + { \ + u32 size; \ + size = (_ring).size; \ + if (!IRDMA_SQ_RING_FULL_ERR(_ring)) { \ + (_ring).head = ((_ring).head + 1) % size; \ + (_retcode) = 0; \ + } else { \ + (_retcode) = -ENOMEM; \ + } \ + } +#define IRDMA_SQ_RING_MOVE_HEAD_BY_COUNT(_ring, _count, _retcode) \ + { \ + u32 size; \ + size = (_ring).size; \ + if ((IRDMA_RING_USED_QUANTA(_ring) + (_count)) < (size - 256)) { \ + (_ring).head = ((_ring).head + (_count)) % size; \ + (_retcode) = 0; \ + } else { \ + (_retcode) = -ENOMEM; \ + } \ + } +#define IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(_ring, _count) \ + (_ring).head = ((_ring).head + (_count)) % (_ring).size + +#define IRDMA_RING_MOVE_TAIL(_ring) \ + (_ring).tail = ((_ring).tail + 1) % (_ring).size + +#define IRDMA_RING_MOVE_HEAD_NOCHECK(_ring) \ + (_ring).head = ((_ring).head + 1) % (_ring).size + +#define IRDMA_RING_MOVE_TAIL_BY_COUNT(_ring, _count) \ + (_ring).tail = ((_ring).tail + (_count)) % (_ring).size + +#define IRDMA_RING_SET_TAIL(_ring, _pos) \ + (_ring).tail = (_pos) % (_ring).size + +#define IRDMA_RING_MOVE_TRUE_TAIL(_ring) \ + (_ring).true_tail = ((_ring).true_tail + 1) % (_ring).size + +#define IRDMA_RING_SET_TRUE_TAIL(_ring, _pos) \ + (_ring).true_tail = (_pos) % (_ring).size + +#define IRDMA_RING_FULL_ERR(_ring) \ + ( \ + (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 1)) \ + ) + +#define IRDMA_ERR_RING_FULL2(_ring) \ + ( \ + (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 2)) \ + ) + +#define IRDMA_ERR_RING_FULL3(_ring) \ + ( \ + (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 3)) \ + ) + +#define IRDMA_SQ_RING_FULL_ERR(_ring) \ + ( \ + (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 257)) \ + ) + +#define IRDMA_ERR_SQ_RING_FULL2(_ring) \ + ( \ + (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 258)) \ + ) +#define IRDMA_ERR_SQ_RING_FULL3(_ring) \ + ( \ + (IRDMA_RING_USED_QUANTA(_ring) == ((_ring).size - 259)) \ + ) +#define IRDMA_RING_MORE_WORK(_ring) \ + ( \ + (IRDMA_RING_USED_QUANTA(_ring) != 0) \ + ) + +#define IRDMA_RING_USED_QUANTA(_ring) \ + ( \ + (((_ring).head + (_ring).size - (_ring).tail) % (_ring).size) \ + ) + +#define IRDMA_RING_FREE_QUANTA(_ring) \ + ( \ + ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 1) \ + ) + +#define IRDMA_SQ_RING_FREE_QUANTA(_ring) \ + ( \ + ((_ring).size - IRDMA_RING_USED_QUANTA(_ring) - 257) \ + ) + +#define IRDMA_ATOMIC_RING_MOVE_HEAD(_ring, index, _retcode) \ + { \ + index = IRDMA_RING_CURRENT_HEAD(_ring); \ + IRDMA_RING_MOVE_HEAD(_ring, _retcode); \ + } + +enum irdma_protocol_used { + IRDMA_ANY_PROTOCOL = 0, + IRDMA_IWARP_PROTOCOL_ONLY = 1, + IRDMA_ROCE_PROTOCOL_ONLY = 2, +}; + +enum irdma_qp_wqe_size { + IRDMA_WQE_SIZE_32 = 32, + IRDMA_WQE_SIZE_64 = 64, + IRDMA_WQE_SIZE_96 = 96, + IRDMA_WQE_SIZE_128 = 128, + IRDMA_WQE_SIZE_256 = 256, +}; + +enum irdma_ws_op_type { + IRDMA_WS_OP_TYPE_NODE = 0, + IRDMA_WS_OP_TYPE_LEAF_NODE_GROUP, +}; + +enum irdma_ws_rate_limit_flags { + IRDMA_WS_RATE_LIMIT_FLAGS_VALID = 0x1, + IRDMA_WS_NO_RDMA_RATE_LIMIT = 0x2, + IRDMA_WS_LEAF_NODE_IS_PART_GROUP = 0x4, + IRDMA_WS_TREE_RATE_LIMITING = 0x8, + IRDMA_WS_PACING_CONTROL = 0x10, +}; + +enum irdma_ws_node_op { + IRDMA_ADD_NODE = 0, + IRDMA_MODIFY_NODE, + IRDMA_DEL_NODE, + IRDMA_FAILOVER_START, + IRDMA_FAILOVER_COMPLETE, +}; + +enum { IRDMA_Q_ALIGNMENT_M = (128 - 1), + IRDMA_AEQ_ALIGNMENT_M = (256 - 1), + IRDMA_Q2_ALIGNMENT_M = (256 - 1), + IRDMA_CEQ_ALIGNMENT_M = (256 - 1), + IRDMA_CQ0_ALIGNMENT_M = (256 - 1), + IRDMA_HOST_CTX_ALIGNMENT_M = (4 - 1), + IRDMA_SHADOWAREA_M = (128 - 1), + IRDMA_FPM_QUERY_BUF_ALIGNMENT_M = (4 - 1), + IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M = (4 - 1), +}; + +enum irdma_alignment { + IRDMA_CQP_ALIGNMENT = 0x200, + IRDMA_AEQ_ALIGNMENT = 0x100, + IRDMA_CEQ_ALIGNMENT = 0x100, + IRDMA_CQ0_ALIGNMENT = 0x100, + IRDMA_SD_BUF_ALIGNMENT = 0x80, + IRDMA_FEATURE_BUF_ALIGNMENT = 0x10, +}; + +/** + * set_64bit_val - set 64 bit value to hw wqe + * @wqe_words: wqe addr to write + * @byte_index: index in wqe + * @val: value to write + **/ +static inline void set_64bit_val(__le64 *wqe_words, u32 byte_index, u64 val) +{ + wqe_words[byte_index >> 3] = cpu_to_le64(val); +} + +/** + * set_32bit_val - set 32 bit value to hw wqe + * @wqe_words: wqe addr to write + * @byte_index: index in wqe + * @val: value to write + **/ +static inline void set_32bit_val(__le32 *wqe_words, u32 byte_index, u32 val) +{ + wqe_words[byte_index >> 2] = cpu_to_le32(val); +} + +/** + * get_64bit_val - read 64 bit value from wqe + * @wqe_words: wqe addr + * @byte_index: index to read from + * @val: read value + **/ +static inline void get_64bit_val(__le64 *wqe_words, u32 byte_index, u64 *val) +{ + *val = le64_to_cpu(wqe_words[byte_index >> 3]); +} + +/** + * get_32bit_val - read 32 bit value from wqe + * @wqe_words: wqe addr + * @byte_index: index to reaad from + * @val: return 32 bit value + **/ +static inline void get_32bit_val(__le32 *wqe_words, u32 byte_index, u32 *val) +{ + *val = le32_to_cpu(wqe_words[byte_index >> 2]); +} + +#endif /* IRDMA_DEFS_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/distro_ver.h b/drivers/intel/irdma-1.14.33/src/irdma/distro_ver.h new file mode 100644 index 000000000..d0b28ad74 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/distro_ver.h @@ -0,0 +1,194 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2024 Intel Corporation */ +#ifndef DISTRO_VER_H +#define DISTRO_VER_H + +#ifndef LINUX_VERSION_CODE +#include +#else +#define KERNEL_VERSION(a, b, c) (((a) << 16) + ((b) << 8) + (c)) +#endif + +#if defined(RHEL_RELEASE_CODE) + +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(9, 2)) && (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(10, 0)) +#define RHEL_9_2 /* Assume any 9.X greater than 9.2 will also work with current 9.2 defines */ +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(9, 1)) +#define RHEL_9_1 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(9, 0)) +#define RHEL_9_0 +#endif + +#if (RHEL_RELEASE_CODE >= RHEL_RELEASE_VERSION(8, 8)) && (RHEL_RELEASE_CODE < RHEL_RELEASE_VERSION(9, 0)) +#define RHEL_8_8 /* Assume any 8.X greater than 8.8 will also work with current 8.8 defines */ +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(8, 7)) +#define RHEL_8_7 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(8, 6)) +#define RHEL_8_6 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(8, 5)) +#define RHEL_8_5 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(8, 4)) +#define RHEL_8_4 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(8, 3)) +#define RHEL_8_3 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(7, 9)) +#define RHEL_7_9 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(8, 2)) +#define RHEL_8_2 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(8, 1)) +#define RHEL_8_1 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(7, 8)) +#define RHEL_7_8 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(7, 7)) +#define RHEL_7_7 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(8, 0)) +#define RHEL_8_0 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(7, 6)) +#define RHEL_7_6 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(7, 5)) +#define RHEL_7_5 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(7, 4)) +#define RHEL_7_4 +#endif + +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(7, 2)) +#define RHEL_7_2 +#endif + +#endif /* RHEL_RELEASE_CODE */ + +#ifdef CONFIG_SUSE_KERNEL +#ifndef SLE_VERSION +#define SLE_VERSION(a, b, c) KERNEL_VERSION(a, b, c) +#endif +#define SLE_LOCALVERSION(a, b, c) KERNEL_VERSION(a, b, c) + +#if (LINUX_VERSION_CODE == KERNEL_VERSION(4, 12, 14) && \ + (SLE_LOCALVERSION_CODE == SLE_LOCALVERSION(94, 41, 0) || \ + (SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(95, 0, 0) && \ + SLE_LOCALVERSION_CODE < SLE_LOCALVERSION(96, 0, 0)))) +/* SLES12 SP4 GM is 4.12.14-94.41 and update kernel is 4.12.14-95.x. */ +#define SLE_VERSION_CODE SLE_VERSION(12, 4, 0) +#define SLES_12_SP_4 +#elif (LINUX_VERSION_CODE == KERNEL_VERSION(4, 12, 14) && \ + SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(25, 23, 0)) +/* SLES15 SP1 Beta1 is 4.12.14-25.23 */ +#define SLE_VERSION_CODE SLE_VERSION(15, 1, 0) +#define SLES_15_SP_1 +#endif + +#if (LINUX_VERSION_CODE == KERNEL_VERSION(4, 12, 14) && \ + (SLE_LOCALVERSION_CODE == SLE_LOCALVERSION(23, 0, 0) || \ + SLE_LOCALVERSION_CODE == SLE_LOCALVERSION(2, 0, 0) || \ + SLE_LOCALVERSION_CODE == SLE_LOCALVERSION(136, 0, 0) || \ + (SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(25, 0, 0) && \ + SLE_LOCALVERSION_CODE < SLE_LOCALVERSION(25, 23, 0)))) +#define SLE_VERSION_CODE SLE_VERSION(15, 0, 0) +#define SLES_15 +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 21) +#if SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(150600ULL, 0, 0) +#define SLES_15_SP_6 +#elif SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(150500ULL, 0, 0) +#define SLES_15_SP_5 +#else +#define SLES_15_SP_4 +#endif +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 18) +#if SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(46, 0, 0) +#define SLES_15_SP_3 +#else +#define SLE_VERSION_CODE SLE_VERSION(15, 2, 0) +#define SLES_15_SP_2 +#endif +#endif + +#if ((LINUX_VERSION_CODE == KERNEL_VERSION(4, 4, 73) || \ + LINUX_VERSION_CODE == KERNEL_VERSION(4, 4, 82) || \ + LINUX_VERSION_CODE == KERNEL_VERSION(4, 4, 92)) || \ + (LINUX_VERSION_CODE == KERNEL_VERSION(4, 4, 103) && \ + (SLE_LOCALVERSION_CODE == SLE_LOCALVERSION(6, 33, 0) || \ + SLE_LOCALVERSION_CODE == SLE_LOCALVERSION(6, 38, 0))) || \ + (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 4, 114) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(4, 5, 0) && \ + SLE_LOCALVERSION_CODE >= SLE_LOCALVERSION(94, 0, 0) && \ + SLE_LOCALVERSION_CODE < SLE_LOCALVERSION(95, 0, 0))) +/* SLES12 SP3 GM is 4.4.73-5 and update kernels are 4.4.82-6.3. + * SLES12 SP3 updates not conflicting with SP2 are: 4.4.{82,92} + * SLES12 SP3 updates conflicting with SP2 are: + * - 4.4.103-6.33.1, 4.4.103-6.38.1 + * - 4.4.{114,120}-94.nn.y + */ +#define SLE_VERSION_CODE SLE_VERSION(12, 3, 0) +#define SLES_12_SP_3 +#endif /* LINUX_VERSION_CODE == KERNEL_VERSION(x,y,z) */ + +#endif /* CONFIG_SUSE_KERENL */ + +#ifdef UTS_UBUNTU_RELEASE_ABI +#define UBUNTU_VERSION_CODE (((~0xFF & LINUX_VERSION_CODE) << 8) + \ + UTS_UBUNTU_RELEASE_ABI) + +#define UBUNTU_VERSION(a, b, c, d) ((KERNEL_VERSION(a, b, 0) << 8) + (d)) + +#if (UBUNTU_VERSION_CODE >= UBUNTU_VERSION(6, 8, 0, 22)) +#define UBUNTU_2404 +#elif (UBUNTU_VERSION_CODE >= UBUNTU_VERSION(5, 15, 0, 25)) +#define UBUNTU_2204 +#elif (UBUNTU_VERSION_CODE >= UBUNTU_VERSION(5, 11, 0, 27)) +#define UBUNTU_200403 +#elif (UBUNTU_VERSION_CODE >= UBUNTU_VERSION(5, 8, 0, 48)) +#define UBUNTU_200402 +#elif (UBUNTU_VERSION_CODE >= UBUNTU_VERSION(5, 4, 0, 139)) +#define UBUNTU_200405 +#elif (UBUNTU_VERSION_CODE >= UBUNTU_VERSION(5, 4, 0, 100)) +#define UBUNTU_200404 +#elif (UBUNTU_VERSION_CODE >= UBUNTU_VERSION(5, 4, 0, 26)) +#define UBUNTU_2004 +#else +#define UBUNTU_1804 +#endif +#endif /* UTS_UBUNTU_RELEASE_ABI */ + +#if !defined(UTS_UBUNTU_RELEASE_ABI) && !defined(RHEL_RELEASE_CODE) && !defined(CONFIG_SUSE_KERNEL) +#ifdef UTS_RELEASE +#if LINUX_VERSION_CODE == KERNEL_VERSION(5, 4, 17) +#define ORACLE_REL +#endif +#endif /* UTS_RELEASE */ +#endif /* !defined(UTS_UBUNTU_RELEASE_ABI) && !defined(RHEL_RELEASE_CODE) && !defined(CONFIG_SUSE_KERNEL) */ + +#endif /* DISTRO_VER_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/hmc.c b/drivers/intel/irdma-1.14.33/src/irdma/hmc.c new file mode 100644 index 000000000..597877936 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/hmc.c @@ -0,0 +1,822 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2024 Intel Corporation */ +#include "osdep.h" +#include "hmc.h" +#include "defs.h" +#include "type.h" +#include "protos.h" +#include "virtchnl.h" + +/** + * irdma_find_sd_index_limit - finds segment descriptor index limit + * @hmc_info: pointer to the HMC configuration information structure + * @type: type of HMC resources we're searching + * @idx: starting index for the object + * @cnt: number of objects we're trying to create + * @sd_idx: pointer to return index of the segment descriptor in question + * @sd_limit: pointer to return the maximum number of segment descriptors + * + * This function calculates the segment descriptor index and index limit + * for the resource defined by irdma_hmc_rsrc_type. + */ + +static void irdma_find_sd_index_limit(struct irdma_hmc_info *hmc_info, u32 type, + u32 idx, u32 cnt, u32 *sd_idx, + u32 *sd_limit) +{ + u64 fpm_addr, fpm_limit; + + fpm_addr = hmc_info->hmc_obj[(type)].base + + hmc_info->hmc_obj[type].size * idx; + fpm_limit = fpm_addr + hmc_info->hmc_obj[type].size * cnt; + *sd_idx = (u32)(fpm_addr / IRDMA_HMC_DIRECT_BP_SIZE); + *sd_limit = (u32)((fpm_limit - 1) / IRDMA_HMC_DIRECT_BP_SIZE); + *sd_limit += 1; +} + +/** + * irdma_find_pd_index_limit - finds page descriptor index limit + * @hmc_info: pointer to the HMC configuration information struct + * @type: HMC resource type we're examining + * @idx: starting index for the object + * @cnt: number of objects we're trying to create + * @pd_idx: pointer to return page descriptor index + * @pd_limit: pointer to return page descriptor index limit + * + * Calculates the page descriptor index and index limit for the resource + * defined by irdma_hmc_rsrc_type. + */ + +static void irdma_find_pd_index_limit(struct irdma_hmc_info *hmc_info, u32 type, + u32 idx, u32 cnt, u32 *pd_idx, + u32 *pd_limit) +{ + u64 fpm_adr, fpm_limit; + + fpm_adr = hmc_info->hmc_obj[type].base + + hmc_info->hmc_obj[type].size * idx; + fpm_limit = fpm_adr + (hmc_info)->hmc_obj[(type)].size * (cnt); + *pd_idx = (u32)(fpm_adr / IRDMA_HMC_PAGED_BP_SIZE); + *pd_limit = (u32)((fpm_limit - 1) / IRDMA_HMC_PAGED_BP_SIZE); + *pd_limit += 1; +} + +/** + * irdma_set_sd_entry - setup entry for sd programming + * @pa: physical addr + * @idx: sd index + * @type: paged or direct sd + * @entry: sd entry ptr + */ +static void irdma_set_sd_entry(u64 pa, u32 idx, enum irdma_sd_entry_type type, + struct irdma_update_sd_entry *entry) +{ + entry->data = pa | + FIELD_PREP(IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT, IRDMA_HMC_MAX_BP_COUNT) | + FIELD_PREP(IRDMA_PFHMC_SDDATALOW_PMSDTYPE, + type == IRDMA_SD_TYPE_PAGED ? 0 : 1) | + FIELD_PREP(IRDMA_PFHMC_SDDATALOW_PMSDVALID, 1); + + entry->cmd = idx | FIELD_PREP(IRDMA_PFHMC_SDCMD_PMSDWR, 1) | + IRDMA_PFHMC_SDCMD_PMSDPARTSEL; +} + +/** + * irdma_clr_sd_entry - setup entry for sd clear + * @idx: sd index + * @type: paged or direct sd + * @entry: sd entry ptr + */ +static void irdma_clr_sd_entry(u32 idx, enum irdma_sd_entry_type type, + struct irdma_update_sd_entry *entry) +{ + entry->data = FIELD_PREP(IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT, IRDMA_HMC_MAX_BP_COUNT) | + FIELD_PREP(IRDMA_PFHMC_SDDATALOW_PMSDTYPE, + type == IRDMA_SD_TYPE_PAGED ? 0 : 1); + + entry->cmd = idx | FIELD_PREP(IRDMA_PFHMC_SDCMD_PMSDWR, 1) | + IRDMA_PFHMC_SDCMD_PMSDPARTSEL; +} + +/** + * irdma_invalidate_pf_hmc_pd - Invalidates the pd cache in the hardware for PF + * @dev: pointer to our device struct + * @sd_idx: segment descriptor index + * @pd_idx: page descriptor index + */ +static inline void irdma_invalidate_pf_hmc_pd(struct irdma_sc_dev *dev, u32 sd_idx, + u32 pd_idx) +{ + u32 val = FIELD_PREP(IRDMA_PFHMC_PDINV_PMSDIDX, sd_idx) | + FIELD_PREP(IRDMA_PFHMC_PDINV_PMSDPARTSEL, 1) | + FIELD_PREP(IRDMA_PFHMC_PDINV_PMPDIDX, pd_idx); + + writel(val, dev->hw_regs[IRDMA_PFHMC_PDINV]); +} + +/** + * irdma_invalidate_vf_hmc_pd - Invalidates the pd cache in the hardware for VF + * @dev: pointer to our device struct + * @sd_idx: segment descriptor index + * @pd_idx: page descriptor index + * @hmc_fn_id: VF's function id + */ +static inline void irdma_invalidate_vf_hmc_pd(struct irdma_sc_dev *dev, + u32 sd_idx, u32 pd_idx, + u16 hmc_fn_id) +{ + u32 val = FIELD_PREP(IRDMA_PFHMC_PDINV_PMSDIDX, sd_idx) | + FIELD_PREP(IRDMA_PFHMC_PDINV_PMPDIDX, pd_idx); + + writel(val, + dev->hw_regs[IRDMA_GLHMC_VFPDINV] + hmc_fn_id - dev->hw_attrs.first_hw_vf_fpm_id); +} + +/** + * irdma_hmc_sd_one - setup 1 sd entry for cqp + * @dev: pointer to the device structure + * @hmc_fn_id: hmc's function id + * @pa: physical addr + * @sd_idx: sd index + * @type: paged or direct sd + * @setsd: flag to set or clear sd + */ +int irdma_hmc_sd_one(struct irdma_sc_dev *dev, u16 hmc_fn_id, u64 pa, u32 sd_idx, + enum irdma_sd_entry_type type, bool setsd) +{ + struct irdma_update_sds_info sdinfo; + + sdinfo.cnt = 1; + sdinfo.hmc_fn_id = hmc_fn_id; + if (setsd) + irdma_set_sd_entry(pa, sd_idx, type, sdinfo.entry); + else + irdma_clr_sd_entry(sd_idx, type, sdinfo.entry); + return dev->cqp->process_cqp_sds(dev, &sdinfo); +} + +/** + * irdma_hmc_sd_grp - setup group of sd entries for cqp + * @dev: pointer to the device structure + * @hmc_info: pointer to the HMC configuration information struct + * @sd_index: sd index + * @sd_cnt: number of sd entries + * @setsd: flag to set or clear sd + */ +static int irdma_hmc_sd_grp(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, u32 sd_index, + u32 sd_cnt, bool setsd) +{ + struct irdma_hmc_sd_entry *sd_entry; + struct irdma_update_sds_info sdinfo = {}; + u64 pa; + u32 i; + int ret_code = 0; + + sdinfo.hmc_fn_id = hmc_info->hmc_fn_id; + for (i = sd_index; i < sd_index + sd_cnt; i++) { + sd_entry = &hmc_info->sd_table.sd_entry[i]; + if (!sd_entry || (!sd_entry->valid && setsd) || + (sd_entry->valid && !setsd)) + continue; + if (setsd) { + pa = (sd_entry->entry_type == IRDMA_SD_TYPE_PAGED) ? + sd_entry->u.pd_table.pd_page_addr.pa : + sd_entry->u.bp.addr.pa; + irdma_set_sd_entry(pa, i, sd_entry->entry_type, + &sdinfo.entry[sdinfo.cnt]); + } else { + irdma_clr_sd_entry(i, sd_entry->entry_type, + &sdinfo.entry[sdinfo.cnt]); + } + sdinfo.cnt++; + if (sdinfo.cnt == IRDMA_MAX_SD_ENTRIES) { + ret_code = dev->cqp->process_cqp_sds(dev, &sdinfo); + if (ret_code) { + ibdev_dbg(to_ibdev(dev), + "HMC: sd_programming failed err=%d\n", + ret_code); + return ret_code; + } + + sdinfo.cnt = 0; + } + } + if (sdinfo.cnt) + ret_code = dev->cqp->process_cqp_sds(dev, &sdinfo); + + return ret_code; +} + +/** + * irdma_vchnl_dev_from_fpm - return vc dev ptr for hmc function id + * @dev: pointer to the device structure + * @hmc_fn_id: hmc's function id + */ +struct irdma_vchnl_dev *irdma_vchnl_dev_from_fpm(struct irdma_sc_dev *dev, + u16 hmc_fn_id) +{ + struct irdma_vchnl_dev *vc_dev = NULL; + u16 idx; + + for (idx = 0; idx < dev->num_vfs; idx++) { + if (dev->vc_dev[idx] && + dev->vc_dev[idx]->pmf_index == hmc_fn_id) { + vc_dev = dev->vc_dev[idx]; + break; + } + } + return vc_dev; +} + +/** + * irdma_vf_hmcinfo_from_fpm - get ptr to hmc for func_id + * @dev: pointer to the device structure + * @hmc_fn_id: hmc's function id + */ +struct irdma_hmc_info *irdma_vf_hmcinfo_from_fpm(struct irdma_sc_dev *dev, + u16 hmc_fn_id) +{ + struct irdma_hmc_info *hmc_info = NULL; + u16 idx; + + for (idx = 0; idx < dev->num_vfs; idx++) { + if (dev->vc_dev[idx] && + dev->vc_dev[idx]->pmf_index == hmc_fn_id) { + hmc_info = &dev->vc_dev[idx]->hmc_info; + break; + } + } + return hmc_info; +} + +/** + * irdma_hmc_finish_add_sd_reg - program sd entries for objects + * @dev: pointer to the device structure + * @info: create obj info + */ +static int irdma_hmc_finish_add_sd_reg(struct irdma_sc_dev *dev, + struct irdma_hmc_create_obj_info *info) +{ + if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) + return -EINVAL; + + if ((info->start_idx + info->count) > + info->hmc_info->hmc_obj[info->rsrc_type].cnt) + return -EINVAL; + + if (!info->add_sd_cnt) + return 0; + return irdma_hmc_sd_grp(dev, info->hmc_info, + info->hmc_info->sd_indexes[0], info->add_sd_cnt, + true); +} + +/** + * irdma_sc_create_hmc_obj - allocate backing store for hmc objects + * @dev: pointer to the device structure + * @info: pointer to irdma_hmc_create_obj_info struct + * + * This will allocate memory for PDs and backing pages and populate + * the sd and pd entries. + */ +int irdma_sc_create_hmc_obj(struct irdma_sc_dev *dev, + struct irdma_hmc_create_obj_info *info) +{ + struct irdma_hmc_sd_entry *sd_entry; + u32 sd_idx, sd_lmt; + u32 pd_idx = 0, pd_lmt = 0; + u32 pd_idx1 = 0, pd_lmt1 = 0; + u32 i, j; + bool pd_error = false; + int ret_code = 0; + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3 && + dev->hmc_info->hmc_obj[info->rsrc_type].mem_loc == IRDMA_LOC_MEM) + return 0; + + if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) { + ibdev_dbg(to_ibdev(dev), + "ERR: invalid hmc obj type %u, start = %u, req cnt %u, cnt = %u\n", + info->rsrc_type, info->start_idx, info->count, + info->hmc_info->hmc_obj[info->rsrc_type].cnt); + + return -EINVAL; + } + + if ((info->start_idx + info->count) > + info->hmc_info->hmc_obj[info->rsrc_type].cnt) { + ibdev_dbg(to_ibdev(dev), + "ERR: error type %u, start = %u, req cnt %u, cnt = %u\n", + info->rsrc_type, info->start_idx, info->count, + info->hmc_info->hmc_obj[info->rsrc_type].cnt); + return -EINVAL; + } + + if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2 && + !dev->privileged) + return irdma_vchnl_req_add_hmc_objs(dev, info->rsrc_type, + info->start_idx, + info->count); + + irdma_find_sd_index_limit(info->hmc_info, info->rsrc_type, + info->start_idx, info->count, &sd_idx, + &sd_lmt); + if (sd_idx >= info->hmc_info->sd_table.sd_cnt || + sd_lmt > info->hmc_info->sd_table.sd_cnt) { + return -EINVAL; + } + + irdma_find_pd_index_limit(info->hmc_info, info->rsrc_type, + info->start_idx, info->count, &pd_idx, + &pd_lmt); + + for (j = sd_idx; j < sd_lmt; j++) { + ret_code = irdma_add_sd_table_entry(dev->hw, info->hmc_info, j, + info->entry_type, + IRDMA_HMC_DIRECT_BP_SIZE); + if (ret_code) + goto exit_sd_error; + + sd_entry = &info->hmc_info->sd_table.sd_entry[j]; + if (sd_entry->entry_type == IRDMA_SD_TYPE_PAGED && + (dev->hmc_info == info->hmc_info && + info->rsrc_type != IRDMA_HMC_IW_PBLE)) { + pd_idx1 = max(pd_idx, (j * IRDMA_HMC_MAX_BP_COUNT)); + pd_lmt1 = min(pd_lmt, (j + 1) * IRDMA_HMC_MAX_BP_COUNT); + for (i = pd_idx1; i < pd_lmt1; i++) { + /* update the pd table entry */ + ret_code = irdma_add_pd_table_entry(dev, + info->hmc_info, + i, NULL); + if (ret_code) { + pd_error = true; + break; + } + } + if (pd_error) { + while (i && (i > pd_idx1)) { + irdma_remove_pd_bp(dev, info->hmc_info, + i - 1); + i--; + } + } + } + if (sd_entry->valid) + continue; + + info->hmc_info->sd_indexes[info->add_sd_cnt] = (u16)j; + info->add_sd_cnt++; + sd_entry->valid = true; + } + return irdma_hmc_finish_add_sd_reg(dev, info); + +exit_sd_error: + while (j && (j > sd_idx)) { + sd_entry = &info->hmc_info->sd_table.sd_entry[j - 1]; + switch (sd_entry->entry_type) { + case IRDMA_SD_TYPE_PAGED: + pd_idx1 = max(pd_idx, (j - 1) * IRDMA_HMC_MAX_BP_COUNT); + pd_lmt1 = min(pd_lmt, (j * IRDMA_HMC_MAX_BP_COUNT)); + for (i = pd_idx1; i < pd_lmt1; i++) + irdma_prep_remove_pd_page(info->hmc_info, i); + break; + case IRDMA_SD_TYPE_DIRECT: + irdma_prep_remove_pd_page(info->hmc_info, (j - 1)); + break; + default: + ret_code = -EINVAL; + break; + } + j--; + } + + return ret_code; +} + +/** + * irdma_finish_del_sd_reg - delete sd entries for objects + * @dev: pointer to the device structure + * @info: dele obj info + * @reset: true if called before reset + */ +static int irdma_finish_del_sd_reg(struct irdma_sc_dev *dev, + struct irdma_hmc_del_obj_info *info, + bool reset) +{ + struct irdma_hmc_sd_entry *sd_entry; + int ret_code = 0; + struct irdma_dma_mem *mem; + u32 i, sd_idx; + + if (dev->privileged && !reset) + ret_code = irdma_hmc_sd_grp(dev, info->hmc_info, + info->hmc_info->sd_indexes[0], + info->del_sd_cnt, false); + + if (ret_code) + ibdev_dbg(to_ibdev(dev), "HMC: error cqp sd sd_grp\n"); + for (i = 0; i < info->del_sd_cnt; i++) { + sd_idx = info->hmc_info->sd_indexes[i]; + sd_entry = &info->hmc_info->sd_table.sd_entry[sd_idx]; + + mem = (sd_entry->entry_type == IRDMA_SD_TYPE_PAGED) ? + &sd_entry->u.pd_table.pd_page_addr : + &sd_entry->u.bp.addr; + + if (!mem || !mem->va) + ibdev_dbg(to_ibdev(dev), "HMC: error cqp sd mem\n"); + else { + dma_free_coherent(dev->hw->device, mem->size, mem->va, + mem->pa); + mem->va = NULL; + } + } + + return ret_code; +} + +/** + * irdma_sc_del_hmc_obj - remove pe hmc objects + * @dev: pointer to the device structure + * @info: pointer to irdma_hmc_del_obj_info struct + * @reset: true if called before reset + * + * This will de-populate the SDs and PDs. It frees + * the memory for PDS and backing storage. After this function is returned, + * caller should deallocate memory allocated previously for + * book-keeping information about PDs and backing storage. + */ +int irdma_sc_del_hmc_obj(struct irdma_sc_dev *dev, + struct irdma_hmc_del_obj_info *info, bool reset) +{ + struct irdma_hmc_pd_table *pd_table; + u32 sd_idx, sd_lmt; + u32 pd_idx, pd_lmt, rel_pd_idx; + u32 i, j; + int ret_code = 0; + + if (dev->hmc_info->hmc_obj[info->rsrc_type].mem_loc == IRDMA_LOC_MEM) + return 0; + + if (info->start_idx >= info->hmc_info->hmc_obj[info->rsrc_type].cnt) { + ibdev_dbg(to_ibdev(dev), + "HMC: error start_idx[%04d] >= [type %04d].cnt[%04d]\n", + info->start_idx, info->rsrc_type, + info->hmc_info->hmc_obj[info->rsrc_type].cnt); + return -EINVAL; + } + + if ((info->start_idx + info->count) > + info->hmc_info->hmc_obj[info->rsrc_type].cnt) { + ibdev_dbg(to_ibdev(dev), + "HMC: error start_idx[%04d] + count %04d >= [type %04d].cnt[%04d]\n", + info->start_idx, info->count, info->rsrc_type, + info->hmc_info->hmc_obj[info->rsrc_type].cnt); + return -EINVAL; + } + if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2 && + !dev->privileged) { + if (!reset) + ret_code = irdma_vchnl_req_del_hmc_obj(dev, + info->rsrc_type, + info->start_idx, + info->count); + if (info->rsrc_type != IRDMA_HMC_IW_PBLE) + return ret_code; + } + + irdma_find_pd_index_limit(info->hmc_info, info->rsrc_type, + info->start_idx, info->count, &pd_idx, + &pd_lmt); + + for (j = pd_idx; j < pd_lmt; j++) { + sd_idx = j / IRDMA_HMC_PD_CNT_IN_SD; + + if (!info->hmc_info->sd_table.sd_entry[sd_idx].valid) + continue; + + if (info->hmc_info->sd_table.sd_entry[sd_idx].entry_type != + IRDMA_SD_TYPE_PAGED) + continue; + + rel_pd_idx = j % IRDMA_HMC_PD_CNT_IN_SD; + pd_table = &info->hmc_info->sd_table.sd_entry[sd_idx].u.pd_table; + if (pd_table->pd_entry && + pd_table->pd_entry[rel_pd_idx].valid) { + ret_code = irdma_remove_pd_bp(dev, info->hmc_info, j); + if (ret_code) { + ibdev_dbg(to_ibdev(dev), + "HMC: remove_pd_bp error\n"); + return ret_code; + } + } + } + + irdma_find_sd_index_limit(info->hmc_info, info->rsrc_type, + info->start_idx, info->count, &sd_idx, + &sd_lmt); + if (sd_idx >= info->hmc_info->sd_table.sd_cnt || + sd_lmt > info->hmc_info->sd_table.sd_cnt) { + ibdev_dbg(to_ibdev(dev), "HMC: invalid sd_idx\n"); + return -EINVAL; + } + + for (i = sd_idx; i < sd_lmt; i++) { + pd_table = &info->hmc_info->sd_table.sd_entry[i].u.pd_table; + if (!info->hmc_info->sd_table.sd_entry[i].valid) + continue; + switch (info->hmc_info->sd_table.sd_entry[i].entry_type) { + case IRDMA_SD_TYPE_DIRECT: + ret_code = irdma_prep_remove_sd_bp(info->hmc_info, i); + if (!ret_code) { + info->hmc_info->sd_indexes[info->del_sd_cnt] = + (u16)i; + info->del_sd_cnt++; + } + break; + case IRDMA_SD_TYPE_PAGED: + ret_code = irdma_prep_remove_pd_page(info->hmc_info, i); + if (ret_code) + break; + if (dev->hmc_info != info->hmc_info && + info->rsrc_type == IRDMA_HMC_IW_PBLE && + pd_table->pd_entry) { + kfree(pd_table->pd_entry_virt_mem.va); + pd_table->pd_entry = NULL; + } + info->hmc_info->sd_indexes[info->del_sd_cnt] = (u16)i; + info->del_sd_cnt++; + break; + default: + break; + } + } + return irdma_finish_del_sd_reg(dev, info, reset); +} + +/** + * irdma_add_sd_table_entry - Adds a segment descriptor to the table + * @hw: pointer to our hw struct + * @hmc_info: pointer to the HMC configuration information struct + * @sd_index: segment descriptor index to manipulate + * @type: what type of segment descriptor we're manipulating + * @direct_mode_sz: size to alloc in direct mode + */ +int irdma_add_sd_table_entry(struct irdma_hw *hw, + struct irdma_hmc_info *hmc_info, u32 sd_index, + enum irdma_sd_entry_type type, u64 direct_mode_sz) +{ + struct irdma_hmc_sd_entry *sd_entry; + struct irdma_dma_mem dma_mem; + u64 alloc_len; + + sd_entry = &hmc_info->sd_table.sd_entry[sd_index]; + if (!sd_entry->valid) { + if (type == IRDMA_SD_TYPE_PAGED) + alloc_len = IRDMA_HMC_PAGED_BP_SIZE; + else + alloc_len = direct_mode_sz; + + /* allocate a 4K pd page or 2M backing page */ + dma_mem.size = ALIGN(alloc_len, IRDMA_HMC_PD_BP_BUF_ALIGNMENT); + dma_mem.va = dma_alloc_coherent(hw->device, dma_mem.size, + &dma_mem.pa, GFP_KERNEL); + if (!dma_mem.va) + return -ENOMEM; + if (type == IRDMA_SD_TYPE_PAGED) { + struct irdma_virt_mem *vmem = + &sd_entry->u.pd_table.pd_entry_virt_mem; + + vmem->size = sizeof(struct irdma_hmc_pd_entry) * 512; + vmem->va = kzalloc(vmem->size, GFP_KERNEL); + if (!vmem->va) { + dma_free_coherent(hw->device, dma_mem.size, + dma_mem.va, dma_mem.pa); + dma_mem.va = NULL; + return -ENOMEM; + } + sd_entry->u.pd_table.pd_entry = vmem->va; + + memcpy(&sd_entry->u.pd_table.pd_page_addr, &dma_mem, + sizeof(sd_entry->u.pd_table.pd_page_addr)); + } else { + memcpy(&sd_entry->u.bp.addr, &dma_mem, + sizeof(sd_entry->u.bp.addr)); + + sd_entry->u.bp.sd_pd_index = sd_index; + } + + hmc_info->sd_table.sd_entry[sd_index].entry_type = type; + hmc_info->sd_table.use_cnt++; + } + if (sd_entry->entry_type == IRDMA_SD_TYPE_DIRECT) + sd_entry->u.bp.use_cnt++; + + return 0; +} + +/** + * irdma_add_pd_table_entry - Adds page descriptor to the specified table + * @dev: pointer to our device structure + * @hmc_info: pointer to the HMC configuration information structure + * @pd_index: which page descriptor index to manipulate + * @rsrc_pg: if not NULL, use preallocated page instead of allocating new one. + * + * This function: + * 1. Initializes the pd entry + * 2. Adds pd_entry in the pd_table + * 3. Mark the entry valid in irdma_hmc_pd_entry structure + * 4. Initializes the pd_entry's ref count to 1 + * assumptions: + * 1. The memory for pd should be pinned down, physically contiguous and + * aligned on 4K boundary and zeroed memory. + * 2. It should be 4K in size. + */ +int irdma_add_pd_table_entry(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, u32 pd_index, + struct irdma_dma_mem *rsrc_pg) +{ + struct irdma_hmc_pd_table *pd_table; + struct irdma_hmc_pd_entry *pd_entry; + struct irdma_dma_mem mem; + struct irdma_dma_mem *page = &mem; + u32 sd_idx, rel_pd_idx; + u64 *pd_addr; + u64 page_desc; + + if (pd_index / IRDMA_HMC_PD_CNT_IN_SD >= hmc_info->sd_table.sd_cnt) + return -EINVAL; + + sd_idx = (pd_index / IRDMA_HMC_PD_CNT_IN_SD); + if (hmc_info->sd_table.sd_entry[sd_idx].entry_type != + IRDMA_SD_TYPE_PAGED) + return 0; + + rel_pd_idx = (pd_index % IRDMA_HMC_PD_CNT_IN_SD); + pd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table; + pd_entry = &pd_table->pd_entry[rel_pd_idx]; + if (!pd_entry->valid) { + if (rsrc_pg) { + pd_entry->rsrc_pg = true; + page = rsrc_pg; + } else { + page->size = ALIGN(IRDMA_HMC_PAGED_BP_SIZE, + IRDMA_HMC_PD_BP_BUF_ALIGNMENT); + page->va = dma_alloc_coherent(dev->hw->device, + page->size, &page->pa, + GFP_KERNEL); + if (!page->va) + return -ENOMEM; + + pd_entry->rsrc_pg = false; + } + + memcpy(&pd_entry->bp.addr, page, sizeof(pd_entry->bp.addr)); + pd_entry->bp.sd_pd_index = pd_index; + pd_entry->bp.entry_type = IRDMA_SD_TYPE_PAGED; + page_desc = page->pa | 0x1; + pd_addr = pd_table->pd_page_addr.va; + pd_addr += rel_pd_idx; + memcpy(pd_addr, &page_desc, sizeof(*pd_addr)); + pd_entry->sd_index = sd_idx; + pd_entry->valid = true; + pd_table->use_cnt++; + /* Invalidating hmc_pd is only relevant to IRDMA_GEN_1/2 */ + + if (hmc_info->hmc_fn_id < dev->hw_attrs.first_hw_vf_fpm_id && + dev->privileged) + irdma_invalidate_pf_hmc_pd(dev, sd_idx, rel_pd_idx); + else if (dev->hw->hmc.hmc_fn_id != hmc_info->hmc_fn_id && + dev->privileged) + irdma_invalidate_vf_hmc_pd(dev, sd_idx, rel_pd_idx, + hmc_info->hmc_fn_id); + } + pd_entry->bp.use_cnt++; + + return 0; +} + +/** + * irdma_remove_pd_bp - remove a backing page from a page descriptor + * @dev: pointer to our HW structure + * @hmc_info: pointer to the HMC configuration information structure + * @idx: the page index + * + * This function: + * 1. Marks the entry in pd table (for paged address mode) or in sd table + * (for direct address mode) invalid. + * 2. Write to register PMPDINV to invalidate the backing page in FV cache + * 3. Decrement the ref count for the pd _entry + * assumptions: + * 1. Caller can deallocate the memory used by backing storage after this + * function returns. + */ +int irdma_remove_pd_bp(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, u32 idx) +{ + struct irdma_hmc_pd_entry *pd_entry; + struct irdma_hmc_pd_table *pd_table; + struct irdma_hmc_sd_entry *sd_entry; + u32 sd_idx, rel_pd_idx; + struct irdma_dma_mem *mem; + u64 *pd_addr; + + sd_idx = idx / IRDMA_HMC_PD_CNT_IN_SD; + rel_pd_idx = idx % IRDMA_HMC_PD_CNT_IN_SD; + if (sd_idx >= hmc_info->sd_table.sd_cnt) + return -EINVAL; + + sd_entry = &hmc_info->sd_table.sd_entry[sd_idx]; + if (sd_entry->entry_type != IRDMA_SD_TYPE_PAGED) + return -EINVAL; + + pd_table = &hmc_info->sd_table.sd_entry[sd_idx].u.pd_table; + pd_entry = &pd_table->pd_entry[rel_pd_idx]; + if (--pd_entry->bp.use_cnt) + return 0; + + pd_entry->valid = false; + pd_table->use_cnt--; + pd_addr = pd_table->pd_page_addr.va; + pd_addr += rel_pd_idx; + memset(pd_addr, 0, sizeof(u64)); + if (dev->privileged && dev->hmc_fn_id == hmc_info->hmc_fn_id) + irdma_invalidate_pf_hmc_pd(dev, sd_idx, idx); + + if (dev->privileged && dev->hmc_fn_id != hmc_info->hmc_fn_id) + irdma_invalidate_vf_hmc_pd(dev, sd_idx, idx, + hmc_info->hmc_fn_id); + + if (!pd_entry->rsrc_pg) { + mem = &pd_entry->bp.addr; + if (!mem || !mem->va) + return -EINVAL; + + dma_free_coherent(dev->hw->device, mem->size, mem->va, + mem->pa); + mem->va = NULL; + } + if (!pd_table->use_cnt) + kfree(pd_table->pd_entry_virt_mem.va); + + return 0; +} + +/** + * irdma_prep_remove_sd_bp - Prepares to remove a backing page from a sd entry + * @hmc_info: pointer to the HMC configuration information structure + * @idx: the page index + */ +int irdma_prep_remove_sd_bp(struct irdma_hmc_info *hmc_info, u32 idx) +{ + struct irdma_hmc_sd_entry *sd_entry; + + sd_entry = &hmc_info->sd_table.sd_entry[idx]; + if (--sd_entry->u.bp.use_cnt) + return -EBUSY; + + hmc_info->sd_table.use_cnt--; + sd_entry->valid = false; + + return 0; +} + +/** + * irdma_prep_remove_pd_page - Prepares to remove a PD page from sd entry. + * @hmc_info: pointer to the HMC configuration information structure + * @idx: segment descriptor index to find the relevant page descriptor + */ +int irdma_prep_remove_pd_page(struct irdma_hmc_info *hmc_info, u32 idx) +{ + struct irdma_hmc_sd_entry *sd_entry; + + sd_entry = &hmc_info->sd_table.sd_entry[idx]; + + if (sd_entry->u.pd_table.use_cnt) + return -EBUSY; + + sd_entry->valid = false; + hmc_info->sd_table.use_cnt--; + + return 0; +} + +/** + * irdma_pf_init_vfhmc - + * @dev: pointer to irdma_dev struct + * @vf_hmc_fn_id: hmc function id for vf driver + * + * Called by pf driver to initialize hmc_info for vf driver instance. + */ +int irdma_pf_init_vfhmc(struct irdma_sc_dev *dev, u8 vf_hmc_fn_id) +{ + if (vf_hmc_fn_id < dev->hw_attrs.first_hw_vf_fpm_id || + (vf_hmc_fn_id >= dev->hw_attrs.first_hw_vf_fpm_id + dev->num_vfs)) { + ibdev_dbg(to_ibdev(dev), "HMC: invalid vf_hmc_fn_id 0x%x\n", + vf_hmc_fn_id); + return -EINVAL; + } + + return irdma_sc_init_iw_hmc(dev, vf_hmc_fn_id); +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/hmc.h b/drivers/intel/irdma-1.14.33/src/irdma/hmc.h new file mode 100644 index 000000000..50da466db --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/hmc.h @@ -0,0 +1,186 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef IRDMA_HMC_H +#define IRDMA_HMC_H + +#include "defs.h" + +#define IRDMA_HMC_MAX_BP_COUNT 512 +#define IRDMA_MAX_SD_ENTRIES 11 +#define IRDMA_HW_DBG_HMC_INVALID_BP_MARK 0xca +#define IRDMA_HMC_INFO_SIGNATURE 0x484d5347 +#define IRDMA_HMC_PD_CNT_IN_SD 512 +#define IRDMA_HMC_DIRECT_BP_SIZE 0x200000 +#define IRDMA_HMC_MAX_SD_COUNT 8192 +#define IRDMA_HMC_PAGED_BP_SIZE 4096 +#define IRDMA_HMC_PD_BP_BUF_ALIGNMENT 4096 +#define IRDMA_FIRST_VF_FPM_ID 8 +#define FPM_MULTIPLIER 1024 +#define IRDMA_OBJ_LOC_MEM_BIT 0x4 +#define IRDMA_XF_MULTIPLIER 16 +#define IRDMA_RRF_MULTIPLIER 8 +#define IRDMA_MIN_PBLE_PAGES 3 +#define IRDMA_HMC_PAGE_SIZE 2097152 +#define IRDMA_MIN_MR_PER_QP 4 +#define IRDMA_MIN_QP_CNT 64 +#define IRDMA_FSIAV_CNT_MAX 1048576 +#define IRDMA_MIN_IRD 8 + +enum irdma_hmc_rsrc_type { + IRDMA_HMC_IW_QP = 0, + IRDMA_HMC_IW_CQ = 1, + IRDMA_HMC_IW_SRQ = 2, + IRDMA_HMC_IW_HTE = 3, + IRDMA_HMC_IW_ARP = 4, + IRDMA_HMC_IW_APBVT_ENTRY = 5, + IRDMA_HMC_IW_MR = 6, + IRDMA_HMC_IW_XF = 7, + IRDMA_HMC_IW_XFFL = 8, + IRDMA_HMC_IW_Q1 = 9, + IRDMA_HMC_IW_Q1FL = 10, + IRDMA_HMC_IW_TIMER = 11, + IRDMA_HMC_IW_FSIMC = 12, + IRDMA_HMC_IW_FSIAV = 13, + IRDMA_HMC_IW_PBLE = 14, + IRDMA_HMC_IW_RRF = 15, + IRDMA_HMC_IW_RRFFL = 16, + IRDMA_HMC_IW_HDR = 17, + IRDMA_HMC_IW_MD = 18, + IRDMA_HMC_IW_OOISC = 19, + IRDMA_HMC_IW_OOISCFFL = 20, + IRDMA_HMC_IW_MAX, /* Must be last entry */ +}; + +enum irdma_sd_entry_type { + IRDMA_SD_TYPE_INVALID = 0, + IRDMA_SD_TYPE_PAGED = 1, + IRDMA_SD_TYPE_DIRECT = 2, +}; + +enum irdma_hmc_obj_mem { + IRDMA_HOST_MEM = 0, + IRDMA_LOC_MEM = 1, +}; + +struct irdma_hmc_obj_info { + u64 base; + u32 max_cnt; + u32 cnt; + u64 size; + enum irdma_hmc_obj_mem mem_loc; +}; + +struct irdma_hmc_bp { + enum irdma_sd_entry_type entry_type; + struct irdma_dma_mem addr; + u32 sd_pd_index; + u32 use_cnt; +}; + +struct irdma_hmc_pd_entry { + struct irdma_hmc_bp bp; + u32 sd_index; + bool rsrc_pg:1; + bool valid:1; +}; + +struct irdma_hmc_pd_table { + struct irdma_dma_mem pd_page_addr; + struct irdma_hmc_pd_entry *pd_entry; + struct irdma_virt_mem pd_entry_virt_mem; + u32 use_cnt; + u32 sd_index; +}; + +struct irdma_hmc_sd_entry { + enum irdma_sd_entry_type entry_type; + bool valid; + union { + struct irdma_hmc_pd_table pd_table; + struct irdma_hmc_bp bp; + } u; +}; + +struct irdma_hmc_sd_table { + struct irdma_virt_mem addr; + u32 sd_cnt; + u32 use_cnt; + struct irdma_hmc_sd_entry *sd_entry; +}; + +struct irdma_hmc_info { + u32 signature; + u16 hmc_fn_id; + u16 first_sd_index; + struct irdma_hmc_obj_info *hmc_obj; + struct irdma_virt_mem hmc_obj_virt_mem; + struct irdma_hmc_sd_table sd_table; + u16 sd_indexes[IRDMA_HMC_MAX_SD_COUNT]; +}; + +struct irdma_update_sd_entry { + u64 cmd; + u64 data; +}; + +struct irdma_update_sds_info { + u32 cnt; + u16 hmc_fn_id; + struct irdma_update_sd_entry entry[IRDMA_MAX_SD_ENTRIES]; +}; + +struct irdma_ccq_cqe_info; +struct irdma_hmc_fcn_info { + u32 vf_id; + u8 protocol_used; + u8 is_pf; + u8 free_fcn; +}; + +struct irdma_hmc_create_obj_info { + struct irdma_hmc_info *hmc_info; + struct irdma_virt_mem add_sd_virt_mem; + u32 rsrc_type; + u32 start_idx; + u32 count; + u32 add_sd_cnt; + enum irdma_sd_entry_type entry_type; + bool privileged; +}; + +struct irdma_hmc_del_obj_info { + struct irdma_hmc_info *hmc_info; + struct irdma_virt_mem del_sd_virt_mem; + u32 rsrc_type; + u32 start_idx; + u32 count; + u32 del_sd_cnt; + bool privileged; +}; + +int irdma_copy_dma_mem(struct irdma_hw *hw, void *dest_buf, + struct irdma_dma_mem *src_mem, u64 src_offset, u64 size); +int irdma_sc_create_hmc_obj(struct irdma_sc_dev *dev, + struct irdma_hmc_create_obj_info *info); +int irdma_sc_del_hmc_obj(struct irdma_sc_dev *dev, + struct irdma_hmc_del_obj_info *info, bool reset); +int irdma_hmc_sd_one(struct irdma_sc_dev *dev, u16 hmc_fn_id, u64 pa, u32 sd_idx, + enum irdma_sd_entry_type type, + bool setsd); +int irdma_update_sds_noccq(struct irdma_sc_dev *dev, + struct irdma_update_sds_info *info); +struct irdma_vchnl_dev *irdma_vchnl_dev_from_fpm(struct irdma_sc_dev *dev, + u16 hmc_fn_id); +struct irdma_hmc_info *irdma_vf_hmcinfo_from_fpm(struct irdma_sc_dev *dev, + u16 hmc_fn_id); +int irdma_add_sd_table_entry(struct irdma_hw *hw, + struct irdma_hmc_info *hmc_info, u32 sd_index, + enum irdma_sd_entry_type type, u64 direct_mode_sz); +int irdma_add_pd_table_entry(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, u32 pd_index, + struct irdma_dma_mem *rsrc_pg); +int irdma_remove_pd_bp(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, u32 idx); +int irdma_prep_remove_sd_bp(struct irdma_hmc_info *hmc_info, u32 idx); +int irdma_prep_remove_pd_page(struct irdma_hmc_info *hmc_info, u32 idx); +#endif /* IRDMA_HMC_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/hw.c b/drivers/intel/irdma-1.14.33/src/irdma/hw.c new file mode 100644 index 000000000..ef7230900 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/hw.c @@ -0,0 +1,2832 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2024 Intel Corporation */ +#include "main.h" + +static struct irdma_rsrc_limits rsrc_limits_table[] = { + [0] = { + .qplimit = SZ_128, + }, + [1] = { + .qplimit = SZ_1K, + }, + [2] = { + .qplimit = SZ_2K, + }, + [3] = { + .qplimit = SZ_4K, + }, + [4] = { + .qplimit = SZ_16K, + }, + [5] = { + .qplimit = SZ_64K, + }, + [6] = { + .qplimit = SZ_128K, + }, + [7] = { + .qplimit = SZ_256K, + }, +}; + +/* types of hmc objects */ +static enum irdma_hmc_rsrc_type iw_hmc_obj_types[] = { + IRDMA_HMC_IW_QP, + IRDMA_HMC_IW_CQ, + IRDMA_HMC_IW_SRQ, + IRDMA_HMC_IW_HTE, + IRDMA_HMC_IW_ARP, + IRDMA_HMC_IW_APBVT_ENTRY, + IRDMA_HMC_IW_MR, + IRDMA_HMC_IW_XF, + IRDMA_HMC_IW_XFFL, + IRDMA_HMC_IW_Q1, + IRDMA_HMC_IW_Q1FL, + IRDMA_HMC_IW_PBLE, + IRDMA_HMC_IW_TIMER, + IRDMA_HMC_IW_FSIMC, + IRDMA_HMC_IW_FSIAV, + IRDMA_HMC_IW_RRF, + IRDMA_HMC_IW_RRFFL, + IRDMA_HMC_IW_HDR, + IRDMA_HMC_IW_MD, + IRDMA_HMC_IW_OOISC, + IRDMA_HMC_IW_OOISCFFL, +}; + +/** + * irdma_iwarp_ce_handler - handle iwarp completions + * @iwcq: iwarp cq receiving event + */ +static void irdma_iwarp_ce_handler(struct irdma_sc_cq *iwcq) +{ + struct irdma_cq *cq = iwcq->back_cq; + + if (!cq->user_mode) + atomic_set(&cq->armed, 0); + if (cq->ibcq.comp_handler) + cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); +} + +/** + * irdma_puda_ce_handler - handle puda completion events + * @rf: RDMA PCI function + * @cq: puda completion q for event + */ +static void irdma_puda_ce_handler(struct irdma_pci_f *rf, + struct irdma_sc_cq *cq) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + u32 compl_error; + int status; + + do { + status = irdma_puda_poll_cmpl(dev, cq, &compl_error); + if (status == -ENOENT) + break; + if (status) { + ibdev_dbg(to_ibdev(dev), "ERR: puda status = %d\n", status); + break; + } + if (compl_error) { + ibdev_dbg(to_ibdev(dev), "ERR: puda compl_err = 0x%x\n", + compl_error); + break; + } + } while (1); + + irdma_sc_ccq_arm(cq); +} + +/** + * irdma_process_ceq - handle ceq for completions + * @rf: RDMA PCI function + * @ceq: ceq having cq for completion + */ +static void irdma_process_ceq(struct irdma_pci_f *rf, struct irdma_ceq *ceq) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_sc_ceq *sc_ceq; + struct irdma_sc_cq *cq; + unsigned long flags; + + sc_ceq = &ceq->sc_ceq; + do { + spin_lock_irqsave(&ceq->ce_lock, flags); + cq = irdma_sc_process_ceq(dev, sc_ceq); + if (!cq) { + spin_unlock_irqrestore(&ceq->ce_lock, flags); + break; + } + + if (cq->cq_type == IRDMA_CQ_TYPE_IWARP) + irdma_iwarp_ce_handler(cq); + + spin_unlock_irqrestore(&ceq->ce_lock, flags); + + if (cq->cq_type == IRDMA_CQ_TYPE_CQP) + queue_work(rf->cqp_cmpl_wq, &rf->cqp_cmpl_work); + else if (cq->cq_type == IRDMA_CQ_TYPE_ILQ || + cq->cq_type == IRDMA_CQ_TYPE_IEQ) + irdma_puda_ce_handler(rf, cq); + } while (1); +} + +static void irdma_set_flush_fields(struct irdma_sc_qp *qp, + struct irdma_aeqe_info *info) +{ + struct qp_err_code qp_err; + + qp->sq_flush_code = info->sq; + qp->rq_flush_code = info->rq; + if (info->sq && qp->qp_uk.uk_attrs->hw_rev >= IRDMA_GEN_3) { + qp->err_sq_idx_valid = true; + qp->err_sq_idx = info->wqe_idx; + } + + qp_err = irdma_ae_to_qp_err_code(info->ae_id); + + qp->flush_code = qp_err.flush_code; + qp->event_type = qp_err.event_type; +} + +/** + * irdma_complete_cqp_request - perform post-completion cleanup + * @cqp: device CQP + * @cqp_request: CQP request + * + * Mark CQP request as done, wake up waiting thread or invoke + * callback function and release/free CQP request. + */ +static void irdma_complete_cqp_request(struct irdma_cqp *cqp, + struct irdma_cqp_request *cqp_request) +{ + WRITE_ONCE(cqp_request->request_done, true); + if (cqp_request->waiting) + wake_up(&cqp_request->waitq); + else if (cqp_request->callback_fcn) + cqp_request->callback_fcn(cqp_request); + irdma_put_cqp_request(cqp, cqp_request); +} + +/** + * irdma_process_ae_def_cmpl - handle IRDMA_AE_CQP_DEFERRED_COMPLETE event + * @rf: RDMA PCI function + * @info: AEQ entry info + */ +static void irdma_process_ae_def_cmpl(struct irdma_pci_f *rf, + struct irdma_aeqe_info *info) +{ + u32 sw_def_info; + u64 scratch; + + irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq); + + irdma_sc_cqp_def_cmpl_ae_handler(&rf->sc_dev, info, true, + &scratch, &sw_def_info); + while (scratch) { + struct irdma_cqp_request *cqp_request = + (struct irdma_cqp_request *)(uintptr_t)scratch; + + irdma_complete_cqp_request(&rf->cqp, cqp_request); + irdma_sc_cqp_def_cmpl_ae_handler(&rf->sc_dev, info, false, + &scratch, &sw_def_info); + } +} + +/** + * irdma_process_aeq - handle aeq events + * @rf: RDMA PCI function + */ +static void irdma_process_aeq(struct irdma_pci_f *rf) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_aeq *aeq = &rf->aeq; + struct irdma_sc_aeq *sc_aeq = &aeq->sc_aeq; + struct irdma_aeqe_info aeinfo; + struct irdma_aeqe_info *info = &aeinfo; + int ret; + struct irdma_qp *iwqp = NULL; + struct irdma_cq *iwcq = NULL; + struct irdma_sc_qp *qp = NULL; + struct irdma_device *iwdev = rf->iwdev; + struct irdma_qp_host_ctx_info *ctx_info = NULL; + struct irdma_srq *iwsrq; + u64 srq_id; + unsigned long flags; + + u32 aeqcnt = 0; + + if (!sc_aeq->size) + return; + + do { + memset(info, 0, sizeof(*info)); + ret = irdma_sc_get_next_aeqe(sc_aeq, info); + if (ret) + break; + + if (info->aeqe_overflow) { + ibdev_err(&iwdev->ibdev, "AEQ has overflowed\n"); + rf->reset = true; + rf->gen_ops.request_reset(rf); + return; + } + + aeqcnt++; + ibdev_dbg(&iwdev->ibdev, + "AEQ: ae_id = 0x%x (%s), is_qp = %d, qp_id = %d, tcp_state = %d, iwarp_state = %d, ae_src = %d\n", + info->ae_id, irdma_get_ae_desc(info->ae_id), info->qp, + info->qp_cq_id, info->tcp_state, info->iwarp_state, + info->ae_src); + + if (info->qp) { + spin_lock_irqsave(&rf->qptable_lock, flags); + iwqp = rf->qp_table[info->qp_cq_id]; + if (!iwqp) { + spin_unlock_irqrestore(&rf->qptable_lock, + flags); + if (info->ae_id == IRDMA_AE_QP_SUSPEND_COMPLETE) { + struct irdma_device *iwdev = rf->iwdev; + + if (!iwdev->vsi.tc_change_pending) + continue; + + atomic_dec(&iwdev->vsi.qp_suspend_reqs); + wake_up(&iwdev->suspend_wq); + continue; + } + ibdev_dbg(&iwdev->ibdev, "AEQ: qp_id %d is already freed\n", + info->qp_cq_id); + continue; + } + irdma_qp_add_ref(&iwqp->ibqp); + spin_unlock_irqrestore(&rf->qptable_lock, flags); + qp = &iwqp->sc_qp; + spin_lock_irqsave(&iwqp->lock, flags); + iwqp->hw_tcp_state = info->tcp_state; + iwqp->hw_iwarp_state = info->iwarp_state; + if (info->ae_id != IRDMA_AE_QP_SUSPEND_COMPLETE) + iwqp->last_aeq = info->ae_id; + spin_unlock_irqrestore(&iwqp->lock, flags); + ctx_info = &iwqp->ctx_info; + } else if (info->srq) { + if (info->ae_id != IRDMA_AE_SRQ_LIMIT) + continue; + } else { + if (info->ae_id != IRDMA_AE_CQ_OPERATION_ERROR && + info->ae_id != IRDMA_AE_CQP_DEFERRED_COMPLETE) + continue; + } + + switch (info->ae_id) { + struct irdma_cm_node *cm_node; + case IRDMA_AE_LLP_CONNECTION_ESTABLISHED: + cm_node = iwqp->cm_node; + if (cm_node->accept_pend) { + atomic_dec(&cm_node->listener->pend_accepts_cnt); + cm_node->accept_pend = 0; + } + iwqp->rts_ae_rcvd = 1; + wake_up_interruptible(&iwqp->waitq); + break; + case IRDMA_AE_LLP_FIN_RECEIVED: + if (qp->term_flags) + break; + if (atomic_inc_return(&iwqp->close_timer_started) == 1) { + iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSE_WAIT; + if (iwqp->ibqp_state == IB_QPS_RTS) { + irdma_next_iw_state(iwqp, + IRDMA_QP_STATE_CLOSING, + 0, 0, 0); + irdma_cm_disconn(iwqp); + } + irdma_schedule_cm_timer(iwqp->cm_node, + (struct irdma_puda_buf *)iwqp, + IRDMA_TIMER_TYPE_CLOSE, + 1, 0); + } + break; + case IRDMA_AE_LLP_CLOSE_COMPLETE: + if (qp->term_flags) + irdma_terminate_done(qp, 0); + else + irdma_cm_disconn(iwqp); + break; + case IRDMA_AE_BAD_CLOSE: + case IRDMA_AE_RESET_SENT: + irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, + 0); + irdma_cm_disconn(iwqp); + break; + case IRDMA_AE_LLP_CONNECTION_RESET: + if (atomic_read(&iwqp->close_timer_started)) + break; + irdma_cm_disconn(iwqp); + break; + case IRDMA_AE_QP_SUSPEND_COMPLETE: + if (iwqp->iwdev->vsi.tc_change_pending) { + if (!atomic_dec_return(&iwqp->sc_qp.vsi->qp_suspend_reqs)) + wake_up(&iwqp->iwdev->suspend_wq); + } + if (iwqp->suspend_pending) { + iwqp->suspend_pending = false; + wake_up(&iwqp->iwdev->suspend_wq); + } + break; + case IRDMA_AE_TERMINATE_SENT: + irdma_terminate_send_fin(qp); + break; + case IRDMA_AE_LLP_TERMINATE_RECEIVED: + irdma_terminate_received(qp, info); + break; + case IRDMA_AE_LCE_CQ_CATASTROPHIC: + case IRDMA_AE_CQ_OPERATION_ERROR: + ibdev_err(&iwdev->ibdev, + "Processing CQ[0x%x] op error, AE 0x%04X\n", + info->qp_cq_id, info->ae_id); + spin_lock_irqsave(&rf->cqtable_lock, flags); + iwcq = rf->cq_table[info->qp_cq_id]; + if (!iwcq) { + spin_unlock_irqrestore(&rf->cqtable_lock, + flags); + ibdev_dbg(&iwdev->ibdev, "AEQ: cq_id %d is already freed\n", + info->qp_cq_id); + continue; + } + irdma_cq_add_ref(&iwcq->ibcq); + spin_unlock_irqrestore(&rf->cqtable_lock, flags); + if (iwcq->ibcq.event_handler) { + struct ib_event ibevent; + + ibevent.device = iwcq->ibcq.device; + ibevent.event = IB_EVENT_CQ_ERR; + ibevent.element.cq = &iwcq->ibcq; + iwcq->ibcq.event_handler(&ibevent, + iwcq->ibcq.cq_context); + } + irdma_cq_rem_ref(&iwcq->ibcq); + break; + case IRDMA_AE_SRQ_LIMIT: + srq_id = info->compl_ctx; + spin_lock_irqsave(&rf->srqtable_lock, flags); + iwsrq = rf->srq_table[srq_id]; + if (!iwsrq) { + spin_unlock_irqrestore(&rf->srqtable_lock, + flags); + ibdev_dbg(&iwdev->ibdev, + "AEQ: srq_id %lluu is already freed\n", + srq_id); + continue; + } + irdma_srq_add_ref(&iwsrq->ibsrq); + spin_unlock_irqrestore(&rf->srqtable_lock, flags); + irdma_srq_event(&iwsrq->sc_srq); + irdma_srq_rem_ref(&iwsrq->ibsrq); + break; + case IRDMA_AE_SRQ_CATASTROPHIC_ERROR: + break; + case IRDMA_AE_CQP_DEFERRED_COMPLETE: + /* Remove completed CQP requests from pending list + * and notify about those CQP ops completion. + */ + irdma_process_ae_def_cmpl(rf, info); + break; + case IRDMA_AE_RESET_NOT_SENT: + case IRDMA_AE_LLP_DOUBT_REACHABILITY: + break; + case IRDMA_AE_RESOURCE_EXHAUSTION: + ibdev_err(&iwdev->ibdev, + "Resource exhaustion reason: q1 = %d xmit or rreq = %d\n", + info->ae_src == IRDMA_AE_SOURCE_RSRC_EXHT_Q1, + info->ae_src == IRDMA_AE_SOURCE_RSRC_EXHT_XT_RR); + break; + case IRDMA_AE_PRIV_OPERATION_DENIED: + case IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE: + case IRDMA_AE_STAG_ZERO_INVALID: + case IRDMA_AE_IB_RREQ_AND_Q1_FULL: + case IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION: + case IRDMA_AE_DDP_UBE_INVALID_MO: + case IRDMA_AE_DDP_UBE_INVALID_QN: + case IRDMA_AE_DDP_NO_L_BIT: + case IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION: + case IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE: + case IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST: + case IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP: + case IRDMA_AE_INVALID_ARP_ENTRY: + case IRDMA_AE_INVALID_TCP_OPTION_RCVD: + case IRDMA_AE_STALE_ARP_ENTRY: + case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: + case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: + case IRDMA_AE_LLP_SYN_RECEIVED: + case IRDMA_AE_LLP_TOO_MANY_RETRIES: + case IRDMA_AE_LCE_QP_CATASTROPHIC: + case IRDMA_AE_LCE_FUNCTION_CATASTROPHIC: + case IRDMA_AE_LLP_TOO_MANY_RNRS: + case IRDMA_AE_REMOTE_QP_CATASTROPHIC: + case IRDMA_AE_LOCAL_QP_CATASTROPHIC: + case IRDMA_AE_RCE_QP_CATASTROPHIC: + case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: + default: + ibdev_err(&iwdev->ibdev, + "AEQ: abnormal ae_id = 0x%x (%s), is_qp = %d, qp_id = %d, ae_source = %d\n", + info->ae_id, irdma_get_ae_desc(info->ae_id), + info->qp, info->qp_cq_id, info->ae_src); + if (rdma_protocol_roce(&iwqp->iwdev->ibdev, 1)) { + ctx_info->roce_info->err_rq_idx_valid = + ctx_info->srq_valid ? false : info->err_rq_idx_valid; + if (ctx_info->roce_info->err_rq_idx_valid) { + ctx_info->roce_info->err_rq_idx = info->wqe_idx; + irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, + ctx_info); + } + irdma_set_flush_fields(qp, info); + irdma_cm_disconn(iwqp); + break; + } + ctx_info->iwarp_info->err_rq_idx_valid = info->err_rq_idx_valid; + if (info->rq) { + ctx_info->iwarp_info->err_rq_idx = info->wqe_idx; + ctx_info->tcp_info_valid = false; + ctx_info->iwarp_info_valid = true; + irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, + ctx_info); + } + if (iwqp->hw_iwarp_state != IRDMA_QP_STATE_RTS && + iwqp->hw_iwarp_state != IRDMA_QP_STATE_TERMINATE) { + irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, 1, 0, 0); + irdma_cm_disconn(iwqp); + } else { + irdma_terminate_connection(qp, info); + } + break; + } + if (info->qp) + irdma_qp_rem_ref(&iwqp->ibqp); + } while (1); + + if (aeqcnt) + irdma_sc_repost_aeq_entries(dev, aeqcnt); +} + +/** + * irdma_ena_intr - set up device interrupts + * @dev: hardware control device structure + * @msix_id: id of the interrupt to be enabled + */ +static void irdma_ena_intr(struct irdma_sc_dev *dev, u32 msix_id) +{ + dev->irq_ops->irdma_en_irq(dev, msix_id); +} + +/** + * irdma_aeq_ceq0_irq_thread - irq thread handler for aeq and ceq 0 + * @irq: msix vector + * @private: rf struct + */ +static irqreturn_t irdma_aeq_ceq0_irq_thread(int irq, void *private) +{ + struct irdma_pci_f *rf = private; + + if (rf->msix_shared) + irdma_process_ceq(rf, rf->ceqlist); + irdma_process_aeq(rf); + irdma_ena_intr(&rf->sc_dev, rf->iw_msixtbl[0].idx); + + return IRQ_HANDLED; +} + +/** + * irdma_ceq_irq_thread - irq thread handler for CEQ + * @irq: msix vector + * @private: rf struct + */ +static irqreturn_t irdma_ceq_irq_thread(int irq, void *private) +{ + struct irdma_ceq *iwceq = private; + struct irdma_pci_f *rf = iwceq->rf; + + irdma_process_ceq(rf, iwceq); + irdma_ena_intr(&rf->sc_dev, iwceq->msix_idx); + + return IRQ_HANDLED; +} + +/** + * irdma_save_msix_info - copy msix vector information to iwarp device + * @rf: RDMA PCI function + * + * Allocate iwdev msix table and copy the msix info to the table + * Return 0 if successful, otherwise return error + */ +static int irdma_save_msix_info(struct irdma_pci_f *rf) +{ + struct irdma_qvlist_info *iw_qvlist; + struct irdma_qv_info *iw_qvinfo; + struct msix_entry *pmsix; + u16 ceq_idx; + u32 i; + u32 size; + + if (!rf->msix_count) { + ibdev_err(to_ibdev(&rf->sc_dev), "No MSI-X vectors reserved for RDMA.\n"); + return -EINVAL; + } + + size = sizeof(struct irdma_msix_vector) * rf->msix_count; + size += sizeof(*iw_qvlist); + size += sizeof(*iw_qvinfo) * rf->msix_count - 1; + rf->iw_msixtbl = kzalloc(size, GFP_KERNEL); + if (!rf->iw_msixtbl) + return -ENOMEM; + + rf->iw_qvlist = (struct irdma_qvlist_info *) + (&rf->iw_msixtbl[rf->msix_count]); + iw_qvlist = rf->iw_qvlist; + iw_qvinfo = iw_qvlist->qv_info; + iw_qvlist->num_vectors = rf->msix_count; + if (rf->msix_count <= num_online_cpus()) + rf->msix_shared = true; + else if (rf->msix_count > num_online_cpus() + 1) + rf->msix_count = num_online_cpus() + 1; + + pmsix = rf->msix_entries; + for (i = 0, ceq_idx = 0; i < rf->msix_count; i++, iw_qvinfo++) { + rf->iw_msixtbl[i].idx = pmsix->entry; + rf->iw_msixtbl[i].irq = pmsix->vector; + rf->iw_msixtbl[i].cpu_affinity = ceq_idx; + if (!i) { + iw_qvinfo->aeq_idx = 0; + if (rf->msix_shared) + iw_qvinfo->ceq_idx = ceq_idx++; + else + iw_qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; + } else { + iw_qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; + iw_qvinfo->ceq_idx = ceq_idx++; + } + iw_qvinfo->itr_idx = IRDMA_IDX_NOITR; + iw_qvinfo->v_idx = rf->iw_msixtbl[i].idx; + pmsix++; + } + + return 0; +} + +/** + * irdma_destroy_irq - destroy device interrupts + * @rf: RDMA PCI function + * @msix_vec: msix vector to disable irq + * @dev_id: parameter to pass to free_irq (used during irq setup) + * + * The function is called when destroying aeq/ceq + */ +static void irdma_destroy_irq(struct irdma_pci_f *rf, + struct irdma_msix_vector *msix_vec, void *dev_id) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + + dev->irq_ops->irdma_dis_irq(dev, msix_vec->idx); + irq_update_affinity_hint(msix_vec->irq, NULL); + free_irq(msix_vec->irq, dev_id); +} + +/** + * irdma_destroy_cqp - destroy control qp + * @rf: RDMA PCI function + * @free_hwcqp: 1 if hw cqp should be freed + * + * Issue destroy cqp request and + * free the resources associated with the cqp + */ +static void irdma_destroy_cqp(struct irdma_pci_f *rf, bool free_hwcqp) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_cqp *cqp = &rf->cqp; + int status = 0; + + status = irdma_sc_cqp_destroy(dev->cqp, free_hwcqp); + if (status) + ibdev_dbg(to_ibdev(dev), "ERR: Destroy CQP failed %d\n", status); + + irdma_cleanup_pending_cqp_op(rf); + dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va, + cqp->sq.pa); + cqp->sq.va = NULL; + kfree(cqp->ooo_op_array); + cqp->ooo_op_array = NULL; + kfree(cqp->scratch_array); + cqp->scratch_array = NULL; + kfree(cqp->cqp_requests); + cqp->cqp_requests = NULL; +} + +static void irdma_destroy_virt_aeq(struct irdma_pci_f *rf) +{ + struct irdma_aeq *aeq = &rf->aeq; + u32 pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); + dma_addr_t *pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; + + irdma_unmap_vm_page_list(&rf->hw, pg_arr, pg_cnt); + irdma_free_pble(rf->pble_rsrc, &aeq->palloc); + vfree(aeq->mem.va); +} + +/** + * irdma_destroy_aeq - destroy aeq + * @rf: RDMA PCI function + * + * Issue a destroy aeq request and + * free the resources associated with the aeq + * The function is called during driver unload + */ +static void irdma_destroy_aeq(struct irdma_pci_f *rf) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_aeq *aeq = &rf->aeq; + int status = -EBUSY; + + if (!rf->msix_shared) { + if (rf->sc_dev.privileged) + rf->sc_dev.irq_ops->irdma_cfg_aeq( + &rf->sc_dev, rf->iw_msixtbl->idx, false); + irdma_destroy_irq(rf, rf->iw_msixtbl, rf); + } + if (rf->reset) + goto exit; + + aeq->sc_aeq.size = 0; + status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_DESTROY); + if (status) + ibdev_dbg(to_ibdev(dev), "ERR: Destroy AEQ failed %d\n", status); + +exit: + if (aeq->virtual_map) + irdma_destroy_virt_aeq(rf); + else { + dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, + aeq->mem.pa); + aeq->mem.va = NULL; + } +} + +/** + * irdma_destroy_ceq - destroy ceq + * @rf: RDMA PCI function + * @iwceq: ceq to be destroyed + * + * Issue a destroy ceq request and + * free the resources associated with the ceq + */ +static void irdma_destroy_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + int status; + + if (rf->reset) + goto exit; + + status = irdma_sc_ceq_destroy(&iwceq->sc_ceq, 0, 1); + if (status) { + ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy command failed %d\n", status); + goto exit; + } + + status = irdma_sc_cceq_destroy_done(&iwceq->sc_ceq); + if (status) + ibdev_dbg(to_ibdev(dev), "ERR: CEQ destroy completion failed %d\n", + status); +exit: + dma_free_coherent(dev->hw->device, iwceq->mem.size, iwceq->mem.va, + iwceq->mem.pa); + iwceq->mem.va = NULL; +} + +/** + * irdma_del_ceq_0 - destroy ceq 0 + * @rf: RDMA PCI function + * + * Disable the ceq 0 interrupt and destroy the ceq 0 + */ +static void irdma_del_ceq_0(struct irdma_pci_f *rf) +{ + struct irdma_ceq *iwceq = rf->ceqlist; + struct irdma_msix_vector *msix_vec; + + if (rf->msix_shared) { + msix_vec = &rf->iw_msixtbl[0]; + if (rf->sc_dev.privileged) + rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, + msix_vec->ceq_id, + msix_vec->idx, false); + irdma_destroy_irq(rf, msix_vec, rf); + } else { + msix_vec = &rf->iw_msixtbl[1]; + irdma_destroy_irq(rf, msix_vec, iwceq); + } + + irdma_destroy_ceq(rf, iwceq); + rf->sc_dev.ceq_valid = false; + rf->ceqs_count = 0; +} + +/** + * irdma_del_ceqs - destroy all ceq's except CEQ 0 + * @rf: RDMA PCI function + * + * Go through all of the device ceq's, except 0, and for each + * ceq disable the ceq interrupt and destroy the ceq + */ +static void irdma_del_ceqs(struct irdma_pci_f *rf) +{ + struct irdma_ceq *iwceq = &rf->ceqlist[1]; + struct irdma_msix_vector *msix_vec; + u32 i = 0; + + if (rf->msix_shared) + msix_vec = &rf->iw_msixtbl[1]; + else + msix_vec = &rf->iw_msixtbl[2]; + + for (i = 1; i < rf->ceqs_count; i++, msix_vec++, iwceq++) { + if (rf->sc_dev.privileged) + rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, + msix_vec->ceq_id, + msix_vec->idx, false); + irdma_destroy_irq(rf, msix_vec, iwceq); + irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, + IRDMA_OP_CEQ_DESTROY); + dma_free_coherent(rf->sc_dev.hw->device, iwceq->mem.size, + iwceq->mem.va, iwceq->mem.pa); + iwceq->mem.va = NULL; + } + rf->ceqs_count = 1; +} + +/** + * irdma_destroy_ccq - destroy control cq + * @rf: RDMA PCI function + * + * Issue destroy ccq request and + * free the resources associated with the ccq + */ +static void irdma_destroy_ccq(struct irdma_pci_f *rf) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_ccq *ccq = &rf->ccq; + int status = 0; + + if (rf->cqp_cmpl_wq) + destroy_workqueue(rf->cqp_cmpl_wq); + if (!rf->reset) + status = irdma_sc_ccq_destroy(dev->ccq, 0, true); + if (status) + ibdev_dbg(to_ibdev(dev), "ERR: CCQ destroy failed %d\n", status); + dma_free_coherent(dev->hw->device, ccq->mem_cq.size, ccq->mem_cq.va, + ccq->mem_cq.pa); + ccq->mem_cq.va = NULL; +} + +/** + * irdma_close_hmc_objects_type - delete hmc objects of a given type + * @dev: iwarp device + * @obj_type: the hmc object type to be deleted + * @hmc_info: host memory info struct + * @privileged: permission to close HMC objects + * @reset: true if called before reset + */ +static void irdma_close_hmc_objects_type(struct irdma_sc_dev *dev, + enum irdma_hmc_rsrc_type obj_type, + struct irdma_hmc_info *hmc_info, + bool privileged, bool reset) +{ + struct irdma_hmc_del_obj_info info = {}; + + info.hmc_info = hmc_info; + info.rsrc_type = obj_type; + info.count = hmc_info->hmc_obj[obj_type].cnt; + info.privileged = privileged; + if (irdma_sc_del_hmc_obj(dev, &info, reset)) + ibdev_dbg(to_ibdev(dev), "ERR: del HMC obj of type %d failed\n", + obj_type); +} + +/** + * irdma_del_hmc_objects - remove all device hmc objects + * @dev: iwarp device + * @hmc_info: hmc_info to free + * @privileged: permission to delete HMC objects + * @reset: true if called before reset + * @vers: hardware version + */ +void irdma_del_hmc_objects(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, bool privileged, + bool reset, enum irdma_vers vers) +{ + unsigned int i; + + for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { + if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) + irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], + hmc_info, privileged, reset); + if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) + break; + } +} + +/** + * irdma_create_hmc_obj_type - create hmc object of a given type + * @dev: hardware control device structure + * @info: information for the hmc object to create + */ +static int irdma_create_hmc_obj_type(struct irdma_sc_dev *dev, + struct irdma_hmc_create_obj_info *info) +{ + return irdma_sc_create_hmc_obj(dev, info); +} + +/** + * irdma_create_hmc_objs - create all hmc objects for the device + * @rf: RDMA PCI function + * @privileged: permission to create HMC objects + * @vers: HW version + * + * Create the device hmc objects and allocate hmc pages + * Return 0 if successful, otherwise clean up and return error + */ +static int irdma_create_hmc_objs(struct irdma_pci_f *rf, bool privileged, + enum irdma_vers vers) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_hmc_create_obj_info info = {}; + int i, status = 0; + + info.hmc_info = dev->hmc_info; + info.privileged = privileged; + info.entry_type = rf->sd_type; + + for (i = 0; i < IW_HMC_OBJ_TYPE_NUM; i++) { + if (iw_hmc_obj_types[i] == IRDMA_HMC_IW_PBLE) + continue; + if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) { + info.rsrc_type = iw_hmc_obj_types[i]; + info.count = dev->hmc_info->hmc_obj[info.rsrc_type].cnt; + info.add_sd_cnt = 0; + status = irdma_create_hmc_obj_type(dev, &info); + if (status) { + ibdev_dbg(to_ibdev(dev), + "ERR: create obj type %d status = %d\n", + iw_hmc_obj_types[i], status); + break; + } + } + if (vers == IRDMA_GEN_1 && i == IRDMA_HMC_IW_TIMER) + break; + } + + if (!status) + return irdma_sc_static_hmc_pages_allocated(dev->cqp, 0, dev->hmc_fn_id, + true, true); + + while (i) { + i--; + /* destroy the hmc objects of a given type */ + if (dev->hmc_info->hmc_obj[iw_hmc_obj_types[i]].cnt) + irdma_close_hmc_objects_type(dev, iw_hmc_obj_types[i], + dev->hmc_info, privileged, + false); + } + + return status; +} + +/** + * irdma_obj_aligned_mem - get aligned memory from device allocated memory + * @rf: RDMA PCI function + * @memptr: points to the memory addresses + * @size: size of memory needed + * @mask: mask for the aligned memory + * + * Get aligned memory of the requested size and + * update the memptr to point to the new aligned memory + * Return 0 if successful, otherwise return no memory error + */ +int irdma_obj_aligned_mem(struct irdma_pci_f *rf, struct irdma_dma_mem *memptr, + u32 size, u32 mask) +{ + unsigned long va, newva; + unsigned long extra; + + va = (unsigned long)rf->obj_next.va; + newva = va; + if (mask) + newva = ALIGN(va, (unsigned long)mask + 1ULL); + extra = newva - va; + memptr->va = (u8 *)va + extra; + memptr->pa = rf->obj_next.pa + extra; + memptr->size = size; + if (((u8 *)memptr->va + size) > ((u8 *)rf->obj_mem.va + rf->obj_mem.size)) + return -ENOMEM; + + rf->obj_next.va = (u8 *)memptr->va + size; + rf->obj_next.pa = memptr->pa + size; + + return 0; +} + +/** + * irdma_create_cqp - create control qp + * @rf: RDMA PCI function + * + * Return 0, if the cqp and all the resources associated with it + * are successfully created, otherwise return error + */ +static int irdma_create_cqp(struct irdma_pci_f *rf) +{ + u32 sqsize = IRDMA_CQP_SW_SQSIZE_2048; + struct irdma_dma_mem mem; + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_cqp_init_info cqp_init_info = {}; + struct irdma_cqp *cqp = &rf->cqp; + u16 maj_err, min_err; + int i, status; + + cqp->cqp_requests = kcalloc(sqsize, sizeof(*cqp->cqp_requests), + GFP_KERNEL); + if (!cqp->cqp_requests) + return -ENOMEM; + + cqp->scratch_array = kcalloc(sqsize, sizeof(*cqp->scratch_array), + GFP_KERNEL); + if (!cqp->scratch_array) { + status = -ENOMEM; + goto err_scratch; + } + + cqp->ooo_op_array = kcalloc(sqsize, sizeof(*cqp->ooo_op_array), + GFP_KERNEL); + if (!cqp->ooo_op_array) { + status = -ENOMEM; + goto err_oop; + } + cqp_init_info.ooo_op_array = cqp->ooo_op_array; + dev->cqp = &cqp->sc_cqp; + dev->cqp->dev = dev; + cqp->sq.size = ALIGN(sizeof(struct irdma_cqp_sq_wqe) * sqsize, + IRDMA_CQP_ALIGNMENT); + cqp->sq.va = dma_alloc_coherent(dev->hw->device, cqp->sq.size, + &cqp->sq.pa, GFP_KERNEL); + if (!cqp->sq.va) { + status = -ENOMEM; + goto err_sq; + } + + status = irdma_obj_aligned_mem(rf, &mem, sizeof(struct irdma_cqp_ctx), + IRDMA_HOST_CTX_ALIGNMENT_M); + if (status) + goto err_ctx; + + dev->cqp->host_ctx_pa = mem.pa; + dev->cqp->host_ctx = mem.va; + /* populate the cqp init info */ + cqp_init_info.dev = dev; + cqp_init_info.sq_size = sqsize; + cqp_init_info.sq = cqp->sq.va; + cqp_init_info.sq_pa = cqp->sq.pa; + cqp_init_info.host_ctx_pa = mem.pa; + cqp_init_info.host_ctx = mem.va; + if (dev->privileged) { + cqp_init_info.hmc_profile = rf->rsrc_profile; + cqp_init_info.ena_vf_count = rf->max_rdma_vfs; + } + cqp_init_info.scratch_array = cqp->scratch_array; + cqp_init_info.protocol_used = rf->protocol_used; + cqp_init_info.en_rem_endpoint_trk = rf->en_rem_endpoint_trk; + memcpy(&cqp_init_info.dcqcn_params, &rf->dcqcn_params, + sizeof(cqp_init_info.dcqcn_params)); + + switch (rf->rdma_ver) { + case IRDMA_GEN_1: + cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_1; + break; + case IRDMA_GEN_2: + cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_2; + break; + case IRDMA_GEN_3: + case IRDMA_GEN_4: + cqp_init_info.hw_maj_ver = IRDMA_CQPHC_HW_MAJVER_GEN_3; + cqp_init_info.ts_override = 1; + break; + } + status = irdma_sc_cqp_init(dev->cqp, &cqp_init_info); + if (status) { + ibdev_dbg(to_ibdev(dev), "ERR: cqp init status %d\n", status); + goto err_ctx; + } + + spin_lock_init(&cqp->req_lock); + spin_lock_init(&cqp->compl_lock); + + status = irdma_sc_cqp_create(dev->cqp, &maj_err, &min_err); + if (status) { + ibdev_dbg(to_ibdev(dev), + "ERR: cqp create failed - status %d maj_err %d min_err %d\n", + status, maj_err, min_err); + goto err_ctx; + } + + INIT_LIST_HEAD(&cqp->cqp_avail_reqs); + INIT_LIST_HEAD(&cqp->cqp_pending_reqs); + + /* init the waitqueue of the cqp_requests and add them to the list */ + for (i = 0; i < sqsize; i++) { + init_waitqueue_head(&cqp->cqp_requests[i].waitq); + list_add_tail(&cqp->cqp_requests[i].list, &cqp->cqp_avail_reqs); + } + init_waitqueue_head(&cqp->remove_wq); + return 0; + +err_ctx: + dma_free_coherent(dev->hw->device, cqp->sq.size, cqp->sq.va, + cqp->sq.pa); + cqp->sq.va = NULL; +err_sq: + kfree(cqp->ooo_op_array); + cqp->ooo_op_array = NULL; +err_oop: + kfree(cqp->scratch_array); + cqp->scratch_array = NULL; +err_scratch: + kfree(cqp->cqp_requests); + cqp->cqp_requests = NULL; + + return status; +} + +/** + * irdma_create_ccq - create control cq + * @rf: RDMA PCI function + * + * Return 0, if the ccq and the resources associated with it + * are successfully created, otherwise return error + */ +static int irdma_create_ccq(struct irdma_pci_f *rf) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_ccq_init_info info = {}; + struct irdma_ccq *ccq = &rf->ccq; + int status; + + dev->ccq = &ccq->sc_cq; + dev->ccq->dev = dev; + info.dev = dev; + ccq->shadow_area.size = sizeof(struct irdma_cq_shadow_area); + ccq->mem_cq.size = ALIGN(sizeof(struct irdma_cqe) * IW_CCQ_SIZE, + IRDMA_CQ0_ALIGNMENT); + ccq->mem_cq.va = dma_alloc_coherent(dev->hw->device, ccq->mem_cq.size, + &ccq->mem_cq.pa, GFP_KERNEL); + if (!ccq->mem_cq.va) + return -ENOMEM; + + status = irdma_obj_aligned_mem(rf, &ccq->shadow_area, + ccq->shadow_area.size, + IRDMA_SHADOWAREA_M); + if (status) + goto exit; + + ccq->sc_cq.back_cq = ccq; + /* populate the ccq init info */ + info.cq_base = ccq->mem_cq.va; + info.cq_pa = ccq->mem_cq.pa; + info.num_elem = IW_CCQ_SIZE; + info.shadow_area = ccq->shadow_area.va; + info.shadow_area_pa = ccq->shadow_area.pa; + info.ceqe_mask = false; + info.ceq_id_valid = true; + info.shadow_read_threshold = 16; + info.vsi = &rf->default_vsi; + status = irdma_sc_ccq_init(dev->ccq, &info); + if (!status) + status = irdma_sc_ccq_create(dev->ccq, 0, true, true); +exit: + if (status) { + dma_free_coherent(dev->hw->device, ccq->mem_cq.size, + ccq->mem_cq.va, ccq->mem_cq.pa); + ccq->mem_cq.va = NULL; + } + + return status; +} + +/** + * irdma_alloc_set_mac - set up a mac address table entry + * @iwdev: irdma device + * + * Allocate a mac ip entry and add it to the hw table Return 0 + * if successful, otherwise return error + */ +static int irdma_alloc_set_mac(struct irdma_device *iwdev) +{ + int status; + + status = irdma_alloc_local_mac_entry(iwdev->rf, + &iwdev->mac_ip_table_idx); + if (!status) { + status = irdma_add_local_mac_entry(iwdev->rf, + (const u8 *)iwdev->netdev->dev_addr, + (u8)iwdev->mac_ip_table_idx); + if (status) + irdma_del_local_mac_entry(iwdev->rf, + (u8)iwdev->mac_ip_table_idx); + } + return status; +} + +/** + * irdma_cfg_ceq_vector - set up the msix interrupt vector for + * ceq + * @rf: RDMA PCI function + * @iwceq: ceq associated with the vector + * @ceq_id: the id number of the iwceq + * @msix_vec: interrupt vector information + * + * Allocate interrupt resources and enable irq handling + * Return 0 if successful, otherwise return error + */ +static int irdma_cfg_ceq_vector(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, + u16 ceq_id, struct irdma_msix_vector *msix_vec) +{ + int status; + + if (rf->msix_shared && !ceq_id) { + snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, + "irdma-%s-AEQCEQ-0", dev_name(&rf->pcidev->dev)); + status = request_threaded_irq(msix_vec->irq, NULL, + irdma_aeq_ceq0_irq_thread, IRQF_ONESHOT, + msix_vec->name, rf); + } else { + snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, + "irdma-%s-CEQ-%d", + dev_name(&rf->pcidev->dev), ceq_id); + status = request_threaded_irq(msix_vec->irq, NULL, + irdma_ceq_irq_thread, IRQF_ONESHOT, + msix_vec->name, iwceq); + } + cpumask_clear(&msix_vec->mask); + cpumask_set_cpu(msix_vec->cpu_affinity, &msix_vec->mask); + irq_update_affinity_hint(msix_vec->irq, &msix_vec->mask); + if (status) { + ibdev_dbg(&rf->iwdev->ibdev, "ERR: ceq irq config fail\n"); + return status; + } + + msix_vec->ceq_id = ceq_id; + if (rf->sc_dev.privileged) + rf->sc_dev.irq_ops->irdma_cfg_ceq(&rf->sc_dev, ceq_id, + msix_vec->idx, true); + else if (rf->rdma_ver == IRDMA_GEN_2) + status = irdma_vchnl_req_ceq_vec_map_gen2(&rf->sc_dev, ceq_id, + msix_vec->idx); + else + status = irdma_vchnl_req_ceq_vec_map(&rf->sc_dev, ceq_id, + msix_vec->idx); + + return status; +} + +/** + * irdma_cfg_aeq_vector - set up the msix vector for aeq + * @rf: RDMA PCI function + * + * Allocate interrupt resources and enable irq handling + * Return 0 if successful, otherwise return error + */ +static int irdma_cfg_aeq_vector(struct irdma_pci_f *rf) +{ + struct irdma_msix_vector *msix_vec = rf->iw_msixtbl; + int status = 0; + + if (!rf->msix_shared) { + snprintf(msix_vec->name, sizeof(msix_vec->name) - 1, + "irdma-%s-AEQ", dev_name(&rf->pcidev->dev)); + status = request_threaded_irq(msix_vec->irq, NULL, + irdma_aeq_ceq0_irq_thread, IRQF_ONESHOT, + msix_vec->name, rf); + } + + if (status) { + ibdev_dbg(&rf->iwdev->ibdev, "ERR: aeq irq config fail\n"); + return status; + } + + if (rf->sc_dev.privileged) + rf->sc_dev.irq_ops->irdma_cfg_aeq(&rf->sc_dev, msix_vec->idx, + true); + else if (rf->rdma_ver == IRDMA_GEN_2) + status = irdma_vchnl_req_aeq_vec_map_gen2(&rf->sc_dev, + msix_vec->idx); + else + status = irdma_vchnl_req_aeq_vec_map(&rf->sc_dev, msix_vec->idx); + return status; +} + +/** + * irdma_create_ceq - create completion event queue + * @rf: RDMA PCI function + * @iwceq: pointer to the ceq resources to be created + * @ceq_id: the id number of the iwceq + * @vsi: SC vsi struct + * + * Return 0, if the ceq and the resources associated with it + * are successfully created, otherwise return error + */ +static int irdma_create_ceq(struct irdma_pci_f *rf, struct irdma_ceq *iwceq, + u16 ceq_id, struct irdma_sc_vsi *vsi) +{ + int status; + struct irdma_ceq_init_info info = {}; + struct irdma_sc_dev *dev = &rf->sc_dev; + u32 ceq_size; + + info.ceq_id = ceq_id; + iwceq->rf = rf; + ceq_size = min(rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt, + dev->hw_attrs.max_hw_ceq_size); + iwceq->mem.size = ALIGN(sizeof(struct irdma_ceqe) * ceq_size, + IRDMA_CEQ_ALIGNMENT); + iwceq->mem.va = dma_alloc_coherent(dev->hw->device, iwceq->mem.size, + &iwceq->mem.pa, GFP_KERNEL); + if (!iwceq->mem.va) + return -ENOMEM; + + info.ceq_id = ceq_id; + info.ceqe_base = iwceq->mem.va; + info.ceqe_pa = iwceq->mem.pa; + info.elem_cnt = ceq_size; + + iwceq->sc_ceq.ceq_id = ceq_id; + info.dev = dev; + info.vsi = vsi; + status = irdma_sc_ceq_init(&iwceq->sc_ceq, &info); + if (!status) { + if (dev->ceq_valid) + status = irdma_cqp_ceq_cmd(&rf->sc_dev, &iwceq->sc_ceq, + IRDMA_OP_CEQ_CREATE); + else + status = irdma_sc_cceq_create(&iwceq->sc_ceq); + } + + if (status) { + dma_free_coherent(dev->hw->device, iwceq->mem.size, + iwceq->mem.va, iwceq->mem.pa); + iwceq->mem.va = NULL; + } + + return status; +} + +/** + * irdma_setup_ceq_0 - create CEQ 0 and it's interrupt resource + * @rf: RDMA PCI function + * + * Allocate a list for all device completion event queues + * Create the ceq 0 and configure it's msix interrupt vector + * Return 0, if successfully set up, otherwise return error + */ +static int irdma_setup_ceq_0(struct irdma_pci_f *rf) +{ + struct irdma_ceq *iwceq; + struct irdma_msix_vector *msix_vec; + u32 i; + int status = 0; + u32 num_ceqs; + + num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); + rf->ceqlist = kcalloc(num_ceqs, sizeof(*rf->ceqlist), GFP_KERNEL); + if (!rf->ceqlist) { + status = -ENOMEM; + goto exit; + } + + iwceq = &rf->ceqlist[0]; + status = irdma_create_ceq(rf, iwceq, 0, &rf->default_vsi); + if (status) { + ibdev_dbg(&rf->iwdev->ibdev, "ERR: create ceq status = %d\n", + status); + goto exit; + } + + spin_lock_init(&iwceq->ce_lock); + i = rf->msix_shared ? 0 : 1; + msix_vec = &rf->iw_msixtbl[i]; + iwceq->irq = msix_vec->irq; + iwceq->msix_idx = msix_vec->idx; + status = irdma_cfg_ceq_vector(rf, iwceq, 0, msix_vec); + if (status) { + irdma_destroy_ceq(rf, iwceq); + goto exit; + } + + irdma_ena_intr(&rf->sc_dev, msix_vec->idx); + rf->ceqs_count++; + +exit: + if (status && !rf->ceqs_count) { + kfree(rf->ceqlist); + rf->ceqlist = NULL; + return status; + } + rf->sc_dev.ceq_valid = true; + + return 0; +} + +/** + * irdma_setup_ceqs - manage the device ceq's and their interrupt resources + * @rf: RDMA PCI function + * @vsi: VSI structure for this CEQ + * + * Allocate a list for all device completion event queues + * Create the ceq's and configure their msix interrupt vectors + * Return 0, if ceqs are successfully set up, otherwise return error + */ +static int irdma_setup_ceqs(struct irdma_pci_f *rf, struct irdma_sc_vsi *vsi) +{ + u32 i; + u16 ceq_id; + struct irdma_ceq *iwceq; + struct irdma_msix_vector *msix_vec; + int status; + u32 num_ceqs; + + num_ceqs = min(rf->msix_count, rf->sc_dev.hmc_fpm_misc.max_ceqs); + i = (rf->msix_shared) ? 1 : 2; + for (ceq_id = 1; i < num_ceqs; i++, ceq_id++) { + iwceq = &rf->ceqlist[ceq_id]; + status = irdma_create_ceq(rf, iwceq, ceq_id, vsi); + if (status) { + ibdev_dbg(&rf->iwdev->ibdev, + "ERR: create ceq status = %d\n", status); + goto del_ceqs; + } + spin_lock_init(&iwceq->ce_lock); + msix_vec = &rf->iw_msixtbl[i]; + iwceq->irq = msix_vec->irq; + iwceq->msix_idx = msix_vec->idx; + status = irdma_cfg_ceq_vector(rf, iwceq, ceq_id, msix_vec); + if (status) { + irdma_destroy_ceq(rf, iwceq); + goto del_ceqs; + } + irdma_ena_intr(&rf->sc_dev, msix_vec->idx); + rf->ceqs_count++; + } + + return 0; + +del_ceqs: + irdma_del_ceqs(rf); + + return status; +} + +static int irdma_create_virt_aeq(struct irdma_pci_f *rf, u32 size) +{ + struct irdma_aeq *aeq = &rf->aeq; + dma_addr_t *pg_arr; + u32 pg_cnt; + int status; + + if (rf->rdma_ver < IRDMA_GEN_2) + return -EOPNOTSUPP; + + aeq->mem.size = sizeof(struct irdma_sc_aeqe) * size; + aeq->mem.va = vzalloc(aeq->mem.size); + + if (!aeq->mem.va) + return -ENOMEM; + + pg_cnt = DIV_ROUND_UP(aeq->mem.size, PAGE_SIZE); + status = irdma_get_pble(rf->pble_rsrc, &aeq->palloc, pg_cnt, true); + if (status) { + vfree(aeq->mem.va); + return status; + } + + pg_arr = (dma_addr_t *)aeq->palloc.level1.addr; + status = irdma_map_vm_page_list(&rf->hw, aeq->mem.va, pg_arr, pg_cnt); + if (status) { + irdma_free_pble(rf->pble_rsrc, &aeq->palloc); + vfree(aeq->mem.va); + return status; + } + + return 0; +} + +/** + * irdma_create_aeq - create async event queue + * @rf: RDMA PCI function + * + * Return 0, if the aeq and the resources associated with it + * are successfully created, otherwise return error + */ +static int irdma_create_aeq(struct irdma_pci_f *rf) +{ + struct irdma_aeq_init_info info = {}; + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_aeq *aeq = &rf->aeq; + struct irdma_hmc_info *hmc_info = rf->sc_dev.hmc_info; + u32 aeq_size; + u8 multiplier = (rf->protocol_used == IRDMA_IWARP_PROTOCOL_ONLY) ? 2 : 1; + int status; + + aeq_size = multiplier * hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt + + hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; + aeq_size = min(aeq_size, dev->hw_attrs.max_hw_aeq_size); + /* GEN_3 does not support virtual AEQ. Cap at max Kernel alloc size */ + if (rf->rdma_ver >= IRDMA_GEN_3) + aeq_size = min(aeq_size, (u32)((PAGE_SIZE << MAX_PAGE_ORDER) / + sizeof(struct irdma_sc_aeqe))); + aeq->mem.size = ALIGN(sizeof(struct irdma_sc_aeqe) * aeq_size, + IRDMA_AEQ_ALIGNMENT); + aeq->mem.va = dma_alloc_coherent(dev->hw->device, aeq->mem.size, + &aeq->mem.pa, + GFP_KERNEL | __GFP_NOWARN); + if (aeq->mem.va) + goto skip_virt_aeq; + else if (rf->rdma_ver >= IRDMA_GEN_3) + return -ENOMEM; + + /* physically mapped aeq failed. setup virtual aeq */ + status = irdma_create_virt_aeq(rf, aeq_size); + if (status) + return status; + + info.virtual_map = true; + aeq->virtual_map = info.virtual_map; + info.pbl_chunk_size = 1; + info.first_pm_pbl_idx = aeq->palloc.level1.idx; + +skip_virt_aeq: + info.aeqe_base = aeq->mem.va; + info.aeq_elem_pa = aeq->mem.pa; + info.elem_cnt = aeq_size; + info.dev = dev; + info.msix_idx = rf->iw_msixtbl->idx; + status = irdma_sc_aeq_init(&aeq->sc_aeq, &info); + if (status) + goto err; + + status = irdma_cqp_aeq_cmd(dev, &aeq->sc_aeq, IRDMA_OP_AEQ_CREATE); + if (status) + goto err; + + return 0; + +err: + if (aeq->virtual_map) + irdma_destroy_virt_aeq(rf); + else { + dma_free_coherent(dev->hw->device, aeq->mem.size, aeq->mem.va, + aeq->mem.pa); + aeq->mem.va = NULL; + } + + return status; +} + +/** + * irdma_setup_aeq - set up the device aeq + * @rf: RDMA PCI function + * + * Create the aeq and configure its msix interrupt vector + * Return 0 if successful, otherwise return error + */ +static int irdma_setup_aeq(struct irdma_pci_f *rf) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + int status; + + status = irdma_create_aeq(rf); + if (status) + return status; + + status = irdma_cfg_aeq_vector(rf); + if (status) { + irdma_destroy_aeq(rf); + return status; + } + + if (!rf->msix_shared) + irdma_ena_intr(dev, rf->iw_msixtbl[0].idx); + + return 0; +} + +/** + * irdma_initialize_ilq - create iwarp local queue for cm + * @iwdev: irdma device + * + * Return 0 if successful, otherwise return error + */ +static int irdma_initialize_ilq(struct irdma_device *iwdev) +{ + struct irdma_puda_rsrc_info info = {}; + int status; + + info.type = IRDMA_PUDA_RSRC_TYPE_ILQ; + info.cq_id = 1; + info.qp_id = 1; + info.count = 1; + info.pd_id = 1; + info.abi_ver = IRDMA_ABI_VER; + info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); + info.rq_size = info.sq_size; + info.buf_size = 1024; + info.tx_buf_cnt = 2 * info.sq_size; + info.receive = irdma_receive_ilq; + info.xmit_complete = irdma_free_sqbuf; + status = irdma_puda_create_rsrc(&iwdev->vsi, &info); + if (status) + ibdev_dbg(&iwdev->ibdev, "ERR: ilq create fail\n"); + + return status; +} + +/** + * irdma_initialize_ieq - create iwarp exception queue + * @iwdev: irdma device + * + * Return 0 if successful, otherwise return error + */ +static int irdma_initialize_ieq(struct irdma_device *iwdev) +{ + struct irdma_puda_rsrc_info info = {}; + int status; + + info.type = IRDMA_PUDA_RSRC_TYPE_IEQ; + info.cq_id = 2; + info.qp_id = iwdev->vsi.exception_lan_q; + info.count = 1; + info.pd_id = 2; + info.abi_ver = IRDMA_ABI_VER; + info.sq_size = min(iwdev->rf->max_qp / 2, (u32)32768); + info.rq_size = info.sq_size; + info.buf_size = iwdev->vsi.mtu + IRDMA_IPV4_PAD; + info.tx_buf_cnt = 4096; + status = irdma_puda_create_rsrc(&iwdev->vsi, &info); + if (status) + ibdev_dbg(&iwdev->ibdev, "ERR: ieq create fail\n"); + + return status; +} + +/** + * irdma_reinitialize_ieq - destroy and re-create ieq + * @vsi: VSI structure + */ +void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi) +{ + struct irdma_device *iwdev = vsi->back_vsi; + struct irdma_pci_f *rf = iwdev->rf; + + irdma_puda_dele_rsrc(vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, false); + if (irdma_initialize_ieq(iwdev)) { + iwdev->rf->reset = true; + rf->gen_ops.request_reset(rf); + } +} + +/** + * irdma_hmc_setup - create hmc objects for the device + * @rf: RDMA PCI function + * + * Set up the device private memory space for the number and size of + * the hmc objects and create the objects + * Return 0 if successful, otherwise return error + */ +static int irdma_hmc_setup(struct irdma_pci_f *rf) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + int status; + u32 qpcnt; + + qpcnt = rsrc_limits_table[rf->limits_sel].qplimit; + + rf->sd_type = IRDMA_SD_TYPE_DIRECT; + status = irdma_cfg_fpm_val(dev, qpcnt); + if (status) + return status; + + status = irdma_create_hmc_objs(rf, true, rf->rdma_ver); + + return status; +} + +/** + * irdma_del_init_mem - deallocate memory resources + * @rf: RDMA PCI function + */ +static void irdma_del_init_mem(struct irdma_pci_f *rf) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + + if (!rf->sc_dev.privileged) + irdma_vchnl_req_put_hmc_fcn(&rf->sc_dev); + kfree(dev->hmc_info->sd_table.sd_entry); + dev->hmc_info->sd_table.sd_entry = NULL; + vfree(rf->mem_rsrc); + rf->mem_rsrc = NULL; + dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, + rf->obj_mem.pa); + rf->obj_mem.va = NULL; + if (rf->rdma_ver != IRDMA_GEN_1) { + kfree(rf->allocated_ws_nodes); + rf->allocated_ws_nodes = NULL; + } + kfree(rf->ceqlist); + rf->ceqlist = NULL; + kfree(rf->iw_msixtbl); + rf->iw_msixtbl = NULL; + kfree(rf->hmc_info_mem); + rf->hmc_info_mem = NULL; +} +/** + * irdma_initialize_dev - initialize device + * @rf: RDMA PCI function + * + * Allocate memory for the hmc objects and initialize iwdev + * Return 0 if successful, otherwise clean up the resources + * and return error + */ +static int irdma_initialize_dev(struct irdma_pci_f *rf) +{ + int status; + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_device_init_info info = {}; + struct irdma_dma_mem mem; + u32 size; + + size = sizeof(struct irdma_hmc_pble_rsrc) + + sizeof(struct irdma_hmc_info) + + (sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX); + + rf->hmc_info_mem = kzalloc(size, GFP_KERNEL); + if (!rf->hmc_info_mem) + return -ENOMEM; + + rf->pble_rsrc = (struct irdma_hmc_pble_rsrc *)rf->hmc_info_mem; + dev->hmc_info = &rf->hw.hmc; + dev->hmc_info->hmc_obj = (struct irdma_hmc_obj_info *) + (rf->pble_rsrc + 1); + + status = irdma_obj_aligned_mem(rf, &mem, IRDMA_QUERY_FPM_BUF_SIZE, + IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); + if (status) + goto error; + + info.fpm_query_buf_pa = mem.pa; + info.fpm_query_buf = mem.va; + + status = irdma_obj_aligned_mem(rf, &mem, IRDMA_COMMIT_FPM_BUF_SIZE, + IRDMA_FPM_COMMIT_BUF_ALIGNMENT_M); + if (status) + goto error; + + info.fpm_commit_buf_pa = mem.pa; + info.fpm_commit_buf = mem.va; + + info.bar0 = rf->hw.hw_addr; + /* Not used in SRIOV VF mode */ + info.hmc_fn_id = rf->pf_id; + info.protocol_used = rf->protocol_used; + info.max_vfs = rf->max_rdma_vfs; + info.hw = &rf->hw; + status = irdma_sc_dev_init(&rf->sc_dev, &info); + if (status) + goto error; + + if (!rf->sc_dev.privileged && dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) + status = irdma_vchnl_req_get_vlan_parsing_cfg( + &rf->sc_dev, &rf->vlan_parse_en); + else + rf->vlan_parse_en = 1; + if (status) + goto error; + return status; +error: + kfree(rf->hmc_info_mem); + rf->hmc_info_mem = NULL; + + return status; +} + +/** + * irdma_rt_deinit_hw - clean up the irdma device resources + * @iwdev: irdma device + * + * remove the mac ip entry and ipv4/ipv6 addresses, destroy the + * device queues and free the pble and the hmc objects + */ +void irdma_rt_deinit_hw(struct irdma_device *iwdev) +{ + struct irdma_sc_qp qp = {}; + ibdev_dbg(&iwdev->ibdev, "INIT: state = %d\n", iwdev->init_state); + + switch (iwdev->init_state) { + case IP_ADDR_REGISTERED: + if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + irdma_del_local_mac_entry(iwdev->rf, + (u8)iwdev->mac_ip_table_idx); + fallthrough; + case AEQ_CREATED: + case PBLE_CHUNK_MEM: + case CEQS_CREATED: + case REM_ENDPOINT_TRK_CREATED: + if (iwdev->rf->en_rem_endpoint_trk) { + qp.dev = &iwdev->rf->sc_dev; + qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID; + qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP; + irdma_cqp_qp_destroy_cmd(qp.dev, &qp); + } + fallthrough; + case IEQ_CREATED: + if (!iwdev->roce_mode) + irdma_puda_dele_rsrc(&iwdev->vsi, IRDMA_PUDA_RSRC_TYPE_IEQ, + iwdev->rf->reset); + fallthrough; + case ILQ_CREATED: + if (!iwdev->roce_mode) + irdma_puda_dele_rsrc(&iwdev->vsi, + IRDMA_PUDA_RSRC_TYPE_ILQ, + iwdev->rf->reset); + break; + default: + ibdev_warn(&iwdev->ibdev, "bad init_state = %d\n", iwdev->init_state); + break; + } + + irdma_cleanup_cm_core(&iwdev->cm_core); + if (iwdev->vsi.pestat) { + irdma_vsi_stats_free(&iwdev->vsi); + kfree(iwdev->vsi.pestat); + } + if (iwdev->cleanup_wq) + destroy_workqueue(iwdev->cleanup_wq); +} + +static int irdma_setup_init_state(struct irdma_pci_f *rf) +{ + int status; + + status = irdma_save_msix_info(rf); + if (status) + return status; + + rf->obj_mem.size = ALIGN(8192, IRDMA_HW_PAGE_SIZE); + rf->obj_mem.va = dma_alloc_coherent(rf->hw.device, rf->obj_mem.size, + &rf->obj_mem.pa, GFP_KERNEL); + if (!rf->obj_mem.va) { + status = -ENOMEM; + goto clean_msixtbl; + } + + rf->obj_next = rf->obj_mem; + status = irdma_initialize_dev(rf); + if (status) + goto clean_obj_mem; + + return 0; + +clean_obj_mem: + dma_free_coherent(rf->hw.device, rf->obj_mem.size, rf->obj_mem.va, + rf->obj_mem.pa); + rf->obj_mem.va = NULL; +clean_msixtbl: + kfree(rf->iw_msixtbl); + rf->iw_msixtbl = NULL; + return status; +} + +/** + * irdma_get_used_rsrc - determine resources used internally + * @iwdev: irdma device + * + * Called at the end of open to get all internal allocations + */ +static void irdma_get_used_rsrc(struct irdma_device *iwdev) +{ + iwdev->rf->used_pds = find_first_zero_bit(iwdev->rf->allocated_pds, + iwdev->rf->max_pd); + iwdev->rf->used_qps = find_first_zero_bit(iwdev->rf->allocated_qps, + iwdev->rf->max_qp); + iwdev->rf->used_cqs = find_first_zero_bit(iwdev->rf->allocated_cqs, + iwdev->rf->max_cq); + iwdev->rf->used_srqs = find_first_zero_bit(iwdev->rf->allocated_srqs, + iwdev->rf->max_srq); + iwdev->rf->used_mrs = find_first_zero_bit(iwdev->rf->allocated_mrs, + iwdev->rf->max_mr); +} + +void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf) +{ + enum init_completion_state state = rf->init_state; + + rf->init_state = INVALID_STATE; + if (rf->rsrc_created) { + irdma_destroy_aeq(rf); + irdma_destroy_pble_prm(rf->pble_rsrc); + irdma_del_ceqs(rf); + rf->rsrc_created = false; + } + + switch (state) { + case CEQ0_CREATED: + irdma_del_ceq_0(rf); + fallthrough; + case CCQ_CREATED: + irdma_destroy_ccq(rf); + fallthrough; + case HW_RSRC_INITIALIZED: + case HMC_OBJS_CREATED: + irdma_del_hmc_objects(&rf->sc_dev, rf->sc_dev.hmc_info, true, + rf->reset, rf->rdma_ver); + fallthrough; + case CQP_CREATED: + irdma_destroy_cqp(rf, !rf->reset); + fallthrough; + case INITIAL_STATE: + irdma_del_init_mem(rf); + break; + case INVALID_STATE: + default: + ibdev_warn(&rf->iwdev->ibdev, "bad init_state = %d\n", rf->init_state); + break; + } +} + +/** + * irdma_rt_init_hw - Initializes runtime portion of HW + * @iwdev: irdma device + * @l2params: qos, tc, mtu info from netdev driver + * + * Create device queues ILQ, IEQ, CEQs and PBLEs. Setup irdma + * device resource objects. + */ +int irdma_rt_init_hw(struct irdma_device *iwdev, + struct irdma_l2params *l2params) +{ + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_sc_qp qp = {}; + struct irdma_vsi_init_info vsi_info = {}; + struct irdma_vsi_stats_info stats_info = {}; + int status; + + vsi_info.vm_vf_type = rf->ftype ? IRDMA_VF_TYPE : IRDMA_PF_TYPE; + vsi_info.dev = dev; + vsi_info.back_vsi = iwdev; + vsi_info.params = l2params; + vsi_info.pf_data_vsi_num = iwdev->vsi_num; + + vsi_info.register_qset = rf->gen_ops.register_qset; + vsi_info.unregister_qset = rf->gen_ops.unregister_qset; + vsi_info.lag_aa = iwdev->lag_mode == IRDMA_LAG_ACTIVE_ACTIVE; + vsi_info.exception_lan_q = 2; + irdma_sc_vsi_init(&iwdev->vsi, &vsi_info); + + status = irdma_setup_cm_core(iwdev, rf->rdma_ver); + if (status) + return status; + + stats_info.pestat = kzalloc(sizeof(*stats_info.pestat), GFP_KERNEL); + if (!stats_info.pestat) { + irdma_cleanup_cm_core(&iwdev->cm_core); + return -ENOMEM; + } + stats_info.fcn_id = dev->hmc_fn_id; + status = irdma_vsi_stats_init(&iwdev->vsi, &stats_info); + if (status) { + irdma_cleanup_cm_core(&iwdev->cm_core); + kfree(stats_info.pestat); + return status; + } + + do { + if (!iwdev->roce_mode) { + status = irdma_initialize_ilq(iwdev); + if (status) + break; + iwdev->init_state = ILQ_CREATED; + status = irdma_initialize_ieq(iwdev); + if (status) + break; + iwdev->init_state = IEQ_CREATED; + } + if (iwdev->rf->en_rem_endpoint_trk) { + qp.dev = dev; + qp.qp_uk.qp_id = IRDMA_REM_ENDPOINT_TRK_QPID; + qp.qp_uk.qp_type = IRDMA_QP_TYPE_IWARP; + status = irdma_cqp_qp_create_cmd(dev, &qp); + if (status) + break; + iwdev->init_state = REM_ENDPOINT_TRK_CREATED; + } + if (!rf->rsrc_created) { + status = irdma_setup_ceqs(rf, &iwdev->vsi); + if (status) + break; + + iwdev->init_state = CEQS_CREATED; + + status = irdma_hmc_init_pble(&rf->sc_dev, + rf->pble_rsrc); + if (status) { + irdma_del_ceqs(rf); + break; + } + + iwdev->init_state = PBLE_CHUNK_MEM; + + status = irdma_setup_aeq(rf); + if (status) { + irdma_destroy_pble_prm(rf->pble_rsrc); + irdma_del_ceqs(rf); + break; + } + iwdev->init_state = AEQ_CREATED; + rf->rsrc_created = true; + } + + if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + irdma_alloc_set_mac(iwdev); + irdma_add_ip(iwdev); + iwdev->init_state = IP_ADDR_REGISTERED; + + /* handles asynch cleanup tasks - disconnect CM , free qp, + * free cq bufs + */ + iwdev->cleanup_wq = alloc_workqueue("irdma-cleanup-wq", + WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE); + if (!iwdev->cleanup_wq) + return -ENOMEM; + irdma_get_used_rsrc(iwdev); + init_waitqueue_head(&iwdev->suspend_wq); + + return 0; + } while (0); + + dev_err(&rf->pcidev->dev, "HW runtime init FAIL status = %d last cmpl = %d\n", + status, iwdev->init_state); + irdma_rt_deinit_hw(iwdev); + + return status; +} + +/** + * irdma_ctrl_init_hw - Initializes control portion of HW + * @rf: RDMA PCI function + * + * Create admin queues, HMC obejcts and RF resource objects + */ +int irdma_ctrl_init_hw(struct irdma_pci_f *rf) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + int status; + + do { + status = irdma_setup_init_state(rf); + if (status) + break; + rf->init_state = INITIAL_STATE; + + status = irdma_create_cqp(rf); + if (status) + break; + rf->init_state = CQP_CREATED; + + dev->feature_info[IRDMA_FEATURE_FW_INFO] = IRDMA_FW_VER_DEFAULT; + if (rf->rdma_ver != IRDMA_GEN_1) { + status = irdma_get_rdma_features(dev); + if (status) + break; + } + + status = irdma_hmc_setup(rf); + if (status) + break; + rf->init_state = HMC_OBJS_CREATED; + + status = irdma_initialize_hw_rsrc(rf); + if (status) + break; + rf->init_state = HW_RSRC_INITIALIZED; + + status = irdma_create_ccq(rf); + if (status) + break; + rf->init_state = CCQ_CREATED; + + status = irdma_setup_ceq_0(rf); + if (status) + break; + rf->init_state = CEQ0_CREATED; + /* Handles processing of CQP completions */ + rf->cqp_cmpl_wq = alloc_ordered_workqueue("cqp_cmpl_wq", + WQ_HIGHPRI | WQ_UNBOUND); + if (!rf->cqp_cmpl_wq) { + status = -ENOMEM; + break; + } + INIT_WORK(&rf->cqp_cmpl_work, cqp_compl_worker); + irdma_sc_ccq_arm(dev->ccq); + return 0; + } while (0); + + pr_err("IRDMA hardware initialization FAILED init_state=%d status=%d\n", + rf->init_state, status); + irdma_ctrl_deinit_hw(rf); + return status; +} + +/** + * irdma_set_hw_rsrc - set hw memory resources. + * @rf: RDMA PCI function + */ +static void irdma_set_hw_rsrc(struct irdma_pci_f *rf) +{ + rf->allocated_qps = (void *)(rf->mem_rsrc + + (sizeof(struct irdma_arp_entry) * rf->arp_table_size)); + rf->allocated_cqs = &rf->allocated_qps[BITS_TO_LONGS(rf->max_qp)]; + rf->allocated_srqs = &rf->allocated_cqs[BITS_TO_LONGS(rf->max_cq)]; + rf->allocated_mrs = &rf->allocated_srqs[BITS_TO_LONGS(rf->max_srq)]; + rf->allocated_pds = &rf->allocated_mrs[BITS_TO_LONGS(rf->max_mr)]; + rf->allocated_ahs = &rf->allocated_pds[BITS_TO_LONGS(rf->max_pd)]; + rf->allocated_mcgs = &rf->allocated_ahs[BITS_TO_LONGS(rf->max_ah)]; + rf->allocated_arps = &rf->allocated_mcgs[BITS_TO_LONGS(rf->max_mcg)]; + + rf->qp_table = (struct irdma_qp **) + (&rf->allocated_arps[BITS_TO_LONGS(rf->arp_table_size)]); + rf->cq_table = (struct irdma_cq **)(&rf->qp_table[rf->max_qp]); + rf->srq_table = (struct irdma_srq **)(&rf->cq_table[rf->max_cq]); + + spin_lock_init(&rf->rsrc_lock); + spin_lock_init(&rf->arp_lock); + spin_lock_init(&rf->qptable_lock); + spin_lock_init(&rf->cqtable_lock); + spin_lock_init(&rf->srqtable_lock); + spin_lock_init(&rf->qh_list_lock); +} + +/** + * irdma_calc_mem_rsrc_size - calculate memory resources size. + * @rf: RDMA PCI function + */ +static u32 irdma_calc_mem_rsrc_size(struct irdma_pci_f *rf) +{ + u32 rsrc_size; + + rsrc_size = sizeof(struct irdma_arp_entry) * rf->arp_table_size; + rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_qp); + rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mr); + rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_cq); + rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_srq); + rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_pd); + rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->arp_table_size); + rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_ah); + rsrc_size += sizeof(unsigned long) * BITS_TO_LONGS(rf->max_mcg); + rsrc_size += sizeof(struct irdma_qp **) * rf->max_qp; + rsrc_size += sizeof(struct irdma_cq **) * rf->max_cq; + rsrc_size += sizeof(struct irdma_srq **) * rf->max_srq; + + return rsrc_size; +} + +/** + * irdma_initialize_hw_rsrc - initialize hw resource tracking array + * @rf: RDMA PCI function + */ +u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf) +{ + u32 rsrc_size; + u32 mrdrvbits; + u32 ret; + + if (rf->rdma_ver != IRDMA_GEN_1) { + rf->allocated_ws_nodes = + kcalloc(BITS_TO_LONGS(IRDMA_MAX_WS_NODES), + sizeof(unsigned long), GFP_KERNEL); + if (!rf->allocated_ws_nodes) + return -ENOMEM; + + set_bit(0, rf->allocated_ws_nodes); + rf->max_ws_node_id = IRDMA_MAX_WS_NODES; + } + rf->max_cqe = rf->sc_dev.hw_attrs.uk_attrs.max_hw_cq_size; + rf->max_qp = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_QP].cnt; + rf->max_mr = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_MR].cnt; + rf->max_cq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_CQ].cnt; + rf->max_srq = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_SRQ].cnt; + rf->max_pd = rf->sc_dev.hw_attrs.max_hw_pds; + rf->arp_table_size = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_ARP].cnt; + rf->max_ah = rf->sc_dev.hmc_info->hmc_obj[IRDMA_HMC_IW_FSIAV].cnt; + rf->max_mcg = rf->max_qp; + + rsrc_size = irdma_calc_mem_rsrc_size(rf); + rf->mem_rsrc = vzalloc(rsrc_size); + if (!rf->mem_rsrc) { + ret = -ENOMEM; + goto mem_rsrc_vmalloc_fail; + } + + rf->arp_table = (struct irdma_arp_entry *)rf->mem_rsrc; + + irdma_set_hw_rsrc(rf); + + set_bit(0, rf->allocated_mrs); + set_bit(0, rf->allocated_qps); + set_bit(0, rf->allocated_cqs); + set_bit(0, rf->allocated_srqs); + set_bit(0, rf->allocated_pds); + set_bit(0, rf->allocated_arps); + set_bit(0, rf->allocated_ahs); + set_bit(0, rf->allocated_mcgs); + set_bit(2, rf->allocated_qps); /* qp 2 IEQ */ + set_bit(1, rf->allocated_qps); /* qp 1 ILQ */ + set_bit(IRDMA_REM_ENDPOINT_TRK_QPID, rf->allocated_qps); /* qp 3 Remote Endpt trk */ + set_bit(1, rf->allocated_cqs); + set_bit(1, rf->allocated_pds); + set_bit(2, rf->allocated_cqs); + set_bit(2, rf->allocated_pds); + + INIT_LIST_HEAD(&rf->mc_qht_list.list); + /* stag index mask has a minimum of 14 bits */ + mrdrvbits = 24 - max(get_count_order(rf->max_mr), 14); + rf->mr_stagmask = ~(((1 << mrdrvbits) - 1) << (32 - mrdrvbits)); + + return 0; + +mem_rsrc_vmalloc_fail: + kfree(rf->allocated_ws_nodes); + rf->allocated_ws_nodes = NULL; + + return ret; +} + +/** + * irdma_cqp_ce_handler - handle cqp completions + * @rf: RDMA PCI function + * @cq: cq for cqp completions + */ +void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) +{ + struct irdma_cqp_request *cqp_request; + struct irdma_sc_dev *dev = &rf->sc_dev; + u32 cqe_count = 0; + struct irdma_ccq_cqe_info info; + unsigned long flags; + int ret; + + do { + memset(&info, 0, sizeof(info)); + spin_lock_irqsave(&rf->cqp.compl_lock, flags); + ret = irdma_sc_ccq_get_cqe_info(cq, &info); + spin_unlock_irqrestore(&rf->cqp.compl_lock, flags); + if (ret) + break; + + cqp_request = (struct irdma_cqp_request *) + (uintptr_t)info.scratch; + if (info.error && irdma_cqp_crit_err(dev, + cqp_request->info.cqp_cmd, + info.maj_err_code, + info.min_err_code)) + ibdev_err(&rf->iwdev->ibdev, + "cqp opcode = 0x%x maj_err_code = 0x%x min_err_code = 0x%x\n", + info.op_code, info.maj_err_code, + info.min_err_code); + if (cqp_request) { + cqp_request->compl_info.maj_err_code = + info.maj_err_code; + cqp_request->compl_info.min_err_code = + info.min_err_code; + cqp_request->compl_info.op_ret_val = info.op_ret_val; + cqp_request->compl_info.error = info.error; + + /* + * If this is deferred or pending completion, then mark + * CQP request as pending to not block the CQ, but don't + * release CQP request, as it is still on the OOO list. + */ + if (info.pending) + cqp_request->pending = true; + else + irdma_complete_cqp_request(&rf->cqp, + cqp_request); + } + + cqe_count++; + } while (1); + + if (cqe_count) { + irdma_process_bh(dev); + irdma_sc_ccq_arm(dev->ccq); + } +} + +/** + * cqp_compl_worker - Handle cqp completions + * @work: Pointer to work structure + */ +void cqp_compl_worker(struct work_struct *work) +{ + struct irdma_pci_f *rf = container_of(work, struct irdma_pci_f, + cqp_cmpl_work); + struct irdma_sc_cq *cq = &rf->ccq.sc_cq; + + irdma_cqp_ce_handler(rf, cq); +} + +/** + * irdma_lookup_apbvt_entry - lookup hash table for an existing apbvt entry corresponding to port + * @cm_core: cm's core + * @port: port to identify apbvt entry + */ +static struct irdma_apbvt_entry *irdma_lookup_apbvt_entry(struct irdma_cm_core *cm_core, + u16 port) +{ + struct irdma_apbvt_entry *entry; + + hash_for_each_possible(cm_core->apbvt_hash_tbl, entry, hlist, port) { + if (entry->port == port) { + entry->use_cnt++; + return entry; + } + } + + return NULL; +} + +/** + * irdma_next_iw_state - modify qp state + * @iwqp: iwarp qp to modify + * @state: next state for qp + * @del_hash: del hash + * @term: term message + * @termlen: length of term message + */ +void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, + u8 termlen) +{ + struct irdma_modify_qp_info info = {}; + + info.next_iwarp_state = state; + info.remove_hash_idx = del_hash; + info.cq_num_valid = true; + info.arp_cache_idx_valid = true; + info.dont_send_term = true; + info.dont_send_fin = true; + info.termlen = termlen; + + if (term & IRDMAQP_TERM_SEND_TERM_ONLY) + info.dont_send_term = false; + if (term & IRDMAQP_TERM_SEND_FIN_ONLY) + info.dont_send_fin = false; + if (iwqp->sc_qp.term_flags && state == IRDMA_QP_STATE_ERROR) + info.reset_tcp_conn = true; + iwqp->hw_iwarp_state = state; + irdma_hw_modify_qp(iwqp->iwdev, iwqp, &info, 0); + iwqp->iwarp_state = info.next_iwarp_state; +} + +/** + * irdma_del_local_mac_entry - remove a mac entry from the hw + * table + * @rf: RDMA PCI function + * @idx: the index of the mac ip address to delete + */ +void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx) +{ + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); + if (!cqp_request) + return; + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = IRDMA_OP_DELETE_LOCAL_MAC_ENTRY; + cqp_info->post_sq = 1; + cqp_info->in.u.del_local_mac_entry.cqp = &iwcqp->sc_cqp; + cqp_info->in.u.del_local_mac_entry.scratch = (uintptr_t)cqp_request; + cqp_info->in.u.del_local_mac_entry.entry_idx = idx; + cqp_info->in.u.del_local_mac_entry.ignore_ref_count = 0; + + irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(iwcqp, cqp_request); +} + +/** + * irdma_add_local_mac_entry - add a mac ip address entry to the + * hw table + * @rf: RDMA PCI function + * @mac_addr: pointer to mac address + * @idx: the index of the mac ip address to add + */ +int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx) +{ + struct irdma_local_mac_entry_info *info; + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + cqp_info->post_sq = 1; + info = &cqp_info->in.u.add_local_mac_entry.info; + ether_addr_copy(info->mac_addr, mac_addr); + info->entry_idx = idx; + cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; + cqp_info->cqp_cmd = IRDMA_OP_ADD_LOCAL_MAC_ENTRY; + cqp_info->in.u.add_local_mac_entry.cqp = &iwcqp->sc_cqp; + cqp_info->in.u.add_local_mac_entry.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(iwcqp, cqp_request); + + return status; +} + +/** + * irdma_alloc_local_mac_entry - allocate a mac entry + * @rf: RDMA PCI function + * @mac_tbl_idx: the index of the new mac address + * + * Allocate a mac address entry and update the mac_tbl_idx + * to hold the index of the newly created mac address + * Return 0 if successful, otherwise return error + */ +int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx) +{ + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status = 0; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY; + cqp_info->post_sq = 1; + cqp_info->in.u.alloc_local_mac_entry.cqp = &iwcqp->sc_cqp; + cqp_info->in.u.alloc_local_mac_entry.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(rf, cqp_request); + if (!status) + *mac_tbl_idx = (u16)cqp_request->compl_info.op_ret_val; + + irdma_put_cqp_request(iwcqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_manage_apbvt_cmd - send cqp command manage apbvt + * @iwdev: irdma device + * @accel_local_port: port for apbvt + * @add_port: add ordelete port + */ +static int irdma_cqp_manage_apbvt_cmd(struct irdma_device *iwdev, + u16 accel_local_port, bool add_port) +{ + struct irdma_apbvt_info *info; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, add_port); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + info = &cqp_info->in.u.manage_apbvt_entry.info; + memset(info, 0, sizeof(*info)); + info->add = add_port; + info->port = accel_local_port; + cqp_info->cqp_cmd = IRDMA_OP_MANAGE_APBVT_ENTRY; + cqp_info->post_sq = 1; + cqp_info->in.u.manage_apbvt_entry.cqp = &iwdev->rf->cqp.sc_cqp; + cqp_info->in.u.manage_apbvt_entry.scratch = (uintptr_t)cqp_request; + ibdev_dbg(&iwdev->ibdev, "DEV: %s: port=0x%04x\n", + (!add_port) ? "DELETE" : "ADD", accel_local_port); + + status = irdma_handle_cqp_op(iwdev->rf, cqp_request); + irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_add_apbvt - add tcp port to HW apbvt table + * @iwdev: irdma device + * @port: port for apbvt + */ +struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port) +{ + struct irdma_cm_core *cm_core = &iwdev->cm_core; + struct irdma_apbvt_entry *entry; + unsigned long flags; + + spin_lock_irqsave(&cm_core->apbvt_lock, flags); + entry = irdma_lookup_apbvt_entry(cm_core, port); + if (entry) { + spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); + return entry; + } + + entry = kzalloc(sizeof(*entry), GFP_ATOMIC); + if (!entry) { + spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); + return NULL; + } + + entry->port = port; + entry->use_cnt = 1; + hash_add(cm_core->apbvt_hash_tbl, &entry->hlist, entry->port); + spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); + + if (irdma_cqp_manage_apbvt_cmd(iwdev, port, true)) { + kfree(entry); + return NULL; + } + + return entry; +} + +/** + * irdma_del_apbvt - delete tcp port from HW apbvt table + * @iwdev: irdma device + * @entry: apbvt entry object + */ +void irdma_del_apbvt(struct irdma_device *iwdev, + struct irdma_apbvt_entry *entry) +{ + struct irdma_cm_core *cm_core = &iwdev->cm_core; + unsigned long flags; + + spin_lock_irqsave(&cm_core->apbvt_lock, flags); + if (--entry->use_cnt) { + spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); + return; + } + + hash_del(&entry->hlist); + /* apbvt_lock is held across CQP delete APBVT OP (non-waiting) to + * protect against race where add APBVT CQP can race ahead of the delete + * APBVT for same port. + */ + irdma_cqp_manage_apbvt_cmd(iwdev, entry->port, false); + kfree(entry); + spin_unlock_irqrestore(&cm_core->apbvt_lock, flags); +} + +void irdma_arp_cqp_op(struct irdma_pci_f *rf, u16 arp_index, + const unsigned char *mac_addr, u32 action) +{ + struct irdma_add_arp_cache_entry_info *info; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); + if (!cqp_request) + return; + + cqp_info = &cqp_request->info; + if (action == IRDMA_ARP_ADD_UPDATE) { + cqp_info->cqp_cmd = IRDMA_OP_ADD_ARP_CACHE_ENTRY; + info = &cqp_info->in.u.add_arp_cache_entry.info; + memset(info, 0, sizeof(*info)); + info->arp_index = (u16)arp_index; + info->permanent = true; + ether_addr_copy(info->mac_addr, mac_addr); + cqp_info->in.u.add_arp_cache_entry.scratch = + (uintptr_t)cqp_request; + cqp_info->in.u.add_arp_cache_entry.cqp = &rf->cqp.sc_cqp; + } else { + cqp_info->cqp_cmd = IRDMA_OP_DELETE_ARP_CACHE_ENTRY; + cqp_info->in.u.del_arp_cache_entry.scratch = + (uintptr_t)cqp_request; + cqp_info->in.u.del_arp_cache_entry.cqp = &rf->cqp.sc_cqp; + cqp_info->in.u.del_arp_cache_entry.arp_index = arp_index; + } + + cqp_info->post_sq = 1; + irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); +} + +/** + * irdma_manage_arp_cache - manage hw arp cache + * @rf: RDMA PCI function + * @mac_addr: mac address ptr + * @ip_addr: ip addr for arp cache + * @action: add, delete or modify + */ +void irdma_manage_arp_cache(struct irdma_pci_f *rf, const unsigned char *mac_addr, + u32 *ip_addr, u32 action) +{ + int arp_index; + + arp_index = irdma_arp_table(rf, ip_addr, mac_addr, action); + if (arp_index == -1) + return; + + irdma_arp_cqp_op(rf, (u16)arp_index, mac_addr, action); +} + +/** + * irdma_send_syn_cqp_callback - do syn/ack after qhash + * @cqp_request: qhash cqp completion + */ +static void irdma_send_syn_cqp_callback(struct irdma_cqp_request *cqp_request) +{ + struct irdma_cm_node *cm_node = cqp_request->param; + + irdma_send_syn(cm_node, 1); + irdma_rem_ref_cm_node(cm_node); +} + +/** + * irdma_manage_qhash - add or modify qhash + * @iwdev: irdma device + * @cminfo: cm info for qhash + * @etype: type (syn or quad) + * @mtype: type of qhash + * @cmnode: cmnode associated with connection + * @wait: wait for completion + */ +int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, + enum irdma_quad_entry_type etype, + enum irdma_quad_hash_manage_type mtype, void *cmnode, + bool wait) +{ + struct irdma_qhash_table_info *info; + struct irdma_cqp *iwcqp = &iwdev->rf->cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_cm_node *cm_node = cmnode; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + info = &cqp_info->in.u.manage_qhash_table_entry.info; + memset(info, 0, sizeof(*info)); + info->vsi = &iwdev->vsi; + info->manage = mtype; + info->entry_type = etype; + if (cminfo->vlan_id < VLAN_N_VID) { + info->vlan_valid = true; + info->vlan_id = cminfo->vlan_id; + } else { + info->vlan_valid = false; + } + info->ipv4_valid = cminfo->ipv4; + info->user_pri = cminfo->user_pri; + ether_addr_copy(info->mac_addr, iwdev->netdev->dev_addr); + info->qp_num = cminfo->qh_qpid; + info->dest_port = cminfo->loc_port; + info->dest_ip[0] = cminfo->loc_addr[0]; + info->dest_ip[1] = cminfo->loc_addr[1]; + info->dest_ip[2] = cminfo->loc_addr[2]; + info->dest_ip[3] = cminfo->loc_addr[3]; + if (etype == IRDMA_QHASH_TYPE_TCP_ESTABLISHED || + etype == IRDMA_QHASH_TYPE_UDP_UNICAST || + etype == IRDMA_QHASH_TYPE_UDP_MCAST || + etype == IRDMA_QHASH_TYPE_ROCE_MCAST || + etype == IRDMA_QHASH_TYPE_ROCEV2_HW) { + info->src_port = cminfo->rem_port; + info->src_ip[0] = cminfo->rem_addr[0]; + info->src_ip[1] = cminfo->rem_addr[1]; + info->src_ip[2] = cminfo->rem_addr[2]; + info->src_ip[3] = cminfo->rem_addr[3]; + } + if (cmnode) { + cqp_request->callback_fcn = irdma_send_syn_cqp_callback; + cqp_request->param = cmnode; + if (!wait) + refcount_inc(&cm_node->refcnt); + } + if (info->ipv4_valid) + ibdev_dbg(&iwdev->ibdev, + "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI4 rem_addr=%pI4 mac=%pM, vlan_id=%d cm_node=%p\n", + (!mtype) ? "DELETE" : "ADD", + __builtin_return_address(0), info->src_port, + info->dest_port, info->src_ip, info->dest_ip, + info->mac_addr, cminfo->vlan_id, + cmnode ? cmnode : NULL); + else + ibdev_dbg(&iwdev->ibdev, + "CM: %s caller: %pS loc_port=0x%04x rem_port=0x%04x loc_addr=%pI6 rem_addr=%pI6 mac=%pM, vlan_id=%d cm_node=%p\n", + (!mtype) ? "DELETE" : "ADD", + __builtin_return_address(0), info->src_port, + info->dest_port, info->src_ip, info->dest_ip, + info->mac_addr, cminfo->vlan_id, + cmnode ? cmnode : NULL); + + cqp_info->in.u.manage_qhash_table_entry.cqp = &iwdev->rf->cqp.sc_cqp; + cqp_info->in.u.manage_qhash_table_entry.scratch = (uintptr_t)cqp_request; + cqp_info->cqp_cmd = IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY; + cqp_info->post_sq = 1; + status = irdma_handle_cqp_op(iwdev->rf, cqp_request); + if (status && cm_node && !wait) + irdma_rem_ref_cm_node(cm_node); + + irdma_put_cqp_request(iwcqp, cqp_request); + + return status; +} + +/** + * irdma_hw_flush_wqes - flush qp's wqe + * @rf: RDMA PCI function + * @qp: hardware control qp + * @info: info for flush + * @wait: flag wait for completion + */ +int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, + struct irdma_qp_flush_info *info, bool wait) +{ + int status; + struct irdma_qp_flush_info *hw_info; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_qp *iwqp = qp->qp_uk.back_qp; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + hw_info = &cqp_request->info.in.u.qp_flush_wqes.info; + memcpy(hw_info, info, sizeof(*hw_info)); + cqp_info->cqp_cmd = IRDMA_OP_QP_FLUSH_WQES; + cqp_info->post_sq = 1; + cqp_info->in.u.qp_flush_wqes.qp = qp; + cqp_info->in.u.qp_flush_wqes.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(rf, cqp_request); + if (status) { + qp->qp_uk.sq_flush_complete = true; + qp->qp_uk.rq_flush_complete = true; + irdma_put_cqp_request(&rf->cqp, cqp_request); + return status; + } + + if (!wait || cqp_request->compl_info.maj_err_code) + goto put_cqp; + + if (info->rq) { + if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_SQ_WQE_FLUSHED || + cqp_request->compl_info.min_err_code == 0) { + /* RQ WQE flush was requested but did not happen */ + qp->qp_uk.rq_flush_complete = true; + } + } + if (info->sq) { + if (cqp_request->compl_info.min_err_code == IRDMA_CQP_COMPL_RQ_WQE_FLUSHED || + cqp_request->compl_info.min_err_code == 0) { + /* SQ WQE flush was requested but did not happen */ + qp->qp_uk.sq_flush_complete = true; + } + } + + ibdev_dbg(&rf->iwdev->ibdev, + "VERBS: qp_id=%d qp_type=%d qpstate=%d ibqpstate=%d last_aeq=%d hw_iw_state=%d maj_err_code=%d min_err_code=%d\n", + iwqp->ibqp.qp_num, rf->protocol_used, iwqp->iwarp_state, + iwqp->ibqp_state, iwqp->last_aeq, iwqp->hw_iwarp_state, + cqp_request->compl_info.maj_err_code, cqp_request->compl_info.min_err_code); +put_cqp: + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_gen_ae - generate AE + * @rf: RDMA PCI function + * @qp: qp associated with AE + * @info: info for ae + * @wait: wait for completion + */ +void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, + struct irdma_gen_ae_info *info, bool wait) +{ + struct irdma_gen_ae_info *ae_info; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); + if (!cqp_request) + return; + + cqp_info = &cqp_request->info; + ae_info = &cqp_request->info.in.u.gen_ae.info; + memcpy(ae_info, info, sizeof(*ae_info)); + cqp_info->cqp_cmd = IRDMA_OP_GEN_AE; + cqp_info->post_sq = 1; + cqp_info->in.u.gen_ae.qp = qp; + cqp_info->in.u.gen_ae.scratch = (uintptr_t)cqp_request; + + irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); +} + +/** + * irdma_manage_pble_bp - manage pbles + * @dev: hardware control device structure + * @info: info for managing pble + */ +int irdma_manage_pble_bp(struct irdma_sc_dev *dev, + struct irdma_manage_pble_info *info) +{ + struct irdma_manage_pble_info *hw_info; + struct irdma_pci_f *rf = dev_to_rf(dev); + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + bool wait = rf->init_state < CCQ_CREATED ? false : true; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + hw_info = &cqp_request->info.in.u.manage_pble_bp.info; + memcpy(hw_info, info, sizeof(*hw_info)); + + cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PBLE_BP; + cqp_info->post_sq = 1; + cqp_info->in.u.manage_pble_bp.cqp = &rf->cqp.sc_cqp; + cqp_info->in.u.manage_pble_bp.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) +{ + struct irdma_qp_flush_info info = {}; + struct irdma_pci_f *rf = iwqp->iwdev->rf; + u8 flush_code = iwqp->sc_qp.flush_code; + + if ((!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) || + ((flush_mask & IRDMA_REFLUSH) && rf->rdma_ver >= IRDMA_GEN_3)) + return; + + /* Set flush info fields*/ + info.sq = flush_mask & IRDMA_FLUSH_SQ; + info.rq = flush_mask & IRDMA_FLUSH_RQ; + + /* Generate userflush errors in CQE */ + info.sq_major_code = IRDMA_FLUSH_MAJOR_ERR; + info.sq_minor_code = FLUSH_GENERAL_ERR; + info.rq_major_code = IRDMA_FLUSH_MAJOR_ERR; + info.rq_minor_code = FLUSH_GENERAL_ERR; + info.userflushcode = true; + info.err_sq_idx_valid = iwqp->sc_qp.err_sq_idx_valid; + info.err_sq_idx = iwqp->sc_qp.err_sq_idx; + + if (flush_mask & IRDMA_REFLUSH) { + if (info.sq) + iwqp->sc_qp.flush_sq = false; + if (info.rq) + iwqp->sc_qp.flush_rq = false; + } else { + if (flush_code) { + if (info.sq && iwqp->sc_qp.sq_flush_code) + info.sq_minor_code = flush_code; + if (info.rq && iwqp->sc_qp.rq_flush_code) + info.rq_minor_code = flush_code; + } + if (irdma_upload_context && irdma_upload_qp_context(iwqp, 0, 1)) + ibdev_warn(&iwqp->iwdev->ibdev, "failed to upload QP context\n"); + if (!iwqp->user_mode && rf->rdma_ver <= IRDMA_GEN_2) + irdma_sched_qp_flush_work(iwqp); + } + + /* Issue flush */ + (void)irdma_hw_flush_wqes(rf, &iwqp->sc_qp, &info, + flush_mask & IRDMA_FLUSH_WAIT); + iwqp->flush_issued = true; +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/i40e_client.h b/drivers/intel/irdma-1.14.33/src/irdma/i40e_client.h new file mode 100644 index 000000000..1256abf7a --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/i40e_client.h @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB-only */ +/* Copyright (C) 2013-2024 Intel Corporation */ + +#ifndef _I40E_CLIENT_H_ +#define _I40E_CLIENT_H_ + +#ifdef USE_INTEL_AUX_BUS +#include "linux/auxiliary_bus.h" +#else +#include +#endif /* USE_INTEL_AUX_BUS */ + +#define I40E_PEER_RDMA_NAME "i40e_rdma" +#define I40E_PEER_RDMA_ID PLATFORM_DEVID_AUTO + +#define I40E_CLIENT_STR_LENGTH 10 +/* Client interface version should be updated anytime there is a change in the + * existing APIs or data structures. + * Note that in-tree i40e has major version of 0 and the structures are not + * identical. For example struct i40e_info and i40e_ops are different. + */ +#define I40E_CLIENT_VERSION_MAJOR 1 +#define I40E_CLIENT_VERSION_MINOR 01 +#define I40E_CLIENT_VERSION_BUILD 00 +#define I40E_CLIENT_VERSION_STR \ + __stringify(I40E_CLIENT_VERSION_MAJOR) "." \ + __stringify(I40E_CLIENT_VERSION_MINOR) "." \ + __stringify(I40E_CLIENT_VERSION_BUILD) + +struct i40e_client_version { + u8 major; + u8 minor; + u8 build; + u8 rsvd; +}; + +enum i40e_client_state { + __I40E_CLIENT_NULL, + __I40E_CLIENT_REGISTERED +}; + +enum i40e_client_instance_state { + __I40E_CLIENT_INSTANCE_NONE, + __I40E_CLIENT_INSTANCE_OPENED, +}; + +struct i40e_ops; +struct i40e_client; + +/* HW does not define a type value for AEQ; only for RX/TX and CEQ. + * In order for us to keep the interface simple, SW will define a + * unique type value for AEQ. + */ +#define I40E_QUEUE_TYPE_PE_AEQ 0x80 +#define I40E_QUEUE_INVALID_IDX 0xFFFF + +struct i40e_qv_info { + u32 v_idx; /* msix_vector */ + u16 ceq_idx; + u16 aeq_idx; + u8 itr_idx; +}; + +struct i40e_qvlist_info { + u32 num_vectors; + struct i40e_qv_info qv_info[1]; +}; + +#define I40E_CLIENT_MSIX_ALL 0xFFFFFFFF + +/* set of LAN parameters useful for clients managed by LAN */ + +/* Struct to hold per priority info */ +struct i40e_prio_qos_params { + u16 qs_handle; /* qs handle for prio */ + u8 tc; /* TC mapped to prio */ + u8 reserved; +}; + +#define I40E_CLIENT_MAX_USER_PRIORITY 8 +/* Struct to hold Client QoS */ +struct i40e_qos_params { + struct i40e_prio_qos_params prio_qos[I40E_CLIENT_MAX_USER_PRIORITY]; +}; + +struct i40e_params { + struct i40e_qos_params qos; + u16 mtu; +}; + +/* Structure to hold Lan device info for a client device */ +struct i40e_info { + struct i40e_client_version version; + u8 lanmac[6]; + struct net_device *netdev; + struct pci_dev *pcidev; + struct auxiliary_device *aux_dev; + u8 __iomem *hw_addr; + u8 fid; /* function id, PF id or VF id */ +#define I40E_CLIENT_FTYPE_PF 0 +#define I40E_CLIENT_FTYPE_VF 1 + u8 ftype; /* function type, PF or VF */ + void *pf; + + /* All L2 params that could change during the life span of the PF + * and needs to be communicated to the client when they change + */ + struct i40e_qvlist_info *qvlist_info; + struct i40e_params params; + struct i40e_ops *ops; + + u16 msix_count; /* number of msix vectors*/ + /* Array down below will be dynamically allocated based on msix_count */ + struct msix_entry *msix_entries; + u16 itr_index; /* Which ITR index the PE driver is suppose to use */ + u16 fw_maj_ver; /* firmware major version */ + u16 fw_min_ver; /* firmware minor version */ + u32 fw_build; /* firmware build number */ + struct i40e_client *client; +}; + +struct i40e_auxiliary_device { + struct auxiliary_device aux_dev; + struct i40e_info *ldev; +}; + +#define I40E_CLIENT_RESET_LEVEL_PF 1 +#define I40E_CLIENT_RESET_LEVEL_CORE 2 +#define I40E_CLIENT_VSI_FLAG_TCP_ENABLE BIT(1) + +struct i40e_ops { + /* setup_q_vector_list enables queues with a particular vector */ + int (*setup_qvlist)(struct i40e_info *ldev, struct i40e_client *client, + struct i40e_qvlist_info *qv_info); + + int (*virtchnl_send)(struct i40e_info *ldev, struct i40e_client *client, + u32 vf_id, u8 *msg, u16 len); + + /* If the PE Engine is unresponsive, RDMA driver can request a reset. + * The level helps determine the level of reset being requested. + */ + void (*request_reset)(struct i40e_info *ldev, + struct i40e_client *client, u32 level); + + /* API for the RDMA driver to set certain VSI flags that control + * PE Engine. + */ + int (*update_vsi_ctxt)(struct i40e_info *ldev, + struct i40e_client *client, + bool is_vf, u32 vf_id, + u32 flag, u32 valid_flag); + + int (*client_device_register)(struct i40e_info *ldev); + + void (*client_device_unregister)(struct i40e_info *ldev); +}; + +struct i40e_client_ops { + /* Should be called from register_client() or whenever PF is ready + * to create a specific client instance. + */ + int (*open)(struct i40e_info *ldev, struct i40e_client *client); + + /* Should be called when netdev is unavailable or when unregister + * call comes in. If the close is happenening due to a reset being + * triggered set the reset bit to true. + */ + void (*close)(struct i40e_info *ldev, struct i40e_client *client, + bool reset); + + /* called when some l2 managed parameters changes - mtu */ + void (*l2_param_change)(struct i40e_info *ldev, + struct i40e_client *client, + struct i40e_params *params); + + int (*virtchnl_receive)(struct i40e_info *ldev, + struct i40e_client *client, u32 vf_id, + u8 *msg, u16 len); + + /* called when a VF is reset by the PF */ + void (*vf_reset)(struct i40e_info *ldev, + struct i40e_client *client, u32 vf_id); + + /* called when the number of VFs changes */ + void (*vf_enable)(struct i40e_info *ldev, + struct i40e_client *client, u32 num_vfs); + + /* returns true if VF is capable of specified offload */ + int (*vf_capable)(struct i40e_info *ldev, + struct i40e_client *client, u32 vf_id); +}; + +/* Client device */ +struct i40e_client_instance { + struct list_head list; + struct i40e_info lan_info; + struct i40e_client *client; + unsigned long state; +}; + +struct i40e_client { + struct list_head list; /* list of registered clients */ + char name[I40E_CLIENT_STR_LENGTH]; + struct i40e_client_version version; + unsigned long state; /* client state */ + atomic_t ref_cnt; /* Count of all the client devices of this kind */ + u32 flags; +#define I40E_CLIENT_FLAGS_LAUNCH_ON_PROBE BIT(0) +#define I40E_TX_FLAGS_NOTIFY_OTHER_EVENTS BIT(2) + u8 type; +#define I40E_CLIENT_IWARP 0 + /* client ops provided by the client */ + const struct i40e_client_ops *ops; +}; + +static inline bool i40e_client_is_registered(struct i40e_client *client) +{ + return test_bit(__I40E_CLIENT_REGISTERED, &client->state); +} + +#endif /* _I40E_CLIENT_H_ */ + diff --git a/drivers/intel/irdma-1.14.33/src/irdma/i40iw_hw.c b/drivers/intel/irdma-1.14.33/src/irdma/i40iw_hw.c new file mode 100644 index 000000000..00c3fc15d --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/i40iw_hw.c @@ -0,0 +1,259 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "osdep.h" +#include "type.h" +#include "i40iw_hw.h" +#include "protos.h" + +static u32 i40iw_regs[IRDMA_MAX_REGS] = { + I40E_PFPE_CQPTAIL, + I40E_PFPE_CQPDB, + I40E_PFPE_CCQPSTATUS, + I40E_PFPE_CCQPHIGH, + I40E_PFPE_CCQPLOW, + I40E_PFPE_CQARM, + I40E_PFPE_CQACK, + I40E_PFPE_AEQALLOC, + I40E_PFPE_CQPERRCODES, + I40E_PFPE_WQEALLOC, + I40E_PFINT_DYN_CTLN(0), + I40IW_DB_ADDR_OFFSET, + + I40E_GLPCI_LBARCTRL, + I40E_GLPE_CPUSTATUS0, + I40E_GLPE_CPUSTATUS1, + I40E_GLPE_CPUSTATUS2, + I40E_PFINT_AEQCTL, + I40E_PFINT_CEQCTL(0), + I40E_VSIQF_CTL(0), + I40E_PFHMC_PDINV, + I40E_GLHMC_VFPDINV(0), + I40E_GLPE_CRITERR, + RSVD_OFFSET, /* PFINT_RATEN not used in FPK */ +}; + +static u32 i40iw_stat_offsets[] = { + I40E_GLPES_PFIP4RXDISCARD(0), + I40E_GLPES_PFIP4RXTRUNC(0), + I40E_GLPES_PFIP4TXNOROUTE(0), + I40E_GLPES_PFIP6RXDISCARD(0), + I40E_GLPES_PFIP6RXTRUNC(0), + I40E_GLPES_PFIP6TXNOROUTE(0), + I40E_GLPES_PFTCPRTXSEG(0), + I40E_GLPES_PFTCPRXOPTERR(0), + I40E_GLPES_PFTCPRXPROTOERR(0), + I40E_GLPES_PFRXVLANERR(0), + + I40E_GLPES_PFIP4RXOCTSLO(0), + I40E_GLPES_PFIP4RXPKTSLO(0), + I40E_GLPES_PFIP4RXFRAGSLO(0), + I40E_GLPES_PFIP4RXMCPKTSLO(0), + I40E_GLPES_PFIP4TXOCTSLO(0), + I40E_GLPES_PFIP4TXPKTSLO(0), + I40E_GLPES_PFIP4TXFRAGSLO(0), + I40E_GLPES_PFIP4TXMCPKTSLO(0), + I40E_GLPES_PFIP6RXOCTSLO(0), + I40E_GLPES_PFIP6RXPKTSLO(0), + I40E_GLPES_PFIP6RXFRAGSLO(0), + I40E_GLPES_PFIP6RXMCPKTSLO(0), + I40E_GLPES_PFIP6TXOCTSLO(0), + I40E_GLPES_PFIP6TXPKTSLO(0), + I40E_GLPES_PFIP6TXFRAGSLO(0), + I40E_GLPES_PFIP6TXMCPKTSLO(0), + I40E_GLPES_PFTCPRXSEGSLO(0), + I40E_GLPES_PFTCPTXSEGLO(0), + I40E_GLPES_PFRDMARXRDSLO(0), + I40E_GLPES_PFRDMARXSNDSLO(0), + I40E_GLPES_PFRDMARXWRSLO(0), + I40E_GLPES_PFRDMATXRDSLO(0), + I40E_GLPES_PFRDMATXSNDSLO(0), + I40E_GLPES_PFRDMATXWRSLO(0), + I40E_GLPES_PFRDMAVBNDLO(0), + I40E_GLPES_PFRDMAVINVLO(0), + I40E_GLPES_PFIP4RXMCOCTSLO(0), + I40E_GLPES_PFIP4TXMCOCTSLO(0), + I40E_GLPES_PFIP6RXMCOCTSLO(0), + I40E_GLPES_PFIP6TXMCOCTSLO(0), + I40E_GLPES_PFUDPRXPKTSLO(0), + I40E_GLPES_PFUDPTXPKTSLO(0) +}; + +static u64 i40iw_masks[IRDMA_MAX_MASKS] = { + I40E_PFPE_CCQPSTATUS_CCQP_DONE, + I40E_PFPE_CCQPSTATUS_CCQP_ERR, + I40E_CQPSQ_STAG_PDID, + I40E_CQPSQ_CQ_CEQID, + I40E_CQPSQ_CQ_CQID, + I40E_COMMIT_FPM_CQCNT, + I40E_CQPSQ_UPESD_HMCFNID, +}; + +static u8 i40iw_shifts[IRDMA_MAX_SHIFTS] = { + I40E_PFPE_CCQPSTATUS_CCQP_DONE_S, + I40E_PFPE_CCQPSTATUS_CCQP_ERR_S, + I40E_CQPSQ_STAG_PDID_S, + I40E_CQPSQ_CQ_CEQID_S, + I40E_CQPSQ_CQ_CQID_S, + I40E_COMMIT_FPM_CQCNT_S, + I40E_CQPSQ_UPESD_HMCFNID_S, +}; + +/** + * i40iw_config_ceq- Configure CEQ interrupt + * @dev: pointer to the device structure + * @ceq_id: Completion Event Queue ID + * @idx: vector index + * @enable: Enable CEQ interrupt when true + */ +static void i40iw_config_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx, + bool enable) +{ + u32 reg_val; + + reg_val = FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_INDX, ceq_id) | + FIELD_PREP(I40E_PFINT_LNKLSTN_FIRSTQ_TYPE, QUEUE_TYPE_CEQ); + wr32(dev->hw, I40E_PFINT_LNKLSTN(idx - 1), reg_val); + + reg_val = FIELD_PREP(I40E_PFINT_DYN_CTLN_ITR_INDX, IRDMA_IDX_NOITR) | + FIELD_PREP(I40E_PFINT_DYN_CTLN_INTENA, 0x1); + wr32(dev->hw, I40E_PFINT_DYN_CTLN(idx - 1), reg_val); + + reg_val = FIELD_PREP(IRDMA_GLINT_CEQCTL_CAUSE_ENA, enable) | + FIELD_PREP(IRDMA_GLINT_CEQCTL_MSIX_INDX, idx) | + FIELD_PREP(I40E_PFINT_CEQCTL_NEXTQ_INDX, NULL_QUEUE_INDEX) | + FIELD_PREP(IRDMA_GLINT_CEQCTL_ITR_INDX, IRDMA_IDX_NOITR); + + wr32(dev->hw, i40iw_regs[IRDMA_GLINT_CEQCTL] + 4 * ceq_id, reg_val); +} + +/** + * i40iw_ena_irq - Enable interrupt + * @dev: pointer to the device structure + * @idx: vector index + */ +static void i40iw_ena_irq(struct irdma_sc_dev *dev, u32 idx) +{ + u32 val; + + val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, 0x1) | + FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, 0x1) | + FIELD_PREP(IRDMA_GLINT_DYN_CTL_ITR_INDX, IRDMA_IDX_NOITR); + wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), val); +} + +/** + * i40iw_disable_irq - Disable interrupt + * @dev: pointer to the device structure + * @idx: vector index + */ +static void i40iw_disable_irq(struct irdma_sc_dev *dev, u32 idx) +{ + wr32(dev->hw, i40iw_regs[IRDMA_GLINT_DYN_CTL] + 4 * (idx - 1), 0); +} + +static const struct irdma_irq_ops i40iw_irq_ops = { + .irdma_cfg_aeq = irdma_cfg_aeq, + .irdma_cfg_ceq = i40iw_config_ceq, + .irdma_dis_irq = i40iw_disable_irq, + .irdma_en_irq = i40iw_ena_irq, +}; + +static const struct irdma_hw_stat_map i40iw_hw_stat_map[] = { + [IRDMA_HW_STAT_INDEX_RXVLANERR] = { 0, 0, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_IP4RXOCTS] = { 8, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4RXPKTS] = { 16, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4RXDISCARD] = { 24, 0, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_IP4RXTRUNC] = { 32, 0, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_IP4RXFRAGS] = { 40, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] = { 48, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXOCTS] = { 56, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXPKTS] = { 64, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXDISCARD] = { 72, 0, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_IP6RXTRUNC] = { 80, 0, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_IP6RXFRAGS] = { 88, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] = { 96, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXOCTS] = { 104, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXPKTS] = { 112, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXFRAGS] = { 120, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] = { 128, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXOCTS] = { 136, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXPKTS] = { 144, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXFRAGS] = { 152, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] = { 160, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] = { 168, 0, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] = { 176, 0, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_TCPRXSEGS] = { 184, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_TCPRXOPTERR] = { 192, 0, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] = { 200, 0, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_TCPTXSEG] = { 208, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_TCPRTXSEG] = { 216, 0, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_RDMARXWRS] = { 224, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMARXRDS] = { 232, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMARXSNDS] = { 240, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMATXWRS] = { 248, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMATXRDS] = { 256, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMATXSNDS] = { 264, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMAVBND] = { 272, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMAVINV] = { 280, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS] = { 288, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS] = { 296, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS] = { 304, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS] = { 312, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_UDPRXPKTS] = { 320, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_UDPTXPKTS] = { 328, 0, IRDMA_MAX_STATS_48 }, +}; + +void i40iw_init_hw(struct irdma_sc_dev *dev) +{ + int i; + u8 __iomem *hw_addr; + + for (i = 0; i < IRDMA_MAX_REGS; ++i) { + hw_addr = dev->hw->hw_addr; + + if (i == IRDMA_DB_ADDR_OFFSET) + hw_addr = NULL; + + dev->hw_regs[i] = (u32 __iomem *)(i40iw_regs[i] + hw_addr); + } + + for (i = 0; i < IRDMA_HW_STAT_INDEX_MAX_GEN_1; ++i) + dev->hw_stats_regs[i] = i40iw_stat_offsets[i]; + + dev->hw_attrs.first_hw_vf_fpm_id = I40IW_FIRST_VF_FPM_ID; + dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID; + + for (i = 0; i < IRDMA_MAX_SHIFTS; ++i) + dev->hw_shifts[i] = i40iw_shifts[i]; + + for (i = 0; i < IRDMA_MAX_MASKS; ++i) + dev->hw_masks[i] = i40iw_masks[i]; + + dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC]; + dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM]; + dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC]; + dev->cqp_db = dev->hw_regs[IRDMA_CQPDB]; + dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK]; + dev->irq_ops = &i40iw_irq_ops; + dev->hw_stats_map = i40iw_hw_stat_map; + + /* Setup the hardware limits, hmc may limit further */ + dev->hw_attrs.uk_attrs.max_hw_wq_frags = I40IW_MAX_WQ_FRAGMENT_COUNT; + dev->hw_attrs.uk_attrs.max_hw_read_sges = I40IW_MAX_SGE_RD; + dev->hw_attrs.max_hw_device_pages = I40IW_MAX_PUSH_PAGE_COUNT; + dev->hw_attrs.uk_attrs.max_hw_inline = I40IW_MAX_INLINE_DATA_SIZE; + dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M; + dev->hw_attrs.max_hw_ird = I40IW_MAX_IRD_SIZE; + dev->hw_attrs.max_hw_ord = I40IW_MAX_ORD_SIZE; + dev->hw_attrs.max_hw_wqes = I40IW_MAX_WQ_ENTRIES; + dev->hw_attrs.uk_attrs.max_hw_rq_quanta = I40IW_QP_SW_MAX_RQ_QUANTA; + dev->hw_attrs.uk_attrs.max_hw_wq_quanta = I40IW_QP_SW_MAX_WQ_QUANTA; + dev->hw_attrs.uk_attrs.max_hw_sq_chunk = I40IW_MAX_QUANTA_PER_WR; + dev->hw_attrs.max_hw_pds = I40IW_MAX_PDS; + dev->hw_attrs.max_stat_inst = I40IW_MAX_STATS_COUNT; + dev->hw_attrs.max_stat_idx = IRDMA_HW_STAT_INDEX_MAX_GEN_1; + dev->hw_attrs.max_hw_outbound_msg_size = I40IW_MAX_OUTBOUND_MSG_SIZE; + dev->hw_attrs.max_hw_inbound_msg_size = I40IW_MAX_INBOUND_MSG_SIZE; + dev->hw_attrs.uk_attrs.min_hw_wq_size = I40IW_MIN_WQ_SIZE; + dev->hw_attrs.max_qp_wr = I40IW_MAX_QP_WRS; +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/i40iw_hw.h b/drivers/intel/irdma-1.14.33/src/irdma/i40iw_hw.h new file mode 100644 index 000000000..cd517d914 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/i40iw_hw.h @@ -0,0 +1,163 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef I40IW_HW_H +#define I40IW_HW_H +#define I40E_VFPE_CQPTAIL1 0x0000A000 /* Reset: VFR */ +#define I40E_VFPE_CQPDB1 0x0000BC00 /* Reset: VFR */ +#define I40E_VFPE_CCQPSTATUS1 0x0000B800 /* Reset: VFR */ +#define I40E_VFPE_CCQPHIGH1 0x00009800 /* Reset: VFR */ +#define I40E_VFPE_CCQPLOW1 0x0000AC00 /* Reset: VFR */ +#define I40E_VFPE_CQARM1 0x0000B400 /* Reset: VFR */ +#define I40E_VFPE_CQACK1 0x0000B000 /* Reset: VFR */ +#define I40E_VFPE_AEQALLOC1 0x0000A400 /* Reset: VFR */ +#define I40E_VFPE_CQPERRCODES1 0x00009C00 /* Reset: VFR */ +#define I40E_VFPE_WQEALLOC1 0x0000C000 /* Reset: VFR */ +#define I40E_VFINT_DYN_CTLN(_INTVF) (0x00024800 + ((_INTVF) * 4)) /* _i=0...511 */ /* Reset: VFR */ + +#define I40E_PFPE_CQPTAIL 0x00008080 /* Reset: PFR */ + +#define I40E_PFPE_CQPDB 0x00008000 /* Reset: PFR */ +#define I40E_PFPE_CCQPSTATUS 0x00008100 /* Reset: PFR */ +#define I40E_PFPE_CCQPHIGH 0x00008200 /* Reset: PFR */ +#define I40E_PFPE_CCQPLOW 0x00008180 /* Reset: PFR */ +#define I40E_PFPE_CQARM 0x00131080 /* Reset: PFR */ +#define I40E_PFPE_CQACK 0x00131100 /* Reset: PFR */ +#define I40E_PFPE_AEQALLOC 0x00131180 /* Reset: PFR */ +#define I40E_PFPE_CQPERRCODES 0x00008880 /* Reset: PFR */ +#define I40E_PFPE_WQEALLOC 0x00138C00 /* Reset: PFR */ +#define I40E_GLPCI_LBARCTRL 0x000BE484 /* Reset: POR */ +#define I40E_GLPE_CPUSTATUS0 0x0000D040 /* Reset: PE_CORER */ +#define I40E_GLPE_CPUSTATUS1 0x0000D044 /* Reset: PE_CORER */ +#define I40E_GLPE_CPUSTATUS2 0x0000D048 /* Reset: PE_CORER */ +#define I40E_GLPE_CRITERR 0x000B4000 /* Reset: PE_CORER */ +#define I40E_PFHMC_PDINV 0x000C0300 /* Reset: PFR */ +#define I40E_GLHMC_VFPDINV(_i) (0x000C8300 + ((_i) * 4)) /* _i=0...31 */ /* Reset: CORER */ +#define I40E_PFINT_DYN_CTLN(_INTPF) (0x00034800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ +#define I40E_PFINT_AEQCTL 0x00038700 /* Reset: CORER */ + +#define I40E_GLPES_PFIP4RXDISCARD(_i) (0x00010600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4RXTRUNC(_i) (0x00010700 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4TXNOROUTE(_i) (0x00012E00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6RXDISCARD(_i) (0x00011200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6RXTRUNC(_i) (0x00011300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ + +#define I40E_GLPES_PFRDMAVBNDLO(_i) (0x00014800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4TXMCOCTSLO(_i) (0x00012000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6RXMCOCTSLO(_i) (0x00011600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6TXMCOCTSLO(_i) (0x00012A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFUDPRXPKTSLO(_i) (0x00013800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFUDPTXPKTSLO(_i) (0x00013A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ + +#define I40E_GLPES_PFIP6TXNOROUTE(_i) (0x00012F00 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFTCPRTXSEG(_i) (0x00013600 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFTCPRXOPTERR(_i) (0x00013200 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFTCPRXPROTOERR(_i) (0x00013300 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFRXVLANERR(_i) (0x00010000 + ((_i) * 4)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4RXOCTSLO(_i) (0x00010200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4RXPKTSLO(_i) (0x00010400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4RXFRAGSLO(_i) (0x00010800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4RXMCPKTSLO(_i) (0x00010C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4TXOCTSLO(_i) (0x00011A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4TXPKTSLO(_i) (0x00011C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4TXFRAGSLO(_i) (0x00011E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4TXMCPKTSLO(_i) (0x00012200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6RXOCTSLO(_i) (0x00010E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6RXPKTSLO(_i) (0x00011000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6RXFRAGSLO(_i) (0x00011400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6TXOCTSLO(_i) (0x00012400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6TXPKTSLO(_i) (0x00012600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6TXFRAGSLO(_i) (0x00012800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6TXMCPKTSLO(_i) (0x00012C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFTCPTXSEGLO(_i) (0x00013400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFRDMARXRDSLO(_i) (0x00013E00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFRDMARXSNDSLO(_i) (0x00014000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFRDMARXWRSLO(_i) (0x00013C00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFRDMATXRDSLO(_i) (0x00014400 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFRDMATXSNDSLO(_i) (0x00014600 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFRDMATXWRSLO(_i) (0x00014200 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP4RXMCOCTSLO(_i) (0x00010A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFIP6RXMCPKTSLO(_i) (0x00011800 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFTCPRXSEGSLO(_i) (0x00013000 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ +#define I40E_GLPES_PFRDMAVINVLO(_i) (0x00014A00 + ((_i) * 8)) /* _i=0...15 */ /* Reset: PE_CORER */ + +#define I40IW_DB_ADDR_OFFSET (4 * 1024 * 1024 - 64 * 1024) + +#define I40IW_VF_DB_ADDR_OFFSET (64 * 1024) + +#define I40E_PFINT_LNKLSTN(_INTPF) (0x00035000 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: PFR */ +#define I40E_PFINT_LNKLSTN_MAX_INDEX 511 + +/* shifts/masks for FLD_[LS/RS]_64 macros used in device table */ +#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX_S 0 +#define I40E_PFINT_LNKLSTN_FIRSTQ_INDX GENMASK(10, 0) +#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_S 11 +#define I40E_PFINT_LNKLSTN_FIRSTQ_TYPE GENMASK(12, 11) +#define I40E_PFINT_CEQCTL(_INTPF) (0x00036800 + ((_INTPF) * 4)) /* _i=0...511 */ /* Reset: CORER */ +#define I40E_PFINT_CEQCTL_MAX_INDEX 511 +#define I40E_PFINT_CEQCTL_MSIX_INDX_S 0 +#define I40E_PFINT_CEQCTL_MSIX_INDX GENMASK(7, 0) +#define I40E_PFINT_CEQCTL_ITR_INDX_S 11 +#define I40E_PFINT_CEQCTL_ITR_INDX GENMASK(12, 11) +#define I40E_PFINT_CEQCTL_MSIX0_INDX_S 13 +#define I40E_PFINT_CEQCTL_MSIX0_INDX GENMASK(15, 13) +#define I40E_PFINT_CEQCTL_NEXTQ_INDX_S 16 +#define I40E_PFINT_CEQCTL_NEXTQ_INDX GENMASK(26, 16) +#define I40E_PFINT_CEQCTL_NEXTQ_TYPE_S 27 +#define I40E_PFINT_CEQCTL_NEXTQ_TYPE GENMASK(28, 27) +#define I40E_PFINT_CEQCTL_CAUSE_ENA_S 30 +#define I40E_PFINT_CEQCTL_CAUSE_ENA BIT(30) +#define I40E_PFINT_CEQCTL_INTEVENT_S 31 +#define I40E_PFINT_CEQCTL_INTEVENT BIT(31) +#define I40E_CQPSQ_STAG_PDID_S 48 +#define I40E_CQPSQ_STAG_PDID GENMASK_ULL(62, 48) +#define I40E_PFPE_CCQPSTATUS_CCQP_DONE_S 0 +#define I40E_PFPE_CCQPSTATUS_CCQP_DONE BIT_ULL(0) +#define I40E_PFPE_CCQPSTATUS_CCQP_ERR_S 31 +#define I40E_PFPE_CCQPSTATUS_CCQP_ERR BIT_ULL(31) +#define I40E_PFINT_DYN_CTLN_ITR_INDX_S 3 +#define I40E_PFINT_DYN_CTLN_ITR_INDX GENMASK(4, 3) +#define I40E_PFINT_DYN_CTLN_INTENA_S 0 +#define I40E_PFINT_DYN_CTLN_INTENA BIT(0) +#define I40E_CQPSQ_CQ_CEQID_S 24 +#define I40E_CQPSQ_CQ_CEQID GENMASK(30, 24) +#define I40E_CQPSQ_CQ_CQID_S 0 +#define I40E_CQPSQ_CQ_CQID GENMASK_ULL(15, 0) +#define I40E_COMMIT_FPM_CQCNT_S 0 +#define I40E_COMMIT_FPM_CQCNT GENMASK_ULL(17, 0) +#define I40E_CQPSQ_UPESD_HMCFNID_S 0 +#define I40E_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0) + +#define I40E_VSIQF_CTL(_VSI) (0x0020D800 + ((_VSI) * 4)) + +enum i40iw_device_caps_const { + I40IW_MAX_WQ_FRAGMENT_COUNT = 3, + I40IW_MAX_SGE_RD = 1, + I40IW_MAX_PUSH_PAGE_COUNT = 0, + I40IW_MAX_INLINE_DATA_SIZE = 48, + I40IW_MAX_IRD_SIZE = 64, + I40IW_MAX_ORD_SIZE = 64, + I40IW_MAX_WQ_ENTRIES = 2048, + I40IW_MAX_WQE_SIZE_RQ = 128, + I40IW_MAX_PDS = 32768, + I40IW_MAX_STATS_COUNT = 16, + I40IW_MAX_CQ_SIZE = 1048575, + I40IW_MAX_OUTBOUND_MSG_SIZE = 2147483647, + I40IW_MAX_INBOUND_MSG_SIZE = 2147483647, + I40IW_MIN_WQ_SIZE = 4 /* WQEs */, +}; + +#define I40IW_QP_WQE_MIN_SIZE 32 +#define I40IW_QP_WQE_MAX_SIZE 128 +#define I40IW_MAX_RQ_WQE_SHIFT 2 +#define I40IW_MAX_QUANTA_PER_WR 2 + +#define I40IW_QP_SW_MAX_SQ_QUANTA 2048 +#define I40IW_QP_SW_MAX_RQ_QUANTA 16384 +#define I40IW_QP_SW_MAX_WQ_QUANTA 2048 +#define I40IW_MAX_QP_WRS ((I40IW_QP_SW_MAX_SQ_QUANTA - IRDMA_SQ_RSVD) / I40IW_MAX_QUANTA_PER_WR) +#define I40IW_FIRST_VF_FPM_ID 16 +#define QUEUE_TYPE_CEQ 2 +#define NULL_QUEUE_INDEX 0x7FF + +void i40iw_init_hw(struct irdma_sc_dev *dev); +#endif /* I40IW_HW_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/i40iw_if.c b/drivers/intel/irdma-1.14.33/src/irdma/i40iw_if.c new file mode 100644 index 000000000..931a54f92 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/i40iw_if.c @@ -0,0 +1,271 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2022 Intel Corporation */ +#include "main.h" +#include "i40iw_hw.h" +#include "i40e_client.h" + +static struct i40e_client i40iw_client; + +/** + * i40iw_l2param_change - handle mss change + * @cdev_info: parent lan device information structure with data/ops + * @client: client for parameter change + * @params: new parameters from L2 + */ +static void i40iw_l2param_change(struct i40e_info *cdev_info, + struct i40e_client *client, + struct i40e_params *params) +{ + struct irdma_l2params l2params = {}; + struct irdma_device *iwdev; + struct ib_device *ibdev; + + ibdev = ib_device_get_by_netdev(cdev_info->netdev, RDMA_DRIVER_IRDMA); + if (!ibdev) + return; + + iwdev = to_iwdev(ibdev); + + if (iwdev->vsi.mtu != params->mtu) { + l2params.mtu_changed = true; + l2params.mtu = params->mtu; + } + irdma_change_l2params(&iwdev->vsi, &l2params); + ib_device_put(ibdev); +} + +/** + * i40iw_close - client interface operation close for iwarp/uda device + * @cdev_info: parent lan device information structure with data/ops + * @client: client to close + * @reset: flag to indicate close on reset + * + * Called by the lan driver during the processing of client unregister + * Destroy and clean up the driver resources + */ +static void i40iw_close(struct i40e_info *cdev_info, struct i40e_client *client, + bool reset) +{ + struct irdma_device *iwdev; + struct ib_device *ibdev; + + ibdev = ib_device_get_by_netdev(cdev_info->netdev, RDMA_DRIVER_IRDMA); + if (WARN_ON(!ibdev)) + return; + + iwdev = to_iwdev(ibdev); + if (reset) + iwdev->rf->reset = true; + + irdma_unregister_notifiers(iwdev); + ib_device_put(&iwdev->ibdev); + irdma_ib_unregister_device(iwdev); +#ifndef IB_DEALLOC_DRIVER_SUPPORT + /* In newer kernels core issues callback irdma_ib_dealloc_device to cleanup + * Older kernels require cleanup here and explicilty need to call ib_dealloc_device + */ + irdma_deinit_device(iwdev); + ib_dealloc_device(&iwdev->ibdev); +#endif /* IB_DEALLOC_DRIVER_SUPPORT */ + pr_debug("INIT: Gen1 PF[%d] close complete\n", PCI_FUNC(cdev_info->pcidev->devfn)); +} + +static void i40iw_request_reset(struct irdma_pci_f *rf) +{ + struct i40e_info *cdev_info = rf->cdev; + + cdev_info->ops->request_reset(cdev_info, &i40iw_client, 1); +} + +static void i40iw_fill_device_info(struct irdma_device *iwdev, struct i40e_info *cdev_info) +{ + struct irdma_pci_f *rf = iwdev->rf; + + rf->rdma_ver = IRDMA_GEN_1; + rf->sc_dev.hw = &rf->hw; + rf->sc_dev.hw_attrs.uk_attrs.hw_rev = IRDMA_GEN_1; + rf->sc_dev.privileged = true; + rf->gen_ops.request_reset = i40iw_request_reset; + rf->hw.hw_addr = cdev_info->hw_addr; + rf->pcidev = cdev_info->pcidev; + rf->hw.device = &rf->pcidev->dev; + rf->ftype = cdev_info->ftype; + rf->pf_id = cdev_info->fid; + rf->cdev = cdev_info; + rf->msix_count = cdev_info->msix_count; + rf->msix_entries = cdev_info->msix_entries; + irdma_set_rf_user_cfg_params(rf); + rf->protocol_used = IRDMA_IWARP_PROTOCOL_ONLY; + rf->iwdev = iwdev; + + iwdev->init_state = INITIAL_STATE; + iwdev->rcv_wnd = IRDMA_CM_DEFAULT_RCV_WND_SCALED; + iwdev->rcv_wscale = IRDMA_CM_DEFAULT_RCV_WND_SCALE; + iwdev->netdev = cdev_info->netdev; + iwdev->aux_dev = cdev_info->aux_dev; + iwdev->vsi_num = 0; +} + +/** + * i40iw_open - client interface operation open for iwarp/uda device + * @cdev_info: parent lan device information structure with data/ops + * @client: iwarp client information, provided during registration + * + * Called by the lan driver during the processing of client register + * Create device resources, set up queues, pble and hmc objects and + * register the device with the ib verbs interface + * Return 0 if successful, otherwise return error + */ +static int i40iw_open(struct i40e_info *cdev_info, struct i40e_client *client) +{ + struct irdma_l2params l2params = {}; + struct irdma_device *iwdev; + struct irdma_pci_f *rf; + int err = -EIO; + int i; + u16 qset; + u16 last_qset = IRDMA_NO_QSET; + struct irdma_handler *hdl; + + iwdev = ib_alloc_device(irdma_device, ibdev); + if (!iwdev) + return -ENOMEM; + + iwdev->rf = kzalloc(sizeof(*rf), GFP_KERNEL); + if (!iwdev->rf) { + ib_dealloc_device(&iwdev->ibdev); + return -ENOMEM; + } + + i40iw_fill_device_info(iwdev, cdev_info); + rf = iwdev->rf; + + hdl = kzalloc(sizeof(*hdl), GFP_KERNEL); + if (!hdl) { + err = -ENOMEM; + goto err_hdl; + } + + hdl->iwdev = iwdev; + iwdev->hdl = hdl; + if (irdma_ctrl_init_hw(rf)) { + err = -EIO; + goto err_ctrl_init; + } + + l2params.mtu = (cdev_info->params.mtu) ? cdev_info->params.mtu : IRDMA_DEFAULT_MTU; + for (i = 0; i < I40E_CLIENT_MAX_USER_PRIORITY; i++) { + qset = cdev_info->params.qos.prio_qos[i].qs_handle; + l2params.up2tc[i] = cdev_info->params.qos.prio_qos[i].tc; + l2params.qs_handle_list[i] = qset; + if (last_qset == IRDMA_NO_QSET) + last_qset = qset; + else if ((qset != last_qset) && (qset != IRDMA_NO_QSET)) + iwdev->dcb_vlan_mode = true; + } + + if (irdma_rt_init_hw(iwdev, &l2params)) { + err = -EIO; + goto err_rt_init; + } + + err = irdma_ib_register_device(iwdev); + if (err) + goto err_ibreg; + + err = irdma_register_notifiers(iwdev); + if (err) + goto err_notifier_reg; + + irdma_add_handler(hdl); +#ifdef CONFIG_DEBUG_FS + irdma_dbg_pf_init(hdl); +#endif + ibdev_dbg(&iwdev->ibdev, "INIT: Gen1 PF[%d] open success\n", + PCI_FUNC(rf->pcidev->devfn)); + + return 0; + +err_notifier_reg: + irdma_ib_unregister_device(iwdev); +err_ibreg: + irdma_rt_deinit_hw(iwdev); +err_rt_init: + irdma_ctrl_deinit_hw(rf); +err_ctrl_init: + kfree(hdl); +err_hdl: + kfree(iwdev->rf); + ib_dealloc_device(&iwdev->ibdev); + + return err; +} + +/* client interface functions */ +static const struct i40e_client_ops i40e_ops = { + .open = i40iw_open, + .close = i40iw_close, + .l2_param_change = i40iw_l2param_change +}; + +static struct i40e_client i40iw_client = { + .ops = &i40e_ops, + .version.major = I40E_CLIENT_VERSION_MAJOR, + .version.minor = I40E_CLIENT_VERSION_MINOR, + .version.build = I40E_CLIENT_VERSION_BUILD, + .type = I40E_CLIENT_IWARP, +}; + +static int i40iw_probe(struct auxiliary_device *aux_dev, const struct auxiliary_device_id *id) +{ + struct i40e_auxiliary_device *i40e_adev = container_of(aux_dev, + struct i40e_auxiliary_device, + aux_dev); + struct i40e_info *cdev_info = i40e_adev->ldev; + + if (cdev_info->version.major != I40E_CLIENT_VERSION_MAJOR || + cdev_info->version.minor != I40E_CLIENT_VERSION_MINOR) { + pr_err("version mismatch:\n"); + pr_err("expected major ver %d, caller specified major ver %d\n", + I40E_CLIENT_VERSION_MAJOR, cdev_info->version.major); + pr_err("expected minor ver %d, caller specified minor ver %d\n", + I40E_CLIENT_VERSION_MINOR, cdev_info->version.minor); + return -EINVAL; + } + + strncpy(i40iw_client.name, "irdma", I40E_CLIENT_STR_LENGTH); + cdev_info->client = &i40iw_client; + + return cdev_info->ops->client_device_register(cdev_info); +} + +#ifdef HAVE_AUXILIARY_DRIVER_INT_REMOVE +static int i40iw_remove(struct auxiliary_device *aux_dev) +#else +static void i40iw_remove(struct auxiliary_device *aux_dev) +#endif +{ + struct i40e_auxiliary_device *i40e_adev = container_of(aux_dev, + struct i40e_auxiliary_device, + aux_dev); + struct i40e_info *cdev_info = i40e_adev->ldev; + + cdev_info->ops->client_device_unregister(cdev_info); +#ifdef HAVE_AUXILIARY_DRIVER_INT_REMOVE + return 0; +#endif /* HAVE_AUXILIARY_DRIVER_INT_REMOVE */ +} + +static const struct auxiliary_device_id i40iw_auxiliary_id_table[] = { + {.name = "i40e.iwarp", }, + {}, +}; + +MODULE_DEVICE_TABLE(auxiliary, i40iw_auxiliary_id_table); + +struct auxiliary_driver i40iw_auxiliary_drv = { + .name = "gen_1", + .id_table = i40iw_auxiliary_id_table, + .probe = i40iw_probe, + .remove = i40iw_remove, +}; diff --git a/drivers/intel/irdma-1.14.33/src/irdma/icrdma_hw.c b/drivers/intel/irdma-1.14.33/src/irdma/icrdma_hw.c new file mode 100644 index 000000000..dbd402082 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/icrdma_hw.c @@ -0,0 +1,392 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2017 - 2023 Intel Corporation */ +#include "osdep.h" +#include "type.h" +#include "icrdma_hw.h" +#include "main.h" + +static u32 icrdma_vf_regs[IRDMA_MAX_REGS] = { + VFPE_CQPTAIL1, + VFPE_CQPDB1, + VFPE_CCQPSTATUS1, + VFPE_CCQPHIGH1, + VFPE_CCQPLOW1, + VFPE_CQARM1, + VFPE_CQACK1, + VFPE_AEQALLOC1, + VFPE_CQPERRCODES1, + VFPE_WQEALLOC1, + VFINT_DYN_CTLN(0), + ICRDMA_VF_DB_ADDR_OFFSET, +}; +static u32 icrdma_regs[IRDMA_MAX_REGS] = { + PFPE_CQPTAIL, + PFPE_CQPDB, + PFPE_CCQPSTATUS, + PFPE_CCQPHIGH, + PFPE_CCQPLOW, + PFPE_CQARM, + PFPE_CQACK, + PFPE_AEQALLOC, + PFPE_CQPERRCODES, + PFPE_WQEALLOC, + GLINT_DYN_CTL(0), + ICRDMA_DB_ADDR_OFFSET, + + GLPCI_LBARCTRL, + GLPE_CPUSTATUS0, + GLPE_CPUSTATUS1, + GLPE_CPUSTATUS2, + PFINT_AEQCTL, + GLINT_CEQCTL(0), + VSIQF_PE_CTL1(0), + PFHMC_PDINV, + GLHMC_VFPDINV(0), + GLPE_CRITERR, + GLINT_RATE(0), +}; + +static u64 icrdma_masks[IRDMA_MAX_MASKS] = { + ICRDMA_CCQPSTATUS_CCQP_DONE, + ICRDMA_CCQPSTATUS_CCQP_ERR, + ICRDMA_CQPSQ_STAG_PDID, + ICRDMA_CQPSQ_CQ_CEQID, + ICRDMA_CQPSQ_CQ_CQID, + ICRDMA_COMMIT_FPM_CQCNT, + ICRDMA_CQPSQ_UPESD_HMCFNID, +}; + +static u8 icrdma_shifts[IRDMA_MAX_SHIFTS] = { + ICRDMA_CCQPSTATUS_CCQP_DONE_S, + ICRDMA_CCQPSTATUS_CCQP_ERR_S, + ICRDMA_CQPSQ_STAG_PDID_S, + ICRDMA_CQPSQ_CQ_CEQID_S, + ICRDMA_CQPSQ_CQ_CQID_S, + ICRDMA_COMMIT_FPM_CQCNT_S, + ICRDMA_CQPSQ_UPESD_HMCFNID_S, +}; + +/** + * icrdma_ena_irq - Enable interrupt + * @dev: pointer to the device structure + * @idx: vector index + */ +static void icrdma_ena_irq(struct irdma_sc_dev *dev, u32 idx) +{ + u32 val; + u32 interval = 0; + + if (dev->ceq_itr && dev->aeq->msix_idx != idx) + interval = dev->ceq_itr >> 1; /* 2 usec units */ + val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_ITR_INDX, IRDMA_IDX_ITR0) | + FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTERVAL, interval) | + FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, true) | + FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, true); + if (dev->privileged) + writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx); + else + writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1)); +} + +/** + * icrdma_disable_irq - Disable interrupt + * @dev: pointer to the device structure + * @idx: vector index + */ +static void icrdma_disable_irq(struct irdma_sc_dev *dev, u32 idx) +{ + if (dev->privileged) + writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + idx); + else + writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx - 1)); +} + +/** + * icrdma_cfg_ceq- Configure CEQ interrupt + * @dev: pointer to the device structure + * @ceq_id: Completion Event Queue ID + * @idx: vector index + * @enable: True to enable, False disables + */ +static void icrdma_cfg_ceq(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx, + bool enable) +{ + u32 reg_val; + + reg_val = enable ? IRDMA_GLINT_CEQCTL_CAUSE_ENA : 0; + reg_val |= (idx << IRDMA_GLINT_CEQCTL_MSIX_INDX_S) | + IRDMA_GLINT_CEQCTL_ITR_INDX; + + writel(reg_val, dev->hw_regs[IRDMA_GLINT_CEQCTL] + ceq_id); +} + +static const struct irdma_irq_ops icrdma_irq_ops = { + .irdma_cfg_aeq = irdma_cfg_aeq, + .irdma_cfg_ceq = icrdma_cfg_ceq, + .irdma_dis_irq = icrdma_disable_irq, + .irdma_en_irq = icrdma_ena_irq, +}; + +static const struct irdma_hw_stat_map icrdma_hw_stat_map[] = { + [IRDMA_HW_STAT_INDEX_RXVLANERR] = { 0, 32, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_IP4RXOCTS] = { 8, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4RXPKTS] = { 16, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4RXDISCARD] = { 24, 32, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_IP4RXTRUNC] = { 24, 0, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_IP4RXFRAGS] = { 32, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS] = { 40, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] = { 48, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXOCTS] = { 56, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXPKTS] = { 64, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXDISCARD] = { 72, 32, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_IP6RXTRUNC] = { 72, 0, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_IP6RXFRAGS] = { 80, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS] = { 88, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] = { 96, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXOCTS] = { 104, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXPKTS] = { 112, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXFRAGS] = { 120, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS] = { 128, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] = { 136, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXOCTS] = { 144, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXPKTS] = { 152, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXFRAGS] = { 160, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS] = { 168, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] = { 176, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] = { 184, 32, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] = { 184, 0, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_TCPRXSEGS] = { 192, 32, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_TCPRXOPTERR] = { 200, 32, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] = { 200, 0, IRDMA_MAX_STATS_24 }, + [IRDMA_HW_STAT_INDEX_TCPTXSEG] = { 208, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_TCPRTXSEG] = { 216, 32, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_UDPRXPKTS] = { 224, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_UDPTXPKTS] = { 232, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMARXWRS] = { 240, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMARXRDS] = { 248, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMARXSNDS] = { 256, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMATXWRS] = { 264, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMATXRDS] = { 272, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMATXSNDS] = { 280, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMAVBND] = { 288, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RDMAVINV] = { 296, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS] = { 304, 0, IRDMA_MAX_STATS_48 }, + [IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED] = { 312, 32, IRDMA_MAX_STATS_16 }, + [IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED] = { 312, 0, IRDMA_MAX_STATS_32 }, + [IRDMA_HW_STAT_INDEX_TXNPCNPSENT] = { 320, 0, IRDMA_MAX_STATS_32 }, +}; + +void icrdma_init_hw(struct irdma_sc_dev *dev) +{ + int i; + u8 __iomem *hw_addr; + + if (dev->privileged) { + for (i = 0; i < IRDMA_MAX_REGS; ++i) { + hw_addr = dev->hw->hw_addr; + + if (i == IRDMA_DB_ADDR_OFFSET) + hw_addr = NULL; + + dev->hw_regs[i] = + (u32 __iomem *)(hw_addr + icrdma_regs[i]); + } + dev->hw_attrs.max_hw_vf_fpm_id = IRDMA_MAX_VF_FPM_ID; + dev->hw_attrs.first_hw_vf_fpm_id = IRDMA_FIRST_VF_FPM_ID; + } else { + for (i = 0; i < IRDMA_MAX_REGS; ++i) { + hw_addr = dev->hw->hw_addr; + + if (i == IRDMA_DB_ADDR_OFFSET) + hw_addr = NULL; + + dev->hw_regs[i] = + (u32 __iomem *)(hw_addr + icrdma_vf_regs[i]); + } + } + + for (i = 0; i < IRDMA_MAX_SHIFTS; ++i) + dev->hw_shifts[i] = icrdma_shifts[i]; + + for (i = 0; i < IRDMA_MAX_MASKS; ++i) + dev->hw_masks[i] = icrdma_masks[i]; + + dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC]; + dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM]; + dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC]; + dev->cqp_db = dev->hw_regs[IRDMA_CQPDB]; + dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK]; + dev->irq_ops = &icrdma_irq_ops; + dev->hw_stats_map = icrdma_hw_stat_map; + dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G; + dev->hw_attrs.max_hw_ird = ICRDMA_MAX_IRD_SIZE; + dev->hw_attrs.max_hw_ord = ICRDMA_MAX_ORD_SIZE; + dev->hw_attrs.max_stat_inst = ICRDMA_MAX_STATS_COUNT; + dev->hw_attrs.max_stat_idx = IRDMA_HW_STAT_INDEX_MAX_GEN_2; + dev->hw_attrs.max_hw_device_pages = ICRDMA_MAX_PUSH_PAGE_COUNT; + + dev->hw_attrs.uk_attrs.max_hw_wq_frags = ICRDMA_MAX_WQ_FRAGMENT_COUNT; + dev->hw_attrs.uk_attrs.max_hw_read_sges = ICRDMA_MAX_SGE_RD; + dev->hw_attrs.uk_attrs.min_hw_wq_size = ICRDMA_MIN_WQ_SIZE; + dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR; + dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RTS_AE | + IRDMA_FEATURE_CQ_RESIZE; +} + +void irdma_init_config_check(struct irdma_config_check *cc, u8 traffic_class, u16 qs_handle) +{ + cc->config_ok = false; + cc->traffic_class = traffic_class; + cc->qs_handle = qs_handle; + cc->lfc_set = 0; + cc->pfc_set = 0; +} + +static bool irdma_is_lfc_set(struct irdma_config_check *cc, struct irdma_sc_vsi *vsi) +{ + u32 lfc = 1; + u8 fn_id = vsi->dev->hmc_fn_id; + + lfc &= (rd32(vsi->dev->hw, + PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_0 + 4 * fn_id) >> 8); + lfc &= (rd32(vsi->dev->hw, + PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_0 + 4 * fn_id) >> 8); + lfc &= rd32(vsi->dev->hw, + PRTMAC_HSEC_CTL_RX_ENABLE_GPP_0 + 4 * vsi->dev->hmc_fn_id); + + if (lfc) + return true; + return false; +} + +static bool irdma_check_tc_has_pfc(struct irdma_sc_vsi *vsi, u64 reg_offset, u16 traffic_class) +{ + u32 value, pfc = 0; + u32 i; + + value = rd32(vsi->dev->hw, reg_offset); + for (i = 0; i < 4; i++) + pfc |= (value >> (8 * i + traffic_class)) & 0x1; + + if (pfc) + return true; + return false; +} + +static bool irdma_is_pfc_set(struct irdma_config_check *cc, struct irdma_sc_vsi *vsi) +{ + u32 pause; + u8 fn_id = vsi->dev->hmc_fn_id; + + pause = (rd32(vsi->dev->hw, + PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_0 + 4 * fn_id) >> + cc->traffic_class) & BIT(0); + pause &= (rd32(vsi->dev->hw, + PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_0 + 4 * fn_id) >> + cc->traffic_class) & BIT(0); + + return irdma_check_tc_has_pfc(vsi, GLDCB_TC2PFC, cc->traffic_class) && + pause; +} + +bool irdma_is_config_ok(struct irdma_config_check *cc, struct irdma_sc_vsi *vsi) +{ + cc->lfc_set = irdma_is_lfc_set(cc, vsi); + cc->pfc_set = irdma_is_pfc_set(cc, vsi); + + cc->config_ok = cc->lfc_set || cc->pfc_set; + + return cc->config_ok; +} + +#define IRDMA_RCV_WND_NO_FC 0x1FFFC +#define IRDMA_RCV_WND_FC 0x3FFFC + +#define IRDMA_CWND_NO_FC 0x20 +#define IRDMA_CWND_FC 0x400 + +#define IRDMA_RTOMIN_NO_FC 0x5 +#define IRDMA_RTOMIN_FC 0x32 + +#define IRDMA_ACKCREDS_NO_FC 0x02 +#define IRDMA_ACKCREDS_FC 0x1E + +static void irdma_check_flow_ctrl(struct irdma_sc_vsi *vsi, u8 user_prio, u8 traffic_class) +{ + struct irdma_config_check *cfg_chk = &vsi->cfg_check[user_prio]; + struct irdma_device *iwdev = vsi->back_vsi; + + if (!irdma_is_config_ok(cfg_chk, vsi)) { + if (!iwdev->override_rcv_wnd) + iwdev->rcv_wnd = IRDMA_RCV_WND_NO_FC; + if (!iwdev->override_cwnd) + iwdev->roce_cwnd = IRDMA_CWND_NO_FC; + if (!iwdev->override_rtomin) + iwdev->roce_rtomin = IRDMA_RTOMIN_NO_FC; + if (!iwdev->override_ackcreds) + iwdev->roce_ackcreds = IRDMA_ACKCREDS_NO_FC; +#define IRDMA_READ_FENCE_RATE_NO_FC 4 + if (iwdev->roce_mode && !iwdev->override_rd_fence_rate) + iwdev->rd_fence_rate = IRDMA_READ_FENCE_RATE_NO_FC; + if (vsi->tc_print_warning[traffic_class]) { + pr_info("INFO: Flow control is disabled for this traffic class (%d) on this vsi.\n", + traffic_class); + vsi->tc_print_warning[traffic_class] = false; + } + } else { + if (!iwdev->override_rcv_wnd) + iwdev->rcv_wnd = IRDMA_RCV_WND_FC; + if (!iwdev->override_cwnd) + iwdev->roce_cwnd = IRDMA_CWND_FC; + if (!iwdev->override_rtomin) + iwdev->roce_rtomin = IRDMA_RTOMIN_FC; + if (!iwdev->override_ackcreds) + iwdev->roce_ackcreds = IRDMA_ACKCREDS_FC; +#define IRDMA_READ_FENCE_RATE_FC 0 + if (!iwdev->override_rd_fence_rate) + iwdev->rd_fence_rate = IRDMA_READ_FENCE_RATE_FC; + if (vsi->tc_print_warning[traffic_class]) { + pr_info("INFO: Flow control is enabled for this traffic class (%d) on this vsi.\n", + traffic_class); + vsi->tc_print_warning[traffic_class] = false; + } + } +} + +void irdma_check_fc_for_tc_update(struct irdma_sc_vsi *vsi, + struct irdma_l2params *l2params) +{ + u8 i; + + if (!vsi->dev->privileged) + return; + for (i = 0; i < IEEE_8021QAZ_MAX_TCS; i++) + vsi->tc_print_warning[i] = true; + + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + struct irdma_config_check *cfg_chk = &vsi->cfg_check[i]; + u8 tc = l2params->up2tc[i]; + + cfg_chk->traffic_class = tc; + cfg_chk->qs_handle = vsi->qos[i].qs_handle[0]; + irdma_check_flow_ctrl(vsi, i, tc); + } +} + +void irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp) +{ + u8 i; + + if (!vsi->dev->privileged) + return; + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + struct irdma_config_check *cfg_chk = &vsi->cfg_check[i]; + + irdma_init_config_check(cfg_chk, + vsi->qos[i].traffic_class, + vsi->qos[i].qs_handle[sc_qp->qs_idx]); + if (sc_qp->qs_handle == cfg_chk->qs_handle) + irdma_check_flow_ctrl(vsi, i, cfg_chk->traffic_class); + } +} + diff --git a/drivers/intel/irdma-1.14.33/src/irdma/icrdma_hw.h b/drivers/intel/irdma-1.14.33/src/irdma/icrdma_hw.h new file mode 100644 index 000000000..1b31715cd --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/icrdma_hw.h @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2017 - 2023 Intel Corporation */ +#ifndef ICRDMA_HW_H +#define ICRDMA_HW_H + +#include "irdma.h" + +#define VFPE_CQPTAIL1 0x0000a000 +#define VFPE_CQPDB1 0x0000bc00 +#define VFPE_CCQPSTATUS1 0x0000b800 +#define VFPE_CCQPHIGH1 0x00009800 +#define VFPE_CCQPLOW1 0x0000ac00 +#define VFPE_CQARM1 0x0000b400 +#define VFPE_CQARM1 0x0000b400 +#define VFPE_CQACK1 0x0000b000 +#define VFPE_AEQALLOC1 0x0000a400 +#define VFPE_CQPERRCODES1 0x00009c00 +#define VFPE_WQEALLOC1 0x0000c000 +#define VFINT_DYN_CTLN(_i) (0x00003800 + ((_i) * 4)) /* _i=0...63 */ + +#define PFPE_CQPTAIL 0x00500880 +#define PFPE_CQPDB 0x00500800 +#define PFPE_CCQPSTATUS 0x0050a000 +#define PFPE_CCQPHIGH 0x0050a100 +#define PFPE_CCQPLOW 0x0050a080 +#define PFPE_CQARM 0x00502c00 +#define PFPE_CQACK 0x00502c80 +#define PFPE_AEQALLOC 0x00502d00 +#define GLINT_DYN_CTL(_INT) (0x00160000 + ((_INT) * 4)) /* _i=0...2047 */ +#define GLPCI_LBARCTRL 0x0009de74 +#define GLPE_CPUSTATUS0 0x0050ba5c +#define GLPE_CPUSTATUS1 0x0050ba60 +#define GLPE_CPUSTATUS2 0x0050ba64 +#define PFINT_AEQCTL 0x0016cb00 +#define PFPE_CQPERRCODES 0x0050a200 +#define PFPE_WQEALLOC 0x00504400 +#define GLINT_CEQCTL(_INT) (0x0015c000 + ((_INT) * 4)) /* _i=0...2047 */ +#define VSIQF_PE_CTL1(_VSI) (0x00414000 + ((_VSI) * 4)) /* _i=0...767 */ +#define PFHMC_PDINV 0x00520300 +#define GLHMC_VFPDINV(_i) (0x00528300 + ((_i) * 4)) /* _i=0...31 */ +#define GLPE_CRITERR 0x00534000 +#define GLINT_RATE(_INT) (0x0015A000 + ((_INT) * 4)) /* _i=0...2047 */ /* Reset Source: CORER */ + +#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_0 0x001e3180 +#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_1 0x001e3184 +#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_2 0x001e3188 +#define PRTMAC_HSEC_CTL_RX_PAUSE_ENABLE_3 0x001e318c + +#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_0 0x001e31a0 +#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_1 0x001e31a4 +#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_2 0x001e31a8 +#define PRTMAC_HSEC_CTL_TX_PAUSE_ENABLE_3 0x001e31aC + +#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_0 0x001e34c0 +#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_1 0x001e34c4 +#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_2 0x001e34c8 +#define PRTMAC_HSEC_CTL_RX_ENABLE_GPP_3 0x001e34cC + +#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_0 0x001e35c0 +#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_1 0x001e35c4 +#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_2 0x001e35c8 +#define PRTMAC_HSEC_CTL_RX_ENABLE_PPP_3 0x001e35cC + +#define GLDCB_TC2PFC 0x001d2694 +#define PRTMAC_HSEC_CTL_RX_ENABLE_GCP 0x001e31c0 + +#define ICRDMA_DB_ADDR_OFFSET (8 * 1024 * 1024 - 64 * 1024) + +#define ICRDMA_VF_DB_ADDR_OFFSET (64 * 1024) + +#define ICRDMA_CCQPSTATUS_CCQP_DONE_S 0 +#define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0) +#define ICRDMA_CCQPSTATUS_CCQP_ERR_S 31 +#define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31) +#define ICRDMA_CQPSQ_STAG_PDID_S 46 +#define ICRDMA_CQPSQ_STAG_PDID GENMASK_ULL(63, 46) +#define ICRDMA_CQPSQ_CQ_CEQID_S 22 +#define ICRDMA_CQPSQ_CQ_CEQID GENMASK_ULL(31, 22) +#define ICRDMA_CQPSQ_CQ_CQID_S 0 +#define ICRDMA_CQPSQ_CQ_CQID GENMASK_ULL(18, 0) +#define ICRDMA_COMMIT_FPM_CQCNT_S 0 +#define ICRDMA_COMMIT_FPM_CQCNT GENMASK_ULL(19, 0) +#define ICRDMA_CQPSQ_UPESD_HMCFNID_S 0 +#define ICRDMA_CQPSQ_UPESD_HMCFNID GENMASK_ULL(5, 0) + +enum icrdma_device_caps_const { + ICRDMA_MAX_WQ_FRAGMENT_COUNT = 13, + ICRDMA_MAX_SGE_RD = 13, + ICRDMA_MAX_STATS_COUNT = 128, + + ICRDMA_MAX_IRD_SIZE = 32, + ICRDMA_MAX_ORD_SIZE = 32, + ICRDMA_MIN_WQ_SIZE = 8 /* WQEs */, + ICRDMA_MAX_PUSH_PAGE_COUNT = 256, + +}; + +void icrdma_init_hw(struct irdma_sc_dev *dev); +void irdma_init_config_check(struct irdma_config_check *cc, + u8 traffic_class, + u16 qs_handle); +bool irdma_is_config_ok(struct irdma_config_check *cc, struct irdma_sc_vsi *vsi); +void irdma_check_fc_for_tc_update(struct irdma_sc_vsi *vsi, + struct irdma_l2params *l2params); +void irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp); +#endif /* ICRDMA_HW_H*/ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_hw.c b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_hw.c new file mode 100644 index 000000000..53d4d6963 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_hw.c @@ -0,0 +1,151 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2018 - 2023 Intel Corporation */ +#include "osdep.h" +#include "type.h" +#include "protos.h" +#include "ig3rdma_regs.h" +#include "ig3rdma_regs_apf.h" +#include "ig3rdma_regs_avf.h" +#include "ig3rdma_hw.h" + +struct ig3_rdma_reg { + u32 reg_offset; + bool privileged; +}; + +/** + * ig3rdma_ena_irq - Enable interrupt + * @dev: pointer to the device structure + * @idx: vector index + */ +static void ig3rdma_ena_irq(struct irdma_sc_dev *dev, u32 idx) +{ + u32 val; + u32 int_stride = 1; /* one u32 per register */ + + if (dev->is_pf) + int_stride = 0x400; + else + idx--; /* VFs use DYN_CTL_N */ + + val = FIELD_PREP(IRDMA_GLINT_DYN_CTL_INTENA, 1) | + FIELD_PREP(IRDMA_GLINT_DYN_CTL_CLEARPBA, 1); + + writel(val, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx * int_stride)); +} + +/** + * ig3rdma_disable_irq - Disable interrupt + * @dev: pointer to the device structure + * @idx: vector index + */ +static void ig3rdma_disable_irq(struct irdma_sc_dev *dev, u32 idx) +{ + u32 int_stride = 1; /* one u32 per register */ + + if (dev->is_pf) + int_stride = 0x400; + else + idx--; /* VFs use DYN_CTL_N */ + + writel(0, dev->hw_regs[IRDMA_GLINT_DYN_CTL] + (idx * int_stride)); +} + +static const struct irdma_irq_ops ig3rdma_irq_ops = { + .irdma_dis_irq = ig3rdma_disable_irq, + .irdma_en_irq = ig3rdma_ena_irq, +}; + +static const struct irdma_hw_stat_map ig3rdma_hw_stat_map[] = { + [IRDMA_HW_STAT_INDEX_RXVLANERR] = { 0, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4RXOCTS] = { 8, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4RXPKTS] = { 16, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4RXDISCARD] = { 24, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4RXTRUNC] = { 32, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4RXFRAGS] = { 40, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS] = { 48, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] = { 56, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6RXOCTS] = { 64, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6RXPKTS] = { 72, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6RXDISCARD] = { 80, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6RXTRUNC] = { 88, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6RXFRAGS] = { 96, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS] = { 104, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] = { 112, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4TXOCTS] = { 120, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4TXPKTS] = { 128, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4TXFRAGS] = { 136, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS] = { 144, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] = { 152, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6TXOCTS] = { 160, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6TXPKTS] = { 168, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6TXFRAGS] = { 176, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS] = { 184, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] = { 192, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] = { 200, 0, 0 }, + [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] = { 208, 0, 0 }, + [IRDMA_HW_STAT_INDEX_TCPRTXSEG] = { 216, 0, 0 }, + [IRDMA_HW_STAT_INDEX_TCPRXOPTERR] = { 224, 0, 0 }, + [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] = { 232, 0, 0 }, + [IRDMA_HW_STAT_INDEX_TCPTXSEG] = { 240, 0, 0 }, + [IRDMA_HW_STAT_INDEX_TCPRXSEGS] = { 248, 0, 0 }, + [IRDMA_HW_STAT_INDEX_UDPRXPKTS] = { 256, 0, 0 }, + [IRDMA_HW_STAT_INDEX_UDPTXPKTS] = { 264, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMARXWRS] = { 272, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMARXRDS] = { 280, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMARXSNDS] = { 288, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMATXWRS] = { 296, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMATXRDS] = { 304, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMATXSNDS] = { 312, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMAVBND] = { 320, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMAVINV] = { 328, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS] = { 336, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED] = { 344, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED] = { 352, 0, 0 }, + [IRDMA_HW_STAT_INDEX_TXNPCNPSENT] = { 360, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RNR_SENT] = { 368, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RNR_RCVD] = { 376, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMAORDLMTCNT] = { 384, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMAIRDLMTCNT] = { 392, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMARXATS] = { 408, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMATXATS] = { 416, 0, 0 }, + [IRDMA_HW_STAT_INDEX_NAKSEQERR] = { 424, 0, 0 }, + [IRDMA_HW_STAT_INDEX_NAKSEQERR_IMPLIED] = { 432, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RTO] = { 440, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RXOOOPKTS] = { 448, 0, 0 }, + [IRDMA_HW_STAT_INDEX_ICRCERR] = { 456, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMARXFLUSH] = { 472, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMATXFLUSH] = { 480, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMARXATOMICWRITE] = { 488, 0, 0 }, + [IRDMA_HW_STAT_INDEX_RDMATXATOMICWRITE] = { 496, 0, 0 }, +}; + +void ig3rdma_init_hw(struct irdma_sc_dev *dev) +{ + dev->irq_ops = &ig3rdma_irq_ops; + dev->hw_stats_map = ig3rdma_hw_stat_map; + + dev->hw_attrs.uk_attrs.max_hw_wq_frags = IG3RDMA_MAX_WQ_FRAGMENT_COUNT; + dev->hw_attrs.uk_attrs.max_hw_read_sges = IG3RDMA_MAX_SGE_RD; + dev->hw_attrs.uk_attrs.max_hw_sq_chunk = IRDMA_MAX_QUANTA_PER_WR; + dev->hw_attrs.first_hw_vf_fpm_id = 0; + dev->hw_attrs.max_hw_vf_fpm_id = IG3_MAX_APFS + IG3_MAX_AVFS; + dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_64_BYTE_CQE; + if (dev->feature_info[IRDMA_FTN_FLAGS] & IRDMA_ATOMICS_ALLOWED_BIT) + dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_ATOMIC_OPS; + dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_CQE_TIMESTAMPING; + + dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_SRQ; + dev->hw_attrs.uk_attrs.feature_flags |= IRDMA_FEATURE_RTS_AE | + IRDMA_FEATURE_CQ_RESIZE; + dev->hw_attrs.page_size_cap = SZ_4K | SZ_2M | SZ_1G; + dev->hw_attrs.max_hw_ird = IG3RDMA_MAX_IRD_SIZE; + dev->hw_attrs.max_hw_ord = IG3RDMA_MAX_ORD_SIZE; + dev->hw_attrs.max_stat_inst = IG3RDMA_MAX_STATS_COUNT; + dev->hw_attrs.max_stat_idx = IRDMA_HW_STAT_INDEX_MAX_GEN_3; + dev->hw_attrs.uk_attrs.min_hw_wq_size = IG3RDMA_MIN_WQ_SIZE; + dev->hw_attrs.uk_attrs.max_hw_srq_quanta = IRDMA_SRQ_MAX_QUANTA; + dev->hw_attrs.uk_attrs.max_hw_inline = IG3RDMA_MAX_INLINE_DATA_SIZE; + dev->hw_attrs.max_hw_device_pages = + dev->is_pf ? IG3RDMA_MAX_PF_PUSH_PAGE_COUNT : IG3RDMA_MAX_VF_PUSH_PAGE_COUNT; +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_hw.h b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_hw.h new file mode 100644 index 000000000..50406f9b9 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_hw.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2021 - 2023 Intel Corporation */ +#ifndef IG3RDMA_HW_H +#define IG3RDMA_HW_H + +#define IG3_MAX_APFS 1 +#define IG3_MAX_AVFS 0 +enum ig3rdma_device_caps_const { + IG3RDMA_MAX_WQ_FRAGMENT_COUNT = 14, + IG3RDMA_MAX_SGE_RD = 14, + + IG3RDMA_MAX_STATS_COUNT = 128, + + IG3RDMA_MAX_IRD_SIZE = 2048, + IG3RDMA_MAX_ORD_SIZE = 2048, + IG3RDMA_MIN_WQ_SIZE = 16 /* WQEs */, + IG3RDMA_MAX_INLINE_DATA_SIZE = 216, + IG3RDMA_MAX_PF_PUSH_PAGE_COUNT = 8192, + IG3RDMA_MAX_VF_PUSH_PAGE_COUNT = 16, +}; + +#endif /* IG3RDMA_HW_H*/ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs.h b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs.h new file mode 100644 index 000000000..35972c3aa --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs.h @@ -0,0 +1,64285 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (C) 2019 Intel Corporation */ + +#ifndef IG3RDMA_REGS_H +#define IG3RDMA_REGS_H + +#include "irdma.h" + +#define IG3_CPUW_GLPE_CONFIGPKT_LIMIT 0x4200D7AC +#define IG3_CPUW_GLPE_CONFIGPKT_LIMIT_RSVD0_S 6 +#define IG3_CPUW_GLPE_CONFIGPKT_LIMIT_RSVD0_M RDMA_MASK3(32, 0x3FFFFFF, IG3_CPUW_GLPE_CONFIGPKT_LIMIT_RSVD0_S) +#define IG3_CPUW_GLPE_CONFIGPKT_LIMIT_PECONFIGPKTLIMIT_S 0 +#define IG3_CPUW_GLPE_CONFIGPKT_LIMIT_PECONFIGPKTLIMIT_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_CONFIGPKT_LIMIT_PECONFIGPKTLIMIT_S) +#define IG3_CPUW_GLPE_CPUGP(_i) 0x4200D020 + ((_i) * 4) /* _i=0...383 */ +#define IG3_CPUW_GLPE_CPUGP_MAX_INDEX_I 383 +#define IG3_CPUW_GLPE_CPUGP_PECPUGP_S 0 +#define IG3_CPUW_GLPE_CPUGP_PECPUGP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUGP_PECPUGP_S) +#define IG3_CPUW_GLPE_CPUSTATUS0 0x4200D620 +#define IG4_CPUW_GLPE_CPUSTATUS0 0x4201A6A0 +#define IG3_CPUW_GLPE_CPUSTATUS0_PECPUSTATUS0_S 0 +#define IG3_CPUW_GLPE_CPUSTATUS0_PECPUSTATUS0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUSTATUS0_PECPUSTATUS0_S) +#define IG3_CPUW_GLPE_CPUSTATUS1 0x4200D624 +#define IG4_CPUW_GLPE_CPUSTATUS1 0x4201A6A4 +#define IG3_CPUW_GLPE_CPUSTATUS1_PECPUSTATUS1_S 0 +#define IG3_CPUW_GLPE_CPUSTATUS1_PECPUSTATUS1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUSTATUS1_PECPUSTATUS1_S) +#define IG3_CPUW_GLPE_CPUSTATUS2 0x4200D628 +#define IG4_CPUW_GLPE_CPUSTATUS2 0x4201A6A8 +#define IG3_CPUW_GLPE_CPUSTATUS2_PECPUSTATUS2_S 0 +#define IG3_CPUW_GLPE_CPUSTATUS2_PECPUSTATUS2_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUSTATUS2_PECPUSTATUS2_S) +#define IG3_CPUW_GLPE_CPUTRIG0 0x4200D62C +#define IG3_CPUW_GLPE_CPUTRIG0_RSVD1_S 20 +#define IG3_CPUW_GLPE_CPUTRIG0_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUTRIG0_RSVD1_S) +#define IG3_CPUW_GLPE_CPUTRIG0_IMC_REQUEST0_S 19 +#define IG3_CPUW_GLPE_CPUTRIG0_IMC_REQUEST0_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG0_IMC_REQUEST0_S) +#define IG3_CPUW_GLPE_CPUTRIG0_OOP_REQUEST0_S 18 +#define IG3_CPUW_GLPE_CPUTRIG0_OOP_REQUEST0_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG0_OOP_REQUEST0_S) +#define IG3_CPUW_GLPE_CPUTRIG0_TEP_REQUEST0_S 17 +#define IG3_CPUW_GLPE_CPUTRIG0_TEP_REQUEST0_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG0_TEP_REQUEST0_S) +#define IG3_CPUW_GLPE_CPUTRIG0_RSVD0_S 16 +#define IG3_CPUW_GLPE_CPUTRIG0_RSVD0_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG0_RSVD0_S) +#define IG3_CPUW_GLPE_CPUTRIG0_PECPUTRIG0_S 0 +#define IG3_CPUW_GLPE_CPUTRIG0_PECPUTRIG0_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_GLPE_CPUTRIG0_PECPUTRIG0_S) +#define IG3_CPUW_GLPE_CPUTRIG1 0x4200D630 +#define IG3_CPUW_GLPE_CPUTRIG1_RSVD1_S 20 +#define IG3_CPUW_GLPE_CPUTRIG1_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUTRIG1_RSVD1_S) +#define IG3_CPUW_GLPE_CPUTRIG1_IMC_REQUEST1_S 19 +#define IG3_CPUW_GLPE_CPUTRIG1_IMC_REQUEST1_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG1_IMC_REQUEST1_S) +#define IG3_CPUW_GLPE_CPUTRIG1_OOP_REQUEST1_S 18 +#define IG3_CPUW_GLPE_CPUTRIG1_OOP_REQUEST1_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG1_OOP_REQUEST1_S) +#define IG3_CPUW_GLPE_CPUTRIG1_RSVD0_S 17 +#define IG3_CPUW_GLPE_CPUTRIG1_RSVD0_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG1_RSVD0_S) +#define IG3_CPUW_GLPE_CPUTRIG1_CQP_REQUEST1_S 16 +#define IG3_CPUW_GLPE_CPUTRIG1_CQP_REQUEST1_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG1_CQP_REQUEST1_S) +#define IG3_CPUW_GLPE_CPUTRIG1_PECPUTRIG1_S 0 +#define IG3_CPUW_GLPE_CPUTRIG1_PECPUTRIG1_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_GLPE_CPUTRIG1_PECPUTRIG1_S) +#define IG3_CPUW_GLPE_CPUTRIG2 0x4200D634 +#define IG3_CPUW_GLPE_CPUTRIG2_RSVD1_S 20 +#define IG3_CPUW_GLPE_CPUTRIG2_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUTRIG2_RSVD1_S) +#define IG3_CPUW_GLPE_CPUTRIG2_IMC_REQUEST2_S 19 +#define IG3_CPUW_GLPE_CPUTRIG2_IMC_REQUEST2_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG2_IMC_REQUEST2_S) +#define IG3_CPUW_GLPE_CPUTRIG2_RSVD0_S 18 +#define IG3_CPUW_GLPE_CPUTRIG2_RSVD0_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG2_RSVD0_S) +#define IG3_CPUW_GLPE_CPUTRIG2_TEP_REQUEST2_S 17 +#define IG3_CPUW_GLPE_CPUTRIG2_TEP_REQUEST2_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG2_TEP_REQUEST2_S) +#define IG3_CPUW_GLPE_CPUTRIG2_CQP_REQUEST2_S 16 +#define IG3_CPUW_GLPE_CPUTRIG2_CQP_REQUEST2_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUTRIG2_CQP_REQUEST2_S) +#define IG3_CPUW_GLPE_CPUTRIG2_PECPUTRIG2_S 0 +#define IG3_CPUW_GLPE_CPUTRIG2_PECPUTRIG2_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_GLPE_CPUTRIG2_PECPUTRIG2_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_COUNT 0x4200D838 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_CMD 0x4200D84C +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_DATA_H 0x4200D858 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_DATA_L 0x4200D854 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_PTR 0x4200D850 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_CMD 0x4200D83C +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_DATA_H 0x4200D848 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_DATA_L 0x4200D844 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_PTR 0x4200D840 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CPUW_GLPE_CPUW_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL 0x4200D800 +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD1_S 25 +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD2_S 17 +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD2_S) +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD3_S 9 +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD3_S) +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_BYPASS_S 8 +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_CONTROL_BYPASS_S) +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD4_S 1 +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CPUW_DTM_CONTROL_RSVD4_S) +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_CONTROL_LOCAL_EN_S) +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_COR_ERR 0x4200D868 +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CPUW_GLPE_CPUW_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUW_DTM_ECC_COR_ERR_CNT_S) +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_UNCOR_ERR 0x4200D864 +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CPUW_GLPE_CPUW_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUW_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG 0x4200D80C +#define IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CPUW_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG 0x4200D810 +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG_MODE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CPUW_DTM_LOG_CFG_MODE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_MASK 0x4200D818 +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_MASK_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_LOG_MASK_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_PATTERN 0x4200D814 +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_LOG_PATTERN_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG 0x4200D804 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_RSVD3_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS 0x4200D808 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_RSVD2_S) +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TIMESTAMP 0x4200D830 +#define IG3_CPUW_GLPE_CPUW_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_TIMESTAMP_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TIMESTAMP_ROLLOVER 0x4200D834 +#define IG3_CPUW_GLPE_CPUW_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG 0x4200D85C +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS 0x4200D860 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPUW_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG 0x4200D81C +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_MODE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_CPUW_DTM_TRIG_CFG_MODE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_COUNT 0x4200D828 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_TRIG_COUNT_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_MASK 0x4200D824 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_TRIG_MASK_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_PATTERN 0x4200D820 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_TIMESTAMP 0x4200D82C +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_CPUW_GLPE_CPUW_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_CPUW_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_CPUW_GLPE_CPUW_ECC_COR_ERR 0x4200D8BC +#define IG3_CPUW_GLPE_CPUW_ECC_COR_ERR_RSVD_S 12 +#define IG3_CPUW_GLPE_CPUW_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CPUW_GLPE_CPUW_ECC_COR_ERR_RSVD_S) +#define IG3_CPUW_GLPE_CPUW_ECC_COR_ERR_CNT_S 0 +#define IG3_CPUW_GLPE_CPUW_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUW_ECC_COR_ERR_CNT_S) +#define IG3_CPUW_GLPE_CPUW_ECC_UNCOR_ERR 0x4200D8B8 +#define IG3_CPUW_GLPE_CPUW_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CPUW_GLPE_CPUW_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CPUW_GLPE_CPUW_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CPUW_GLPE_CPUW_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CPUW_GLPE_CPUW_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_CPUW_ECC_UNCOR_ERR_CNT_S) +#define IG3_CPUW_GLPE_CPUW_FLR_TXCMP_MKR_CNT 0x4200D7D8 +#define IG3_CPUW_GLPE_CPUW_FLR_TXCMP_MKR_CNT_RSVD_S 6 +#define IG3_CPUW_GLPE_CPUW_FLR_TXCMP_MKR_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_CPUW_GLPE_CPUW_FLR_TXCMP_MKR_CNT_RSVD_S) +#define IG3_CPUW_GLPE_CPUW_FLR_TXCMP_MKR_CNT_MKR_CNT_S 0 +#define IG3_CPUW_GLPE_CPUW_FLR_TXCMP_MKR_CNT_MKR_CNT_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_CPUW_FLR_TXCMP_MKR_CNT_MKR_CNT_S) +#define IG3_CPUW_GLPE_CPU_CONFIG 0x4200D7B4 +#define IG3_CPUW_GLPE_CPU_CONFIG_RSVD_S 1 +#define IG3_CPUW_GLPE_CPU_CONFIG_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CPUW_GLPE_CPU_CONFIG_RSVD_S) +#define IG3_CPUW_GLPE_CPU_CONFIG_PRIVILEGED_S 0 +#define IG3_CPUW_GLPE_CPU_CONFIG_PRIVILEGED_M RDMA_BIT2(32, IG3_CPUW_GLPE_CPU_CONFIG_PRIVILEGED_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG 0x4200D880 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD3_S 20 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD3_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RM_S 16 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RM_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD2_S 14 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RME_S 12 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RME_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD1_S 10 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ERR_CNT_S 9 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ERR_CNT_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_FIX_CNT_S 8 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_FIX_CNT_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD0_S 6 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_RSVD0_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_MASK_INT_S 5 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_MASK_INT_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_LS_BYPASS_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_LS_FORCE_S 3 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_LS_FORCE_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_EN_S 0 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_CFG_ECC_EN_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS 0x4200D884 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_RSVD1_S 30 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_RSVD0_S 4 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_INIT_DONE_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_ECC_FIX_S) +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_DRAM_MEM_STATUS_ECC_ERR_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG 0x4200D888 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD3_S 20 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD3_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RM_S 16 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RM_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD2_S 14 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RME_S 12 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RME_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD1_S 10 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ERR_CNT_S 9 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ERR_CNT_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_FIX_CNT_S 8 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_FIX_CNT_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD0_S 6 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_RSVD0_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_MASK_INT_S 5 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_MASK_INT_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_LS_BYPASS_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_LS_FORCE_S 3 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_LS_FORCE_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_EN_S 0 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_CFG_ECC_EN_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS 0x4200D88C +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_RSVD1_S 30 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_RSVD0_S 4 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_INIT_DONE_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_ECC_FIX_S) +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CPUW_GLPE_CQP_IRAM_MEM_STATUS_ECC_ERR_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG 0x4200D8B0 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD3_S 20 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD3_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RM_S 16 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RM_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD2_S 14 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RME_S 12 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RME_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD1_S 10 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ERR_CNT_S 9 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ERR_CNT_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_FIX_CNT_S 8 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_FIX_CNT_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD0_S 6 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_RSVD0_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_MASK_INT_S 5 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_MASK_INT_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_LS_BYPASS_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_LS_FORCE_S 3 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_LS_FORCE_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_EN_S 0 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_CFG_ECC_EN_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS 0x4200D8B4 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_RSVD1_S 30 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_RSVD0_S 4 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_INIT_DONE_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_ECC_FIX_S) +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CPUW_GLPE_CSR_RAM_MEM_STATUS_ECC_ERR_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_CNT 0x4200D7BC +#define IG3_CPUW_GLPE_DRAIN_MARKER_CNT_RSVD_S 8 +#define IG3_CPUW_GLPE_DRAIN_MARKER_CNT_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CPUW_GLPE_DRAIN_MARKER_CNT_RSVD_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_CNT_COUNT_S 0 +#define IG3_CPUW_GLPE_DRAIN_MARKER_CNT_COUNT_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_DRAIN_MARKER_CNT_COUNT_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG 0x4200D7B8 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_RSVD1_S 16 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_RSVD1_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_FUNCTION_VALID_S 15 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_FUNCTION_VALID_M RDMA_BIT2(32, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_FUNCTION_VALID_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_HOST_S 12 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_HOST_M RDMA_MASK3(32, 0x7, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_HOST_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_SRC_PE_DEST_PE_S 10 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_SRC_PE_DEST_PE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_SRC_PE_DEST_PE_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_PORT_ID_S 8 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_PORT_ID_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_PORT_ID_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_TRAFFIC_CLASS_S 5 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_TRAFFIC_CLASS_M RDMA_MASK3(32, 0x7, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_TRAFFIC_CLASS_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_PKT_TYPE_S 3 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_PKT_TYPE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_PKT_TYPE_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_CONTROL_COMMAND_S 2 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_CONTROL_COMMAND_M RDMA_BIT2(32, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_CONTROL_COMMAND_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_LOOPBACK_S 1 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_LOOPBACK_M RDMA_BIT2(32, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_LOOPBACK_S) +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_DIRECTION_S 0 +#define IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_DIRECTION_M RDMA_BIT2(32, IG3_CPUW_GLPE_DRAIN_MARKER_TRIG_DIRECTION_S) +#define IG3_CPUW_GLPE_FWLD_DATA(_i) 0x4200D648 + ((_i) * 4) /* _i=0...63 */ +#define IG3_CPUW_GLPE_FWLD_DATA_MAX_INDEX_I 63 +#define IG3_CPUW_GLPE_FWLD_DATA_DATA_S 0 +#define IG3_CPUW_GLPE_FWLD_DATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_FWLD_DATA_DATA_S) +#define IG3_CPUW_GLPE_FWLD_DATA_LEGACY 0x4200D748 +#define IG3_CPUW_GLPE_FWLD_DATA_LEGACY_DATA_S 0 +#define IG3_CPUW_GLPE_FWLD_DATA_LEGACY_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_FWLD_DATA_LEGACY_DATA_S) +#define IG3_CPUW_GLPE_FWLD_ENABLE 0x4200D644 +#define IG3_CPUW_GLPE_FWLD_ENABLE_RSVD0_S 1 +#define IG3_CPUW_GLPE_FWLD_ENABLE_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CPUW_GLPE_FWLD_ENABLE_RSVD0_S) +#define IG3_CPUW_GLPE_FWLD_ENABLE_CPU_ENABLE_S 0 +#define IG3_CPUW_GLPE_FWLD_ENABLE_CPU_ENABLE_M RDMA_BIT2(32, IG3_CPUW_GLPE_FWLD_ENABLE_CPU_ENABLE_S) +#define IG3_CPUW_GLPE_FWLD_STATUS 0x4200D640 +#define IG3_CPUW_GLPE_FWLD_STATUS_RSVD0_S 2 +#define IG3_CPUW_GLPE_FWLD_STATUS_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CPUW_GLPE_FWLD_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_FWLD_STATUS_DONE_S 1 +#define IG3_CPUW_GLPE_FWLD_STATUS_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_FWLD_STATUS_DONE_S) +#define IG3_CPUW_GLPE_FWLD_STATUS_AUTOLOAD_REQUESTED_S 0 +#define IG3_CPUW_GLPE_FWLD_STATUS_AUTOLOAD_REQUESTED_M RDMA_BIT2(32, IG3_CPUW_GLPE_FWLD_STATUS_AUTOLOAD_REQUESTED_S) +#define IG3_CPUW_GLPE_FW_PRODUCT_ID 0x4200D638 +#define IG3_CPUW_GLPE_FW_PRODUCT_ID_PROD_ID_S 0 +#define IG3_CPUW_GLPE_FW_PRODUCT_ID_PROD_ID_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_FW_PRODUCT_ID_PROD_ID_S) +#define IG3_CPUW_GLPE_FW_REV 0x4200D63C +#define IG3_CPUW_GLPE_FW_REV_MAJOR_REV_S 16 +#define IG3_CPUW_GLPE_FW_REV_MAJOR_REV_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_GLPE_FW_REV_MAJOR_REV_S) +#define IG3_CPUW_GLPE_FW_REV_MINOR_REV_S 0 +#define IG3_CPUW_GLPE_FW_REV_MINOR_REV_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_GLPE_FW_REV_MINOR_REV_S) +#define IG3_CPUW_GLPE_IMCREQ(_i) 0x4200D74C + ((_i) * 4) /* _i=0...7 */ +#define IG3_CPUW_GLPE_IMCREQ_MAX_INDEX_I 7 +#define IG3_CPUW_GLPE_IMCREQ_PE_IMCREQ_DATA_S 0 +#define IG3_CPUW_GLPE_IMCREQ_PE_IMCREQ_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_IMCREQ_PE_IMCREQ_DATA_S) +#define IG3_CPUW_GLPE_IMCRESP(_i) 0x4200D76C + ((_i) * 4) /* _i=0...15 */ +#define IG3_CPUW_GLPE_IMCRESP_MAX_INDEX_I 15 +#define IG3_CPUW_GLPE_IMCRESP_PE_IMCRESP_DATA_S 0 +#define IG3_CPUW_GLPE_IMCRESP_PE_IMCRESP_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_GLPE_IMCRESP_PE_IMCRESP_DATA_S) +#define IG3_CPUW_GLPE_IPF_CONFIG 0x4200D7B0 +#define IG3_CPUW_GLPE_IPF_CONFIG_RSVD_S 6 +#define IG3_CPUW_GLPE_IPF_CONFIG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_CPUW_GLPE_IPF_CONFIG_RSVD_S) +#define IG3_CPUW_GLPE_IPF_CONFIG_IPF_PF_NUM_S 0 +#define IG3_CPUW_GLPE_IPF_CONFIG_IPF_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_IPF_CONFIG_IPF_PF_NUM_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG 0x4200D8A0 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD3_S 20 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD3_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RM_S 16 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RM_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD2_S 14 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RME_S 12 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RME_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD1_S 10 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ERR_CNT_S 9 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ERR_CNT_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_FIX_CNT_S 8 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_FIX_CNT_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD0_S 6 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_RSVD0_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_MASK_INT_S 5 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_MASK_INT_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_LS_BYPASS_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_LS_FORCE_S 3 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_LS_FORCE_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_EN_S 0 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_CFG_ECC_EN_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS 0x4200D8A4 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_RSVD1_S 30 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_RSVD0_S 4 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_INIT_DONE_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_ECC_FIX_S) +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_DRAM_MEM_STATUS_ECC_ERR_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG 0x4200D8A8 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD3_S 20 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD3_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RM_S 16 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RM_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD2_S 14 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RME_S 12 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RME_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD1_S 10 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ERR_CNT_S 9 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ERR_CNT_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_FIX_CNT_S 8 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_FIX_CNT_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD0_S 6 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_RSVD0_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_MASK_INT_S 5 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_MASK_INT_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_LS_BYPASS_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_LS_FORCE_S 3 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_LS_FORCE_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_EN_S 0 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_CFG_ECC_EN_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS 0x4200D8AC +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_RSVD1_S 30 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_RSVD0_S 4 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_INIT_DONE_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_ECC_FIX_S) +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CPUW_GLPE_OOP_IRAM_MEM_STATUS_ECC_ERR_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG 0x4200D890 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD3_S 20 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD3_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RM_S 16 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RM_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD2_S 14 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RME_S 12 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RME_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD1_S 10 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ERR_CNT_S 9 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ERR_CNT_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_FIX_CNT_S 8 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_FIX_CNT_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD0_S 6 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_RSVD0_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_MASK_INT_S 5 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_MASK_INT_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_LS_BYPASS_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_LS_FORCE_S 3 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_LS_FORCE_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_EN_S 0 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_CFG_ECC_EN_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS 0x4200D894 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_RSVD1_S 30 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_RSVD0_S 4 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_INIT_DONE_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_ECC_FIX_S) +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_DRAM_MEM_STATUS_ECC_ERR_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG 0x4200D898 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD3_S 20 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD3_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RM_S 16 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RM_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD2_S 14 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD2_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RME_S 12 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RME_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD1_S 10 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD1_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ERR_CNT_S 9 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ERR_CNT_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_FIX_CNT_S 8 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_FIX_CNT_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD0_S 6 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_RSVD0_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_MASK_INT_S 5 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_MASK_INT_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_LS_BYPASS_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_LS_FORCE_S 3 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_LS_FORCE_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_EN_S 0 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_CFG_ECC_EN_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS 0x4200D89C +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_RSVD1_S 30 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_RSVD0_S 4 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_INIT_DONE_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_ECC_FIX_S) +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CPUW_GLPE_TEP_IRAM_MEM_STATUS_ECC_ERR_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS 0x4200D7CC +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_DONE_S 31 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_DONE_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_RSVD1_S 27 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_RSVD1_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_PORT_NUM_S 24 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_PORT_NUM_M RDMA_MASK3(32, 0x7, IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_PORT_NUM_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_RSVD0_S 20 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_RSVD0_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_FUNC_TYPE_S 18 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_FUNC_TYPE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_FUNC_TYPE_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_FUNC_NUM_S 6 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_FUNC_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_FUNC_NUM_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_PHY_FUNC_S 0 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_PHY_FUNC_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_XLR_CLNCACHE_STATUS_PHY_FUNC_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG 0x4200D7C8 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_BUSY_S 31 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_BUSY_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_BUSY_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_RSVD1_S 27 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_RSVD1_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_PORT_NUM_S 24 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_PORT_NUM_M RDMA_MASK3(32, 0x7, IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_PORT_NUM_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_RSVD0_S 20 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_RSVD0_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_RSVD0_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_FUNC_TYPE_S 18 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_FUNC_TYPE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_FUNC_TYPE_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_FUNC_NUM_S 6 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_FUNC_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_FUNC_NUM_S) +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_PHY_FUNC_S 0 +#define IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_PHY_FUNC_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_XLR_CLNCACHE_TRIG_PHY_FUNC_S) +#define IG3_CPUW_GLPE_XLR_OOP_REQ 0x4200D7E0 +#define IG3_CPUW_GLPE_XLR_OOP_REQ_BUSY_S 31 +#define IG3_CPUW_GLPE_XLR_OOP_REQ_BUSY_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_OOP_REQ_BUSY_S) +#define IG3_CPUW_GLPE_XLR_OOP_REQ_OP_S 30 +#define IG3_CPUW_GLPE_XLR_OOP_REQ_OP_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_OOP_REQ_OP_S) +#define IG3_CPUW_GLPE_XLR_OOP_REQ_RSVD_S 20 +#define IG3_CPUW_GLPE_XLR_OOP_REQ_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_CPUW_GLPE_XLR_OOP_REQ_RSVD_S) +#define IG3_CPUW_GLPE_XLR_OOP_REQ_VDEV_VF_TYPE_S 18 +#define IG3_CPUW_GLPE_XLR_OOP_REQ_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_XLR_OOP_REQ_VDEV_VF_TYPE_S) +#define IG3_CPUW_GLPE_XLR_OOP_REQ_VDEV_VF_NUM_S 6 +#define IG3_CPUW_GLPE_XLR_OOP_REQ_VDEV_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_XLR_OOP_REQ_VDEV_VF_NUM_S) +#define IG3_CPUW_GLPE_XLR_OOP_REQ_PF_NUM_S 0 +#define IG3_CPUW_GLPE_XLR_OOP_REQ_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_XLR_OOP_REQ_PF_NUM_S) +#define IG3_CPUW_GLPE_XLR_POST 0x4200D7D0 +#define IG3_CPUW_GLPE_XLR_POST_BUSY_S 31 +#define IG3_CPUW_GLPE_XLR_POST_BUSY_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_POST_BUSY_S) +#define IG3_CPUW_GLPE_XLR_POST_RSVD1_S 27 +#define IG3_CPUW_GLPE_XLR_POST_RSVD1_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_POST_RSVD1_S) +#define IG3_CPUW_GLPE_XLR_POST_PORT_NUM_S 24 +#define IG3_CPUW_GLPE_XLR_POST_PORT_NUM_M RDMA_MASK3(32, 0x7, IG3_CPUW_GLPE_XLR_POST_PORT_NUM_S) +#define IG3_CPUW_GLPE_XLR_POST_RSVD0_S 20 +#define IG3_CPUW_GLPE_XLR_POST_RSVD0_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_POST_RSVD0_S) +#define IG3_CPUW_GLPE_XLR_POST_FUNC_TYPE_S 18 +#define IG3_CPUW_GLPE_XLR_POST_FUNC_TYPE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_XLR_POST_FUNC_TYPE_S) +#define IG3_CPUW_GLPE_XLR_POST_FUNC_NUM_S 6 +#define IG3_CPUW_GLPE_XLR_POST_FUNC_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_XLR_POST_FUNC_NUM_S) +#define IG3_CPUW_GLPE_XLR_POST_PHY_FUNC_S 0 +#define IG3_CPUW_GLPE_XLR_POST_PHY_FUNC_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_XLR_POST_PHY_FUNC_S) +#define IG3_CPUW_GLPE_XLR_POST_STATUS 0x4200D7D4 +#define IG3_CPUW_GLPE_XLR_POST_STATUS_DONE_S 31 +#define IG3_CPUW_GLPE_XLR_POST_STATUS_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_POST_STATUS_DONE_S) +#define IG3_CPUW_GLPE_XLR_POST_STATUS_RSVD1_S 27 +#define IG3_CPUW_GLPE_XLR_POST_STATUS_RSVD1_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_POST_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_XLR_POST_STATUS_PORT_NUM_S 24 +#define IG3_CPUW_GLPE_XLR_POST_STATUS_PORT_NUM_M RDMA_MASK3(32, 0x7, IG3_CPUW_GLPE_XLR_POST_STATUS_PORT_NUM_S) +#define IG3_CPUW_GLPE_XLR_POST_STATUS_RSVD0_S 20 +#define IG3_CPUW_GLPE_XLR_POST_STATUS_RSVD0_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_POST_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_XLR_POST_STATUS_FUNC_TYPE_S 18 +#define IG3_CPUW_GLPE_XLR_POST_STATUS_FUNC_TYPE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_XLR_POST_STATUS_FUNC_TYPE_S) +#define IG3_CPUW_GLPE_XLR_POST_STATUS_FUNC_NUM_S 6 +#define IG3_CPUW_GLPE_XLR_POST_STATUS_FUNC_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_XLR_POST_STATUS_FUNC_NUM_S) +#define IG3_CPUW_GLPE_XLR_POST_STATUS_PHY_FUNC_S 0 +#define IG3_CPUW_GLPE_XLR_POST_STATUS_PHY_FUNC_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_XLR_POST_STATUS_PHY_FUNC_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC 0x4200D7C0 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_BUSY_S 31 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_BUSY_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_STP_FUNC_BUSY_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_RSVD1_S 27 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_RSVD1_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_STP_FUNC_RSVD1_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_PORT_NUM_S 24 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_PORT_NUM_M RDMA_MASK3(32, 0x7, IG3_CPUW_GLPE_XLR_STP_FUNC_PORT_NUM_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_RSVD0_S 20 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_RSVD0_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_STP_FUNC_RSVD0_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_FUNC_TYPE_S 18 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_FUNC_TYPE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_XLR_STP_FUNC_FUNC_TYPE_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_FUNC_NUM_S 6 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_FUNC_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_XLR_STP_FUNC_FUNC_NUM_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_PHY_FUNC_S 0 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_PHY_FUNC_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_XLR_STP_FUNC_PHY_FUNC_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS 0x4200D7C4 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_DONE_S 31 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_DONE_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_DONE_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_RSVD1_S 27 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_RSVD1_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_RSVD1_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_PORT_NUM_S 24 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_PORT_NUM_M RDMA_MASK3(32, 0x7, IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_PORT_NUM_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_RSVD0_S 20 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_RSVD0_M RDMA_MASK3(32, 0xF, IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_RSVD0_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_FUNC_TYPE_S 18 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_FUNC_TYPE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_FUNC_TYPE_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_FUNC_NUM_S 6 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_FUNC_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_FUNC_NUM_S) +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_PHY_FUNC_S 0 +#define IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_PHY_FUNC_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_XLR_STP_FUNC_STATUS_PHY_FUNC_S) +#define IG3_CPUW_GLPE_XLR_TEP_REQ 0x4200D7DC +#define IG3_CPUW_GLPE_XLR_TEP_REQ_BUSY_S 31 +#define IG3_CPUW_GLPE_XLR_TEP_REQ_BUSY_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_TEP_REQ_BUSY_S) +#define IG3_CPUW_GLPE_XLR_TEP_REQ_OP_S 30 +#define IG3_CPUW_GLPE_XLR_TEP_REQ_OP_M RDMA_BIT2(32, IG3_CPUW_GLPE_XLR_TEP_REQ_OP_S) +#define IG3_CPUW_GLPE_XLR_TEP_REQ_RSVD_S 20 +#define IG3_CPUW_GLPE_XLR_TEP_REQ_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_CPUW_GLPE_XLR_TEP_REQ_RSVD_S) +#define IG3_CPUW_GLPE_XLR_TEP_REQ_VDEV_VF_TYPE_S 18 +#define IG3_CPUW_GLPE_XLR_TEP_REQ_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CPUW_GLPE_XLR_TEP_REQ_VDEV_VF_TYPE_S) +#define IG3_CPUW_GLPE_XLR_TEP_REQ_VDEV_VF_NUM_S 6 +#define IG3_CPUW_GLPE_XLR_TEP_REQ_VDEV_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_GLPE_XLR_TEP_REQ_VDEV_VF_NUM_S) +#define IG3_CPUW_GLPE_XLR_TEP_REQ_PF_NUM_S 0 +#define IG3_CPUW_GLPE_XLR_TEP_REQ_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_CPUW_GLPE_XLR_TEP_REQ_PF_NUM_S) +#define IG3_CPUW_PMFPE_CCQPEXTSTATUS(_i) 0x42002000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CPUW_PMFPE_CCQPEXTSTATUS_MAX_INDEX_I 1031 +#define IG3_CPUW_PMFPE_CCQPEXTSTATUS_RSVD_S 16 +#define IG3_CPUW_PMFPE_CCQPEXTSTATUS_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_PMFPE_CCQPEXTSTATUS_RSVD_S) +#define IG3_CPUW_PMFPE_CCQPEXTSTATUS_DBPT_INDEX_S 0 +#define IG3_CPUW_PMFPE_CCQPEXTSTATUS_DBPT_INDEX_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_PMFPE_CCQPEXTSTATUS_DBPT_INDEX_S) +#define IG3_CPUW_PMFPE_CCQPHIGH(_i) 0x42006000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CPUW_PMFPE_CCQPHIGH_MAX_INDEX_I 1031 +#define IG3_CPUW_PMFPE_CCQPHIGH_PECCQPHIGH_S 0 +#define IG3_CPUW_PMFPE_CCQPHIGH_PECCQPHIGH_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_PMFPE_CCQPHIGH_PECCQPHIGH_S) +#define IG3_CPUW_PMFPE_CCQPLOW(_i) 0x42004000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CPUW_PMFPE_CCQPLOW_MAX_INDEX_I 1031 +#define IG3_CPUW_PMFPE_CCQPLOW_PECCQPLOW_S 0 +#define IG3_CPUW_PMFPE_CCQPLOW_PECCQPLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CPUW_PMFPE_CCQPLOW_PECCQPLOW_S) +#define IG3_CPUW_PMFPE_CCQPSTATUS(_i) 0x42000000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CPUW_PMFPE_CCQPSTATUS_MAX_INDEX_I 1031 +#define IG3_CPUW_PMFPE_CCQPSTATUS_CCQP_ERR_S 31 +#define IG3_CPUW_PMFPE_CCQPSTATUS_CCQP_ERR_M RDMA_BIT2(32, IG3_CPUW_PMFPE_CCQPSTATUS_CCQP_ERR_S) +#define IG3_CPUW_PMFPE_CCQPSTATUS_RSVD2_S 28 +#define IG3_CPUW_PMFPE_CCQPSTATUS_RSVD2_M RDMA_MASK3(32, 0x7, IG3_CPUW_PMFPE_CCQPSTATUS_RSVD2_S) +#define IG3_CPUW_PMFPE_CCQPSTATUS_RDMA_EN_VFS_S 16 +#define IG3_CPUW_PMFPE_CCQPSTATUS_RDMA_EN_VFS_M RDMA_MASK3(32, 0xFFF, IG3_CPUW_PMFPE_CCQPSTATUS_RDMA_EN_VFS_S) +#define IG3_CPUW_PMFPE_CCQPSTATUS_RSVD1_S 7 +#define IG3_CPUW_PMFPE_CCQPSTATUS_RSVD1_M RDMA_MASK3(32, 0x1FF, IG3_CPUW_PMFPE_CCQPSTATUS_RSVD1_S) +#define IG3_CPUW_PMFPE_CCQPSTATUS_HMC_PROFILE_S 4 +#define IG3_CPUW_PMFPE_CCQPSTATUS_HMC_PROFILE_M RDMA_MASK3(32, 0x7, IG3_CPUW_PMFPE_CCQPSTATUS_HMC_PROFILE_S) +#define IG3_CPUW_PMFPE_CCQPSTATUS_RSVD0_S 1 +#define IG3_CPUW_PMFPE_CCQPSTATUS_RSVD0_M RDMA_MASK3(32, 0x7, IG3_CPUW_PMFPE_CCQPSTATUS_RSVD0_S) +#define IG3_CPUW_PMFPE_CCQPSTATUS_CCQP_DONE_S 0 +#define IG3_CPUW_PMFPE_CCQPSTATUS_CCQP_DONE_M RDMA_BIT2(32, IG3_CPUW_PMFPE_CCQPSTATUS_CCQP_DONE_S) +#define IG3_CPUW_PMFPE_CQPDB(_i) 0x4200A000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CPUW_PMFPE_CQPDB_MAX_INDEX_I 1031 +#define IG3_CPUW_PMFPE_CQPDB_RSVD_S 11 +#define IG3_CPUW_PMFPE_CQPDB_RSVD_M RDMA_MASK3(32, 0x1FFFFF, IG3_CPUW_PMFPE_CQPDB_RSVD_S) +#define IG3_CPUW_PMFPE_CQPDB_WQHEAD_S 0 +#define IG3_CPUW_PMFPE_CQPDB_WQHEAD_M RDMA_MASK3(32, 0x7FF, IG3_CPUW_PMFPE_CQPDB_WQHEAD_S) +#define IG3_CPUW_PMFPE_CQPERRCODES(_i) 0x42008000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CPUW_PMFPE_CQPERRCODES_MAX_INDEX_I 1031 +#define IG3_CPUW_PMFPE_CQPERRCODES_CQP_MAJOR_CODE_S 16 +#define IG3_CPUW_PMFPE_CQPERRCODES_CQP_MAJOR_CODE_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_PMFPE_CQPERRCODES_CQP_MAJOR_CODE_S) +#define IG3_CPUW_PMFPE_CQPERRCODES_CQP_MINOR_CODE_S 0 +#define IG3_CPUW_PMFPE_CQPERRCODES_CQP_MINOR_CODE_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_PMFPE_CQPERRCODES_CQP_MINOR_CODE_S) +#define IG3_CPUW_PMFPE_CQPTAIL(_i) (0x4200C000 + ((_i) * 4)) /* _i=0...1031 */ +#define IG4_CPUW_PMFPE_CQPTAIL(_i) (0x42018000 + ((_i) * 4)) /* _i=0...1031 */ +#define IG3_CPUW_PMFPE_CQPTAIL_MAX_INDEX_I 1031 +#define IG3_CPUW_PMFPE_CQPTAIL_CQP_OP_ERR_S 31 +#define IG3_CPUW_PMFPE_CQPTAIL_CQP_OP_ERR_M RDMA_BIT2(32, IG3_CPUW_PMFPE_CQPTAIL_CQP_OP_ERR_S) +#define IG3_CPUW_PMFPE_CQPTAIL_RSVD_S 11 +#define IG3_CPUW_PMFPE_CQPTAIL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CPUW_PMFPE_CQPTAIL_RSVD_S) +#define IG3_CPUW_PMFPE_CQPTAIL_WQTAIL_S 0 +#define IG3_CPUW_PMFPE_CQPTAIL_WQTAIL_M RDMA_MASK3(32, 0x7FF, IG3_CPUW_PMFPE_CQPTAIL_WQTAIL_S) +#define IG3_CPUW_RDMA_FUSE 0x4200D7E4 +#define IG3_CPUW_RDMA_FUSE_RSVD_S 16 +#define IG3_CPUW_RDMA_FUSE_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CPUW_RDMA_FUSE_RSVD_S) +#define IG3_CPUW_RDMA_FUSE_RDMA_ASO_ENABLE_S 8 +#define IG3_CPUW_RDMA_FUSE_RDMA_ASO_ENABLE_M RDMA_MASK3(32, 0xFF, IG3_CPUW_RDMA_FUSE_RDMA_ASO_ENABLE_S) +#define IG3_CPUW_RDMA_FUSE_RDMA_RESERVED_S 7 +#define IG3_CPUW_RDMA_FUSE_RDMA_RESERVED_M RDMA_BIT2(32, IG3_CPUW_RDMA_FUSE_RDMA_RESERVED_S) +#define IG3_CPUW_RDMA_FUSE_RDMA_SWFWLD_DISABLE_S 6 +#define IG3_CPUW_RDMA_FUSE_RDMA_SWFWLD_DISABLE_M RDMA_BIT2(32, IG3_CPUW_RDMA_FUSE_RDMA_SWFWLD_DISABLE_S) +#define IG3_CPUW_RDMA_FUSE_RDMA_CRT_DISABLE_S 5 +#define IG3_CPUW_RDMA_FUSE_RDMA_CRT_DISABLE_M RDMA_BIT2(32, IG3_CPUW_RDMA_FUSE_RDMA_CRT_DISABLE_S) +#define IG3_CPUW_RDMA_FUSE_RDMA_TILECLK_DISABLE_S 0 +#define IG3_CPUW_RDMA_FUSE_RDMA_TILECLK_DISABLE_M RDMA_MASK3(32, 0x1F, IG3_CPUW_RDMA_FUSE_RDMA_TILECLK_DISABLE_S) +#define IG3_FLM_GLHMC_PEOOISCFFLCNT_PE(_i) 0x42086000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_FLM_GLHMC_PEOOISCFFLCNT_PE_MAX_INDEX_I 1031 +#define IG3_FLM_GLHMC_PEOOISCFFLCNT_PE_RSVD_S 29 +#define IG3_FLM_GLHMC_PEOOISCFFLCNT_PE_RSVD_M RDMA_MASK3(32, 0x7, IG3_FLM_GLHMC_PEOOISCFFLCNT_PE_RSVD_S) +#define IG3_FLM_GLHMC_PEOOISCFFLCNT_PE_FPMPEOOISCFFLCNT_S 0 +#define IG3_FLM_GLHMC_PEOOISCFFLCNT_PE_FPMPEOOISCFFLCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_FLM_GLHMC_PEOOISCFFLCNT_PE_FPMPEOOISCFFLCNT_S) +#define IG3_FLM_GLHMC_PEQ1FLCNT_PE(_i) 0x42082000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_FLM_GLHMC_PEQ1FLCNT_PE_MAX_INDEX_I 1031 +#define IG3_FLM_GLHMC_PEQ1FLCNT_PE_RSVD_S 29 +#define IG3_FLM_GLHMC_PEQ1FLCNT_PE_RSVD_M RDMA_MASK3(32, 0x7, IG3_FLM_GLHMC_PEQ1FLCNT_PE_RSVD_S) +#define IG3_FLM_GLHMC_PEQ1FLCNT_PE_FPMPEQ1FLCNT_S 0 +#define IG3_FLM_GLHMC_PEQ1FLCNT_PE_FPMPEQ1FLCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_FLM_GLHMC_PEQ1FLCNT_PE_FPMPEQ1FLCNT_S) +#define IG3_FLM_GLHMC_PERRFFLCNT_PE(_i) 0x42084000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_FLM_GLHMC_PERRFFLCNT_PE_MAX_INDEX_I 1031 +#define IG3_FLM_GLHMC_PERRFFLCNT_PE_RSVD_S 29 +#define IG3_FLM_GLHMC_PERRFFLCNT_PE_RSVD_M RDMA_MASK3(32, 0x7, IG3_FLM_GLHMC_PERRFFLCNT_PE_RSVD_S) +#define IG3_FLM_GLHMC_PERRFFLCNT_PE_FPMPERRFFLCNT_S 0 +#define IG3_FLM_GLHMC_PERRFFLCNT_PE_FPMPERRFFLCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_FLM_GLHMC_PERRFFLCNT_PE_FPMPERRFFLCNT_S) +#define IG3_FLM_GLHMC_PEXFFLCNT_PE(_i) 0x42080000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_FLM_GLHMC_PEXFFLCNT_PE_MAX_INDEX_I 1031 +#define IG3_FLM_GLHMC_PEXFFLCNT_PE_RSVD_S 29 +#define IG3_FLM_GLHMC_PEXFFLCNT_PE_RSVD_M RDMA_MASK3(32, 0x7, IG3_FLM_GLHMC_PEXFFLCNT_PE_RSVD_S) +#define IG3_FLM_GLHMC_PEXFFLCNT_PE_FPMPEXFFLCNT_S 0 +#define IG3_FLM_GLHMC_PEXFFLCNT_PE_FPMPEXFFLCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_FLM_GLHMC_PEXFFLCNT_PE_FPMPEXFFLCNT_S) +#define IG3_FLM_GLPE_FLMCTRL0 0x42090000 +#define IG3_FLM_GLPE_FLMCTRL0_DISABLE_S 31 +#define IG3_FLM_GLPE_FLMCTRL0_DISABLE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLMCTRL0_DISABLE_S) +#define IG3_FLM_GLPE_FLMCTRL0_RSVD2_S 20 +#define IG3_FLM_GLPE_FLMCTRL0_RSVD2_M RDMA_MASK3(32, 0x7FF, IG3_FLM_GLPE_FLMCTRL0_RSVD2_S) +#define IG3_FLM_GLPE_FLMCTRL0_PMF_S 8 +#define IG3_FLM_GLPE_FLMCTRL0_PMF_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLMCTRL0_PMF_S) +#define IG3_FLM_GLPE_FLMCTRL0_RSVD1_S 6 +#define IG3_FLM_GLPE_FLMCTRL0_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLMCTRL0_RSVD1_S) +#define IG3_FLM_GLPE_FLMCTRL0_FLIST_S 4 +#define IG3_FLM_GLPE_FLMCTRL0_FLIST_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLMCTRL0_FLIST_S) +#define IG3_FLM_GLPE_FLMCTRL0_RSVD0_S 3 +#define IG3_FLM_GLPE_FLMCTRL0_RSVD0_M RDMA_BIT2(32, IG3_FLM_GLPE_FLMCTRL0_RSVD0_S) +#define IG3_FLM_GLPE_FLMCTRL0_OPCODE_S 0 +#define IG3_FLM_GLPE_FLMCTRL0_OPCODE_M RDMA_MASK3(32, 0x7, IG3_FLM_GLPE_FLMCTRL0_OPCODE_S) +#define IG3_FLM_GLPE_FLMCTRL1 0x42090004 +#define IG3_FLM_GLPE_FLMCTRL1_RSVD_S 20 +#define IG3_FLM_GLPE_FLMCTRL1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLMCTRL1_RSVD_S) +#define IG3_FLM_GLPE_FLMCTRL1_VDEV_VF_TYPE_S 18 +#define IG3_FLM_GLPE_FLMCTRL1_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLMCTRL1_VDEV_VF_TYPE_S) +#define IG3_FLM_GLPE_FLMCTRL1_VDEV_VF_NUM_S 6 +#define IG3_FLM_GLPE_FLMCTRL1_VDEV_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLMCTRL1_VDEV_VF_NUM_S) +#define IG3_FLM_GLPE_FLMCTRL1_PF_NUM_S 0 +#define IG3_FLM_GLPE_FLMCTRL1_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_FLM_GLPE_FLMCTRL1_PF_NUM_S) +#define IG3_FLM_GLPE_FLMPTR 0x4209000C +#define IG3_FLM_GLPE_FLMPTR_RSVD_S 28 +#define IG3_FLM_GLPE_FLMPTR_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLMPTR_RSVD_S) +#define IG3_FLM_GLPE_FLMPTR_PEFLMPTR_S 0 +#define IG3_FLM_GLPE_FLMPTR_PEFLMPTR_M RDMA_MASK3(32, 0xFFFFFFF, IG3_FLM_GLPE_FLMPTR_PEFLMPTR_S) +#define IG3_FLM_GLPE_FLMPTRHEAD 0x42090014 +#define IG3_FLM_GLPE_FLMPTRHEAD_RSVD_S 28 +#define IG3_FLM_GLPE_FLMPTRHEAD_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLMPTRHEAD_RSVD_S) +#define IG3_FLM_GLPE_FLMPTRHEAD_PTR_S 0 +#define IG3_FLM_GLPE_FLMPTRHEAD_PTR_M RDMA_MASK3(32, 0xFFFFFFF, IG3_FLM_GLPE_FLMPTRHEAD_PTR_S) +#define IG3_FLM_GLPE_FLMPTRHEADMAX 0x42090018 +#define IG3_FLM_GLPE_FLMPTRHEADMAX_RSVD_S 28 +#define IG3_FLM_GLPE_FLMPTRHEADMAX_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLMPTRHEADMAX_RSVD_S) +#define IG3_FLM_GLPE_FLMPTRHEADMAX_PTR_S 0 +#define IG3_FLM_GLPE_FLMPTRHEADMAX_PTR_M RDMA_MASK3(32, 0xFFFFFFF, IG3_FLM_GLPE_FLMPTRHEADMAX_PTR_S) +#define IG3_FLM_GLPE_FLMPTRTAIL 0x42090010 +#define IG3_FLM_GLPE_FLMPTRTAIL_RSVD_S 28 +#define IG3_FLM_GLPE_FLMPTRTAIL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLMPTRTAIL_RSVD_S) +#define IG3_FLM_GLPE_FLMPTRTAIL_PTR_S 0 +#define IG3_FLM_GLPE_FLMPTRTAIL_PTR_M RDMA_MASK3(32, 0xFFFFFFF, IG3_FLM_GLPE_FLMPTRTAIL_PTR_S) +#define IG3_FLM_GLPE_FLMSTATUS 0x42090008 +#define IG3_FLM_GLPE_FLMSTATUS_BUSY_S 31 +#define IG3_FLM_GLPE_FLMSTATUS_BUSY_M RDMA_BIT2(32, IG3_FLM_GLPE_FLMSTATUS_BUSY_S) +#define IG3_FLM_GLPE_FLMSTATUS_RSVD_S 4 +#define IG3_FLM_GLPE_FLMSTATUS_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_FLM_GLPE_FLMSTATUS_RSVD_S) +#define IG3_FLM_GLPE_FLMSTATUS_STATUS_S 0 +#define IG3_FLM_GLPE_FLMSTATUS_STATUS_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLMSTATUS_STATUS_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG 0x42090040 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD3_S 20 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD3_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RM_S 16 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RM_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD2_S 14 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD2_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RME_S 12 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RME_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD1_S 10 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_FIX_CNT_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD0_S 6 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_RSVD0_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_MASK_INT_S 5 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_MASK_INT_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_LS_BYPASS_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_LS_FORCE_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_EN_S 0 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_CFG_ECC_EN_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS 0x42090044 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_RSVD1_S 30 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_RSVD1_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_RSVD0_S 4 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_RSVD0_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_ECC_FIX_S) +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_CNT_MEM_STATUS_ECC_ERR_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG 0x42090048 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD3_S 20 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD3_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RM_S 16 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RM_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD2_S 14 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD2_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RME_S 12 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RME_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD1_S 10 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_FIX_CNT_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD0_S 6 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_RSVD0_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_MASK_INT_S 5 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_MASK_INT_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_LS_BYPASS_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_LS_FORCE_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_EN_S 0 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_CFG_ECC_EN_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS 0x4209004C +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_RSVD1_S 30 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_RSVD1_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_RSVD0_S 4 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_RSVD0_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_ECC_FIX_S) +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_CSR_ERR_MEM_STATUS_ECC_ERR_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_COUNT 0x420900B8 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_CMD 0x420900CC +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_DATA_H 0x420900D8 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_DATA_L 0x420900D4 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_PTR 0x420900D0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_CMD 0x420900BC +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_DATA_H 0x420900C8 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_DATA_L 0x420900C4 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_PTR 0x420900C0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_FLM_GLPE_FLM_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_CONTROL 0x42090080 +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD1_S 25 +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD2_S 17 +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD2_S) +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD3_S 9 +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD3_S) +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_BYPASS_S 8 +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_CONTROL_BYPASS_S) +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD4_S 1 +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_DTM_CONTROL_RSVD4_S) +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_FLM_GLPE_FLM_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_CONTROL_LOCAL_EN_S) +#define IG3_FLM_GLPE_FLM_DTM_ECC_COR_ERR 0x420900E8 +#define IG3_FLM_GLPE_FLM_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_FLM_GLPE_FLM_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_FLM_GLPE_FLM_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_FLM_GLPE_FLM_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_FLM_GLPE_FLM_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLM_DTM_ECC_COR_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_DTM_ECC_UNCOR_ERR 0x420900E4 +#define IG3_FLM_GLPE_FLM_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_FLM_GLPE_FLM_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_FLM_GLPE_FLM_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_FLM_GLPE_FLM_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_FLM_GLPE_FLM_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLM_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_DTM_GROUP_CFG 0x4209008C +#define IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_FLM_GLPE_FLM_DTM_LOG_CFG 0x42090090 +#define IG3_FLM_GLPE_FLM_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_FLM_GLPE_FLM_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_FLM_GLPE_FLM_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_FLM_GLPE_FLM_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_FLM_GLPE_FLM_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_FLM_GLPE_FLM_DTM_LOG_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_LOG_CFG_MODE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_DTM_LOG_CFG_MODE_S) +#define IG3_FLM_GLPE_FLM_DTM_LOG_MASK 0x42090098 +#define IG3_FLM_GLPE_FLM_DTM_LOG_MASK_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_LOG_MASK_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_LOG_PATTERN 0x42090094 +#define IG3_FLM_GLPE_FLM_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_LOG_PATTERN_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG 0x42090084 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_RSVD2_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_RSVD3_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_STS 0x42090088 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_FLM_GLPE_FLM_DTM_MAIN_STS_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_DTM_MAIN_STS_RSVD2_S) +#define IG3_FLM_GLPE_FLM_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_FLM_GLPE_FLM_DTM_TIMESTAMP 0x420900B0 +#define IG3_FLM_GLPE_FLM_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_TIMESTAMP_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_TIMESTAMP_ROLLOVER 0x420900B4 +#define IG3_FLM_GLPE_FLM_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG 0x420900DC +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS 0x420900E0 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG 0x4209009C +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_RSVD2_S) +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_MODE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLM_DTM_TRIG_CFG_MODE_S) +#define IG3_FLM_GLPE_FLM_DTM_TRIG_COUNT 0x420900A8 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_TRIG_COUNT_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_TRIG_MASK 0x420900A4 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_TRIG_MASK_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_TRIG_PATTERN 0x420900A0 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_FLM_GLPE_FLM_DTM_TRIG_TIMESTAMP 0x420900AC +#define IG3_FLM_GLPE_FLM_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_FLM_GLPE_FLM_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLM_GLPE_FLM_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_FLM_GLPE_FLM_ECC_COR_ERR 0x42090054 +#define IG3_FLM_GLPE_FLM_ECC_COR_ERR_RSVD_S 12 +#define IG3_FLM_GLPE_FLM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_FLM_GLPE_FLM_ECC_COR_ERR_RSVD_S) +#define IG3_FLM_GLPE_FLM_ECC_COR_ERR_CNT_S 0 +#define IG3_FLM_GLPE_FLM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLM_ECC_COR_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_ECC_UNCOR_ERR 0x42090050 +#define IG3_FLM_GLPE_FLM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_FLM_GLPE_FLM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_FLM_GLPE_FLM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_FLM_GLPE_FLM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_FLM_GLPE_FLM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLM_GLPE_FLM_ECC_UNCOR_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG 0x42090020 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD3_S 20 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD3_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RM_S 16 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RM_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD2_S 14 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD2_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RME_S 12 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RME_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD1_S 10 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_FIX_CNT_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD0_S 6 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_RSVD0_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_MASK_INT_S 5 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_MASK_INT_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_LS_BYPASS_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_LS_FORCE_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_EN_S 0 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_CFG_ECC_EN_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS 0x42090024 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_RSVD1_S 30 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_RSVD1_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_RSVD0_S 4 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_RSVD0_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_ECC_FIX_S) +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_LFSR_MEM_STATUS_ECC_ERR_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG 0x42090030 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD3_S 20 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD3_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RM_S 16 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RM_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD2_S 14 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD2_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RME_S 12 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RME_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD1_S 10 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_FIX_CNT_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD0_S 6 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_RSVD0_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_MASK_INT_S 5 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_MASK_INT_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_LS_BYPASS_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_LS_FORCE_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_EN_S 0 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_CFG_ECC_EN_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS 0x42090034 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_RSVD1_S 30 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_RSVD1_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_RSVD0_S 4 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_RSVD0_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_ECC_FIX_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MAX_MEM_STATUS_ECC_ERR_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG 0x42090028 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD3_S 20 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD3_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RM_S 16 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RM_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD2_S 14 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD2_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RME_S 12 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RME_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD1_S 10 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_FIX_CNT_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD0_S 6 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_RSVD0_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_MASK_INT_S 5 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_MASK_INT_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_LS_BYPASS_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_LS_FORCE_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_EN_S 0 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_CFG_ECC_EN_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS 0x4209002C +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_RSVD1_S 30 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_RSVD1_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_RSVD0_S 4 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_RSVD0_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_ECC_FIX_S) +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_HEAD_MEM_STATUS_ECC_ERR_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG 0x42090038 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD3_S 20 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD3_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RM_S 16 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RM_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD2_S 14 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD2_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RME_S 12 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RME_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD1_S 10 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD1_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ERR_CNT_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_FIX_CNT_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD0_S 6 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_RSVD0_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_MASK_INT_S 5 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_MASK_INT_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_LS_BYPASS_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_LS_FORCE_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_EN_S 0 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_CFG_ECC_EN_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS 0x4209003C +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_RSVD1_S 30 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_RSVD1_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_RSVD0_S 4 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_RSVD0_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_INIT_DONE_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_ECC_FIX_S) +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLM_GLPE_FLM_PTR_TAIL_MEM_STATUS_ECC_ERR_S) +#define IG3_FLM_GLPE_OOISC_ALLOCERR(_i) 0x4208E000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_FLM_GLPE_OOISC_ALLOCERR_MAX_INDEX_I 1031 +#define IG3_FLM_GLPE_OOISC_ALLOCERR_RSVD_S 16 +#define IG3_FLM_GLPE_OOISC_ALLOCERR_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_FLM_GLPE_OOISC_ALLOCERR_RSVD_S) +#define IG3_FLM_GLPE_OOISC_ALLOCERR_ERROR_COUNT_S 0 +#define IG3_FLM_GLPE_OOISC_ALLOCERR_ERROR_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_FLM_GLPE_OOISC_ALLOCERR_ERROR_COUNT_S) +#define IG3_FLM_GLPE_Q1_ALLOCERR(_i) 0x4208A000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_FLM_GLPE_Q1_ALLOCERR_MAX_INDEX_I 1031 +#define IG3_FLM_GLPE_Q1_ALLOCERR_RSVD_S 16 +#define IG3_FLM_GLPE_Q1_ALLOCERR_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_FLM_GLPE_Q1_ALLOCERR_RSVD_S) +#define IG3_FLM_GLPE_Q1_ALLOCERR_ERROR_COUNT_S 0 +#define IG3_FLM_GLPE_Q1_ALLOCERR_ERROR_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_FLM_GLPE_Q1_ALLOCERR_ERROR_COUNT_S) +#define IG3_FLM_GLPE_RRSP_ALLOCERR(_i) 0x4208C000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_FLM_GLPE_RRSP_ALLOCERR_MAX_INDEX_I 1031 +#define IG3_FLM_GLPE_RRSP_ALLOCERR_RSVD_S 16 +#define IG3_FLM_GLPE_RRSP_ALLOCERR_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_FLM_GLPE_RRSP_ALLOCERR_RSVD_S) +#define IG3_FLM_GLPE_RRSP_ALLOCERR_ERROR_COUNT_S 0 +#define IG3_FLM_GLPE_RRSP_ALLOCERR_ERROR_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_FLM_GLPE_RRSP_ALLOCERR_ERROR_COUNT_S) +#define IG3_FLM_GLPE_XMIT_ALLOCERR(_i) 0x42088000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_FLM_GLPE_XMIT_ALLOCERR_MAX_INDEX_I 1031 +#define IG3_FLM_GLPE_XMIT_ALLOCERR_RSVD_S 16 +#define IG3_FLM_GLPE_XMIT_ALLOCERR_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_FLM_GLPE_XMIT_ALLOCERR_RSVD_S) +#define IG3_FLM_GLPE_XMIT_ALLOCERR_ERROR_COUNT_S 0 +#define IG3_FLM_GLPE_XMIT_ALLOCERR_ERROR_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_FLM_GLPE_XMIT_ALLOCERR_ERROR_COUNT_S) +#define IG3_FLM_GPLE_FLMDEBUG 0x4209001C +#define IG3_FLM_GPLE_FLMDEBUG_RSVD_S 3 +#define IG3_FLM_GPLE_FLMDEBUG_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_FLM_GPLE_FLMDEBUG_RSVD_S) +#define IG3_FLM_GPLE_FLMDEBUG_SOFT_RESET_S 2 +#define IG3_FLM_GPLE_FLMDEBUG_SOFT_RESET_M RDMA_BIT2(32, IG3_FLM_GPLE_FLMDEBUG_SOFT_RESET_S) +#define IG3_FLM_GPLE_FLMDEBUG_BYPASS_RAM_DISABLE_S 1 +#define IG3_FLM_GPLE_FLMDEBUG_BYPASS_RAM_DISABLE_M RDMA_BIT2(32, IG3_FLM_GPLE_FLMDEBUG_BYPASS_RAM_DISABLE_S) +#define IG3_FLM_GPLE_FLMDEBUG_STORE_PTR_RESET_S 0 +#define IG3_FLM_GPLE_FLMDEBUG_STORE_PTR_RESET_M RDMA_BIT2(32, IG3_FLM_GPLE_FLMDEBUG_STORE_PTR_RESET_S) +#define IG3_TMR_GLPE_TCPNOWDIV(_i) 0x420A2000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_TMR_GLPE_TCPNOWDIV_MAX_INDEX_I 1031 +#define IG3_TMR_GLPE_TCPNOWDIV_RSVD_S 16 +#define IG3_TMR_GLPE_TCPNOWDIV_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_TMR_GLPE_TCPNOWDIV_RSVD_S) +#define IG3_TMR_GLPE_TCPNOWDIV_TCPNOWDIV_S 0 +#define IG3_TMR_GLPE_TCPNOWDIV_TCPNOWDIV_M RDMA_MASK3(32, 0xFFFF, IG3_TMR_GLPE_TCPNOWDIV_TCPNOWDIV_S) +#define IG3_TMR_GLPE_TCPNOWINIT 0x420A6014 +#define IG3_TMR_GLPE_TCPNOWINIT_TCPNOWINIT_S 0 +#define IG3_TMR_GLPE_TCPNOWINIT_TCPNOWINIT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TCPNOWINIT_TCPNOWINIT_S) +#define IG3_TMR_GLPE_TCPTMRCFG(_i) 0x420A4000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_TMR_GLPE_TCPTMRCFG_MAX_INDEX_I 1031 +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMREN_S 31 +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMREN_M RDMA_BIT2(32, IG3_TMR_GLPE_TCPTMRCFG_PETCPTMREN_S) +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRST_S 30 +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRST_M RDMA_BIT2(32, IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRST_S) +#define IG3_TMR_GLPE_TCPTMRCFG_RSVD2_S 27 +#define IG3_TMR_GLPE_TCPTMRCFG_RSVD2_M RDMA_MASK3(32, 0x7, IG3_TMR_GLPE_TCPTMRCFG_RSVD2_S) +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRNUMQP512BLK_S 16 +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRNUMQP512BLK_M RDMA_MASK3(32, 0x7FF, IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRNUMQP512BLK_S) +#define IG3_TMR_GLPE_TCPTMRCFG_PEROCEV2RTOPOLICY_S 15 +#define IG3_TMR_GLPE_TCPTMRCFG_PEROCEV2RTOPOLICY_M RDMA_BIT2(32, IG3_TMR_GLPE_TCPTMRCFG_PEROCEV2RTOPOLICY_S) +#define IG3_TMR_GLPE_TCPTMRCFG_RSVD1_S 13 +#define IG3_TMR_GLPE_TCPTMRCFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TCPTMRCFG_RSVD1_S) +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRBKTSHIFT_S 8 +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRBKTSHIFT_M RDMA_MASK3(32, 0x1F, IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRBKTSHIFT_S) +#define IG3_TMR_GLPE_TCPTMRCFG_RSVD0_S 5 +#define IG3_TMR_GLPE_TCPTMRCFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_TMR_GLPE_TCPTMRCFG_RSVD0_S) +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRBKTMSKBITS_S 0 +#define IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRBKTMSKBITS_M RDMA_MASK3(32, 0x1F, IG3_TMR_GLPE_TCPTMRCFG_PETCPTMRBKTMSKBITS_S) +#define IG3_TMR_GLPE_TMRCTRL0 0x420A6000 +#define IG3_TMR_GLPE_TMRCTRL0_TRIG_S 31 +#define IG3_TMR_GLPE_TMRCTRL0_TRIG_M RDMA_BIT2(32, IG3_TMR_GLPE_TMRCTRL0_TRIG_S) +#define IG3_TMR_GLPE_TMRCTRL0_RSVD_S 26 +#define IG3_TMR_GLPE_TMRCTRL0_RSVD_M RDMA_MASK3(32, 0x1F, IG3_TMR_GLPE_TMRCTRL0_RSVD_S) +#define IG3_TMR_GLPE_TMRCTRL0_REXMIT_DELTA_S 0 +#define IG3_TMR_GLPE_TMRCTRL0_REXMIT_DELTA_M RDMA_MASK3(32, 0x3FFFFFF, IG3_TMR_GLPE_TMRCTRL0_REXMIT_DELTA_S) +#define IG3_TMR_GLPE_TMRCTRL1 0x420A6004 +#define IG3_TMR_GLPE_TMRCTRL1_DACK_OP_S 30 +#define IG3_TMR_GLPE_TMRCTRL1_DACK_OP_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMRCTRL1_DACK_OP_S) +#define IG3_TMR_GLPE_TMRCTRL1_REXMIT_OP_S 28 +#define IG3_TMR_GLPE_TMRCTRL1_REXMIT_OP_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMRCTRL1_REXMIT_OP_S) +#define IG3_TMR_GLPE_TMRCTRL1_PERSIST_OP_S 26 +#define IG3_TMR_GLPE_TMRCTRL1_PERSIST_OP_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMRCTRL1_PERSIST_OP_S) +#define IG3_TMR_GLPE_TMRCTRL1_IDLE_OP_S 24 +#define IG3_TMR_GLPE_TMRCTRL1_IDLE_OP_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMRCTRL1_IDLE_OP_S) +#define IG3_TMR_GLPE_TMRCTRL1_GP_OP_S 22 +#define IG3_TMR_GLPE_TMRCTRL1_GP_OP_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMRCTRL1_GP_OP_S) +#define IG3_TMR_GLPE_TMRCTRL1_RSVD_S 19 +#define IG3_TMR_GLPE_TMRCTRL1_RSVD_M RDMA_MASK3(32, 0x7, IG3_TMR_GLPE_TMRCTRL1_RSVD_S) +#define IG3_TMR_GLPE_TMRCTRL1_LINEADDR_S 10 +#define IG3_TMR_GLPE_TMRCTRL1_LINEADDR_M RDMA_MASK3(32, 0x1FF, IG3_TMR_GLPE_TMRCTRL1_LINEADDR_S) +#define IG3_TMR_GLPE_TMRCTRL1_DACK_DELTA_S 0 +#define IG3_TMR_GLPE_TMRCTRL1_DACK_DELTA_M RDMA_MASK3(32, 0x3FF, IG3_TMR_GLPE_TMRCTRL1_DACK_DELTA_S) +#define IG3_TMR_GLPE_TMRCTRL2 0x420A6008 +#define IG3_TMR_GLPE_TMRCTRL2_PMF_S 20 +#define IG3_TMR_GLPE_TMRCTRL2_PMF_M RDMA_MASK3(32, 0xFFF, IG3_TMR_GLPE_TMRCTRL2_PMF_S) +#define IG3_TMR_GLPE_TMRCTRL2_VDEV_VF_TYPE_S 18 +#define IG3_TMR_GLPE_TMRCTRL2_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMRCTRL2_VDEV_VF_TYPE_S) +#define IG3_TMR_GLPE_TMRCTRL2_VDEV_VF_NUM_S 6 +#define IG3_TMR_GLPE_TMRCTRL2_VDEV_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_TMR_GLPE_TMRCTRL2_VDEV_VF_NUM_S) +#define IG3_TMR_GLPE_TMRCTRL2_PF_NUM_S 0 +#define IG3_TMR_GLPE_TMRCTRL2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_TMR_GLPE_TMRCTRL2_PF_NUM_S) +#define IG3_TMR_GLPE_TMRCTRL3 0x420A600C +#define IG3_TMR_GLPE_TMRCTRL3_RSVD_S 30 +#define IG3_TMR_GLPE_TMRCTRL3_RSVD_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMRCTRL3_RSVD_S) +#define IG3_TMR_GLPE_TMRCTRL3_HOST_S 27 +#define IG3_TMR_GLPE_TMRCTRL3_HOST_M RDMA_MASK3(32, 0x7, IG3_TMR_GLPE_TMRCTRL3_HOST_S) +#define IG3_TMR_GLPE_TMRCTRL3_TILE_S 24 +#define IG3_TMR_GLPE_TMRCTRL3_TILE_M RDMA_MASK3(32, 0x7, IG3_TMR_GLPE_TMRCTRL3_TILE_S) +#define IG3_TMR_GLPE_TMRCTRL3_QP_NUM_S 0 +#define IG3_TMR_GLPE_TMRCTRL3_QP_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_TMR_GLPE_TMRCTRL3_QP_NUM_S) +#define IG3_TMR_GLPE_TMRSTAT 0x420A6010 +#define IG3_TMR_GLPE_TMRSTAT_RSVD_S 2 +#define IG3_TMR_GLPE_TMRSTAT_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_TMR_GLPE_TMRSTAT_RSVD_S) +#define IG3_TMR_GLPE_TMRSTAT_SCN_BUSY_S 1 +#define IG3_TMR_GLPE_TMRSTAT_SCN_BUSY_M RDMA_BIT2(32, IG3_TMR_GLPE_TMRSTAT_SCN_BUSY_S) +#define IG3_TMR_GLPE_TMRSTAT_CSR_BUSY_S 0 +#define IG3_TMR_GLPE_TMRSTAT_CSR_BUSY_M RDMA_BIT2(32, IG3_TMR_GLPE_TMRSTAT_CSR_BUSY_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_COUNT 0x420A60B8 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_CMD 0x420A60CC +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_DATA_H 0x420A60D8 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_DATA_L 0x420A60D4 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_PTR 0x420A60D0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_CMD 0x420A60BC +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_DATA_H 0x420A60C8 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_DATA_L 0x420A60C4 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_PTR 0x420A60C0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_TMR_GLPE_TMR_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_CONTROL 0x420A6080 +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD1_S 25 +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD2_S 17 +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD2_S) +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD3_S 9 +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD3_S) +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_BYPASS_S 8 +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_CONTROL_BYPASS_S) +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD4_S 1 +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_TMR_GLPE_TMR_DTM_CONTROL_RSVD4_S) +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_TMR_GLPE_TMR_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_CONTROL_LOCAL_EN_S) +#define IG3_TMR_GLPE_TMR_DTM_ECC_COR_ERR 0x420A60E8 +#define IG3_TMR_GLPE_TMR_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_TMR_GLPE_TMR_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TMR_GLPE_TMR_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_TMR_GLPE_TMR_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_TMR_GLPE_TMR_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TMR_GLPE_TMR_DTM_ECC_COR_ERR_CNT_S) +#define IG3_TMR_GLPE_TMR_DTM_ECC_UNCOR_ERR 0x420A60E4 +#define IG3_TMR_GLPE_TMR_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TMR_GLPE_TMR_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TMR_GLPE_TMR_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TMR_GLPE_TMR_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TMR_GLPE_TMR_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TMR_GLPE_TMR_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_TMR_GLPE_TMR_DTM_GROUP_CFG 0x420A608C +#define IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_TMR_GLPE_TMR_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_TMR_GLPE_TMR_DTM_LOG_CFG 0x420A6090 +#define IG3_TMR_GLPE_TMR_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_TMR_GLPE_TMR_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_TMR_GLPE_TMR_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_TMR_GLPE_TMR_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_TMR_GLPE_TMR_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_TMR_GLPE_TMR_DTM_LOG_CFG_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_LOG_CFG_MODE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMR_DTM_LOG_CFG_MODE_S) +#define IG3_TMR_GLPE_TMR_DTM_LOG_MASK 0x420A6098 +#define IG3_TMR_GLPE_TMR_DTM_LOG_MASK_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_LOG_MASK_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_LOG_PATTERN 0x420A6094 +#define IG3_TMR_GLPE_TMR_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_LOG_PATTERN_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG 0x420A6084 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_RSVD2_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_RSVD3_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_STS 0x420A6088 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_TMR_GLPE_TMR_DTM_MAIN_STS_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_TMR_GLPE_TMR_DTM_MAIN_STS_RSVD2_S) +#define IG3_TMR_GLPE_TMR_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_TMR_GLPE_TMR_DTM_TIMESTAMP 0x420A60B0 +#define IG3_TMR_GLPE_TMR_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_TIMESTAMP_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_TIMESTAMP_ROLLOVER 0x420A60B4 +#define IG3_TMR_GLPE_TMR_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG 0x420A60DC +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS 0x420A60E0 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TMR_GLPE_TMR_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG 0x420A609C +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_RSVD1_S) +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_RSVD2_S) +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_MODE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_TMR_GLPE_TMR_DTM_TRIG_CFG_MODE_S) +#define IG3_TMR_GLPE_TMR_DTM_TRIG_COUNT 0x420A60A8 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_TRIG_COUNT_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_TRIG_MASK 0x420A60A4 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_TRIG_MASK_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_TRIG_PATTERN 0x420A60A0 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_TMR_GLPE_TMR_DTM_TRIG_TIMESTAMP 0x420A60AC +#define IG3_TMR_GLPE_TMR_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_TMR_GLPE_TMR_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_GLPE_TMR_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_TMR_GLPE_TMR_HF 0x420A6018 +#define IG3_TMR_GLPE_TMR_HF_CNT_S 16 +#define IG3_TMR_GLPE_TMR_HF_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_TMR_GLPE_TMR_HF_CNT_S) +#define IG3_TMR_GLPE_TMR_HF_VAL_S 0 +#define IG3_TMR_GLPE_TMR_HF_VAL_M RDMA_MASK3(32, 0xFFFF, IG3_TMR_GLPE_TMR_HF_VAL_S) +#define IG3_TMR_PMFPE_TCPNOWTIMER(_i) 0x420A0000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_TMR_PMFPE_TCPNOWTIMER_MAX_INDEX_I 1031 +#define IG3_TMR_PMFPE_TCPNOWTIMER_TCP_NOW_S 0 +#define IG3_TMR_PMFPE_TCPNOWTIMER_TCP_NOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMR_PMFPE_TCPNOWTIMER_TCP_NOW_S) +#define IG3_PTXI_GLPE_PMFCOUNT_CTRL 0x420C6308 +#define IG3_PTXI_GLPE_PMFCOUNT_CTRL_RSVD_S 1 +#define IG3_PTXI_GLPE_PMFCOUNT_CTRL_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTXI_GLPE_PMFCOUNT_CTRL_RSVD_S) +#define IG3_PTXI_GLPE_PMFCOUNT_CTRL_STALL_S 0 +#define IG3_PTXI_GLPE_PMFCOUNT_CTRL_STALL_M RDMA_BIT2(32, IG3_PTXI_GLPE_PMFCOUNT_CTRL_STALL_S) +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG(_i) 0x420C6338 + ((_i) * 4) /* _i=0...7 */ +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_MAX_INDEX_I 7 +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_BUSY_S 31 +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_BUSY_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_BUSY_S) +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_HOSTID_S 28 +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_HOSTID_S) +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_VM_VF_TYPE_S 26 +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_VM_VF_TYPE_S) +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_PF_NUM_S 20 +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_PF_NUM_S) +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_VM_VF_NUM_S 8 +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_VM_VF_NUM_S) +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_PORT_S 5 +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_PORT_M RDMA_MASK3(32, 0x7, IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_PORT_S) +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_RSVD0_S 0 +#define IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PTXI_GLPE_PTXCMP_MKR_TRIG_RSVD0_S) +#define IG3_PTXI_GLPE_PTXI_CONFIG 0x420C630C +#define IG3_PTXI_GLPE_PTXI_CONFIG_RSVD_S 2 +#define IG3_PTXI_GLPE_PTXI_CONFIG_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PTXI_GLPE_PTXI_CONFIG_RSVD_S) +#define IG3_PTXI_GLPE_PTXI_CONFIG_STALL_FLR_ON_FULL_S 1 +#define IG3_PTXI_GLPE_PTXI_CONFIG_STALL_FLR_ON_FULL_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_CONFIG_STALL_FLR_ON_FULL_S) +#define IG3_PTXI_GLPE_PTXI_CONFIG_STALL_FLUSH_ON_FULL_S 0 +#define IG3_PTXI_GLPE_PTXI_CONFIG_STALL_FLUSH_ON_FULL_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_CONFIG_STALL_FLUSH_ON_FULL_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_COUNT 0x420C63B8 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_CMD 0x420C63CC +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_DATA_H 0x420C63D8 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_DATA_L 0x420C63D4 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_PTR 0x420C63D0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_CMD 0x420C63BC +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_DATA_H 0x420C63C8 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_DATA_L 0x420C63C4 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_PTR 0x420C63C0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTXI_GLPE_PTXI_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL 0x420C6380 +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD1_S 25 +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD2_S 17 +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD2_S) +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD3_S 9 +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD3_S) +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_BYPASS_S 8 +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_CONTROL_BYPASS_S) +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD4_S 1 +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PTXI_GLPE_PTXI_DTM_CONTROL_RSVD4_S) +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_COR_ERR 0x420C63E8 +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTXI_GLPE_PTXI_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTXI_GLPE_PTXI_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_UNCOR_ERR 0x420C63E4 +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTXI_GLPE_PTXI_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTXI_GLPE_PTXI_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG 0x420C638C +#define IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTXI_GLPE_PTXI_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG 0x420C6390 +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG_MODE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PTXI_GLPE_PTXI_DTM_LOG_CFG_MODE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_MASK 0x420C6398 +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_LOG_MASK_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_PATTERN 0x420C6394 +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG 0x420C6384 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS 0x420C6388 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_RSVD2_S) +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TIMESTAMP 0x420C63B0 +#define IG3_PTXI_GLPE_PTXI_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_TIMESTAMP_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TIMESTAMP_ROLLOVER 0x420C63B4 +#define IG3_PTXI_GLPE_PTXI_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG 0x420C63DC +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS 0x420C63E0 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PTXI_GLPE_PTXI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG 0x420C639C +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PTXI_GLPE_PTXI_DTM_TRIG_CFG_MODE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_COUNT 0x420C63A8 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_MASK 0x420C63A4 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_TRIG_MASK_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_PATTERN 0x420C63A0 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_TIMESTAMP 0x420C63AC +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PTXI_GLPE_PTXI_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTXI_GLPE_PTXI_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PTXI_GLPE_PTX_FLR_MKR_CNT 0x420C6314 +#define IG3_PTXI_GLPE_PTX_FLR_MKR_CNT_RSVD_S 8 +#define IG3_PTXI_GLPE_PTX_FLR_MKR_CNT_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTXI_GLPE_PTX_FLR_MKR_CNT_RSVD_S) +#define IG3_PTXI_GLPE_PTX_FLR_MKR_CNT_MKR_CNT_S 0 +#define IG3_PTXI_GLPE_PTX_FLR_MKR_CNT_MKR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PTXI_GLPE_PTX_FLR_MKR_CNT_MKR_CNT_S) +#define IG3_PTXI_GLPE_PTX_FLUSH_MKR_CNT 0x420C6310 +#define IG3_PTXI_GLPE_PTX_FLUSH_MKR_CNT_RSVD_S 16 +#define IG3_PTXI_GLPE_PTX_FLUSH_MKR_CNT_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PTXI_GLPE_PTX_FLUSH_MKR_CNT_RSVD_S) +#define IG3_PTXI_GLPE_PTX_FLUSH_MKR_CNT_MKR_CNT_S 0 +#define IG3_PTXI_GLPE_PTX_FLUSH_MKR_CNT_MKR_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PTXI_GLPE_PTX_FLUSH_MKR_CNT_MKR_CNT_S) +#define IG3_PTXI_GLPE_XLR_DROP(_i) 0x420C6318 + ((_i) * 4) /* _i=0...7 */ +#define IG3_PTXI_GLPE_XLR_DROP_MAX_INDEX_I 7 +#define IG3_PTXI_GLPE_XLR_DROP_DROP_S 31 +#define IG3_PTXI_GLPE_XLR_DROP_DROP_M RDMA_BIT2(32, IG3_PTXI_GLPE_XLR_DROP_DROP_S) +#define IG3_PTXI_GLPE_XLR_DROP_RSVD_S 20 +#define IG3_PTXI_GLPE_XLR_DROP_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_PTXI_GLPE_XLR_DROP_RSVD_S) +#define IG3_PTXI_GLPE_XLR_DROP_FUNC_TYPE_S 18 +#define IG3_PTXI_GLPE_XLR_DROP_FUNC_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTXI_GLPE_XLR_DROP_FUNC_TYPE_S) +#define IG3_PTXI_GLPE_XLR_DROP_FUNC_NUM_S 6 +#define IG3_PTXI_GLPE_XLR_DROP_FUNC_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTXI_GLPE_XLR_DROP_FUNC_NUM_S) +#define IG3_PTXI_GLPE_XLR_DROP_PHY_FUNC_S 0 +#define IG3_PTXI_GLPE_XLR_DROP_PHY_FUNC_M RDMA_MASK3(32, 0x3F, IG3_PTXI_GLPE_XLR_DROP_PHY_FUNC_S) +#define IG3_PTXI_PMFPE_IPCONFIG0(_i) 0x420C0000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PTXI_PMFPE_IPCONFIG0_MAX_INDEX_I 1031 +#define IG3_PTXI_PMFPE_IPCONFIG0_RSVD_S 18 +#define IG3_PTXI_PMFPE_IPCONFIG0_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_PTXI_PMFPE_IPCONFIG0_RSVD_S) +#define IG3_PTXI_PMFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17 +#define IG3_PTXI_PMFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M RDMA_BIT2(32, IG3_PTXI_PMFPE_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S) +#define IG3_PTXI_PMFPE_IPCONFIG0_USEENTIREIDRANGE_S 16 +#define IG3_PTXI_PMFPE_IPCONFIG0_USEENTIREIDRANGE_M RDMA_BIT2(32, IG3_PTXI_PMFPE_IPCONFIG0_USEENTIREIDRANGE_S) +#define IG3_PTXI_PMFPE_IPCONFIG0_PEIPID_S 0 +#define IG3_PTXI_PMFPE_IPCONFIG0_PEIPID_M RDMA_MASK3(32, 0xFFFF, IG3_PTXI_PMFPE_IPCONFIG0_PEIPID_S) +#define IG3_PTXI_PMFPE_PMFCOUNT(_i) 0x420C2000 + ((_i) * 4) /* _i=0...4127 */ +#define IG3_PTXI_PMFPE_PMFCOUNT_MAX_INDEX_I 4127 +#define IG3_PTXI_PMFPE_PMFCOUNT_FW_TOKEN_S 24 +#define IG3_PTXI_PMFPE_PMFCOUNT_FW_TOKEN_M RDMA_MASK3(32, 0xFF, IG3_PTXI_PMFPE_PMFCOUNT_FW_TOKEN_S) +#define IG3_PTXI_PMFPE_PMFCOUNT_RSVD1_S 23 +#define IG3_PTXI_PMFPE_PMFCOUNT_RSVD1_M RDMA_BIT2(32, IG3_PTXI_PMFPE_PMFCOUNT_RSVD1_S) +#define IG3_PTXI_PMFPE_PMFCOUNT_HOST_ID_S 20 +#define IG3_PTXI_PMFPE_PMFCOUNT_HOST_ID_M RDMA_MASK3(32, 0x7, IG3_PTXI_PMFPE_PMFCOUNT_HOST_ID_S) +#define IG3_PTXI_PMFPE_PMFCOUNT_FLUSH_PENDING_S 19 +#define IG3_PTXI_PMFPE_PMFCOUNT_FLUSH_PENDING_M RDMA_BIT2(32, IG3_PTXI_PMFPE_PMFCOUNT_FLUSH_PENDING_S) +#define IG3_PTXI_PMFPE_PMFCOUNT_RSVD0_S 18 +#define IG3_PTXI_PMFPE_PMFCOUNT_RSVD0_M RDMA_BIT2(32, IG3_PTXI_PMFPE_PMFCOUNT_RSVD0_S) +#define IG3_PTXI_PMFPE_PMFCOUNT_COUNT_S 0 +#define IG3_PTXI_PMFPE_PMFCOUNT_COUNT_M RDMA_MASK3(32, 0x3FFFF, IG3_PTXI_PMFPE_PMFCOUNT_COUNT_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH(_i) 0x420C6200 + ((_i) * 4) /* _i=0...65 */ +#define IG3_PTXI_PMFPE_PMF_EPOCH_MAX_INDEX_I 65 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH15_S 30 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH15_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH15_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH14_S 28 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH14_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH14_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH13_S 26 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH13_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH13_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH12_S 24 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH12_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH12_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH11_S 22 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH11_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH11_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH10_S 20 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH10_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH10_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH9_S 18 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH9_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH9_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH8_S 16 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH8_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH8_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH7_S 14 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH7_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH7_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH6_S 12 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH6_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH6_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH5_S 10 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH5_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH5_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH4_S 8 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH4_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH4_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH3_S 6 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH3_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH3_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH2_S 4 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH2_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH2_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH1_S 2 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH1_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH1_S) +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH0_S 0 +#define IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH0_M RDMA_MASK3(32, 0x3, IG3_PTXI_PMFPE_PMF_EPOCH_EPOCH0_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_BUS_INDEX 0x420E1110 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL 0x420E1100 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_TRIG_OP_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_CTRL_FREEZE_SET_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_FREEZE_ON_CNT_VAL 0x420E1120 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_OBS_BUS 0x420E1140 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT0 0x420E1160 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT0_CNT0_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT1_0 0x420E1168 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT1_1 0x420E116C +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL 0x420E1158 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_CTRL 0x420E1138 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_GAP 0x420E1128 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_RC_GAP_RC_GAP_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_TRNS 0x420E1130 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS 0x420E1108 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_READY_S 5 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_READY_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_VALID_S 4 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_VALID_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB0_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_TRANS_CNT 0x420E1118 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_TRIG_MASK 0x420E1148 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CORE_GLPE_CORE_BOB0_BOB_TRIG_VALUE 0x420E1150 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CORE_GLPE_CORE_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_BUS_INDEX 0x420E1190 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL 0x420E1180 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_TRIG_OP_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_CTRL_FREEZE_SET_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_FREEZE_ON_CNT_VAL 0x420E11A0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_OBS_BUS 0x420E11C0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT0 0x420E11E0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT0_CNT0_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT1_0 0x420E11E8 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT1_1 0x420E11EC +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL 0x420E11D8 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_CTRL 0x420E11B8 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_GAP 0x420E11A8 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_RC_GAP_RC_GAP_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_TRNS 0x420E11B0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS 0x420E1188 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_READY_S 5 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_READY_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_VALID_S 4 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_VALID_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB1_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_TRANS_CNT 0x420E1198 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_TRIG_MASK 0x420E11C8 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CORE_GLPE_CORE_BOB1_BOB_TRIG_VALUE 0x420E11D0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CORE_GLPE_CORE_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_BUS_INDEX 0x420E1210 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL 0x420E1200 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_TRIG_OP_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_CTRL_FREEZE_SET_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_FREEZE_ON_CNT_VAL 0x420E1220 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_OBS_BUS 0x420E1240 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT0 0x420E1260 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT0_CNT0_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT1_0 0x420E1268 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT1_1 0x420E126C +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL 0x420E1258 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_CTRL 0x420E1238 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_GAP 0x420E1228 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_RC_GAP_RC_GAP_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_TRNS 0x420E1230 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS 0x420E1208 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_READY_S 5 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_READY_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_VALID_S 4 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_VALID_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB2_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_TRANS_CNT 0x420E1218 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_TRIG_MASK 0x420E1248 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CORE_GLPE_CORE_BOB2_BOB_TRIG_VALUE 0x420E1250 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CORE_GLPE_CORE_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_BUS_INDEX 0x420E1290 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL 0x420E1280 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_TRIG_OP_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_CTRL_FREEZE_SET_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_FREEZE_ON_CNT_VAL 0x420E12A0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_OBS_BUS 0x420E12C0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT0 0x420E12E0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT0_CNT0_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT1_0 0x420E12E8 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT1_1 0x420E12EC +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL 0x420E12D8 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_CTRL 0x420E12B8 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_GAP 0x420E12A8 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_RC_GAP_RC_GAP_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_TRNS 0x420E12B0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS 0x420E1288 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_READY_S 5 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_READY_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_VALID_S 4 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_VALID_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB3_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_TRANS_CNT 0x420E1298 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_TRIG_MASK 0x420E12C8 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CORE_GLPE_CORE_BOB3_BOB_TRIG_VALUE 0x420E12D0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CORE_GLPE_CORE_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_BUS_INDEX 0x420E1310 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL 0x420E1300 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_TRIG_OP_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_CTRL_FREEZE_SET_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_FREEZE_ON_CNT_VAL 0x420E1320 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_OBS_BUS 0x420E1340 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT0 0x420E1360 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT0_CNT0_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT1_0 0x420E1368 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT1_1 0x420E136C +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL 0x420E1358 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB4_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_CTRL 0x420E1338 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_GAP 0x420E1328 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_RC_GAP_RC_GAP_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_TRNS 0x420E1330 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS 0x420E1308 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_READY_S 5 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_READY_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_VALID_S 4 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_VALID_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB4_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_TRANS_CNT 0x420E1318 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_TRIG_MASK 0x420E1348 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CORE_GLPE_CORE_BOB4_BOB_TRIG_VALUE 0x420E1350 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CORE_GLPE_CORE_BOB4_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB4_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_BUS_INDEX 0x420E1390 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL 0x420E1380 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_TRIG_OP_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_CTRL_FREEZE_SET_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_FREEZE_ON_CNT_VAL 0x420E13A0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_OBS_BUS 0x420E13C0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT0 0x420E13E0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT0_CNT0_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT1_0 0x420E13E8 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT1_1 0x420E13EC +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL 0x420E13D8 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CORE_GLPE_CORE_BOB5_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_CTRL 0x420E13B8 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_GAP 0x420E13A8 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_RC_GAP_RC_GAP_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_TRNS 0x420E13B0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS 0x420E1388 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_I_FREEZE_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_READY_S 5 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_READY_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_VALID_S 4 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_VALID_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CORE_GLPE_CORE_BOB5_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_TRANS_CNT 0x420E1398 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_TRIG_MASK 0x420E13C8 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CORE_GLPE_CORE_BOB5_BOB_TRIG_VALUE 0x420E13D0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CORE_GLPE_CORE_BOB5_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_CORE_BOB5_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC0 0x420E104C +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST3_THOLD_S 24 +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST3_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST3_THOLD_S) +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST2_THOLD_S 16 +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST2_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST2_THOLD_S) +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST1_THOLD_S 8 +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST1_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST1_THOLD_S) +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST0_THOLD_S 0 +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST0_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CPAL_HOST_ALLOC0_HOST0_THOLD_S) +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC1 0x420E1050 +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC1_RSVD_S 16 +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC1_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CORE_GLPE_CPAL_HOST_ALLOC1_RSVD_S) +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC1_HOST5_THOLD_S 8 +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC1_HOST5_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CPAL_HOST_ALLOC1_HOST5_THOLD_S) +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC1_HOST4_THOLD_S 0 +#define IG3_CORE_GLPE_CPAL_HOST_ALLOC1_HOST4_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_CPAL_HOST_ALLOC1_HOST4_THOLD_S) +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC0 0x420E1054 +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST3_THOLD_S 24 +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST3_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST3_THOLD_S) +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST2_THOLD_S 16 +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST2_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST2_THOLD_S) +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST1_THOLD_S 8 +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST1_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST1_THOLD_S) +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST0_THOLD_S 0 +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST0_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_DPAL_HOST_ALLOC0_HOST0_THOLD_S) +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC1 0x420E1058 +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC1_RSVD_S 16 +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC1_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CORE_GLPE_DPAL_HOST_ALLOC1_RSVD_S) +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC1_HOST5_THOLD_S 8 +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC1_HOST5_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_DPAL_HOST_ALLOC1_HOST5_THOLD_S) +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC1_HOST4_THOLD_S 0 +#define IG3_CORE_GLPE_DPAL_HOST_ALLOC1_HOST4_THOLD_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_DPAL_HOST_ALLOC1_HOST4_THOLD_S) +#define IG3_CORE_GLPE_DTM_GLOBAL_EN 0x420E105C +#define IG3_CORE_GLPE_DTM_GLOBAL_EN_RSVD_S 1 +#define IG3_CORE_GLPE_DTM_GLOBAL_EN_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CORE_GLPE_DTM_GLOBAL_EN_RSVD_S) +#define IG3_CORE_GLPE_DTM_GLOBAL_EN_GLOBAL_EN_S 0 +#define IG3_CORE_GLPE_DTM_GLOBAL_EN_GLOBAL_EN_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_GLOBAL_EN_GLOBAL_EN_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_31_0 0x420E1060 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_31_0_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_31_0_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_0_31_0_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_63_32 0x420E1064 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_63_32_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_63_32_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_0_63_32_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_75_64 0x420E1068 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_75_64_RSVD_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_75_64_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_0_75_64_RSVD_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_75_64_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_0_75_64_MASK_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_0_75_64_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_31_0 0x420E106C +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_31_0_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_31_0_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_1_31_0_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_63_32 0x420E1070 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_63_32_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_63_32_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_1_63_32_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_75_64 0x420E1074 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_75_64_RSVD_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_75_64_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_1_75_64_RSVD_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_75_64_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_1_75_64_MASK_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_1_75_64_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_31_0 0x420E1078 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_31_0_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_31_0_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_2_31_0_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_63_32 0x420E107C +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_63_32_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_63_32_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_2_63_32_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_75_64 0x420E1080 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_75_64_RSVD_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_75_64_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_2_75_64_RSVD_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_75_64_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_2_75_64_MASK_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_2_75_64_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_31_0 0x420E1084 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_31_0_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_31_0_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_3_31_0_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_63_32 0x420E1088 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_63_32_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_63_32_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_3_63_32_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_75_64 0x420E108C +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_75_64_RSVD_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_75_64_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_3_75_64_RSVD_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_75_64_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_3_75_64_MASK_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_3_75_64_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_31_0 0x420E1090 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_31_0_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_31_0_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_4_31_0_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_63_32 0x420E1094 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_63_32_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_63_32_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_4_63_32_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_75_64 0x420E1098 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_75_64_RSVD_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_75_64_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_4_75_64_RSVD_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_75_64_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_4_75_64_MASK_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_4_75_64_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_31_0 0x420E109C +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_31_0_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_31_0_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_5_31_0_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_63_32 0x420E10A0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_63_32_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_63_32_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_5_63_32_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_75_64 0x420E10A4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_75_64_RSVD_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_75_64_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_5_75_64_RSVD_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_75_64_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_5_75_64_MASK_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_5_75_64_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_31_0 0x420E10A8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_31_0_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_31_0_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_6_31_0_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_63_32 0x420E10AC +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_63_32_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_63_32_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_6_63_32_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_75_64 0x420E10B0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_75_64_RSVD_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_75_64_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_6_75_64_RSVD_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_75_64_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_6_75_64_MASK_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_6_75_64_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_31_0 0x420E10B4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_31_0_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_31_0_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_7_31_0_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_63_32 0x420E10B8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_63_32_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_63_32_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_7_63_32_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_75_64 0x420E10BC +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_75_64_RSVD_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_75_64_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_7_75_64_RSVD_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_75_64_MASK_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_7_75_64_MASK_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_7_75_64_MASK_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8 0x420E10C4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD7_S 31 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD7_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_15_S 28 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_15_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_15_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD6_S 27 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD6_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_14_S 24 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_14_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_14_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD5_S 23 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD5_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_13_S 20 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_13_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_13_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD4_S 19 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD4_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_12_S 16 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_12_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_12_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD3_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD3_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_11_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_11_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_11_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_10_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_10_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_10_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_9_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_9_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_9_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_8_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_8_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_15_8_MASK_SEL_8_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16 0x420E10C8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD7_S 31 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD7_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_23_S 28 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_23_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_23_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD6_S 27 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD6_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_22_S 24 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_22_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_22_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD5_S 23 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD5_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_21_S 20 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_21_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_21_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD4_S 19 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD4_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_20_S 16 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_20_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_20_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD3_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD3_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_19_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_19_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_19_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_18_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_18_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_18_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_17_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_17_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_17_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_16_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_16_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_23_16_MASK_SEL_16_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24 0x420E10CC +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD7_S 31 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD7_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_31_S 28 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_31_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_31_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD6_S 27 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD6_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_30_S 24 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_30_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_30_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD5_S 23 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD5_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_29_S 20 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_29_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_29_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD4_S 19 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD4_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_28_S 16 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_28_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_28_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD3_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD3_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_27_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_27_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_27_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_26_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_26_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_26_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_25_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_25_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_25_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_24_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_24_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_31_24_MASK_SEL_24_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32 0x420E10D0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD7_S 31 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD7_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_39_S 28 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_39_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_39_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD6_S 27 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD6_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_38_S 24 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_38_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_38_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD5_S 23 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD5_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_37_S 20 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_37_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_37_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD4_S 19 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD4_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_36_S 16 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_36_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_36_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD3_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD3_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_35_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_35_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_35_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_34_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_34_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_34_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_33_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_33_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_33_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_32_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_32_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_39_32_MASK_SEL_32_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40 0x420E10D4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD7_S 31 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD7_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_47_S 28 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_47_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_47_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD6_S 27 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD6_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_46_S 24 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_46_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_46_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD5_S 23 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD5_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_45_S 20 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_45_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_45_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD4_S 19 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD4_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_44_S 16 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_44_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_44_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD3_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD3_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_43_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_43_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_43_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_42_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_42_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_42_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_41_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_41_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_41_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_40_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_40_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_47_40_MASK_SEL_40_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48 0x420E10D8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD7_S 31 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD7_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_55_S 28 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_55_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_55_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD6_S 27 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD6_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_54_S 24 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_54_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_54_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD5_S 23 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD5_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_53_S 20 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_53_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_53_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD4_S 19 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD4_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_52_S 16 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_52_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_52_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD3_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD3_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_51_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_51_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_51_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_50_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_50_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_50_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_49_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_49_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_49_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_48_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_48_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_55_48_MASK_SEL_48_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56 0x420E10DC +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD7_S 31 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD7_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_63_S 28 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_63_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_63_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD6_S 27 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD6_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_62_S 24 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_62_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_62_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD5_S 23 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD5_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_61_S 20 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_61_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_61_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD4_S 19 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD4_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_60_S 16 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_60_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_60_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD3_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD3_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_59_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_59_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_59_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_58_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_58_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_58_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_57_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_57_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_57_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_56_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_56_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_63_56_MASK_SEL_56_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64 0x420E10E0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD7_S 31 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD7_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_71_S 28 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_71_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_71_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD6_S 27 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD6_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_70_S 24 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_70_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_70_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD5_S 23 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD5_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_69_S 20 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_69_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_69_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD4_S 19 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD4_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_68_S 16 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_68_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_68_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD3_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD3_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_67_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_67_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_67_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_66_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_66_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_66_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_65_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_65_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_65_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_64_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_64_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_71_64_MASK_SEL_64_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72 0x420E10E4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD5_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD5_M RDMA_MASK3(32, 0x1FFFF, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_75_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_75_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_75_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_74_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_74_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_74_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_73_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_73_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_73_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_72_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_72_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_75_72_MASK_SEL_72_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0 0x420E10C0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD7_S 31 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD7_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_7_S 28 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_7_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_7_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD6_S 27 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD6_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_6_S 24 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_6_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_6_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD5_S 23 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD5_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_5_S 20 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_5_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_5_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD4_S 19 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD4_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_4_S 16 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_4_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_4_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD3_S 15 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD3_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_3_S 12 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_3_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_3_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD2_S 11 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD2_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_2_S 8 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_2_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_2_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD1_S 7 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD1_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_1_S 4 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_1_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_1_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD0_S 3 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_RSVD0_S) +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_0_S 0 +#define IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_0_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_DTM_MATRIX_MASK_SEL_7_0_MASK_SEL_0_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL(_i) 0x420E0000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CORE_GLPE_FLM_OBJCTRL_MAX_INDEX_I 1031 +#define IG3_CORE_GLPE_FLM_OBJCTRL_FLMEN_S 31 +#define IG3_CORE_GLPE_FLM_OBJCTRL_FLMEN_M RDMA_BIT2(32, IG3_CORE_GLPE_FLM_OBJCTRL_FLMEN_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL_FLMST_S 30 +#define IG3_CORE_GLPE_FLM_OBJCTRL_FLMST_M RDMA_BIT2(32, IG3_CORE_GLPE_FLM_OBJCTRL_FLMST_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL_RSVD3_S 27 +#define IG3_CORE_GLPE_FLM_OBJCTRL_RSVD3_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_FLM_OBJCTRL_RSVD3_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL_OOISC_BLOCKSIZE_S 24 +#define IG3_CORE_GLPE_FLM_OBJCTRL_OOISC_BLOCKSIZE_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_FLM_OBJCTRL_OOISC_BLOCKSIZE_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL_RSVD2_S 19 +#define IG3_CORE_GLPE_FLM_OBJCTRL_RSVD2_M RDMA_MASK3(32, 0x1F, IG3_CORE_GLPE_FLM_OBJCTRL_RSVD2_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL_RRSP_BLOCKSIZE_S 16 +#define IG3_CORE_GLPE_FLM_OBJCTRL_RRSP_BLOCKSIZE_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_FLM_OBJCTRL_RRSP_BLOCKSIZE_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL_RSVD1_S 11 +#define IG3_CORE_GLPE_FLM_OBJCTRL_RSVD1_M RDMA_MASK3(32, 0x1F, IG3_CORE_GLPE_FLM_OBJCTRL_RSVD1_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL_Q1_BLOCKSIZE_S 8 +#define IG3_CORE_GLPE_FLM_OBJCTRL_Q1_BLOCKSIZE_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_FLM_OBJCTRL_Q1_BLOCKSIZE_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL_RSVD0_S 3 +#define IG3_CORE_GLPE_FLM_OBJCTRL_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_CORE_GLPE_FLM_OBJCTRL_RSVD0_S) +#define IG3_CORE_GLPE_FLM_OBJCTRL_XMIT_BLOCKSIZE_S 0 +#define IG3_CORE_GLPE_FLM_OBJCTRL_XMIT_BLOCKSIZE_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_FLM_OBJCTRL_XMIT_BLOCKSIZE_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0 0x420E1020 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_BUSY_S 31 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_BUSY_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_BUSY_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_OP_S 28 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_OP_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_PMF_TABLE_CTRL0_OP_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_C_MASK_S 27 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_C_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_C_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_C_S 26 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_C_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_C_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_W_MASK_S 25 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_W_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_W_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_W_S 24 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_W_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_ISMASKED_W_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_C_MASK_S 23 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_C_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_C_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_C_S 22 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_C_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_C_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_W_MASK_S 21 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_W_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_W_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_W_S 20 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_W_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_INFLR_W_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_C_MASK_S 19 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_C_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_C_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_C_S 18 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_C_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_C_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_W_MASK_S 17 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_W_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_W_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_W_S 16 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_W_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_INTEAM_W_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_C_MASK_S 15 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_C_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_C_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_C_S 14 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_C_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_C_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_W_MASK_S 13 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_W_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_W_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_W_S 12 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_W_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL0_VALID_W_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_TBL_IDX_S 0 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL0_TBL_IDX_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_PMF_TABLE_CTRL0_TBL_IDX_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1 0x420E1024 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_C_MASK_S 31 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_C_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_C_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_RSVD1_S 28 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_RSVD1_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_PMF_TABLE_CTRL1_RSVD1_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_C_S 16 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_C_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_C_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_W_MASK_S 15 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_W_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_W_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_RSVD0_S 12 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_PMF_TABLE_CTRL1_RSVD0_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_W_S 0 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_W_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_PMF_TABLE_CTRL1_PMF_W_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2 0x420E1028 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_HOSTID_W_MASK_S 31 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_HOSTID_W_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL2_HOSTID_W_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_TYPE_W_MASK_S 30 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_TYPE_W_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_TYPE_W_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_W_MASK_S 29 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_W_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_W_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_PF_W_MASK_S 28 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_PF_W_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL2_PF_W_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_RSVD_S 23 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_RSVD_M RDMA_MASK3(32, 0x1F, IG3_CORE_GLPE_PMF_TABLE_CTRL2_RSVD_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_HOSTID_W_S 20 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_HOSTID_W_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_PMF_TABLE_CTRL2_HOSTID_W_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_TYPE_W_S 18 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_TYPE_W_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_TYPE_W_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_W_S 6 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_W_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_PMF_TABLE_CTRL2_VDEV_VF_W_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_PF_W_S 0 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL2_PF_W_M RDMA_MASK3(32, 0x3F, IG3_CORE_GLPE_PMF_TABLE_CTRL2_PF_W_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3 0x420E102C +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_HOSTID_C_MASK_S 31 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_HOSTID_C_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL3_HOSTID_C_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_TYPE_C_MASK_S 30 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_TYPE_C_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_TYPE_C_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_C_MASK_S 29 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_C_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_C_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_PF_C_MASK_S 28 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_PF_C_MASK_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_CTRL3_PF_C_MASK_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_RSVD_S 23 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_RSVD_M RDMA_MASK3(32, 0x1F, IG3_CORE_GLPE_PMF_TABLE_CTRL3_RSVD_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_HOSTID_C_S 20 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_HOSTID_C_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_PMF_TABLE_CTRL3_HOSTID_C_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_TYPE_C_S 18 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_TYPE_C_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_TYPE_C_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_C_S 6 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_C_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_PMF_TABLE_CTRL3_VDEV_VF_C_S) +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_PF_C_S 0 +#define IG3_CORE_GLPE_PMF_TABLE_CTRL3_PF_C_M RDMA_MASK3(32, 0x3F, IG3_CORE_GLPE_PMF_TABLE_CTRL3_PF_C_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA0 0x420E1030 +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_HIT_S 31 +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_HIT_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_DATA0_HIT_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_RSVD_S 28 +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_RSVD_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_PMF_TABLE_DATA0_RSVD_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_PMF_S 16 +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_PMF_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_PMF_TABLE_DATA0_PMF_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_INTEAM_S 15 +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_INTEAM_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_DATA0_INTEAM_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_INFLR_S 14 +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_INFLR_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_DATA0_INFLR_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_ISMASKED_S 13 +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_ISMASKED_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_DATA0_ISMASKED_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_VALID_S 12 +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_VALID_M RDMA_BIT2(32, IG3_CORE_GLPE_PMF_TABLE_DATA0_VALID_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_TBL_IDX_S 0 +#define IG3_CORE_GLPE_PMF_TABLE_DATA0_TBL_IDX_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_PMF_TABLE_DATA0_TBL_IDX_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA1 0x420E1034 +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_RSVD_S 23 +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_CORE_GLPE_PMF_TABLE_DATA1_RSVD_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_HOSTID_S 20 +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_PMF_TABLE_DATA1_HOSTID_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_VDEV_VF_TYPE_S 18 +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_PMF_TABLE_DATA1_VDEV_VF_TYPE_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_VDEV_VF_S 6 +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_VDEV_VF_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_PMF_TABLE_DATA1_VDEV_VF_S) +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_PF_S 0 +#define IG3_CORE_GLPE_PMF_TABLE_DATA1_PF_M RDMA_MASK3(32, 0x3F, IG3_CORE_GLPE_PMF_TABLE_DATA1_PF_S) +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL 0x420E1038 +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_BUSY_S 31 +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_BUSY_M RDMA_BIT2(32, IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_BUSY_S) +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_RSVD_S 15 +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_RSVD_S) +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_OP_S 14 +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_OP_M RDMA_BIT2(32, IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_OP_S) +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_FTYPE_S 12 +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_FTYPE_S) +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_TBL_IDX_S 0 +#define IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_TBL_IDX_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_PRECACHE_TABLE_CTRL_TBL_IDX_S) +#define IG3_CORE_GLPE_PRECACHE_TABLE_DATA 0x420E103C +#define IG3_CORE_GLPE_PRECACHE_TABLE_DATA_RSVD_S 3 +#define IG3_CORE_GLPE_PRECACHE_TABLE_DATA_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_CORE_GLPE_PRECACHE_TABLE_DATA_RSVD_S) +#define IG3_CORE_GLPE_PRECACHE_TABLE_DATA_PROTOCOL_S 0 +#define IG3_CORE_GLPE_PRECACHE_TABLE_DATA_PROTOCOL_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_PRECACHE_TABLE_DATA_PROTOCOL_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHHI 0x420E1048 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_CORE_GLPE_SRQ_FWQPFLUSHHI_RSVD0_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHHI_QPID_S 6 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_GLPE_SRQ_FWQPFLUSHHI_QPID_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_CORE_GLPE_SRQ_FWQPFLUSHHI_PF_NUM_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO 0x420E1044 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_BUSY_S 31 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_BUSY_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_RSVD0_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_HOSTID_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_PMF_S 0 +#define IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_CORE_GLPE_SRQ_FWQPFLUSHLO_PMF_S) +#define IG3_CORE_GLPE_TMR_COMP 0x420E1040 +#define IG3_CORE_GLPE_TMR_COMP_RSVD_S 8 +#define IG3_CORE_GLPE_TMR_COMP_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CORE_GLPE_TMR_COMP_RSVD_S) +#define IG3_CORE_GLPE_TMR_COMP_COMP_S 0 +#define IG3_CORE_GLPE_TMR_COMP_COMP_M RDMA_MASK3(32, 0xFF, IG3_CORE_GLPE_TMR_COMP_COMP_S) +#define IG3_RLCR_GLPE_RLADDR 0x420E2010 +#define IG3_RLCR_GLPE_RLADDR_RSVD_S 13 +#define IG3_RLCR_GLPE_RLADDR_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_RLCR_GLPE_RLADDR_RSVD_S) +#define IG3_RLCR_GLPE_RLADDR_RL_ADDR_S 0 +#define IG3_RLCR_GLPE_RLADDR_RL_ADDR_M RDMA_MASK3(32, 0x1FFF, IG3_RLCR_GLPE_RLADDR_RL_ADDR_S) +#define IG3_RLCR_GLPE_RLC_DPC_COMP 0x420E2024 +#define IG3_RLCR_GLPE_RLC_DPC_COMP_RSVD_S 13 +#define IG3_RLCR_GLPE_RLC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_RLCR_GLPE_RLC_DPC_COMP_RSVD_S) +#define IG3_RLCR_GLPE_RLC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_RLCR_GLPE_RLC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_RLCR_GLPE_RLC_DPC_COMP_COMP_FTYPE_S) +#define IG3_RLCR_GLPE_RLC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_RLCR_GLPE_RLC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_RLCR_GLPE_RLC_DPC_COMP_COMP_FNUM_S) +#define IG3_RLCR_GLPE_RLC_DPC_COMP_COMP_VALID_S 0 +#define IG3_RLCR_GLPE_RLC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DPC_COMP_COMP_VALID_S) +#define IG3_RLCR_GLPE_RLC_DPC_REQ 0x420E2020 +#define IG3_RLCR_GLPE_RLC_DPC_REQ_RSVD_S 12 +#define IG3_RLCR_GLPE_RLC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCR_GLPE_RLC_DPC_REQ_RSVD_S) +#define IG3_RLCR_GLPE_RLC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_RLCR_GLPE_RLC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_RLCR_GLPE_RLC_DPC_REQ_REQ_FTYPE_S) +#define IG3_RLCR_GLPE_RLC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_RLCR_GLPE_RLC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_RLCR_GLPE_RLC_DPC_REQ_REQ_FNUM_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_COUNT 0x420E20B8 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_CMD 0x420E20CC +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_DATA_H 0x420E20D8 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_DATA_L 0x420E20D4 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_PTR 0x420E20D0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_CMD 0x420E20BC +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_DATA_H 0x420E20C8 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_DATA_L 0x420E20C4 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_PTR 0x420E20C0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCR_GLPE_RLC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL 0x420E2080 +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD1_S 25 +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD2_S 17 +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD2_S) +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD3_S 9 +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD3_S) +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_BYPASS_S 8 +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_CONTROL_BYPASS_S) +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD4_S 1 +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_RLCR_GLPE_RLC_DTM_CONTROL_RSVD4_S) +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_RLCR_GLPE_RLC_DTM_ECC_COR_ERR 0x420E20E8 +#define IG3_RLCR_GLPE_RLC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_RLCR_GLPE_RLC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCR_GLPE_RLC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_RLCR_GLPE_RLC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RLCR_GLPE_RLC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_RLCR_GLPE_RLC_DTM_ECC_UNCOR_ERR 0x420E20E4 +#define IG3_RLCR_GLPE_RLC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_RLCR_GLPE_RLC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCR_GLPE_RLC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_RLCR_GLPE_RLC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RLCR_GLPE_RLC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG 0x420E208C +#define IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_RLCR_GLPE_RLC_DTM_LOG_CFG 0x420E2090 +#define IG3_RLCR_GLPE_RLC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_RLCR_GLPE_RLC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_RLCR_GLPE_RLC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_RLCR_GLPE_RLC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_RLCR_GLPE_RLC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_RLCR_GLPE_RLC_DTM_LOG_CFG_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_LOG_CFG_MODE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_RLCR_GLPE_RLC_DTM_LOG_CFG_MODE_S) +#define IG3_RLCR_GLPE_RLC_DTM_LOG_MASK 0x420E2098 +#define IG3_RLCR_GLPE_RLC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_LOG_MASK_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_LOG_PATTERN 0x420E2094 +#define IG3_RLCR_GLPE_RLC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG 0x420E2084 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_STS 0x420E2088 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_RSVD2_S) +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TIMESTAMP 0x420E20B0 +#define IG3_RLCR_GLPE_RLC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_TIMESTAMP_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TIMESTAMP_ROLLOVER 0x420E20B4 +#define IG3_RLCR_GLPE_RLC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG 0x420E20DC +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS 0x420E20E0 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG 0x420E209C +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_RLCR_GLPE_RLC_DTM_TRIG_CFG_MODE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_COUNT 0x420E20A8 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_MASK 0x420E20A4 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_TRIG_MASK_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_PATTERN 0x420E20A0 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_TIMESTAMP 0x420E20AC +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_RLCR_GLPE_RLC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_RLCR_GLPE_RLC_ERRDATA 0x420E201C +#define IG3_RLCR_GLPE_RLC_ERRDATA_Q_NUM_S 8 +#define IG3_RLCR_GLPE_RLC_ERRDATA_Q_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_RLCR_GLPE_RLC_ERRDATA_Q_NUM_S) +#define IG3_RLCR_GLPE_RLC_ERRDATA_RSVD0_S 7 +#define IG3_RLCR_GLPE_RLC_ERRDATA_RSVD0_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_ERRDATA_RSVD0_S) +#define IG3_RLCR_GLPE_RLC_ERRDATA_Q_TYPE_S 4 +#define IG3_RLCR_GLPE_RLC_ERRDATA_Q_TYPE_M RDMA_MASK3(32, 0x7, IG3_RLCR_GLPE_RLC_ERRDATA_Q_TYPE_S) +#define IG3_RLCR_GLPE_RLC_ERRDATA_ERROR_CODE_S 0 +#define IG3_RLCR_GLPE_RLC_ERRDATA_ERROR_CODE_M RDMA_MASK3(32, 0xF, IG3_RLCR_GLPE_RLC_ERRDATA_ERROR_CODE_S) +#define IG3_RLCR_GLPE_RLC_ERRINFO 0x420E2018 +#define IG3_RLCR_GLPE_RLC_ERRINFO_RLS_ERROR_CNT_S 24 +#define IG3_RLCR_GLPE_RLC_ERRINFO_RLS_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_ERRINFO_RLS_ERROR_CNT_S) +#define IG3_RLCR_GLPE_RLC_ERRINFO_RLU_ERROR_CNT_S 16 +#define IG3_RLCR_GLPE_RLC_ERRINFO_RLU_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_ERRINFO_RLU_ERROR_CNT_S) +#define IG3_RLCR_GLPE_RLC_ERRINFO_DBL_ERROR_CNT_S 8 +#define IG3_RLCR_GLPE_RLC_ERRINFO_DBL_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_RLCR_GLPE_RLC_ERRINFO_DBL_ERROR_CNT_S) +#define IG3_RLCR_GLPE_RLC_ERRINFO_RSVD1_S 7 +#define IG3_RLCR_GLPE_RLC_ERRINFO_RSVD1_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_ERRINFO_RSVD1_S) +#define IG3_RLCR_GLPE_RLC_ERRINFO_ERROR_INST_S 4 +#define IG3_RLCR_GLPE_RLC_ERRINFO_ERROR_INST_M RDMA_MASK3(32, 0x7, IG3_RLCR_GLPE_RLC_ERRINFO_ERROR_INST_S) +#define IG3_RLCR_GLPE_RLC_ERRINFO_RSVD0_S 1 +#define IG3_RLCR_GLPE_RLC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7, IG3_RLCR_GLPE_RLC_ERRINFO_RSVD0_S) +#define IG3_RLCR_GLPE_RLC_ERRINFO_ERROR_VALID_S 0 +#define IG3_RLCR_GLPE_RLC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLC_ERRINFO_ERROR_VALID_S) +#define IG3_RLCR_GLPE_RLDATA 0x420E2014 +#define IG3_RLCR_GLPE_RLDATA_RL_DATA_S 0 +#define IG3_RLCR_GLPE_RLDATA_RL_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCR_GLPE_RLDATA_RL_DATA_S) +#define IG3_RLCR_GLPE_RLQUERY(_i) 0x420E2000 + ((_i) * 4) /* _i=0...1 */ +#define IG3_RLCR_GLPE_RLQUERY_MAX_INDEX_I 1 +#define IG3_RLCR_GLPE_RLQUERY_RSVD_S 12 +#define IG3_RLCR_GLPE_RLQUERY_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCR_GLPE_RLQUERY_RSVD_S) +#define IG3_RLCR_GLPE_RLQUERY_RLINDEX_S 0 +#define IG3_RLCR_GLPE_RLQUERY_RLINDEX_M RDMA_MASK3(32, 0xFFF, IG3_RLCR_GLPE_RLQUERY_RLINDEX_S) +#define IG3_RLCR_GLPE_RLSTAT(_i) 0x420E2008 + ((_i) * 4) /* _i=0...1 */ +#define IG3_RLCR_GLPE_RLSTAT_MAX_INDEX_I 1 +#define IG3_RLCR_GLPE_RLSTAT_RSVD_S 2 +#define IG3_RLCR_GLPE_RLSTAT_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_RLCR_GLPE_RLSTAT_RSVD_S) +#define IG3_RLCR_GLPE_RLSTAT_RL_EMPTY_S 1 +#define IG3_RLCR_GLPE_RLSTAT_RL_EMPTY_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLSTAT_RL_EMPTY_S) +#define IG3_RLCR_GLPE_RLSTAT_QUERY_DONE_S 0 +#define IG3_RLCR_GLPE_RLSTAT_QUERY_DONE_M RDMA_BIT2(32, IG3_RLCR_GLPE_RLSTAT_QUERY_DONE_S) +#define IG3_RLCC_GLPE_RLADDR 0x420E2410 +#define IG3_RLCC_GLPE_RLADDR_RSVD_S 13 +#define IG3_RLCC_GLPE_RLADDR_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_RLCC_GLPE_RLADDR_RSVD_S) +#define IG3_RLCC_GLPE_RLADDR_RL_ADDR_S 0 +#define IG3_RLCC_GLPE_RLADDR_RL_ADDR_M RDMA_MASK3(32, 0x1FFF, IG3_RLCC_GLPE_RLADDR_RL_ADDR_S) +#define IG3_RLCC_GLPE_RLC_DPC_COMP 0x420E2424 +#define IG3_RLCC_GLPE_RLC_DPC_COMP_RSVD_S 13 +#define IG3_RLCC_GLPE_RLC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_RLCC_GLPE_RLC_DPC_COMP_RSVD_S) +#define IG3_RLCC_GLPE_RLC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_RLCC_GLPE_RLC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_RLCC_GLPE_RLC_DPC_COMP_COMP_FTYPE_S) +#define IG3_RLCC_GLPE_RLC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_RLCC_GLPE_RLC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_RLCC_GLPE_RLC_DPC_COMP_COMP_FNUM_S) +#define IG3_RLCC_GLPE_RLC_DPC_COMP_COMP_VALID_S 0 +#define IG3_RLCC_GLPE_RLC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DPC_COMP_COMP_VALID_S) +#define IG3_RLCC_GLPE_RLC_DPC_REQ 0x420E2420 +#define IG3_RLCC_GLPE_RLC_DPC_REQ_RSVD_S 12 +#define IG3_RLCC_GLPE_RLC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCC_GLPE_RLC_DPC_REQ_RSVD_S) +#define IG3_RLCC_GLPE_RLC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_RLCC_GLPE_RLC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_RLCC_GLPE_RLC_DPC_REQ_REQ_FTYPE_S) +#define IG3_RLCC_GLPE_RLC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_RLCC_GLPE_RLC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_RLCC_GLPE_RLC_DPC_REQ_REQ_FNUM_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_COUNT 0x420E24B8 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_CMD 0x420E24CC +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_DATA_H 0x420E24D8 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_DATA_L 0x420E24D4 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_PTR 0x420E24D0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_CMD 0x420E24BC +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_DATA_H 0x420E24C8 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_DATA_L 0x420E24C4 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_PTR 0x420E24C0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCC_GLPE_RLC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL 0x420E2480 +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD1_S 25 +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD2_S 17 +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD2_S) +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD3_S 9 +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD3_S) +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_BYPASS_S 8 +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_CONTROL_BYPASS_S) +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD4_S 1 +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_RLCC_GLPE_RLC_DTM_CONTROL_RSVD4_S) +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_RLCC_GLPE_RLC_DTM_ECC_COR_ERR 0x420E24E8 +#define IG3_RLCC_GLPE_RLC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_RLCC_GLPE_RLC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCC_GLPE_RLC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_RLCC_GLPE_RLC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RLCC_GLPE_RLC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_RLCC_GLPE_RLC_DTM_ECC_UNCOR_ERR 0x420E24E4 +#define IG3_RLCC_GLPE_RLC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_RLCC_GLPE_RLC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCC_GLPE_RLC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_RLCC_GLPE_RLC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RLCC_GLPE_RLC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG 0x420E248C +#define IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_RLCC_GLPE_RLC_DTM_LOG_CFG 0x420E2490 +#define IG3_RLCC_GLPE_RLC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_RLCC_GLPE_RLC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_RLCC_GLPE_RLC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_RLCC_GLPE_RLC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_RLCC_GLPE_RLC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_RLCC_GLPE_RLC_DTM_LOG_CFG_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_LOG_CFG_MODE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_RLCC_GLPE_RLC_DTM_LOG_CFG_MODE_S) +#define IG3_RLCC_GLPE_RLC_DTM_LOG_MASK 0x420E2498 +#define IG3_RLCC_GLPE_RLC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_LOG_MASK_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_LOG_PATTERN 0x420E2494 +#define IG3_RLCC_GLPE_RLC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG 0x420E2484 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_STS 0x420E2488 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_RSVD2_S) +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TIMESTAMP 0x420E24B0 +#define IG3_RLCC_GLPE_RLC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_TIMESTAMP_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TIMESTAMP_ROLLOVER 0x420E24B4 +#define IG3_RLCC_GLPE_RLC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG 0x420E24DC +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS 0x420E24E0 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG 0x420E249C +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_RLCC_GLPE_RLC_DTM_TRIG_CFG_MODE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_COUNT 0x420E24A8 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_MASK 0x420E24A4 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_TRIG_MASK_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_PATTERN 0x420E24A0 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_TIMESTAMP 0x420E24AC +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_RLCC_GLPE_RLC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_RLCC_GLPE_RLC_ERRDATA 0x420E241C +#define IG3_RLCC_GLPE_RLC_ERRDATA_Q_NUM_S 8 +#define IG3_RLCC_GLPE_RLC_ERRDATA_Q_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_RLCC_GLPE_RLC_ERRDATA_Q_NUM_S) +#define IG3_RLCC_GLPE_RLC_ERRDATA_RSVD0_S 7 +#define IG3_RLCC_GLPE_RLC_ERRDATA_RSVD0_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_ERRDATA_RSVD0_S) +#define IG3_RLCC_GLPE_RLC_ERRDATA_Q_TYPE_S 4 +#define IG3_RLCC_GLPE_RLC_ERRDATA_Q_TYPE_M RDMA_MASK3(32, 0x7, IG3_RLCC_GLPE_RLC_ERRDATA_Q_TYPE_S) +#define IG3_RLCC_GLPE_RLC_ERRDATA_ERROR_CODE_S 0 +#define IG3_RLCC_GLPE_RLC_ERRDATA_ERROR_CODE_M RDMA_MASK3(32, 0xF, IG3_RLCC_GLPE_RLC_ERRDATA_ERROR_CODE_S) +#define IG3_RLCC_GLPE_RLC_ERRINFO 0x420E2418 +#define IG3_RLCC_GLPE_RLC_ERRINFO_RLS_ERROR_CNT_S 24 +#define IG3_RLCC_GLPE_RLC_ERRINFO_RLS_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_ERRINFO_RLS_ERROR_CNT_S) +#define IG3_RLCC_GLPE_RLC_ERRINFO_RLU_ERROR_CNT_S 16 +#define IG3_RLCC_GLPE_RLC_ERRINFO_RLU_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_ERRINFO_RLU_ERROR_CNT_S) +#define IG3_RLCC_GLPE_RLC_ERRINFO_DBL_ERROR_CNT_S 8 +#define IG3_RLCC_GLPE_RLC_ERRINFO_DBL_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_RLCC_GLPE_RLC_ERRINFO_DBL_ERROR_CNT_S) +#define IG3_RLCC_GLPE_RLC_ERRINFO_RSVD1_S 7 +#define IG3_RLCC_GLPE_RLC_ERRINFO_RSVD1_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_ERRINFO_RSVD1_S) +#define IG3_RLCC_GLPE_RLC_ERRINFO_ERROR_INST_S 4 +#define IG3_RLCC_GLPE_RLC_ERRINFO_ERROR_INST_M RDMA_MASK3(32, 0x7, IG3_RLCC_GLPE_RLC_ERRINFO_ERROR_INST_S) +#define IG3_RLCC_GLPE_RLC_ERRINFO_RSVD0_S 1 +#define IG3_RLCC_GLPE_RLC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7, IG3_RLCC_GLPE_RLC_ERRINFO_RSVD0_S) +#define IG3_RLCC_GLPE_RLC_ERRINFO_ERROR_VALID_S 0 +#define IG3_RLCC_GLPE_RLC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLC_ERRINFO_ERROR_VALID_S) +#define IG3_RLCC_GLPE_RLDATA 0x420E2414 +#define IG3_RLCC_GLPE_RLDATA_RL_DATA_S 0 +#define IG3_RLCC_GLPE_RLDATA_RL_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RLCC_GLPE_RLDATA_RL_DATA_S) +#define IG3_RLCC_GLPE_RLQUERY(_i) 0x420E2400 + ((_i) * 4) /* _i=0...1 */ +#define IG3_RLCC_GLPE_RLQUERY_MAX_INDEX_I 1 +#define IG3_RLCC_GLPE_RLQUERY_RSVD_S 12 +#define IG3_RLCC_GLPE_RLQUERY_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RLCC_GLPE_RLQUERY_RSVD_S) +#define IG3_RLCC_GLPE_RLQUERY_RLINDEX_S 0 +#define IG3_RLCC_GLPE_RLQUERY_RLINDEX_M RDMA_MASK3(32, 0xFFF, IG3_RLCC_GLPE_RLQUERY_RLINDEX_S) +#define IG3_RLCC_GLPE_RLSTAT(_i) 0x420E2408 + ((_i) * 4) /* _i=0...1 */ +#define IG3_RLCC_GLPE_RLSTAT_MAX_INDEX_I 1 +#define IG3_RLCC_GLPE_RLSTAT_RSVD_S 2 +#define IG3_RLCC_GLPE_RLSTAT_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_RLCC_GLPE_RLSTAT_RSVD_S) +#define IG3_RLCC_GLPE_RLSTAT_RL_EMPTY_S 1 +#define IG3_RLCC_GLPE_RLSTAT_RL_EMPTY_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLSTAT_RL_EMPTY_S) +#define IG3_RLCC_GLPE_RLSTAT_QUERY_DONE_S 0 +#define IG3_RLCC_GLPE_RLSTAT_QUERY_DONE_M RDMA_BIT2(32, IG3_RLCC_GLPE_RLSTAT_QUERY_DONE_S) +#define IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS 0x420E2830 +#define IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS_RSVD_S 3 +#define IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS_RSVD_S) +#define IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS_DISABLE_S 2 +#define IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS_DISABLE_M RDMA_BIT2(32, IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS_DISABLE_S) +#define IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS_STOP_SCREAM_STAT_S 0 +#define IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS_STOP_SCREAM_STAT_M RDMA_MASK3(32, 0x3, IG3_CEH_GLGEN_PE_STOP_SCREAM_RAS_STOP_SCREAM_STAT_S) +#define IG3_CEH_GLPE_CRITERR_MODMASK 0x420E2804 +#define IG3_CEH_GLPE_CRITERR_MODMASK_MODULE_MASK0_S 1 +#define IG3_CEH_GLPE_CRITERR_MODMASK_MODULE_MASK0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CEH_GLPE_CRITERR_MODMASK_MODULE_MASK0_S) +#define IG3_CEH_GLPE_CRITERR_MODMASK_RSVD_S 0 +#define IG3_CEH_GLPE_CRITERR_MODMASK_RSVD_M RDMA_BIT2(32, IG3_CEH_GLPE_CRITERR_MODMASK_RSVD_S) +#define IG3_CEH_GLPE_CRITERR_MODMASK1 0x420E2808 +#define IG3_CEH_GLPE_CRITERR_MODMASK1_MODULE_MASK_S 0 +#define IG3_CEH_GLPE_CRITERR_MODMASK1_MODULE_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CEH_GLPE_CRITERR_MODMASK1_MODULE_MASK_S) +#define IG3_CEH_GLPE_CRITERR_MODMASK2 0x420E280C +#define IG3_CEH_GLPE_CRITERR_MODMASK2_MODULE_MASK_S 0 +#define IG3_CEH_GLPE_CRITERR_MODMASK2_MODULE_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CEH_GLPE_CRITERR_MODMASK2_MODULE_MASK_S) +#define IG3_CEH_GLPE_CRITERR_STATUS 0x420E2800 +#define IG3_CEH_GLPE_CRITERR_STATUS_RSVD_S 17 +#define IG3_CEH_GLPE_CRITERR_STATUS_RSVD_M RDMA_MASK3(32, 0x7FFF, IG3_CEH_GLPE_CRITERR_STATUS_RSVD_S) +#define IG3_CEH_GLPE_CRITERR_STATUS_ERROR_SET_S 16 +#define IG3_CEH_GLPE_CRITERR_STATUS_ERROR_SET_M RDMA_BIT2(32, IG3_CEH_GLPE_CRITERR_STATUS_ERROR_SET_S) +#define IG3_CEH_GLPE_CRITERR_STATUS_ERROR_MODULE_S 8 +#define IG3_CEH_GLPE_CRITERR_STATUS_ERROR_MODULE_M RDMA_MASK3(32, 0xFF, IG3_CEH_GLPE_CRITERR_STATUS_ERROR_MODULE_S) +#define IG3_CEH_GLPE_CRITERR_STATUS_ERROR_TYPE_S 6 +#define IG3_CEH_GLPE_CRITERR_STATUS_ERROR_TYPE_M RDMA_MASK3(32, 0x3, IG3_CEH_GLPE_CRITERR_STATUS_ERROR_TYPE_S) +#define IG3_CEH_GLPE_CRITERR_STATUS_ERROR_INST_S 0 +#define IG3_CEH_GLPE_CRITERR_STATUS_ERROR_INST_M RDMA_MASK3(32, 0x3F, IG3_CEH_GLPE_CRITERR_STATUS_ERROR_INST_S) +#define IG3_CEH_GLPE_CRITERR_TRGTMASK(_i) 0x420E2810 + ((_i) * 4) /* _i=0...7 */ +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_MAX_INDEX_I 7 +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_1_MODULE_S 24 +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_1_MODULE_M RDMA_MASK3(32, 0xFF, IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_1_MODULE_S) +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_1_TYPE_S 22 +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_1_TYPE_M RDMA_MASK3(32, 0x3, IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_1_TYPE_S) +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_1_INST_S 16 +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_1_INST_M RDMA_MASK3(32, 0x3F, IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_1_INST_S) +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_0_MODULE_S 8 +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_0_MODULE_M RDMA_MASK3(32, 0xFF, IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_0_MODULE_S) +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_0_TYPE_S 6 +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_0_TYPE_M RDMA_MASK3(32, 0x3, IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_0_TYPE_S) +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_0_INST_S 0 +#define IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_0_INST_M RDMA_MASK3(32, 0x3F, IG3_CEH_GLPE_CRITERR_TRGTMASK_TRGT_MATCH_0_INST_S) +#define IG3_TMGR_GLPE_TMGR_CLIENTREQ_HI 0x420E2C44 +#define IG3_TMGR_GLPE_TMGR_CLIENTREQ_HI_CLIENTREQ_HI_S 0 +#define IG3_TMGR_GLPE_TMGR_CLIENTREQ_HI_CLIENTREQ_HI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CLIENTREQ_HI_CLIENTREQ_HI_S) +#define IG3_TMGR_GLPE_TMGR_CLIENTREQ_LO 0x420E2C40 +#define IG3_TMGR_GLPE_TMGR_CLIENTREQ_LO_CLIENTREQ_LO_S 0 +#define IG3_TMGR_GLPE_TMGR_CLIENTREQ_LO_CLIENTREQ_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CLIENTREQ_LO_CLIENTREQ_LO_S) +#define IG3_TMGR_GLPE_TMGR_CLIENTRESP_HI 0x420E2C4C +#define IG3_TMGR_GLPE_TMGR_CLIENTRESP_HI_CLIENTRESP_HI_S 0 +#define IG3_TMGR_GLPE_TMGR_CLIENTRESP_HI_CLIENTRESP_HI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CLIENTRESP_HI_CLIENTRESP_HI_S) +#define IG3_TMGR_GLPE_TMGR_CLIENTRESP_LO 0x420E2C48 +#define IG3_TMGR_GLPE_TMGR_CLIENTRESP_LO_CLIENTRESP_LO_S 0 +#define IG3_TMGR_GLPE_TMGR_CLIENTRESP_LO_CLIENTRESP_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CLIENTRESP_LO_CLIENTRESP_LO_S) +#define IG3_TMGR_GLPE_TMGR_CMSNOOPMISS_HI 0x420E2C64 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPMISS_HI_CMSNOOPMISS_HI_S 0 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPMISS_HI_CMSNOOPMISS_HI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CMSNOOPMISS_HI_CMSNOOPMISS_HI_S) +#define IG3_TMGR_GLPE_TMGR_CMSNOOPMISS_LO 0x420E2C60 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPMISS_LO_CMSNOOPMISS_LOW_S 0 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPMISS_LO_CMSNOOPMISS_LOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CMSNOOPMISS_LO_CMSNOOPMISS_LOW_S) +#define IG3_TMGR_GLPE_TMGR_CMSNOOPREQ_HI 0x420E2C54 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPREQ_HI_CMSNOOPREQ_HI_S 0 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPREQ_HI_CMSNOOPREQ_HI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CMSNOOPREQ_HI_CMSNOOPREQ_HI_S) +#define IG3_TMGR_GLPE_TMGR_CMSNOOPREQ_LO 0x420E2C50 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPREQ_LO_CMSNOOPREQ_LO_S 0 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPREQ_LO_CMSNOOPREQ_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CMSNOOPREQ_LO_CMSNOOPREQ_LO_S) +#define IG3_TMGR_GLPE_TMGR_CMSNOOPRESP_HI 0x420E2C5C +#define IG3_TMGR_GLPE_TMGR_CMSNOOPRESP_HI_CMSNOOPRESP_HI_S 0 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPRESP_HI_CMSNOOPRESP_HI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CMSNOOPRESP_HI_CMSNOOPRESP_HI_S) +#define IG3_TMGR_GLPE_TMGR_CMSNOOPRESP_LO 0x420E2C58 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPRESP_LO_CMSNOOPRESP_LO_S 0 +#define IG3_TMGR_GLPE_TMGR_CMSNOOPRESP_LO_CMSNOOPRESP_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_CMSNOOPRESP_LO_CMSNOOPRESP_LO_S) +#define IG3_TMGR_GLPE_TMGR_COALESCE_HI 0x420E2C3C +#define IG3_TMGR_GLPE_TMGR_COALESCE_HI_COALESCE_HI_S 0 +#define IG3_TMGR_GLPE_TMGR_COALESCE_HI_COALESCE_HI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_COALESCE_HI_COALESCE_HI_S) +#define IG3_TMGR_GLPE_TMGR_COALESCE_LO 0x420E2C38 +#define IG3_TMGR_GLPE_TMGR_COALESCE_LO_COALESCE_LO_S 0 +#define IG3_TMGR_GLPE_TMGR_COALESCE_LO_COALESCE_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_COALESCE_LO_COALESCE_LO_S) +#define IG3_TMGR_GLPE_TMGR_CONFIG(_i) 0x420E2C04 + ((_i) * 4) /* _i=0...4 */ +#define IG3_TMGR_GLPE_TMGR_CONFIG_MAX_INDEX_I 4 +#define IG3_TMGR_GLPE_TMGR_CONFIG_RSVD2_S 25 +#define IG3_TMGR_GLPE_TMGR_CONFIG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_TMGR_GLPE_TMGR_CONFIG_RSVD2_S) +#define IG3_TMGR_GLPE_TMGR_CONFIG_NUM_AVAIL_OFFSET_S 16 +#define IG3_TMGR_GLPE_TMGR_CONFIG_NUM_AVAIL_OFFSET_M RDMA_MASK3(32, 0x1FF, IG3_TMGR_GLPE_TMGR_CONFIG_NUM_AVAIL_OFFSET_S) +#define IG3_TMGR_GLPE_TMGR_CONFIG_RSVD1_S 10 +#define IG3_TMGR_GLPE_TMGR_CONFIG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_TMGR_GLPE_TMGR_CONFIG_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_CONFIG_SEL_MODE_S 8 +#define IG3_TMGR_GLPE_TMGR_CONFIG_SEL_MODE_M RDMA_MASK3(32, 0x3, IG3_TMGR_GLPE_TMGR_CONFIG_SEL_MODE_S) +#define IG3_TMGR_GLPE_TMGR_CONFIG_RSVD0_S 5 +#define IG3_TMGR_GLPE_TMGR_CONFIG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_TMGR_GLPE_TMGR_CONFIG_RSVD0_S) +#define IG3_TMGR_GLPE_TMGR_CONFIG_TILE_ASSIGNMENT_S 0 +#define IG3_TMGR_GLPE_TMGR_CONFIG_TILE_ASSIGNMENT_M RDMA_MASK3(32, 0x1F, IG3_TMGR_GLPE_TMGR_CONFIG_TILE_ASSIGNMENT_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL 0x420E2C2C +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_DEBUG_MODE_S 16 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_DEBUG_MODE_M RDMA_MASK3(32, 0xFFFF, IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_DEBUG_MODE_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_DEBUG_VALUE_S 4 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_DEBUG_VALUE_M RDMA_MASK3(32, 0xFFF, IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_DEBUG_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_SW_RESET_S 3 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_SW_RESET_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_SW_RESET_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_ENABLE_STATS_S 2 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_ENABLE_STATS_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_ENABLE_STATS_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_CLEAR_STATS_S 1 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_CLEAR_STATS_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_CLEAR_STATS_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_STOP_CLIENT_IF_S 0 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_STOP_CLIENT_IF_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATS_CTL_STOP_CLIENT_IF_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1 0x420E2C30 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_RSVD1_S 31 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_RSVD1_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_DOUT_CLIENT_ID_S 27 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_DOUT_CLIENT_ID_M RDMA_MASK3(32, 0xF, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_DOUT_CLIENT_ID_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_PKT_CNT_COMPLETE_WR_ERR_S 26 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_PKT_CNT_COMPLETE_WR_ERR_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_PKT_CNT_COMPLETE_WR_ERR_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_OVERFLOW_S 25 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_OVERFLOW_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_OVERFLOW_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_UNDERFLOW_S 24 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_UNDERFLOW_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_UNDERFLOW_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_FULL_SPACE_S 18 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_FULL_SPACE_M RDMA_MASK3(32, 0x3F, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_ORD_FIFO_FULL_SPACE_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_PKT_CNT_PENDING_WR_ERR_S 17 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_PKT_CNT_PENDING_WR_ERR_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_PKT_CNT_PENDING_WR_ERR_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_REQ_FIFO_OVERFLOW_S 16 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_REQ_FIFO_OVERFLOW_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_REQ_FIFO_OVERFLOW_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_REQ_FIFO_UNDERFLOW_S 15 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_REQ_FIFO_UNDERFLOW_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_REQ_FIFO_UNDERFLOW_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_REQ_FIFO_FULL_SPACE_S 9 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_REQ_FIFO_FULL_SPACE_M RDMA_MASK3(32, 0x3F, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_REQ_FIFO_FULL_SPACE_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_PKT_CNT_OUTSTANDING_WR_ERR_S 8 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_PKT_CNT_OUTSTANDING_WR_ERR_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_PKT_CNT_OUTSTANDING_WR_ERR_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_OUT_FIFO_OVERFLOW_S 7 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_OUT_FIFO_OVERFLOW_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_OUT_FIFO_OVERFLOW_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_OUT_FIFO_UNDERFLOW_S 6 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_OUT_FIFO_UNDERFLOW_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_OUT_FIFO_UNDERFLOW_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_OUT_FIFO_FULL_SPACE_S 0 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_OUT_FIFO_FULL_SPACE_M RDMA_MASK3(32, 0x3F, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS1_CSR_OUT_FIFO_FULL_SPACE_S) +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS2 0x420E2C34 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS2_TMGR_DEBUG_STATUS2_S 0 +#define IG3_TMGR_GLPE_TMGR_DEBUG_STATUS2_TMGR_DEBUG_STATUS2_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DEBUG_STATUS2_TMGR_DEBUG_STATUS2_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_COUNT 0x420E2CB8 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_CMD 0x420E2CCC +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_DATA_H 0x420E2CD8 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_DATA_L 0x420E2CD4 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_PTR 0x420E2CD0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_CMD 0x420E2CBC +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_DATA_H 0x420E2CC8 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_DATA_L 0x420E2CC4 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_PTR 0x420E2CC0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_TMGR_GLPE_TMGR_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL 0x420E2C80 +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD1_S 25 +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD2_S 17 +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD2_S) +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD3_S 9 +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD3_S) +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_BYPASS_S 8 +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_CONTROL_BYPASS_S) +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD4_S 1 +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_TMGR_GLPE_TMGR_DTM_CONTROL_RSVD4_S) +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_CONTROL_LOCAL_EN_S) +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_COR_ERR 0x420E2CE8 +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TMGR_GLPE_TMGR_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TMGR_GLPE_TMGR_DTM_ECC_COR_ERR_CNT_S) +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_UNCOR_ERR 0x420E2CE4 +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TMGR_GLPE_TMGR_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TMGR_GLPE_TMGR_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG 0x420E2C8C +#define IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_TMGR_GLPE_TMGR_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG 0x420E2C90 +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG_MODE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_TMGR_GLPE_TMGR_DTM_LOG_CFG_MODE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_MASK 0x420E2C98 +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_MASK_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_LOG_MASK_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_PATTERN 0x420E2C94 +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_LOG_PATTERN_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG 0x420E2C84 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_RSVD2_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_RSVD3_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS 0x420E2C88 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_RSVD2_S) +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TIMESTAMP 0x420E2CB0 +#define IG3_TMGR_GLPE_TMGR_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_TIMESTAMP_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TIMESTAMP_ROLLOVER 0x420E2CB4 +#define IG3_TMGR_GLPE_TMGR_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG 0x420E2CDC +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS 0x420E2CE0 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TMGR_GLPE_TMGR_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG 0x420E2C9C +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_RSVD2_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_MODE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_TMGR_GLPE_TMGR_DTM_TRIG_CFG_MODE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_COUNT 0x420E2CA8 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_TRIG_COUNT_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_MASK 0x420E2CA4 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_TRIG_MASK_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_PATTERN 0x420E2CA0 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_TIMESTAMP 0x420E2CAC +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_TMGR_GLPE_TMGR_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TMGR_GLPE_TMGR_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_TMGR_GLPE_TMGR_SELECTION 0x420E2C00 +#define IG3_TMGR_GLPE_TMGR_SELECTION_RSVD1_S 3 +#define IG3_TMGR_GLPE_TMGR_SELECTION_RSVD1_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_TMGR_GLPE_TMGR_SELECTION_RSVD1_S) +#define IG3_TMGR_GLPE_TMGR_SELECTION_TILE_ASSIGNMENT_S 0 +#define IG3_TMGR_GLPE_TMGR_SELECTION_TILE_ASSIGNMENT_M RDMA_MASK3(32, 0x7, IG3_TMGR_GLPE_TMGR_SELECTION_TILE_ASSIGNMENT_S) +#define IG3_TMGR_GLPE_TMGR_STATUS(_i) 0x420E2C18 + ((_i) * 4) /* _i=0...4 */ +#define IG3_TMGR_GLPE_TMGR_STATUS_MAX_INDEX_I 4 +#define IG3_TMGR_GLPE_TMGR_STATUS_RSVD_S 16 +#define IG3_TMGR_GLPE_TMGR_STATUS_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_TMGR_GLPE_TMGR_STATUS_RSVD_S) +#define IG3_TMGR_GLPE_TMGR_STATUS_NUM_CACHELINE_S 0 +#define IG3_TMGR_GLPE_TMGR_STATUS_NUM_CACHELINE_M RDMA_MASK3(32, 0xFFFF, IG3_TMGR_GLPE_TMGR_STATUS_NUM_CACHELINE_S) +#define IG3_SQCE_GLPE_SQCE_CONFIG 0x420E3070 +#define IG3_SQCE_GLPE_SQCE_CONFIG_RSVD_S 3 +#define IG3_SQCE_GLPE_SQCE_CONFIG_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SQCE_GLPE_SQCE_CONFIG_RSVD_S) +#define IG3_SQCE_GLPE_SQCE_CONFIG_CRT_XMIT_RAM_EN_S 2 +#define IG3_SQCE_GLPE_SQCE_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_SQCE_GLPE_SQCE_CONFIG_DBL_DIS_S 1 +#define IG3_SQCE_GLPE_SQCE_CONFIG_DBL_DIS_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_CONFIG_DBL_DIS_S) +#define IG3_SQCE_GLPE_SQCE_CONFIG_COALESCE_DIS_S 0 +#define IG3_SQCE_GLPE_SQCE_CONFIG_COALESCE_DIS_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_CONFIG_COALESCE_DIS_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_COUNT 0x420E30B8 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_CMD 0x420E30CC +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_DATA_H 0x420E30D8 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_DATA_L 0x420E30D4 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_PTR 0x420E30D0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_CMD 0x420E30BC +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_DATA_H 0x420E30C8 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_DATA_L 0x420E30C4 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_PTR 0x420E30C0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQCE_GLPE_SQCE_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL 0x420E3080 +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD1_S 25 +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD2_S 17 +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD2_S) +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD3_S 9 +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD3_S) +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_BYPASS_S 8 +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_CONTROL_BYPASS_S) +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD4_S 1 +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SQCE_GLPE_SQCE_DTM_CONTROL_RSVD4_S) +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_COR_ERR 0x420E30E8 +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQCE_GLPE_SQCE_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GLPE_SQCE_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_UNCOR_ERR 0x420E30E4 +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQCE_GLPE_SQCE_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GLPE_SQCE_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG 0x420E308C +#define IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQCE_GLPE_SQCE_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG 0x420E3090 +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG_MODE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SQCE_GLPE_SQCE_DTM_LOG_CFG_MODE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_MASK 0x420E3098 +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_LOG_MASK_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_PATTERN 0x420E3094 +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG 0x420E3084 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS 0x420E3088 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_RSVD2_S) +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TIMESTAMP 0x420E30B0 +#define IG3_SQCE_GLPE_SQCE_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_TIMESTAMP_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TIMESTAMP_ROLLOVER 0x420E30B4 +#define IG3_SQCE_GLPE_SQCE_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG 0x420E30DC +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS 0x420E30E0 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG 0x420E309C +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SQCE_GLPE_SQCE_DTM_TRIG_CFG_MODE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_COUNT 0x420E30A8 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_MASK 0x420E30A4 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_TRIG_MASK_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_PATTERN 0x420E30A0 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_TIMESTAMP 0x420E30AC +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SQCE_GLPE_SQCE_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQCE_GLPE_SQCE_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRDROP(_i) 0x420E3040 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQCE_GLPE_SQCE_FWFLRDROP_MAX_INDEX_I 7 +#define IG3_SQCE_GLPE_SQCE_FWFLRDROP_EN_S 31 +#define IG3_SQCE_GLPE_SQCE_FWFLRDROP_EN_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_FWFLRDROP_EN_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRDROP_RSVD0_S 12 +#define IG3_SQCE_GLPE_SQCE_FWFLRDROP_RSVD0_M RDMA_MASK3(32, 0x7FFFF, IG3_SQCE_GLPE_SQCE_FWFLRDROP_RSVD0_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRDROP_PMF_S 0 +#define IG3_SQCE_GLPE_SQCE_FWFLRDROP_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GLPE_SQCE_FWFLRDROP_PMF_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI 0x420E3060 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI_RSVD0_S 26 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI_RSVD0_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI_QPID_S 6 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI_QPID_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI_PF_NUM_S 0 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHHI_PF_NUM_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO 0x420E3064 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_BUSY_S 31 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_BUSY_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_REQ_TYPE_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_RSVD0_S 29 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_RSVD0_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_HOSTID_S 26 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_HOSTID_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_VM_VF_NUM_S) +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_PMF_S 0 +#define IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GLPE_SQCE_FWFLRQPFLUSHLO_PMF_S) +#define IG3_SQCE_GLPE_SQCE_FWSYNCRESP(_i) 0x420E3068 + ((_i) * 4) /* _i=0...1 */ +#define IG3_SQCE_GLPE_SQCE_FWSYNCRESP_MAX_INDEX_I 1 +#define IG3_SQCE_GLPE_SQCE_FWSYNCRESP_RSVD_S 18 +#define IG3_SQCE_GLPE_SQCE_FWSYNCRESP_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_SQCE_GLPE_SQCE_FWSYNCRESP_RSVD_S) +#define IG3_SQCE_GLPE_SQCE_FWSYNCRESP_COUNT_S 8 +#define IG3_SQCE_GLPE_SQCE_FWSYNCRESP_COUNT_M RDMA_MASK3(32, 0x3FF, IG3_SQCE_GLPE_SQCE_FWSYNCRESP_COUNT_S) +#define IG3_SQCE_GLPE_SQCE_FWSYNCRESP_TAG_S 0 +#define IG3_SQCE_GLPE_SQCE_FWSYNCRESP_TAG_M RDMA_MASK3(32, 0xFF, IG3_SQCE_GLPE_SQCE_FWSYNCRESP_TAG_S) +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI(_i) 0x420E3020 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_MAX_INDEX_I 7 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_RSVD0_S 26 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_RSVD0_S) +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_QPID_S 6 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_QPID_S) +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_PF_NUM_S 0 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQCE_GPLE_SQCE_FWFLUSHDROPHI_PF_NUM_S) +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO(_i) 0x420E3000 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_MAX_INDEX_I 7 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_EN_S 31 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_EN_M RDMA_BIT2(32, IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_EN_S) +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_RSVD0_S 29 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_RSVD0_S) +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_HOSTID_S 26 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_HOSTID_S) +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_VM_VF_TYPE_S 24 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_VM_VF_TYPE_S) +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_VM_VF_NUM_S 12 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_VM_VF_NUM_S) +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_PMF_S 0 +#define IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_GPLE_SQCE_FWFLUSHDROPLO_PMF_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG 0x420E3100 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_INST_NUM_S 25 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_INST_NUM_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD3_S 20 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD3_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RM_S 16 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RM_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD2_S 14 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD2_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_POWER_GATE_EN_S 13 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_POWER_GATE_EN_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RME_S 12 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RME_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RME_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD1_S 10 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD1_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ERR_CNT_S 9 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ERR_CNT_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_FIX_CNT_S 8 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_FIX_CNT_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD0_S 6 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_RSVD0_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_MASK_INT_S 5 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_MASK_INT_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_LS_BYPASS_S 4 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_LS_BYPASS_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_LS_FORCE_S 3 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_LS_FORCE_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_INVERT_2_S 2 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_INVERT_2_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_INVERT_1_S 1 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_INVERT_1_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_EN_S 0 +#define IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_CFG_ECC_EN_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS 0x420E3104 +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_RSVD1_S 30 +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_RSVD1_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_RSVD0_S 4 +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_RSVD0_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_INIT_DONE_S 2 +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_INIT_DONE_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_ECC_FIX_S 1 +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_ECC_FIX_S) +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_ECC_ERR_S 0 +#define IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_PTR_STATUS_ECC_ERR_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG 0x420E3108 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD3_S 20 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD3_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RM_S 16 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RM_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD2_S 14 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD2_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RME_S 12 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RME_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD1_S 10 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD1_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ERR_CNT_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_FIX_CNT_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD0_S 6 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_RSVD0_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_MASK_INT_S 5 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_MASK_INT_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_LS_BYPASS_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_LS_FORCE_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_EN_S 0 +#define IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_CFG_ECC_EN_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS 0x420E310C +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_RSVD1_S 30 +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_RSVD1_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_RSVD0_S 4 +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_RSVD0_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_INIT_DONE_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_ECC_FIX_S) +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQCE_SQCE_CRTBUF_RAM_STATUS_ECC_ERR_S) +#define IG3_SQCE_SQCE_ECC_COR_ERR 0x420E311C +#define IG3_SQCE_SQCE_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQCE_SQCE_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQCE_SQCE_ECC_COR_ERR_RSVD_S) +#define IG3_SQCE_SQCE_ECC_COR_ERR_CNT_S 0 +#define IG3_SQCE_SQCE_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_SQCE_ECC_COR_ERR_CNT_S) +#define IG3_SQCE_SQCE_ECC_UNCOR_ERR 0x420E3118 +#define IG3_SQCE_SQCE_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQCE_SQCE_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQCE_SQCE_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQCE_SQCE_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQCE_SQCE_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQCE_SQCE_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG 0x420E3110 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD3_S 20 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD3_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RM_S 16 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RM_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD2_S 14 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD2_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RME_S 12 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RME_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD1_S 10 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD1_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ERR_CNT_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_FIX_CNT_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD0_S 6 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_RSVD0_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_MASK_INT_S 5 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_MASK_INT_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_LS_BYPASS_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_LS_FORCE_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_EN_S 0 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_CFG_ECC_EN_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS 0x420E3114 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_RSVD1_S 30 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_RSVD1_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_RSVD0_S 4 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_RSVD0_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_INIT_DONE_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_ECC_FIX_S) +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQCE_SQCE_SCN_DBL_RAM_STATUS_ECC_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0 0x420E3404 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RSVD_S 26 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RSVD_M RDMA_MASK3(32, 0x3F, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_CORE_FAT_ERR_S 25 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_CORE_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_CORE_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_STATS_FAT_ERR_S 24 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_STATS_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_STATS_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_CPUW_FAT_ERR_S 23 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_CPUW_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_CPUW_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX4_FAT_ERR_S 22 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX4_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX4_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX3_FAT_ERR_S 21 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX3_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX3_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX2_FAT_ERR_S 20 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX2_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX2_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX1_FAT_ERR_S 19 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX1_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX1_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX0_FAT_ERR_S 18 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX0_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TX0_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX4_FAT_ERR_S 17 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX4_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX4_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX3_FAT_ERR_S 16 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX3_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX3_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX2_FAT_ERR_S 15 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX2_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX2_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX1_FAT_ERR_S 14 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX1_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX1_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX0_FAT_ERR_S 13 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX0_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_RX0_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX4_FAT_ERR_S 12 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX4_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX4_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX3_FAT_ERR_S 11 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX3_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX3_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX2_FAT_ERR_S 10 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX2_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX2_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX1_FAT_ERR_S 9 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX1_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX1_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX0_FAT_ERR_S 8 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX0_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DRX0_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DBL_FAT_ERR_S 7 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DBL_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_DBL_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TOC_FAT_ERR_S 6 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TOC_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_TOC_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_XOC_FAT_ERR_S 5 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_XOC_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_XOC_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_Q1OC_FAT_ERR_S 4 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_Q1OC_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_Q1OC_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_CQOC_FAT_ERR_S 3 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_CQOC_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_CQOC_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_MROC_FAT_ERR_S 2 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_MROC_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_MROC_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_PBLOC1_FAT_ERR_S 1 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_PBLOC1_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_PBLOC1_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_PBLOC0_FAT_ERR_S 0 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR0_PBLOC0_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR0_PBLOC0_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1 0x420E3408 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RSVD_S 16 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM4_FAT_ERR_S 15 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM4_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM4_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM3_FAT_ERR_S 14 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM3_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM3_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM2_FAT_ERR_S 13 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM2_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM2_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM1_FAT_ERR_S 12 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM1_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM1_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM0_FAT_ERR_S 11 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM0_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CPM0_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_PMAT_FAT_ERR_S 10 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_PMAT_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_PMAT_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_MSOC_FAT_ERR_S 9 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_MSOC_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_MSOC_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_FLOC_FAT_ERR_S 8 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_FLOC_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_FLOC_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CRX_FAT_ERR_S 7 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CRX_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CRX_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_BRX_FAT_ERR_S 6 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_BRX_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_BRX_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_AMP_FAT_ERR_S 5 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_AMP_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_AMP_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CQM_FAT_ERR_S 4 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CQM_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_CQM_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_TSCD_FAT_ERR_S 3 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_TSCD_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_TSCD_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RMI1_FAT_ERR_S 2 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RMI1_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RMI1_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RMI0_FAT_ERR_S 1 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RMI0_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RMI0_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RHI_FAT_ERR_S 0 +#define IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RHI_FAT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_ECR1_RHI_FAT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0 0x420E340C +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RSVD_S 26 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RSVD_M RDMA_MASK3(32, 0x3F, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_CORE_FAT_MSK_S 25 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_CORE_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_CORE_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_STATS_FAT_MSK_S 24 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_STATS_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_STATS_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_CPUW_FAT_MSK_S 23 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_CPUW_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_CPUW_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX4_FAT_MSK_S 22 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX4_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX4_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX3_FAT_MSK_S 21 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX3_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX3_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX2_FAT_MSK_S 20 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX2_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX2_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX1_FAT_MSK_S 19 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX1_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX1_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX0_FAT_MSK_S 18 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX0_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TX0_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX4_FAT_MSK_S 17 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX4_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX4_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX3_FAT_MSK_S 16 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX3_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX3_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX2_FAT_MSK_S 15 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX2_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX2_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX1_FAT_MSK_S 14 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX1_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX1_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX0_FAT_MSK_S 13 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX0_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_RX0_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX4_FAT_MSK_S 12 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX4_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX4_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX3_FAT_MSK_S 11 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX3_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX3_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX2_FAT_MSK_S 10 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX2_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX2_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX1_FAT_MSK_S 9 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX1_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX1_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX0_FAT_MSK_S 8 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX0_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DRX0_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DBL_FAT_MSK_S 7 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DBL_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_DBL_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TOC_FAT_MSK_S 6 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TOC_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_TOC_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_XOC_FAT_MSK_S 5 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_XOC_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_XOC_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_Q1OC_FAT_MSK_S 4 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_Q1OC_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_Q1OC_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_CQOC_FAT_MSK_S 3 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_CQOC_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_CQOC_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_MROC_FAT_MSK_S 2 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_MROC_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_MROC_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_PBLOC1_FAT_MSK_S 1 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_PBLOC1_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_PBLOC1_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_PBLOC0_FAT_MSK_S 0 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK0_PBLOC0_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK0_PBLOC0_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1 0x420E3410 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RSVD_S 16 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM4_FAT_MSK_S 15 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM4_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM4_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM3_FAT_MSK_S 14 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM3_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM3_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM2_FAT_MSK_S 13 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM2_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM2_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM1_FAT_MSK_S 12 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM1_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM1_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM0_FAT_MSK_S 11 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM0_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CPM0_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_PMAT_FAT_MSK_S 10 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_PMAT_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_PMAT_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_MSOC_FAT_MSK_S 9 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_MSOC_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_MSOC_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_FLOC_FAT_MSK_S 8 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_FLOC_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_FLOC_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CRX_FAT_MSK_S 7 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CRX_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CRX_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_BRX_FAT_MSK_S 6 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_BRX_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_BRX_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_AMP_FAT_MSK_S 5 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_AMP_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_AMP_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CQM_FAT_MSK_S 4 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CQM_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_CQM_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_TSCD_FAT_MSK_S 3 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_TSCD_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_TSCD_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RMI1_FAT_MSK_S 2 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RMI1_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RMI1_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RMI0_FAT_MSK_S 1 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RMI0_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RMI0_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RHI_FAT_MSK_S 0 +#define IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RHI_FAT_MSK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_FATAL_MSK1_RHI_FAT_MSK_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0 0x420E341C +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0_RSVD_S 17 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0_RSVD_M RDMA_MASK3(32, 0x7FFF, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0_PECRIT_ERR_S 16 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0_PECRIT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0_PECRIT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0_HMC_ERR_S 0 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0_HMC_ERR_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR0_HMC_ERR_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1 0x420E3420 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1_UNCORR_ERR_S 31 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1_UNCORR_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1_UNCORR_ERR_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1_RSVD_S 16 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1_RSVD_M RDMA_MASK3(32, 0x7FFF, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1_CMPE_CRC_ERR_S 0 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1_CMPE_CRC_ERR_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR1_CMPE_CRC_ERR_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0 0x420E342C +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0_RSVD_S 17 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0_RSVD_M RDMA_MASK3(32, 0x7FFF, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0_PECRIT_ERR_MASK_S 16 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0_PECRIT_ERR_MASK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0_PECRIT_ERR_MASK_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0_HMC_ERR_MASK_S 0 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0_HMC_ERR_MASK_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK0_HMC_ERR_MASK_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1 0x420E3430 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1_UNCORR_ERR_MASK_S 31 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1_UNCORR_ERR_MASK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1_UNCORR_ERR_MASK_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1_RSVD_S 16 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1_RSVD_M RDMA_MASK3(32, 0x7FFF, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1_CMPE_CRC_ERR_MASK_S 0 +#define IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1_CMPE_CRC_ERR_MASK_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_INT_ARES_ICR_MSK1_CMPE_CRC_ERR_MASK_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0 0x420E3414 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0_RSVD_S 17 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0_RSVD_M RDMA_MASK3(32, 0x7FFF, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0_PECRIT_ERR_S 16 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0_PECRIT_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0_PECRIT_ERR_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0_HMC_ERR_S 0 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0_HMC_ERR_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR0_HMC_ERR_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1 0x420E3418 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_UNCORR_ERR_S 31 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_UNCORR_ERR_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_UNCORR_ERR_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_IMC_FW_REQ_S 30 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_IMC_FW_REQ_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_IMC_FW_REQ_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_RSVD_S 16 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_CMPE_CRC_ERR_S 0 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_CMPE_CRC_ERR_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR1_CMPE_CRC_ERR_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0 0x420E3424 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0_RSVD_S 17 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0_RSVD_M RDMA_MASK3(32, 0x7FFF, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0_PECRIT_ERR_MASK_S 16 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0_PECRIT_ERR_MASK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0_PECRIT_ERR_MASK_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0_HMC_ERR_MASK_S 0 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0_HMC_ERR_MASK_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK0_HMC_ERR_MASK_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1 0x420E3428 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_UNCORR_ERR_MASK_S 31 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_UNCORR_ERR_MASK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_UNCORR_ERR_MASK_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_IMC_FW_REQ_MASK_S 30 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_IMC_FW_REQ_MASK_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_IMC_FW_REQ_MASK_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_RSVD_S 16 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_CMPE_CRC_ERR_MASK_S 0 +#define IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_CMPE_CRC_ERR_MASK_M RDMA_MASK3(32, 0xFFFF, IG3_STOP_SCREAM_RDMA_INT_IMC_ICR_MSK1_CMPE_CRC_ERR_MASK_S) +#define IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS 0x420E3400 +#define IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS_RSVD_S 3 +#define IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS_RSVD_S) +#define IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS_DISABLE_S 2 +#define IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS_DISABLE_M RDMA_BIT2(32, IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS_DISABLE_S) +#define IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS_STOP_SCREAM_STAT_S 0 +#define IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS_STOP_SCREAM_STAT_M RDMA_MASK3(32, 0x3, IG3_STOP_SCREAM_RDMA_STOP_SCREAM_RAS_STOP_SCREAM_STAT_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_COUNT 0x420E4038 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_CMD 0x420E404C +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_DATA_H 0x420E4058 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_DATA_L 0x420E4054 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_PTR 0x420E4050 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_CMD 0x420E403C +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_DATA_H 0x420E4048 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_DATA_L 0x420E4044 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_PTR 0x420E4040 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RHA_GLPE_RHA_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_CONTROL 0x420E4000 +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD1_S 25 +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD2_S 17 +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD2_S) +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD3_S 9 +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD3_S) +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_BYPASS_S 8 +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_CONTROL_BYPASS_S) +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD4_S 1 +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_RHA_GLPE_RHA_DTM_CONTROL_RSVD4_S) +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_RHA_GLPE_RHA_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_CONTROL_LOCAL_EN_S) +#define IG3_RHA_GLPE_RHA_DTM_ECC_COR_ERR 0x420E4068 +#define IG3_RHA_GLPE_RHA_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_RHA_GLPE_RHA_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RHA_GLPE_RHA_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_RHA_GLPE_RHA_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_RHA_GLPE_RHA_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RHA_GLPE_RHA_DTM_ECC_COR_ERR_CNT_S) +#define IG3_RHA_GLPE_RHA_DTM_ECC_UNCOR_ERR 0x420E4064 +#define IG3_RHA_GLPE_RHA_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_RHA_GLPE_RHA_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RHA_GLPE_RHA_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_RHA_GLPE_RHA_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_RHA_GLPE_RHA_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RHA_GLPE_RHA_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_RHA_GLPE_RHA_DTM_GROUP_CFG 0x420E400C +#define IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RHA_GLPE_RHA_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_RHA_GLPE_RHA_DTM_LOG_CFG 0x420E4010 +#define IG3_RHA_GLPE_RHA_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_RHA_GLPE_RHA_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_RHA_GLPE_RHA_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_RHA_GLPE_RHA_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_RHA_GLPE_RHA_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_RHA_GLPE_RHA_DTM_LOG_CFG_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_LOG_CFG_MODE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_RHA_GLPE_RHA_DTM_LOG_CFG_MODE_S) +#define IG3_RHA_GLPE_RHA_DTM_LOG_MASK 0x420E4018 +#define IG3_RHA_GLPE_RHA_DTM_LOG_MASK_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_LOG_MASK_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_LOG_PATTERN 0x420E4014 +#define IG3_RHA_GLPE_RHA_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_LOG_PATTERN_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG 0x420E4004 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_RSVD2_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_RSVD3_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_STS 0x420E4008 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_RHA_GLPE_RHA_DTM_MAIN_STS_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RHA_GLPE_RHA_DTM_MAIN_STS_RSVD2_S) +#define IG3_RHA_GLPE_RHA_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_RHA_GLPE_RHA_DTM_TIMESTAMP 0x420E4030 +#define IG3_RHA_GLPE_RHA_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_TIMESTAMP_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_TIMESTAMP_ROLLOVER 0x420E4034 +#define IG3_RHA_GLPE_RHA_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG 0x420E405C +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS 0x420E4060 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RHA_GLPE_RHA_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG 0x420E401C +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_RSVD1_S) +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_RSVD2_S) +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_MODE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_RHA_GLPE_RHA_DTM_TRIG_CFG_MODE_S) +#define IG3_RHA_GLPE_RHA_DTM_TRIG_COUNT 0x420E4028 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_TRIG_COUNT_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_TRIG_MASK 0x420E4024 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_TRIG_MASK_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_TRIG_PATTERN 0x420E4020 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_RHA_GLPE_RHA_DTM_TRIG_TIMESTAMP 0x420E402C +#define IG3_RHA_GLPE_RHA_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_RHA_GLPE_RHA_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHA_GLPE_RHA_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG 0x420E4400 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS 0x420E4404 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_ENTRY_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG 0x420E4408 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS 0x420E440C +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_LEAFOBJ_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG 0x420E4410 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS 0x420E4414 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_CPAL_PADDROBJ_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG 0x420E4418 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS 0x420E441C +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_ENTRY_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG 0x420E4420 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS 0x420E4424 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_LEAFOBJ_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG 0x420E4428 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS 0x420E442C +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_DPAL_PADDROBJ_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_COR_ERR 0x420E4434 +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_COR_ERR_RSVD_S 12 +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_SHCTL_GLPE_PAL_ECC_COR_ERR_RSVD_S) +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_COR_ERR_CNT_S 0 +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CORE_SHCTL_GLPE_PAL_ECC_COR_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_UNCOR_ERR 0x420E4430 +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_SHCTL_GLPE_PAL_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CORE_SHCTL_GLPE_PAL_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CORE_SHCTL_GLPE_PAL_ECC_UNCOR_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG 0x420E4518 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS 0x420E451C +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PMF_CNTR_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_COR_ERR 0x420E4524 +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_COR_ERR_RSVD_S 12 +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_SHCTL_GLPE_PTXI_ECC_COR_ERR_RSVD_S) +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_COR_ERR_CNT_S 0 +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CORE_SHCTL_GLPE_PTXI_ECC_COR_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_UNCOR_ERR 0x420E4520 +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_SHCTL_GLPE_PTXI_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CORE_SHCTL_GLPE_PTXI_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CORE_SHCTL_GLPE_PTXI_ECC_UNCOR_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG 0x420E4510 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS 0x420E4514 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_PTX_CSR_RAM_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_COR_ERR 0x420E450C +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_COR_ERR_RSVD_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_SHCTL_GLPE_RLC_ECC_COR_ERR_RSVD_S) +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_COR_ERR_CNT_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CORE_SHCTL_GLPE_RLC_ECC_COR_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_UNCOR_ERR 0x420E4508 +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_SHCTL_GLPE_RLC_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CORE_SHCTL_GLPE_RLC_ECC_UNCOR_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG 0x420E44D8 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS 0x420E44DC +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG 0x420E44E0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS 0x420E44E4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST0_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG 0x420E44F0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS 0x420E44F4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG 0x420E44F8 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS 0x420E44FC +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_RDYLIST1_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG 0x420E44E8 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS 0x420E44EC +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET0_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG 0x420E4500 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS 0x420E4504 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_RLC_TRIPLET1_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG 0x420E44B0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS 0x420E44B4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG 0x420E44B8 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS 0x420E44BC +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG 0x420E44C0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS 0x420E44C4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_2_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG 0x420E44C8 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS 0x420E44CC +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CFG_3_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG 0x420E4450 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS 0x420E4454 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG 0x420E4458 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS 0x420E445C +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG 0x420E4460 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS 0x420E4464 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_2_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG 0x420E4468 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS 0x420E446C +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_CNT_3_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG 0x420E4470 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS 0x420E4474 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG 0x420E4478 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS 0x420E447C +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG 0x420E4480 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS 0x420E4484 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_2_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG 0x420E4488 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS 0x420E448C +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_DIV_3_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_COR_ERR 0x420E44D4 +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_COR_ERR_RSVD_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_SHCTL_GLPE_TMR_ECC_COR_ERR_RSVD_S) +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_COR_ERR_CNT_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CORE_SHCTL_GLPE_TMR_ECC_COR_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_UNCOR_ERR 0x420E44D0 +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CORE_SHCTL_GLPE_TMR_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CORE_SHCTL_GLPE_TMR_ECC_UNCOR_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG 0x420E4490 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS 0x420E4494 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG 0x420E4498 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS 0x420E449C +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG 0x420E44A0 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS 0x420E44A4 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_2_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG 0x420E44A8 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS 0x420E44AC +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_NOW_3_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG 0x420E4448 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS 0x420E444C +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_BUCKET_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG 0x420E4438 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS 0x420E443C +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_SCN_MEM_STATUS_ECC_ERR_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG 0x420E4440 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD3_S 20 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD3_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RM_S 16 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RM_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD2_S 14 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RME_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RME_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD1_S 10 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ERR_CNT_S 9 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ERR_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_FIX_CNT_S 8 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_FIX_CNT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD0_S 6 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_MASK_INT_S 5 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_MASK_INT_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_LS_BYPASS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_LS_FORCE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_LS_FORCE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_EN_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_CFG_ECC_EN_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS 0x420E4444 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_RSVD1_S 30 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_RSVD1_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_RSVD0_S 4 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_RSVD0_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_INIT_DONE_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_ECC_FIX_S) +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CORE_SHCTL_GLPE_TMR_UCB_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS(_i) 0x42400028 + ((_i) * 4) /* _i=0...4 */ +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS_MAX_INDEX_I 4 +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS_RSVD_S 24 +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS_RSVD_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_APM_THRESHOLDS_RSVD_S) +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS_PMAT_REQ_THRESHOLD_S 16 +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS_PMAT_REQ_THRESHOLD_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_APM_THRESHOLDS_PMAT_REQ_THRESHOLD_S) +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS_PBLOC_REQ_THRESHOLD_S 8 +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS_PBLOC_REQ_THRESHOLD_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_APM_THRESHOLDS_PBLOC_REQ_THRESHOLD_S) +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS_MROC_REQ_THRESHOLD_S 0 +#define IG3_AMP_GLPE_AMP_APM_THRESHOLDS_MROC_REQ_THRESHOLD_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_APM_THRESHOLDS_MROC_REQ_THRESHOLD_S) +#define IG3_AMP_GLPE_AMP_CFG 0x42400004 +#define IG3_AMP_GLPE_AMP_CFG_RSVD_S 1 +#define IG3_AMP_GLPE_AMP_CFG_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_AMP_GLPE_AMP_CFG_RSVD_S) +#define IG3_AMP_GLPE_AMP_CFG_EN_TYPE_2B_MW_S 0 +#define IG3_AMP_GLPE_AMP_CFG_EN_TYPE_2B_MW_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_CFG_EN_TYPE_2B_MW_S) +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES(_i) 0x4240003C + ((_i) * 4) /* _i=0...4 */ +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_MAX_INDEX_I 4 +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_RSVD_S 24 +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_RSVD_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_RSVD_S) +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_PMAT_CNT_S 16 +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_PMAT_CNT_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_PMAT_CNT_S) +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_PBLOC_CNT_S 8 +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_PBLOC_CNT_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_PBLOC_CNT_S) +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_MROC_CNT_S 0 +#define IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_MROC_CNT_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_CONSUMED_RESOURCES_MROC_CNT_S) +#define IG3_AMP_GLPE_AMP_DBG_CFG(_i) 0x42400008 + ((_i) * 4) /* _i=0...4 */ +#define IG3_AMP_GLPE_AMP_DBG_CFG_MAX_INDEX_I 4 +#define IG3_AMP_GLPE_AMP_DBG_CFG_RSVD2_S 23 +#define IG3_AMP_GLPE_AMP_DBG_CFG_RSVD2_M RDMA_MASK3(32, 0x1FF, IG3_AMP_GLPE_AMP_DBG_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_DBG_CFG_DBG_CAM1_IDX_S 16 +#define IG3_AMP_GLPE_AMP_DBG_CFG_DBG_CAM1_IDX_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DBG_CFG_DBG_CAM1_IDX_S) +#define IG3_AMP_GLPE_AMP_DBG_CFG_RSVD1_S 15 +#define IG3_AMP_GLPE_AMP_DBG_CFG_RSVD1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DBG_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DBG_CFG_DBG_CAM0_IDX_S 8 +#define IG3_AMP_GLPE_AMP_DBG_CFG_DBG_CAM0_IDX_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DBG_CFG_DBG_CAM0_IDX_S) +#define IG3_AMP_GLPE_AMP_DBG_CFG_RSVD0_S 7 +#define IG3_AMP_GLPE_AMP_DBG_CFG_RSVD0_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DBG_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_DBG_CFG_DBG_REQTAG_S 0 +#define IG3_AMP_GLPE_AMP_DBG_CFG_DBG_REQTAG_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DBG_CFG_DBG_REQTAG_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_COUNT 0x42400138 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_CMD 0x4240014C +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_DATA_H 0x42400158 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_DATA_L 0x42400154 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_PTR 0x42400150 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_CMD 0x4240013C +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_DATA_H 0x42400148 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_DATA_L 0x42400144 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_PTR 0x42400140 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_AMP_GLPE_AMP_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_CFG 0x4240001C +#define IG3_AMP_GLPE_AMP_DTM_CFG_RSVD_S 3 +#define IG3_AMP_GLPE_AMP_DTM_CFG_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_AMP_GLPE_AMP_DTM_CFG_RSVD_S) +#define IG3_AMP_GLPE_AMP_DTM_CFG_AMP_ENG_SEL_S 0 +#define IG3_AMP_GLPE_AMP_DTM_CFG_AMP_ENG_SEL_M RDMA_MASK3(32, 0x7, IG3_AMP_GLPE_AMP_DTM_CFG_AMP_ENG_SEL_S) +#define IG3_AMP_GLPE_AMP_DTM_CONTROL 0x42400100 +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD1_S 25 +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD2_S 17 +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD2_S) +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD3_S 9 +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD3_S) +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_BYPASS_S 8 +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_CONTROL_BYPASS_S) +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD4_S 1 +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DTM_CONTROL_RSVD4_S) +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_AMP_GLPE_AMP_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_CONTROL_LOCAL_EN_S) +#define IG3_AMP_GLPE_AMP_DTM_ECC_COR_ERR 0x42400168 +#define IG3_AMP_GLPE_AMP_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_AMP_GLPE_AMP_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_AMP_GLPE_AMP_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_AMP_GLPE_AMP_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_AMP_GLPE_AMP_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_AMP_GLPE_AMP_DTM_ECC_COR_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_DTM_ECC_UNCOR_ERR 0x42400164 +#define IG3_AMP_GLPE_AMP_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_AMP_GLPE_AMP_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_AMP_GLPE_AMP_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_AMP_GLPE_AMP_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_AMP_GLPE_AMP_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_AMP_GLPE_AMP_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_DTM_GROUP_CFG 0x4240010C +#define IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_AMP_GLPE_AMP_DTM_LOG_CFG 0x42400110 +#define IG3_AMP_GLPE_AMP_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_AMP_GLPE_AMP_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_AMP_GLPE_AMP_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_AMP_GLPE_AMP_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_AMP_GLPE_AMP_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_AMP_GLPE_AMP_DTM_LOG_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_LOG_CFG_MODE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_DTM_LOG_CFG_MODE_S) +#define IG3_AMP_GLPE_AMP_DTM_LOG_MASK 0x42400118 +#define IG3_AMP_GLPE_AMP_DTM_LOG_MASK_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_LOG_MASK_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_LOG_PATTERN 0x42400114 +#define IG3_AMP_GLPE_AMP_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_LOG_PATTERN_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG 0x42400104 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_STS 0x42400108 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_AMP_GLPE_AMP_DTM_MAIN_STS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DTM_MAIN_STS_RSVD2_S) +#define IG3_AMP_GLPE_AMP_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_AMP_GLPE_AMP_DTM_TIMESTAMP 0x42400130 +#define IG3_AMP_GLPE_AMP_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_TIMESTAMP_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_TIMESTAMP_ROLLOVER 0x42400134 +#define IG3_AMP_GLPE_AMP_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG 0x4240015C +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS 0x42400160 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG 0x4240011C +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_MODE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_DTM_TRIG_CFG_MODE_S) +#define IG3_AMP_GLPE_AMP_DTM_TRIG_COUNT 0x42400128 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_TRIG_COUNT_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_TRIG_MASK 0x42400124 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_TRIG_MASK_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_TRIG_PATTERN 0x42400120 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_AMP_GLPE_AMP_DTM_TRIG_TIMESTAMP 0x4240012C +#define IG3_AMP_GLPE_AMP_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_AMP_GLPE_AMP_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_AMP_GLPE_AMP_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_AMP_GLPE_AMP_ECC_COR_ERR 0x424000D4 +#define IG3_AMP_GLPE_AMP_ECC_COR_ERR_RSVD_S 12 +#define IG3_AMP_GLPE_AMP_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_AMP_GLPE_AMP_ECC_COR_ERR_RSVD_S) +#define IG3_AMP_GLPE_AMP_ECC_COR_ERR_CNT_S 0 +#define IG3_AMP_GLPE_AMP_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_AMP_GLPE_AMP_ECC_COR_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_ECC_UNCOR_ERR 0x424000D0 +#define IG3_AMP_GLPE_AMP_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_AMP_GLPE_AMP_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_AMP_GLPE_AMP_ECC_UNCOR_ERR_RSVD_S) +#define IG3_AMP_GLPE_AMP_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_AMP_GLPE_AMP_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_AMP_GLPE_AMP_ECC_UNCOR_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG 0x42400050 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS 0x42400054 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_0_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG 0x42400068 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS 0x4240006C +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_1_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG 0x42400080 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS 0x42400084 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_2_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG 0x42400098 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS 0x4240009C +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_3_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG 0x424000B0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS 0x424000B4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_LOOP_FIFO_4_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG 0x424000C8 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS 0x424000CC +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MIM_TBL_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG 0x42400058 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS 0x4240005C +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG 0x42400070 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS 0x42400074 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG 0x42400088 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS 0x4240008C +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG 0x424000A0 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS 0x424000A4 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG 0x424000B8 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS 0x424000BC +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_MRTE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG 0x42400060 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS 0x42400064 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_0_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG 0x42400078 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS 0x4240007C +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_1_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG 0x42400090 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS 0x42400094 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_2_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG 0x424000A8 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS 0x424000AC +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_3_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG 0x424000C0 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD3_S 20 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD3_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RM_S 16 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RM_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD2_S 14 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD2_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RME_S 12 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RME_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD1_S 10 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ERR_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_FIX_CNT_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD0_S 6 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_MASK_INT_S 5 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_MASK_INT_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_LS_BYPASS_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_LS_FORCE_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_EN_S 0 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_CFG_ECC_EN_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS 0x424000C4 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_RSVD1_S 30 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_RSVD1_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_RSVD0_S 4 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_RSVD0_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_INIT_DONE_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_ECC_FIX_S) +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_AMP_GLPE_AMP_TAG_4_MEM_STATUS_ECC_ERR_S) +#define IG3_AMP_GLPE_ATM_CONFIG 0x42400000 +#define IG3_AMP_GLPE_ATM_CONFIG_RSVD0_S 2 +#define IG3_AMP_GLPE_ATM_CONFIG_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_AMP_GLPE_ATM_CONFIG_RSVD0_S) +#define IG3_AMP_GLPE_ATM_CONFIG_SEL_MODE_S 0 +#define IG3_AMP_GLPE_ATM_CONFIG_SEL_MODE_M RDMA_MASK3(32, 0x3, IG3_AMP_GLPE_ATM_CONFIG_SEL_MODE_S) +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD 0x42400020 +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD_TBLWR_S 31 +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD_TBLWR_M RDMA_BIT2(32, IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD_TBLWR_S) +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD_RSVD_S 12 +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD_RSVD_S) +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD_PMFIDX_S 0 +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD_PMFIDX_M RDMA_MASK3(32, 0xFFF, IG3_AMP_GLPE_FWMRTEIDXMASKTBL_CMD_PMFIDX_S) +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_DATA 0x42400024 +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_DATA_RSVD_S 5 +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_DATA_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_AMP_GLPE_FWMRTEIDXMASKTBL_DATA_RSVD_S) +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_DATA_MRTEIDXMASKBITS_S 0 +#define IG3_AMP_GLPE_FWMRTEIDXMASKTBL_DATA_MRTEIDXMASKBITS_M RDMA_MASK3(32, 0x1F, IG3_AMP_GLPE_FWMRTEIDXMASKTBL_DATA_MRTEIDXMASKBITS_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG 0x42400410 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_INST_NUM_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD3_S 20 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD3_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RM_S 16 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RM_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD2_S 14 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD2_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_POWER_GATE_EN_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RME_S 12 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RME_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RME_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD1_S 10 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD1_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ERR_CNT_S 9 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ERR_CNT_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_FIX_CNT_S 8 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_FIX_CNT_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD0_S 6 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_RSVD0_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_MASK_INT_S 5 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_MASK_INT_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_LS_BYPASS_S 4 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_LS_BYPASS_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_LS_FORCE_S 3 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_LS_FORCE_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_INVERT_2_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_INVERT_1_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_EN_S 0 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_CFG_ECC_EN_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS 0x42400414 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_RSVD1_S 30 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_RSVD1_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_RSVD0_S 4 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_RSVD0_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_INIT_DONE_S 2 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_INIT_DONE_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_ECC_FIX_S 1 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_ECC_FIX_S) +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_ECC_ERR_S 0 +#define IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CHUNK_RAM_STATUS_ECC_ERR_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG 0x42400418 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_INST_NUM_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD3_S 20 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD3_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RM_S 16 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RM_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD2_S 14 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD2_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_POWER_GATE_EN_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RME_S 12 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RME_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RME_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD1_S 10 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD1_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ERR_CNT_S 9 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ERR_CNT_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_FIX_CNT_S 8 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_FIX_CNT_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD0_S 6 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_RSVD0_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_MASK_INT_S 5 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_MASK_INT_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_LS_BYPASS_S 4 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_LS_BYPASS_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_LS_FORCE_S 3 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_LS_FORCE_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_INVERT_2_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_INVERT_1_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_EN_S 0 +#define IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_CFG_ECC_EN_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS 0x4240041C +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_RSVD1_S 30 +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_RSVD1_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_RSVD0_S 4 +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_RSVD0_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_INIT_DONE_S 2 +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_INIT_DONE_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_ECC_FIX_S 1 +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_ECC_FIX_S) +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_ECC_ERR_S 0 +#define IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_CLID_RAM_STATUS_ECC_ERR_S) +#define IG3_BRX_GLPE_BRX_CONFIG 0x42400400 +#define IG3_BRX_GLPE_BRX_CONFIG_RSVD1_S 3 +#define IG3_BRX_GLPE_BRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_BRX_GLPE_BRX_CONFIG_RSVD1_S) +#define IG3_BRX_GLPE_BRX_CONFIG_CRC_MASK_S 0 +#define IG3_BRX_GLPE_BRX_CONFIG_CRC_MASK_M RDMA_MASK3(32, 0x7, IG3_BRX_GLPE_BRX_CONFIG_CRC_MASK_S) +#define IG3_BRX_GLPE_BRX_DEBUG 0x42400404 +#define IG3_BRX_GLPE_BRX_DEBUG_RSVD0_S 11 +#define IG3_BRX_GLPE_BRX_DEBUG_RSVD0_M RDMA_MASK3(32, 0x1FFFFF, IG3_BRX_GLPE_BRX_DEBUG_RSVD0_S) +#define IG3_BRX_GLPE_BRX_DEBUG_USED_RX_CHUNKS_S 0 +#define IG3_BRX_GLPE_BRX_DEBUG_USED_RX_CHUNKS_M RDMA_MASK3(32, 0x7FF, IG3_BRX_GLPE_BRX_DEBUG_USED_RX_CHUNKS_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_COUNT 0x424004B8 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_CMD 0x424004CC +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_DATA_H 0x424004D8 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_DATA_L 0x424004D4 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_PTR 0x424004D0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_CMD 0x424004BC +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_DATA_H 0x424004C8 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_DATA_L 0x424004C4 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_PTR 0x424004C0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_BRX_GLPE_BRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_CONTROL 0x42400480 +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD2_S) +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD3_S) +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_CONTROL_BYPASS_S) +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_DTM_CONTROL_RSVD4_S) +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_BRX_GLPE_BRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_BRX_GLPE_BRX_DTM_ECC_COR_ERR 0x424004E8 +#define IG3_BRX_GLPE_BRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_BRX_GLPE_BRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_BRX_GLPE_BRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_BRX_GLPE_BRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_BRX_GLPE_BRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_BRX_GLPE_BRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_BRX_GLPE_BRX_DTM_ECC_UNCOR_ERR 0x424004E4 +#define IG3_BRX_GLPE_BRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_BRX_GLPE_BRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_BRX_GLPE_BRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_BRX_GLPE_BRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_BRX_GLPE_BRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_BRX_GLPE_BRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_BRX_GLPE_BRX_DTM_GROUP_CFG 0x4240048C +#define IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_BRX_GLPE_BRX_DTM_LOG_CFG 0x42400490 +#define IG3_BRX_GLPE_BRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_BRX_GLPE_BRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_BRX_GLPE_BRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_BRX_GLPE_BRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_BRX_GLPE_BRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_BRX_GLPE_BRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_DTM_LOG_CFG_MODE_S) +#define IG3_BRX_GLPE_BRX_DTM_LOG_MASK 0x42400498 +#define IG3_BRX_GLPE_BRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_LOG_MASK_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_LOG_PATTERN 0x42400494 +#define IG3_BRX_GLPE_BRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG 0x42400484 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_STS 0x42400488 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_BRX_GLPE_BRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_BRX_GLPE_BRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_BRX_GLPE_BRX_DTM_TIMESTAMP 0x424004B0 +#define IG3_BRX_GLPE_BRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_TIMESTAMP_ROLLOVER 0x424004B4 +#define IG3_BRX_GLPE_BRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG 0x424004DC +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS 0x424004E0 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG 0x4240049C +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_BRX_GLPE_BRX_DTM_TRIG_CFG_MODE_S) +#define IG3_BRX_GLPE_BRX_DTM_TRIG_COUNT 0x424004A8 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_TRIG_MASK 0x424004A4 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_TRIG_PATTERN 0x424004A0 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_BRX_GLPE_BRX_DTM_TRIG_TIMESTAMP 0x424004AC +#define IG3_BRX_GLPE_BRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_BRX_GLPE_BRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_BRX_GLPE_BRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_BRX_GLPE_BRX_ECC_COR_ERR 0x4240040C +#define IG3_BRX_GLPE_BRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_BRX_GLPE_BRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_BRX_GLPE_BRX_ECC_COR_ERR_RSVD_S) +#define IG3_BRX_GLPE_BRX_ECC_COR_ERR_CNT_S 0 +#define IG3_BRX_GLPE_BRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_BRX_GLPE_BRX_ECC_COR_ERR_CNT_S) +#define IG3_BRX_GLPE_BRX_ECC_UNCOR_ERR 0x42400408 +#define IG3_BRX_GLPE_BRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_BRX_GLPE_BRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_BRX_GLPE_BRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_BRX_GLPE_BRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_BRX_GLPE_BRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_BRX_GLPE_BRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG 0x42400420 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_INST_NUM_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD3_S 20 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD3_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RM_S 16 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RM_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD2_S 14 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD2_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_POWER_GATE_EN_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RME_S 12 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RME_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RME_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD1_S 10 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD1_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ERR_CNT_S 9 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ERR_CNT_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_FIX_CNT_S 8 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_FIX_CNT_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD0_S 6 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_RSVD0_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_MASK_INT_S 5 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_MASK_INT_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_LS_BYPASS_S 4 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_LS_BYPASS_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_LS_FORCE_S 3 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_LS_FORCE_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_INVERT_2_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_INVERT_1_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_EN_S 0 +#define IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_CFG_ECC_EN_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS 0x42400424 +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_RSVD1_S 30 +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_RSVD1_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_RSVD0_S 4 +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_RSVD0_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_INIT_DONE_S 2 +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_INIT_DONE_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_ECC_FIX_S 1 +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_ECC_FIX_S) +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_ECC_ERR_S 0 +#define IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_BRX_GLPE_BRX_FREE_RAM_STATUS_ECC_ERR_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_BUS_INDEX 0x42400A10 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL 0x42400A00 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_TRIG_OP_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_CTRL_FREEZE_SET_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_FREEZE_ON_CNT_VAL 0x42400A20 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_OBS_BUS 0x42400A40 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT0 0x42400A60 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT0_CNT0_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT1_0 0x42400A68 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT1_1 0x42400A6C +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL 0x42400A58 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_CTRL 0x42400A38 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_GAP 0x42400A28 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_RC_GAP_RC_GAP_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_TRNS 0x42400A30 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS 0x42400A08 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_I_FREEZE_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_READY_S 5 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_READY_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_VALID_S 4 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_VALID_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB0_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_TRANS_CNT 0x42400A18 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_TRIG_MASK 0x42400A48 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CRX_GLPE_CRX_BOB0_BOB_TRIG_VALUE 0x42400A50 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_BUS_INDEX 0x42400A90 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL 0x42400A80 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_TRIG_OP_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_CTRL_FREEZE_SET_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_FREEZE_ON_CNT_VAL 0x42400AA0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_OBS_BUS 0x42400AC0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT0 0x42400AE0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT0_CNT0_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT1_0 0x42400AE8 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT1_1 0x42400AEC +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL 0x42400AD8 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_CTRL 0x42400AB8 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_GAP 0x42400AA8 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_RC_GAP_RC_GAP_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_TRNS 0x42400AB0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS 0x42400A88 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_I_FREEZE_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_READY_S 5 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_READY_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_VALID_S 4 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_VALID_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB1_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_TRANS_CNT 0x42400A98 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_TRIG_MASK 0x42400AC8 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CRX_GLPE_CRX_BOB1_BOB_TRIG_VALUE 0x42400AD0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_BUS_INDEX 0x42400B10 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL 0x42400B00 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_TRIG_OP_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_CTRL_FREEZE_SET_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_FREEZE_ON_CNT_VAL 0x42400B20 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_OBS_BUS 0x42400B40 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT0 0x42400B60 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT0_CNT0_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT1_0 0x42400B68 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT1_1 0x42400B6C +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL 0x42400B58 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_CTRL 0x42400B38 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_GAP 0x42400B28 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_RC_GAP_RC_GAP_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_TRNS 0x42400B30 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS 0x42400B08 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_I_FREEZE_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_READY_S 5 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_READY_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_VALID_S 4 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_VALID_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB2_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_TRANS_CNT 0x42400B18 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_TRIG_MASK 0x42400B48 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CRX_GLPE_CRX_BOB2_BOB_TRIG_VALUE 0x42400B50 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_BUS_INDEX 0x42400B90 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL 0x42400B80 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_TRIG_OP_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_CTRL_FREEZE_SET_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_FREEZE_ON_CNT_VAL 0x42400BA0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_OBS_BUS 0x42400BC0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT0 0x42400BE0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT0_CNT0_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT1_0 0x42400BE8 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT1_1 0x42400BEC +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL 0x42400BD8 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_CTRL 0x42400BB8 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_GAP 0x42400BA8 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_RC_GAP_RC_GAP_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_TRNS 0x42400BB0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS 0x42400B88 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_I_FREEZE_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_READY_S 5 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_READY_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_VALID_S 4 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_VALID_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_BOB3_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_TRANS_CNT 0x42400B98 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_TRIG_MASK 0x42400BC8 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CRX_GLPE_CRX_BOB3_BOB_TRIG_VALUE 0x42400BD0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CRX_GLPE_CRX_CONFIG 0x42400800 +#define IG3_CRX_GLPE_CRX_CONFIG_RSVD1_S 3 +#define IG3_CRX_GLPE_CRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_CRX_GLPE_CRX_CONFIG_RSVD1_S) +#define IG3_CRX_GLPE_CRX_CONFIG_CRC_MASK_S 0 +#define IG3_CRX_GLPE_CRX_CONFIG_CRC_MASK_M RDMA_MASK3(32, 0x7, IG3_CRX_GLPE_CRX_CONFIG_CRC_MASK_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_COUNT 0x424009B8 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_CMD 0x424009CC +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_DATA_H 0x424009D8 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_DATA_L 0x424009D4 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_PTR 0x424009D0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_CMD 0x424009BC +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_DATA_H 0x424009C8 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_DATA_L 0x424009C4 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_PTR 0x424009C0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_CRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_CONTROL 0x42400980 +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD2_S) +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD3_S) +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_CONTROL_BYPASS_S) +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_CRX_DTM_CONTROL_RSVD4_S) +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_CRX_GLPE_CRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_CRX_GLPE_CRX_DTM_ECC_COR_ERR 0x424009E8 +#define IG3_CRX_GLPE_CRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_CRX_GLPE_CRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_CRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_CRX_GLPE_CRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_CRX_GLPE_CRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_CRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_CRX_GLPE_CRX_DTM_ECC_UNCOR_ERR 0x424009E4 +#define IG3_CRX_GLPE_CRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CRX_GLPE_CRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_CRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CRX_GLPE_CRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CRX_GLPE_CRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_CRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_CRX_GLPE_CRX_DTM_GROUP_CFG 0x4240098C +#define IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_CRX_GLPE_CRX_DTM_LOG_CFG 0x42400990 +#define IG3_CRX_GLPE_CRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_CRX_GLPE_CRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_CRX_GLPE_CRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_CRX_GLPE_CRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_CRX_GLPE_CRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CRX_GLPE_CRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_DTM_LOG_CFG_MODE_S) +#define IG3_CRX_GLPE_CRX_DTM_LOG_MASK 0x42400998 +#define IG3_CRX_GLPE_CRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_LOG_MASK_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_LOG_PATTERN 0x42400994 +#define IG3_CRX_GLPE_CRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG 0x42400984 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_STS 0x42400988 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_CRX_GLPE_CRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_CRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_CRX_GLPE_CRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_CRX_GLPE_CRX_DTM_TIMESTAMP 0x424009B0 +#define IG3_CRX_GLPE_CRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_TIMESTAMP_ROLLOVER 0x424009B4 +#define IG3_CRX_GLPE_CRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG 0x424009DC +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS 0x424009E0 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CRX_GLPE_CRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG 0x4240099C +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_CRX_DTM_TRIG_CFG_MODE_S) +#define IG3_CRX_GLPE_CRX_DTM_TRIG_COUNT 0x424009A8 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_TRIG_MASK 0x424009A4 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_TRIG_PATTERN 0x424009A0 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_CRX_GLPE_CRX_DTM_TRIG_TIMESTAMP 0x424009AC +#define IG3_CRX_GLPE_CRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_CRX_GLPE_CRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CRX_GLPE_CRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_CRX_GLPE_CRX_ECC_COR_ERR 0x424008E0 +#define IG3_CRX_GLPE_CRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_CRX_GLPE_CRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_CRX_ECC_COR_ERR_RSVD_S) +#define IG3_CRX_GLPE_CRX_ECC_COR_ERR_CNT_S 0 +#define IG3_CRX_GLPE_CRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_CRX_ECC_COR_ERR_CNT_S) +#define IG3_CRX_GLPE_CRX_ECC_UNCOR_ERR 0x424008DC +#define IG3_CRX_GLPE_CRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CRX_GLPE_CRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_CRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CRX_GLPE_CRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CRX_GLPE_CRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_CRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG 0x424008E4 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_INST_NUM_S 25 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_INST_NUM_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD3_S 20 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD3_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RM_S 16 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_MC_OC_BUF_CFG_RM_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD2_S 14 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD2_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_POWER_GATE_EN_S 13 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_POWER_GATE_EN_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RME_S 12 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RME_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_RME_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD1_S 10 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD1_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ERR_CNT_S 9 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_ERR_CNT_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_FIX_CNT_S 8 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_FIX_CNT_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD0_S 6 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_MC_OC_BUF_CFG_RSVD0_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_MASK_INT_S 5 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_MASK_INT_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_LS_BYPASS_S 4 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_LS_BYPASS_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_LS_FORCE_S 3 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_LS_FORCE_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_INVERT_2_S 2 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_INVERT_2_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_INVERT_1_S 1 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_INVERT_1_S) +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_EN_S 0 +#define IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_CFG_ECC_EN_S) +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS 0x424008E8 +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_RSVD1_S 30 +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_MC_OC_BUF_STATUS_RSVD1_S) +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CRX_GLPE_MC_OC_BUF_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_RSVD0_S 4 +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_MC_OC_BUF_STATUS_RSVD0_S) +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_INIT_DONE_S 2 +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_STATUS_INIT_DONE_S) +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_ECC_FIX_S 1 +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_STATUS_ECC_FIX_S) +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_ECC_ERR_S 0 +#define IG3_CRX_GLPE_MC_OC_BUF_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CRX_GLPE_MC_OC_BUF_STATUS_ECC_ERR_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD 0x424008AC +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_RSVD_S 8 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_RSVD_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST7_CREDIT_EN_S 7 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST7_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST7_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST6_CREDIT_EN_S 6 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST6_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST6_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST5_CREDIT_EN_S 5 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST5_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST5_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST4_CREDIT_EN_S 4 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST4_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST4_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST3_CREDIT_EN_S 3 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST3_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST3_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST2_CREDIT_EN_S 2 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST2_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST2_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST1_CREDIT_EN_S 1 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST1_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST1_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST0_CREDIT_EN_S 0 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST0_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PD_HOST0_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD 0x424008C4 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_RSVD_S 8 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_RSVD_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST7_CREDIT_EN_S 7 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST7_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST7_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST6_CREDIT_EN_S 6 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST6_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST6_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST5_CREDIT_EN_S 5 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST5_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST5_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST4_CREDIT_EN_S 4 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST4_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST4_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST3_CREDIT_EN_S 3 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST3_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST3_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST2_CREDIT_EN_S 2 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST2_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST2_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST1_CREDIT_EN_S 1 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST1_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST1_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST0_CREDIT_EN_S 0 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST0_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_CRT_PMD_HOST0_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD 0x4240087C +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_RSVD_S 8 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_RSVD_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST7_CREDIT_EN_S 7 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST7_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST7_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST6_CREDIT_EN_S 6 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST6_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST6_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST5_CREDIT_EN_S 5 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST5_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST5_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST4_CREDIT_EN_S 4 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST4_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST4_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST3_CREDIT_EN_S 3 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST3_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST3_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST2_CREDIT_EN_S 2 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST2_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST2_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST1_CREDIT_EN_S 1 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST1_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST1_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST0_CREDIT_EN_S 0 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST0_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PD_HOST0_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD 0x42400894 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_RSVD_S 8 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_RSVD_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST7_CREDIT_EN_S 7 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST7_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST7_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST6_CREDIT_EN_S 6 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST6_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST6_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST5_CREDIT_EN_S 5 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST5_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST5_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST4_CREDIT_EN_S 4 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST4_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST4_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST3_CREDIT_EN_S 3 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST3_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST3_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST2_CREDIT_EN_S 2 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST2_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST2_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST1_CREDIT_EN_S 1 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST1_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST1_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST0_CREDIT_EN_S 0 +#define IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST0_CREDIT_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_MIF_HOST_CREDIT_ENABLE_PR_PMD_HOST0_CREDIT_EN_S) +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_CRT_PD(_i) 0x424008B0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_CRT_PD_MAX_INDEX_I 4 +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_CRT_PD_RSVD_S 12 +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_CRT_PD_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_CRT_PD_RSVD_S) +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_CRT_PD_INIT_VALUE_S 0 +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_CRT_PD_INIT_VALUE_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_CRT_PD_INIT_VALUE_S) +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_PR_PD(_i) 0x42400880 + ((_i) * 4) /* _i=0...4 */ +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_PR_PD_MAX_INDEX_I 4 +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_PR_PD_RSVD_S 12 +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_PR_PD_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_PR_PD_RSVD_S) +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_PR_PD_INIT_VALUE_S 0 +#define IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_PR_PD_INIT_VALUE_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_MIF_PD_INITIAL_CREDIT_VALUE_PR_PD_INIT_VALUE_S) +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_CRT_PMD(_i) 0x424008C8 + ((_i) * 4) /* _i=0...4 */ +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_CRT_PMD_MAX_INDEX_I 4 +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_CRT_PMD_RSVD_S 12 +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_CRT_PMD_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_CRT_PMD_RSVD_S) +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_CRT_PMD_INIT_VALUE_S 0 +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_CRT_PMD_INIT_VALUE_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_CRT_PMD_INIT_VALUE_S) +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_PR_PMD(_i) 0x42400898 + ((_i) * 4) /* _i=0...4 */ +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_PR_PMD_MAX_INDEX_I 4 +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_PR_PMD_RSVD_S 12 +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_PR_PMD_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_PR_PMD_RSVD_S) +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_PR_PMD_INIT_VALUE_S 0 +#define IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_PR_PMD_INIT_VALUE_M RDMA_MASK3(32, 0xFFF, IG3_CRX_GLPE_MIF_PMD_INITIAL_CREDIT_VALUE_PR_PMD_INIT_VALUE_S) +#define IG3_CRX_GLPE_PARSEPTR_CRT_DEF 0x42400844 +#define IG3_CRX_GLPE_PARSEPTR_CRT_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_CRT_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_CRT_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_CRT_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_CRT_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_CRT_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_PARSEPTR_IPV4_DEF(_i) 0x42400810 + ((_i) * 4) /* _i=0...2 */ +#define IG3_CRX_GLPE_PARSEPTR_IPV4_DEF_MAX_INDEX_I 2 +#define IG3_CRX_GLPE_PARSEPTR_IPV4_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_IPV4_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_IPV4_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_IPV4_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_IPV4_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_IPV4_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_PARSEPTR_IPV6_DEF(_i) 0x4240081C + ((_i) * 4) /* _i=0...2 */ +#define IG3_CRX_GLPE_PARSEPTR_IPV6_DEF_MAX_INDEX_I 2 +#define IG3_CRX_GLPE_PARSEPTR_IPV6_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_IPV6_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_IPV6_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_IPV6_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_IPV6_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_IPV6_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_PARSEPTR_MAC_DEF(_i) 0x42400804 + ((_i) * 4) /* _i=0...2 */ +#define IG3_CRX_GLPE_PARSEPTR_MAC_DEF_MAX_INDEX_I 2 +#define IG3_CRX_GLPE_PARSEPTR_MAC_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_MAC_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_MAC_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_MAC_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_MAC_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_MAC_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_PARSEPTR_PAY_DEF 0x42400848 +#define IG3_CRX_GLPE_PARSEPTR_PAY_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_PAY_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_PAY_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_PAY_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_PAY_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_PAY_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_PARSEPTR_ROCEV2_DEF 0x42400840 +#define IG3_CRX_GLPE_PARSEPTR_ROCEV2_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_ROCEV2_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_ROCEV2_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_ROCEV2_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_ROCEV2_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_ROCEV2_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_PARSEPTR_TCP_DEF 0x4240083C +#define IG3_CRX_GLPE_PARSEPTR_TCP_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_TCP_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_TCP_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_TCP_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_TCP_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_TCP_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_PARSEPTR_UDP_DEF 0x42400838 +#define IG3_CRX_GLPE_PARSEPTR_UDP_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_UDP_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_UDP_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_UDP_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_UDP_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_UDP_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_PARSEPTR_VLAN_EXTERNAL_DEF(_i) 0x42400830 + ((_i) * 4) /* _i=0...1 */ +#define IG3_CRX_GLPE_PARSEPTR_VLAN_EXTERNAL_DEF_MAX_INDEX_I 1 +#define IG3_CRX_GLPE_PARSEPTR_VLAN_EXTERNAL_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_VLAN_EXTERNAL_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_VLAN_EXTERNAL_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_VLAN_EXTERNAL_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_VLAN_EXTERNAL_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_VLAN_EXTERNAL_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_PARSEPTR_VLAN_INTERNAL_DEF(_i) 0x42400828 + ((_i) * 4) /* _i=0...1 */ +#define IG3_CRX_GLPE_PARSEPTR_VLAN_INTERNAL_DEF_MAX_INDEX_I 1 +#define IG3_CRX_GLPE_PARSEPTR_VLAN_INTERNAL_DEF_RSVD_S 8 +#define IG3_CRX_GLPE_PARSEPTR_VLAN_INTERNAL_DEF_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CRX_GLPE_PARSEPTR_VLAN_INTERNAL_DEF_RSVD_S) +#define IG3_CRX_GLPE_PARSEPTR_VLAN_INTERNAL_DEF_PARSEPTRID_S 0 +#define IG3_CRX_GLPE_PARSEPTR_VLAN_INTERNAL_DEF_PARSEPTRID_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_PARSEPTR_VLAN_INTERNAL_DEF_PARSEPTRID_S) +#define IG3_CRX_GLPE_RB_CREDIT_LIMIT(_i) 0x4240084C + ((_i) * 4) /* _i=0...4 */ +#define IG3_CRX_GLPE_RB_CREDIT_LIMIT_MAX_INDEX_I 4 +#define IG3_CRX_GLPE_RB_CREDIT_LIMIT_RSVD_S 22 +#define IG3_CRX_GLPE_RB_CREDIT_LIMIT_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_CRX_GLPE_RB_CREDIT_LIMIT_RSVD_S) +#define IG3_CRX_GLPE_RB_CREDIT_LIMIT_SHARED_S 11 +#define IG3_CRX_GLPE_RB_CREDIT_LIMIT_SHARED_M RDMA_MASK3(32, 0x7FF, IG3_CRX_GLPE_RB_CREDIT_LIMIT_SHARED_S) +#define IG3_CRX_GLPE_RB_CREDIT_LIMIT_DEDICATED_S 0 +#define IG3_CRX_GLPE_RB_CREDIT_LIMIT_DEDICATED_M RDMA_MASK3(32, 0x7FF, IG3_CRX_GLPE_RB_CREDIT_LIMIT_DEDICATED_S) +#define IG3_CRX_GLPE_RB_CREDIT_USED(_i) 0x42400864 + ((_i) * 4) /* _i=0...4 */ +#define IG3_CRX_GLPE_RB_CREDIT_USED_MAX_INDEX_I 4 +#define IG3_CRX_GLPE_RB_CREDIT_USED_RSVD_S 22 +#define IG3_CRX_GLPE_RB_CREDIT_USED_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_CRX_GLPE_RB_CREDIT_USED_RSVD_S) +#define IG3_CRX_GLPE_RB_CREDIT_USED_SHARED_S 11 +#define IG3_CRX_GLPE_RB_CREDIT_USED_SHARED_M RDMA_MASK3(32, 0x7FF, IG3_CRX_GLPE_RB_CREDIT_USED_SHARED_S) +#define IG3_CRX_GLPE_RB_CREDIT_USED_DEDICATED_S 0 +#define IG3_CRX_GLPE_RB_CREDIT_USED_DEDICATED_M RDMA_MASK3(32, 0x7FF, IG3_CRX_GLPE_RB_CREDIT_USED_DEDICATED_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG 0x424008EC +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_INST_NUM_S 25 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_INST_NUM_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD3_S 20 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD3_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RM_S 16 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_RB_DATA_0_CFG_RM_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD2_S 14 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD2_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_POWER_GATE_EN_S 13 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_POWER_GATE_EN_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RME_S 12 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RME_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_RME_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD1_S 10 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD1_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ERR_CNT_S 9 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_ERR_CNT_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_FIX_CNT_S 8 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_FIX_CNT_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD0_S 6 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_DATA_0_CFG_RSVD0_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_MASK_INT_S 5 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_MASK_INT_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_LS_BYPASS_S 4 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_LS_BYPASS_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_LS_FORCE_S 3 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_LS_FORCE_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_INVERT_2_S 2 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_INVERT_2_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_INVERT_1_S 1 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_INVERT_1_S) +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_EN_S 0 +#define IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_CFG_ECC_EN_S) +#define IG3_CRX_GLPE_RB_DATA_0_STATUS 0x424008F0 +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_RSVD1_S 30 +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_DATA_0_STATUS_RSVD1_S) +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CRX_GLPE_RB_DATA_0_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_RSVD0_S 4 +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_RB_DATA_0_STATUS_RSVD0_S) +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_INIT_DONE_S 2 +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_STATUS_INIT_DONE_S) +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_ECC_FIX_S 1 +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_STATUS_ECC_FIX_S) +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_ECC_ERR_S 0 +#define IG3_CRX_GLPE_RB_DATA_0_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_0_STATUS_ECC_ERR_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG 0x424008F4 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_INST_NUM_S 25 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_INST_NUM_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD3_S 20 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD3_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RM_S 16 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_RB_DATA_1_CFG_RM_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD2_S 14 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD2_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_POWER_GATE_EN_S 13 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_POWER_GATE_EN_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RME_S 12 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RME_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_RME_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD1_S 10 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD1_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ERR_CNT_S 9 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_ERR_CNT_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_FIX_CNT_S 8 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_FIX_CNT_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD0_S 6 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_DATA_1_CFG_RSVD0_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_MASK_INT_S 5 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_MASK_INT_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_LS_BYPASS_S 4 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_LS_BYPASS_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_LS_FORCE_S 3 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_LS_FORCE_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_INVERT_2_S 2 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_INVERT_2_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_INVERT_1_S 1 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_INVERT_1_S) +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_EN_S 0 +#define IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_CFG_ECC_EN_S) +#define IG3_CRX_GLPE_RB_DATA_1_STATUS 0x424008F8 +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_RSVD1_S 30 +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_DATA_1_STATUS_RSVD1_S) +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CRX_GLPE_RB_DATA_1_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_RSVD0_S 4 +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_RB_DATA_1_STATUS_RSVD0_S) +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_INIT_DONE_S 2 +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_STATUS_INIT_DONE_S) +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_ECC_FIX_S 1 +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_STATUS_ECC_FIX_S) +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_ECC_ERR_S 0 +#define IG3_CRX_GLPE_RB_DATA_1_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_DATA_1_STATUS_ECC_ERR_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG 0x424008FC +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_INST_NUM_S 25 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_INST_NUM_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD3_S 20 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD3_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RM_S 16 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_RB_METADATA_0_CFG_RM_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD2_S 14 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD2_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_POWER_GATE_EN_S 13 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_POWER_GATE_EN_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RME_S 12 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RME_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_RME_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD1_S 10 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD1_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ERR_CNT_S 9 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_ERR_CNT_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_FIX_CNT_S 8 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_FIX_CNT_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD0_S 6 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_METADATA_0_CFG_RSVD0_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_MASK_INT_S 5 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_MASK_INT_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_LS_BYPASS_S 4 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_LS_BYPASS_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_LS_FORCE_S 3 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_LS_FORCE_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_INVERT_2_S 2 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_INVERT_2_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_INVERT_1_S 1 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_INVERT_1_S) +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_EN_S 0 +#define IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_CFG_ECC_EN_S) +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS 0x42400900 +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_RSVD1_S 30 +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_METADATA_0_STATUS_RSVD1_S) +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CRX_GLPE_RB_METADATA_0_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_RSVD0_S 4 +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_RB_METADATA_0_STATUS_RSVD0_S) +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_INIT_DONE_S 2 +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_STATUS_INIT_DONE_S) +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_ECC_FIX_S 1 +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_STATUS_ECC_FIX_S) +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_ECC_ERR_S 0 +#define IG3_CRX_GLPE_RB_METADATA_0_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_0_STATUS_ECC_ERR_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG 0x42400904 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_INST_NUM_S 25 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_INST_NUM_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD3_S 20 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD3_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RM_S 16 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CRX_GLPE_RB_METADATA_1_CFG_RM_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD2_S 14 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD2_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_POWER_GATE_EN_S 13 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_POWER_GATE_EN_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RME_S 12 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RME_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_RME_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD1_S 10 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD1_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ERR_CNT_S 9 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_ERR_CNT_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_FIX_CNT_S 8 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_FIX_CNT_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD0_S 6 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_METADATA_1_CFG_RSVD0_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_MASK_INT_S 5 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_MASK_INT_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_LS_BYPASS_S 4 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_LS_BYPASS_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_LS_FORCE_S 3 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_LS_FORCE_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_INVERT_2_S 2 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_INVERT_2_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_INVERT_1_S 1 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_INVERT_1_S) +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_EN_S 0 +#define IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_CFG_ECC_EN_S) +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS 0x42400908 +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_RSVD1_S 30 +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CRX_GLPE_RB_METADATA_1_STATUS_RSVD1_S) +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CRX_GLPE_RB_METADATA_1_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_RSVD0_S 4 +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CRX_GLPE_RB_METADATA_1_STATUS_RSVD0_S) +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_INIT_DONE_S 2 +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_STATUS_INIT_DONE_S) +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_ECC_FIX_S 1 +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_STATUS_ECC_FIX_S) +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_ECC_ERR_S 0 +#define IG3_CRX_GLPE_RB_METADATA_1_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CRX_GLPE_RB_METADATA_1_STATUS_ECC_ERR_S) +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT 0x42400860 +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT_RSVD_S 22 +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT_RSVD_S) +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT_TOTAL_SHARED_S 11 +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT_TOTAL_SHARED_M RDMA_MASK3(32, 0x7FF, IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT_TOTAL_SHARED_S) +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT_TOTAL_CREDIT_S 0 +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT_TOTAL_CREDIT_M RDMA_MASK3(32, 0x7FF, IG3_CRX_GLPE_RB_TOTAL_CREDIT_LIMIT_TOTAL_CREDIT_S) +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED 0x42400878 +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED_RSVD_S 22 +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED_RSVD_S) +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED_TOTAL_SHARED_S 11 +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED_TOTAL_SHARED_M RDMA_MASK3(32, 0x7FF, IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED_TOTAL_SHARED_S) +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED_TOTAL_DEDICATED_S 0 +#define IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED_TOTAL_DEDICATED_M RDMA_MASK3(32, 0x7FF, IG3_CRX_GLPE_RB_TOTAL_CREDIT_USED_TOTAL_DEDICATED_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_CRED(_i) 0x424837C0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_CRED_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_CRED_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_CRED_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_CRED_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_HW(_i) 0x42483880 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_HW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_HW_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_HW_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_HW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_HW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_HW_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_HW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_LW(_i) 0x42483940 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_LW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_LW_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_LW_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_LW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_LW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_LW_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_BUF_LW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_CRED(_i) 0x424837A0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_CRED_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_CRED_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_CRED_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_CRED_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_HW(_i) 0x42483860 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_HW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_HW_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_HW_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_HW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_HW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_HW_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_HW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_LW(_i) 0x42483920 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_LW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_LW_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_LW_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_LW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_LW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_LW_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_RX_PKT_LW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_CRED(_i) 0x42483780 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_CRED_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_CRED_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_CRED_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_CRED_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_HW(_i) 0x42483840 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_HW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_HW_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_HW_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_HW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_HW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_HW_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_HW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_LW(_i) 0x42483900 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_LW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_LW_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_LW_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_LW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_LW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_LW_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_BUF_LW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_CRED(_i) 0x42483760 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_CRED_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_CRED_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_CRED_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_CRED_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_HW(_i) 0x42483820 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_HW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_HW_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_HW_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_HW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_HW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_HW_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_HW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_LW(_i) 0x424838E0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_LW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_LW_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_LW_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_LW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_LW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_LW_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_REQ_TX_PKT_LW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_CRED(_i) 0x42483740 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_CRED_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_CRED_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_CRED_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_CRED_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_HW(_i) 0x42483800 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_HW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_HW_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_HW_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_HW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_HW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_HW_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_HW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_LW(_i) 0x424838C0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_LW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_LW_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_LW_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_LW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_LW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_LW_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_BUF_LW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_CRED(_i) 0x42483720 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_CRED_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_CRED_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_CRED_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_CRED_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_HW(_i) 0x424837E0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_HW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_HW_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_HW_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_HW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_HW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_HW_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_HW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_LW(_i) 0x424838A0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_LW_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_LW_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_LW_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_LW_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_LW_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_LW_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_HOST_RSP_TX_PKT_LW_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC 0x4248B0C4 +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_BUF_CREDIT_RX_S 21 +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_BUF_CREDIT_RX_M RDMA_MASK3(32, 0x7FF, IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_BUF_CREDIT_RX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_RSVD3_S 19 +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_RSVD3_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_RSVD3_S) +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_PKT_CREDIT_RX_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_PKT_CREDIT_RX_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_PKT_CREDIT_RX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_RSVD2_S 13 +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_RSVD2_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_BUF_CREDIT_TX_S 8 +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_BUF_CREDIT_TX_M RDMA_MASK3(32, 0x1F, IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_BUF_CREDIT_TX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_RSVD1_S 3 +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_RSVD1_M RDMA_MASK3(32, 0x1F, IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_PKT_CREDIT_TX_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_PKT_CREDIT_TX_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_CRT_PUSH_REQ_ALLOC_REQ_PKT_CREDIT_TX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_HW_PROFILE(_i) 0x4248B050 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_HW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_HW_PROFILE_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_HW_PROFILE_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_HW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_HW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_HW_PROFILE_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_HW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_LW_PROFILE(_i) 0x4248B0B0 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_LW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_LW_PROFILE_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_LW_PROFILE_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_LW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_LW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_LW_PROFILE_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_BUF_LW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_HW_PROFILE(_i) 0x4248B040 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_HW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_HW_PROFILE_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_HW_PROFILE_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_HW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_HW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_HW_PROFILE_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_HW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_LW_PROFILE(_i) 0x4248B0A0 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_LW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_LW_PROFILE_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_LW_PROFILE_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_LW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_LW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_LW_PROFILE_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_RX_PKT_LW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_HW_PROFILE(_i) 0x4248B030 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_HW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_HW_PROFILE_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_HW_PROFILE_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_HW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_HW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_HW_PROFILE_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_HW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_LW_PROFILE(_i) 0x4248B090 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_LW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_LW_PROFILE_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_LW_PROFILE_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_LW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_LW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_LW_PROFILE_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_BUF_LW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_HW_PROFILE(_i) 0x4248B020 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_HW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_HW_PROFILE_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_HW_PROFILE_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_HW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_HW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_HW_PROFILE_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_HW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_LW_PROFILE(_i) 0x4248B080 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_LW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_LW_PROFILE_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_LW_PROFILE_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_LW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_LW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_LW_PROFILE_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_REQ_TX_PKT_LW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_HW_PROFILE(_i) 0x4248B010 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_HW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_HW_PROFILE_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_HW_PROFILE_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_HW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_HW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_HW_PROFILE_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_HW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_LW_PROFILE(_i) 0x4248B070 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_LW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_LW_PROFILE_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_LW_PROFILE_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_LW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_LW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_LW_PROFILE_THRESH_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_BUF_LW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_HW_PROFILE(_i) 0x4248B000 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_HW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_HW_PROFILE_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_HW_PROFILE_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_HW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_HW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_HW_PROFILE_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_HW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_LW_PROFILE(_i) 0x4248B060 + ((_i) * 4) /* _i=0...3 */ +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_LW_PROFILE_MAX_INDEX_I 3 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_LW_PROFILE_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_LW_PROFILE_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_LW_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_LW_PROFILE_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_LW_PROFILE_THRESH_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_RSP_TX_PKT_LW_PROFILE_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC 0x4248B0C0 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_BUF_CREDIT_RX_S 21 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_BUF_CREDIT_RX_M RDMA_MASK3(32, 0x7FF, IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_BUF_CREDIT_RX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_RSVD3_S 20 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_RSVD3_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_RSVD3_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_PKT_CREDIT_RX_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_PKT_CREDIT_RX_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_PKT_CREDIT_RX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_RSVD2_S 13 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_RSVD2_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_BUF_CREDIT_TX_S 8 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_BUF_CREDIT_TX_M RDMA_MASK3(32, 0x1F, IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_BUF_CREDIT_TX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_RSVD1_S 4 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_PKT_CREDIT_TX_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_PKT_CREDIT_TX_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_CRT_TSCD_REQ_ALLOC_REQ_PKT_CREDIT_TX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC 0x4248B0C8 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSVD2_S 13 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSVD2_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSP_BUF_CREDIT_TX_S 8 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSP_BUF_CREDIT_TX_M RDMA_MASK3(32, 0x1F, IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSP_BUF_CREDIT_TX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSVD1_S 4 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSP_PKT_CREDIT_TX_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSP_PKT_CREDIT_TX_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_CRT_TSCD_RSP_ALLOC_RSP_PKT_CREDIT_TX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG 0x4248B200 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD3_S 20 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD3_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RM_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RM_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD2_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RME_S 12 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RME_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD1_S 10 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ERR_CNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_FIX_CNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD0_S 6 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_RSVD0_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_MASK_INT_S 5 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_MASK_INT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_LS_BYPASS_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_LS_FORCE_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_EN_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_CFG_ECC_EN_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS 0x4248B204 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_RSVD1_S 30 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_RSVD0_S 4 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_RSVD0_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_INIT_DONE_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_ECC_FIX_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CRT_VF_MEM_STATUS_ECC_ERR_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_PROFILE(_i) 0x4248A000 + ((_i) * 4) /* _i=0...1023 */ +#define IG3_PEPM_GLPE_PEPM_CRT_VF_PROFILE_MAX_INDEX_I 1023 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_PROFILE_RSVD_S 2 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_PROFILE_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_PROFILE_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_PROFILE_PROFILE_ID_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_PROFILE_PROFILE_ID_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_CRT_VF_PROFILE_PROFILE_ID_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_BUF_CRED(_i) 0x42489000 + ((_i) * 4) /* _i=0...1023 */ +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_BUF_CRED_MAX_INDEX_I 1023 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_BUF_CRED_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_BUF_CRED_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_BUF_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_BUF_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_BUF_CRED_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_BUF_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_PKT_CRED(_i) 0x42488000 + ((_i) * 4) /* _i=0...1023 */ +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_PKT_CRED_MAX_INDEX_I 1023 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_PKT_CRED_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_PKT_CRED_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_PKT_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_PKT_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_PKT_CRED_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_RX_PKT_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_BUF_CRED(_i) 0x42487000 + ((_i) * 4) /* _i=0...1023 */ +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_BUF_CRED_MAX_INDEX_I 1023 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_BUF_CRED_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_BUF_CRED_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_BUF_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_BUF_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_BUF_CRED_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_BUF_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_PKT_CRED(_i) 0x42486000 + ((_i) * 4) /* _i=0...1023 */ +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_PKT_CRED_MAX_INDEX_I 1023 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_PKT_CRED_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_PKT_CRED_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_PKT_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_PKT_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_PKT_CRED_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_VF_REQ_TX_PKT_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_BUF_CRED(_i) 0x42485000 + ((_i) * 4) /* _i=0...1023 */ +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_BUF_CRED_MAX_INDEX_I 1023 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_BUF_CRED_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_BUF_CRED_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_BUF_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_BUF_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_BUF_CRED_COUNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_BUF_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_PKT_CRED(_i) 0x42484000 + ((_i) * 4) /* _i=0...1023 */ +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_PKT_CRED_MAX_INDEX_I 1023 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_PKT_CRED_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_PKT_CRED_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_PKT_CRED_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_PKT_CRED_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_PKT_CRED_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_CRT_VF_RSP_TX_PKT_CRED_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_CSR_CNT_HI 0x4248B160 +#define IG3_PEPM_GLPE_PEPM_CSR_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_CSR_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CSR_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_CSR_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CSR_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_CSR_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_CSR_CNT_LO 0x4248B164 +#define IG3_PEPM_GLPE_PEPM_CSR_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_CSR_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_CSR_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_CTRL 0x42480000 +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_IDLE_S 31 +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_IDLE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CTRL_PEPM_IDLE_S) +#define IG3_PEPM_GLPE_PEPM_CTRL_RSVD2_S 24 +#define IG3_PEPM_GLPE_PEPM_CTRL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_CTRL_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_S 16 +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_CTRL_PEPM_PUSH_MARGIN_S) +#define IG3_PEPM_GLPE_PEPM_CTRL_RSVD1_S 9 +#define IG3_PEPM_GLPE_PEPM_CTRL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_CTRL_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_HALT_S 8 +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_HALT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CTRL_PEPM_HALT_S) +#define IG3_PEPM_GLPE_PEPM_CTRL_RSVD0_S 4 +#define IG3_PEPM_GLPE_PEPM_CTRL_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_CTRL_RSVD0_S) +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_TS_UPDATE_S 3 +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_TS_UPDATE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CTRL_PEPM_TS_UPDATE_S) +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_MODE_S 1 +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_MODE_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_CTRL_PEPM_MODE_S) +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_ENABLE_S 0 +#define IG3_PEPM_GLPE_PEPM_CTRL_PEPM_ENABLE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_CTRL_PEPM_ENABLE_S) +#define IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_HI 0x4248B148 +#define IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_LO 0x4248B14C +#define IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DEALLOC_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_COUNT 0x4248B1B8 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_CMD 0x4248B1CC +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_DATA_H 0x4248B1D8 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_DATA_L 0x4248B1D4 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_PTR 0x4248B1D0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_CMD 0x4248B1BC +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_DATA_H 0x4248B1C8 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_DATA_L 0x4248B1C4 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_PTR 0x4248B1C0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL 0x4248B180 +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD1_S 25 +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD2_S 17 +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD3_S 9 +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD3_S) +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_BYPASS_S 8 +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_CONTROL_BYPASS_S) +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD4_S 1 +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_DTM_CONTROL_RSVD4_S) +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_COR_ERR 0x4248B1E8 +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_UNCOR_ERR 0x4248B1E4 +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG 0x4248B18C +#define IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG 0x4248B190 +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG_MODE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_DTM_LOG_CFG_MODE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_MASK 0x4248B198 +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_LOG_MASK_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_PATTERN 0x4248B194 +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG 0x4248B184 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS 0x4248B188 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TIMESTAMP 0x4248B1B0 +#define IG3_PEPM_GLPE_PEPM_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_TIMESTAMP_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TIMESTAMP_ROLLOVER 0x4248B1B4 +#define IG3_PEPM_GLPE_PEPM_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG 0x4248B1DC +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS 0x4248B1E0 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG 0x4248B19C +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_DTM_TRIG_CFG_MODE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_COUNT 0x4248B1A8 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_MASK 0x4248B1A4 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_TRIG_MASK_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_PATTERN 0x4248B1A0 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_TIMESTAMP 0x4248B1AC +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PEPM_GLPE_PEPM_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PEPM_GLPE_PEPM_ECC_COR_ERR 0x4248B214 +#define IG3_PEPM_GLPE_PEPM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEPM_GLPE_PEPM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_ECC_COR_ERR_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_ECC_COR_ERR_CNT_S) +#define IG3_PEPM_GLPE_PEPM_ECC_UNCOR_ERR 0x4248B210 +#define IG3_PEPM_GLPE_PEPM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEPM_GLPE_PEPM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEPM_GLPE_PEPM_ERLID_CNT_HI 0x4248B108 +#define IG3_PEPM_GLPE_PEPM_ERLID_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_ERLID_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_ERLID_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_ERLID_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_ERLID_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_ERLID_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_ERLID_CNT_LO 0x4248B10C +#define IG3_PEPM_GLPE_PEPM_ERLID_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_ERLID_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_ERLID_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC 0x4248B0CC +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_RSVD2_S 30 +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_RSP_ERLID_ALLOC_SIZE_S 16 +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_RSP_ERLID_ALLOC_SIZE_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_RSP_ERLID_ALLOC_SIZE_S) +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_RSVD1_S 14 +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_REQ_ERLID_ALLOC_SIZE_S 0 +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_REQ_ERLID_ALLOC_SIZE_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_ALLOC_REQ_ERLID_ALLOC_SIZE_S) +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_PUSH 0x4248B0D0 +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_PUSH_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_PUSH_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_PUSH_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_PUSH_PUSH_ERLID_ALLOC_SIZE_S 0 +#define IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_PUSH_PUSH_ERLID_ALLOC_SIZE_M RDMA_MASK3(32, 0x3FFF, IG3_PEPM_GLPE_PEPM_ERLID_QUANTA_TX_PUSH_PUSH_ERLID_ALLOC_SIZE_S) +#define IG3_PEPM_GLPE_PEPM_ERR_MSK 0x4248B174 +#define IG3_PEPM_GLPE_PEPM_ERR_MSK_MASK_S 0 +#define IG3_PEPM_GLPE_PEPM_ERR_MSK_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_ERR_MSK_MASK_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC 0x4248B178 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_RSVD_S 30 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_RSVD_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_ERR_SRC_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_BUF_CNTR_FTZ_S 29 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_BUF_CNTR_FTZ_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_BUF_CNTR_FTZ_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_PKT_CNTR_FTZ_S 28 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_PKT_CNTR_FTZ_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_PKT_CNTR_FTZ_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VMIF_FIFO_OVF_S 27 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VMIF_FIFO_OVF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_VMIF_FIFO_OVF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VMIF_FIFO_UDF_S 26 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VMIF_FIFO_UDF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_VMIF_FIFO_UDF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TS_UPDATE_FIFO_OVF_S 25 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TS_UPDATE_FIFO_OVF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_TS_UPDATE_FIFO_OVF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TS_UPDATE_FIFO_UDF_S 24 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TS_UPDATE_FIFO_UDF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_TS_UPDATE_FIFO_UDF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_DEALLOC_FIFO_OVF_S 23 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_DEALLOC_FIFO_OVF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_DEALLOC_FIFO_OVF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_DEALLOC_FIFO_UDF_S 22 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_DEALLOC_FIFO_UDF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_DEALLOC_FIFO_UDF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_RSP_FIFO_UDF_S 21 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_RSP_FIFO_UDF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_RSP_FIFO_UDF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_REQ_FIFO_UDF_S 20 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_REQ_FIFO_UDF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_REQ_FIFO_UDF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_RSP_FIFO_OVF_S 19 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_RSP_FIFO_OVF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_RSP_FIFO_OVF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_REQ_FIFO_OVF_S 18 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_REQ_FIFO_OVF_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_TSIF_REQ_FIFO_OVF_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VMRL_DRP_TXBW_ERR_S 17 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VMRL_DRP_TXBW_ERR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_VMRL_DRP_TXBW_ERR_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VMRL_DRP_TRANS_ERR_S 16 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VMRL_DRP_TRANS_ERR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_VMRL_DRP_TRANS_ERR_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_ERL_CAM_VMISS_S 15 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_ERL_CAM_VMISS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_ERL_CAM_VMISS_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_ERL_CAM_MISS_S 14 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_ERL_CAM_MISS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_ERL_CAM_MISS_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_ERL_CAM_ALIGN_ERR_S 13 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_ERL_CAM_ALIGN_ERR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_ERL_CAM_ALIGN_ERR_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VF_CAM_VMISS_S 12 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VF_CAM_VMISS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_VF_CAM_VMISS_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VF_CAM_MISS_S 11 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VF_CAM_MISS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_VF_CAM_MISS_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VF_CAM_ALIGN_ERR_S 10 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_VF_CAM_ALIGN_ERR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_VF_CAM_ALIGN_ERR_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_HOST_CAM_VMISS_S 9 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_HOST_CAM_VMISS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_HOST_CAM_VMISS_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_HOST_CAM_MISS_S 8 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_HOST_CAM_MISS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_HOST_CAM_MISS_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_HOST_CAM_ALIGN_ERR_S 7 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_HOST_CAM_ALIGN_ERR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_HOST_CAM_ALIGN_ERR_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_UNEXPECTED_ARB_TRAN_S 6 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_UNEXPECTED_ARB_TRAN_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_UNEXPECTED_ARB_TRAN_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_DISABLED_W_ACT_REQS_S 5 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_DISABLED_W_ACT_REQS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_DISABLED_W_ACT_REQS_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_UNEXPECTED_PROTOCOL_S 4 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_UNEXPECTED_PROTOCOL_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_UNEXPECTED_PROTOCOL_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_POP_NO_PROTO_VLD_S 3 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_POP_NO_PROTO_VLD_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_POP_NO_PROTO_VLD_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_POP_NO_READ_VLD_S 2 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_POP_NO_READ_VLD_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_POP_NO_READ_VLD_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_PROTO_VLD_NO_POP_S 1 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_PROTO_VLD_NO_POP_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_PROTO_VLD_NO_POP_S) +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_READ_VLD_NO_POP_S 0 +#define IG3_PEPM_GLPE_PEPM_ERR_SRC_READ_VLD_NO_POP_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_ERR_SRC_READ_VLD_NO_POP_S) +#define IG3_PEPM_GLPE_PEPM_ERR_STS 0x4248B170 +#define IG3_PEPM_GLPE_PEPM_ERR_STS_ERR_S 0 +#define IG3_PEPM_GLPE_PEPM_ERR_STS_ERR_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_ERR_STS_ERR_S) +#define IG3_PEPM_GLPE_PEPM_FCG_MAP(_i) 0x42480800 + ((_i) * 4) /* _i=0...2175 */ +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_MAX_INDEX_I 2175 +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_VALID_S 31 +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_VALID_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_FCG_MAP_VALID_S) +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_RSVD1_S 30 +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_RSVD1_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_FCG_MAP_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_LLTC_S 29 +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_LLTC_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_FCG_MAP_LLTC_S) +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_CGD_S 23 +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_CGD_M RDMA_MASK3(32, 0x3F, IG3_PEPM_GLPE_PEPM_FCG_MAP_CGD_S) +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_VF_S 13 +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_VF_M RDMA_MASK3(32, 0x3FF, IG3_PEPM_GLPE_PEPM_FCG_MAP_VF_S) +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_HOST_S 10 +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_HOST_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_FCG_MAP_HOST_S) +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_ERLID_S 0 +#define IG3_PEPM_GLPE_PEPM_FCG_MAP_ERLID_M RDMA_MASK3(32, 0x3FF, IG3_PEPM_GLPE_PEPM_FCG_MAP_ERLID_S) +#define IG3_PEPM_GLPE_PEPM_FREE_CNT_HI 0x4248B168 +#define IG3_PEPM_GLPE_PEPM_FREE_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_FREE_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_FREE_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_FREE_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_FREE_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_FREE_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_FREE_CNT_LO 0x4248B16C +#define IG3_PEPM_GLPE_PEPM_FREE_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_FREE_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_FREE_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_FUNC_CNT_HI 0x4248B0E8 +#define IG3_PEPM_GLPE_PEPM_FUNC_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_FUNC_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_FUNC_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_FUNC_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_FUNC_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_FUNC_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_FUNC_CNT_LO 0x4248B0EC +#define IG3_PEPM_GLPE_PEPM_FUNC_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_FUNC_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_FUNC_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_HI 0x4248B120 +#define IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_LO 0x4248B124 +#define IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_GLOBAL_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_HOST_CNT_HI 0x4248B0E0 +#define IG3_PEPM_GLPE_PEPM_HOST_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_HOST_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_HOST_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_HOST_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_HOST_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_HOST_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_HOST_CNT_LO 0x4248B0E4 +#define IG3_PEPM_GLPE_PEPM_HOST_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_HOST_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_HOST_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_INFLT_CNT_HI 0x4248B0F0 +#define IG3_PEPM_GLPE_PEPM_INFLT_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_INFLT_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_INFLT_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_INFLT_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_INFLT_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_INFLT_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_INFLT_CNT_LO 0x4248B0F4 +#define IG3_PEPM_GLPE_PEPM_INFLT_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_INFLT_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_INFLT_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_LLTC_CNT_HI 0x4248B0F8 +#define IG3_PEPM_GLPE_PEPM_LLTC_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_LLTC_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_LLTC_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_LLTC_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_LLTC_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_LLTC_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_LLTC_CNT_LO 0x4248B0FC +#define IG3_PEPM_GLPE_PEPM_LLTC_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_LLTC_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_LLTC_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_PFC_CNT_HI 0x4248B158 +#define IG3_PEPM_GLPE_PEPM_PFC_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_PFC_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_PFC_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_PFC_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_PFC_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_PFC_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_PFC_CNT_LO 0x4248B15C +#define IG3_PEPM_GLPE_PEPM_PFC_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_PFC_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_PFC_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_HI 0x4248B118 +#define IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_LO 0x4248B11C +#define IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_PFC_FC_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1 0x4248B0D4 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_RSVD2_S 30 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_PMON_CTRL1_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_ERLID_SEL_S 20 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_ERLID_SEL_M RDMA_MASK3(32, 0x3FF, IG3_PEPM_GLPE_PEPM_PMON_CTRL1_ERLID_SEL_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_VF_SEL_S 8 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_VF_SEL_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_PMON_CTRL1_VF_SEL_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_RSVD1_S 7 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_RSVD1_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_PMON_CTRL1_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_HOST_SEL_S 4 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_HOST_SEL_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_PMON_CTRL1_HOST_SEL_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_GLOBAL_SEL_S 2 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_GLOBAL_SEL_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_PMON_CTRL1_GLOBAL_SEL_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_START_CNTS_S 1 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_START_CNTS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_PMON_CTRL1_START_CNTS_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_CLEAR_CNTS_S 0 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL1_CLEAR_CNTS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_PMON_CTRL1_CLEAR_CNTS_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2 0x4248B0D8 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_RSVD1_S 30 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_PMON_CTRL2_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_ICQ_PORT_S 28 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_ICQ_PORT_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_PMON_CTRL2_ICQ_PORT_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_ICQ_TC_S 25 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_ICQ_TC_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_PMON_CTRL2_ICQ_TC_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_TC_SEL_S 22 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_TC_SEL_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_PMON_CTRL2_TC_SEL_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_LLTC_SEL_S 19 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_LLTC_SEL_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_PMON_CTRL2_LLTC_SEL_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_INFLT_SEL_S 16 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_INFLT_SEL_M RDMA_MASK3(32, 0x7, IG3_PEPM_GLPE_PEPM_PMON_CTRL2_INFLT_SEL_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_RSVD_S 14 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_RSVD_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_PMON_CTRL2_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_QSET_GRP_S 12 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_QSET_GRP_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_PMON_CTRL2_QSET_GRP_S) +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_QSET_SEL_S 0 +#define IG3_PEPM_GLPE_PEPM_PMON_CTRL2_QSET_SEL_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_PMON_CTRL2_QSET_SEL_S) +#define IG3_PEPM_GLPE_PEPM_PMON_SMPL 0x4248B0DC +#define IG3_PEPM_GLPE_PEPM_PMON_SMPL_SAMPLE_CLKS_S 0 +#define IG3_PEPM_GLPE_PEPM_PMON_SMPL_SAMPLE_CLKS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_PMON_SMPL_SAMPLE_CLKS_S) +#define IG3_PEPM_GLPE_PEPM_PUSH_CNT_HI 0x4248B140 +#define IG3_PEPM_GLPE_PEPM_PUSH_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_PUSH_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_PUSH_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_PUSH_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_PUSH_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_PUSH_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_PUSH_CNT_LO 0x4248B144 +#define IG3_PEPM_GLPE_PEPM_PUSH_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_PUSH_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_PUSH_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_HI 0x4248B130 +#define IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_LO 0x4248B134 +#define IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_PUSH_NAK_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_QSET_CNT_HI 0x4248B110 +#define IG3_PEPM_GLPE_PEPM_QSET_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_QSET_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_QSET_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_QSET_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_QSET_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_QSET_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_QSET_CNT_LO 0x4248B114 +#define IG3_PEPM_GLPE_PEPM_QSET_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_QSET_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_QSET_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TC_CNT_HI 0x4248B100 +#define IG3_PEPM_GLPE_PEPM_TC_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_TC_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_TC_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TC_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TC_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_TC_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TC_CNT_LO 0x4248B104 +#define IG3_PEPM_GLPE_PEPM_TC_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TC_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_TC_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TSCD_CNT_HI 0x4248B138 +#define IG3_PEPM_GLPE_PEPM_TSCD_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_TSCD_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_TSCD_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TSCD_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TSCD_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_TSCD_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TSCD_CNT_LO 0x4248B13C +#define IG3_PEPM_GLPE_PEPM_TSCD_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TSCD_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_TSCD_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_HI 0x4248B128 +#define IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_LO 0x4248B12C +#define IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_TSCD_NAK_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TSUPD_CNT_HI 0x4248B150 +#define IG3_PEPM_GLPE_PEPM_TSUPD_CNT_HI_RSVD_S 16 +#define IG3_PEPM_GLPE_PEPM_TSUPD_CNT_HI_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_TSUPD_CNT_HI_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TSUPD_CNT_HI_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TSUPD_CNT_HI_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_PEPM_GLPE_PEPM_TSUPD_CNT_HI_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TSUPD_CNT_LO 0x4248B154 +#define IG3_PEPM_GLPE_PEPM_TSUPD_CNT_LO_CNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TSUPD_CNT_LO_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEPM_GLPE_PEPM_TSUPD_CNT_LO_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_BYTES(_i) 0x424833C0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_AGG_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_AGG_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_AGG_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HBUF(_i) 0x424833A0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_AGG_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_AGG_HBUF_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_BYTES(_i) 0x42483400 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_AGG_HW_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_BYTES_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_BYTES_THRESH_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_AGG_HW_BYTES_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_HBUF(_i) 0x424833E0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_AGG_HW_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_HBUF_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_HW_HBUF_THRESH_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_AGG_HW_HBUF_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_BYTES(_i) 0x42483440 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_AGG_LW_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_BYTES_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_BYTES_THRESH_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_AGG_LW_BYTES_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_HBUF(_i) 0x42483420 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_AGG_LW_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_HBUF_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_AGG_LW_HBUF_THRESH_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_AGG_LW_HBUF_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_BYTES 0x42483704 +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_ALLOC_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_BYTES_BYTES_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_BYTES_BYTES_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_ALLOC_BYTES_BYTES_S) +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_HBUF 0x42483700 +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_HBUF_RSVD_S 4 +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_HBUF_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PEPM_GLPE_PEPM_TS_ALLOC_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_HBUF_CREDIT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_ALLOC_HBUF_CREDIT_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_TS_ALLOC_HBUF_CREDIT_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG 0x4248B208 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD3_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD3_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RM_S 16 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RM_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD2_S 14 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD2_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RME_S 12 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RME_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD1_S 10 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ERR_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_FIX_CNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD0_S 6 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_RSVD0_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_MASK_INT_S 5 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_MASK_INT_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_LS_BYPASS_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_LS_FORCE_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_EN_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_CFG_ECC_EN_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS 0x4248B20C +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_RSVD1_S 30 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_RSVD1_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_RSVD0_S 4 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_RSVD0_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_INIT_DONE_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_ECC_FIX_S) +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEPM_GLPE_PEPM_TS_CGD_MEM_STATUS_ECC_ERR_S) +#define IG3_PEPM_GLPE_PEPM_TS_HW_BYTES(_i) 0x42483100 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_HW_BYTES_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_HW_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_HW_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_HW_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_HW_BYTES_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_HW_BYTES_THRESH_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_HW_BYTES_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_HW_HBUF(_i) 0x42483000 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_HW_HBUF_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_HW_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_HW_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_HW_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_HW_HBUF_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_HW_HBUF_THRESH_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_HW_HBUF_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_IB_BYTES(_i) 0x42482B00 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_IB_BYTES_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_IB_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_IB_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_IB_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_IB_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_IB_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_IB_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_IB_HBUF(_i) 0x42482A00 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_IB_HBUF_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_IB_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_IB_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_IB_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_IB_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_IB_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_IB_HBUF_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_BYTES(_i) 0x424835C0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_HBUF(_i) 0x424835A0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_IB_HBUF_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_BYTES(_i) 0x42483600 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_HBUF(_i) 0x424835E0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_RB_HBUF_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_BYTES(_i) 0x42483640 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_HBUF(_i) 0x42483620 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_AGG_WB_HBUF_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_BYTES(_i) 0x42483680 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_BYTES_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_BYTES_THRESH_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_BYTES_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_HBUF(_i) 0x42483660 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_HBUF_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_HBUF_THRESH_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_HW_HBUF_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_BYTES(_i) 0x424836C0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_BYTES_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_BYTES_THRESH_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_BYTES_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_HBUF(_i) 0x424836A0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_HBUF_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_HBUF_THRESH_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_LW_HBUF_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_MAP(_i) 0x424836E0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_MAP_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_MAP_RSVD_S 8 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_MAP_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_MAP_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_MAP_TCMAP_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LLTC_MAP_TCMAP_M RDMA_MASK3(32, 0xFF, IG3_PEPM_GLPE_PEPM_TS_LLTC_MAP_TCMAP_S) +#define IG3_PEPM_GLPE_PEPM_TS_LW_BYTES(_i) 0x42483300 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_LW_BYTES_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_LW_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_LW_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_LW_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LW_BYTES_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LW_BYTES_THRESH_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_LW_BYTES_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_LW_HBUF(_i) 0x42483200 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_LW_HBUF_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_LW_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_LW_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_LW_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_LW_HBUF_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_LW_HBUF_THRESH_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_LW_HBUF_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_RB_BYTES(_i) 0x42482D00 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_RB_BYTES_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_RB_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_RB_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_RB_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_RB_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_RB_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_RB_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_RB_HBUF(_i) 0x42482C00 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_RB_HBUF_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_RB_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_RB_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_RB_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_RB_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_RB_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_RB_HBUF_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_BYTES(_i) 0x42483480 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_HBUF(_i) 0x42483460 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_IB_HBUF_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_BYTES(_i) 0x424834C0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_HBUF(_i) 0x424834A0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_RB_HBUF_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_BYTES(_i) 0x42483500 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_HBUF(_i) 0x424834E0 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_TC_AGG_WB_HBUF_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_BYTES(_i) 0x42483540 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_TC_HW_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_BYTES_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_BYTES_THRESH_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_TC_HW_BYTES_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_HBUF(_i) 0x42483520 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_TC_HW_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_HBUF_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_HW_HBUF_THRESH_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_TC_HW_HBUF_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_BYTES(_i) 0x42483580 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_BYTES_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_TC_LW_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_BYTES_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_BYTES_THRESH_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_TC_LW_BYTES_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_HBUF(_i) 0x42483560 + ((_i) * 4) /* _i=0...4 */ +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_HBUF_MAX_INDEX_I 4 +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_TC_LW_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_HBUF_THRESH_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_TC_LW_HBUF_THRESH_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_TC_LW_HBUF_THRESH_S) +#define IG3_PEPM_GLPE_PEPM_TS_WB_BYTES(_i) 0x42482F00 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_WB_BYTES_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_WB_BYTES_RSVD_S 20 +#define IG3_PEPM_GLPE_PEPM_TS_WB_BYTES_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_PEPM_GLPE_PEPM_TS_WB_BYTES_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_WB_BYTES_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_WB_BYTES_COUNT_M RDMA_MASK3(32, 0xFFFFF, IG3_PEPM_GLPE_PEPM_TS_WB_BYTES_COUNT_S) +#define IG3_PEPM_GLPE_PEPM_TS_WB_HBUF(_i) 0x42482E00 + ((_i) * 4) /* _i=0...39 */ +#define IG3_PEPM_GLPE_PEPM_TS_WB_HBUF_MAX_INDEX_I 39 +#define IG3_PEPM_GLPE_PEPM_TS_WB_HBUF_RSVD_S 13 +#define IG3_PEPM_GLPE_PEPM_TS_WB_HBUF_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEPM_GLPE_PEPM_TS_WB_HBUF_RSVD_S) +#define IG3_PEPM_GLPE_PEPM_TS_WB_HBUF_COUNT_S 0 +#define IG3_PEPM_GLPE_PEPM_TS_WB_HBUF_COUNT_M RDMA_MASK3(32, 0x1FFF, IG3_PEPM_GLPE_PEPM_TS_WB_HBUF_COUNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_BUS_INDEX 0x424C0290 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL 0x424C0280 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_RESERVED_31_10_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_TRIG_OP_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_TRIG_OP_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_FREEZE_RESET_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_CTRL_FREEZE_SET_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_FREEZE_ON_CNT_VAL 0x424C02A0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_OBS_BUS 0x424C02C0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT0 0x424C02E0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT0_CNT0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT1_0 0x424C02E8 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT1_1 0x424C02EC +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL 0x424C02D8 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_CTRL 0x424C02B8 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_GAP 0x424C02A8 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_GAP_RC_GAP_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_TRNS 0x424C02B0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS 0x424C0288 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_RESERVED_31_8_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_I_FREEZE_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_I_FREEZE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_READY_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_READY_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_VALID_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_VALID_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRANS_CNT 0x424C0298 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRIG_MASK 0x424C02C8 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRIG_VALUE 0x424C02D0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BOB_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL 0x424C024C +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_DONE_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_RD_EN_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_RD_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_RSVD_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_DW_SEL_S 18 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_DW_SEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_ADR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_CTL_ADR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_DATA 0x424C0250 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_DATA_RD_DW_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_DBG_DATA_RD_DW_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG 0x424C0244 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD3_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RM_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD2_S 14 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RME_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RME_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD1_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ERR_CNT_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_FIX_CNT_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_FIX_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD0_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_MASK_INT_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_MASK_INT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_LS_BYPASS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_LS_FORCE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_LS_FORCE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_EN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_CFG_ECC_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS 0x424C0248 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_RSVD1_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_RSVD0_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_ECC_FIX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_BRANCH_TABLE_MEM_STATUS_ECC_ERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_COUNT 0x424C0338 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_CMD 0x424C034C +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_DATA_H 0x424C0358 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_DATA_L 0x424C0354 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_PTR 0x424C0350 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_CMD 0x424C033C +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_DATA_H 0x424C0348 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_DATA_L 0x424C0344 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_PTR 0x424C0340 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL 0x424C0300 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD1_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD2_S 17 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD3_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_BYPASS_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_BYPASS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD4_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_RSVD4_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_CONTROL_LOCAL_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_COR_ERR 0x424C0368 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_COR_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_UNCOR_ERR 0x424C0364 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG 0x424C030C +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG 0x424C0310 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG_MODE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_CFG_MODE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_MASK 0x424C0318 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_MASK_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_MASK_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_PATTERN 0x424C0314 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_LOG_PATTERN_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG 0x424C0304 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS 0x424C0308 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TIMESTAMP 0x424C0330 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TIMESTAMP_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TIMESTAMP_ROLLOVER 0x424C0334 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG 0x424C035C +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS 0x424C0360 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG 0x424C031C +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_MODE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_CFG_MODE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_COUNT 0x424C0328 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_COUNT_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_MASK 0x424C0324 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_MASK_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_PATTERN 0x424C0320 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_TIMESTAMP 0x424C032C +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_COR_ERR 0x424C01F0 +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_COR_ERR_RSVD_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_ECC_COR_ERR_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_COR_ERR_CNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_ECC_COR_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_UNCOR_ERR 0x424C01EC +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_ECC_UNCOR_ERR_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_ECC_UNCOR_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG 0x424C015C +#define IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG_RSVD_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG_BRANCH_LOOP_DETECTED_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG_BRANCH_LOOP_DETECTED_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG_BRANCH_LOOP_DETECTED_S) +#define IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG_FWERR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG_FWERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_ERRSTATREG_FWERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FIFO_OVF_CAPTURE 0x424C01E4 +#define IG3_MEV_TSCD_GLPE_TSCD_FIFO_OVF_CAPTURE_FIFO_OVF_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_FIFO_OVF_CAPTURE_FIFO_OVF_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_FIFO_OVF_CAPTURE_FIFO_OVF_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FIFO_UDF_CAPTURE 0x424C01E8 +#define IG3_MEV_TSCD_GLPE_TSCD_FIFO_UDF_CAPTURE_FIFO_UDF_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_FIFO_UDF_CAPTURE_FIFO_UDF_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_FIFO_UDF_CAPTURE_FIFO_UDF_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FLR(_i) 0x424C016C + ((_i) * 4) /* _i=0...7 */ +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_MAX_INDEX_I 7 +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_BUSY_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_BUSY_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_FLR_BUSY_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_HOSTID_S 28 +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_HOSTID_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_FLR_HOSTID_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_VM_VF_TYPE_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_FLR_VM_VF_TYPE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_PF_NUM_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_MEV_TSCD_GLPE_TSCD_FLR_PF_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_VM_VF_NUM_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_FLR_VM_VF_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_PORT_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_PORT_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_FLR_PORT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_RSVD0_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_FLR_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_FLR_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQHI 0x424C0168 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQHI_PMF_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQHI_PMF_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQHI_PMF_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQHI_RSVD_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQHI_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQHI_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO 0x424C0164 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_BUSY_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_BUSY_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_BUSY_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_HOSTID_S 28 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_HOSTID_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_VM_VF_TYPE_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_VM_VF_TYPE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_PF_NUM_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_PF_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_VM_VF_NUM_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_VM_VF_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_TAG_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_TAG_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_FWSYNCREQLO_TAG_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH 0x424C009C +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_RSVD_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_RSVD_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_VALUE_ENTRYIDX_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_VALUE_ENTRYIDX_M RDMA_MASK3(32, 0x7FFFF, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_VALUE_ENTRYIDX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_FLDSZ_S 7 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_FLDSZ_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_FLDSZ_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_FLDOFFS_NUMENTS_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_FLDOFFS_NUMENTS_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDH_FLDOFFS_NUMENTS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL 0x424C0098 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_NTROOTNODE_S 29 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_NTROOTNODE_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_NTROOTNODE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_RSVD_S 28 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_RSVD_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_NTLEVEL_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_NTLEVEL_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_NTLEVEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_CTRLTYPE_S 22 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_CTRLTYPE_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_CTRLTYPE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_TBLENTRYIDX_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_TBLENTRYIDX_M RDMA_MASK3(32, 0x3FFF, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_TBLENTRYIDX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_TBLTYPE_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_TBLTYPE_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_TBLTYPE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_OPCODE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_OPCODE_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_IFBCMDL_OPCODE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL 0x424C00A4 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_PATHMASKCLRCNT_S 24 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_PATHMASKCLRCNT_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_PATHMASKCLRCNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_NWATIMER_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_NWATIMER_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_NWATIMER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_RSVD_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_RSVD_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_IOQDEPTH1_EN_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_IOQDEPTH1_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_IOQDEPTH1_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_NODE_SCAN_EN_S 7 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_NODE_SCAN_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_NODE_SCAN_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_ISSUE_FILTER_EN_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_ISSUE_FILTER_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_ISSUE_FILTER_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_NODE_HIERARCHY_EN_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_NODE_HIERARCHY_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_NODE_HIERARCHY_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_QSET_DIRECT_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_QSET_DIRECT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_QSET_DIRECT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_SCH_ENA_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_SCH_ENA_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_SCH_ENA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_BCMDCLRERR_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_BCMDCLRERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_BCMDCLRERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_ICMDCLRERR_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_ICMDCLRERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_ICMDCLRERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_BCMDDB_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_BCMDDB_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFCTRL_BCMDDB_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFDATA(_i) 0x424C0080 + ((_i) * 4) /* _i=0...3 */ +#define IG3_MEV_TSCD_GLPE_TSCD_IFDATA_MAX_INDEX_I 3 +#define IG3_MEV_TSCD_GLPE_TSCD_IFDATA_TSCDIFDATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_IFDATA_TSCDIFDATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_IFDATA_TSCDIFDATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFDATA_INFO 0x424C0000 +#define IG3_MEV_TSCD_GLPE_TSCD_IFDATA_INFO_RSVD_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_IFDATA_INFO_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_IFDATA_INFO_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFDATA_INFO_NUM_IFDATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_IFDATA_INFO_NUM_IFDATA_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_IFDATA_INFO_NUM_IFDATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDH 0x424C0094 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_RSVD_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_RSVD_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_VALUE_ENTRYIDX_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_VALUE_ENTRYIDX_M RDMA_MASK3(32, 0x7FFFF, IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_VALUE_ENTRYIDX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_FLDSZ_S 7 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_FLDSZ_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_FLDSZ_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_FLDOFFS_NUMENTS_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_FLDOFFS_NUMENTS_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_IFICMDH_FLDOFFS_NUMENTS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL 0x424C0090 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_NTROOTNODE_S 29 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_NTROOTNODE_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_NTROOTNODE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_RSVD_S 28 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_RSVD_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_NTLEVEL_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_NTLEVEL_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_NTLEVEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_CTRLTYPE_S 22 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_CTRLTYPE_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_CTRLTYPE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_TBLENTRYIDX_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_TBLENTRYIDX_M RDMA_MASK3(32, 0x3FFF, IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_TBLENTRYIDX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_TBLTYPE_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_TBLTYPE_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_TBLTYPE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_OPCODE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_OPCODE_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_IFICMDL_OPCODE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS 0x424C00A0 +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_RSVD_S 11 +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_RSVD_M RDMA_MASK3(32, 0x1FFFFF, IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_SCH_IDLE_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_SCH_IDLE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_SCH_IDLE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_SCH_ENA_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_SCH_ENA_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_SCH_ENA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_BCMDERR_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_BCMDERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_BCMDERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_ICMDERR_S 7 +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_ICMDERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_ICMDERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_ICMDBZ_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_ICMDBZ_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_ICMDBZ_S) +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_ENTRAVAIL_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_ENTRAVAIL_M RDMA_MASK3(32, 0x3F, IG3_MEV_TSCD_GLPE_TSCD_IFSTATUS_ENTRAVAIL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_INCSCHEDCFGCOUNT 0x424C0158 +#define IG3_MEV_TSCD_GLPE_TSCD_INCSCHEDCFGCOUNT_INCSCHEDCFGCOUNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_INCSCHEDCFGCOUNT_INCSCHEDCFGCOUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_INCSCHEDCFGCOUNT_INCSCHEDCFGCOUNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL 0x424C01FC +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_DONE_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_RD_EN_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_RD_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_RSVD_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_DW_SEL_S 18 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_DW_SEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_ADR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_CTL_ADR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_DATA 0x424C0200 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_DATA_RD_DW_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_DBG_DATA_RD_DW_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG 0x424C01F4 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD3_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RM_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD2_S 14 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RME_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RME_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD1_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ERR_CNT_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_FIX_CNT_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_FIX_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD0_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_MASK_INT_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_MASK_INT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_LS_BYPASS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_LS_FORCE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_LS_FORCE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_EN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_CFG_ECC_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS 0x424C01F8 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_RSVD1_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_RSVD0_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_ECC_FIX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L3_NODE_TABLE_MEM_STATUS_ECC_ERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL 0x424C020C +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_DONE_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_RD_EN_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_RD_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_RSVD_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_DW_SEL_S 18 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_DW_SEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_ADR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_CTL_ADR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_DATA 0x424C0210 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_DATA_RD_DW_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_DBG_DATA_RD_DW_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG 0x424C0204 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD3_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RM_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD2_S 14 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RME_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RME_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD1_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ERR_CNT_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_FIX_CNT_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_FIX_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD0_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_MASK_INT_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_MASK_INT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_LS_BYPASS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_LS_FORCE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_LS_FORCE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_EN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_CFG_ECC_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS 0x424C0208 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_RSVD1_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_RSVD0_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_ECC_FIX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L4_NODE_TABLE_MEM_STATUS_ECC_ERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL 0x424C021C +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_DONE_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_RD_EN_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_RD_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_RSVD_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_DW_SEL_S 18 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_DW_SEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_ADR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_CTL_ADR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_DATA 0x424C0220 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_DATA_RD_DW_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_DBG_DATA_RD_DW_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG 0x424C0214 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD3_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RM_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD2_S 14 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RME_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RME_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD1_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ERR_CNT_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_FIX_CNT_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_FIX_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD0_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_MASK_INT_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_MASK_INT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_LS_BYPASS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_LS_FORCE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_LS_FORCE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_EN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_CFG_ECC_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS 0x424C0218 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_RSVD1_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_RSVD0_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_ECC_FIX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L5_NODE_TABLE_MEM_STATUS_ECC_ERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL 0x424C022C +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_DONE_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_RD_EN_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_RD_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_RSVD_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_DW_SEL_S 18 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_DW_SEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_ADR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_CTL_ADR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_DATA 0x424C0230 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_DATA_RD_DW_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_DBG_DATA_RD_DW_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG 0x424C0224 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD3_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RM_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD2_S 14 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RME_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RME_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD1_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ERR_CNT_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_FIX_CNT_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_FIX_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD0_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_MASK_INT_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_MASK_INT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_LS_BYPASS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_LS_FORCE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_LS_FORCE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_EN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_CFG_ECC_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS 0x424C0228 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_RSVD1_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_RSVD0_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_ECC_FIX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L6_NODE_TABLE_MEM_STATUS_ECC_ERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL 0x424C023C +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_DONE_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_RD_EN_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_RD_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_RSVD_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_DW_SEL_S 18 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_DW_SEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_ADR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_CTL_ADR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_DATA 0x424C0240 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_DATA_RD_DW_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_DBG_DATA_RD_DW_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG 0x424C0234 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD3_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RM_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD2_S 14 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RME_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RME_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD1_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ERR_CNT_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_FIX_CNT_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_FIX_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD0_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_MASK_INT_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_MASK_INT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_LS_BYPASS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_LS_FORCE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_LS_FORCE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_EN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_CFG_ECC_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS 0x424C0238 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_RSVD1_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_RSVD0_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_ECC_FIX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_L7_NODE_TABLE_MEM_STATUS_ECC_ERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_INFO 0x424C0008 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MAX_RN_S 24 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MAX_RN_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MAX_RN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MIN_RN_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MIN_RN_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MIN_RN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MAX_LVL_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MAX_LVL_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MAX_LVL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MIN_LVL_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MIN_LVL_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_NT_INFO_MIN_LVL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL(_i) 0x424C002C + ((_i) * 16) /* _i=0...0 */ +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_MAX_INDEX_I 0 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_RESERVED3_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_RESERVED3_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_RESERVED3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO0 0x424C0010 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO0_MAX_TOTAL_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO0_MAX_TOTAL_M RDMA_MASK3(32, 0xFFFF, IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO0_MAX_TOTAL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO0_MAX_PER_ROOT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO0_MAX_PER_ROOT_M RDMA_MASK3(32, 0xFFFF, IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO0_MAX_PER_ROOT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO1 0x424C0014 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO1_RESERVED1_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO1_RESERVED1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO1_RESERVED1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2 0x424C0018 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_MAX_CHILDREN_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_MAX_CHILDREN_M RDMA_MASK3(32, 0xFFFF, IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_MAX_CHILDREN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_CHILD_NALLOC_SIZE_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_CHILD_NALLOC_SIZE_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_CHILD_NALLOC_SIZE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_CHILD_ALIGNMENT_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_CHILD_ALIGNMENT_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_CHILD_ALIGNMENT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_MIN_CHILDREN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_MIN_CHILDREN_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO2_MIN_CHILDREN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO3 0x424C001C +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO3_RESERVED3_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO3_RESERVED3_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_NT_LVL_L1_INFO3_RESERVED3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PEPM 0x424C0160 +#define IG3_MEV_TSCD_GLPE_TSCD_PEPM_RSVD_S 14 +#define IG3_MEV_TSCD_GLPE_TSCD_PEPM_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_PEPM_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PEPM_QUANTA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_PEPM_QUANTA_M RDMA_MASK3(32, 0x3FFF, IG3_MEV_TSCD_GLPE_TSCD_PEPM_QUANTA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL(_i) 0x424C0118 + ((_i) * 4) /* _i=0...15 */ +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_MAX_INDEX_I 15 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_RSVD1_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_QSINDEX_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_QSINDEX_M RDMA_MASK3(32, 0x3FF, IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_QSINDEX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_RSVD0_S 13 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_RSVD0_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_TCINDEX_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_TCINDEX_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_TCINDEX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_PORTINDEX_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_PORTINDEX_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_PORTINDEX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_RESOURCESELECT_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_RESOURCESELECT_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_RESOURCESELECT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_COUNTERTYPE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_COUNTERTYPE_M RDMA_MASK3(32, 0x7, IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCONTROL_COUNTERTYPE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCOUNT(_i) 0x424C00D8 + ((_i) * 4) /* _i=0...15 */ +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCOUNT_MAX_INDEX_I 15 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCOUNT_PRGPERFCOUNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCOUNT_PRGPERFCOUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_PRGPERFCOUNT_PRGPERFCOUNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QST_INFO 0x424C0004 +#define IG3_MEV_TSCD_GLPE_TSCD_QST_INFO_MAX_QS_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_QST_INFO_MAX_QS_M RDMA_MASK3(32, 0xFFFF, IG3_MEV_TSCD_GLPE_TSCD_QST_INFO_MAX_QS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QST_INFO_MIN_QS_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_QST_INFO_MIN_QS_M RDMA_MASK3(32, 0xFFFF, IG3_MEV_TSCD_GLPE_TSCD_QST_INFO_MIN_QS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL 0x424C025C +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_DONE_S 31 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_RD_EN_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_RD_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_RSVD_S 26 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_DW_SEL_S 18 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_DW_SEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_ADR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_CTL_ADR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_DATA 0x424C0260 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_DATA_RD_DW_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_DBG_DATA_RD_DW_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG 0x424C0254 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD3_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD3_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RM_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RM_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD2_S 14 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RME_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RME_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD1_S 10 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ERR_CNT_S 9 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ERR_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_FIX_CNT_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_FIX_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD0_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_MASK_INT_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_MASK_INT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_LS_BYPASS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_LS_FORCE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_LS_FORCE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_EN_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_CFG_ECC_EN_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS 0x424C0258 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_RSVD1_S 30 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_RSVD0_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_INIT_DONE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_ECC_FIX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_QUEUE_SET_TABLE_MEM_STATUS_ECC_ERR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2CMD 0x424C00AC +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2CMD_RSVD_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2CMD_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2CMD_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2CMD_RLMTBLIDX_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2CMD_RLMTBLIDX_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2CMD_RLMTBLIDX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAHI 0x424C00D4 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAHI_DATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAHI_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAHI_DATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATALO 0x424C00C8 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATALO_DATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATALO_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATALO_DATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAMIDHI 0x424C00D0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAMIDHI_DATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAMIDHI_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAMIDHI_DATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAMIDLO 0x424C00CC +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAMIDLO_DATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAMIDLO_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2DATAMIDLO_DATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2STATUS 0x424C00B4 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2STATUS_RSVD_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2STATUS_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2STATUS_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2STATUS_VALID_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2STATUS_VALID_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRD2STATUS_VALID_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDCMD 0x424C00A8 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDCMD_RSVD_S 12 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDCMD_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDCMD_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDCMD_RLMTBLIDX_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDCMD_RLMTBLIDX_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDCMD_RLMTBLIDX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAHI 0x424C00C4 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAHI_DATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAHI_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAHI_DATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATALO 0x424C00B8 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATALO_DATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATALO_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATALO_DATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAMIDHI 0x424C00C0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAMIDHI_DATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAMIDHI_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAMIDHI_DATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAMIDLO 0x424C00BC +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAMIDLO_DATA_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAMIDLO_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDDATAMIDLO_DATA_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDSTATUS 0x424C00B0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDSTATUS_RSVD_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDSTATUS_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDSTATUS_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDSTATUS_VALID_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDSTATUS_VALID_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_RLMTBLRDSTATUS_VALID_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL 0x424C018C +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL_RSVD_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL_FREERUN_TOGGLE_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL_FREERUN_TOGGLE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL_FREERUN_TOGGLE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL_ONESHOT_TOGGLE_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL_ONESHOT_TOGGLE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_CTL_ONESHOT_TOGGLE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_ENTRY_OP_CNT(_i) 0x424C01CC + ((_i) * 4) /* _i=0...1 */ +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_ENTRY_OP_CNT_MAX_INDEX_I 1 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_ENTRY_OP_CNT_ENTRY_OP_CNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_ENTRY_OP_CNT_ENTRY_OP_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_ENTRY_OP_CNT_ENTRY_OP_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_DISPOSITION_CNT(_i) 0x424C01C4 + ((_i) * 4) /* _i=0...1 */ +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_DISPOSITION_CNT_MAX_INDEX_I 1 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_DISPOSITION_CNT_EXIT_DISPOSITION_CNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_DISPOSITION_CNT_EXIT_DISPOSITION_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_DISPOSITION_CNT_EXIT_DISPOSITION_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_LATENCY_HISTO_BINCNT(_i) 0x424C01A4 + ((_i) * 4) /* _i=0...7 */ +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_LATENCY_HISTO_BINCNT_MAX_INDEX_I 7 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_LATENCY_HISTO_BINCNT_EXITLATENCY_HISTO_BINCNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_LATENCY_HISTO_BINCNT_EXITLATENCY_HISTO_BINCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_EXIT_LATENCY_HISTO_BINCNT_EXITLATENCY_HISTO_BINCNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_NWA_DONE_CNT 0x424C01D8 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_NWA_DONE_CNT_NWA_DONE_CNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_NWA_DONE_CNT_NWA_DONE_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_NWA_DONE_CNT_NWA_DONE_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_PREFETCH_LOAD_CNT 0x424C01D4 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_PREFETCH_LOAD_CNT_PREFETCH_LOAD_CNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_PREFETCH_LOAD_CNT_PREFETCH_LOAD_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_PREFETCH_LOAD_CNT_PREFETCH_LOAD_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_CTL 0x424C01DC +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_CTL_RSVD_S 7 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_CTL_RSVD_M RDMA_MASK3(32, 0x1FFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_CTL_RSVD_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_CTL_QSETS_ISSUED_INDEX_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_CTL_QSETS_ISSUED_INDEX_M RDMA_MASK3(32, 0x7F, IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_CTL_QSETS_ISSUED_INDEX_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_DATA 0x424C01E0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_DATA_QSETS_ISSUED_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_DATA_QSETS_ISSUED_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_QSETS_ISSUED_DATA_QSETS_ISSUED_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS 0x424C0194 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_FREERUN_ROLLOVER_CNT_S 24 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_FREERUN_ROLLOVER_CNT_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_FREERUN_ROLLOVER_CNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_RSVD2_S 23 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_RSVD2_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_RSVD2_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_WAMON_EDGE_ROLLOVER_S 22 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_WAMON_EDGE_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_WAMON_EDGE_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_WAMON_LVL_ROLLOVER_S 21 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_WAMON_LVL_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_WAMON_LVL_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_PREFETCH_ROLLOVER_S 20 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_PREFETCH_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_PREFETCH_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_EXIT_DISCARD_ROLLOVER_S 19 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_EXIT_DISCARD_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_EXIT_DISCARD_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_EXIT_ISSUE_ROLLOVER_S 18 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_EXIT_ISSUE_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_EXIT_ISSUE_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_ENTRY_NWA_ROLLOVER_S 17 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_ENTRY_NWA_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_ENTRY_NWA_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_ENTRY_WA_ROLLOVER_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_ENTRY_WA_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_ENTRY_WA_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_RSVD1_S 8 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN7_ROLLOVER_S 7 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN7_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN7_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN6_ROLLOVER_S 6 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN6_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN6_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN5_ROLLOVER_S 5 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN5_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN5_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN4_ROLLOVER_S 4 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN4_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN4_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN3_ROLLOVER_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN3_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN3_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN2_ROLLOVER_S 2 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN2_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN2_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_RSVD0_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_RSVD0_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN0_ROLLOVER_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN0_ROLLOVER_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_STATUS_HISTO_BIN0_ROLLOVER_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_TMR 0x424C0190 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_TMR_STATSTMR_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_TMR_STATSTMR_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_TMR_STATSTMR_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL 0x424C0198 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_RSVD1_S 18 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_RSVD1_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_FINAL_WA_EDGE_S 17 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_FINAL_WA_EDGE_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_FINAL_WA_EDGE_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_EDGE_VALID_S 16 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_EDGE_VALID_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_EDGE_VALID_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_RSVD0_S 15 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_RSVD0_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_RSVD0_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_QSET_S 3 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_QSET_M RDMA_MASK3(32, 0xFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_QSET_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_SEL_S 1 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_SEL_M RDMA_MASK3(32, 0x3, IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_SEL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_LVL_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_LVL_M RDMA_BIT2(32, IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_CTL_WA_LVL_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_EDGECNT 0x424C01A0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_EDGECNT_WA_EDGECNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_EDGECNT_WA_EDGECNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_EDGECNT_WA_EDGECNT_S) +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_LVLCNT 0x424C019C +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_LVLCNT_WA_LVLCNT_S 0 +#define IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_LVLCNT_WA_LVLCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MEV_TSCD_GLPE_TSCD_STATS_WAMON_LVLCNT_WA_LVLCNT_S) +#define IG3_STATS_GLPES_CNPPROCESSEDHI 0x4266E8A4 +#define IG3_STATS_GLPES_CNPPROCESSEDHI_CNPPROCESSEDLO_S 0 +#define IG3_STATS_GLPES_CNPPROCESSEDHI_CNPPROCESSEDLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_CNPPROCESSEDHI_CNPPROCESSEDLO_S) +#define IG3_STATS_GLPES_CNPPROCESSEDLO 0x4266E8A0 +#define IG3_STATS_GLPES_CNPPROCESSEDLO_CNPPROCESSEDLO_S 0 +#define IG3_STATS_GLPES_CNPPROCESSEDLO_CNPPROCESSEDLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_CNPPROCESSEDLO_CNPPROCESSEDLO_S) +#define IG3_STATS_GLPES_DUPRREQRCVDHI 0x4266E8F4 +#define IG3_STATS_GLPES_DUPRREQRCVDHI_DUPRREQRCVDHI_S 0 +#define IG3_STATS_GLPES_DUPRREQRCVDHI_DUPRREQRCVDHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_DUPRREQRCVDHI_DUPRREQRCVDHI_S) +#define IG3_STATS_GLPES_DUPRREQRCVDLO 0x4266E8F0 +#define IG3_STATS_GLPES_DUPRREQRCVDLO_DUPRREQRCVDLO_S 0 +#define IG3_STATS_GLPES_DUPRREQRCVDLO_DUPRREQRCVDLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_DUPRREQRCVDLO_DUPRREQRCVDLO_S) +#define IG3_STATS_GLPES_HMCERRCNTHI 0x4266E8FC +#define IG3_STATS_GLPES_HMCERRCNTHI_HMCERRCNTHI_S 0 +#define IG3_STATS_GLPES_HMCERRCNTHI_HMCERRCNTHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_HMCERRCNTHI_HMCERRCNTHI_S) +#define IG3_STATS_GLPES_HMCERRCNTLO 0x4266E8F8 +#define IG3_STATS_GLPES_HMCERRCNTLO_HMCERRCNTLO_S 0 +#define IG3_STATS_GLPES_HMCERRCNTLO_HMCERRCNTLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_HMCERRCNTLO_HMCERRCNTLO_S) +#define IG3_STATS_GLPES_OOPCNTGP0HI 0x4266E884 +#define IG3_STATS_GLPES_OOPCNTGP0HI_OOPGP0_S 0 +#define IG3_STATS_GLPES_OOPCNTGP0HI_OOPGP0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_OOPCNTGP0HI_OOPGP0_S) +#define IG3_STATS_GLPES_OOPCNTGP0LO 0x4266E880 +#define IG3_STATS_GLPES_OOPCNTGP0LO_OOPGP0_S 0 +#define IG3_STATS_GLPES_OOPCNTGP0LO_OOPGP0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_OOPCNTGP0LO_OOPGP0_S) +#define IG3_STATS_GLPES_OOPCNTGP1HI 0x4266E88C +#define IG3_STATS_GLPES_OOPCNTGP1HI_OOPGP1_S 0 +#define IG3_STATS_GLPES_OOPCNTGP1HI_OOPGP1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_OOPCNTGP1HI_OOPGP1_S) +#define IG3_STATS_GLPES_OOPCNTGP1LO 0x4266E888 +#define IG3_STATS_GLPES_OOPCNTGP1LO_OOPGP1_S 0 +#define IG3_STATS_GLPES_OOPCNTGP1LO_OOPGP1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_OOPCNTGP1LO_OOPGP1_S) +#define IG3_STATS_GLPES_OOPCNTGP2HI 0x4266E894 +#define IG3_STATS_GLPES_OOPCNTGP2HI_OOPGP2_S 0 +#define IG3_STATS_GLPES_OOPCNTGP2HI_OOPGP2_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_OOPCNTGP2HI_OOPGP2_S) +#define IG3_STATS_GLPES_OOPCNTGP2LO 0x4266E890 +#define IG3_STATS_GLPES_OOPCNTGP2LO_OOPGP2_S 0 +#define IG3_STATS_GLPES_OOPCNTGP2LO_OOPGP2_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_OOPCNTGP2LO_OOPGP2_S) +#define IG3_STATS_GLPES_OOPCNTGP3HI 0x4266E89C +#define IG3_STATS_GLPES_OOPCNTGP3HI_OOPGP3_S 0 +#define IG3_STATS_GLPES_OOPCNTGP3HI_OOPGP3_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_OOPCNTGP3HI_OOPGP3_S) +#define IG3_STATS_GLPES_OOPCNTGP3LO 0x4266E898 +#define IG3_STATS_GLPES_OOPCNTGP3LO_OOPGP3_S 0 +#define IG3_STATS_GLPES_OOPCNTGP3LO_OOPGP3_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_OOPCNTGP3LO_OOPGP3_S) +#define IG3_STATS_GLPES_PERNRRCVDHI(_i) 0x42669300 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PERNRRCVDHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PERNRRCVDHI_PERNRRCVDHI_S 0 +#define IG3_STATS_GLPES_PERNRRCVDHI_PERNRRCVDHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PERNRRCVDHI_PERNRRCVDHI_S) +#define IG3_STATS_GLPES_PERNRRCVDLO(_i) 0x42668200 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PERNRRCVDLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PERNRRCVDLO_PERNRRCVDLO_S 0 +#define IG3_STATS_GLPES_PERNRRCVDLO_PERNRRCVDLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PERNRRCVDLO_PERNRRCVDLO_S) +#define IG3_STATS_GLPES_PERNRSENTHI(_i) 0x4263A700 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PERNRSENTHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PERNRSENTHI_PERNRSENTHI_S 0 +#define IG3_STATS_GLPES_PERNRSENTHI_PERNRSENTHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PERNRSENTHI_PERNRSENTHI_S) +#define IG3_STATS_GLPES_PERNRSENTLO(_i) 0x42639600 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PERNRSENTLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PERNRSENTLO_PERNRSENTLO_S 0 +#define IG3_STATS_GLPES_PERNRSENTLO_PERNRSENTLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PERNRSENTLO_PERNRSENTLO_S) +#define IG3_STATS_GLPES_PFIP4RXDISCARDHI(_i) 0x42614300 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXDISCARDHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXDISCARDHI_IP4RXDISCARD_S 0 +#define IG3_STATS_GLPES_PFIP4RXDISCARDHI_IP4RXDISCARD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXDISCARDHI_IP4RXDISCARD_S) +#define IG3_STATS_GLPES_PFIP4RXDISCARDLO(_i) 0x42613200 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXDISCARDLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXDISCARDLO_IP4RXDISCARD_S 0 +#define IG3_STATS_GLPES_PFIP4RXDISCARDLO_IP4RXDISCARD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXDISCARDLO_IP4RXDISCARD_S) +#define IG3_STATS_GLPES_PFIP4RXFRAGSHI(_i) 0x42616500 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXFRAGSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_S 0 +#define IG3_STATS_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXFRAGSHI_IP4RXFRAGSHI_S) +#define IG3_STATS_GLPES_PFIP4RXFRAGSLO(_i) 0x42615400 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXFRAGSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_S 0 +#define IG3_STATS_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXFRAGSLO_IP4RXFRAGSLO_S) +#define IG3_STATS_GLPES_PFIP4RXMCOCTSHI(_i) 0x42605500 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXMCOCTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_S 0 +#define IG3_STATS_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXMCOCTSHI_IP4RXMCOCTSHI_S) +#define IG3_STATS_GLPES_PFIP4RXMCOCTSLO(_i) 0x42604400 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXMCOCTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_S 0 +#define IG3_STATS_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXMCOCTSLO_IP4RXMCOCTSLO_S) +#define IG3_STATS_GLPES_PFIP4RXMCPKTSHI(_i) 0x42607700 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXMCPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_S 0 +#define IG3_STATS_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXMCPKTSHI_IP4RXMCPKTSHI_S) +#define IG3_STATS_GLPES_PFIP4RXMCPKTSLO(_i) 0x42606600 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXMCPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_S 0 +#define IG3_STATS_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXMCPKTSLO_IP4RXMCPKTSLO_S) +#define IG3_STATS_GLPES_PFIP4RXOCTSHI(_i) 0x42601100 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXOCTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_S 0 +#define IG3_STATS_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXOCTSHI_IP4RXOCTSHI_S) +#define IG3_STATS_GLPES_PFIP4RXOCTSLO(_i) 0x42600000 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXOCTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_S 0 +#define IG3_STATS_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXOCTSLO_IP4RXOCTSLO_S) +#define IG3_STATS_GLPES_PFIP4RXPKTSHI(_i) 0x42603300 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_S 0 +#define IG3_STATS_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXPKTSHI_IP4RXPKTSHI_S) +#define IG3_STATS_GLPES_PFIP4RXPKTSLO(_i) 0x42602200 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_S 0 +#define IG3_STATS_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXPKTSLO_IP4RXPKTSLO_S) +#define IG3_STATS_GLPES_PFIP4RXTRUNCHI(_i) 0x42618700 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXTRUNCHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXTRUNCHI_IP4RXTRUNC_S 0 +#define IG3_STATS_GLPES_PFIP4RXTRUNCHI_IP4RXTRUNC_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXTRUNCHI_IP4RXTRUNC_S) +#define IG3_STATS_GLPES_PFIP4RXTRUNCLO(_i) 0x42617600 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4RXTRUNCLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4RXTRUNCLO_IP4RXTRUNC_S 0 +#define IG3_STATS_GLPES_PFIP4RXTRUNCLO_IP4RXTRUNC_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4RXTRUNCLO_IP4RXTRUNC_S) +#define IG3_STATS_GLPES_PFIP4TXFRAGSHI(_i) 0x42653F00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXFRAGSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_S 0 +#define IG3_STATS_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXFRAGSHI_IP4TXFRAGSHI_S) +#define IG3_STATS_GLPES_PFIP4TXFRAGSLO(_i) 0x42652E00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXFRAGSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_S 0 +#define IG3_STATS_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXFRAGSLO_IP4TXFRAGSLO_S) +#define IG3_STATS_GLPES_PFIP4TXMCOCTSHI(_i) 0x42645100 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXMCOCTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_S 0 +#define IG3_STATS_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXMCOCTSHI_IP4TXMCOCTSHI_S) +#define IG3_STATS_GLPES_PFIP4TXMCOCTSLO(_i) 0x42644000 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXMCOCTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_S 0 +#define IG3_STATS_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXMCOCTSLO_IP4TXMCOCTSLO_S) +#define IG3_STATS_GLPES_PFIP4TXMCPKTSHI(_i) 0x42647300 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXMCPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_S 0 +#define IG3_STATS_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXMCPKTSHI_IP4TXMCPKTSHI_S) +#define IG3_STATS_GLPES_PFIP4TXMCPKTSLO(_i) 0x42646200 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXMCPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_S 0 +#define IG3_STATS_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXMCPKTSLO_IP4TXMCPKTSLO_S) +#define IG3_STATS_GLPES_PFIP4TXNOROUTEHI(_i) 0x42651D00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXNOROUTEHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXNOROUTEHI_IP4TXNOROUTE_S 0 +#define IG3_STATS_GLPES_PFIP4TXNOROUTEHI_IP4TXNOROUTE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXNOROUTEHI_IP4TXNOROUTE_S) +#define IG3_STATS_GLPES_PFIP4TXNOROUTELO(_i) 0x42650C00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXNOROUTELO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXNOROUTELO_IP4TXNOROUTE_S 0 +#define IG3_STATS_GLPES_PFIP4TXNOROUTELO_IP4TXNOROUTE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXNOROUTELO_IP4TXNOROUTE_S) +#define IG3_STATS_GLPES_PFIP4TXOCTSHI(_i) 0x42640D00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXOCTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_S 0 +#define IG3_STATS_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXOCTSHI_IP4TXOCTSHI_S) +#define IG3_STATS_GLPES_PFIP4TXOCTSLO(_i) 0x4263FC00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXOCTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_S 0 +#define IG3_STATS_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXOCTSLO_IP4TXOCTSLO_S) +#define IG3_STATS_GLPES_PFIP4TXPKTSHI(_i) 0x42642F00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_S 0 +#define IG3_STATS_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXPKTSHI_IP4TXPKTSHI_S) +#define IG3_STATS_GLPES_PFIP4TXPKTSLO(_i) 0x42641E00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP4TXPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_S 0 +#define IG3_STATS_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP4TXPKTSLO_IP4TXPKTSLO_S) +#define IG3_STATS_GLPES_PFIP6RXDISCARDHI(_i) 0x4261CB00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXDISCARDHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXDISCARDHI_IP6RXDISCARD_S 0 +#define IG3_STATS_GLPES_PFIP6RXDISCARDHI_IP6RXDISCARD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXDISCARDHI_IP6RXDISCARD_S) +#define IG3_STATS_GLPES_PFIP6RXDISCARDLO(_i) 0x4261BA00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXDISCARDLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXDISCARDLO_IP6RXDISCARD_S 0 +#define IG3_STATS_GLPES_PFIP6RXDISCARDLO_IP6RXDISCARD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXDISCARDLO_IP6RXDISCARD_S) +#define IG3_STATS_GLPES_PFIP6RXFRAGSHI(_i) 0x4261ED00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXFRAGSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_S 0 +#define IG3_STATS_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXFRAGSHI_IP6RXFRAGSHI_S) +#define IG3_STATS_GLPES_PFIP6RXFRAGSLO(_i) 0x4261DC00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXFRAGSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_S 0 +#define IG3_STATS_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXFRAGSLO_IP6RXFRAGSLO_S) +#define IG3_STATS_GLPES_PFIP6RXMCOCTSHI(_i) 0x4260DD00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXMCOCTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_S 0 +#define IG3_STATS_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXMCOCTSHI_IP6RXMCOCTSHI_S) +#define IG3_STATS_GLPES_PFIP6RXMCOCTSLO(_i) 0x4260CC00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXMCOCTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_S 0 +#define IG3_STATS_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXMCOCTSLO_IP6RXMCOCTSLO_S) +#define IG3_STATS_GLPES_PFIP6RXMCPKTSHI(_i) 0x4260FF00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXMCPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_S 0 +#define IG3_STATS_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXMCPKTSHI_IP6RXMCPKTSHI_S) +#define IG3_STATS_GLPES_PFIP6RXMCPKTSLO(_i) 0x4260EE00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXMCPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_S 0 +#define IG3_STATS_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXMCPKTSLO_IP6RXMCPKTSLO_S) +#define IG3_STATS_GLPES_PFIP6RXOCTSHI(_i) 0x42609900 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXOCTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_S 0 +#define IG3_STATS_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXOCTSHI_IP6RXOCTSHI_S) +#define IG3_STATS_GLPES_PFIP6RXOCTSLO(_i) 0x42608800 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXOCTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_S 0 +#define IG3_STATS_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXOCTSLO_IP6RXOCTSLO_S) +#define IG3_STATS_GLPES_PFIP6RXPKTSHI(_i) 0x4260BB00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_S 0 +#define IG3_STATS_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXPKTSHI_IP6RXPKTSHI_S) +#define IG3_STATS_GLPES_PFIP6RXPKTSLO(_i) 0x4260AA00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_S 0 +#define IG3_STATS_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXPKTSLO_IP6RXPKTSLO_S) +#define IG3_STATS_GLPES_PFIP6RXTRUNCHI(_i) 0x42623100 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXTRUNCHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXTRUNCHI_IP6RXTRUNC_S 0 +#define IG3_STATS_GLPES_PFIP6RXTRUNCHI_IP6RXTRUNC_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXTRUNCHI_IP6RXTRUNC_S) +#define IG3_STATS_GLPES_PFIP6RXTRUNCLO(_i) 0x42622000 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6RXTRUNCLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6RXTRUNCLO_IP6RXTRUNC_S 0 +#define IG3_STATS_GLPES_PFIP6RXTRUNCLO_IP6RXTRUNC_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6RXTRUNCLO_IP6RXTRUNC_S) +#define IG3_STATS_GLPES_PFIP6TXFRAGSHI(_i) 0x42658300 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXFRAGSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_S 0 +#define IG3_STATS_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXFRAGSHI_IP6TXFRAGSHI_S) +#define IG3_STATS_GLPES_PFIP6TXFRAGSLO(_i) 0x42657200 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXFRAGSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_S 0 +#define IG3_STATS_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXFRAGSLO_IP6TXFRAGSLO_S) +#define IG3_STATS_GLPES_PFIP6TXMCOCTSHI(_i) 0x4264D900 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXMCOCTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_S 0 +#define IG3_STATS_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXMCOCTSHI_IP6TXMCOCTSHI_S) +#define IG3_STATS_GLPES_PFIP6TXMCOCTSLO(_i) 0x4264C800 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXMCOCTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_S 0 +#define IG3_STATS_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXMCOCTSLO_IP6TXMCOCTSLO_S) +#define IG3_STATS_GLPES_PFIP6TXMCPKTSHI(_i) 0x4264FB00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXMCPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_S 0 +#define IG3_STATS_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXMCPKTSHI_IP6TXMCPKTSHI_S) +#define IG3_STATS_GLPES_PFIP6TXMCPKTSLO(_i) 0x4264EA00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXMCPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_S 0 +#define IG3_STATS_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXMCPKTSLO_IP6TXMCPKTSLO_S) +#define IG3_STATS_GLPES_PFIP6TXNOROUTEHI(_i) 0x42656100 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXNOROUTEHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXNOROUTEHI_IP6TXNOROUTE_S 0 +#define IG3_STATS_GLPES_PFIP6TXNOROUTEHI_IP6TXNOROUTE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXNOROUTEHI_IP6TXNOROUTE_S) +#define IG3_STATS_GLPES_PFIP6TXNOROUTELO(_i) 0x42655000 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXNOROUTELO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXNOROUTELO_IP6TXNOROUTE_S 0 +#define IG3_STATS_GLPES_PFIP6TXNOROUTELO_IP6TXNOROUTE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXNOROUTELO_IP6TXNOROUTE_S) +#define IG3_STATS_GLPES_PFIP6TXOCTSHI(_i) 0x42649500 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXOCTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_S 0 +#define IG3_STATS_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXOCTSHI_IP6TXOCTSHI_S) +#define IG3_STATS_GLPES_PFIP6TXOCTSLO(_i) 0x42648400 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXOCTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_S 0 +#define IG3_STATS_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXOCTSLO_IP6TXOCTSLO_S) +#define IG3_STATS_GLPES_PFIP6TXPKTSHI(_i) 0x4264B700 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_S 0 +#define IG3_STATS_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXPKTSHI_IP6TXPKTSHI_S) +#define IG3_STATS_GLPES_PFIP6TXPKTSLO(_i) 0x4264A600 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFIP6TXPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_S 0 +#define IG3_STATS_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFIP6TXPKTSLO_IP6TXPKTSLO_S) +#define IG3_STATS_GLPES_PFRDMARXATSHI(_i) 0x4262B900 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMARXATSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMARXATSHI_RDMARXATSHI_S 0 +#define IG3_STATS_GLPES_PFRDMARXATSHI_RDMARXATSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMARXATSHI_RDMARXATSHI_S) +#define IG3_STATS_GLPES_PFRDMARXATSLO(_i) 0x4262A800 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMARXATSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMARXATSLO_RDMARXATSLO_S 0 +#define IG3_STATS_GLPES_PFRDMARXATSLO_RDMARXATSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMARXATSLO_RDMARXATSLO_S) +#define IG3_STATS_GLPES_PFRDMARXRDSHI(_i) 0x4262FD00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMARXRDSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_S 0 +#define IG3_STATS_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMARXRDSHI_RDMARXRDSHI_S) +#define IG3_STATS_GLPES_PFRDMARXRDSLO(_i) 0x4262EC00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMARXRDSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_S 0 +#define IG3_STATS_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMARXRDSLO_RDMARXRDSLO_S) +#define IG3_STATS_GLPES_PFRDMARXSNDSHI(_i) 0x42631F00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMARXSNDSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_S 0 +#define IG3_STATS_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMARXSNDSHI_RDMARXSNDSHI_S) +#define IG3_STATS_GLPES_PFRDMARXSNDSLO(_i) 0x42630E00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMARXSNDSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_S 0 +#define IG3_STATS_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMARXSNDSLO_RDMARXSNDSLO_S) +#define IG3_STATS_GLPES_PFRDMARXWRSHI(_i) 0x4262DB00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMARXWRSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_S 0 +#define IG3_STATS_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMARXWRSHI_RDMARXWRSHI_S) +#define IG3_STATS_GLPES_PFRDMARXWRSLO(_i) 0x4262CA00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMARXWRSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_S 0 +#define IG3_STATS_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMARXWRSLO_RDMARXWRSLO_S) +#define IG3_STATS_GLPES_PFRDMATXATSHI(_i) 0x4265E900 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMATXATSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMATXATSHI_RDMARXATSHI_S 0 +#define IG3_STATS_GLPES_PFRDMATXATSHI_RDMARXATSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMATXATSHI_RDMARXATSHI_S) +#define IG3_STATS_GLPES_PFRDMATXATSLO(_i) 0x4265D800 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMATXATSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMATXATSLO_RDMARXATSLO_S 0 +#define IG3_STATS_GLPES_PFRDMATXATSLO_RDMARXATSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMATXATSLO_RDMARXATSLO_S) +#define IG3_STATS_GLPES_PFRDMATXRDSHI(_i) 0x42662D00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMATXRDSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_S 0 +#define IG3_STATS_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMATXRDSHI_RDMARXRDSHI_S) +#define IG3_STATS_GLPES_PFRDMATXRDSLO(_i) 0x42661C00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMATXRDSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_S 0 +#define IG3_STATS_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMATXRDSLO_RDMARXRDSLO_S) +#define IG3_STATS_GLPES_PFRDMATXSNDSHI(_i) 0x42664F00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMATXSNDSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_S 0 +#define IG3_STATS_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMATXSNDSHI_RDMARXSNDSHI_S) +#define IG3_STATS_GLPES_PFRDMATXSNDSLO(_i) 0x42663E00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMATXSNDSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_S 0 +#define IG3_STATS_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMATXSNDSLO_RDMARXSNDSLO_S) +#define IG3_STATS_GLPES_PFRDMATXWRSHI(_i) 0x42660B00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMATXWRSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_S 0 +#define IG3_STATS_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMATXWRSHI_RDMARXWRSHI_S) +#define IG3_STATS_GLPES_PFRDMATXWRSLO(_i) 0x4265FA00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMATXWRSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_S 0 +#define IG3_STATS_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMATXWRSLO_RDMARXWRSLO_S) +#define IG3_STATS_GLPES_PFRDMAVBNDHI(_i) 0x42634100 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMAVBNDHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_S 0 +#define IG3_STATS_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMAVBNDHI_RDMAVBNDHI_S) +#define IG3_STATS_GLPES_PFRDMAVBNDLO(_i) 0x42633000 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMAVBNDLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_S 0 +#define IG3_STATS_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMAVBNDLO_RDMAVBNDLO_S) +#define IG3_STATS_GLPES_PFRDMAVINVHI(_i) 0x42636300 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMAVINVHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMAVINVHI_RDMAVINVHI_S 0 +#define IG3_STATS_GLPES_PFRDMAVINVHI_RDMAVINVHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMAVINVHI_RDMAVINVHI_S) +#define IG3_STATS_GLPES_PFRDMAVINVLO(_i) 0x42635200 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRDMAVINVLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRDMAVINVLO_RDMAVINVLO_S 0 +#define IG3_STATS_GLPES_PFRDMAVINVLO_RDMAVINVLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRDMAVINVLO_RDMAVINVLO_S) +#define IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSHI(_i) 0x42638500 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSHI_FRXNPECNMARKEDPKTSHI_S 0 +#define IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSHI_FRXNPECNMARKEDPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSHI_FRXNPECNMARKEDPKTSHI_S) +#define IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSLO(_i) 0x42637400 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_S 0 +#define IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRXNPECNMARKEDPKTSLO_RXNPECNMARKEDPKTSLO_S) +#define IG3_STATS_GLPES_PFRXRPCNPHANDLEDHI(_i) 0x42629700 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRXRPCNPHANDLEDHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRXRPCNPHANDLEDHI_RXRPCNPHANDLED_S 0 +#define IG3_STATS_GLPES_PFRXRPCNPHANDLEDHI_RXRPCNPHANDLED_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRXRPCNPHANDLEDHI_RXRPCNPHANDLED_S) +#define IG3_STATS_GLPES_PFRXRPCNPHANDLEDLO(_i) 0x42628600 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRXRPCNPHANDLEDLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRXRPCNPHANDLEDLO_RXRPCNPHANDLED_S 0 +#define IG3_STATS_GLPES_PFRXRPCNPHANDLEDLO_RXRPCNPHANDLED_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRXRPCNPHANDLEDLO_RXRPCNPHANDLED_S) +#define IG3_STATS_GLPES_PFRXRPCNPIGNOREDHI(_i) 0x4261A900 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRXRPCNPIGNOREDHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRXRPCNPIGNOREDHI_RPCNPIGNORED_S 0 +#define IG3_STATS_GLPES_PFRXRPCNPIGNOREDHI_RPCNPIGNORED_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRXRPCNPIGNOREDHI_RPCNPIGNORED_S) +#define IG3_STATS_GLPES_PFRXRPCNPIGNOREDLO(_i) 0x42619800 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRXRPCNPIGNOREDLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRXRPCNPIGNOREDLO_RPCNPIGNORED_S 0 +#define IG3_STATS_GLPES_PFRXRPCNPIGNOREDLO_RPCNPIGNORED_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRXRPCNPIGNOREDLO_RPCNPIGNORED_S) +#define IG3_STATS_GLPES_PFRXVLANERRHI(_i) 0x42612100 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRXVLANERRHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRXVLANERRHI_RXVLANERR_S 0 +#define IG3_STATS_GLPES_PFRXVLANERRHI_RXVLANERR_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRXVLANERRHI_RXVLANERR_S) +#define IG3_STATS_GLPES_PFRXVLANERRLO(_i) 0x42611000 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFRXVLANERRLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFRXVLANERRLO_RXVLANERR_S 0 +#define IG3_STATS_GLPES_PFRXVLANERRLO_RXVLANERR_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFRXVLANERRLO_RXVLANERR_S) +#define IG3_STATS_GLPES_PFTCPRTXSEGHI(_i) 0x4265C700 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPRTXSEGHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPRTXSEGHI_TCPRTXSEG_S 0 +#define IG3_STATS_GLPES_PFTCPRTXSEGHI_TCPRTXSEG_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPRTXSEGHI_TCPRTXSEG_S) +#define IG3_STATS_GLPES_PFTCPRTXSEGLO(_i) 0x4265B600 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPRTXSEGLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPRTXSEGLO_TCPRTXSEG_S 0 +#define IG3_STATS_GLPES_PFTCPRTXSEGLO_TCPRTXSEG_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPRTXSEGLO_TCPRTXSEG_S) +#define IG3_STATS_GLPES_PFTCPRXOPTERRHI(_i) 0x42627500 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPRXOPTERRHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPRXOPTERRHI_TCPRXOPTERR_S 0 +#define IG3_STATS_GLPES_PFTCPRXOPTERRHI_TCPRXOPTERR_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPRXOPTERRHI_TCPRXOPTERR_S) +#define IG3_STATS_GLPES_PFTCPRXOPTERRLO(_i) 0x42626400 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPRXOPTERRLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPRXOPTERRLO_TCPRXOPTERR_S 0 +#define IG3_STATS_GLPES_PFTCPRXOPTERRLO_TCPRXOPTERR_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPRXOPTERRLO_TCPRXOPTERR_S) +#define IG3_STATS_GLPES_PFTCPRXPROTOERRHI(_i) 0x42620F00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPRXPROTOERRHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPRXPROTOERRHI_TCPRXPROTOERR_S 0 +#define IG3_STATS_GLPES_PFTCPRXPROTOERRHI_TCPRXPROTOERR_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPRXPROTOERRHI_TCPRXPROTOERR_S) +#define IG3_STATS_GLPES_PFTCPRXPROTOERRLO(_i) 0x4261FE00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPRXPROTOERRLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPRXPROTOERRLO_TCPRXPROTOERR_S 0 +#define IG3_STATS_GLPES_PFTCPRXPROTOERRLO_TCPRXPROTOERR_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPRXPROTOERRLO_TCPRXPROTOERR_S) +#define IG3_STATS_GLPES_PFTCPRXSEGSHI(_i) 0x4263C900 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPRXSEGSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_S 0 +#define IG3_STATS_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPRXSEGSHI_TCPRXSEGSHI_S) +#define IG3_STATS_GLPES_PFTCPRXSEGSLO(_i) 0x4263B800 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPRXSEGSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_S 0 +#define IG3_STATS_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPRXSEGSLO_TCPRXSEGSLO_S) +#define IG3_STATS_GLPES_PFTCPTXSEGSHI(_i) 0x4266B500 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPTXSEGSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPTXSEGSHI_TCPTXSEGHI_S 0 +#define IG3_STATS_GLPES_PFTCPTXSEGSHI_TCPTXSEGHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPTXSEGSHI_TCPTXSEGHI_S) +#define IG3_STATS_GLPES_PFTCPTXSEGSLO(_i) 0x4266A400 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTCPTXSEGSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTCPTXSEGSLO_TCPTXSEGLO_S 0 +#define IG3_STATS_GLPES_PFTCPTXSEGSLO_TCPTXSEGLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTCPTXSEGSLO_TCPTXSEGLO_S) +#define IG3_STATS_GLPES_PFTXNPCNPSENTHI(_i) 0x42667100 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTXNPCNPSENTHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTXNPCNPSENTHI_PFTXNPCNPSENT_S 0 +#define IG3_STATS_GLPES_PFTXNPCNPSENTHI_PFTXNPCNPSENT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTXNPCNPSENTHI_PFTXNPCNPSENT_S) +#define IG3_STATS_GLPES_PFTXNPCNPSENTLO(_i) 0x42666000 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFTXNPCNPSENTLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFTXNPCNPSENTLO_PFTXNPCNPSENT_S 0 +#define IG3_STATS_GLPES_PFTXNPCNPSENTLO_PFTXNPCNPSENT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFTXNPCNPSENTLO_PFTXNPCNPSENT_S) +#define IG3_STATS_GLPES_PFUDPRXPKTSHI(_i) 0x4263EB00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFUDPRXPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_S 0 +#define IG3_STATS_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFUDPRXPKTSHI_UDPRXPKTSHI_S) +#define IG3_STATS_GLPES_PFUDPRXPKTSLO(_i) 0x4263DA00 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFUDPRXPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_S 0 +#define IG3_STATS_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFUDPRXPKTSLO_UDPRXPKTSLO_S) +#define IG3_STATS_GLPES_PFUDPTXPKTSHI(_i) 0x4266D700 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFUDPTXPKTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_S 0 +#define IG3_STATS_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFUDPTXPKTSHI_UDPTXPKTSHI_S) +#define IG3_STATS_GLPES_PFUDPTXPKTSLO(_i) 0x4266C600 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_PFUDPTXPKTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_S 0 +#define IG3_STATS_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PFUDPTXPKTSLO_UDPTXPKTSLO_S) +#define IG3_STATS_GLPES_PSHGCTRKTBLCNTHI 0x4266EEAC +#define IG3_STATS_GLPES_PSHGCTRKTBLCNTHI_PSHGCTRKTBLCNT_S 0 +#define IG3_STATS_GLPES_PSHGCTRKTBLCNTHI_PSHGCTRKTBLCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHGCTRKTBLCNTHI_PSHGCTRKTBLCNT_S) +#define IG3_STATS_GLPES_PSHGCTRKTBLCNTLO 0x4266EEA8 +#define IG3_STATS_GLPES_PSHGCTRKTBLCNTLO_PSHGCTRKTBLCNT_S 0 +#define IG3_STATS_GLPES_PSHGCTRKTBLCNTLO_PSHGCTRKTBLCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHGCTRKTBLCNTLO_PSHGCTRKTBLCNT_S) +#define IG3_STATS_GLPES_PSHINCWQECNTHI 0x4266EE94 +#define IG3_STATS_GLPES_PSHINCWQECNTHI_PSHINCWQECNT_S 0 +#define IG3_STATS_GLPES_PSHINCWQECNTHI_PSHINCWQECNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHINCWQECNTHI_PSHINCWQECNT_S) +#define IG3_STATS_GLPES_PSHINCWQECNTLO 0x4266EE90 +#define IG3_STATS_GLPES_PSHINCWQECNTLO_PSHINCWQECNT_S 0 +#define IG3_STATS_GLPES_PSHINCWQECNTLO_PSHINCWQECNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHINCWQECNTLO_PSHINCWQECNT_S) +#define IG3_STATS_GLPES_PSHINVACCESSCNTHI 0x4266EE9C +#define IG3_STATS_GLPES_PSHINVACCESSCNTHI_PSHINVACCESSCNT_S 0 +#define IG3_STATS_GLPES_PSHINVACCESSCNTHI_PSHINVACCESSCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHINVACCESSCNTHI_PSHINVACCESSCNT_S) +#define IG3_STATS_GLPES_PSHINVACCESSCNTLO 0x4266EE98 +#define IG3_STATS_GLPES_PSHINVACCESSCNTLO_PSHINVACCESSCNT_S 0 +#define IG3_STATS_GLPES_PSHINVACCESSCNTLO_PSHINVACCESSCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHINVACCESSCNTLO_PSHINVACCESSCNT_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0(_i) 0x4266EEC8 + ((_i) * 4) /* _i=0...7 */ +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_MAX_INDEX_I 7 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_VALID_S 31 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_VALID_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T0_VALID_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_RSVD_S 30 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_RSVD_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T0_RSVD_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_PAGE_OFST_S 24 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_PAGE_OFST_M RDMA_MASK3(32, 0x3F, IG3_STATS_GLPES_PSHINVACCESSTRC_T0_PAGE_OFST_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_PAGE_IDX_S 14 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_PAGE_IDX_M RDMA_MASK3(32, 0x3FF, IG3_STATS_GLPES_PSHINVACCESSTRC_T0_PAGE_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_VF_IDX_S 2 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_VF_IDX_M RDMA_MASK3(32, 0xFFF, IG3_STATS_GLPES_PSHINVACCESSTRC_T0_VF_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_VM_VF_TYPE_S 0 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T0_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPES_PSHINVACCESSTRC_T0_VM_VF_TYPE_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1(_i) 0x4266EEE8 + ((_i) * 4) /* _i=0...7 */ +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_MAX_INDEX_I 7 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_VALID_S 31 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_VALID_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T1_VALID_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_RSVD_S 30 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_RSVD_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T1_RSVD_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_PAGE_OFST_S 24 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_PAGE_OFST_M RDMA_MASK3(32, 0x3F, IG3_STATS_GLPES_PSHINVACCESSTRC_T1_PAGE_OFST_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_PAGE_IDX_S 14 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_PAGE_IDX_M RDMA_MASK3(32, 0x3FF, IG3_STATS_GLPES_PSHINVACCESSTRC_T1_PAGE_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_VF_IDX_S 2 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_VF_IDX_M RDMA_MASK3(32, 0xFFF, IG3_STATS_GLPES_PSHINVACCESSTRC_T1_VF_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_VM_VF_TYPE_S 0 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPES_PSHINVACCESSTRC_T1_VM_VF_TYPE_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2(_i) 0x4266EF08 + ((_i) * 4) /* _i=0...7 */ +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_MAX_INDEX_I 7 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_VALID_S 31 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_VALID_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T2_VALID_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_RSVD_S 30 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_RSVD_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T2_RSVD_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_PAGE_OFST_S 24 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_PAGE_OFST_M RDMA_MASK3(32, 0x3F, IG3_STATS_GLPES_PSHINVACCESSTRC_T2_PAGE_OFST_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_PAGE_IDX_S 14 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_PAGE_IDX_M RDMA_MASK3(32, 0x3FF, IG3_STATS_GLPES_PSHINVACCESSTRC_T2_PAGE_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_VF_IDX_S 2 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_VF_IDX_M RDMA_MASK3(32, 0xFFF, IG3_STATS_GLPES_PSHINVACCESSTRC_T2_VF_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_VM_VF_TYPE_S 0 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T2_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPES_PSHINVACCESSTRC_T2_VM_VF_TYPE_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3(_i) 0x4266EF28 + ((_i) * 4) /* _i=0...7 */ +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_MAX_INDEX_I 7 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_VALID_S 31 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_VALID_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T3_VALID_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_RSVD_S 30 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_RSVD_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T3_RSVD_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_PAGE_OFST_S 24 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_PAGE_OFST_M RDMA_MASK3(32, 0x3F, IG3_STATS_GLPES_PSHINVACCESSTRC_T3_PAGE_OFST_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_PAGE_IDX_S 14 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_PAGE_IDX_M RDMA_MASK3(32, 0x3FF, IG3_STATS_GLPES_PSHINVACCESSTRC_T3_PAGE_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_VF_IDX_S 2 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_VF_IDX_M RDMA_MASK3(32, 0xFFF, IG3_STATS_GLPES_PSHINVACCESSTRC_T3_VF_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_VM_VF_TYPE_S 0 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T3_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPES_PSHINVACCESSTRC_T3_VM_VF_TYPE_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4(_i) 0x4266EF48 + ((_i) * 4) /* _i=0...7 */ +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_MAX_INDEX_I 7 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_VALID_S 31 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_VALID_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T4_VALID_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_RSVD_S 30 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_RSVD_M RDMA_BIT2(32, IG3_STATS_GLPES_PSHINVACCESSTRC_T4_RSVD_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_PAGE_OFST_S 24 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_PAGE_OFST_M RDMA_MASK3(32, 0x3F, IG3_STATS_GLPES_PSHINVACCESSTRC_T4_PAGE_OFST_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_PAGE_IDX_S 14 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_PAGE_IDX_M RDMA_MASK3(32, 0x3FF, IG3_STATS_GLPES_PSHINVACCESSTRC_T4_PAGE_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_VF_IDX_S 2 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_VF_IDX_M RDMA_MASK3(32, 0xFFF, IG3_STATS_GLPES_PSHINVACCESSTRC_T4_VF_IDX_S) +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_VM_VF_TYPE_S 0 +#define IG3_STATS_GLPES_PSHINVACCESSTRC_T4_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPES_PSHINVACCESSTRC_T4_VM_VF_TYPE_S) +#define IG3_STATS_GLPES_PSHINVSQHDCNTHI 0x4266EEB4 +#define IG3_STATS_GLPES_PSHINVSQHDCNTHI_PSHINVSQHDCNT_S 0 +#define IG3_STATS_GLPES_PSHINVSQHDCNTHI_PSHINVSQHDCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHINVSQHDCNTHI_PSHINVSQHDCNT_S) +#define IG3_STATS_GLPES_PSHINVSQHDCNTLO 0x4266EEB0 +#define IG3_STATS_GLPES_PSHINVSQHDCNTLO_PSHINVSQHDCNT_S 0 +#define IG3_STATS_GLPES_PSHINVSQHDCNTLO_PSHINVSQHDCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHINVSQHDCNTLO_PSHINVSQHDCNT_S) +#define IG3_STATS_GLPES_PSHNOCREDCNTHI 0x4266EE84 +#define IG3_STATS_GLPES_PSHNOCREDCNTHI_PSHNOCREDCNT_S 0 +#define IG3_STATS_GLPES_PSHNOCREDCNTHI_PSHNOCREDCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHNOCREDCNTHI_PSHNOCREDCNT_S) +#define IG3_STATS_GLPES_PSHNOCREDCNTLO 0x4266EE80 +#define IG3_STATS_GLPES_PSHNOCREDCNTLO_PSHNOCREDCNT_S 0 +#define IG3_STATS_GLPES_PSHNOCREDCNTLO_PSHNOCREDCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHNOCREDCNTLO_PSHNOCREDCNT_S) +#define IG3_STATS_GLPES_PSHNOTRKTBLDBCNTHI 0x4266EE8C +#define IG3_STATS_GLPES_PSHNOTRKTBLDBCNTHI_PSHNOTRKTBLDBCNT_S 0 +#define IG3_STATS_GLPES_PSHNOTRKTBLDBCNTHI_PSHNOTRKTBLDBCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHNOTRKTBLDBCNTHI_PSHNOTRKTBLDBCNT_S) +#define IG3_STATS_GLPES_PSHNOTRKTBLDBCNTLO 0x4266EE88 +#define IG3_STATS_GLPES_PSHNOTRKTBLDBCNTLO_PSHNOTRKTBLDBCNT_S 0 +#define IG3_STATS_GLPES_PSHNOTRKTBLDBCNTLO_PSHNOTRKTBLDBCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHNOTRKTBLDBCNTLO_PSHNOTRKTBLDBCNT_S) +#define IG3_STATS_GLPES_PSHNOTRKTBLTRNCNTHI 0x4266EEC4 +#define IG3_STATS_GLPES_PSHNOTRKTBLTRNCNTHI_PSHNOTRKTBLCNT_S 0 +#define IG3_STATS_GLPES_PSHNOTRKTBLTRNCNTHI_PSHNOTRKTBLCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHNOTRKTBLTRNCNTHI_PSHNOTRKTBLCNT_S) +#define IG3_STATS_GLPES_PSHNOTRKTBLTRNCNTLO 0x4266EEC0 +#define IG3_STATS_GLPES_PSHNOTRKTBLTRNCNTLO_PSHNOTRKTBLCNT_S 0 +#define IG3_STATS_GLPES_PSHNOTRKTBLTRNCNTLO_PSHNOTRKTBLCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHNOTRKTBLTRNCNTLO_PSHNOTRKTBLCNT_S) +#define IG3_STATS_GLPES_PSHPFCDROPCNTHI 0x4266EEBC +#define IG3_STATS_GLPES_PSHPFCDROPCNTHI_PSHPFCDROPCNT_S 0 +#define IG3_STATS_GLPES_PSHPFCDROPCNTHI_PSHPFCDROPCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHPFCDROPCNTHI_PSHPFCDROPCNT_S) +#define IG3_STATS_GLPES_PSHPFCDROPCNTLO 0x4266EEB8 +#define IG3_STATS_GLPES_PSHPFCDROPCNTLO_PSHPFCDROPCNT_S 0 +#define IG3_STATS_GLPES_PSHPFCDROPCNTLO_PSHPFCDROPCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHPFCDROPCNTLO_PSHPFCDROPCNT_S) +#define IG3_STATS_GLPES_PSHSQXMITCNTHI 0x4266EEA4 +#define IG3_STATS_GLPES_PSHSQXMITCNTHI_PSHSQXMITCNT_S 0 +#define IG3_STATS_GLPES_PSHSQXMITCNTHI_PSHSQXMITCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHSQXMITCNTHI_PSHSQXMITCNT_S) +#define IG3_STATS_GLPES_PSHSQXMITCNTLO 0x4266EEA0 +#define IG3_STATS_GLPES_PSHSQXMITCNTLO_PSHSQXMITCNT_S 0 +#define IG3_STATS_GLPES_PSHSQXMITCNTLO_PSHSQXMITCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_PSHSQXMITCNTLO_PSHSQXMITCNT_S) +#define IG3_STATS_GLPES_RDMAIRDLMTCNTSHI(_i) 0x42625300 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_RDMAIRDLMTCNTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_RDMAIRDLMTCNTSHI_RDMAIRDLMTCNTLCNTSHI_S 0 +#define IG3_STATS_GLPES_RDMAIRDLMTCNTSHI_RDMAIRDLMTCNTLCNTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMAIRDLMTCNTSHI_RDMAIRDLMTCNTLCNTSHI_S) +#define IG3_STATS_GLPES_RDMAIRDLMTCNTSLO(_i) 0x42624200 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_RDMAIRDLMTCNTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_RDMAIRDLMTCNTSLO_RDMAIRDLMTCNTLCNTSLO_S 0 +#define IG3_STATS_GLPES_RDMAIRDLMTCNTSLO_RDMAIRDLMTCNTLCNTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMAIRDLMTCNTSLO_RDMAIRDLMTCNTLCNTSLO_S) +#define IG3_STATS_GLPES_RDMAORDLMTCNTSHI(_i) 0x4265A500 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_RDMAORDLMTCNTSHI_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_RDMAORDLMTCNTSHI_RDMAORDLMTCNTLCNTSHI_S 0 +#define IG3_STATS_GLPES_RDMAORDLMTCNTSHI_RDMAORDLMTCNTLCNTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMAORDLMTCNTSHI_RDMAORDLMTCNTLCNTSHI_S) +#define IG3_STATS_GLPES_RDMAORDLMTCNTSLO(_i) 0x42659400 + ((_i) * 4) /* _i=0...1087 */ +#define IG3_STATS_GLPES_RDMAORDLMTCNTSLO_MAX_INDEX_I 1087 +#define IG3_STATS_GLPES_RDMAORDLMTCNTSLO_RDMAORDLMTCNTLCNTSLO_S 0 +#define IG3_STATS_GLPES_RDMAORDLMTCNTSLO_RDMAORDLMTCNTLCNTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMAORDLMTCNTSLO_RDMAORDLMTCNTLCNTSLO_S) +#define IG3_STATS_GLPES_RDMARXMULTFPDUSHI 0x4266E81C +#define IG3_STATS_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_S 0 +#define IG3_STATS_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMARXMULTFPDUSHI_RDMARXMULTFPDUSHI_S) +#define IG3_STATS_GLPES_RDMARXMULTFPDUSLO 0x4266E818 +#define IG3_STATS_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_S 0 +#define IG3_STATS_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMARXMULTFPDUSLO_RDMARXMULTFPDUSLO_S) +#define IG3_STATS_GLPES_RDMARXOOODDPHI 0x4266E824 +#define IG3_STATS_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_S 0 +#define IG3_STATS_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMARXOOODDPHI_RDMARXOOODDPHI_S) +#define IG3_STATS_GLPES_RDMARXOOODDPLO 0x4266E820 +#define IG3_STATS_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_S 0 +#define IG3_STATS_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMARXOOODDPLO_RDMARXOOODDPLO_S) +#define IG3_STATS_GLPES_RDMARXOOONOMARKHI 0x4266E814 +#define IG3_STATS_GLPES_RDMARXOOONOMARKHI_RDMAOOONOMARK_S 0 +#define IG3_STATS_GLPES_RDMARXOOONOMARKHI_RDMAOOONOMARK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMARXOOONOMARKHI_RDMAOOONOMARK_S) +#define IG3_STATS_GLPES_RDMARXOOONOMARKLO 0x4266E810 +#define IG3_STATS_GLPES_RDMARXOOONOMARKLO_RDMAOOONOMARK_S 0 +#define IG3_STATS_GLPES_RDMARXOOONOMARKLO_RDMAOOONOMARK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMARXOOONOMARKLO_RDMAOOONOMARK_S) +#define IG3_STATS_GLPES_RDMARXUNALIGNHI 0x4266E804 +#define IG3_STATS_GLPES_RDMARXUNALIGNHI_RDMRXAUNALIGN_S 0 +#define IG3_STATS_GLPES_RDMARXUNALIGNHI_RDMRXAUNALIGN_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMARXUNALIGNHI_RDMRXAUNALIGN_S) +#define IG3_STATS_GLPES_RDMARXUNALIGNLO 0x4266E800 +#define IG3_STATS_GLPES_RDMARXUNALIGNLO_RDMRXAUNALIGN_S 0 +#define IG3_STATS_GLPES_RDMARXUNALIGNLO_RDMRXAUNALIGN_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RDMARXUNALIGNLO_RDMRXAUNALIGN_S) +#define IG3_STATS_GLPES_RNRNAKREQHI 0x4266E8EC +#define IG3_STATS_GLPES_RNRNAKREQHI_RNRNAKREQHI_S 0 +#define IG3_STATS_GLPES_RNRNAKREQHI_RNRNAKREQHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RNRNAKREQHI_RNRNAKREQHI_S) +#define IG3_STATS_GLPES_RNRNAKREQLO 0x4266E8E8 +#define IG3_STATS_GLPES_RNRNAKREQLO_RNRNAKREQLO_S 0 +#define IG3_STATS_GLPES_RNRNAKREQLO_RNRNAKREQLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RNRNAKREQLO_RNRNAKREQLO_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID11HI 0x4266E80C +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID11HI_RXRAM2RSVDCNTRID11HI_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID11HI_RXRAM2RSVDCNTRID11HI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID11HI_RXRAM2RSVDCNTRID11HI_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID11LO 0x4266E808 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID11LO_RXRAM2RSVDCNTRID11LO_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID11LO_RXRAM2RSVDCNTRID11LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID11LO_RXRAM2RSVDCNTRID11LO_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1AHI 0x4266E854 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1AHI_RXRAM2RSVDCNTRID1AHI_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1AHI_RXRAM2RSVDCNTRID1AHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID1AHI_RXRAM2RSVDCNTRID1AHI_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1ALO 0x4266E850 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1ALO_RXRAM2RSVDCNTRID1ALO_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1ALO_RXRAM2RSVDCNTRID1ALO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID1ALO_RXRAM2RSVDCNTRID1ALO_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1BHI 0x4266E85C +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1BHI_RXRAM2RSVDCNTRID1BHI_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1BHI_RXRAM2RSVDCNTRID1BHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID1BHI_RXRAM2RSVDCNTRID1BHI_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1BLO 0x4266E858 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1BLO_RXRAM2RSVDCNTRID1BLO_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1BLO_RXRAM2RSVDCNTRID1BLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID1BLO_RXRAM2RSVDCNTRID1BLO_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1CHI 0x4266E864 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1CHI_RXRAM2RSVDCNTRID1CHI_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1CHI_RXRAM2RSVDCNTRID1CHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID1CHI_RXRAM2RSVDCNTRID1CHI_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1CLO 0x4266E860 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1CLO_RXRAM2RSVDCNTRID1CLO_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1CLO_RXRAM2RSVDCNTRID1CLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID1CLO_RXRAM2RSVDCNTRID1CLO_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1DHI 0x4266E86C +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1DHI_RXRAM2RSVDCNTRID1DHI_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1DHI_RXRAM2RSVDCNTRID1DHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID1DHI_RXRAM2RSVDCNTRID1DHI_S) +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1DLO 0x4266E868 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1DLO_RXRAM2RSVDCNTRID1DLO_S 0 +#define IG3_STATS_GLPES_RXRAM2RSVDCNTRID1DLO_RXRAM2RSVDCNTRID1DLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RXRAM2RSVDCNTRID1DLO_RXRAM2RSVDCNTRID1DLO_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_MAX_VAL(_i) 0x4266EE40 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_MAX_VAL_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_MAX_VAL_THRESHOLD_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_MAX_VAL_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_MAX_VAL_THRESHOLD_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H0(_i) 0x4266E940 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H0_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H0_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H0_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H0_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H1(_i) 0x4266E980 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H1_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H1_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H1_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H1_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H2(_i) 0x4266E9C0 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H2_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H2_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H2_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H2_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H3(_i) 0x4266EA00 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H3_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H3_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H3_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H3_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H4(_i) 0x4266EA40 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H4_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H4_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P0_H4_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H0(_i) 0x4266EA80 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H0_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H0_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H0_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H0_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H1(_i) 0x4266EAC0 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H1_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H1_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H1_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H1_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H2(_i) 0x4266EB00 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H2_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H2_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H2_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H2_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H3(_i) 0x4266EB40 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H3_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H3_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H3_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H3_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H4(_i) 0x4266EB80 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H4_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H4_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P1_H4_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H0(_i) 0x4266EBC0 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H0_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H0_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H0_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H0_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H1(_i) 0x4266EC00 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H1_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H1_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H1_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H1_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H2(_i) 0x4266EC40 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H2_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H2_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H2_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H2_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H3(_i) 0x4266EC80 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H3_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H3_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H3_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H3_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H4(_i) 0x4266ECC0 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H4_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H4_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P2_H4_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H0(_i) 0x4266ED00 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H0_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H0_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H0_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H0_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H1(_i) 0x4266ED40 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H1_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H1_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H1_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H1_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H2(_i) 0x4266ED80 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H2_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H2_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H2_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H2_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H3(_i) 0x4266EDC0 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H3_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H3_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H3_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H3_COUNT_S) +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H4(_i) 0x4266EE00 + ((_i) * 4) /* _i=0...15 */ +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H4_MAX_INDEX_I 15 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H4_COUNT_S 0 +#define IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_RX_LATENCY_HIS_P3_H4_COUNT_S) +#define IG3_STATS_GLPES_TCPRXFOURHOLEHI 0x4266E84C +#define IG3_STATS_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S 0 +#define IG3_STATS_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXFOURHOLEHI_TCPRXFOURHOLEHI_S) +#define IG3_STATS_GLPES_TCPRXFOURHOLELO 0x4266E848 +#define IG3_STATS_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S 0 +#define IG3_STATS_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXFOURHOLELO_TCPRXFOURHOLELO_S) +#define IG3_STATS_GLPES_TCPRXONEHOLEHI 0x4266E834 +#define IG3_STATS_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S 0 +#define IG3_STATS_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXONEHOLEHI_TCPRXONEHOLEHI_S) +#define IG3_STATS_GLPES_TCPRXONEHOLELO 0x4266E830 +#define IG3_STATS_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_S 0 +#define IG3_STATS_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXONEHOLELO_TCPRXONEHOLELO_S) +#define IG3_STATS_GLPES_TCPRXPUREACKSHI 0x4266E82C +#define IG3_STATS_GLPES_TCPRXPUREACKSHI_TCPRXPUREACKSHI_S 0 +#define IG3_STATS_GLPES_TCPRXPUREACKSHI_TCPRXPUREACKSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXPUREACKSHI_TCPRXPUREACKSHI_S) +#define IG3_STATS_GLPES_TCPRXPUREACKSLO 0x4266E828 +#define IG3_STATS_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_S 0 +#define IG3_STATS_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXPUREACKSLO_TCPRXPUREACKLO_S) +#define IG3_STATS_GLPES_TCPRXTHREEHOLEHI 0x4266E844 +#define IG3_STATS_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_S 0 +#define IG3_STATS_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXTHREEHOLEHI_TCPRXTHREEHOLEHI_S) +#define IG3_STATS_GLPES_TCPRXTHREEHOLELO 0x4266E840 +#define IG3_STATS_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_S 0 +#define IG3_STATS_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXTHREEHOLELO_TCPRXTHREEHOLELO_S) +#define IG3_STATS_GLPES_TCPRXTWOHOLEHI 0x4266E83C +#define IG3_STATS_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_S 0 +#define IG3_STATS_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXTWOHOLEHI_TCPRXTWOHOLEHI_S) +#define IG3_STATS_GLPES_TCPRXTWOHOLELO 0x4266E838 +#define IG3_STATS_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_S 0 +#define IG3_STATS_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPRXTWOHOLELO_TCPRXTWOHOLELO_S) +#define IG3_STATS_GLPES_TCPTXRETRANSFASTHI 0x4266E8AC +#define IG3_STATS_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_S 0 +#define IG3_STATS_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPTXRETRANSFASTHI_TCPTXRETRANSFASTHI_S) +#define IG3_STATS_GLPES_TCPTXRETRANSFASTLO 0x4266E8A8 +#define IG3_STATS_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_S 0 +#define IG3_STATS_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPTXRETRANSFASTLO_TCPTXRETRANSFASTLO_S) +#define IG3_STATS_GLPES_TCPTXTOUTSFASTHI 0x4266E8B4 +#define IG3_STATS_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_S 0 +#define IG3_STATS_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPTXTOUTSFASTHI_TCPTXTOUTSFASTHI_S) +#define IG3_STATS_GLPES_TCPTXTOUTSFASTLO 0x4266E8B0 +#define IG3_STATS_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_S 0 +#define IG3_STATS_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPTXTOUTSFASTLO_TCPTXTOUTSFASTLO_S) +#define IG3_STATS_GLPES_TCPTXTOUTSHI 0x4266E8BC +#define IG3_STATS_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_S 0 +#define IG3_STATS_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPTXTOUTSHI_TCPTXTOUTSHI_S) +#define IG3_STATS_GLPES_TCPTXTOUTSLO 0x4266E8B8 +#define IG3_STATS_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_S 0 +#define IG3_STATS_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TCPTXTOUTSLO_TCPTXTOUTSLO_S) +#define IG3_STATS_GLPES_TEPCNTGP0HI 0x4266E8C4 +#define IG3_STATS_GLPES_TEPCNTGP0HI_TEPGP0_S 0 +#define IG3_STATS_GLPES_TEPCNTGP0HI_TEPGP0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TEPCNTGP0HI_TEPGP0_S) +#define IG3_STATS_GLPES_TEPCNTGP0LO 0x4266E8C0 +#define IG3_STATS_GLPES_TEPCNTGP0LO_TEPGP0_S 0 +#define IG3_STATS_GLPES_TEPCNTGP0LO_TEPGP0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TEPCNTGP0LO_TEPGP0_S) +#define IG3_STATS_GLPES_TEPCNTGP1HI 0x4266E8CC +#define IG3_STATS_GLPES_TEPCNTGP1HI_TEPGP1_S 0 +#define IG3_STATS_GLPES_TEPCNTGP1HI_TEPGP1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TEPCNTGP1HI_TEPGP1_S) +#define IG3_STATS_GLPES_TEPCNTGP1LO 0x4266E8C8 +#define IG3_STATS_GLPES_TEPCNTGP1LO_TEPGP1_S 0 +#define IG3_STATS_GLPES_TEPCNTGP1LO_TEPGP1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TEPCNTGP1LO_TEPGP1_S) +#define IG3_STATS_GLPES_TEPCNTGP2HI 0x4266E8D4 +#define IG3_STATS_GLPES_TEPCNTGP2HI_TEPGP2_S 0 +#define IG3_STATS_GLPES_TEPCNTGP2HI_TEPGP2_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TEPCNTGP2HI_TEPGP2_S) +#define IG3_STATS_GLPES_TEPCNTGP2LO 0x4266E8D0 +#define IG3_STATS_GLPES_TEPCNTGP2LO_TEPGP2_S 0 +#define IG3_STATS_GLPES_TEPCNTGP2LO_TEPGP2_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TEPCNTGP2LO_TEPGP2_S) +#define IG3_STATS_GLPES_TEPCNTGP3HI 0x4266E8DC +#define IG3_STATS_GLPES_TEPCNTGP3HI_TEPGP3_S 0 +#define IG3_STATS_GLPES_TEPCNTGP3HI_TEPGP3_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TEPCNTGP3HI_TEPGP3_S) +#define IG3_STATS_GLPES_TEPCNTGP3LO 0x4266E8D8 +#define IG3_STATS_GLPES_TEPCNTGP3LO_TEPGP3_S 0 +#define IG3_STATS_GLPES_TEPCNTGP3LO_TEPGP3_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TEPCNTGP3LO_TEPGP3_S) +#define IG3_STATS_GLPES_TXABORTSHI 0x4266E8E4 +#define IG3_STATS_GLPES_TXABORTSHI_TXABORTSHI_S 0 +#define IG3_STATS_GLPES_TXABORTSHI_TXABORTSHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TXABORTSHI_TXABORTSHI_S) +#define IG3_STATS_GLPES_TXABORTSLO 0x4266E8E0 +#define IG3_STATS_GLPES_TXABORTSLO_TXABORTSLO_S 0 +#define IG3_STATS_GLPES_TXABORTSLO_TXABORTSLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_TXABORTSLO_TXABORTSLO_S) +#define IG3_STATS_GLPES_UDPMCDPIGNREPLCNTHI 0x4266E87C +#define IG3_STATS_GLPES_UDPMCDPIGNREPLCNTHI_GLPE_UDAMCDPIGNREPLCNT_S 0 +#define IG3_STATS_GLPES_UDPMCDPIGNREPLCNTHI_GLPE_UDAMCDPIGNREPLCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_UDPMCDPIGNREPLCNTHI_GLPE_UDAMCDPIGNREPLCNT_S) +#define IG3_STATS_GLPES_UDPMCDPIGNREPLCNTLO 0x4266E878 +#define IG3_STATS_GLPES_UDPMCDPIGNREPLCNTLO_GLPE_UDAMCDPIGNREPLCNT_S 0 +#define IG3_STATS_GLPES_UDPMCDPIGNREPLCNTLO_GLPE_UDAMCDPIGNREPLCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_UDPMCDPIGNREPLCNTLO_GLPE_UDAMCDPIGNREPLCNT_S) +#define IG3_STATS_GLPES_UDPMCREPLCNTHI 0x4266E874 +#define IG3_STATS_GLPES_UDPMCREPLCNTHI_UDAMCREPLCNT_S 0 +#define IG3_STATS_GLPES_UDPMCREPLCNTHI_UDAMCREPLCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_UDPMCREPLCNTHI_UDAMCREPLCNT_S) +#define IG3_STATS_GLPES_UDPMCREPLCNTLO 0x4266E870 +#define IG3_STATS_GLPES_UDPMCREPLCNTLO_UDAMCREPLCNT_S 0 +#define IG3_STATS_GLPES_UDPMCREPLCNTLO_UDAMCREPLCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_UDPMCREPLCNTLO_UDAMCREPLCNT_S) +#define IG3_STATS_GLPES_XLRCOUNTHI 0x4266E904 +#define IG3_STATS_GLPES_XLRCOUNTHI_XLRCOUNTHI_S 0 +#define IG3_STATS_GLPES_XLRCOUNTHI_XLRCOUNTHI_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_XLRCOUNTHI_XLRCOUNTHI_S) +#define IG3_STATS_GLPES_XLRCOUNTLO 0x4266E900 +#define IG3_STATS_GLPES_XLRCOUNTLO_XLRCOUNTLO_S 0 +#define IG3_STATS_GLPES_XLRCOUNTLO_XLRCOUNTLO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_STATS_GLPES_XLRCOUNTLO_XLRCOUNTLO_S) +#define IG3_STATS_GLPE_STATS_ECC_COR_ERR 0x4266EFA4 +#define IG3_STATS_GLPE_STATS_ECC_COR_ERR_RSVD_S 12 +#define IG3_STATS_GLPE_STATS_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_STATS_GLPE_STATS_ECC_COR_ERR_RSVD_S) +#define IG3_STATS_GLPE_STATS_ECC_COR_ERR_CNT_S 0 +#define IG3_STATS_GLPE_STATS_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_STATS_GLPE_STATS_ECC_COR_ERR_CNT_S) +#define IG3_STATS_GLPE_STATS_ECC_UNCOR_ERR 0x4266EFA0 +#define IG3_STATS_GLPE_STATS_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_STATS_GLPE_STATS_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_STATS_GLPE_STATS_ECC_UNCOR_ERR_RSVD_S) +#define IG3_STATS_GLPE_STATS_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_STATS_GLPE_STATS_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_STATS_GLPE_STATS_ECC_UNCOR_ERR_CNT_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG 0x4266EF98 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD3_S 20 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD3_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RM_S 16 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RM_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD2_S 14 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD2_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RME_S 12 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RME_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD1_S 10 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD1_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ERR_CNT_S 9 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ERR_CNT_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_FIX_CNT_S 8 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_FIX_CNT_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD0_S 6 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_RSVD0_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_MASK_INT_S 5 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_MASK_INT_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_LS_BYPASS_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_LS_FORCE_S 3 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_LS_FORCE_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_EN_S 0 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_CFG_ECC_EN_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS 0x4266EF9C +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_RSVD1_S 30 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_RSVD1_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_RSVD0_S 4 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_RSVD0_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_ECC_FIX_S) +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_FOUR_MEM_STATUS_ECC_ERR_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG 0x4266EF68 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD3_S 20 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD3_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RM_S 16 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RM_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD2_S 14 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD2_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RME_S 12 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RME_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD1_S 10 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD1_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ERR_CNT_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_FIX_CNT_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD0_S 6 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_RSVD0_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_MASK_INT_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_LS_FORCE_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_CFG_ECC_EN_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS 0x4266EF6C +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_RSVD1_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_RSVD0_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG 0x4266EF70 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD3_S 20 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD3_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RM_S 16 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RM_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD2_S 14 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD2_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RME_S 12 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RME_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD1_S 10 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD1_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ERR_CNT_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_FIX_CNT_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD0_S 6 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_RSVD0_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_MASK_INT_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_LS_FORCE_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_CFG_ECC_EN_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS 0x4266EF74 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_RSVD1_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_RSVD0_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_ONE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG 0x4266EF88 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD3_S 20 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD3_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RM_S 16 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RM_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD2_S 14 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD2_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RME_S 12 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RME_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD1_S 10 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD1_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ERR_CNT_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_FIX_CNT_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD0_S 6 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_RSVD0_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_MASK_INT_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_LS_FORCE_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_CFG_ECC_EN_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS 0x4266EF8C +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_RSVD1_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_RSVD0_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG 0x4266EF90 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD3_S 20 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD3_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RM_S 16 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RM_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD2_S 14 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD2_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RME_S 12 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RME_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD1_S 10 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD1_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ERR_CNT_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_FIX_CNT_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD0_S 6 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_RSVD0_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_MASK_INT_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_LS_FORCE_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_CFG_ECC_EN_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS 0x4266EF94 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_RSVD1_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_RSVD0_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_THREE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG 0x4266EF78 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD3_S 20 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD3_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RM_S 16 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RM_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD2_S 14 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD2_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RME_S 12 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RME_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD1_S 10 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD1_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ERR_CNT_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_FIX_CNT_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD0_S 6 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_RSVD0_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_MASK_INT_S 5 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_MASK_INT_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_LS_BYPASS_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_LS_FORCE_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_EN_S 0 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_CFG_ECC_EN_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS 0x4266EF7C +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_RSVD1_S 30 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_RSVD1_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_RSVD0_S 4 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_RSVD0_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_ECC_FIX_S) +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_0_MEM_STATUS_ECC_ERR_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG 0x4266EF80 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD3_S 20 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD3_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RM_S 16 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RM_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD2_S 14 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD2_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RME_S 12 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RME_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD1_S 10 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD1_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ERR_CNT_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_FIX_CNT_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD0_S 6 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_RSVD0_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_MASK_INT_S 5 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_MASK_INT_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_LS_BYPASS_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_LS_FORCE_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_EN_S 0 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_CFG_ECC_EN_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS 0x4266EF84 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_RSVD1_S 30 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_RSVD1_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_RSVD0_S 4 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_RSVD0_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_INIT_DONE_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_ECC_FIX_S) +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_STATS_GLPE_STATS_TWO_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_GLHMC_CEQMAX 0x42807214 +#define IG3_PMAT_GLHMC_CEQMAX_RSVD_S 12 +#define IG3_PMAT_GLHMC_CEQMAX_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_GLHMC_CEQMAX_RSVD_S) +#define IG3_PMAT_GLHMC_CEQMAX_GLHMC_CEQMAX_S 0 +#define IG3_PMAT_GLHMC_CEQMAX_GLHMC_CEQMAX_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_GLHMC_CEQMAX_GLHMC_CEQMAX_S) +#define IG3_PMAT_GLHMC_DBCQMAX 0x42807210 +#define IG3_PMAT_GLHMC_DBCQMAX_RSVD_S 22 +#define IG3_PMAT_GLHMC_DBCQMAX_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_PMAT_GLHMC_DBCQMAX_RSVD_S) +#define IG3_PMAT_GLHMC_DBCQMAX_GLHMC_DBCQMAX_S 0 +#define IG3_PMAT_GLHMC_DBCQMAX_GLHMC_DBCQMAX_M RDMA_MASK3(32, 0x3FFFFF, IG3_PMAT_GLHMC_DBCQMAX_GLHMC_DBCQMAX_S) +#define IG3_PMAT_GLHMC_DBQPMAX 0x4280720C +#define IG3_PMAT_GLHMC_DBQPMAX_RSVD_S 21 +#define IG3_PMAT_GLHMC_DBQPMAX_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_PMAT_GLHMC_DBQPMAX_RSVD_S) +#define IG3_PMAT_GLHMC_DBQPMAX_GLHMC_DBQPMAX_S 0 +#define IG3_PMAT_GLHMC_DBQPMAX_GLHMC_DBQPMAX_M RDMA_MASK3(32, 0x1FFFFF, IG3_PMAT_GLHMC_DBQPMAX_GLHMC_DBQPMAX_S) +#define IG3_PMAT_GLHMC_DEBUG 0x428071C4 +#define IG3_PMAT_GLHMC_DEBUG_RSVD_S 4 +#define IG3_PMAT_GLHMC_DEBUG_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_DEBUG_RSVD_S) +#define IG3_PMAT_GLHMC_DEBUG_NAK_DIS_S 3 +#define IG3_PMAT_GLHMC_DEBUG_NAK_DIS_M RDMA_BIT2(32, IG3_PMAT_GLHMC_DEBUG_NAK_DIS_S) +#define IG3_PMAT_GLHMC_DEBUG_PD_DIS_S 2 +#define IG3_PMAT_GLHMC_DEBUG_PD_DIS_M RDMA_BIT2(32, IG3_PMAT_GLHMC_DEBUG_PD_DIS_S) +#define IG3_PMAT_GLHMC_DEBUG_MEM_DIS_S 1 +#define IG3_PMAT_GLHMC_DEBUG_MEM_DIS_M RDMA_BIT2(32, IG3_PMAT_GLHMC_DEBUG_MEM_DIS_S) +#define IG3_PMAT_GLHMC_DEBUG_SOFT_RESET_S 0 +#define IG3_PMAT_GLHMC_DEBUG_SOFT_RESET_M RDMA_BIT2(32, IG3_PMAT_GLHMC_DEBUG_SOFT_RESET_S) +#define IG3_PMAT_GLHMC_DOMAIN_ID 0x4280721C +#define IG3_PMAT_GLHMC_DOMAIN_ID_RSVD_S 3 +#define IG3_PMAT_GLHMC_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_DOMAIN_ID_RSVD_S) +#define IG3_PMAT_GLHMC_DOMAIN_ID_ATOMIC_DOMAIN_ID_S 0 +#define IG3_PMAT_GLHMC_DOMAIN_ID_ATOMIC_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_DOMAIN_ID_ATOMIC_DOMAIN_ID_S) +#define IG3_PMAT_GLHMC_FSIAVBASE(_i) 0x42830000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_FSIAVBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_FSIAVBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_FSIAVBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_FSIAVBASE_RSVD_S) +#define IG3_PMAT_GLHMC_FSIAVBASE_FPMFSIAVBASE_S 0 +#define IG3_PMAT_GLHMC_FSIAVBASE_FPMFSIAVBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_FSIAVBASE_FPMFSIAVBASE_S) +#define IG3_PMAT_GLHMC_FSIAVCNT(_i) 0x42832000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_FSIAVCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_FSIAVCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_FSIAVCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_FSIAVCNT_RSVD_S) +#define IG3_PMAT_GLHMC_FSIAVCNT_FPMFSIAVCNT_S 0 +#define IG3_PMAT_GLHMC_FSIAVCNT_FPMFSIAVCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_FSIAVCNT_FPMFSIAVCNT_S) +#define IG3_PMAT_GLHMC_FSIAVMAX 0x428071A0 +#define IG3_PMAT_GLHMC_FSIAVMAX_RSVD_S 22 +#define IG3_PMAT_GLHMC_FSIAVMAX_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_PMAT_GLHMC_FSIAVMAX_RSVD_S) +#define IG3_PMAT_GLHMC_FSIAVMAX_PMFSIAVMAX_S 0 +#define IG3_PMAT_GLHMC_FSIAVMAX_PMFSIAVMAX_M RDMA_MASK3(32, 0x3FFFFF, IG3_PMAT_GLHMC_FSIAVMAX_PMFSIAVMAX_S) +#define IG3_PMAT_GLHMC_FSIAVOBJSZ 0x4280719C +#define IG3_PMAT_GLHMC_FSIAVOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_FSIAVOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_FSIAVOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_S 0 +#define IG3_PMAT_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_FSIAVOBJSZ_PMFSIAVOBJSZ_S) +#define IG3_PMAT_GLHMC_FSIMCBASE(_i) 0x42844000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_FSIMCBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_FSIMCBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_FSIMCBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_FSIMCBASE_RSVD_S) +#define IG3_PMAT_GLHMC_FSIMCBASE_FPMFSIMCBASE_S 0 +#define IG3_PMAT_GLHMC_FSIMCBASE_FPMFSIMCBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_FSIMCBASE_FPMFSIMCBASE_S) +#define IG3_PMAT_GLHMC_FSIMCCNT(_i) 0x42846000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_FSIMCCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_FSIMCCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_FSIMCCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_FSIMCCNT_RSVD_S) +#define IG3_PMAT_GLHMC_FSIMCCNT_FPMFSIMCSZ_S 0 +#define IG3_PMAT_GLHMC_FSIMCCNT_FPMFSIMCSZ_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_FSIMCCNT_FPMFSIMCSZ_S) +#define IG3_PMAT_GLHMC_FSIMCMAX 0x42807198 +#define IG3_PMAT_GLHMC_FSIMCMAX_RSVD_S 14 +#define IG3_PMAT_GLHMC_FSIMCMAX_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_GLHMC_FSIMCMAX_RSVD_S) +#define IG3_PMAT_GLHMC_FSIMCMAX_PMFSIMCMAX_S 0 +#define IG3_PMAT_GLHMC_FSIMCMAX_PMFSIMCMAX_M RDMA_MASK3(32, 0x3FFF, IG3_PMAT_GLHMC_FSIMCMAX_PMFSIMCMAX_S) +#define IG3_PMAT_GLHMC_FSIMCOBJSZ 0x42807194 +#define IG3_PMAT_GLHMC_FSIMCOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_FSIMCOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_FSIMCOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_S 0 +#define IG3_PMAT_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_FSIMCOBJSZ_PMFSIMCOBJSZ_S) +#define IG3_PMAT_GLHMC_FWPDINV 0x428071B8 +#define IG3_PMAT_GLHMC_FWPDINV_RSVD1_S 25 +#define IG3_PMAT_GLHMC_FWPDINV_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PMAT_GLHMC_FWPDINV_RSVD1_S) +#define IG3_PMAT_GLHMC_FWPDINV_PMPDIDX_S 16 +#define IG3_PMAT_GLHMC_FWPDINV_PMPDIDX_M RDMA_MASK3(32, 0x1FF, IG3_PMAT_GLHMC_FWPDINV_PMPDIDX_S) +#define IG3_PMAT_GLHMC_FWPDINV_RSVD_S 15 +#define IG3_PMAT_GLHMC_FWPDINV_RSVD_M RDMA_BIT2(32, IG3_PMAT_GLHMC_FWPDINV_RSVD_S) +#define IG3_PMAT_GLHMC_FWPDINV_PMSDIDX_S 0 +#define IG3_PMAT_GLHMC_FWPDINV_PMSDIDX_M RDMA_MASK3(32, 0x7FFF, IG3_PMAT_GLHMC_FWPDINV_PMSDIDX_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0 0x428071F8 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_CMD_DONE_S 31 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_CMD_DONE_M RDMA_BIT2(32, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_CMD_DONE_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_CMD_FAILED_S 30 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_CMD_FAILED_M RDMA_BIT2(32, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_CMD_FAILED_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_RSVD2_S 29 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_RSVD2_M RDMA_BIT2(32, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_RSVD2_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_VDEV_VF_TYPE_S 27 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_VDEV_VF_TYPE_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_RSVD1_S 26 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_RSVD1_M RDMA_BIT2(32, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_RSVD1_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_VDEV_VF_NUM_S 16 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_VDEV_VF_NUM_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_CMD_S 13 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_CMD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_CMD_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_TYPE_S 8 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_TYPE_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_RSVD0_S 6 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_RSVD0_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_PF_NUM_S 0 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PMAT_GLHMC_IMCOBJCACHECTL0_OBJ_PF_NUM_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL1 0x428071FC +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL1_RSVD_S 28 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_IMCOBJCACHECTL1_RSVD_S) +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL1_OBJ_INDEX_S 0 +#define IG3_PMAT_GLHMC_IMCOBJCACHECTL1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_IMCOBJCACHECTL1_OBJ_INDEX_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0(_i) 0x42807000 + ((_i) * 4) /* _i=0...15 */ +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_MAX_INDEX_I 15 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_CMD_DONE_S 31 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_CMD_DONE_M RDMA_BIT2(32, IG3_PMAT_GLHMC_OBJECTCACHECTL0_CMD_DONE_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_CMD_FAILED_S 30 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_CMD_FAILED_M RDMA_BIT2(32, IG3_PMAT_GLHMC_OBJECTCACHECTL0_CMD_FAILED_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_RSVD2_S 29 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_RSVD2_M RDMA_BIT2(32, IG3_PMAT_GLHMC_OBJECTCACHECTL0_RSVD2_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_VDEV_VF_TYPE_S 27 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_VDEV_VF_TYPE_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_RSVD1_S 26 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_RSVD1_M RDMA_BIT2(32, IG3_PMAT_GLHMC_OBJECTCACHECTL0_RSVD1_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_VDEV_VF_NUM_S 16 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_VDEV_VF_NUM_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_CMD_S 13 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_CMD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_OBJECTCACHECTL0_CMD_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_TYPE_S 8 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_TYPE_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_RSVD0_S 6 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_GLHMC_OBJECTCACHECTL0_RSVD0_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_PF_NUM_S 0 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PMAT_GLHMC_OBJECTCACHECTL0_OBJ_PF_NUM_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL1(_i) 0x42807100 + ((_i) * 4) /* _i=0...15 */ +#define IG3_PMAT_GLHMC_OBJECTCACHECTL1_MAX_INDEX_I 15 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL1_RSVD_S 28 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_OBJECTCACHECTL1_RSVD_S) +#define IG3_PMAT_GLHMC_OBJECTCACHECTL1_OBJ_INDEX_S 0 +#define IG3_PMAT_GLHMC_OBJECTCACHECTL1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_OBJECTCACHECTL1_OBJ_INDEX_S) +#define IG3_PMAT_GLHMC_PASID(_i) 0x42802000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PASID_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PASID_RSVD_S 21 +#define IG3_PMAT_GLHMC_PASID_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_PMAT_GLHMC_PASID_RSVD_S) +#define IG3_PMAT_GLHMC_PASID_PASID_VALID_S 20 +#define IG3_PMAT_GLHMC_PASID_PASID_VALID_M RDMA_BIT2(32, IG3_PMAT_GLHMC_PASID_PASID_VALID_S) +#define IG3_PMAT_GLHMC_PASID_PASID_S 0 +#define IG3_PMAT_GLHMC_PASID_PASID_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_GLHMC_PASID_PASID_S) +#define IG3_PMAT_GLHMC_PE32BRSVDBASE(_i) 0x4283C000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PE32BRSVDBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PE32BRSVDBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PE32BRSVDBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PE32BRSVDBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PE32BRSVDBASE_FPMPE32BRSVDBASE_S 0 +#define IG3_PMAT_GLHMC_PE32BRSVDBASE_FPMPE32BRSVDBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PE32BRSVDBASE_FPMPE32BRSVDBASE_S) +#define IG3_PMAT_GLHMC_PE32BRSVDCNT(_i) 0x4283E000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PE32BRSVDCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PE32BRSVDCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PE32BRSVDCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PE32BRSVDCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PE32BRSVDCNT_FPMPE32BRSVDCNT_S 0 +#define IG3_PMAT_GLHMC_PE32BRSVDCNT_FPMPE32BRSVDCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PE32BRSVDCNT_FPMPE32BRSVDCNT_S) +#define IG3_PMAT_GLHMC_PE32BRSVDMAX 0x428071D4 +#define IG3_PMAT_GLHMC_PE32BRSVDMAX_RSVD_S 29 +#define IG3_PMAT_GLHMC_PE32BRSVDMAX_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PE32BRSVDMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PE32BRSVDMAX_PMPE32BRSVDMAX_S 0 +#define IG3_PMAT_GLHMC_PE32BRSVDMAX_PMPE32BRSVDMAX_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PE32BRSVDMAX_PMPE32BRSVDMAX_S) +#define IG3_PMAT_GLHMC_PE32BRSVDOBJSZ 0x428071D0 +#define IG3_PMAT_GLHMC_PE32BRSVDOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PE32BRSVDOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PE32BRSVDOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PE32BRSVDOBJSZ_PMPE32BRSVDOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PE32BRSVDOBJSZ_PMPE32BRSVDOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PE32BRSVDOBJSZ_PMPE32BRSVDOBJSZ_S) +#define IG3_PMAT_GLHMC_PE64BRSVDBASE(_i) 0x42840000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PE64BRSVDBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PE64BRSVDBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PE64BRSVDBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PE64BRSVDBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PE64BRSVDBASE_FPMPE64BRSVDBASE_S 0 +#define IG3_PMAT_GLHMC_PE64BRSVDBASE_FPMPE64BRSVDBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PE64BRSVDBASE_FPMPE64BRSVDBASE_S) +#define IG3_PMAT_GLHMC_PE64BRSVDCNT(_i) 0x42842000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PE64BRSVDCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PE64BRSVDCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PE64BRSVDCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PE64BRSVDCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PE64BRSVDCNT_FPMPE64BRSVDCNT_S 0 +#define IG3_PMAT_GLHMC_PE64BRSVDCNT_FPMPE64BRSVDCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PE64BRSVDCNT_FPMPE64BRSVDCNT_S) +#define IG3_PMAT_GLHMC_PE64BRSVDMAX 0x428071DC +#define IG3_PMAT_GLHMC_PE64BRSVDMAX_RSVD_S 29 +#define IG3_PMAT_GLHMC_PE64BRSVDMAX_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PE64BRSVDMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PE64BRSVDMAX_PMPE64BRSVDMAX_S 0 +#define IG3_PMAT_GLHMC_PE64BRSVDMAX_PMPE64BRSVDMAX_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PE64BRSVDMAX_PMPE64BRSVDMAX_S) +#define IG3_PMAT_GLHMC_PE64BRSVDOBJSZ 0x428071D8 +#define IG3_PMAT_GLHMC_PE64BRSVDOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PE64BRSVDOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PE64BRSVDOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PE64BRSVDOBJSZ_PMPE64BRSVDOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PE64BRSVDOBJSZ_PMPE64BRSVDOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PE64BRSVDOBJSZ_PMPE64BRSVDOBJSZ_S) +#define IG3_PMAT_GLHMC_PEARPBASE(_i) 0x42818000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEARPBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEARPBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEARPBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEARPBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEARPBASE_FPMPEARPBASE_S 0 +#define IG3_PMAT_GLHMC_PEARPBASE_FPMPEARPBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEARPBASE_FPMPEARPBASE_S) +#define IG3_PMAT_GLHMC_PEARPCNT(_i) 0x4281A000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEARPCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEARPCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEARPCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEARPCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PEARPCNT_FPMPEARPCNT_S 0 +#define IG3_PMAT_GLHMC_PEARPCNT_FPMPEARPCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEARPCNT_FPMPEARPCNT_S) +#define IG3_PMAT_GLHMC_PEARPMAX 0x42807170 +#define IG3_PMAT_GLHMC_PEARPMAX_RSVD_S 17 +#define IG3_PMAT_GLHMC_PEARPMAX_RSVD_M RDMA_MASK3(32, 0x7FFF, IG3_PMAT_GLHMC_PEARPMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEARPMAX_PMPEARPMAX_S 0 +#define IG3_PMAT_GLHMC_PEARPMAX_PMPEARPMAX_M RDMA_MASK3(32, 0x1FFFF, IG3_PMAT_GLHMC_PEARPMAX_PMPEARPMAX_S) +#define IG3_PMAT_GLHMC_PEARPOBJSZ 0x4280716C +#define IG3_PMAT_GLHMC_PEARPOBJSZ_RSVD_S 3 +#define IG3_PMAT_GLHMC_PEARPOBJSZ_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEARPOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEARPOBJSZ_PMPEARPOBJSZ_S) +#define IG3_PMAT_GLHMC_PECQBASE(_i) 0x4280C000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PECQBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PECQBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PECQBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PECQBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PECQBASE_FPMPECQBASE_S 0 +#define IG3_PMAT_GLHMC_PECQBASE_FPMPECQBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PECQBASE_FPMPECQBASE_S) +#define IG3_PMAT_GLHMC_PECQCNT(_i) 0x4280E000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PECQCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PECQCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PECQCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PECQCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PECQCNT_FPMPECQCNT_S 0 +#define IG3_PMAT_GLHMC_PECQCNT_FPMPECQCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PECQCNT_FPMPECQCNT_S) +#define IG3_PMAT_GLHMC_PECQOBJSZ 0x42807158 +#define IG3_PMAT_GLHMC_PECQOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PECQOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PECQOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PECQOBJSZ_PMPECQOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PECQOBJSZ_PMPECQOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PECQOBJSZ_PMPECQOBJSZ_S) +#define IG3_PMAT_GLHMC_PEHDRBASE(_i) 0x42848000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEHDRBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEHDRBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEHDRBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEHDRBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_S 0 +#define IG3_PMAT_GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEHDRBASE_GLHMC_PEHDRBASE_S) +#define IG3_PMAT_GLHMC_PEHDRCNT(_i) 0x4284A000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEHDRCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEHDRCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEHDRCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEHDRCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_S 0 +#define IG3_PMAT_GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEHDRCNT_GLHMC_PEHDRCNT_S) +#define IG3_PMAT_GLHMC_PEHDRMAX 0x42807148 +#define IG3_PMAT_GLHMC_PEHDRMAX_RSVD_S 21 +#define IG3_PMAT_GLHMC_PEHDRMAX_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_PMAT_GLHMC_PEHDRMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEHDRMAX_PMPEHDRMAX_S 0 +#define IG3_PMAT_GLHMC_PEHDRMAX_PMPEHDRMAX_M RDMA_MASK3(32, 0x1FFFFF, IG3_PMAT_GLHMC_PEHDRMAX_PMPEHDRMAX_S) +#define IG3_PMAT_GLHMC_PEHDROBJSZ 0x42807144 +#define IG3_PMAT_GLHMC_PEHDROBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PEHDROBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEHDROBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_S 0 +#define IG3_PMAT_GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEHDROBJSZ_PMPEHDROBJSZ_S) +#define IG3_PMAT_GLHMC_PEHTCNT(_i) 0x42816000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEHTCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEHTCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEHTCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEHTCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PEHTCNT_FPMPEHTCNT_S 0 +#define IG3_PMAT_GLHMC_PEHTCNT_FPMPEHTCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEHTCNT_FPMPEHTCNT_S) +#define IG3_PMAT_GLHMC_PEHTEBASE(_i) 0x42814000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEHTEBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEHTEBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEHTEBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEHTEBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEHTEBASE_FPMPEHTEBASE_S 0 +#define IG3_PMAT_GLHMC_PEHTEBASE_FPMPEHTEBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEHTEBASE_FPMPEHTEBASE_S) +#define IG3_PMAT_GLHMC_PEHTEOBJSZ 0x42807164 +#define IG3_PMAT_GLHMC_PEHTEOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PEHTEOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEHTEOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEHTEOBJSZ_PMPEHTEOBJSZ_S) +#define IG3_PMAT_GLHMC_PEHTMAX 0x42807168 +#define IG3_PMAT_GLHMC_PEHTMAX_RSVD_S 21 +#define IG3_PMAT_GLHMC_PEHTMAX_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_PMAT_GLHMC_PEHTMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEHTMAX_PMPEHTMAX_S 0 +#define IG3_PMAT_GLHMC_PEHTMAX_PMPEHTMAX_M RDMA_MASK3(32, 0x1FFFFF, IG3_PMAT_GLHMC_PEHTMAX_PMPEHTMAX_S) +#define IG3_PMAT_GLHMC_PEMRBASE(_i) 0x4281C000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEMRBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEMRBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEMRBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEMRBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEMRBASE_FPMPEMRBASE_S 0 +#define IG3_PMAT_GLHMC_PEMRBASE_FPMPEMRBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEMRBASE_FPMPEMRBASE_S) +#define IG3_PMAT_GLHMC_PEMRCNT(_i) 0x4281E000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEMRCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEMRCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEMRCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEMRCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PEMRCNT_FPMPEMRSZ_S 0 +#define IG3_PMAT_GLHMC_PEMRCNT_FPMPEMRSZ_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEMRCNT_FPMPEMRSZ_S) +#define IG3_PMAT_GLHMC_PEMRMAX 0x42807178 +#define IG3_PMAT_GLHMC_PEMRMAX_RSVD_S 23 +#define IG3_PMAT_GLHMC_PEMRMAX_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PMAT_GLHMC_PEMRMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEMRMAX_PMPEMRMAX_S 0 +#define IG3_PMAT_GLHMC_PEMRMAX_PMPEMRMAX_M RDMA_MASK3(32, 0x7FFFFF, IG3_PMAT_GLHMC_PEMRMAX_PMPEMRMAX_S) +#define IG3_PMAT_GLHMC_PEMROBJSZ 0x42807174 +#define IG3_PMAT_GLHMC_PEMROBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PEMROBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEMROBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PEMROBJSZ_PMPEMROBJSZ_S 0 +#define IG3_PMAT_GLHMC_PEMROBJSZ_PMPEMROBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEMROBJSZ_PMPEMROBJSZ_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0 0x428071F0 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_CMD_DONE_S 31 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_CMD_DONE_M RDMA_BIT2(32, IG3_PMAT_GLHMC_PEOBJCACHECTL0_CMD_DONE_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_CMD_FAILED_S 30 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_CMD_FAILED_M RDMA_BIT2(32, IG3_PMAT_GLHMC_PEOBJCACHECTL0_CMD_FAILED_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_RSVD2_S 29 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_RSVD2_M RDMA_BIT2(32, IG3_PMAT_GLHMC_PEOBJCACHECTL0_RSVD2_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_VDEV_VF_TYPE_S 27 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_VDEV_VF_TYPE_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_RSVD1_S 26 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_RSVD1_M RDMA_BIT2(32, IG3_PMAT_GLHMC_PEOBJCACHECTL0_RSVD1_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_VDEV_VF_NUM_S 16 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_VDEV_VF_NUM_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_CMD_S 13 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_CMD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEOBJCACHECTL0_CMD_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_TYPE_S 8 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_TYPE_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_RSVD0_S 6 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_GLHMC_PEOBJCACHECTL0_RSVD0_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_PF_NUM_S 0 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PMAT_GLHMC_PEOBJCACHECTL0_OBJ_PF_NUM_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL1 0x428071F4 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL1_RSVD_S 28 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEOBJCACHECTL1_RSVD_S) +#define IG3_PMAT_GLHMC_PEOBJCACHECTL1_OBJ_INDEX_S 0 +#define IG3_PMAT_GLHMC_PEOBJCACHECTL1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEOBJCACHECTL1_OBJ_INDEX_S) +#define IG3_PMAT_GLHMC_PEOOISCBASE(_i) 0x4284C000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEOOISCBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEOOISCBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEOOISCBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEOOISCBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_S 0 +#define IG3_PMAT_GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEOOISCBASE_GLHMC_PEOOISCBASE_S) +#define IG3_PMAT_GLHMC_PEOOISCCNT(_i) 0x4284E000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEOOISCCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEOOISCCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEOOISCCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEOOISCCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_S 0 +#define IG3_PMAT_GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEOOISCCNT_GLHMC_PEOOISCCNT_S) +#define IG3_PMAT_GLHMC_PEOOISCFFLBASE(_i) 0x42858000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEOOISCFFLBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEOOISCFFLBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEOOISCFFLBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEOOISCFFLBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S 0 +#define IG3_PMAT_GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEOOISCFFLBASE_GLHMC_PEOOISCFFLBASE_S) +#define IG3_PMAT_GLHMC_PEOOISCFFLCNT_PMAT(_i) 0x4285A000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEOOISCFFLCNT_PMAT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEOOISCFFLCNT_PMAT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEOOISCFFLCNT_PMAT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEOOISCFFLCNT_PMAT_RSVD_S) +#define IG3_PMAT_GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFFLCNT_S 0 +#define IG3_PMAT_GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFFLCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEOOISCFFLCNT_PMAT_FPMPEOOISCFFLCNT_S) +#define IG3_PMAT_GLHMC_PEOOISCFFLMAX 0x428071EC +#define IG3_PMAT_GLHMC_PEOOISCFFLMAX_RSVD_S 21 +#define IG3_PMAT_GLHMC_PEOOISCFFLMAX_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_PMAT_GLHMC_PEOOISCFFLMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_S 0 +#define IG3_PMAT_GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_M RDMA_MASK3(32, 0x1FFFFF, IG3_PMAT_GLHMC_PEOOISCFFLMAX_PMPEOOISCFFLMAX_S) +#define IG3_PMAT_GLHMC_PEOOISCMAX 0x42807150 +#define IG3_PMAT_GLHMC_PEOOISCMAX_RSVD_S 21 +#define IG3_PMAT_GLHMC_PEOOISCMAX_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_PMAT_GLHMC_PEOOISCMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEOOISCMAX_PMPEOOISCMAX_S 0 +#define IG3_PMAT_GLHMC_PEOOISCMAX_PMPEOOISCMAX_M RDMA_MASK3(32, 0x1FFFFF, IG3_PMAT_GLHMC_PEOOISCMAX_PMPEOOISCMAX_S) +#define IG3_PMAT_GLHMC_PEOOISCOBJSZ 0x4280714C +#define IG3_PMAT_GLHMC_PEOOISCOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PEOOISCOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEOOISCOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEOOISCOBJSZ_PMPEOOISCOBJSZ_S) +#define IG3_PMAT_GLHMC_PEPBLBASE(_i) 0x42834000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEPBLBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEPBLBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEPBLBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEPBLBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEPBLBASE_FPMPEPBLBASE_S 0 +#define IG3_PMAT_GLHMC_PEPBLBASE_FPMPEPBLBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEPBLBASE_FPMPEPBLBASE_S) +#define IG3_PMAT_GLHMC_PEPBLCNT(_i) 0x42836000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEPBLCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEPBLCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEPBLCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEPBLCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PEPBLCNT_FPMPEPBLCNT_S 0 +#define IG3_PMAT_GLHMC_PEPBLCNT_FPMPEPBLCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEPBLCNT_FPMPEPBLCNT_S) +#define IG3_PMAT_GLHMC_PEPBLMAX 0x428071A4 +#define IG3_PMAT_GLHMC_PEPBLMAX_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEPBLMAX_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEPBLMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEPBLMAX_PMPEPBLMAX_S 0 +#define IG3_PMAT_GLHMC_PEPBLMAX_PMPEPBLMAX_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEPBLMAX_PMPEPBLMAX_S) +#define IG3_PMAT_GLHMC_PEQ1BASE(_i) 0x42828000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEQ1BASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEQ1BASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEQ1BASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEQ1BASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEQ1BASE_FPMPEQ1BASE_S 0 +#define IG3_PMAT_GLHMC_PEQ1BASE_FPMPEQ1BASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEQ1BASE_FPMPEQ1BASE_S) +#define IG3_PMAT_GLHMC_PEQ1CNT(_i) 0x4282A000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEQ1CNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEQ1CNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEQ1CNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEQ1CNT_RSVD_S) +#define IG3_PMAT_GLHMC_PEQ1CNT_FPMPEQ1CNT_S 0 +#define IG3_PMAT_GLHMC_PEQ1CNT_FPMPEQ1CNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEQ1CNT_FPMPEQ1CNT_S) +#define IG3_PMAT_GLHMC_PEQ1FLBASE(_i) 0x4282C000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEQ1FLBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEQ1FLBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEQ1FLBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEQ1FLBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_S 0 +#define IG3_PMAT_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEQ1FLBASE_FPMPEQ1FLBASE_S) +#define IG3_PMAT_GLHMC_PEQ1FLCNT_PMAT(_i) 0x4282E000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEQ1FLCNT_PMAT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEQ1FLCNT_PMAT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEQ1FLCNT_PMAT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEQ1FLCNT_PMAT_RSVD_S) +#define IG3_PMAT_GLHMC_PEQ1FLCNT_PMAT_FPMPEQ1FLCNT_S 0 +#define IG3_PMAT_GLHMC_PEQ1FLCNT_PMAT_FPMPEQ1FLCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEQ1FLCNT_PMAT_FPMPEQ1FLCNT_S) +#define IG3_PMAT_GLHMC_PEQ1FLMAX 0x42807190 +#define IG3_PMAT_GLHMC_PEQ1FLMAX_RSVD_S 28 +#define IG3_PMAT_GLHMC_PEQ1FLMAX_RSVD_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEQ1FLMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_S 0 +#define IG3_PMAT_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEQ1FLMAX_PMPEQ1FLMAX_S) +#define IG3_PMAT_GLHMC_PEQ1MAX 0x4280718C +#define IG3_PMAT_GLHMC_PEQ1MAX_RSVD_S 28 +#define IG3_PMAT_GLHMC_PEQ1MAX_RSVD_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEQ1MAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEQ1MAX_PMPEQ1MAX_S 0 +#define IG3_PMAT_GLHMC_PEQ1MAX_PMPEQ1MAX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEQ1MAX_PMPEQ1MAX_S) +#define IG3_PMAT_GLHMC_PEQ1OBJSZ 0x42807188 +#define IG3_PMAT_GLHMC_PEQ1OBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PEQ1OBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEQ1OBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_S 0 +#define IG3_PMAT_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEQ1OBJSZ_PMPEQ1OBJSZ_S) +#define IG3_PMAT_GLHMC_PEQPBASE(_i) 0x42808000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEQPBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEQPBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEQPBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEQPBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEQPBASE_FPMPEQPBASE_S 0 +#define IG3_PMAT_GLHMC_PEQPBASE_FPMPEQPBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEQPBASE_FPMPEQPBASE_S) +#define IG3_PMAT_GLHMC_PEQPCNT(_i) 0x4280A000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEQPCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEQPCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEQPCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEQPCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PEQPCNT_FPMPEQPCNT_S 0 +#define IG3_PMAT_GLHMC_PEQPCNT_FPMPEQPCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEQPCNT_FPMPEQPCNT_S) +#define IG3_PMAT_GLHMC_PEQPOBJSZ 0x42807154 +#define IG3_PMAT_GLHMC_PEQPOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PEQPOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEQPOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEQPOBJSZ_PMPEQPOBJSZ_S) +#define IG3_PMAT_GLHMC_PERRFBASE(_i) 0x42850000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PERRFBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PERRFBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PERRFBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PERRFBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PERRFBASE_GLHMC_PERRFBASE_S 0 +#define IG3_PMAT_GLHMC_PERRFBASE_GLHMC_PERRFBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PERRFBASE_GLHMC_PERRFBASE_S) +#define IG3_PMAT_GLHMC_PERRFCNT(_i) 0x42852000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PERRFCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PERRFCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PERRFCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PERRFCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PERRFCNT_GLHMC_PERRFCNT_S 0 +#define IG3_PMAT_GLHMC_PERRFCNT_GLHMC_PERRFCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PERRFCNT_GLHMC_PERRFCNT_S) +#define IG3_PMAT_GLHMC_PERRFFLBASE(_i) 0x42854000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PERRFFLBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PERRFFLBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PERRFFLBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PERRFFLBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_S 0 +#define IG3_PMAT_GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PERRFFLBASE_GLHMC_PERRFFLBASE_S) +#define IG3_PMAT_GLHMC_PERRFFLCNT_PMAT(_i) 0x42856000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PERRFFLCNT_PMAT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PERRFFLCNT_PMAT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PERRFFLCNT_PMAT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PERRFFLCNT_PMAT_RSVD_S) +#define IG3_PMAT_GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_S 0 +#define IG3_PMAT_GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PERRFFLCNT_PMAT_FPMPERRFFLCNT_S) +#define IG3_PMAT_GLHMC_PERRFFLMAX 0x428071E8 +#define IG3_PMAT_GLHMC_PERRFFLMAX_RSVD_S 27 +#define IG3_PMAT_GLHMC_PERRFFLMAX_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PERRFFLMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PERRFFLMAX_PMPERRFFLMAX_S 0 +#define IG3_PMAT_GLHMC_PERRFFLMAX_PMPERRFFLMAX_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PERRFFLMAX_PMPERRFFLMAX_S) +#define IG3_PMAT_GLHMC_PERRFMAX 0x428071E4 +#define IG3_PMAT_GLHMC_PERRFMAX_RSVD_S 28 +#define IG3_PMAT_GLHMC_PERRFMAX_RSVD_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PERRFMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PERRFMAX_PMPERRFMAX_S 0 +#define IG3_PMAT_GLHMC_PERRFMAX_PMPERRFMAX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PERRFMAX_PMPERRFMAX_S) +#define IG3_PMAT_GLHMC_PERRFOBJSZ 0x428071E0 +#define IG3_PMAT_GLHMC_PERRFOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PERRFOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PERRFOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PERRFOBJSZ_PMPERRFOBJSZ_S) +#define IG3_PMAT_GLHMC_PESRQBASE(_i) 0x42810000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PESRQBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PESRQBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PESRQBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PESRQBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PESRQBASE_FPMPESRQBASE_S 0 +#define IG3_PMAT_GLHMC_PESRQBASE_FPMPESRQBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PESRQBASE_FPMPESRQBASE_S) +#define IG3_PMAT_GLHMC_PESRQCNT(_i) 0x42812000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PESRQCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PESRQCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PESRQCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PESRQCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PESRQCNT_FPMPESRQCNT_S 0 +#define IG3_PMAT_GLHMC_PESRQCNT_FPMPESRQCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PESRQCNT_FPMPESRQCNT_S) +#define IG3_PMAT_GLHMC_PESRQMAX 0x42807160 +#define IG3_PMAT_GLHMC_PESRQMAX_RSVD_S 17 +#define IG3_PMAT_GLHMC_PESRQMAX_RSVD_M RDMA_MASK3(32, 0x7FFF, IG3_PMAT_GLHMC_PESRQMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PESRQMAX_PMPESRQMAX_S 0 +#define IG3_PMAT_GLHMC_PESRQMAX_PMPESRQMAX_M RDMA_MASK3(32, 0x1FFFF, IG3_PMAT_GLHMC_PESRQMAX_PMPESRQMAX_S) +#define IG3_PMAT_GLHMC_PESRQOBJSZ 0x4280715C +#define IG3_PMAT_GLHMC_PESRQOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PESRQOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PESRQOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PESRQOBJSZ_PMPESRQOBJSZ_S) +#define IG3_PMAT_GLHMC_PETIMERBASE(_i) 0x42838000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PETIMERBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PETIMERBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PETIMERBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PETIMERBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PETIMERBASE_FPMPETIMERBASE_S 0 +#define IG3_PMAT_GLHMC_PETIMERBASE_FPMPETIMERBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PETIMERBASE_FPMPETIMERBASE_S) +#define IG3_PMAT_GLHMC_PETIMERCNT(_i) 0x4283A000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PETIMERCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PETIMERCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PETIMERCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PETIMERCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PETIMERCNT_FPMPETIMERCNT_S 0 +#define IG3_PMAT_GLHMC_PETIMERCNT_FPMPETIMERCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PETIMERCNT_FPMPETIMERCNT_S) +#define IG3_PMAT_GLHMC_PETIMERMAX 0x428071CC +#define IG3_PMAT_GLHMC_PETIMERMAX_RSVD_S 29 +#define IG3_PMAT_GLHMC_PETIMERMAX_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PETIMERMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PETIMERMAX_PMPETIMERMAX_S 0 +#define IG3_PMAT_GLHMC_PETIMERMAX_PMPETIMERMAX_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PETIMERMAX_PMPETIMERMAX_S) +#define IG3_PMAT_GLHMC_PETIMEROBJSZ 0x428071C8 +#define IG3_PMAT_GLHMC_PETIMEROBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PETIMEROBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PETIMEROBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_S 0 +#define IG3_PMAT_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PETIMEROBJSZ_PMPETIMEROBJSZ_S) +#define IG3_PMAT_GLHMC_PEXFBASE(_i) 0x42820000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEXFBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEXFBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEXFBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEXFBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEXFBASE_FPMPEXFBASE_S 0 +#define IG3_PMAT_GLHMC_PEXFBASE_FPMPEXFBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEXFBASE_FPMPEXFBASE_S) +#define IG3_PMAT_GLHMC_PEXFCNT(_i) 0x42822000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEXFCNT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEXFCNT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEXFCNT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEXFCNT_RSVD_S) +#define IG3_PMAT_GLHMC_PEXFCNT_FPMPEXFCNT_S 0 +#define IG3_PMAT_GLHMC_PEXFCNT_FPMPEXFCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEXFCNT_FPMPEXFCNT_S) +#define IG3_PMAT_GLHMC_PEXFFLBASE(_i) 0x42824000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEXFFLBASE_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEXFFLBASE_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEXFFLBASE_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEXFFLBASE_RSVD_S) +#define IG3_PMAT_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_S 0 +#define IG3_PMAT_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEXFFLBASE_FPMPEXFFLBASE_S) +#define IG3_PMAT_GLHMC_PEXFFLCNT_PMAT(_i) 0x42826000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PMAT_GLHMC_PEXFFLCNT_PMAT_MAX_INDEX_I 1031 +#define IG3_PMAT_GLHMC_PEXFFLCNT_PMAT_RSVD_S 29 +#define IG3_PMAT_GLHMC_PEXFFLCNT_PMAT_RSVD_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_PEXFFLCNT_PMAT_RSVD_S) +#define IG3_PMAT_GLHMC_PEXFFLCNT_PMAT_FPMPEXFFLCNT_S 0 +#define IG3_PMAT_GLHMC_PEXFFLCNT_PMAT_FPMPEXFFLCNT_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_PMAT_GLHMC_PEXFFLCNT_PMAT_FPMPEXFFLCNT_S) +#define IG3_PMAT_GLHMC_PEXFFLMAX 0x42807184 +#define IG3_PMAT_GLHMC_PEXFFLMAX_RSVD_S 27 +#define IG3_PMAT_GLHMC_PEXFFLMAX_RSVD_M RDMA_MASK3(32, 0x1F, IG3_PMAT_GLHMC_PEXFFLMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEXFFLMAX_PMPEXFFLMAX_S 0 +#define IG3_PMAT_GLHMC_PEXFFLMAX_PMPEXFFLMAX_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PMAT_GLHMC_PEXFFLMAX_PMPEXFFLMAX_S) +#define IG3_PMAT_GLHMC_PEXFMAX 0x42807180 +#define IG3_PMAT_GLHMC_PEXFMAX_RSVD_S 28 +#define IG3_PMAT_GLHMC_PEXFMAX_RSVD_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEXFMAX_RSVD_S) +#define IG3_PMAT_GLHMC_PEXFMAX_PMPEXFMAX_S 0 +#define IG3_PMAT_GLHMC_PEXFMAX_PMPEXFMAX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEXFMAX_PMPEXFMAX_S) +#define IG3_PMAT_GLHMC_PEXFOBJSZ 0x4280717C +#define IG3_PMAT_GLHMC_PEXFOBJSZ_RSVD_S 4 +#define IG3_PMAT_GLHMC_PEXFOBJSZ_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PMAT_GLHMC_PEXFOBJSZ_RSVD_S) +#define IG3_PMAT_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_S 0 +#define IG3_PMAT_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_M RDMA_MASK3(32, 0xF, IG3_PMAT_GLHMC_PEXFOBJSZ_PMPEXFOBJSZ_S) +#define IG3_PMAT_GLHMC_PMATCFG 0x42807140 +#define IG3_PMAT_GLHMC_PMATCFG_RSVD_S 1 +#define IG3_PMAT_GLHMC_PMATCFG_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PMAT_GLHMC_PMATCFG_RSVD_S) +#define IG3_PMAT_GLHMC_PMATCFG_DISABLE_PCIE_CLK_GATING_S 0 +#define IG3_PMAT_GLHMC_PMATCFG_DISABLE_PCIE_CLK_GATING_M RDMA_BIT2(32, IG3_PMAT_GLHMC_PMATCFG_DISABLE_PCIE_CLK_GATING_S) +#define IG3_PMAT_GLHMC_SDCMD 0x428071A8 +#define IG3_PMAT_GLHMC_SDCMD_PMSDWR_S 31 +#define IG3_PMAT_GLHMC_SDCMD_PMSDWR_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SDCMD_PMSDWR_S) +#define IG3_PMAT_GLHMC_SDCMD_RSVD_S 15 +#define IG3_PMAT_GLHMC_SDCMD_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PMAT_GLHMC_SDCMD_RSVD_S) +#define IG3_PMAT_GLHMC_SDCMD_PMSDIDX_S 0 +#define IG3_PMAT_GLHMC_SDCMD_PMSDIDX_M RDMA_MASK3(32, 0x7FFF, IG3_PMAT_GLHMC_SDCMD_PMSDIDX_S) +#define IG3_PMAT_GLHMC_SDDATA0 0x428071AC +#define IG3_PMAT_GLHMC_SDDATA0_PMSDDATALOW_S 12 +#define IG3_PMAT_GLHMC_SDDATA0_PMSDDATALOW_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_GLHMC_SDDATA0_PMSDDATALOW_S) +#define IG3_PMAT_GLHMC_SDDATA0_PMSDBPCOUNT_S 2 +#define IG3_PMAT_GLHMC_SDDATA0_PMSDBPCOUNT_M RDMA_MASK3(32, 0x3FF, IG3_PMAT_GLHMC_SDDATA0_PMSDBPCOUNT_S) +#define IG3_PMAT_GLHMC_SDDATA0_PMSDTYPE_S 1 +#define IG3_PMAT_GLHMC_SDDATA0_PMSDTYPE_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SDDATA0_PMSDTYPE_S) +#define IG3_PMAT_GLHMC_SDDATA0_PMSDVALID_S 0 +#define IG3_PMAT_GLHMC_SDDATA0_PMSDVALID_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SDDATA0_PMSDVALID_S) +#define IG3_PMAT_GLHMC_SDDATA1 0x428071B0 +#define IG3_PMAT_GLHMC_SDDATA1_PMSDDATAHIGH_S 0 +#define IG3_PMAT_GLHMC_SDDATA1_PMSDDATAHIGH_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_GLHMC_SDDATA1_PMSDDATAHIGH_S) +#define IG3_PMAT_GLHMC_SDDATA2 0x428071B4 +#define IG3_PMAT_GLHMC_SDDATA2_RSVD0_S 25 +#define IG3_PMAT_GLHMC_SDDATA2_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PMAT_GLHMC_SDDATA2_RSVD0_S) +#define IG3_PMAT_GLHMC_SDDATA2_PMSDHOSTID_S 22 +#define IG3_PMAT_GLHMC_SDDATA2_PMSDHOSTID_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_SDDATA2_PMSDHOSTID_S) +#define IG3_PMAT_GLHMC_SDDATA2_PMF_TYPE_S 20 +#define IG3_PMAT_GLHMC_SDDATA2_PMF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PMAT_GLHMC_SDDATA2_PMF_TYPE_S) +#define IG3_PMAT_GLHMC_SDDATA2_VF_S 10 +#define IG3_PMAT_GLHMC_SDDATA2_VF_M RDMA_MASK3(32, 0x3FF, IG3_PMAT_GLHMC_SDDATA2_VF_S) +#define IG3_PMAT_GLHMC_SDDATA2_PF_S 4 +#define IG3_PMAT_GLHMC_SDDATA2_PF_M RDMA_MASK3(32, 0x3F, IG3_PMAT_GLHMC_SDDATA2_PF_S) +#define IG3_PMAT_GLHMC_SDDATA2_PMCHAN_S 3 +#define IG3_PMAT_GLHMC_SDDATA2_PMCHAN_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SDDATA2_PMCHAN_S) +#define IG3_PMAT_GLHMC_SDDATA2_PMSDMEM_S 0 +#define IG3_PMAT_GLHMC_SDDATA2_PMSDMEM_M RDMA_MASK3(32, 0x7, IG3_PMAT_GLHMC_SDDATA2_PMSDMEM_S) +#define IG3_PMAT_GLHMC_SDMAX 0x42807218 +#define IG3_PMAT_GLHMC_SDMAX_RSVD_S 16 +#define IG3_PMAT_GLHMC_SDMAX_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PMAT_GLHMC_SDMAX_RSVD_S) +#define IG3_PMAT_GLHMC_SDMAX_GLHMC_SDMAX_S 0 +#define IG3_PMAT_GLHMC_SDMAX_GLHMC_SDMAX_M RDMA_MASK3(32, 0xFFFF, IG3_PMAT_GLHMC_SDMAX_GLHMC_SDMAX_S) +#define IG3_PMAT_GLHMC_SDPARTTABLE(_i) 0x42804000 + ((_i) * 4) /* _i=0...3071 */ +#define IG3_PMAT_GLHMC_SDPARTTABLE_MAX_INDEX_I 3071 +#define IG3_PMAT_GLHMC_SDPARTTABLE_SDPTVALID_S 31 +#define IG3_PMAT_GLHMC_SDPARTTABLE_SDPTVALID_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SDPARTTABLE_SDPTVALID_S) +#define IG3_PMAT_GLHMC_SDPARTTABLE_RSVD_S 30 +#define IG3_PMAT_GLHMC_SDPARTTABLE_RSVD_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SDPARTTABLE_RSVD_S) +#define IG3_PMAT_GLHMC_SDPARTTABLE_SDPTPF_S 24 +#define IG3_PMAT_GLHMC_SDPARTTABLE_SDPTPF_M RDMA_MASK3(32, 0x3F, IG3_PMAT_GLHMC_SDPARTTABLE_SDPTPF_S) +#define IG3_PMAT_GLHMC_SDPARTTABLE_SDPTPMF_S 12 +#define IG3_PMAT_GLHMC_SDPARTTABLE_SDPTPMF_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_GLHMC_SDPARTTABLE_SDPTPMF_S) +#define IG3_PMAT_GLHMC_SDPARTTABLE_SDPTBASE_S 0 +#define IG3_PMAT_GLHMC_SDPARTTABLE_SDPTBASE_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_GLHMC_SDPARTTABLE_SDPTBASE_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD 0x428071BC +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKVLD_S 31 +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKVLD_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKVLD_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_RSVD1_S 30 +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_RSVD1_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SPDT_LKUP_CMD_RSVD1_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKPF_S 24 +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKPF_M RDMA_MASK3(32, 0x3F, IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKPF_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKPMF_S 12 +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKPMF_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKPMF_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKBASE_S 0 +#define IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKBASE_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_GLHMC_SPDT_LKUP_CMD_SDPTLKBASE_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS 0x428071C0 +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_RSVD1_S 16 +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_RSVD1_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_SDPTINDEX_S 4 +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_SDPTINDEX_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_SDPTINDEX_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_RSVD0_S 2 +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_RSVD0_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_HIT_S 1 +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_HIT_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_HIT_S) +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_VLD_S 0 +#define IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_VLD_M RDMA_BIT2(32, IG3_PMAT_GLHMC_SPDT_LKUP_STATUS_VLD_S) +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO 0x42807204 +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_RSVD0_S 12 +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_RSVD0_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_GLPE_PMAT_XLR_ZERO_RSVD0_S) +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_PMF_S 0 +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_GLPE_PMAT_XLR_ZERO_PMF_S) +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS 0x42807208 +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS_DONE_S 31 +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS_DONE_M RDMA_BIT2(32, IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS_DONE_S) +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS_RSVD0_S 12 +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS_RSVD0_M RDMA_MASK3(32, 0x7FFFF, IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS_RSVD0_S) +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS_PMF_S 0 +#define IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_GLPE_PMAT_XLR_ZERO_STATUS_PMF_S) +#define IG3_PMAT_PFHMC_ERRORDATA(_i) 0x42800100 + ((_i) * 4) /* _i=0...15 */ +#define IG3_PMAT_PFHMC_ERRORDATA_MAX_INDEX_I 15 +#define IG3_PMAT_PFHMC_ERRORDATA_RSVD_S 30 +#define IG3_PMAT_PFHMC_ERRORDATA_RSVD_M RDMA_MASK3(32, 0x3, IG3_PMAT_PFHMC_ERRORDATA_RSVD_S) +#define IG3_PMAT_PFHMC_ERRORDATA_HMC_ERROR_DATA_S 0 +#define IG3_PMAT_PFHMC_ERRORDATA_HMC_ERROR_DATA_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PMAT_PFHMC_ERRORDATA_HMC_ERROR_DATA_S) +#define IG3_PMAT_PFHMC_ERRORINFO(_i) 0x42800000 + ((_i) * 4) /* _i=0...15 */ +#define IG3_PMAT_PFHMC_ERRORINFO_MAX_INDEX_I 15 +#define IG3_PMAT_PFHMC_ERRORINFO_ERROR_DETECTED_S 31 +#define IG3_PMAT_PFHMC_ERRORINFO_ERROR_DETECTED_M RDMA_BIT2(32, IG3_PMAT_PFHMC_ERRORINFO_ERROR_DETECTED_S) +#define IG3_PMAT_PFHMC_ERRORINFO_RSVD2_S 25 +#define IG3_PMAT_PFHMC_ERRORINFO_RSVD2_M RDMA_MASK3(32, 0x3F, IG3_PMAT_PFHMC_ERRORINFO_RSVD2_S) +#define IG3_PMAT_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_S 20 +#define IG3_PMAT_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PFHMC_ERRORINFO_HMC_OBJECT_TYPE_S) +#define IG3_PMAT_PFHMC_ERRORINFO_HMC_ERROR_TYPE_S 16 +#define IG3_PMAT_PFHMC_ERRORINFO_HMC_ERROR_TYPE_M RDMA_MASK3(32, 0xF, IG3_PMAT_PFHMC_ERRORINFO_HMC_ERROR_TYPE_S) +#define IG3_PMAT_PFHMC_ERRORINFO_RSVD1_S 13 +#define IG3_PMAT_PFHMC_ERRORINFO_RSVD1_M RDMA_MASK3(32, 0x7, IG3_PMAT_PFHMC_ERRORINFO_RSVD1_S) +#define IG3_PMAT_PFHMC_ERRORINFO_PMF_ISVF_S 12 +#define IG3_PMAT_PFHMC_ERRORINFO_PMF_ISVF_M RDMA_BIT2(32, IG3_PMAT_PFHMC_ERRORINFO_PMF_ISVF_S) +#define IG3_PMAT_PFHMC_ERRORINFO_PMF_INDEX_S 0 +#define IG3_PMAT_PFHMC_ERRORINFO_PMF_INDEX_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_PFHMC_ERRORINFO_PMF_INDEX_S) +#define IG3_PMAT_PMAT_ECC_COR_ERR 0x4285B09C +#define IG3_PMAT_PMAT_ECC_COR_ERR_RSVD_S 12 +#define IG3_PMAT_PMAT_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_PMAT_ECC_COR_ERR_RSVD_S) +#define IG3_PMAT_PMAT_ECC_COR_ERR_CNT_S 0 +#define IG3_PMAT_PMAT_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_PMAT_ECC_COR_ERR_CNT_S) +#define IG3_PMAT_PMAT_ECC_UNCOR_ERR 0x4285B098 +#define IG3_PMAT_PMAT_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PMAT_PMAT_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_PMAT_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PMAT_PMAT_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PMAT_PMAT_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_PMAT_ECC_UNCOR_ERR_CNT_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG 0x4285B068 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS 0x4285B06C +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CMPL_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG 0x4285B070 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS 0x4285B074 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA0_CQ_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG 0x4285B078 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS 0x4285B07C +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CMPL_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG 0x4285B080 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS 0x4285B084 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_LOCA1_CQ_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG 0x4285B028 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS 0x4285B02C +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BASE_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG 0x4285B030 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS 0x4285B034 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BNDS_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG 0x4285B040 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS 0x4285B044 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_LNK_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG 0x4285B038 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS 0x4285B03C +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_OBJ_BP_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG 0x4285B088 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_PASID_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PASID_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_PASID_MEM_STATUS 0x4285B08C +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PASID_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_PASID_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_PASID_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_PASID_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_PASID_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG 0x4285B058 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS 0x4285B05C +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CMPL_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_PCIE_CMP_NRDY_CNT 0x42807200 +#define IG3_PMAT_PMAT_PCIE_CMP_NRDY_CNT_PCIECMPNRDYCNT_S 0 +#define IG3_PMAT_PMAT_PCIE_CMP_NRDY_CNT_PCIECMPNRDYCNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_PMAT_PCIE_CMP_NRDY_CNT_PCIECMPNRDYCNT_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG 0x4285B060 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS 0x4285B064 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_CQ_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG 0x4285B048 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS 0x4285B04C +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_DAT_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG 0x4285B050 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS 0x4285B054 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_PCIE_NAK_HDR_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG 0x4285B020 +#define IG3_PMAT_PMAT_ST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_ST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_ST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_ST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_ST_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_ST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_ST_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_ST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_ST_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_ST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_ST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_RSVD1_S 10 +#define IG3_PMAT_PMAT_ST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_ST_MEM_CFG_RSVD1_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_ST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_ST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_ST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_ST_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_ST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_ST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_ST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_ST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_ST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_ST_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_ST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_ST_MEM_STATUS 0x4285B024 +#define IG3_PMAT_PMAT_ST_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_ST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_ST_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_ST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_ST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_ST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_ST_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_ST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_ST_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_ST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_ST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_ST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_ST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_ST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_ST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_ST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_ST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_ST_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG 0x4285B090 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RSVD3_S 20 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_PMAT_TCAM_MEM_CFG_RSVD3_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RM_S 16 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_PMAT_TCAM_MEM_CFG_RM_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RSVD2_S 14 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_TCAM_MEM_CFG_RSVD2_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RME_S 12 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_RME_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_UPDATE_DISABLE_S 11 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_UPDATE_DISABLE_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_UPDATE_DISABLE_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_CHECK_ERR_DISABLE_S 10 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_CHECK_ERR_DISABLE_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_CHECK_ERR_DISABLE_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ERR_CNT_S 9 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_ERR_CNT_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_FIX_CNT_S 8 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_FIX_CNT_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RSVD0_S 6 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_TCAM_MEM_CFG_RSVD0_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_MASK_INT_S 5 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_MASK_INT_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_LS_BYPASS_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_LS_FORCE_S 3 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_LS_FORCE_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_EN_S 0 +#define IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_CFG_ECC_EN_S) +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS 0x4285B094 +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_RSVD1_S 30 +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_PMAT_TCAM_MEM_STATUS_RSVD1_S) +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_PMAT_TCAM_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_RSVD0_S 4 +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_PMAT_TCAM_MEM_STATUS_RSVD0_S) +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_STATUS_INIT_DONE_S) +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_STATUS_ECC_FIX_S) +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_PMAT_TCAM_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_PMAT_TCAM_MEM_STATUS_ECC_ERR_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_COUNT 0x42880038 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_CMD 0x4288004C +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_DATA_H 0x42880058 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_DATA_L 0x42880054 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_PTR 0x42880050 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_CMD 0x4288003C +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_DATA_H 0x42880048 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_DATA_L 0x42880044 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_PTR 0x42880040 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL 0x42880000 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD1_S 25 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD2_S 17 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD2_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD3_S 9 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD3_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_BYPASS_S 8 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_BYPASS_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD4_S 1 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_RSVD4_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_COR_ERR 0x42880068 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_UNCOR_ERR 0x42880064 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG 0x4288000C +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG 0x42880010 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG_MODE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_CFG_MODE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_MASK 0x42880018 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_MASK_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_PATTERN 0x42880014 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG 0x42880004 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS 0x42880008 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_RSVD2_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TIMESTAMP 0x42880030 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TIMESTAMP_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TIMESTAMP_ROLLOVER 0x42880034 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG 0x4288005C +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS 0x42880060 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG 0x4288001C +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_CFG_MODE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_COUNT 0x42880028 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_MASK 0x42880024 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_MASK_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_PATTERN 0x42880020 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_TIMESTAMP 0x4288002C +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PMAT_DTM_GLPE_PMAT_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PDOC_GLPDOC_CACHESIZE 0x42880480 +#define IG3_PDOC_GLPDOC_CACHESIZE_RSVD_S 24 +#define IG3_PDOC_GLPDOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHESIZE_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHESIZE_WAYS_S 20 +#define IG3_PDOC_GLPDOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHESIZE_WAYS_S) +#define IG3_PDOC_GLPDOC_CACHESIZE_SETS_S 8 +#define IG3_PDOC_GLPDOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_CACHESIZE_SETS_S) +#define IG3_PDOC_GLPDOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_PDOC_GLPDOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHESIZE_WORD_SIZE_S) +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL 0x4288050C +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_DATA 0x42880510 +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG 0x428804C4 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS 0x428804C8 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL 0x42880514 +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_DATA 0x42880518 +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG 0x428804CC +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS 0x428804D0 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL 0x4288051C +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_DATA 0x42880520 +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG 0x428804D4 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS 0x428804D8 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL 0x42880524 +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_DATA 0x42880528 +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG 0x428804DC +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS 0x428804E0 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL 0x4288052C +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_DATA 0x42880530 +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG 0x428804E4 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS 0x428804E8 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL 0x42880534 +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_DATA 0x42880538 +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG 0x428804EC +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS 0x428804F0 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL 0x4288053C +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_DATA 0x42880540 +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG 0x428804F4 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS 0x428804F8 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL 0x42880544 +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_DATA 0x42880548 +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG 0x428804FC +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS 0x42880500 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_CACHE_CTRL 0x42880400 +#define IG3_PDOC_GLPDOC_CACHE_CTRL_RSVD_S 2 +#define IG3_PDOC_GLPDOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PDOC_GLPDOC_CACHE_CTRL_RSVD_S) +#define IG3_PDOC_GLPDOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_PDOC_GLPDOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_PDOC_GLPDOC_CECC_ERR 0x42880470 +#define IG3_PDOC_GLPDOC_CECC_ERR_RSVD1_S 28 +#define IG3_PDOC_GLPDOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CECC_ERR_RSVD1_S) +#define IG3_PDOC_GLPDOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PDOC_GLPDOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CECC_ERR_RSVD0_S 12 +#define IG3_PDOC_GLPDOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_CECC_ERR_RSVD0_S) +#define IG3_PDOC_GLPDOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PDOC_GLPDOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_CSTATELKUP_CFG 0x42880478 +#define IG3_PDOC_GLPDOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_PDOC_GLPDOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PDOC_GLPDOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_PDOC_GLPDOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_PDOC_GLPDOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_PDOC_GLPDOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_PDOC_GLPDOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_PDOC_GLPDOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_PDOC_GLPDOC_DPC_COMP 0x42880488 +#define IG3_PDOC_GLPDOC_DPC_COMP_RSVD_S 13 +#define IG3_PDOC_GLPDOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PDOC_GLPDOC_DPC_COMP_RSVD_S) +#define IG3_PDOC_GLPDOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_PDOC_GLPDOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_PDOC_GLPDOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_PDOC_GLPDOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PDOC_GLPDOC_DPC_COMP_COMP_FNUM_S) +#define IG3_PDOC_GLPDOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_PDOC_GLPDOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DPC_COMP_COMP_VALID_S) +#define IG3_PDOC_GLPDOC_DPC_REQ 0x42880484 +#define IG3_PDOC_GLPDOC_DPC_REQ_RSVD_S 12 +#define IG3_PDOC_GLPDOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PDOC_GLPDOC_DPC_REQ_RSVD_S) +#define IG3_PDOC_GLPDOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_PDOC_GLPDOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_PDOC_GLPDOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_PDOC_GLPDOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PDOC_GLPDOC_DPC_REQ_REQ_FNUM_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_COUNT 0x428805B8 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_CMD 0x428805CC +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_DATA_H 0x428805D8 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_DATA_L 0x428805D4 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_PTR 0x428805D0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_CMD 0x428805BC +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_DATA_H 0x428805C8 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_DATA_L 0x428805C4 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_PTR 0x428805C0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PDOC_GLPDOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_CONTROL 0x42880580 +#define IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PDOC_GLPDOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD2_S) +#define IG3_PDOC_GLPDOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PDOC_GLPDOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD3_S) +#define IG3_PDOC_GLPDOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_PDOC_GLPDOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_CONTROL_BYPASS_S) +#define IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_DTM_CONTROL_RSVD4_S) +#define IG3_PDOC_GLPDOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PDOC_GLPDOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PDOC_GLPDOC_DTM_ECC_COR_ERR 0x428805E8 +#define IG3_PDOC_GLPDOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PDOC_GLPDOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PDOC_GLPDOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PDOC_GLPDOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PDOC_GLPDOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_DTM_ECC_UNCOR_ERR 0x428805E4 +#define IG3_PDOC_GLPDOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PDOC_GLPDOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PDOC_GLPDOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PDOC_GLPDOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PDOC_GLPDOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_DTM_GROUP_CFG 0x4288058C +#define IG3_PDOC_GLPDOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PDOC_GLPDOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PDOC_GLPDOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PDOC_GLPDOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PDOC_GLPDOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PDOC_GLPDOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PDOC_GLPDOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PDOC_GLPDOC_DTM_LOG_CFG 0x42880590 +#define IG3_PDOC_GLPDOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PDOC_GLPDOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PDOC_GLPDOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PDOC_GLPDOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PDOC_GLPDOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PDOC_GLPDOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_PDOC_GLPDOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_DTM_LOG_CFG_MODE_S) +#define IG3_PDOC_GLPDOC_DTM_LOG_MASK 0x42880598 +#define IG3_PDOC_GLPDOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_LOG_MASK_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_LOG_PATTERN 0x42880594 +#define IG3_PDOC_GLPDOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG 0x42880584 +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PDOC_GLPDOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PDOC_GLPDOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PDOC_GLPDOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_STS 0x42880588 +#define IG3_PDOC_GLPDOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PDOC_GLPDOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PDOC_GLPDOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PDOC_GLPDOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PDOC_GLPDOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_PDOC_GLPDOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PDOC_GLPDOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PDOC_GLPDOC_DTM_TIMESTAMP 0x428805B0 +#define IG3_PDOC_GLPDOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_TIMESTAMP_ROLLOVER 0x428805B4 +#define IG3_PDOC_GLPDOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG 0x428805DC +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS 0x428805E0 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG 0x4288059C +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PDOC_GLPDOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_DTM_TRIG_CFG_MODE_S) +#define IG3_PDOC_GLPDOC_DTM_TRIG_COUNT 0x428805A8 +#define IG3_PDOC_GLPDOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_TRIG_MASK 0x428805A4 +#define IG3_PDOC_GLPDOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_TRIG_PATTERN 0x428805A0 +#define IG3_PDOC_GLPDOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PDOC_GLPDOC_DTM_TRIG_TIMESTAMP 0x428805AC +#define IG3_PDOC_GLPDOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PDOC_GLPDOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PDOC_GLPDOC_ECC_CTL 0x4288046C +#define IG3_PDOC_GLPDOC_ECC_CTL_RSVD_S 8 +#define IG3_PDOC_GLPDOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_ECC_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_PDOC_GLPDOC_ERRDATA0 0x4288045C +#define IG3_PDOC_GLPDOC_ERRDATA0_RSVD1_S 31 +#define IG3_PDOC_GLPDOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ERRDATA0_RSVD1_S) +#define IG3_PDOC_GLPDOC_ERRDATA0_PF_NUM_S 25 +#define IG3_PDOC_GLPDOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PDOC_GLPDOC_ERRDATA0_PF_NUM_S) +#define IG3_PDOC_GLPDOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_PDOC_GLPDOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PDOC_GLPDOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_PDOC_GLPDOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_PDOC_GLPDOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_PDOC_GLPDOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_PDOC_GLPDOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_PDOC_GLPDOC_ERRDATA0_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_ERRDATA0_RSVD0_S) +#define IG3_PDOC_GLPDOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_PDOC_GLPDOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_PDOC_GLPDOC_ERRDATA0_ERROR_CODE_S) +#define IG3_PDOC_GLPDOC_ERRDATA1 0x42880460 +#define IG3_PDOC_GLPDOC_ERRDATA1_RSVD_S 28 +#define IG3_PDOC_GLPDOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_ERRDATA1_RSVD_S) +#define IG3_PDOC_GLPDOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_PDOC_GLPDOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PDOC_GLPDOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_PDOC_GLPDOC_ERRDATA2 0x42880464 +#define IG3_PDOC_GLPDOC_ERRDATA2_RSVD_S 23 +#define IG3_PDOC_GLPDOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PDOC_GLPDOC_ERRDATA2_RSVD_S) +#define IG3_PDOC_GLPDOC_ERRDATA2_OPTYPE_S 20 +#define IG3_PDOC_GLPDOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_PDOC_GLPDOC_ERRDATA2_OPTYPE_S) +#define IG3_PDOC_GLPDOC_ERRDATA2_OFFSET_S 7 +#define IG3_PDOC_GLPDOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_PDOC_GLPDOC_ERRDATA2_OFFSET_S) +#define IG3_PDOC_GLPDOC_ERRDATA2_LENGTH_S 0 +#define IG3_PDOC_GLPDOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_ERRDATA2_LENGTH_S) +#define IG3_PDOC_GLPDOC_ERRDATA3 0x42880468 +#define IG3_PDOC_GLPDOC_ERRDATA3_RSVD_S 15 +#define IG3_PDOC_GLPDOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_PDOC_GLPDOC_ERRDATA3_RSVD_S) +#define IG3_PDOC_GLPDOC_ERRDATA3_TAG_S 0 +#define IG3_PDOC_GLPDOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_PDOC_GLPDOC_ERRDATA3_TAG_S) +#define IG3_PDOC_GLPDOC_ERRINFO 0x42880458 +#define IG3_PDOC_GLPDOC_ERRINFO_RSVD1_S 16 +#define IG3_PDOC_GLPDOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PDOC_GLPDOC_ERRINFO_RSVD1_S) +#define IG3_PDOC_GLPDOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_PDOC_GLPDOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_ERRINFO_ERROR_CNT_S) +#define IG3_PDOC_GLPDOC_ERRINFO_RSVD0_S 1 +#define IG3_PDOC_GLPDOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_ERRINFO_RSVD0_S) +#define IG3_PDOC_GLPDOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_PDOC_GLPDOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_ERRINFO_ERROR_VALID_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG 0x428804BC +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS 0x428804C0 +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG 0x428804B4 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_FILL_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS 0x428804B8 +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_MAXOSR 0x42880474 +#define IG3_PDOC_GLPDOC_MAXOSR_RSVD1_S 11 +#define IG3_PDOC_GLPDOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0x1FFFFF, IG3_PDOC_GLPDOC_MAXOSR_RSVD1_S) +#define IG3_PDOC_GLPDOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 10 +#define IG3_PDOC_GLPDOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_PDOC_GLPDOC_MAXOSR_RSVD0_S 8 +#define IG3_PDOC_GLPDOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_MAXOSR_RSVD0_S) +#define IG3_PDOC_GLPDOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_PDOC_GLPDOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_PDOC_GLPDOC_MEM_ECC_COR_ERR 0x42880558 +#define IG3_PDOC_GLPDOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PDOC_GLPDOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PDOC_GLPDOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_PDOC_GLPDOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_PDOC_GLPDOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_MEM_ECC_UNCOR_ERR 0x42880554 +#define IG3_PDOC_GLPDOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PDOC_GLPDOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PDOC_GLPDOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PDOC_GLPDOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PDOC_GLPDOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PDOC_GLPDOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL 0x4288054C +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_PLIST_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_PLIST_DBG_DATA 0x42880550 +#define IG3_PDOC_GLPDOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG 0x428804AC +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS 0x428804B0 +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_PMATINV_CFG 0x4288047C +#define IG3_PDOC_GLPDOC_PMATINV_CFG_RSVD_S 6 +#define IG3_PDOC_GLPDOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_PDOC_GLPDOC_PMATINV_CFG_RSVD_S) +#define IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_PDOC_GLPDOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_PDOC_GLPDOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PDOC_GLPDOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_PDOC_GLPDOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_PDOC_GLPDOC_STAT_CTL 0x42880404 +#define IG3_PDOC_GLPDOC_STAT_CTL_RSVD_S 5 +#define IG3_PDOC_GLPDOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PDOC_GLPDOC_STAT_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_PDOC_GLPDOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_PDOC_GLPDOC_STAT_FENCING_TIME_HI 0x4288044C +#define IG3_PDOC_GLPDOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_STAT_FENCING_TIME_LO 0x42880448 +#define IG3_PDOC_GLPDOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_ENTRIES 0x4288042C +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_LIST_DEPTH 0x42880434 +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_PDOC_GLPDOC_STAT_MAX_VIRT_PENDING_LISTS 0x42880430 +#define IG3_PDOC_GLPDOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_PDOC_GLPDOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_PDOC_GLPDOC_STAT_OBJ_CNT 0x42880408 +#define IG3_PDOC_GLPDOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_PDOC_GLPDOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_PDOC_GLPDOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PDOC_GLPDOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_HI 0x42880444 +#define IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_LO 0x42880440 +#define IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_HI 0x42880420 +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_LO 0x4288041C +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_HI 0x42880428 +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_LO 0x42880424 +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_STAT_RD_HIT_HI 0x42880410 +#define IG3_PDOC_GLPDOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_STAT_RD_HIT_LO 0x4288040C +#define IG3_PDOC_GLPDOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_STAT_RD_MISS_HI 0x42880418 +#define IG3_PDOC_GLPDOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_STAT_RD_MISS_LO 0x42880414 +#define IG3_PDOC_GLPDOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_HI 0x42880454 +#define IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_LO 0x42880450 +#define IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_HI 0x4288043C +#define IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_LO 0x42880438 +#define IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL 0x42880504 +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_DBG_CTL_DONE_S) +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_TAG_DBG_CTL_RSVD_S) +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_PDOC_GLPDOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_TAG_DBG_CTL_ADR_S) +#define IG3_PDOC_GLPDOC_TAG_DBG_DATA 0x42880508 +#define IG3_PDOC_GLPDOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_PDOC_GLPDOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG 0x4288049C +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_TAG_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS 0x428804A0 +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HI 0x42880490 +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_HI 0x42880498 +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_LO 0x42880494 +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_TOTAL_TAG_LO 0x4288048C +#define IG3_PDOC_GLPDOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_PDOC_GLPDOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PDOC_GLPDOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG 0x428804A4 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RM_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RME_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS 0x428804A8 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PDOC_GLPDOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_ARPTBLE_OBJOFST 0x4290007C +#define IG3_PBLOC0_GLPBLOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_PBLOC0_GLPBLOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PBLOC0_GLPBLOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PBLOC0_GLPBLOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC0_GLPBLOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PBLOC0_GLPBLOC_CACHESIZE 0x429000AC +#define IG3_PBLOC0_GLPBLOC_CACHESIZE_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHESIZE_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHESIZE_WAYS_S 20 +#define IG3_PBLOC0_GLPBLOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHESIZE_WAYS_S) +#define IG3_PBLOC0_GLPBLOC_CACHESIZE_SETS_S 8 +#define IG3_PBLOC0_GLPBLOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_CACHESIZE_SETS_S) +#define IG3_PBLOC0_GLPBLOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHESIZE_WORD_SIZE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL 0x42900138 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_DATA 0x4290013C +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG 0x429000F0 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS 0x429000F4 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL 0x42900140 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_DATA 0x42900144 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG 0x429000F8 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS 0x429000FC +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL 0x42900148 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_DATA 0x4290014C +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG 0x42900100 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS 0x42900104 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL 0x42900150 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_DATA 0x42900154 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG 0x42900108 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS 0x4290010C +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL 0x42900158 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_DATA 0x4290015C +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG 0x42900110 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS 0x42900114 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL 0x42900160 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_DATA 0x42900164 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG 0x42900118 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS 0x4290011C +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL 0x42900168 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_DATA 0x4290016C +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG 0x42900120 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS 0x42900124 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL 0x42900170 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_DATA 0x42900174 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG 0x42900128 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS 0x4290012C +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_CTRL 0x42900000 +#define IG3_PBLOC0_GLPBLOC_CACHE_CTRL_RSVD_S 2 +#define IG3_PBLOC0_GLPBLOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PBLOC0_GLPBLOC_CACHE_CTRL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_PBLOC0_GLPBLOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_PBLOC0_GLPBLOC_CECC_ERR 0x4290009C +#define IG3_PBLOC0_GLPBLOC_CECC_ERR_RSVD1_S 28 +#define IG3_PBLOC0_GLPBLOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CECC_ERR_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PBLOC0_GLPBLOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CECC_ERR_RSVD0_S 12 +#define IG3_PBLOC0_GLPBLOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_CECC_ERR_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PBLOC0_GLPBLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG 0x429000A4 +#define IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_PBLOC0_GLPBLOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_PBLOC0_GLPBLOC_DPC_COMP 0x429000B4 +#define IG3_PBLOC0_GLPBLOC_DPC_COMP_RSVD_S 13 +#define IG3_PBLOC0_GLPBLOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PBLOC0_GLPBLOC_DPC_COMP_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_PBLOC0_GLPBLOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_PBLOC0_GLPBLOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_PBLOC0_GLPBLOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC0_GLPBLOC_DPC_COMP_COMP_FNUM_S) +#define IG3_PBLOC0_GLPBLOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_PBLOC0_GLPBLOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DPC_COMP_COMP_VALID_S) +#define IG3_PBLOC0_GLPBLOC_DPC_REQ 0x429000B0 +#define IG3_PBLOC0_GLPBLOC_DPC_REQ_RSVD_S 12 +#define IG3_PBLOC0_GLPBLOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC0_GLPBLOC_DPC_REQ_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_PBLOC0_GLPBLOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_PBLOC0_GLPBLOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_PBLOC0_GLPBLOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC0_GLPBLOC_DPC_REQ_REQ_FNUM_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_COUNT 0x42900238 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_CMD 0x4290024C +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_DATA_H 0x42900258 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_DATA_L 0x42900254 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_PTR 0x42900250 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_CMD 0x4290023C +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_DATA_H 0x42900248 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_DATA_L 0x42900244 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_PTR 0x42900240 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC0_GLPBLOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL 0x42900200 +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_CONTROL_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_DTM_CONTROL_RSVD4_S) +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_COR_ERR 0x42900268 +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC0_GLPBLOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_UNCOR_ERR 0x42900264 +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC0_GLPBLOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG 0x4290020C +#define IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG 0x42900210 +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_DTM_LOG_CFG_MODE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_MASK 0x42900218 +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_LOG_MASK_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_PATTERN 0x42900214 +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG 0x42900204 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS 0x42900208 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TIMESTAMP 0x42900230 +#define IG3_PBLOC0_GLPBLOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TIMESTAMP_ROLLOVER 0x42900234 +#define IG3_PBLOC0_GLPBLOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG 0x4290025C +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS 0x42900260 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG 0x4290021C +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_DTM_TRIG_CFG_MODE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_COUNT 0x42900228 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_MASK 0x42900224 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_PATTERN 0x42900220 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_TIMESTAMP 0x4290022C +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PBLOC0_GLPBLOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PBLOC0_GLPBLOC_ECC_CTL 0x42900094 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_RSVD_S 8 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_ECC_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA0 0x42900084 +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_RSVD1_S 31 +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ERRDATA0_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_PF_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PBLOC0_GLPBLOC_ERRDATA0_PF_NUM_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC0_GLPBLOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_ERRDATA0_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_PBLOC0_GLPBLOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_PBLOC0_GLPBLOC_ERRDATA0_ERROR_CODE_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA1 0x42900088 +#define IG3_PBLOC0_GLPBLOC_ERRDATA1_RSVD_S 28 +#define IG3_PBLOC0_GLPBLOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_ERRDATA1_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_PBLOC0_GLPBLOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PBLOC0_GLPBLOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA2 0x4290008C +#define IG3_PBLOC0_GLPBLOC_ERRDATA2_RSVD_S 23 +#define IG3_PBLOC0_GLPBLOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PBLOC0_GLPBLOC_ERRDATA2_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA2_OPTYPE_S 20 +#define IG3_PBLOC0_GLPBLOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_PBLOC0_GLPBLOC_ERRDATA2_OPTYPE_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA2_OFFSET_S 7 +#define IG3_PBLOC0_GLPBLOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_PBLOC0_GLPBLOC_ERRDATA2_OFFSET_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA2_LENGTH_S 0 +#define IG3_PBLOC0_GLPBLOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_ERRDATA2_LENGTH_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA3 0x42900090 +#define IG3_PBLOC0_GLPBLOC_ERRDATA3_RSVD_S 15 +#define IG3_PBLOC0_GLPBLOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_PBLOC0_GLPBLOC_ERRDATA3_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_ERRDATA3_TAG_S 0 +#define IG3_PBLOC0_GLPBLOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_PBLOC0_GLPBLOC_ERRDATA3_TAG_S) +#define IG3_PBLOC0_GLPBLOC_ERRINFO 0x42900080 +#define IG3_PBLOC0_GLPBLOC_ERRINFO_RSVD1_S 16 +#define IG3_PBLOC0_GLPBLOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PBLOC0_GLPBLOC_ERRINFO_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_ERRINFO_ERROR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_ERRINFO_RSVD0_S 1 +#define IG3_PBLOC0_GLPBLOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_ERRINFO_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_PBLOC0_GLPBLOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_ERRINFO_ERROR_VALID_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG 0x429000E8 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS 0x429000EC +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG 0x429000E0 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS 0x429000E4 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_HECC_ERR 0x42900098 +#define IG3_PBLOC0_GLPBLOC_HECC_ERR_RSVD1_S 28 +#define IG3_PBLOC0_GLPBLOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_HECC_ERR_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PBLOC0_GLPBLOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_HECC_ERR_RSVD0_S 12 +#define IG3_PBLOC0_GLPBLOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_HECC_ERR_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PBLOC0_GLPBLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_MAXOSR 0x429000A0 +#define IG3_PBLOC0_GLPBLOC_MAXOSR_RSVD1_S 11 +#define IG3_PBLOC0_GLPBLOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0x1FFFFF, IG3_PBLOC0_GLPBLOC_MAXOSR_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 10 +#define IG3_PBLOC0_GLPBLOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_PBLOC0_GLPBLOC_MAXOSR_RSVD0_S 8 +#define IG3_PBLOC0_GLPBLOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_MAXOSR_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_PBLOC0_GLPBLOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_COR_ERR 0x42900184 +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC0_GLPBLOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_UNCOR_ERR 0x42900180 +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC0_GLPBLOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PBLOC0_GLPBLOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC0_GLPBLOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_PBLE_OBJOFST 0x42900078 +#define IG3_PBLOC0_GLPBLOC_PBLE_OBJOFST_RSVD_S 10 +#define IG3_PBLOC0_GLPBLOC_PBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PBLOC0_GLPBLOC_PBLE_OBJOFST_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_PBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PBLOC0_GLPBLOC_PBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC0_GLPBLOC_PBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL 0x42900178 +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_PLIST_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_DATA 0x4290017C +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG 0x429000D8 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS 0x429000DC +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG 0x429000A8 +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_RSVD_S 6 +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_PBLOC0_GLPBLOC_PMATINV_CFG_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_PBLOC0_GLPBLOC_STAT_CTL 0x42900004 +#define IG3_PBLOC0_GLPBLOC_STAT_CTL_RSVD_S 5 +#define IG3_PBLOC0_GLPBLOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PBLOC0_GLPBLOC_STAT_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_HI 0x4290006C +#define IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_LO 0x42900068 +#define IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_ENTRIES 0x4290004C +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH 0x42900054 +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS 0x42900050 +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_OBJ_CNT 0x42900008 +#define IG3_PBLOC0_GLPBLOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_PBLOC0_GLPBLOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PBLOC0_GLPBLOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_HI 0x42900064 +#define IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_LO 0x42900060 +#define IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_HI 0x42900030 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_LO 0x4290002C +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_HI 0x42900038 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_LO 0x42900034 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_HI 0x42900010 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_LO 0x4290000C +#define IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_HI 0x42900018 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_LO 0x42900014 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_HI 0x42900074 +#define IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_LO 0x42900070 +#define IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_HI 0x4290005C +#define IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_LO 0x42900058 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_HI 0x42900040 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_LO 0x4290003C +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_HI 0x42900048 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_LO 0x42900044 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_HI 0x42900020 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_LO 0x4290001C +#define IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_HI 0x42900028 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_LO 0x42900024 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL 0x42900130 +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_DONE_S) +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_TAG_DBG_CTL_ADR_S) +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_DATA 0x42900134 +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC0_GLPBLOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG 0x429000C8 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS 0x429000CC +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HI 0x429000BC +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_HI 0x429000C4 +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_LO 0x429000C0 +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_LO 0x429000B8 +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_PBLOC0_GLPBLOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC0_GLPBLOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG 0x429000D0 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RM_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RME_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS 0x429000D4 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC0_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_ARPTBLE_OBJOFST 0x4290047C +#define IG3_PBLOC1_GLPBLOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_PBLOC1_GLPBLOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PBLOC1_GLPBLOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PBLOC1_GLPBLOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC1_GLPBLOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PBLOC1_GLPBLOC_CACHESIZE 0x429004AC +#define IG3_PBLOC1_GLPBLOC_CACHESIZE_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHESIZE_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHESIZE_WAYS_S 20 +#define IG3_PBLOC1_GLPBLOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHESIZE_WAYS_S) +#define IG3_PBLOC1_GLPBLOC_CACHESIZE_SETS_S 8 +#define IG3_PBLOC1_GLPBLOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_CACHESIZE_SETS_S) +#define IG3_PBLOC1_GLPBLOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHESIZE_WORD_SIZE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL 0x42900538 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_DATA 0x4290053C +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG 0x429004F0 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS 0x429004F4 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL 0x42900540 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_DATA 0x42900544 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG 0x429004F8 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS 0x429004FC +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL 0x42900548 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_DATA 0x4290054C +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG 0x42900500 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS 0x42900504 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL 0x42900550 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_DATA 0x42900554 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG 0x42900508 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS 0x4290050C +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL 0x42900558 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_DATA 0x4290055C +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG 0x42900510 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS 0x42900514 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL 0x42900560 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_DATA 0x42900564 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG 0x42900518 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS 0x4290051C +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL 0x42900568 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_DATA 0x4290056C +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG 0x42900520 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS 0x42900524 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL 0x42900570 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_DATA 0x42900574 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG 0x42900528 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS 0x4290052C +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_CTRL 0x42900400 +#define IG3_PBLOC1_GLPBLOC_CACHE_CTRL_RSVD_S 2 +#define IG3_PBLOC1_GLPBLOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PBLOC1_GLPBLOC_CACHE_CTRL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_PBLOC1_GLPBLOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_PBLOC1_GLPBLOC_CECC_ERR 0x4290049C +#define IG3_PBLOC1_GLPBLOC_CECC_ERR_RSVD1_S 28 +#define IG3_PBLOC1_GLPBLOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CECC_ERR_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PBLOC1_GLPBLOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CECC_ERR_RSVD0_S 12 +#define IG3_PBLOC1_GLPBLOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_CECC_ERR_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PBLOC1_GLPBLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG 0x429004A4 +#define IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_PBLOC1_GLPBLOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_PBLOC1_GLPBLOC_DPC_COMP 0x429004B4 +#define IG3_PBLOC1_GLPBLOC_DPC_COMP_RSVD_S 13 +#define IG3_PBLOC1_GLPBLOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PBLOC1_GLPBLOC_DPC_COMP_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_PBLOC1_GLPBLOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_PBLOC1_GLPBLOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_PBLOC1_GLPBLOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC1_GLPBLOC_DPC_COMP_COMP_FNUM_S) +#define IG3_PBLOC1_GLPBLOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_PBLOC1_GLPBLOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DPC_COMP_COMP_VALID_S) +#define IG3_PBLOC1_GLPBLOC_DPC_REQ 0x429004B0 +#define IG3_PBLOC1_GLPBLOC_DPC_REQ_RSVD_S 12 +#define IG3_PBLOC1_GLPBLOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC1_GLPBLOC_DPC_REQ_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_PBLOC1_GLPBLOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_PBLOC1_GLPBLOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_PBLOC1_GLPBLOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC1_GLPBLOC_DPC_REQ_REQ_FNUM_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_COUNT 0x42900638 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_CMD 0x4290064C +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_DATA_H 0x42900658 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_DATA_L 0x42900654 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_PTR 0x42900650 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_CMD 0x4290063C +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_DATA_H 0x42900648 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_DATA_L 0x42900644 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_PTR 0x42900640 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC1_GLPBLOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL 0x42900600 +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_CONTROL_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_DTM_CONTROL_RSVD4_S) +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_COR_ERR 0x42900668 +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC1_GLPBLOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_UNCOR_ERR 0x42900664 +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC1_GLPBLOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG 0x4290060C +#define IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG 0x42900610 +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_DTM_LOG_CFG_MODE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_MASK 0x42900618 +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_LOG_MASK_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_PATTERN 0x42900614 +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG 0x42900604 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS 0x42900608 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TIMESTAMP 0x42900630 +#define IG3_PBLOC1_GLPBLOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TIMESTAMP_ROLLOVER 0x42900634 +#define IG3_PBLOC1_GLPBLOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG 0x4290065C +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS 0x42900660 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG 0x4290061C +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_DTM_TRIG_CFG_MODE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_COUNT 0x42900628 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_MASK 0x42900624 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_PATTERN 0x42900620 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_TIMESTAMP 0x4290062C +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PBLOC1_GLPBLOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PBLOC1_GLPBLOC_ECC_CTL 0x42900494 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_RSVD_S 8 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_ECC_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA0 0x42900484 +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_RSVD1_S 31 +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ERRDATA0_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_PF_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PBLOC1_GLPBLOC_ERRDATA0_PF_NUM_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC1_GLPBLOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_ERRDATA0_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_PBLOC1_GLPBLOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_PBLOC1_GLPBLOC_ERRDATA0_ERROR_CODE_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA1 0x42900488 +#define IG3_PBLOC1_GLPBLOC_ERRDATA1_RSVD_S 28 +#define IG3_PBLOC1_GLPBLOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_ERRDATA1_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_PBLOC1_GLPBLOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PBLOC1_GLPBLOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA2 0x4290048C +#define IG3_PBLOC1_GLPBLOC_ERRDATA2_RSVD_S 23 +#define IG3_PBLOC1_GLPBLOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PBLOC1_GLPBLOC_ERRDATA2_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA2_OPTYPE_S 20 +#define IG3_PBLOC1_GLPBLOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_PBLOC1_GLPBLOC_ERRDATA2_OPTYPE_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA2_OFFSET_S 7 +#define IG3_PBLOC1_GLPBLOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_PBLOC1_GLPBLOC_ERRDATA2_OFFSET_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA2_LENGTH_S 0 +#define IG3_PBLOC1_GLPBLOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_ERRDATA2_LENGTH_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA3 0x42900490 +#define IG3_PBLOC1_GLPBLOC_ERRDATA3_RSVD_S 15 +#define IG3_PBLOC1_GLPBLOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_PBLOC1_GLPBLOC_ERRDATA3_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_ERRDATA3_TAG_S 0 +#define IG3_PBLOC1_GLPBLOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_PBLOC1_GLPBLOC_ERRDATA3_TAG_S) +#define IG3_PBLOC1_GLPBLOC_ERRINFO 0x42900480 +#define IG3_PBLOC1_GLPBLOC_ERRINFO_RSVD1_S 16 +#define IG3_PBLOC1_GLPBLOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PBLOC1_GLPBLOC_ERRINFO_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_ERRINFO_ERROR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_ERRINFO_RSVD0_S 1 +#define IG3_PBLOC1_GLPBLOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_ERRINFO_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_PBLOC1_GLPBLOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_ERRINFO_ERROR_VALID_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG 0x429004E8 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS 0x429004EC +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG 0x429004E0 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS 0x429004E4 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_HECC_ERR 0x42900498 +#define IG3_PBLOC1_GLPBLOC_HECC_ERR_RSVD1_S 28 +#define IG3_PBLOC1_GLPBLOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_HECC_ERR_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PBLOC1_GLPBLOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_HECC_ERR_RSVD0_S 12 +#define IG3_PBLOC1_GLPBLOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_HECC_ERR_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PBLOC1_GLPBLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_MAXOSR 0x429004A0 +#define IG3_PBLOC1_GLPBLOC_MAXOSR_RSVD1_S 11 +#define IG3_PBLOC1_GLPBLOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0x1FFFFF, IG3_PBLOC1_GLPBLOC_MAXOSR_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 10 +#define IG3_PBLOC1_GLPBLOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_PBLOC1_GLPBLOC_MAXOSR_RSVD0_S 8 +#define IG3_PBLOC1_GLPBLOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_MAXOSR_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_PBLOC1_GLPBLOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_COR_ERR 0x42900584 +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC1_GLPBLOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_UNCOR_ERR 0x42900580 +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PBLOC1_GLPBLOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PBLOC1_GLPBLOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PBLOC1_GLPBLOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_PBLE_OBJOFST 0x42900478 +#define IG3_PBLOC1_GLPBLOC_PBLE_OBJOFST_RSVD_S 10 +#define IG3_PBLOC1_GLPBLOC_PBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PBLOC1_GLPBLOC_PBLE_OBJOFST_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_PBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PBLOC1_GLPBLOC_PBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PBLOC1_GLPBLOC_PBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL 0x42900578 +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_PLIST_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_DATA 0x4290057C +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG 0x429004D8 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS 0x429004DC +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG 0x429004A8 +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_RSVD_S 6 +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_PBLOC1_GLPBLOC_PMATINV_CFG_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_PBLOC1_GLPBLOC_STAT_CTL 0x42900404 +#define IG3_PBLOC1_GLPBLOC_STAT_CTL_RSVD_S 5 +#define IG3_PBLOC1_GLPBLOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PBLOC1_GLPBLOC_STAT_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_HI 0x4290046C +#define IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_LO 0x42900468 +#define IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_ENTRIES 0x4290044C +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH 0x42900454 +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS 0x42900450 +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_OBJ_CNT 0x42900408 +#define IG3_PBLOC1_GLPBLOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_PBLOC1_GLPBLOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PBLOC1_GLPBLOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_HI 0x42900464 +#define IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_LO 0x42900460 +#define IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_HI 0x42900430 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_LO 0x4290042C +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_HI 0x42900438 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_LO 0x42900434 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_HI 0x42900410 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_LO 0x4290040C +#define IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_HI 0x42900418 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_LO 0x42900414 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_HI 0x42900474 +#define IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_LO 0x42900470 +#define IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_HI 0x4290045C +#define IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_LO 0x42900458 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_HI 0x42900440 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_LO 0x4290043C +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_HI 0x42900448 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_LO 0x42900444 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_HI 0x42900420 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_LO 0x4290041C +#define IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_HI 0x42900428 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_LO 0x42900424 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL 0x42900530 +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_DONE_S) +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_TAG_DBG_CTL_ADR_S) +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_DATA 0x42900534 +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_PBLOC1_GLPBLOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG 0x429004C8 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS 0x429004CC +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HI 0x429004BC +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_HI 0x429004C4 +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_LO 0x429004C0 +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_LO 0x429004B8 +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_PBLOC1_GLPBLOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PBLOC1_GLPBLOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG 0x429004D0 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RM_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RME_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS 0x429004D4 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PBLOC1_GLPBLOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_ARPTBLE_OBJOFST 0x42900878 +#define IG3_MSOC_GLMSOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_CACHESIZE 0x429008E0 +#define IG3_MSOC_GLMSOC_CACHESIZE_RSVD_S 24 +#define IG3_MSOC_GLMSOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHESIZE_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHESIZE_WAYS_S 20 +#define IG3_MSOC_GLMSOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHESIZE_WAYS_S) +#define IG3_MSOC_GLMSOC_CACHESIZE_SETS_S 8 +#define IG3_MSOC_GLMSOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLMSOC_CACHESIZE_SETS_S) +#define IG3_MSOC_GLMSOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_MSOC_GLMSOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHESIZE_WORD_SIZE_S) +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL 0x4290096C +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_DATA 0x42900970 +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG 0x42900924 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS 0x42900928 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL 0x42900974 +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_DATA 0x42900978 +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG 0x4290092C +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS 0x42900930 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL 0x4290097C +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_DATA 0x42900980 +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG 0x42900934 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS 0x42900938 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL 0x42900984 +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_DATA 0x42900988 +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG 0x4290093C +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS 0x42900940 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL 0x4290098C +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_DATA 0x42900990 +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG 0x42900944 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS 0x42900948 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL 0x42900994 +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_DATA 0x42900998 +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG 0x4290094C +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS 0x42900950 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL 0x4290099C +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_DATA 0x429009A0 +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG 0x42900954 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS 0x42900958 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL 0x429009A4 +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_DATA 0x429009A8 +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG 0x4290095C +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS 0x42900960 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_CACHE_CTRL 0x42900800 +#define IG3_MSOC_GLMSOC_CACHE_CTRL_RSVD_S 2 +#define IG3_MSOC_GLMSOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_MSOC_GLMSOC_CACHE_CTRL_RSVD_S) +#define IG3_MSOC_GLMSOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_MSOC_GLMSOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_MSOC_GLMSOC_CECC_ERR 0x429008D0 +#define IG3_MSOC_GLMSOC_CECC_ERR_RSVD1_S 28 +#define IG3_MSOC_GLMSOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CECC_ERR_RSVD1_S) +#define IG3_MSOC_GLMSOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_MSOC_GLMSOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLMSOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CECC_ERR_RSVD0_S 12 +#define IG3_MSOC_GLMSOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_CECC_ERR_RSVD0_S) +#define IG3_MSOC_GLMSOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_MSOC_GLMSOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLMSOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_CQCTX_OBJOFST 0x42900884 +#define IG3_MSOC_GLMSOC_CQCTX_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_CQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_CQCTX_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_CSTATELKUP_CFG 0x429008D8 +#define IG3_MSOC_GLMSOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_MSOC_GLMSOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_MSOC_GLMSOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_MSOC_GLMSOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_MSOC_GLMSOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_MSOC_GLMSOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_MSOC_GLMSOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_MSOC_GLMSOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_MSOC_GLMSOC_DPC_COMP 0x429008E8 +#define IG3_MSOC_GLMSOC_DPC_COMP_RSVD_S 13 +#define IG3_MSOC_GLMSOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_MSOC_GLMSOC_DPC_COMP_RSVD_S) +#define IG3_MSOC_GLMSOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_MSOC_GLMSOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_MSOC_GLMSOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_MSOC_GLMSOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_DPC_COMP_COMP_FNUM_S) +#define IG3_MSOC_GLMSOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_MSOC_GLMSOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_DPC_COMP_COMP_VALID_S) +#define IG3_MSOC_GLMSOC_DPC_REQ 0x429008E4 +#define IG3_MSOC_GLMSOC_DPC_REQ_RSVD_S 12 +#define IG3_MSOC_GLMSOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MSOC_GLMSOC_DPC_REQ_RSVD_S) +#define IG3_MSOC_GLMSOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_MSOC_GLMSOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_MSOC_GLMSOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_MSOC_GLMSOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_DPC_REQ_REQ_FNUM_S) +#define IG3_MSOC_GLMSOC_ECC_CTL 0x429008C8 +#define IG3_MSOC_GLMSOC_ECC_CTL_RSVD_S 8 +#define IG3_MSOC_GLMSOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_ECC_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_MSOC_GLMSOC_ERRDATA0 0x429008B8 +#define IG3_MSOC_GLMSOC_ERRDATA0_RSVD1_S 31 +#define IG3_MSOC_GLMSOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ERRDATA0_RSVD1_S) +#define IG3_MSOC_GLMSOC_ERRDATA0_PF_NUM_S 25 +#define IG3_MSOC_GLMSOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_MSOC_GLMSOC_ERRDATA0_PF_NUM_S) +#define IG3_MSOC_GLMSOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_MSOC_GLMSOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_MSOC_GLMSOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_MSOC_GLMSOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_MSOC_GLMSOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_MSOC_GLMSOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_MSOC_GLMSOC_ERRDATA0_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_ERRDATA0_RSVD0_S) +#define IG3_MSOC_GLMSOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_MSOC_GLMSOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_MSOC_GLMSOC_ERRDATA0_ERROR_CODE_S) +#define IG3_MSOC_GLMSOC_ERRDATA1 0x429008BC +#define IG3_MSOC_GLMSOC_ERRDATA1_RSVD_S 28 +#define IG3_MSOC_GLMSOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_ERRDATA1_RSVD_S) +#define IG3_MSOC_GLMSOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_MSOC_GLMSOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_MSOC_GLMSOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_MSOC_GLMSOC_ERRDATA2 0x429008C0 +#define IG3_MSOC_GLMSOC_ERRDATA2_RSVD_S 23 +#define IG3_MSOC_GLMSOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_MSOC_GLMSOC_ERRDATA2_RSVD_S) +#define IG3_MSOC_GLMSOC_ERRDATA2_OPTYPE_S 20 +#define IG3_MSOC_GLMSOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_MSOC_GLMSOC_ERRDATA2_OPTYPE_S) +#define IG3_MSOC_GLMSOC_ERRDATA2_OFFSET_S 7 +#define IG3_MSOC_GLMSOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_MSOC_GLMSOC_ERRDATA2_OFFSET_S) +#define IG3_MSOC_GLMSOC_ERRDATA2_LENGTH_S 0 +#define IG3_MSOC_GLMSOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_ERRDATA2_LENGTH_S) +#define IG3_MSOC_GLMSOC_ERRDATA3 0x429008C4 +#define IG3_MSOC_GLMSOC_ERRDATA3_RSVD_S 15 +#define IG3_MSOC_GLMSOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_MSOC_GLMSOC_ERRDATA3_RSVD_S) +#define IG3_MSOC_GLMSOC_ERRDATA3_TAG_S 0 +#define IG3_MSOC_GLMSOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_MSOC_GLMSOC_ERRDATA3_TAG_S) +#define IG3_MSOC_GLMSOC_ERRINFO 0x429008B4 +#define IG3_MSOC_GLMSOC_ERRINFO_RSVD1_S 16 +#define IG3_MSOC_GLMSOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_MSOC_GLMSOC_ERRINFO_RSVD1_S) +#define IG3_MSOC_GLMSOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_MSOC_GLMSOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_ERRINFO_ERROR_CNT_S) +#define IG3_MSOC_GLMSOC_ERRINFO_RSVD0_S 1 +#define IG3_MSOC_GLMSOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_ERRINFO_RSVD0_S) +#define IG3_MSOC_GLMSOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_MSOC_GLMSOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_ERRINFO_ERROR_VALID_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG 0x4290091C +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS 0x42900920 +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG 0x42900914 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_FILL_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS 0x42900918 +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_FSIADR_OBJOFST 0x4290088C +#define IG3_MSOC_GLMSOC_FSIADR_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_FSIADR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_FSIADR_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_FSIMCAST_OBJOFST 0x42900890 +#define IG3_MSOC_GLMSOC_FSIMCAST_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_FSIMCAST_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_FSIMCAST_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_HDR_OBJOFST 0x429008A0 +#define IG3_MSOC_GLMSOC_HDR_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_HDR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_HDR_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_HECC_ERR 0x429008CC +#define IG3_MSOC_GLMSOC_HECC_ERR_RSVD1_S 28 +#define IG3_MSOC_GLMSOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_HECC_ERR_RSVD1_S) +#define IG3_MSOC_GLMSOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_MSOC_GLMSOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLMSOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_HECC_ERR_RSVD0_S 12 +#define IG3_MSOC_GLMSOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_HECC_ERR_RSVD0_S) +#define IG3_MSOC_GLMSOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_MSOC_GLMSOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLMSOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_IRRQ_OBJOFST 0x42900880 +#define IG3_MSOC_GLMSOC_IRRQ_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_IRRQ_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_IRRQ_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_MAXOSR 0x429008D4 +#define IG3_MSOC_GLMSOC_MAXOSR_RSVD1_S 15 +#define IG3_MSOC_GLMSOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0x1FFFF, IG3_MSOC_GLMSOC_MAXOSR_RSVD1_S) +#define IG3_MSOC_GLMSOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 10 +#define IG3_MSOC_GLMSOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_MSOC_GLMSOC_MAXOSR_RSVD0_S 8 +#define IG3_MSOC_GLMSOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_MAXOSR_RSVD0_S) +#define IG3_MSOC_GLMSOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_MSOC_GLMSOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_MSOC_GLMSOC_MEM_ECC_COR_ERR 0x429009B8 +#define IG3_MSOC_GLMSOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_MSOC_GLMSOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MSOC_GLMSOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_MSOC_GLMSOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_MSOC_GLMSOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLMSOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_MEM_ECC_UNCOR_ERR 0x429009B4 +#define IG3_MSOC_GLMSOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_MSOC_GLMSOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MSOC_GLMSOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_MSOC_GLMSOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_MSOC_GLMSOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLMSOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_OOISCFL_OBJOFST 0x429008B0 +#define IG3_MSOC_GLMSOC_OOISCFL_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_OOISCFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_OOISCFL_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_OOISC_OBJOFST 0x429008AC +#define IG3_MSOC_GLMSOC_OOISC_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_OOISC_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_OOISC_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL 0x429009AC +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_PLIST_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_PLIST_DBG_DATA 0x429009B0 +#define IG3_MSOC_GLMSOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG 0x4290090C +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS 0x42900910 +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_PMATINV_CFG 0x429008DC +#define IG3_MSOC_GLMSOC_PMATINV_CFG_RSVD_S 6 +#define IG3_MSOC_GLMSOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_MSOC_GLMSOC_PMATINV_CFG_RSVD_S) +#define IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_MSOC_GLMSOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_MSOC_GLMSOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_MSOC_GLMSOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_MSOC_GLMSOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_MSOC_GLMSOC_Q1FL_OBJOFST 0x42900898 +#define IG3_MSOC_GLMSOC_Q1FL_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_Q1FL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_Q1FL_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_RRFL_OBJOFST 0x429008A8 +#define IG3_MSOC_GLMSOC_RRFL_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_RRFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_RRFL_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_RRF_OBJOFST 0x429008A4 +#define IG3_MSOC_GLMSOC_RRF_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_RRF_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_RRF_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_SRQCTX_OBJOFST 0x42900888 +#define IG3_MSOC_GLMSOC_SRQCTX_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_SRQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_SRQCTX_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_STAT_CTL 0x42900804 +#define IG3_MSOC_GLMSOC_STAT_CTL_RSVD_S 5 +#define IG3_MSOC_GLMSOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_MSOC_GLMSOC_STAT_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_MSOC_GLMSOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_MSOC_GLMSOC_STAT_FENCING_TIME_HI 0x4290086C +#define IG3_MSOC_GLMSOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_FENCING_TIME_LO 0x42900868 +#define IG3_MSOC_GLMSOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_ENTRIES 0x4290084C +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_LIST_DEPTH 0x42900854 +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_MAX_VIRT_PENDING_LISTS 0x42900850 +#define IG3_MSOC_GLMSOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_MSOC_GLMSOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_OBJ_CNT 0x42900808 +#define IG3_MSOC_GLMSOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_MSOC_GLMSOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_MSOC_GLMSOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_MSOC_GLMSOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_HI 0x42900864 +#define IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_LO 0x42900860 +#define IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_HI 0x42900830 +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_LO 0x4290082C +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_HI 0x42900838 +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_LO 0x42900834 +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_RD_HIT_HI 0x42900810 +#define IG3_MSOC_GLMSOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_RD_HIT_LO 0x4290080C +#define IG3_MSOC_GLMSOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_RD_MISS_HI 0x42900818 +#define IG3_MSOC_GLMSOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_RD_MISS_LO 0x42900814 +#define IG3_MSOC_GLMSOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_HI 0x42900874 +#define IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_LO 0x42900870 +#define IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_HI 0x4290085C +#define IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_LO 0x42900858 +#define IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_HI 0x42900840 +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_LO 0x4290083C +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_HI 0x42900848 +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_LO 0x42900844 +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_WR_HIT_HI 0x42900820 +#define IG3_MSOC_GLMSOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_WR_HIT_LO 0x4290081C +#define IG3_MSOC_GLMSOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_STAT_WR_MISS_HI 0x42900828 +#define IG3_MSOC_GLMSOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_STAT_WR_MISS_LO 0x42900824 +#define IG3_MSOC_GLMSOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL 0x42900964 +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_DBG_CTL_DONE_S) +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_TAG_DBG_CTL_RSVD_S) +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_MSOC_GLMSOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_TAG_DBG_CTL_ADR_S) +#define IG3_MSOC_GLMSOC_TAG_DBG_DATA 0x42900968 +#define IG3_MSOC_GLMSOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_MSOC_GLMSOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG 0x429008FC +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_TAG_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS 0x42900900 +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_TIMER_OBJOFST 0x4290089C +#define IG3_MSOC_GLMSOC_TIMER_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_TIMER_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_TIMER_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HI 0x429008F0 +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_HI 0x429008F8 +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_LO 0x429008F4 +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_TOTAL_TAG_LO 0x429008EC +#define IG3_MSOC_GLMSOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_MSOC_GLMSOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLMSOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_MSOC_GLMSOC_TXFIFO_OBJOFST 0x4290087C +#define IG3_MSOC_GLMSOC_TXFIFO_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_TXFIFO_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_TXFIFO_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG 0x42900904 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RM_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RME_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS 0x42900908 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLMSOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLMSOC_XFFL_OBJOFST 0x42900894 +#define IG3_MSOC_GLMSOC_XFFL_OBJOFST_RSVD_S 10 +#define IG3_MSOC_GLMSOC_XFFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_MSOC_GLMSOC_XFFL_OBJOFST_RSVD_S) +#define IG3_MSOC_GLMSOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_MSOC_GLMSOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_MSOC_GLMSOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_COUNT 0x42900A38 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_CMD 0x42900A4C +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_DATA_H 0x42900A58 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_DATA_L 0x42900A54 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_PTR 0x42900A50 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_CMD 0x42900A3C +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_DATA_H 0x42900A48 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_DATA_L 0x42900A44 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_PTR 0x42900A40 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_MSOC_GLPE_MSOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL 0x42900A00 +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD2_S) +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD3_S) +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_CONTROL_BYPASS_S) +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLPE_MSOC_DTM_CONTROL_RSVD4_S) +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_COR_ERR 0x42900A68 +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MSOC_GLPE_MSOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLPE_MSOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_UNCOR_ERR 0x42900A64 +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_MSOC_GLPE_MSOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_MSOC_GLPE_MSOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG 0x42900A0C +#define IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLPE_MSOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG 0x42900A10 +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLPE_MSOC_DTM_LOG_CFG_MODE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_MASK 0x42900A18 +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_LOG_MASK_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_PATTERN 0x42900A14 +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG 0x42900A04 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS 0x42900A08 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TIMESTAMP 0x42900A30 +#define IG3_MSOC_GLPE_MSOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TIMESTAMP_ROLLOVER 0x42900A34 +#define IG3_MSOC_GLPE_MSOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG 0x42900A5C +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS 0x42900A60 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_MSOC_GLPE_MSOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG 0x42900A1C +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_MSOC_GLPE_MSOC_DTM_TRIG_CFG_MODE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_COUNT 0x42900A28 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_MASK 0x42900A24 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_PATTERN 0x42900A20 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_TIMESTAMP 0x42900A2C +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_MSOC_GLPE_MSOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_MSOC_GLPE_MSOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PEOC1_GLPEOC_ARPTBLE_OBJOFST 0x42900C78 +#define IG3_PEOC1_GLPEOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_CACHESIZE 0x42900CE0 +#define IG3_PEOC1_GLPEOC_CACHESIZE_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHESIZE_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHESIZE_WAYS_S 20 +#define IG3_PEOC1_GLPEOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHESIZE_WAYS_S) +#define IG3_PEOC1_GLPEOC_CACHESIZE_SETS_S 8 +#define IG3_PEOC1_GLPEOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_CACHESIZE_SETS_S) +#define IG3_PEOC1_GLPEOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_PEOC1_GLPEOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHESIZE_WORD_SIZE_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL 0x42900D6C +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_DATA 0x42900D70 +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG 0x42900D24 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS 0x42900D28 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL 0x42900D74 +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_DATA 0x42900D78 +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG 0x42900D2C +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS 0x42900D30 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL 0x42900D7C +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_DATA 0x42900D80 +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG 0x42900D34 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS 0x42900D38 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL 0x42900D84 +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_DATA 0x42900D88 +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG 0x42900D3C +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS 0x42900D40 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL 0x42900D8C +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_DATA 0x42900D90 +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG 0x42900D44 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS 0x42900D48 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL 0x42900D94 +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_DATA 0x42900D98 +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG 0x42900D4C +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS 0x42900D50 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL 0x42900D9C +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_DATA 0x42900DA0 +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG 0x42900D54 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS 0x42900D58 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL 0x42900DA4 +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_DATA 0x42900DA8 +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG 0x42900D5C +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS 0x42900D60 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_CACHE_CTRL 0x42900C00 +#define IG3_PEOC1_GLPEOC_CACHE_CTRL_RSVD_S 2 +#define IG3_PEOC1_GLPEOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PEOC1_GLPEOC_CACHE_CTRL_RSVD_S) +#define IG3_PEOC1_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_PEOC1_GLPEOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_PEOC1_GLPEOC_CECC_ERR 0x42900CD0 +#define IG3_PEOC1_GLPEOC_CECC_ERR_RSVD1_S 28 +#define IG3_PEOC1_GLPEOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CECC_ERR_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC1_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CECC_ERR_RSVD0_S 12 +#define IG3_PEOC1_GLPEOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_CECC_ERR_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC1_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_CQCTX_OBJOFST 0x42900C84 +#define IG3_PEOC1_GLPEOC_CQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_CQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_CQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_CSTATELKUP_CFG 0x42900CD8 +#define IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_PEOC1_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_PEOC1_GLPEOC_DPC_COMP 0x42900CE8 +#define IG3_PEOC1_GLPEOC_DPC_COMP_RSVD_S 13 +#define IG3_PEOC1_GLPEOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEOC1_GLPEOC_DPC_COMP_RSVD_S) +#define IG3_PEOC1_GLPEOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_PEOC1_GLPEOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_PEOC1_GLPEOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_PEOC1_GLPEOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_DPC_COMP_COMP_FNUM_S) +#define IG3_PEOC1_GLPEOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_PEOC1_GLPEOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DPC_COMP_COMP_VALID_S) +#define IG3_PEOC1_GLPEOC_DPC_REQ 0x42900CE4 +#define IG3_PEOC1_GLPEOC_DPC_REQ_RSVD_S 12 +#define IG3_PEOC1_GLPEOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC1_GLPEOC_DPC_REQ_RSVD_S) +#define IG3_PEOC1_GLPEOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_PEOC1_GLPEOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_PEOC1_GLPEOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_PEOC1_GLPEOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_DPC_REQ_REQ_FNUM_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_COUNT 0x42900E38 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_CMD 0x42900E4C +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_DATA_H 0x42900E58 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_DATA_L 0x42900E54 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_PTR 0x42900E50 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_CMD 0x42900E3C +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_DATA_H 0x42900E48 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_DATA_L 0x42900E44 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_PTR 0x42900E40 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC1_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_CONTROL 0x42900E00 +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD2_S) +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD3_S) +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_CONTROL_BYPASS_S) +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_DTM_CONTROL_RSVD4_S) +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PEOC1_GLPEOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PEOC1_GLPEOC_DTM_ECC_COR_ERR 0x42900E68 +#define IG3_PEOC1_GLPEOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC1_GLPEOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC1_GLPEOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC1_GLPEOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC1_GLPEOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_DTM_ECC_UNCOR_ERR 0x42900E64 +#define IG3_PEOC1_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC1_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC1_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC1_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC1_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_DTM_GROUP_CFG 0x42900E0C +#define IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PEOC1_GLPEOC_DTM_LOG_CFG 0x42900E10 +#define IG3_PEOC1_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PEOC1_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC1_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PEOC1_GLPEOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PEOC1_GLPEOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC1_GLPEOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_DTM_LOG_CFG_MODE_S) +#define IG3_PEOC1_GLPEOC_DTM_LOG_MASK 0x42900E18 +#define IG3_PEOC1_GLPEOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_LOG_MASK_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_LOG_PATTERN 0x42900E14 +#define IG3_PEOC1_GLPEOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG 0x42900E04 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_STS 0x42900E08 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC1_GLPEOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_PEOC1_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PEOC1_GLPEOC_DTM_TIMESTAMP 0x42900E30 +#define IG3_PEOC1_GLPEOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_TIMESTAMP_ROLLOVER 0x42900E34 +#define IG3_PEOC1_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG 0x42900E5C +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS 0x42900E60 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG 0x42900E1C +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_DTM_TRIG_CFG_MODE_S) +#define IG3_PEOC1_GLPEOC_DTM_TRIG_COUNT 0x42900E28 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_TRIG_MASK 0x42900E24 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_TRIG_PATTERN 0x42900E20 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PEOC1_GLPEOC_DTM_TRIG_TIMESTAMP 0x42900E2C +#define IG3_PEOC1_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC1_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PEOC1_GLPEOC_ECC_CTL 0x42900CC8 +#define IG3_PEOC1_GLPEOC_ECC_CTL_RSVD_S 8 +#define IG3_PEOC1_GLPEOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_ECC_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_ERRDATA0 0x42900CB8 +#define IG3_PEOC1_GLPEOC_ERRDATA0_RSVD1_S 31 +#define IG3_PEOC1_GLPEOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ERRDATA0_RSVD1_S) +#define IG3_PEOC1_GLPEOC_ERRDATA0_PF_NUM_S 25 +#define IG3_PEOC1_GLPEOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PEOC1_GLPEOC_ERRDATA0_PF_NUM_S) +#define IG3_PEOC1_GLPEOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_PEOC1_GLPEOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_PEOC1_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_PEOC1_GLPEOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_PEOC1_GLPEOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_PEOC1_GLPEOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_PEOC1_GLPEOC_ERRDATA0_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_ERRDATA0_RSVD0_S) +#define IG3_PEOC1_GLPEOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_PEOC1_GLPEOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_PEOC1_GLPEOC_ERRDATA0_ERROR_CODE_S) +#define IG3_PEOC1_GLPEOC_ERRDATA1 0x42900CBC +#define IG3_PEOC1_GLPEOC_ERRDATA1_RSVD_S 28 +#define IG3_PEOC1_GLPEOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_ERRDATA1_RSVD_S) +#define IG3_PEOC1_GLPEOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_PEOC1_GLPEOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PEOC1_GLPEOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_PEOC1_GLPEOC_ERRDATA2 0x42900CC0 +#define IG3_PEOC1_GLPEOC_ERRDATA2_RSVD_S 23 +#define IG3_PEOC1_GLPEOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PEOC1_GLPEOC_ERRDATA2_RSVD_S) +#define IG3_PEOC1_GLPEOC_ERRDATA2_OPTYPE_S 20 +#define IG3_PEOC1_GLPEOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_PEOC1_GLPEOC_ERRDATA2_OPTYPE_S) +#define IG3_PEOC1_GLPEOC_ERRDATA2_OFFSET_S 7 +#define IG3_PEOC1_GLPEOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_PEOC1_GLPEOC_ERRDATA2_OFFSET_S) +#define IG3_PEOC1_GLPEOC_ERRDATA2_LENGTH_S 0 +#define IG3_PEOC1_GLPEOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_ERRDATA2_LENGTH_S) +#define IG3_PEOC1_GLPEOC_ERRDATA3 0x42900CC4 +#define IG3_PEOC1_GLPEOC_ERRDATA3_RSVD_S 15 +#define IG3_PEOC1_GLPEOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC1_GLPEOC_ERRDATA3_RSVD_S) +#define IG3_PEOC1_GLPEOC_ERRDATA3_TAG_S 0 +#define IG3_PEOC1_GLPEOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC1_GLPEOC_ERRDATA3_TAG_S) +#define IG3_PEOC1_GLPEOC_ERRINFO 0x42900CB4 +#define IG3_PEOC1_GLPEOC_ERRINFO_RSVD1_S 16 +#define IG3_PEOC1_GLPEOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC1_GLPEOC_ERRINFO_RSVD1_S) +#define IG3_PEOC1_GLPEOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_PEOC1_GLPEOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_ERRINFO_ERROR_CNT_S) +#define IG3_PEOC1_GLPEOC_ERRINFO_RSVD0_S 1 +#define IG3_PEOC1_GLPEOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_ERRINFO_RSVD0_S) +#define IG3_PEOC1_GLPEOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_PEOC1_GLPEOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_ERRINFO_ERROR_VALID_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG 0x42900D1C +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS 0x42900D20 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG 0x42900D14 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS 0x42900D18 +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_FSIADR_OBJOFST 0x42900C8C +#define IG3_PEOC1_GLPEOC_FSIADR_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_FSIADR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_FSIADR_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_FSIMCAST_OBJOFST 0x42900C90 +#define IG3_PEOC1_GLPEOC_FSIMCAST_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_FSIMCAST_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_FSIMCAST_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_HDR_OBJOFST 0x42900CA0 +#define IG3_PEOC1_GLPEOC_HDR_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_HDR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_HDR_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_HECC_ERR 0x42900CCC +#define IG3_PEOC1_GLPEOC_HECC_ERR_RSVD1_S 28 +#define IG3_PEOC1_GLPEOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_HECC_ERR_RSVD1_S) +#define IG3_PEOC1_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC1_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_HECC_ERR_RSVD0_S 12 +#define IG3_PEOC1_GLPEOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_HECC_ERR_RSVD0_S) +#define IG3_PEOC1_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC1_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_IRRQ_OBJOFST 0x42900C80 +#define IG3_PEOC1_GLPEOC_IRRQ_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_IRRQ_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_IRRQ_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_MAXOSR 0x42900CD4 +#define IG3_PEOC1_GLPEOC_MAXOSR_RSVD1_S 12 +#define IG3_PEOC1_GLPEOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC1_GLPEOC_MAXOSR_RSVD1_S) +#define IG3_PEOC1_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 8 +#define IG3_PEOC1_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_PEOC1_GLPEOC_MAXOSR_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_MAXOSR_RSVD0_S) +#define IG3_PEOC1_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_PEOC1_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0x3F, IG3_PEOC1_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_PEOC1_GLPEOC_MEM_ECC_COR_ERR 0x42900DB8 +#define IG3_PEOC1_GLPEOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC1_GLPEOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC1_GLPEOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC1_GLPEOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC1_GLPEOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_MEM_ECC_UNCOR_ERR 0x42900DB4 +#define IG3_PEOC1_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC1_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC1_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC1_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC1_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC1_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_OOISCFL_OBJOFST 0x42900CB0 +#define IG3_PEOC1_GLPEOC_OOISCFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_OOISCFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_OOISCFL_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_OOISC_OBJOFST 0x42900CAC +#define IG3_PEOC1_GLPEOC_OOISC_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_OOISC_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_OOISC_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL 0x42900DAC +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_PLIST_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_PLIST_DBG_DATA 0x42900DB0 +#define IG3_PEOC1_GLPEOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG 0x42900D0C +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS 0x42900D10 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_PMATINV_CFG 0x42900CDC +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_RSVD_S 6 +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_PEOC1_GLPEOC_PMATINV_CFG_RSVD_S) +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_PEOC1_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_PEOC1_GLPEOC_Q1FL_OBJOFST 0x42900C98 +#define IG3_PEOC1_GLPEOC_Q1FL_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_Q1FL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_Q1FL_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_RRFL_OBJOFST 0x42900CA8 +#define IG3_PEOC1_GLPEOC_RRFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_RRFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_RRFL_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_RRF_OBJOFST 0x42900CA4 +#define IG3_PEOC1_GLPEOC_RRF_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_RRF_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_RRF_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_SRQCTX_OBJOFST 0x42900C88 +#define IG3_PEOC1_GLPEOC_SRQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_SRQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_SRQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_STAT_CTL 0x42900C04 +#define IG3_PEOC1_GLPEOC_STAT_CTL_RSVD_S 5 +#define IG3_PEOC1_GLPEOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PEOC1_GLPEOC_STAT_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_PEOC1_GLPEOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_HI 0x42900C6C +#define IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_LO 0x42900C68 +#define IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_ENTRIES 0x42900C4C +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH 0x42900C54 +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS 0x42900C50 +#define IG3_PEOC1_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_PEOC1_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_OBJ_CNT 0x42900C08 +#define IG3_PEOC1_GLPEOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_PEOC1_GLPEOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_PEOC1_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC1_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_HI 0x42900C64 +#define IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_LO 0x42900C60 +#define IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_HI 0x42900C30 +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_LO 0x42900C2C +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_HI 0x42900C38 +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_LO 0x42900C34 +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_HIT_HI 0x42900C10 +#define IG3_PEOC1_GLPEOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_HIT_LO 0x42900C0C +#define IG3_PEOC1_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_MISS_HI 0x42900C18 +#define IG3_PEOC1_GLPEOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_RD_MISS_LO 0x42900C14 +#define IG3_PEOC1_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_HI 0x42900C74 +#define IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_LO 0x42900C70 +#define IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_HI 0x42900C5C +#define IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_LO 0x42900C58 +#define IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_HI 0x42900C40 +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_LO 0x42900C3C +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_HI 0x42900C48 +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_LO 0x42900C44 +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_HIT_HI 0x42900C20 +#define IG3_PEOC1_GLPEOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_HIT_LO 0x42900C1C +#define IG3_PEOC1_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_MISS_HI 0x42900C28 +#define IG3_PEOC1_GLPEOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_STAT_WR_MISS_LO 0x42900C24 +#define IG3_PEOC1_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL 0x42900D64 +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_DBG_CTL_DONE_S) +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_TAG_DBG_CTL_RSVD_S) +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_PEOC1_GLPEOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_TAG_DBG_CTL_ADR_S) +#define IG3_PEOC1_GLPEOC_TAG_DBG_DATA 0x42900D68 +#define IG3_PEOC1_GLPEOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC1_GLPEOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG 0x42900CFC +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS 0x42900D00 +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_TIMER_OBJOFST 0x42900C9C +#define IG3_PEOC1_GLPEOC_TIMER_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_TIMER_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_TIMER_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HI 0x42900CF0 +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_HI 0x42900CF8 +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_LO 0x42900CF4 +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_LO 0x42900CEC +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_PEOC1_GLPEOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC1_GLPEOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_PEOC1_GLPEOC_TXFIFO_OBJOFST 0x42900C7C +#define IG3_PEOC1_GLPEOC_TXFIFO_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_TXFIFO_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_TXFIFO_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG 0x42900D04 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RM_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RME_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS 0x42900D08 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC1_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC1_GLPEOC_XFFL_OBJOFST 0x42900C94 +#define IG3_PEOC1_GLPEOC_XFFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC1_GLPEOC_XFFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC1_GLPEOC_XFFL_OBJOFST_RSVD_S) +#define IG3_PEOC1_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC1_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC1_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_ARPTBLE_OBJOFST 0x42901078 +#define IG3_FLOC_GLFLOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_CACHESIZE 0x429010E0 +#define IG3_FLOC_GLFLOC_CACHESIZE_RSVD_S 24 +#define IG3_FLOC_GLFLOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHESIZE_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHESIZE_WAYS_S 20 +#define IG3_FLOC_GLFLOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHESIZE_WAYS_S) +#define IG3_FLOC_GLFLOC_CACHESIZE_SETS_S 8 +#define IG3_FLOC_GLFLOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLFLOC_CACHESIZE_SETS_S) +#define IG3_FLOC_GLFLOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_FLOC_GLFLOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHESIZE_WORD_SIZE_S) +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL 0x4290116C +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_DATA 0x42901170 +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG 0x42901124 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS 0x42901128 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL 0x42901174 +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_DATA 0x42901178 +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG 0x4290112C +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS 0x42901130 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL 0x4290117C +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_DATA 0x42901180 +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG 0x42901134 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS 0x42901138 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL 0x42901184 +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_DATA 0x42901188 +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG 0x4290113C +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS 0x42901140 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL 0x4290118C +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_DATA 0x42901190 +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG 0x42901144 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS 0x42901148 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL 0x42901194 +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_DATA 0x42901198 +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG 0x4290114C +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS 0x42901150 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL 0x4290119C +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_DATA 0x429011A0 +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG 0x42901154 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS 0x42901158 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL 0x429011A4 +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_DATA 0x429011A8 +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG 0x4290115C +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS 0x42901160 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_CACHE_CTRL 0x42901000 +#define IG3_FLOC_GLFLOC_CACHE_CTRL_RSVD_S 2 +#define IG3_FLOC_GLFLOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_FLOC_GLFLOC_CACHE_CTRL_RSVD_S) +#define IG3_FLOC_GLFLOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_FLOC_GLFLOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_FLOC_GLFLOC_CECC_ERR 0x429010D0 +#define IG3_FLOC_GLFLOC_CECC_ERR_RSVD1_S 28 +#define IG3_FLOC_GLFLOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CECC_ERR_RSVD1_S) +#define IG3_FLOC_GLFLOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_FLOC_GLFLOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLFLOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CECC_ERR_RSVD0_S 12 +#define IG3_FLOC_GLFLOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_CECC_ERR_RSVD0_S) +#define IG3_FLOC_GLFLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_FLOC_GLFLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLFLOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_CQCTX_OBJOFST 0x42901084 +#define IG3_FLOC_GLFLOC_CQCTX_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_CQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_CQCTX_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_CSTATELKUP_CFG 0x429010D8 +#define IG3_FLOC_GLFLOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_FLOC_GLFLOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_FLOC_GLFLOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_FLOC_GLFLOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_FLOC_GLFLOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_FLOC_GLFLOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_FLOC_GLFLOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_FLOC_GLFLOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_FLOC_GLFLOC_DPC_COMP 0x429010E8 +#define IG3_FLOC_GLFLOC_DPC_COMP_RSVD_S 13 +#define IG3_FLOC_GLFLOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_FLOC_GLFLOC_DPC_COMP_RSVD_S) +#define IG3_FLOC_GLFLOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_FLOC_GLFLOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_FLOC_GLFLOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_FLOC_GLFLOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_DPC_COMP_COMP_FNUM_S) +#define IG3_FLOC_GLFLOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_FLOC_GLFLOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_DPC_COMP_COMP_VALID_S) +#define IG3_FLOC_GLFLOC_DPC_REQ 0x429010E4 +#define IG3_FLOC_GLFLOC_DPC_REQ_RSVD_S 12 +#define IG3_FLOC_GLFLOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_FLOC_GLFLOC_DPC_REQ_RSVD_S) +#define IG3_FLOC_GLFLOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_FLOC_GLFLOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_FLOC_GLFLOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_FLOC_GLFLOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_DPC_REQ_REQ_FNUM_S) +#define IG3_FLOC_GLFLOC_ECC_CTL 0x429010C8 +#define IG3_FLOC_GLFLOC_ECC_CTL_RSVD_S 8 +#define IG3_FLOC_GLFLOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_ECC_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_FLOC_GLFLOC_ERRDATA0 0x429010B8 +#define IG3_FLOC_GLFLOC_ERRDATA0_RSVD1_S 31 +#define IG3_FLOC_GLFLOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ERRDATA0_RSVD1_S) +#define IG3_FLOC_GLFLOC_ERRDATA0_PF_NUM_S 25 +#define IG3_FLOC_GLFLOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_FLOC_GLFLOC_ERRDATA0_PF_NUM_S) +#define IG3_FLOC_GLFLOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_FLOC_GLFLOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_FLOC_GLFLOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_FLOC_GLFLOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_FLOC_GLFLOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_FLOC_GLFLOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_FLOC_GLFLOC_ERRDATA0_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_ERRDATA0_RSVD0_S) +#define IG3_FLOC_GLFLOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_FLOC_GLFLOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_FLOC_GLFLOC_ERRDATA0_ERROR_CODE_S) +#define IG3_FLOC_GLFLOC_ERRDATA1 0x429010BC +#define IG3_FLOC_GLFLOC_ERRDATA1_RSVD_S 28 +#define IG3_FLOC_GLFLOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_ERRDATA1_RSVD_S) +#define IG3_FLOC_GLFLOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_FLOC_GLFLOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_FLOC_GLFLOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_FLOC_GLFLOC_ERRDATA2 0x429010C0 +#define IG3_FLOC_GLFLOC_ERRDATA2_RSVD_S 23 +#define IG3_FLOC_GLFLOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_FLOC_GLFLOC_ERRDATA2_RSVD_S) +#define IG3_FLOC_GLFLOC_ERRDATA2_OPTYPE_S 20 +#define IG3_FLOC_GLFLOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_FLOC_GLFLOC_ERRDATA2_OPTYPE_S) +#define IG3_FLOC_GLFLOC_ERRDATA2_OFFSET_S 7 +#define IG3_FLOC_GLFLOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_FLOC_GLFLOC_ERRDATA2_OFFSET_S) +#define IG3_FLOC_GLFLOC_ERRDATA2_LENGTH_S 0 +#define IG3_FLOC_GLFLOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_ERRDATA2_LENGTH_S) +#define IG3_FLOC_GLFLOC_ERRDATA3 0x429010C4 +#define IG3_FLOC_GLFLOC_ERRDATA3_RSVD_S 15 +#define IG3_FLOC_GLFLOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_FLOC_GLFLOC_ERRDATA3_RSVD_S) +#define IG3_FLOC_GLFLOC_ERRDATA3_TAG_S 0 +#define IG3_FLOC_GLFLOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_FLOC_GLFLOC_ERRDATA3_TAG_S) +#define IG3_FLOC_GLFLOC_ERRINFO 0x429010B4 +#define IG3_FLOC_GLFLOC_ERRINFO_RSVD1_S 16 +#define IG3_FLOC_GLFLOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_FLOC_GLFLOC_ERRINFO_RSVD1_S) +#define IG3_FLOC_GLFLOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_FLOC_GLFLOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_ERRINFO_ERROR_CNT_S) +#define IG3_FLOC_GLFLOC_ERRINFO_RSVD0_S 1 +#define IG3_FLOC_GLFLOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_ERRINFO_RSVD0_S) +#define IG3_FLOC_GLFLOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_FLOC_GLFLOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_ERRINFO_ERROR_VALID_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG 0x4290111C +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS 0x42901120 +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG 0x42901114 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_FILL_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS 0x42901118 +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_FSIADR_OBJOFST 0x4290108C +#define IG3_FLOC_GLFLOC_FSIADR_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_FSIADR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_FSIADR_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_FSIMCAST_OBJOFST 0x42901090 +#define IG3_FLOC_GLFLOC_FSIMCAST_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_FSIMCAST_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_FSIMCAST_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_HDR_OBJOFST 0x429010A0 +#define IG3_FLOC_GLFLOC_HDR_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_HDR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_HDR_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_HECC_ERR 0x429010CC +#define IG3_FLOC_GLFLOC_HECC_ERR_RSVD1_S 28 +#define IG3_FLOC_GLFLOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_HECC_ERR_RSVD1_S) +#define IG3_FLOC_GLFLOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_FLOC_GLFLOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLFLOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_HECC_ERR_RSVD0_S 12 +#define IG3_FLOC_GLFLOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_HECC_ERR_RSVD0_S) +#define IG3_FLOC_GLFLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_FLOC_GLFLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLFLOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_IRRQ_OBJOFST 0x42901080 +#define IG3_FLOC_GLFLOC_IRRQ_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_IRRQ_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_IRRQ_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_MAXOSR 0x429010D4 +#define IG3_FLOC_GLFLOC_MAXOSR_RSVD1_S 14 +#define IG3_FLOC_GLFLOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_MAXOSR_RSVD1_S) +#define IG3_FLOC_GLFLOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 10 +#define IG3_FLOC_GLFLOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_FLOC_GLFLOC_MAXOSR_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_MAXOSR_RSVD0_S) +#define IG3_FLOC_GLFLOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_FLOC_GLFLOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0x3F, IG3_FLOC_GLFLOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_FLOC_GLFLOC_MEM_ECC_COR_ERR 0x429011B8 +#define IG3_FLOC_GLFLOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_FLOC_GLFLOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_FLOC_GLFLOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_FLOC_GLFLOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_FLOC_GLFLOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLFLOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_MEM_ECC_UNCOR_ERR 0x429011B4 +#define IG3_FLOC_GLFLOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_FLOC_GLFLOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_FLOC_GLFLOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_FLOC_GLFLOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_FLOC_GLFLOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLFLOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_OOISCFL_OBJOFST 0x429010B0 +#define IG3_FLOC_GLFLOC_OOISCFL_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_OOISCFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_OOISCFL_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_OOISC_OBJOFST 0x429010AC +#define IG3_FLOC_GLFLOC_OOISC_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_OOISC_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_OOISC_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL 0x429011AC +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_PLIST_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_PLIST_DBG_DATA 0x429011B0 +#define IG3_FLOC_GLFLOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG 0x4290110C +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS 0x42901110 +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_PMATINV_CFG 0x429010DC +#define IG3_FLOC_GLFLOC_PMATINV_CFG_RSVD_S 6 +#define IG3_FLOC_GLFLOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_FLOC_GLFLOC_PMATINV_CFG_RSVD_S) +#define IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_FLOC_GLFLOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_FLOC_GLFLOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_FLOC_GLFLOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_FLOC_GLFLOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_FLOC_GLFLOC_Q1FL_OBJOFST 0x42901098 +#define IG3_FLOC_GLFLOC_Q1FL_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_Q1FL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_Q1FL_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_RRFL_OBJOFST 0x429010A8 +#define IG3_FLOC_GLFLOC_RRFL_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_RRFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_RRFL_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_RRF_OBJOFST 0x429010A4 +#define IG3_FLOC_GLFLOC_RRF_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_RRF_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_RRF_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_SRQCTX_OBJOFST 0x42901088 +#define IG3_FLOC_GLFLOC_SRQCTX_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_SRQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_SRQCTX_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_STAT_CTL 0x42901004 +#define IG3_FLOC_GLFLOC_STAT_CTL_RSVD_S 5 +#define IG3_FLOC_GLFLOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_FLOC_GLFLOC_STAT_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_FLOC_GLFLOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_FLOC_GLFLOC_STAT_FENCING_TIME_HI 0x4290106C +#define IG3_FLOC_GLFLOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_FENCING_TIME_LO 0x42901068 +#define IG3_FLOC_GLFLOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_ENTRIES 0x4290104C +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_LIST_DEPTH 0x42901054 +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_MAX_VIRT_PENDING_LISTS 0x42901050 +#define IG3_FLOC_GLFLOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_FLOC_GLFLOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_OBJ_CNT 0x42901008 +#define IG3_FLOC_GLFLOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_FLOC_GLFLOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_FLOC_GLFLOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_FLOC_GLFLOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_HI 0x42901064 +#define IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_LO 0x42901060 +#define IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_HI 0x42901030 +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_LO 0x4290102C +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_HI 0x42901038 +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_LO 0x42901034 +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_RD_HIT_HI 0x42901010 +#define IG3_FLOC_GLFLOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_RD_HIT_LO 0x4290100C +#define IG3_FLOC_GLFLOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_RD_MISS_HI 0x42901018 +#define IG3_FLOC_GLFLOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_RD_MISS_LO 0x42901014 +#define IG3_FLOC_GLFLOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_HI 0x42901074 +#define IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_LO 0x42901070 +#define IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_HI 0x4290105C +#define IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_LO 0x42901058 +#define IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_HI 0x42901040 +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_LO 0x4290103C +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_HI 0x42901048 +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_LO 0x42901044 +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_WR_HIT_HI 0x42901020 +#define IG3_FLOC_GLFLOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_WR_HIT_LO 0x4290101C +#define IG3_FLOC_GLFLOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_STAT_WR_MISS_HI 0x42901028 +#define IG3_FLOC_GLFLOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_STAT_WR_MISS_LO 0x42901024 +#define IG3_FLOC_GLFLOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL 0x42901164 +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_DBG_CTL_DONE_S) +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_TAG_DBG_CTL_RSVD_S) +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_FLOC_GLFLOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_TAG_DBG_CTL_ADR_S) +#define IG3_FLOC_GLFLOC_TAG_DBG_DATA 0x42901168 +#define IG3_FLOC_GLFLOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_FLOC_GLFLOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG 0x429010FC +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_TAG_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS 0x42901100 +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_TIMER_OBJOFST 0x4290109C +#define IG3_FLOC_GLFLOC_TIMER_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_TIMER_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_TIMER_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HI 0x429010F0 +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_HI 0x429010F8 +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_LO 0x429010F4 +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_TOTAL_TAG_LO 0x429010EC +#define IG3_FLOC_GLFLOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_FLOC_GLFLOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLFLOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_FLOC_GLFLOC_TXFIFO_OBJOFST 0x4290107C +#define IG3_FLOC_GLFLOC_TXFIFO_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_TXFIFO_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_TXFIFO_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG 0x42901104 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RM_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RME_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS 0x42901108 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLFLOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLFLOC_XFFL_OBJOFST 0x42901094 +#define IG3_FLOC_GLFLOC_XFFL_OBJOFST_RSVD_S 10 +#define IG3_FLOC_GLFLOC_XFFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_FLOC_GLFLOC_XFFL_OBJOFST_RSVD_S) +#define IG3_FLOC_GLFLOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_FLOC_GLFLOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_FLOC_GLFLOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_COUNT 0x42901238 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_CMD 0x4290124C +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_DATA_H 0x42901258 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_DATA_L 0x42901254 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_PTR 0x42901250 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_CMD 0x4290123C +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_DATA_H 0x42901248 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_DATA_L 0x42901244 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_PTR 0x42901240 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_FLOC_GLPE_FLOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL 0x42901200 +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD2_S) +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD3_S) +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_CONTROL_BYPASS_S) +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLPE_FLOC_DTM_CONTROL_RSVD4_S) +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_COR_ERR 0x42901268 +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_FLOC_GLPE_FLOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLPE_FLOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_UNCOR_ERR 0x42901264 +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_FLOC_GLPE_FLOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_FLOC_GLPE_FLOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG 0x4290120C +#define IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLPE_FLOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG 0x42901210 +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLPE_FLOC_DTM_LOG_CFG_MODE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_MASK 0x42901218 +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_LOG_MASK_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_PATTERN 0x42901214 +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG 0x42901204 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS 0x42901208 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TIMESTAMP 0x42901230 +#define IG3_FLOC_GLPE_FLOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TIMESTAMP_ROLLOVER 0x42901234 +#define IG3_FLOC_GLPE_FLOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG 0x4290125C +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS 0x42901260 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_FLOC_GLPE_FLOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG 0x4290121C +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_FLOC_GLPE_FLOC_DTM_TRIG_CFG_MODE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_COUNT 0x42901228 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_MASK 0x42901224 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_PATTERN 0x42901220 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_TIMESTAMP 0x4290122C +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_FLOC_GLPE_FLOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_FLOC_GLPE_FLOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PEOC4_GLPEOC_ARPTBLE_OBJOFST 0x42901478 +#define IG3_PEOC4_GLPEOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_CACHESIZE 0x429014E0 +#define IG3_PEOC4_GLPEOC_CACHESIZE_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHESIZE_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHESIZE_WAYS_S 20 +#define IG3_PEOC4_GLPEOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHESIZE_WAYS_S) +#define IG3_PEOC4_GLPEOC_CACHESIZE_SETS_S 8 +#define IG3_PEOC4_GLPEOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_CACHESIZE_SETS_S) +#define IG3_PEOC4_GLPEOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_PEOC4_GLPEOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHESIZE_WORD_SIZE_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL 0x4290156C +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_DATA 0x42901570 +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG 0x42901524 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS 0x42901528 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL 0x42901574 +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_DATA 0x42901578 +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG 0x4290152C +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS 0x42901530 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL 0x4290157C +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_DATA 0x42901580 +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG 0x42901534 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS 0x42901538 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL 0x42901584 +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_DATA 0x42901588 +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG 0x4290153C +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS 0x42901540 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL 0x4290158C +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_DATA 0x42901590 +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG 0x42901544 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS 0x42901548 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL 0x42901594 +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_DATA 0x42901598 +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG 0x4290154C +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS 0x42901550 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL 0x4290159C +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_DATA 0x429015A0 +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG 0x42901554 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS 0x42901558 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL 0x429015A4 +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_DATA 0x429015A8 +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG 0x4290155C +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS 0x42901560 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_CACHE_CTRL 0x42901400 +#define IG3_PEOC4_GLPEOC_CACHE_CTRL_RSVD_S 2 +#define IG3_PEOC4_GLPEOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PEOC4_GLPEOC_CACHE_CTRL_RSVD_S) +#define IG3_PEOC4_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_PEOC4_GLPEOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_PEOC4_GLPEOC_CECC_ERR 0x429014D0 +#define IG3_PEOC4_GLPEOC_CECC_ERR_RSVD1_S 28 +#define IG3_PEOC4_GLPEOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CECC_ERR_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC4_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CECC_ERR_RSVD0_S 12 +#define IG3_PEOC4_GLPEOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_CECC_ERR_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC4_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_CQCTX_OBJOFST 0x42901484 +#define IG3_PEOC4_GLPEOC_CQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_CQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_CQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_CSTATELKUP_CFG 0x429014D8 +#define IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_PEOC4_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_PEOC4_GLPEOC_DPC_COMP 0x429014E8 +#define IG3_PEOC4_GLPEOC_DPC_COMP_RSVD_S 13 +#define IG3_PEOC4_GLPEOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEOC4_GLPEOC_DPC_COMP_RSVD_S) +#define IG3_PEOC4_GLPEOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_PEOC4_GLPEOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_PEOC4_GLPEOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_PEOC4_GLPEOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_DPC_COMP_COMP_FNUM_S) +#define IG3_PEOC4_GLPEOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_PEOC4_GLPEOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DPC_COMP_COMP_VALID_S) +#define IG3_PEOC4_GLPEOC_DPC_REQ 0x429014E4 +#define IG3_PEOC4_GLPEOC_DPC_REQ_RSVD_S 12 +#define IG3_PEOC4_GLPEOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC4_GLPEOC_DPC_REQ_RSVD_S) +#define IG3_PEOC4_GLPEOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_PEOC4_GLPEOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_PEOC4_GLPEOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_PEOC4_GLPEOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_DPC_REQ_REQ_FNUM_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_COUNT 0x42901638 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_CMD 0x4290164C +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_DATA_H 0x42901658 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_DATA_L 0x42901654 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_PTR 0x42901650 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_CMD 0x4290163C +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_DATA_H 0x42901648 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_DATA_L 0x42901644 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_PTR 0x42901640 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC4_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_CONTROL 0x42901600 +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD2_S) +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD3_S) +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_CONTROL_BYPASS_S) +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_DTM_CONTROL_RSVD4_S) +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PEOC4_GLPEOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PEOC4_GLPEOC_DTM_ECC_COR_ERR 0x42901668 +#define IG3_PEOC4_GLPEOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC4_GLPEOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC4_GLPEOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC4_GLPEOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC4_GLPEOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_DTM_ECC_UNCOR_ERR 0x42901664 +#define IG3_PEOC4_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC4_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC4_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC4_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC4_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_DTM_GROUP_CFG 0x4290160C +#define IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PEOC4_GLPEOC_DTM_LOG_CFG 0x42901610 +#define IG3_PEOC4_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PEOC4_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC4_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PEOC4_GLPEOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PEOC4_GLPEOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC4_GLPEOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_DTM_LOG_CFG_MODE_S) +#define IG3_PEOC4_GLPEOC_DTM_LOG_MASK 0x42901618 +#define IG3_PEOC4_GLPEOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_LOG_MASK_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_LOG_PATTERN 0x42901614 +#define IG3_PEOC4_GLPEOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG 0x42901604 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_STS 0x42901608 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC4_GLPEOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_PEOC4_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PEOC4_GLPEOC_DTM_TIMESTAMP 0x42901630 +#define IG3_PEOC4_GLPEOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_TIMESTAMP_ROLLOVER 0x42901634 +#define IG3_PEOC4_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG 0x4290165C +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS 0x42901660 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG 0x4290161C +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_DTM_TRIG_CFG_MODE_S) +#define IG3_PEOC4_GLPEOC_DTM_TRIG_COUNT 0x42901628 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_TRIG_MASK 0x42901624 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_TRIG_PATTERN 0x42901620 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PEOC4_GLPEOC_DTM_TRIG_TIMESTAMP 0x4290162C +#define IG3_PEOC4_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC4_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PEOC4_GLPEOC_ECC_CTL 0x429014C8 +#define IG3_PEOC4_GLPEOC_ECC_CTL_RSVD_S 8 +#define IG3_PEOC4_GLPEOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_ECC_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_ERRDATA0 0x429014B8 +#define IG3_PEOC4_GLPEOC_ERRDATA0_RSVD1_S 31 +#define IG3_PEOC4_GLPEOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ERRDATA0_RSVD1_S) +#define IG3_PEOC4_GLPEOC_ERRDATA0_PF_NUM_S 25 +#define IG3_PEOC4_GLPEOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PEOC4_GLPEOC_ERRDATA0_PF_NUM_S) +#define IG3_PEOC4_GLPEOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_PEOC4_GLPEOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_PEOC4_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_PEOC4_GLPEOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_PEOC4_GLPEOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_PEOC4_GLPEOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_PEOC4_GLPEOC_ERRDATA0_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_ERRDATA0_RSVD0_S) +#define IG3_PEOC4_GLPEOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_PEOC4_GLPEOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_PEOC4_GLPEOC_ERRDATA0_ERROR_CODE_S) +#define IG3_PEOC4_GLPEOC_ERRDATA1 0x429014BC +#define IG3_PEOC4_GLPEOC_ERRDATA1_RSVD_S 28 +#define IG3_PEOC4_GLPEOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_ERRDATA1_RSVD_S) +#define IG3_PEOC4_GLPEOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_PEOC4_GLPEOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PEOC4_GLPEOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_PEOC4_GLPEOC_ERRDATA2 0x429014C0 +#define IG3_PEOC4_GLPEOC_ERRDATA2_RSVD_S 23 +#define IG3_PEOC4_GLPEOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PEOC4_GLPEOC_ERRDATA2_RSVD_S) +#define IG3_PEOC4_GLPEOC_ERRDATA2_OPTYPE_S 20 +#define IG3_PEOC4_GLPEOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_PEOC4_GLPEOC_ERRDATA2_OPTYPE_S) +#define IG3_PEOC4_GLPEOC_ERRDATA2_OFFSET_S 7 +#define IG3_PEOC4_GLPEOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_PEOC4_GLPEOC_ERRDATA2_OFFSET_S) +#define IG3_PEOC4_GLPEOC_ERRDATA2_LENGTH_S 0 +#define IG3_PEOC4_GLPEOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_ERRDATA2_LENGTH_S) +#define IG3_PEOC4_GLPEOC_ERRDATA3 0x429014C4 +#define IG3_PEOC4_GLPEOC_ERRDATA3_RSVD_S 15 +#define IG3_PEOC4_GLPEOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC4_GLPEOC_ERRDATA3_RSVD_S) +#define IG3_PEOC4_GLPEOC_ERRDATA3_TAG_S 0 +#define IG3_PEOC4_GLPEOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC4_GLPEOC_ERRDATA3_TAG_S) +#define IG3_PEOC4_GLPEOC_ERRINFO 0x429014B4 +#define IG3_PEOC4_GLPEOC_ERRINFO_RSVD1_S 16 +#define IG3_PEOC4_GLPEOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC4_GLPEOC_ERRINFO_RSVD1_S) +#define IG3_PEOC4_GLPEOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_PEOC4_GLPEOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_ERRINFO_ERROR_CNT_S) +#define IG3_PEOC4_GLPEOC_ERRINFO_RSVD0_S 1 +#define IG3_PEOC4_GLPEOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_ERRINFO_RSVD0_S) +#define IG3_PEOC4_GLPEOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_PEOC4_GLPEOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_ERRINFO_ERROR_VALID_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG 0x4290151C +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS 0x42901520 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG 0x42901514 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS 0x42901518 +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_FSIADR_OBJOFST 0x4290148C +#define IG3_PEOC4_GLPEOC_FSIADR_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_FSIADR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_FSIADR_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_FSIMCAST_OBJOFST 0x42901490 +#define IG3_PEOC4_GLPEOC_FSIMCAST_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_FSIMCAST_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_FSIMCAST_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_HDR_OBJOFST 0x429014A0 +#define IG3_PEOC4_GLPEOC_HDR_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_HDR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_HDR_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_HECC_ERR 0x429014CC +#define IG3_PEOC4_GLPEOC_HECC_ERR_RSVD1_S 28 +#define IG3_PEOC4_GLPEOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_HECC_ERR_RSVD1_S) +#define IG3_PEOC4_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC4_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_HECC_ERR_RSVD0_S 12 +#define IG3_PEOC4_GLPEOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_HECC_ERR_RSVD0_S) +#define IG3_PEOC4_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC4_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_IRRQ_OBJOFST 0x42901480 +#define IG3_PEOC4_GLPEOC_IRRQ_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_IRRQ_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_IRRQ_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_MAXOSR 0x429014D4 +#define IG3_PEOC4_GLPEOC_MAXOSR_RSVD1_S 15 +#define IG3_PEOC4_GLPEOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC4_GLPEOC_MAXOSR_RSVD1_S) +#define IG3_PEOC4_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 10 +#define IG3_PEOC4_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_PEOC4_GLPEOC_MAXOSR_RSVD0_S 8 +#define IG3_PEOC4_GLPEOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_MAXOSR_RSVD0_S) +#define IG3_PEOC4_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_PEOC4_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_PEOC4_GLPEOC_MEM_ECC_COR_ERR 0x429015B8 +#define IG3_PEOC4_GLPEOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC4_GLPEOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC4_GLPEOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC4_GLPEOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC4_GLPEOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_MEM_ECC_UNCOR_ERR 0x429015B4 +#define IG3_PEOC4_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC4_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC4_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC4_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC4_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC4_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_OOISCFL_OBJOFST 0x429014B0 +#define IG3_PEOC4_GLPEOC_OOISCFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_OOISCFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_OOISCFL_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_OOISC_OBJOFST 0x429014AC +#define IG3_PEOC4_GLPEOC_OOISC_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_OOISC_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_OOISC_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL 0x429015AC +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_PLIST_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_PLIST_DBG_DATA 0x429015B0 +#define IG3_PEOC4_GLPEOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG 0x4290150C +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS 0x42901510 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_PMATINV_CFG 0x429014DC +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_RSVD_S 6 +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_PEOC4_GLPEOC_PMATINV_CFG_RSVD_S) +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_PEOC4_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_PEOC4_GLPEOC_Q1FL_OBJOFST 0x42901498 +#define IG3_PEOC4_GLPEOC_Q1FL_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_Q1FL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_Q1FL_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_RRFL_OBJOFST 0x429014A8 +#define IG3_PEOC4_GLPEOC_RRFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_RRFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_RRFL_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_RRF_OBJOFST 0x429014A4 +#define IG3_PEOC4_GLPEOC_RRF_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_RRF_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_RRF_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_SRQCTX_OBJOFST 0x42901488 +#define IG3_PEOC4_GLPEOC_SRQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_SRQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_SRQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_STAT_CTL 0x42901404 +#define IG3_PEOC4_GLPEOC_STAT_CTL_RSVD_S 5 +#define IG3_PEOC4_GLPEOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PEOC4_GLPEOC_STAT_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_PEOC4_GLPEOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_HI 0x4290146C +#define IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_LO 0x42901468 +#define IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_ENTRIES 0x4290144C +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH 0x42901454 +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS 0x42901450 +#define IG3_PEOC4_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_PEOC4_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_OBJ_CNT 0x42901408 +#define IG3_PEOC4_GLPEOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_PEOC4_GLPEOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_PEOC4_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC4_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_HI 0x42901464 +#define IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_LO 0x42901460 +#define IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_HI 0x42901430 +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_LO 0x4290142C +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_HI 0x42901438 +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_LO 0x42901434 +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_HIT_HI 0x42901410 +#define IG3_PEOC4_GLPEOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_HIT_LO 0x4290140C +#define IG3_PEOC4_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_MISS_HI 0x42901418 +#define IG3_PEOC4_GLPEOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_RD_MISS_LO 0x42901414 +#define IG3_PEOC4_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_HI 0x42901474 +#define IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_LO 0x42901470 +#define IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_HI 0x4290145C +#define IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_LO 0x42901458 +#define IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_HI 0x42901440 +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_LO 0x4290143C +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_HI 0x42901448 +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_LO 0x42901444 +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_HIT_HI 0x42901420 +#define IG3_PEOC4_GLPEOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_HIT_LO 0x4290141C +#define IG3_PEOC4_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_MISS_HI 0x42901428 +#define IG3_PEOC4_GLPEOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_STAT_WR_MISS_LO 0x42901424 +#define IG3_PEOC4_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL 0x42901564 +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_DBG_CTL_DONE_S) +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_TAG_DBG_CTL_RSVD_S) +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_PEOC4_GLPEOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_TAG_DBG_CTL_ADR_S) +#define IG3_PEOC4_GLPEOC_TAG_DBG_DATA 0x42901568 +#define IG3_PEOC4_GLPEOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC4_GLPEOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG 0x429014FC +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS 0x42901500 +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_TIMER_OBJOFST 0x4290149C +#define IG3_PEOC4_GLPEOC_TIMER_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_TIMER_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_TIMER_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HI 0x429014F0 +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_HI 0x429014F8 +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_LO 0x429014F4 +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_LO 0x429014EC +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_PEOC4_GLPEOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC4_GLPEOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_PEOC4_GLPEOC_TXFIFO_OBJOFST 0x4290147C +#define IG3_PEOC4_GLPEOC_TXFIFO_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_TXFIFO_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_TXFIFO_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG 0x42901504 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RM_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RME_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS 0x42901508 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC4_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC4_GLPEOC_XFFL_OBJOFST 0x42901494 +#define IG3_PEOC4_GLPEOC_XFFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC4_GLPEOC_XFFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC4_GLPEOC_XFFL_OBJOFST_RSVD_S) +#define IG3_PEOC4_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC4_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC4_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_ARPTBLE_OBJOFST 0x42901878 +#define IG3_PEOC6_GLPEOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_CACHESIZE 0x429018E0 +#define IG3_PEOC6_GLPEOC_CACHESIZE_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHESIZE_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHESIZE_WAYS_S 20 +#define IG3_PEOC6_GLPEOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHESIZE_WAYS_S) +#define IG3_PEOC6_GLPEOC_CACHESIZE_SETS_S 8 +#define IG3_PEOC6_GLPEOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_CACHESIZE_SETS_S) +#define IG3_PEOC6_GLPEOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_PEOC6_GLPEOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHESIZE_WORD_SIZE_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL 0x4290196C +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_DATA 0x42901970 +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG 0x42901924 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS 0x42901928 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL 0x42901974 +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_DATA 0x42901978 +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG 0x4290192C +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS 0x42901930 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL 0x4290197C +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_DATA 0x42901980 +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG 0x42901934 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS 0x42901938 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL 0x42901984 +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_DATA 0x42901988 +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG 0x4290193C +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS 0x42901940 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL 0x4290198C +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_DATA 0x42901990 +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG 0x42901944 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS 0x42901948 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL 0x42901994 +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_DATA 0x42901998 +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG 0x4290194C +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS 0x42901950 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL 0x4290199C +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_DATA 0x429019A0 +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG 0x42901954 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS 0x42901958 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL 0x429019A4 +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_DATA 0x429019A8 +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG 0x4290195C +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS 0x42901960 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_CACHE_CTRL 0x42901800 +#define IG3_PEOC6_GLPEOC_CACHE_CTRL_RSVD_S 2 +#define IG3_PEOC6_GLPEOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PEOC6_GLPEOC_CACHE_CTRL_RSVD_S) +#define IG3_PEOC6_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_PEOC6_GLPEOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_PEOC6_GLPEOC_CECC_ERR 0x429018D0 +#define IG3_PEOC6_GLPEOC_CECC_ERR_RSVD1_S 28 +#define IG3_PEOC6_GLPEOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CECC_ERR_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC6_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CECC_ERR_RSVD0_S 12 +#define IG3_PEOC6_GLPEOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_CECC_ERR_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC6_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_CQCTX_OBJOFST 0x42901884 +#define IG3_PEOC6_GLPEOC_CQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_CQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_CQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_CSTATELKUP_CFG 0x429018D8 +#define IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_PEOC6_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_PEOC6_GLPEOC_DPC_COMP 0x429018E8 +#define IG3_PEOC6_GLPEOC_DPC_COMP_RSVD_S 13 +#define IG3_PEOC6_GLPEOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEOC6_GLPEOC_DPC_COMP_RSVD_S) +#define IG3_PEOC6_GLPEOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_PEOC6_GLPEOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_PEOC6_GLPEOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_PEOC6_GLPEOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_DPC_COMP_COMP_FNUM_S) +#define IG3_PEOC6_GLPEOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_PEOC6_GLPEOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DPC_COMP_COMP_VALID_S) +#define IG3_PEOC6_GLPEOC_DPC_REQ 0x429018E4 +#define IG3_PEOC6_GLPEOC_DPC_REQ_RSVD_S 12 +#define IG3_PEOC6_GLPEOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC6_GLPEOC_DPC_REQ_RSVD_S) +#define IG3_PEOC6_GLPEOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_PEOC6_GLPEOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_PEOC6_GLPEOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_PEOC6_GLPEOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_DPC_REQ_REQ_FNUM_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_COUNT 0x42901A38 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_CMD 0x42901A4C +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_DATA_H 0x42901A58 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_DATA_L 0x42901A54 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_PTR 0x42901A50 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_CMD 0x42901A3C +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_DATA_H 0x42901A48 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_DATA_L 0x42901A44 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_PTR 0x42901A40 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC6_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_CONTROL 0x42901A00 +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD2_S) +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD3_S) +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_CONTROL_BYPASS_S) +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_DTM_CONTROL_RSVD4_S) +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PEOC6_GLPEOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PEOC6_GLPEOC_DTM_ECC_COR_ERR 0x42901A68 +#define IG3_PEOC6_GLPEOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC6_GLPEOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC6_GLPEOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC6_GLPEOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC6_GLPEOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_DTM_ECC_UNCOR_ERR 0x42901A64 +#define IG3_PEOC6_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC6_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC6_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC6_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC6_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_DTM_GROUP_CFG 0x42901A0C +#define IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PEOC6_GLPEOC_DTM_LOG_CFG 0x42901A10 +#define IG3_PEOC6_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PEOC6_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC6_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PEOC6_GLPEOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PEOC6_GLPEOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC6_GLPEOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_DTM_LOG_CFG_MODE_S) +#define IG3_PEOC6_GLPEOC_DTM_LOG_MASK 0x42901A18 +#define IG3_PEOC6_GLPEOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_LOG_MASK_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_LOG_PATTERN 0x42901A14 +#define IG3_PEOC6_GLPEOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG 0x42901A04 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_STS 0x42901A08 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC6_GLPEOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_PEOC6_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PEOC6_GLPEOC_DTM_TIMESTAMP 0x42901A30 +#define IG3_PEOC6_GLPEOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_TIMESTAMP_ROLLOVER 0x42901A34 +#define IG3_PEOC6_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG 0x42901A5C +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS 0x42901A60 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG 0x42901A1C +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_DTM_TRIG_CFG_MODE_S) +#define IG3_PEOC6_GLPEOC_DTM_TRIG_COUNT 0x42901A28 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_TRIG_MASK 0x42901A24 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_TRIG_PATTERN 0x42901A20 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PEOC6_GLPEOC_DTM_TRIG_TIMESTAMP 0x42901A2C +#define IG3_PEOC6_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC6_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PEOC6_GLPEOC_ECC_CTL 0x429018C8 +#define IG3_PEOC6_GLPEOC_ECC_CTL_RSVD_S 8 +#define IG3_PEOC6_GLPEOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_ECC_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_ERRDATA0 0x429018B8 +#define IG3_PEOC6_GLPEOC_ERRDATA0_RSVD1_S 31 +#define IG3_PEOC6_GLPEOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ERRDATA0_RSVD1_S) +#define IG3_PEOC6_GLPEOC_ERRDATA0_PF_NUM_S 25 +#define IG3_PEOC6_GLPEOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PEOC6_GLPEOC_ERRDATA0_PF_NUM_S) +#define IG3_PEOC6_GLPEOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_PEOC6_GLPEOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_PEOC6_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_PEOC6_GLPEOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_PEOC6_GLPEOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_PEOC6_GLPEOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_PEOC6_GLPEOC_ERRDATA0_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_ERRDATA0_RSVD0_S) +#define IG3_PEOC6_GLPEOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_PEOC6_GLPEOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_PEOC6_GLPEOC_ERRDATA0_ERROR_CODE_S) +#define IG3_PEOC6_GLPEOC_ERRDATA1 0x429018BC +#define IG3_PEOC6_GLPEOC_ERRDATA1_RSVD_S 28 +#define IG3_PEOC6_GLPEOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_ERRDATA1_RSVD_S) +#define IG3_PEOC6_GLPEOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_PEOC6_GLPEOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PEOC6_GLPEOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_PEOC6_GLPEOC_ERRDATA2 0x429018C0 +#define IG3_PEOC6_GLPEOC_ERRDATA2_RSVD_S 23 +#define IG3_PEOC6_GLPEOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PEOC6_GLPEOC_ERRDATA2_RSVD_S) +#define IG3_PEOC6_GLPEOC_ERRDATA2_OPTYPE_S 20 +#define IG3_PEOC6_GLPEOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_PEOC6_GLPEOC_ERRDATA2_OPTYPE_S) +#define IG3_PEOC6_GLPEOC_ERRDATA2_OFFSET_S 7 +#define IG3_PEOC6_GLPEOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_PEOC6_GLPEOC_ERRDATA2_OFFSET_S) +#define IG3_PEOC6_GLPEOC_ERRDATA2_LENGTH_S 0 +#define IG3_PEOC6_GLPEOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_ERRDATA2_LENGTH_S) +#define IG3_PEOC6_GLPEOC_ERRDATA3 0x429018C4 +#define IG3_PEOC6_GLPEOC_ERRDATA3_RSVD_S 15 +#define IG3_PEOC6_GLPEOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC6_GLPEOC_ERRDATA3_RSVD_S) +#define IG3_PEOC6_GLPEOC_ERRDATA3_TAG_S 0 +#define IG3_PEOC6_GLPEOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC6_GLPEOC_ERRDATA3_TAG_S) +#define IG3_PEOC6_GLPEOC_ERRINFO 0x429018B4 +#define IG3_PEOC6_GLPEOC_ERRINFO_RSVD1_S 16 +#define IG3_PEOC6_GLPEOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC6_GLPEOC_ERRINFO_RSVD1_S) +#define IG3_PEOC6_GLPEOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_PEOC6_GLPEOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_ERRINFO_ERROR_CNT_S) +#define IG3_PEOC6_GLPEOC_ERRINFO_RSVD0_S 1 +#define IG3_PEOC6_GLPEOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_ERRINFO_RSVD0_S) +#define IG3_PEOC6_GLPEOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_PEOC6_GLPEOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_ERRINFO_ERROR_VALID_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG 0x4290191C +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS 0x42901920 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG 0x42901914 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS 0x42901918 +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_FSIADR_OBJOFST 0x4290188C +#define IG3_PEOC6_GLPEOC_FSIADR_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_FSIADR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_FSIADR_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_FSIMCAST_OBJOFST 0x42901890 +#define IG3_PEOC6_GLPEOC_FSIMCAST_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_FSIMCAST_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_FSIMCAST_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_HDR_OBJOFST 0x429018A0 +#define IG3_PEOC6_GLPEOC_HDR_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_HDR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_HDR_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_HECC_ERR 0x429018CC +#define IG3_PEOC6_GLPEOC_HECC_ERR_RSVD1_S 28 +#define IG3_PEOC6_GLPEOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_HECC_ERR_RSVD1_S) +#define IG3_PEOC6_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC6_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_HECC_ERR_RSVD0_S 12 +#define IG3_PEOC6_GLPEOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_HECC_ERR_RSVD0_S) +#define IG3_PEOC6_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC6_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_IRRQ_OBJOFST 0x42901880 +#define IG3_PEOC6_GLPEOC_IRRQ_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_IRRQ_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_IRRQ_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_MAXOSR 0x429018D4 +#define IG3_PEOC6_GLPEOC_MAXOSR_RSVD1_S 15 +#define IG3_PEOC6_GLPEOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC6_GLPEOC_MAXOSR_RSVD1_S) +#define IG3_PEOC6_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 10 +#define IG3_PEOC6_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_PEOC6_GLPEOC_MAXOSR_RSVD0_S 8 +#define IG3_PEOC6_GLPEOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_MAXOSR_RSVD0_S) +#define IG3_PEOC6_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_PEOC6_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_PEOC6_GLPEOC_MEM_ECC_COR_ERR 0x429019B8 +#define IG3_PEOC6_GLPEOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC6_GLPEOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC6_GLPEOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC6_GLPEOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC6_GLPEOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_MEM_ECC_UNCOR_ERR 0x429019B4 +#define IG3_PEOC6_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC6_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC6_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC6_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC6_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC6_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_OOISCFL_OBJOFST 0x429018B0 +#define IG3_PEOC6_GLPEOC_OOISCFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_OOISCFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_OOISCFL_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_OOISC_OBJOFST 0x429018AC +#define IG3_PEOC6_GLPEOC_OOISC_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_OOISC_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_OOISC_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL 0x429019AC +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_PLIST_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_PLIST_DBG_DATA 0x429019B0 +#define IG3_PEOC6_GLPEOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG 0x4290190C +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS 0x42901910 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_PMATINV_CFG 0x429018DC +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_RSVD_S 6 +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_PEOC6_GLPEOC_PMATINV_CFG_RSVD_S) +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_PEOC6_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_PEOC6_GLPEOC_Q1FL_OBJOFST 0x42901898 +#define IG3_PEOC6_GLPEOC_Q1FL_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_Q1FL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_Q1FL_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_RRFL_OBJOFST 0x429018A8 +#define IG3_PEOC6_GLPEOC_RRFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_RRFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_RRFL_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_RRF_OBJOFST 0x429018A4 +#define IG3_PEOC6_GLPEOC_RRF_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_RRF_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_RRF_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_SRQCTX_OBJOFST 0x42901888 +#define IG3_PEOC6_GLPEOC_SRQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_SRQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_SRQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_STAT_CTL 0x42901804 +#define IG3_PEOC6_GLPEOC_STAT_CTL_RSVD_S 5 +#define IG3_PEOC6_GLPEOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PEOC6_GLPEOC_STAT_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_PEOC6_GLPEOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_HI 0x4290186C +#define IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_LO 0x42901868 +#define IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_ENTRIES 0x4290184C +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH 0x42901854 +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS 0x42901850 +#define IG3_PEOC6_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_PEOC6_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_OBJ_CNT 0x42901808 +#define IG3_PEOC6_GLPEOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_PEOC6_GLPEOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_PEOC6_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC6_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_HI 0x42901864 +#define IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_LO 0x42901860 +#define IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_HI 0x42901830 +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_LO 0x4290182C +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_HI 0x42901838 +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_LO 0x42901834 +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_HIT_HI 0x42901810 +#define IG3_PEOC6_GLPEOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_HIT_LO 0x4290180C +#define IG3_PEOC6_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_MISS_HI 0x42901818 +#define IG3_PEOC6_GLPEOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_RD_MISS_LO 0x42901814 +#define IG3_PEOC6_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_HI 0x42901874 +#define IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_LO 0x42901870 +#define IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_HI 0x4290185C +#define IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_LO 0x42901858 +#define IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_HI 0x42901840 +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_LO 0x4290183C +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_HI 0x42901848 +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_LO 0x42901844 +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_HIT_HI 0x42901820 +#define IG3_PEOC6_GLPEOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_HIT_LO 0x4290181C +#define IG3_PEOC6_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_MISS_HI 0x42901828 +#define IG3_PEOC6_GLPEOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_STAT_WR_MISS_LO 0x42901824 +#define IG3_PEOC6_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL 0x42901964 +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_DBG_CTL_DONE_S) +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_TAG_DBG_CTL_RSVD_S) +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_PEOC6_GLPEOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_TAG_DBG_CTL_ADR_S) +#define IG3_PEOC6_GLPEOC_TAG_DBG_DATA 0x42901968 +#define IG3_PEOC6_GLPEOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC6_GLPEOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG 0x429018FC +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS 0x42901900 +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_TIMER_OBJOFST 0x4290189C +#define IG3_PEOC6_GLPEOC_TIMER_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_TIMER_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_TIMER_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HI 0x429018F0 +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_HI 0x429018F8 +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_LO 0x429018F4 +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_LO 0x429018EC +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_PEOC6_GLPEOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC6_GLPEOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_PEOC6_GLPEOC_TXFIFO_OBJOFST 0x4290187C +#define IG3_PEOC6_GLPEOC_TXFIFO_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_TXFIFO_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_TXFIFO_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG 0x42901904 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RM_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RME_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS 0x42901908 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC6_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC6_GLPEOC_XFFL_OBJOFST 0x42901894 +#define IG3_PEOC6_GLPEOC_XFFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC6_GLPEOC_XFFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC6_GLPEOC_XFFL_OBJOFST_RSVD_S) +#define IG3_PEOC6_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC6_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC6_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_ARPTBLE_OBJOFST 0x42901C78 +#define IG3_PEOC7_GLPEOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_CACHESIZE 0x42901CE0 +#define IG3_PEOC7_GLPEOC_CACHESIZE_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHESIZE_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHESIZE_WAYS_S 20 +#define IG3_PEOC7_GLPEOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHESIZE_WAYS_S) +#define IG3_PEOC7_GLPEOC_CACHESIZE_SETS_S 8 +#define IG3_PEOC7_GLPEOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_CACHESIZE_SETS_S) +#define IG3_PEOC7_GLPEOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_PEOC7_GLPEOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHESIZE_WORD_SIZE_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL 0x42901D6C +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_DATA 0x42901D70 +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG 0x42901D24 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS 0x42901D28 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL 0x42901D74 +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_DATA 0x42901D78 +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG 0x42901D2C +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS 0x42901D30 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL 0x42901D7C +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_DATA 0x42901D80 +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG 0x42901D34 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS 0x42901D38 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL 0x42901D84 +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_DATA 0x42901D88 +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG 0x42901D3C +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS 0x42901D40 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL 0x42901D8C +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_DATA 0x42901D90 +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG 0x42901D44 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS 0x42901D48 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL 0x42901D94 +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_DATA 0x42901D98 +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG 0x42901D4C +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS 0x42901D50 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL 0x42901D9C +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_DATA 0x42901DA0 +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG 0x42901D54 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS 0x42901D58 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL 0x42901DA4 +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_DATA 0x42901DA8 +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG 0x42901D5C +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS 0x42901D60 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_CACHE_CTRL 0x42901C00 +#define IG3_PEOC7_GLPEOC_CACHE_CTRL_RSVD_S 2 +#define IG3_PEOC7_GLPEOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PEOC7_GLPEOC_CACHE_CTRL_RSVD_S) +#define IG3_PEOC7_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_PEOC7_GLPEOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_PEOC7_GLPEOC_CECC_ERR 0x42901CD0 +#define IG3_PEOC7_GLPEOC_CECC_ERR_RSVD1_S 28 +#define IG3_PEOC7_GLPEOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CECC_ERR_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC7_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CECC_ERR_RSVD0_S 12 +#define IG3_PEOC7_GLPEOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_CECC_ERR_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC7_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_CQCTX_OBJOFST 0x42901C84 +#define IG3_PEOC7_GLPEOC_CQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_CQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_CQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_CSTATELKUP_CFG 0x42901CD8 +#define IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_PEOC7_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_PEOC7_GLPEOC_DPC_COMP 0x42901CE8 +#define IG3_PEOC7_GLPEOC_DPC_COMP_RSVD_S 13 +#define IG3_PEOC7_GLPEOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEOC7_GLPEOC_DPC_COMP_RSVD_S) +#define IG3_PEOC7_GLPEOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_PEOC7_GLPEOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_PEOC7_GLPEOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_PEOC7_GLPEOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_DPC_COMP_COMP_FNUM_S) +#define IG3_PEOC7_GLPEOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_PEOC7_GLPEOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DPC_COMP_COMP_VALID_S) +#define IG3_PEOC7_GLPEOC_DPC_REQ 0x42901CE4 +#define IG3_PEOC7_GLPEOC_DPC_REQ_RSVD_S 12 +#define IG3_PEOC7_GLPEOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC7_GLPEOC_DPC_REQ_RSVD_S) +#define IG3_PEOC7_GLPEOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_PEOC7_GLPEOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_PEOC7_GLPEOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_PEOC7_GLPEOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_DPC_REQ_REQ_FNUM_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_COUNT 0x42901E38 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_CMD 0x42901E4C +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_DATA_H 0x42901E58 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_DATA_L 0x42901E54 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_PTR 0x42901E50 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_CMD 0x42901E3C +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_DATA_H 0x42901E48 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_DATA_L 0x42901E44 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_PTR 0x42901E40 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC7_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_CONTROL 0x42901E00 +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD2_S) +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD3_S) +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_CONTROL_BYPASS_S) +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_DTM_CONTROL_RSVD4_S) +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PEOC7_GLPEOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PEOC7_GLPEOC_DTM_ECC_COR_ERR 0x42901E68 +#define IG3_PEOC7_GLPEOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC7_GLPEOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC7_GLPEOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC7_GLPEOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC7_GLPEOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_DTM_ECC_UNCOR_ERR 0x42901E64 +#define IG3_PEOC7_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC7_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC7_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC7_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC7_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_DTM_GROUP_CFG 0x42901E0C +#define IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PEOC7_GLPEOC_DTM_LOG_CFG 0x42901E10 +#define IG3_PEOC7_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PEOC7_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC7_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PEOC7_GLPEOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PEOC7_GLPEOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC7_GLPEOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_DTM_LOG_CFG_MODE_S) +#define IG3_PEOC7_GLPEOC_DTM_LOG_MASK 0x42901E18 +#define IG3_PEOC7_GLPEOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_LOG_MASK_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_LOG_PATTERN 0x42901E14 +#define IG3_PEOC7_GLPEOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG 0x42901E04 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_STS 0x42901E08 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC7_GLPEOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_PEOC7_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PEOC7_GLPEOC_DTM_TIMESTAMP 0x42901E30 +#define IG3_PEOC7_GLPEOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_TIMESTAMP_ROLLOVER 0x42901E34 +#define IG3_PEOC7_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG 0x42901E5C +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS 0x42901E60 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG 0x42901E1C +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_DTM_TRIG_CFG_MODE_S) +#define IG3_PEOC7_GLPEOC_DTM_TRIG_COUNT 0x42901E28 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_TRIG_MASK 0x42901E24 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_TRIG_PATTERN 0x42901E20 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PEOC7_GLPEOC_DTM_TRIG_TIMESTAMP 0x42901E2C +#define IG3_PEOC7_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC7_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PEOC7_GLPEOC_ECC_CTL 0x42901CC8 +#define IG3_PEOC7_GLPEOC_ECC_CTL_RSVD_S 8 +#define IG3_PEOC7_GLPEOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_ECC_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_ERRDATA0 0x42901CB8 +#define IG3_PEOC7_GLPEOC_ERRDATA0_RSVD1_S 31 +#define IG3_PEOC7_GLPEOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ERRDATA0_RSVD1_S) +#define IG3_PEOC7_GLPEOC_ERRDATA0_PF_NUM_S 25 +#define IG3_PEOC7_GLPEOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PEOC7_GLPEOC_ERRDATA0_PF_NUM_S) +#define IG3_PEOC7_GLPEOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_PEOC7_GLPEOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_PEOC7_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_PEOC7_GLPEOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_PEOC7_GLPEOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_PEOC7_GLPEOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_PEOC7_GLPEOC_ERRDATA0_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_ERRDATA0_RSVD0_S) +#define IG3_PEOC7_GLPEOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_PEOC7_GLPEOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_PEOC7_GLPEOC_ERRDATA0_ERROR_CODE_S) +#define IG3_PEOC7_GLPEOC_ERRDATA1 0x42901CBC +#define IG3_PEOC7_GLPEOC_ERRDATA1_RSVD_S 28 +#define IG3_PEOC7_GLPEOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_ERRDATA1_RSVD_S) +#define IG3_PEOC7_GLPEOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_PEOC7_GLPEOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PEOC7_GLPEOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_PEOC7_GLPEOC_ERRDATA2 0x42901CC0 +#define IG3_PEOC7_GLPEOC_ERRDATA2_RSVD_S 23 +#define IG3_PEOC7_GLPEOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PEOC7_GLPEOC_ERRDATA2_RSVD_S) +#define IG3_PEOC7_GLPEOC_ERRDATA2_OPTYPE_S 20 +#define IG3_PEOC7_GLPEOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_PEOC7_GLPEOC_ERRDATA2_OPTYPE_S) +#define IG3_PEOC7_GLPEOC_ERRDATA2_OFFSET_S 7 +#define IG3_PEOC7_GLPEOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_PEOC7_GLPEOC_ERRDATA2_OFFSET_S) +#define IG3_PEOC7_GLPEOC_ERRDATA2_LENGTH_S 0 +#define IG3_PEOC7_GLPEOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_ERRDATA2_LENGTH_S) +#define IG3_PEOC7_GLPEOC_ERRDATA3 0x42901CC4 +#define IG3_PEOC7_GLPEOC_ERRDATA3_RSVD_S 15 +#define IG3_PEOC7_GLPEOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC7_GLPEOC_ERRDATA3_RSVD_S) +#define IG3_PEOC7_GLPEOC_ERRDATA3_TAG_S 0 +#define IG3_PEOC7_GLPEOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC7_GLPEOC_ERRDATA3_TAG_S) +#define IG3_PEOC7_GLPEOC_ERRINFO 0x42901CB4 +#define IG3_PEOC7_GLPEOC_ERRINFO_RSVD1_S 16 +#define IG3_PEOC7_GLPEOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC7_GLPEOC_ERRINFO_RSVD1_S) +#define IG3_PEOC7_GLPEOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_PEOC7_GLPEOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_ERRINFO_ERROR_CNT_S) +#define IG3_PEOC7_GLPEOC_ERRINFO_RSVD0_S 1 +#define IG3_PEOC7_GLPEOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_ERRINFO_RSVD0_S) +#define IG3_PEOC7_GLPEOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_PEOC7_GLPEOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_ERRINFO_ERROR_VALID_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG 0x42901D1C +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS 0x42901D20 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG 0x42901D14 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS 0x42901D18 +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_FSIADR_OBJOFST 0x42901C8C +#define IG3_PEOC7_GLPEOC_FSIADR_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_FSIADR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_FSIADR_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_FSIMCAST_OBJOFST 0x42901C90 +#define IG3_PEOC7_GLPEOC_FSIMCAST_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_FSIMCAST_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_FSIMCAST_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_HDR_OBJOFST 0x42901CA0 +#define IG3_PEOC7_GLPEOC_HDR_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_HDR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_HDR_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_HECC_ERR 0x42901CCC +#define IG3_PEOC7_GLPEOC_HECC_ERR_RSVD1_S 28 +#define IG3_PEOC7_GLPEOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_HECC_ERR_RSVD1_S) +#define IG3_PEOC7_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC7_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_HECC_ERR_RSVD0_S 12 +#define IG3_PEOC7_GLPEOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_HECC_ERR_RSVD0_S) +#define IG3_PEOC7_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC7_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_IRRQ_OBJOFST 0x42901C80 +#define IG3_PEOC7_GLPEOC_IRRQ_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_IRRQ_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_IRRQ_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_MAXOSR 0x42901CD4 +#define IG3_PEOC7_GLPEOC_MAXOSR_RSVD1_S 15 +#define IG3_PEOC7_GLPEOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC7_GLPEOC_MAXOSR_RSVD1_S) +#define IG3_PEOC7_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 10 +#define IG3_PEOC7_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_PEOC7_GLPEOC_MAXOSR_RSVD0_S 8 +#define IG3_PEOC7_GLPEOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_MAXOSR_RSVD0_S) +#define IG3_PEOC7_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_PEOC7_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_PEOC7_GLPEOC_MEM_ECC_COR_ERR 0x42901DB8 +#define IG3_PEOC7_GLPEOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC7_GLPEOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC7_GLPEOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC7_GLPEOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC7_GLPEOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_MEM_ECC_UNCOR_ERR 0x42901DB4 +#define IG3_PEOC7_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC7_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC7_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC7_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC7_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC7_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_OOISCFL_OBJOFST 0x42901CB0 +#define IG3_PEOC7_GLPEOC_OOISCFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_OOISCFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_OOISCFL_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_OOISC_OBJOFST 0x42901CAC +#define IG3_PEOC7_GLPEOC_OOISC_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_OOISC_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_OOISC_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL 0x42901DAC +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_PLIST_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_PLIST_DBG_DATA 0x42901DB0 +#define IG3_PEOC7_GLPEOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG 0x42901D0C +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS 0x42901D10 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_PMATINV_CFG 0x42901CDC +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_RSVD_S 6 +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_PEOC7_GLPEOC_PMATINV_CFG_RSVD_S) +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_PEOC7_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_PEOC7_GLPEOC_Q1FL_OBJOFST 0x42901C98 +#define IG3_PEOC7_GLPEOC_Q1FL_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_Q1FL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_Q1FL_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_RRFL_OBJOFST 0x42901CA8 +#define IG3_PEOC7_GLPEOC_RRFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_RRFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_RRFL_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_RRF_OBJOFST 0x42901CA4 +#define IG3_PEOC7_GLPEOC_RRF_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_RRF_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_RRF_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_SRQCTX_OBJOFST 0x42901C88 +#define IG3_PEOC7_GLPEOC_SRQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_SRQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_SRQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_STAT_CTL 0x42901C04 +#define IG3_PEOC7_GLPEOC_STAT_CTL_RSVD_S 5 +#define IG3_PEOC7_GLPEOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PEOC7_GLPEOC_STAT_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_PEOC7_GLPEOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_HI 0x42901C6C +#define IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_LO 0x42901C68 +#define IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_ENTRIES 0x42901C4C +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH 0x42901C54 +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS 0x42901C50 +#define IG3_PEOC7_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_PEOC7_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_OBJ_CNT 0x42901C08 +#define IG3_PEOC7_GLPEOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_PEOC7_GLPEOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_PEOC7_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC7_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_HI 0x42901C64 +#define IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_LO 0x42901C60 +#define IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_HI 0x42901C30 +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_LO 0x42901C2C +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_HI 0x42901C38 +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_LO 0x42901C34 +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_HIT_HI 0x42901C10 +#define IG3_PEOC7_GLPEOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_HIT_LO 0x42901C0C +#define IG3_PEOC7_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_MISS_HI 0x42901C18 +#define IG3_PEOC7_GLPEOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_RD_MISS_LO 0x42901C14 +#define IG3_PEOC7_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_HI 0x42901C74 +#define IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_LO 0x42901C70 +#define IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_HI 0x42901C5C +#define IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_LO 0x42901C58 +#define IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_HI 0x42901C40 +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_LO 0x42901C3C +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_HI 0x42901C48 +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_LO 0x42901C44 +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_HIT_HI 0x42901C20 +#define IG3_PEOC7_GLPEOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_HIT_LO 0x42901C1C +#define IG3_PEOC7_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_MISS_HI 0x42901C28 +#define IG3_PEOC7_GLPEOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_STAT_WR_MISS_LO 0x42901C24 +#define IG3_PEOC7_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL 0x42901D64 +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_DBG_CTL_DONE_S) +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_TAG_DBG_CTL_RSVD_S) +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_PEOC7_GLPEOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_TAG_DBG_CTL_ADR_S) +#define IG3_PEOC7_GLPEOC_TAG_DBG_DATA 0x42901D68 +#define IG3_PEOC7_GLPEOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC7_GLPEOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG 0x42901CFC +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS 0x42901D00 +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_TIMER_OBJOFST 0x42901C9C +#define IG3_PEOC7_GLPEOC_TIMER_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_TIMER_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_TIMER_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HI 0x42901CF0 +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_HI 0x42901CF8 +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_LO 0x42901CF4 +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_LO 0x42901CEC +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_PEOC7_GLPEOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC7_GLPEOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_PEOC7_GLPEOC_TXFIFO_OBJOFST 0x42901C7C +#define IG3_PEOC7_GLPEOC_TXFIFO_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_TXFIFO_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_TXFIFO_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG 0x42901D04 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RM_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RME_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS 0x42901D08 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC7_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC7_GLPEOC_XFFL_OBJOFST 0x42901C94 +#define IG3_PEOC7_GLPEOC_XFFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC7_GLPEOC_XFFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC7_GLPEOC_XFFL_OBJOFST_RSVD_S) +#define IG3_PEOC7_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC7_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC7_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_ARPTBLE_OBJOFST 0x42902078 +#define IG3_PEOC8_GLPEOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_CACHESIZE 0x429020E0 +#define IG3_PEOC8_GLPEOC_CACHESIZE_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHESIZE_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHESIZE_WAYS_S 20 +#define IG3_PEOC8_GLPEOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHESIZE_WAYS_S) +#define IG3_PEOC8_GLPEOC_CACHESIZE_SETS_S 8 +#define IG3_PEOC8_GLPEOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_CACHESIZE_SETS_S) +#define IG3_PEOC8_GLPEOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_PEOC8_GLPEOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHESIZE_WORD_SIZE_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL 0x4290216C +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_DATA 0x42902170 +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG 0x42902124 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS 0x42902128 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL 0x42902174 +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_DATA 0x42902178 +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG 0x4290212C +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS 0x42902130 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL 0x4290217C +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_DATA 0x42902180 +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG 0x42902134 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS 0x42902138 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL 0x42902184 +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_DATA 0x42902188 +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG 0x4290213C +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS 0x42902140 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL 0x4290218C +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_DATA 0x42902190 +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG 0x42902144 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS 0x42902148 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL 0x42902194 +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_DATA 0x42902198 +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG 0x4290214C +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS 0x42902150 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL 0x4290219C +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_DATA 0x429021A0 +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG 0x42902154 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS 0x42902158 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL 0x429021A4 +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_DATA 0x429021A8 +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG 0x4290215C +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS 0x42902160 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_CACHE_CTRL 0x42902000 +#define IG3_PEOC8_GLPEOC_CACHE_CTRL_RSVD_S 2 +#define IG3_PEOC8_GLPEOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PEOC8_GLPEOC_CACHE_CTRL_RSVD_S) +#define IG3_PEOC8_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_PEOC8_GLPEOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_PEOC8_GLPEOC_CECC_ERR 0x429020D0 +#define IG3_PEOC8_GLPEOC_CECC_ERR_RSVD1_S 28 +#define IG3_PEOC8_GLPEOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CECC_ERR_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC8_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CECC_ERR_RSVD0_S 12 +#define IG3_PEOC8_GLPEOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_CECC_ERR_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC8_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_CQCTX_OBJOFST 0x42902084 +#define IG3_PEOC8_GLPEOC_CQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_CQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_CQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_CSTATELKUP_CFG 0x429020D8 +#define IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_PEOC8_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_PEOC8_GLPEOC_DPC_COMP 0x429020E8 +#define IG3_PEOC8_GLPEOC_DPC_COMP_RSVD_S 13 +#define IG3_PEOC8_GLPEOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEOC8_GLPEOC_DPC_COMP_RSVD_S) +#define IG3_PEOC8_GLPEOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_PEOC8_GLPEOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_PEOC8_GLPEOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_PEOC8_GLPEOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_DPC_COMP_COMP_FNUM_S) +#define IG3_PEOC8_GLPEOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_PEOC8_GLPEOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DPC_COMP_COMP_VALID_S) +#define IG3_PEOC8_GLPEOC_DPC_REQ 0x429020E4 +#define IG3_PEOC8_GLPEOC_DPC_REQ_RSVD_S 12 +#define IG3_PEOC8_GLPEOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC8_GLPEOC_DPC_REQ_RSVD_S) +#define IG3_PEOC8_GLPEOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_PEOC8_GLPEOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_PEOC8_GLPEOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_PEOC8_GLPEOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_DPC_REQ_REQ_FNUM_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_COUNT 0x42902238 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_CMD 0x4290224C +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_DATA_H 0x42902258 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_DATA_L 0x42902254 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_PTR 0x42902250 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_CMD 0x4290223C +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_DATA_H 0x42902248 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_DATA_L 0x42902244 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_PTR 0x42902240 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC8_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_CONTROL 0x42902200 +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD2_S) +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD3_S) +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_CONTROL_BYPASS_S) +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_DTM_CONTROL_RSVD4_S) +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PEOC8_GLPEOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PEOC8_GLPEOC_DTM_ECC_COR_ERR 0x42902268 +#define IG3_PEOC8_GLPEOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC8_GLPEOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC8_GLPEOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC8_GLPEOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC8_GLPEOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_DTM_ECC_UNCOR_ERR 0x42902264 +#define IG3_PEOC8_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC8_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC8_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC8_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC8_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_DTM_GROUP_CFG 0x4290220C +#define IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PEOC8_GLPEOC_DTM_LOG_CFG 0x42902210 +#define IG3_PEOC8_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PEOC8_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC8_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PEOC8_GLPEOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PEOC8_GLPEOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC8_GLPEOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_DTM_LOG_CFG_MODE_S) +#define IG3_PEOC8_GLPEOC_DTM_LOG_MASK 0x42902218 +#define IG3_PEOC8_GLPEOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_LOG_MASK_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_LOG_PATTERN 0x42902214 +#define IG3_PEOC8_GLPEOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG 0x42902204 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_STS 0x42902208 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC8_GLPEOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_PEOC8_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PEOC8_GLPEOC_DTM_TIMESTAMP 0x42902230 +#define IG3_PEOC8_GLPEOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_TIMESTAMP_ROLLOVER 0x42902234 +#define IG3_PEOC8_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG 0x4290225C +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS 0x42902260 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG 0x4290221C +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_DTM_TRIG_CFG_MODE_S) +#define IG3_PEOC8_GLPEOC_DTM_TRIG_COUNT 0x42902228 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_TRIG_MASK 0x42902224 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_TRIG_PATTERN 0x42902220 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PEOC8_GLPEOC_DTM_TRIG_TIMESTAMP 0x4290222C +#define IG3_PEOC8_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC8_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PEOC8_GLPEOC_ECC_CTL 0x429020C8 +#define IG3_PEOC8_GLPEOC_ECC_CTL_RSVD_S 8 +#define IG3_PEOC8_GLPEOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_ECC_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_ERRDATA0 0x429020B8 +#define IG3_PEOC8_GLPEOC_ERRDATA0_RSVD1_S 31 +#define IG3_PEOC8_GLPEOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ERRDATA0_RSVD1_S) +#define IG3_PEOC8_GLPEOC_ERRDATA0_PF_NUM_S 25 +#define IG3_PEOC8_GLPEOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PEOC8_GLPEOC_ERRDATA0_PF_NUM_S) +#define IG3_PEOC8_GLPEOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_PEOC8_GLPEOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_PEOC8_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_PEOC8_GLPEOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_PEOC8_GLPEOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_PEOC8_GLPEOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_PEOC8_GLPEOC_ERRDATA0_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_ERRDATA0_RSVD0_S) +#define IG3_PEOC8_GLPEOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_PEOC8_GLPEOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_PEOC8_GLPEOC_ERRDATA0_ERROR_CODE_S) +#define IG3_PEOC8_GLPEOC_ERRDATA1 0x429020BC +#define IG3_PEOC8_GLPEOC_ERRDATA1_RSVD_S 28 +#define IG3_PEOC8_GLPEOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_ERRDATA1_RSVD_S) +#define IG3_PEOC8_GLPEOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_PEOC8_GLPEOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PEOC8_GLPEOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_PEOC8_GLPEOC_ERRDATA2 0x429020C0 +#define IG3_PEOC8_GLPEOC_ERRDATA2_RSVD_S 23 +#define IG3_PEOC8_GLPEOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PEOC8_GLPEOC_ERRDATA2_RSVD_S) +#define IG3_PEOC8_GLPEOC_ERRDATA2_OPTYPE_S 20 +#define IG3_PEOC8_GLPEOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_PEOC8_GLPEOC_ERRDATA2_OPTYPE_S) +#define IG3_PEOC8_GLPEOC_ERRDATA2_OFFSET_S 7 +#define IG3_PEOC8_GLPEOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_PEOC8_GLPEOC_ERRDATA2_OFFSET_S) +#define IG3_PEOC8_GLPEOC_ERRDATA2_LENGTH_S 0 +#define IG3_PEOC8_GLPEOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_ERRDATA2_LENGTH_S) +#define IG3_PEOC8_GLPEOC_ERRDATA3 0x429020C4 +#define IG3_PEOC8_GLPEOC_ERRDATA3_RSVD_S 15 +#define IG3_PEOC8_GLPEOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC8_GLPEOC_ERRDATA3_RSVD_S) +#define IG3_PEOC8_GLPEOC_ERRDATA3_TAG_S 0 +#define IG3_PEOC8_GLPEOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC8_GLPEOC_ERRDATA3_TAG_S) +#define IG3_PEOC8_GLPEOC_ERRINFO 0x429020B4 +#define IG3_PEOC8_GLPEOC_ERRINFO_RSVD1_S 16 +#define IG3_PEOC8_GLPEOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC8_GLPEOC_ERRINFO_RSVD1_S) +#define IG3_PEOC8_GLPEOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_PEOC8_GLPEOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_ERRINFO_ERROR_CNT_S) +#define IG3_PEOC8_GLPEOC_ERRINFO_RSVD0_S 1 +#define IG3_PEOC8_GLPEOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_ERRINFO_RSVD0_S) +#define IG3_PEOC8_GLPEOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_PEOC8_GLPEOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_ERRINFO_ERROR_VALID_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG 0x4290211C +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS 0x42902120 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG 0x42902114 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS 0x42902118 +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_FSIADR_OBJOFST 0x4290208C +#define IG3_PEOC8_GLPEOC_FSIADR_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_FSIADR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_FSIADR_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_FSIMCAST_OBJOFST 0x42902090 +#define IG3_PEOC8_GLPEOC_FSIMCAST_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_FSIMCAST_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_FSIMCAST_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_HDR_OBJOFST 0x429020A0 +#define IG3_PEOC8_GLPEOC_HDR_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_HDR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_HDR_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_HECC_ERR 0x429020CC +#define IG3_PEOC8_GLPEOC_HECC_ERR_RSVD1_S 28 +#define IG3_PEOC8_GLPEOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_HECC_ERR_RSVD1_S) +#define IG3_PEOC8_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC8_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_HECC_ERR_RSVD0_S 12 +#define IG3_PEOC8_GLPEOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_HECC_ERR_RSVD0_S) +#define IG3_PEOC8_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC8_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_IRRQ_OBJOFST 0x42902080 +#define IG3_PEOC8_GLPEOC_IRRQ_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_IRRQ_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_IRRQ_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_MAXOSR 0x429020D4 +#define IG3_PEOC8_GLPEOC_MAXOSR_RSVD1_S 12 +#define IG3_PEOC8_GLPEOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC8_GLPEOC_MAXOSR_RSVD1_S) +#define IG3_PEOC8_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 8 +#define IG3_PEOC8_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_PEOC8_GLPEOC_MAXOSR_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_MAXOSR_RSVD0_S) +#define IG3_PEOC8_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_PEOC8_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0x3F, IG3_PEOC8_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_PEOC8_GLPEOC_MEM_ECC_COR_ERR 0x429021B8 +#define IG3_PEOC8_GLPEOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC8_GLPEOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC8_GLPEOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC8_GLPEOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC8_GLPEOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_MEM_ECC_UNCOR_ERR 0x429021B4 +#define IG3_PEOC8_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC8_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC8_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC8_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC8_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC8_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_OOISCFL_OBJOFST 0x429020B0 +#define IG3_PEOC8_GLPEOC_OOISCFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_OOISCFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_OOISCFL_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_OOISC_OBJOFST 0x429020AC +#define IG3_PEOC8_GLPEOC_OOISC_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_OOISC_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_OOISC_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL 0x429021AC +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_PLIST_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_PLIST_DBG_DATA 0x429021B0 +#define IG3_PEOC8_GLPEOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG 0x4290210C +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS 0x42902110 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_PMATINV_CFG 0x429020DC +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_RSVD_S 6 +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_PEOC8_GLPEOC_PMATINV_CFG_RSVD_S) +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_PEOC8_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_PEOC8_GLPEOC_Q1FL_OBJOFST 0x42902098 +#define IG3_PEOC8_GLPEOC_Q1FL_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_Q1FL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_Q1FL_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_RRFL_OBJOFST 0x429020A8 +#define IG3_PEOC8_GLPEOC_RRFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_RRFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_RRFL_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_RRF_OBJOFST 0x429020A4 +#define IG3_PEOC8_GLPEOC_RRF_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_RRF_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_RRF_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_SRQCTX_OBJOFST 0x42902088 +#define IG3_PEOC8_GLPEOC_SRQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_SRQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_SRQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_STAT_CTL 0x42902004 +#define IG3_PEOC8_GLPEOC_STAT_CTL_RSVD_S 5 +#define IG3_PEOC8_GLPEOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PEOC8_GLPEOC_STAT_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_PEOC8_GLPEOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_HI 0x4290206C +#define IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_LO 0x42902068 +#define IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_ENTRIES 0x4290204C +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH 0x42902054 +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS 0x42902050 +#define IG3_PEOC8_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_PEOC8_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_OBJ_CNT 0x42902008 +#define IG3_PEOC8_GLPEOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_PEOC8_GLPEOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_PEOC8_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC8_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_HI 0x42902064 +#define IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_LO 0x42902060 +#define IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_HI 0x42902030 +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_LO 0x4290202C +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_HI 0x42902038 +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_LO 0x42902034 +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_HIT_HI 0x42902010 +#define IG3_PEOC8_GLPEOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_HIT_LO 0x4290200C +#define IG3_PEOC8_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_MISS_HI 0x42902018 +#define IG3_PEOC8_GLPEOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_RD_MISS_LO 0x42902014 +#define IG3_PEOC8_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_HI 0x42902074 +#define IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_LO 0x42902070 +#define IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_HI 0x4290205C +#define IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_LO 0x42902058 +#define IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_HI 0x42902040 +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_LO 0x4290203C +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_HI 0x42902048 +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_LO 0x42902044 +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_HIT_HI 0x42902020 +#define IG3_PEOC8_GLPEOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_HIT_LO 0x4290201C +#define IG3_PEOC8_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_MISS_HI 0x42902028 +#define IG3_PEOC8_GLPEOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_STAT_WR_MISS_LO 0x42902024 +#define IG3_PEOC8_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL 0x42902164 +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_DBG_CTL_DONE_S) +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_TAG_DBG_CTL_RSVD_S) +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_PEOC8_GLPEOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_TAG_DBG_CTL_ADR_S) +#define IG3_PEOC8_GLPEOC_TAG_DBG_DATA 0x42902168 +#define IG3_PEOC8_GLPEOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC8_GLPEOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG 0x429020FC +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS 0x42902100 +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_TIMER_OBJOFST 0x4290209C +#define IG3_PEOC8_GLPEOC_TIMER_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_TIMER_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_TIMER_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HI 0x429020F0 +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_HI 0x429020F8 +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_LO 0x429020F4 +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_LO 0x429020EC +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_PEOC8_GLPEOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC8_GLPEOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_PEOC8_GLPEOC_TXFIFO_OBJOFST 0x4290207C +#define IG3_PEOC8_GLPEOC_TXFIFO_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_TXFIFO_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_TXFIFO_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG 0x42902104 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RM_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RME_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS 0x42902108 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC8_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC8_GLPEOC_XFFL_OBJOFST 0x42902094 +#define IG3_PEOC8_GLPEOC_XFFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC8_GLPEOC_XFFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC8_GLPEOC_XFFL_OBJOFST_RSVD_S) +#define IG3_PEOC8_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC8_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC8_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_ARPTBLE_OBJOFST 0x42902478 +#define IG3_PEOC9_GLPEOC_ARPTBLE_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_ARPTBLE_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_ARPTBLE_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_ARPTBLE_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_CACHESIZE 0x429024E0 +#define IG3_PEOC9_GLPEOC_CACHESIZE_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_CACHESIZE_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHESIZE_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHESIZE_WAYS_S 20 +#define IG3_PEOC9_GLPEOC_CACHESIZE_WAYS_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHESIZE_WAYS_S) +#define IG3_PEOC9_GLPEOC_CACHESIZE_SETS_S 8 +#define IG3_PEOC9_GLPEOC_CACHESIZE_SETS_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_CACHESIZE_SETS_S) +#define IG3_PEOC9_GLPEOC_CACHESIZE_WORD_SIZE_S 0 +#define IG3_PEOC9_GLPEOC_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHESIZE_WORD_SIZE_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL 0x4290256C +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_0_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_DATA 0x42902570 +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_CACHE_0_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG 0x42902524 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS 0x42902528 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_0_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL 0x42902574 +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_1_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_DATA 0x42902578 +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_CACHE_1_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG 0x4290252C +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS 0x42902530 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_1_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL 0x4290257C +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_2_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_DATA 0x42902580 +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_CACHE_2_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG 0x42902534 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS 0x42902538 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_2_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL 0x42902584 +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_3_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_DATA 0x42902588 +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_CACHE_3_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG 0x4290253C +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS 0x42902540 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_3_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL 0x4290258C +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_4_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_DATA 0x42902590 +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_4_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_CACHE_4_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG 0x42902544 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS 0x42902548 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_4_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL 0x42902594 +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_5_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_DATA 0x42902598 +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_5_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_CACHE_5_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG 0x4290254C +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS 0x42902550 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_5_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL 0x4290259C +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_6_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_DATA 0x429025A0 +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_6_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_CACHE_6_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG 0x42902554 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS 0x42902558 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_6_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL 0x429025A4 +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_7_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_DATA 0x429025A8 +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_7_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_CACHE_7_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG 0x4290255C +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS 0x42902560 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CACHE_7_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_CACHE_CTRL 0x42902400 +#define IG3_PEOC9_GLPEOC_CACHE_CTRL_RSVD_S 2 +#define IG3_PEOC9_GLPEOC_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_PEOC9_GLPEOC_CACHE_CTRL_RSVD_S) +#define IG3_PEOC9_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S 0 +#define IG3_PEOC9_GLPEOC_CACHE_CTRL_SCALE_FACTOR_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_CACHE_CTRL_SCALE_FACTOR_S) +#define IG3_PEOC9_GLPEOC_CECC_ERR 0x429024D0 +#define IG3_PEOC9_GLPEOC_CECC_ERR_RSVD1_S 28 +#define IG3_PEOC9_GLPEOC_CECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CECC_ERR_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC9_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_CECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CECC_ERR_RSVD0_S 12 +#define IG3_PEOC9_GLPEOC_CECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_CECC_ERR_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC9_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_CECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_CQCTX_OBJOFST 0x42902484 +#define IG3_PEOC9_GLPEOC_CQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_CQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_CQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_CQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_CSTATELKUP_CFG 0x429024D8 +#define IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_RSVD1_S 9 +#define IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S 8 +#define IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_LKUP_REPLAY_ON_PEND_CLR_S) +#define IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_RSVD0_S 3 +#define IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S 0 +#define IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_M RDMA_MASK3(32, 0x7, IG3_PEOC9_GLPEOC_CSTATELKUP_CFG_LKUP_RATE_LIMIT_WTCYCLES_S) +#define IG3_PEOC9_GLPEOC_DPC_COMP 0x429024E8 +#define IG3_PEOC9_GLPEOC_DPC_COMP_RSVD_S 13 +#define IG3_PEOC9_GLPEOC_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_PEOC9_GLPEOC_DPC_COMP_RSVD_S) +#define IG3_PEOC9_GLPEOC_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_PEOC9_GLPEOC_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_DPC_COMP_COMP_FTYPE_S) +#define IG3_PEOC9_GLPEOC_DPC_COMP_COMP_FNUM_S 1 +#define IG3_PEOC9_GLPEOC_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_DPC_COMP_COMP_FNUM_S) +#define IG3_PEOC9_GLPEOC_DPC_COMP_COMP_VALID_S 0 +#define IG3_PEOC9_GLPEOC_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DPC_COMP_COMP_VALID_S) +#define IG3_PEOC9_GLPEOC_DPC_REQ 0x429024E4 +#define IG3_PEOC9_GLPEOC_DPC_REQ_RSVD_S 12 +#define IG3_PEOC9_GLPEOC_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC9_GLPEOC_DPC_REQ_RSVD_S) +#define IG3_PEOC9_GLPEOC_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_PEOC9_GLPEOC_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_DPC_REQ_REQ_FTYPE_S) +#define IG3_PEOC9_GLPEOC_DPC_REQ_REQ_FNUM_S 0 +#define IG3_PEOC9_GLPEOC_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_DPC_REQ_REQ_FNUM_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_COUNT 0x42902638 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_CMD 0x4290264C +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_DATA_H 0x42902658 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_DATA_L 0x42902654 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_PTR 0x42902650 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_CMD 0x4290263C +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_DATA_H 0x42902648 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_DATA_L 0x42902644 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_PTR 0x42902640 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC9_GLPEOC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_CONTROL 0x42902600 +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD1_S 25 +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD2_S 17 +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD2_S) +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD3_S 9 +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD3_S) +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_BYPASS_S 8 +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_CONTROL_BYPASS_S) +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD4_S 1 +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_DTM_CONTROL_RSVD4_S) +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PEOC9_GLPEOC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PEOC9_GLPEOC_DTM_ECC_COR_ERR 0x42902668 +#define IG3_PEOC9_GLPEOC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC9_GLPEOC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC9_GLPEOC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC9_GLPEOC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC9_GLPEOC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_DTM_ECC_UNCOR_ERR 0x42902664 +#define IG3_PEOC9_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC9_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC9_GLPEOC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC9_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC9_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_DTM_GROUP_CFG 0x4290260C +#define IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PEOC9_GLPEOC_DTM_LOG_CFG 0x42902610 +#define IG3_PEOC9_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PEOC9_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC9_GLPEOC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PEOC9_GLPEOC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PEOC9_GLPEOC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC9_GLPEOC_DTM_LOG_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_LOG_CFG_MODE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_DTM_LOG_CFG_MODE_S) +#define IG3_PEOC9_GLPEOC_DTM_LOG_MASK 0x42902618 +#define IG3_PEOC9_GLPEOC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_LOG_MASK_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_LOG_PATTERN 0x42902614 +#define IG3_PEOC9_GLPEOC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG 0x42902604 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_STS 0x42902608 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PEOC9_GLPEOC_DTM_MAIN_STS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_DTM_MAIN_STS_RSVD2_S) +#define IG3_PEOC9_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PEOC9_GLPEOC_DTM_TIMESTAMP 0x42902630 +#define IG3_PEOC9_GLPEOC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_TIMESTAMP_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_TIMESTAMP_ROLLOVER 0x42902634 +#define IG3_PEOC9_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG 0x4290265C +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS 0x42902660 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG 0x4290261C +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_DTM_TRIG_CFG_MODE_S) +#define IG3_PEOC9_GLPEOC_DTM_TRIG_COUNT 0x42902628 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_TRIG_MASK 0x42902624 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_TRIG_MASK_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_TRIG_PATTERN 0x42902620 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PEOC9_GLPEOC_DTM_TRIG_TIMESTAMP 0x4290262C +#define IG3_PEOC9_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PEOC9_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PEOC9_GLPEOC_ECC_CTL 0x429024C8 +#define IG3_PEOC9_GLPEOC_ECC_CTL_RSVD_S 8 +#define IG3_PEOC9_GLPEOC_ECC_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_ECC_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S 7 +#define IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT2_S) +#define IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S 6 +#define IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_INVERT1_S) +#define IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S 4 +#define IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ECC_CTL_CLIENT_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S 3 +#define IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_INVERT2_S) +#define IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S 2 +#define IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_INVERT1_S) +#define IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S 1 +#define IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ECC_CTL_HOST_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_ERRDATA0 0x429024B8 +#define IG3_PEOC9_GLPEOC_ERRDATA0_RSVD1_S 31 +#define IG3_PEOC9_GLPEOC_ERRDATA0_RSVD1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ERRDATA0_RSVD1_S) +#define IG3_PEOC9_GLPEOC_ERRDATA0_PF_NUM_S 25 +#define IG3_PEOC9_GLPEOC_ERRDATA0_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PEOC9_GLPEOC_ERRDATA0_PF_NUM_S) +#define IG3_PEOC9_GLPEOC_ERRDATA0_VDEV_VF_NUM_S 15 +#define IG3_PEOC9_GLPEOC_ERRDATA0_VDEV_VF_NUM_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_ERRDATA0_VDEV_VF_NUM_S) +#define IG3_PEOC9_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S 13 +#define IG3_PEOC9_GLPEOC_ERRDATA0_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_ERRDATA0_VDEV_VF_TYPE_S) +#define IG3_PEOC9_GLPEOC_ERRDATA0_OBJ_TYPE_S 8 +#define IG3_PEOC9_GLPEOC_ERRDATA0_OBJ_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_ERRDATA0_OBJ_TYPE_S) +#define IG3_PEOC9_GLPEOC_ERRDATA0_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_ERRDATA0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_ERRDATA0_RSVD0_S) +#define IG3_PEOC9_GLPEOC_ERRDATA0_ERROR_CODE_S 0 +#define IG3_PEOC9_GLPEOC_ERRDATA0_ERROR_CODE_M RDMA_MASK3(32, 0x3F, IG3_PEOC9_GLPEOC_ERRDATA0_ERROR_CODE_S) +#define IG3_PEOC9_GLPEOC_ERRDATA1 0x429024BC +#define IG3_PEOC9_GLPEOC_ERRDATA1_RSVD_S 28 +#define IG3_PEOC9_GLPEOC_ERRDATA1_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_ERRDATA1_RSVD_S) +#define IG3_PEOC9_GLPEOC_ERRDATA1_OBJ_INDEX_S 0 +#define IG3_PEOC9_GLPEOC_ERRDATA1_OBJ_INDEX_M RDMA_MASK3(32, 0xFFFFFFF, IG3_PEOC9_GLPEOC_ERRDATA1_OBJ_INDEX_S) +#define IG3_PEOC9_GLPEOC_ERRDATA2 0x429024C0 +#define IG3_PEOC9_GLPEOC_ERRDATA2_RSVD_S 23 +#define IG3_PEOC9_GLPEOC_ERRDATA2_RSVD_M RDMA_MASK3(32, 0x1FF, IG3_PEOC9_GLPEOC_ERRDATA2_RSVD_S) +#define IG3_PEOC9_GLPEOC_ERRDATA2_OPTYPE_S 20 +#define IG3_PEOC9_GLPEOC_ERRDATA2_OPTYPE_M RDMA_MASK3(32, 0x7, IG3_PEOC9_GLPEOC_ERRDATA2_OPTYPE_S) +#define IG3_PEOC9_GLPEOC_ERRDATA2_OFFSET_S 7 +#define IG3_PEOC9_GLPEOC_ERRDATA2_OFFSET_M RDMA_MASK3(32, 0x1FFF, IG3_PEOC9_GLPEOC_ERRDATA2_OFFSET_S) +#define IG3_PEOC9_GLPEOC_ERRDATA2_LENGTH_S 0 +#define IG3_PEOC9_GLPEOC_ERRDATA2_LENGTH_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_ERRDATA2_LENGTH_S) +#define IG3_PEOC9_GLPEOC_ERRDATA3 0x429024C4 +#define IG3_PEOC9_GLPEOC_ERRDATA3_RSVD_S 15 +#define IG3_PEOC9_GLPEOC_ERRDATA3_RSVD_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC9_GLPEOC_ERRDATA3_RSVD_S) +#define IG3_PEOC9_GLPEOC_ERRDATA3_TAG_S 0 +#define IG3_PEOC9_GLPEOC_ERRDATA3_TAG_M RDMA_MASK3(32, 0x7FFF, IG3_PEOC9_GLPEOC_ERRDATA3_TAG_S) +#define IG3_PEOC9_GLPEOC_ERRINFO 0x429024B4 +#define IG3_PEOC9_GLPEOC_ERRINFO_RSVD1_S 16 +#define IG3_PEOC9_GLPEOC_ERRINFO_RSVD1_M RDMA_MASK3(32, 0xFFFF, IG3_PEOC9_GLPEOC_ERRINFO_RSVD1_S) +#define IG3_PEOC9_GLPEOC_ERRINFO_ERROR_CNT_S 8 +#define IG3_PEOC9_GLPEOC_ERRINFO_ERROR_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_ERRINFO_ERROR_CNT_S) +#define IG3_PEOC9_GLPEOC_ERRINFO_RSVD0_S 1 +#define IG3_PEOC9_GLPEOC_ERRINFO_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_ERRINFO_RSVD0_S) +#define IG3_PEOC9_GLPEOC_ERRINFO_ERROR_VALID_S 0 +#define IG3_PEOC9_GLPEOC_ERRINFO_ERROR_VALID_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_ERRINFO_ERROR_VALID_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG 0x4290251C +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS 0x42902520 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_EVICT_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG 0x42902514 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS 0x42902518 +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_FILL_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_FSIADR_OBJOFST 0x4290248C +#define IG3_PEOC9_GLPEOC_FSIADR_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_FSIADR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_FSIADR_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_FSIADR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_FSIMCAST_OBJOFST 0x42902490 +#define IG3_PEOC9_GLPEOC_FSIMCAST_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_FSIMCAST_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_FSIMCAST_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_FSIMCAST_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_HDR_OBJOFST 0x429024A0 +#define IG3_PEOC9_GLPEOC_HDR_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_HDR_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_HDR_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_HDR_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_HECC_ERR 0x429024CC +#define IG3_PEOC9_GLPEOC_HECC_ERR_RSVD1_S 28 +#define IG3_PEOC9_GLPEOC_HECC_ERR_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_HECC_ERR_RSVD1_S) +#define IG3_PEOC9_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S 16 +#define IG3_PEOC9_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_HECC_ERR_COR_ECC_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_HECC_ERR_RSVD0_S 12 +#define IG3_PEOC9_GLPEOC_HECC_ERR_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_HECC_ERR_RSVD0_S) +#define IG3_PEOC9_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S 0 +#define IG3_PEOC9_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_HECC_ERR_UNCOR_ECC_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_IRRQ_OBJOFST 0x42902480 +#define IG3_PEOC9_GLPEOC_IRRQ_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_IRRQ_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_IRRQ_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_IRRQ_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_MAXOSR 0x429024D4 +#define IG3_PEOC9_GLPEOC_MAXOSR_RSVD1_S 15 +#define IG3_PEOC9_GLPEOC_MAXOSR_RSVD1_M RDMA_MASK3(32, 0x1FFFF, IG3_PEOC9_GLPEOC_MAXOSR_RSVD1_S) +#define IG3_PEOC9_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S 10 +#define IG3_PEOC9_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_MAXOSR_MAX_OSR_CLNT_WRPULL_S) +#define IG3_PEOC9_GLPEOC_MAXOSR_RSVD0_S 8 +#define IG3_PEOC9_GLPEOC_MAXOSR_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_MAXOSR_RSVD0_S) +#define IG3_PEOC9_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S 0 +#define IG3_PEOC9_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_MAXOSR_MAX_OSR_PMAT_FETCH_S) +#define IG3_PEOC9_GLPEOC_MEM_ECC_COR_ERR 0x429025B8 +#define IG3_PEOC9_GLPEOC_MEM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PEOC9_GLPEOC_MEM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC9_GLPEOC_MEM_ECC_COR_ERR_RSVD_S) +#define IG3_PEOC9_GLPEOC_MEM_ECC_COR_ERR_CNT_S 0 +#define IG3_PEOC9_GLPEOC_MEM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_MEM_ECC_COR_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_MEM_ECC_UNCOR_ERR 0x429025B4 +#define IG3_PEOC9_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PEOC9_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PEOC9_GLPEOC_MEM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PEOC9_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PEOC9_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PEOC9_GLPEOC_MEM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_OOISCFL_OBJOFST 0x429024B0 +#define IG3_PEOC9_GLPEOC_OOISCFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_OOISCFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_OOISCFL_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_OOISCFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_OOISC_OBJOFST 0x429024AC +#define IG3_PEOC9_GLPEOC_OOISC_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_OOISC_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_OOISC_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_OOISC_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL 0x429025AC +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_PLIST_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_PLIST_DBG_DATA 0x429025B0 +#define IG3_PEOC9_GLPEOC_PLIST_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_PLIST_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_PLIST_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG 0x4290250C +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS 0x42902510 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PLIST_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_PMATINV_CFG 0x429024DC +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_RSVD_S 6 +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_PEOC9_GLPEOC_PMATINV_CFG_RSVD_S) +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S 5 +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYPRNTANDFN_FENCE_EN_S) +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S 4 +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S 3 +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYFN_FENCE_EN_S) +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S 2 +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PMATINV_CFG_WBINVBYOBJ_FENCE_EN_S) +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S 1 +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PMATINV_CFG_INVBYTYPEANDFN_FENCE_EN_S) +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S 0 +#define IG3_PEOC9_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_PMATINV_CFG_INVBYFN_FENCE_EN_S) +#define IG3_PEOC9_GLPEOC_Q1FL_OBJOFST 0x42902498 +#define IG3_PEOC9_GLPEOC_Q1FL_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_Q1FL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_Q1FL_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_Q1FL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_RRFL_OBJOFST 0x429024A8 +#define IG3_PEOC9_GLPEOC_RRFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_RRFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_RRFL_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_RRFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_RRF_OBJOFST 0x429024A4 +#define IG3_PEOC9_GLPEOC_RRF_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_RRF_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_RRF_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_RRF_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_SRQCTX_OBJOFST 0x42902488 +#define IG3_PEOC9_GLPEOC_SRQCTX_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_SRQCTX_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_SRQCTX_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_SRQCTX_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_STAT_CTL 0x42902404 +#define IG3_PEOC9_GLPEOC_STAT_CTL_RSVD_S 5 +#define IG3_PEOC9_GLPEOC_STAT_CTL_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_PEOC9_GLPEOC_STAT_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_CTL_OBJECT_TYPE_S 0 +#define IG3_PEOC9_GLPEOC_STAT_CTL_OBJECT_TYPE_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_STAT_CTL_OBJECT_TYPE_S) +#define IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_HI 0x4290246C +#define IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_LO 0x42902468 +#define IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_FENCING_TIME_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_ENTRIES 0x4290244C +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S 8 +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_ENTRIES_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S 0 +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_ENTRIES_CNT_S) +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH 0x42902454 +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S 8 +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_MAX_PENDING_LIST_DEPTH_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS 0x42902450 +#define IG3_PEOC9_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S 8 +#define IG3_PEOC9_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_MAX_VIRT_PENDING_LISTS_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_OBJ_CNT 0x42902408 +#define IG3_PEOC9_GLPEOC_STAT_OBJ_CNT_RSVD_S 14 +#define IG3_PEOC9_GLPEOC_STAT_OBJ_CNT_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_STAT_OBJ_CNT_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S 0 +#define IG3_PEOC9_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_M RDMA_MASK3(32, 0x3FFF, IG3_PEOC9_GLPEOC_STAT_OBJ_CNT_OBJECT_COUNT_S) +#define IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_HI 0x42902464 +#define IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_LO 0x42902460 +#define IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_PENDLING_LIST_FULL_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_HI 0x42902430 +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_LO 0x4290242C +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_RD_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_HI 0x42902438 +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_LO 0x42902434 +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_RD_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_HIT_HI 0x42902410 +#define IG3_PEOC9_GLPEOC_STAT_RD_HIT_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_RD_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_RD_HIT_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_RD_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_RD_HIT_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_HIT_LO 0x4290240C +#define IG3_PEOC9_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_RD_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_RD_HIT_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_MISS_HI 0x42902418 +#define IG3_PEOC9_GLPEOC_STAT_RD_MISS_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_RD_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_RD_MISS_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_RD_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_RD_MISS_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_RD_MISS_LO 0x42902414 +#define IG3_PEOC9_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_RD_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_RD_MISS_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_HI 0x42902474 +#define IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_LO 0x42902470 +#define IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_REPLAY_TIME_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_HI 0x4290245C +#define IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_LO 0x42902458 +#define IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_BUFF_FULL_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_HI 0x42902440 +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_LO 0x4290243C +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_DATA_IDLE_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_HI 0x42902448 +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_LO 0x42902444 +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_DATA_XFER_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_HIT_HI 0x42902420 +#define IG3_PEOC9_GLPEOC_STAT_WR_HIT_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_WR_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_WR_HIT_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_HIT_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_HIT_LO 0x4290241C +#define IG3_PEOC9_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_HIT_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_MISS_HI 0x42902428 +#define IG3_PEOC9_GLPEOC_STAT_WR_MISS_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_STAT_WR_MISS_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_STAT_WR_MISS_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_MISS_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_MISS_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_STAT_WR_MISS_LO 0x42902424 +#define IG3_PEOC9_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_STAT_WR_MISS_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_STAT_WR_MISS_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL 0x42902564 +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_DONE_S 31 +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_DBG_CTL_DONE_S) +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_RD_EN_S 30 +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_DBG_CTL_RD_EN_S) +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_RSVD_S 26 +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_TAG_DBG_CTL_RSVD_S) +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_DW_SEL_S 18 +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_TAG_DBG_CTL_DW_SEL_S) +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_ADR_S 0 +#define IG3_PEOC9_GLPEOC_TAG_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_TAG_DBG_CTL_ADR_S) +#define IG3_PEOC9_GLPEOC_TAG_DBG_DATA 0x42902568 +#define IG3_PEOC9_GLPEOC_TAG_DBG_DATA_RD_DW_S 0 +#define IG3_PEOC9_GLPEOC_TAG_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_TAG_DBG_DATA_RD_DW_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG 0x429024FC +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS 0x42902500 +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_TIMER_OBJOFST 0x4290249C +#define IG3_PEOC9_GLPEOC_TIMER_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_TIMER_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_TIMER_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_TIMER_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HI 0x429024F0 +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_TOTAL_TAG_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_TOTAL_TAG_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_HI 0x429024F8 +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S 24 +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_HI_RSVD_S) +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S 0 +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_M RDMA_MASK3(32, 0xFFFFFF, IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_HI_CNT_HI_S) +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_LO 0x429024F4 +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_TOTAL_TAG_HIT_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_LO 0x429024EC +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_LO_CNT_LO_S 0 +#define IG3_PEOC9_GLPEOC_TOTAL_TAG_LO_CNT_LO_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PEOC9_GLPEOC_TOTAL_TAG_LO_CNT_LO_S) +#define IG3_PEOC9_GLPEOC_TXFIFO_OBJOFST 0x4290247C +#define IG3_PEOC9_GLPEOC_TXFIFO_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_TXFIFO_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_TXFIFO_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_TXFIFO_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG 0x42902504 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD3_S 20 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD3_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RM_S 16 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RM_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD2_S 14 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD2_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RME_S 12 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RME_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD1_S 10 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD1_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ERR_CNT_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_FIX_CNT_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD0_S 6 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_RSVD0_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_MASK_INT_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_LS_FORCE_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_CFG_ECC_EN_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS 0x42902508 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_RSVD1_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_RSVD0_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PEOC9_GLPEOC_WRBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_PEOC9_GLPEOC_XFFL_OBJOFST 0x42902494 +#define IG3_PEOC9_GLPEOC_XFFL_OBJOFST_RSVD_S 10 +#define IG3_PEOC9_GLPEOC_XFFL_OBJOFST_RSVD_M RDMA_MASK3(32, 0x3FFFFF, IG3_PEOC9_GLPEOC_XFFL_OBJOFST_RSVD_S) +#define IG3_PEOC9_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S 0 +#define IG3_PEOC9_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_M RDMA_MASK3(32, 0x3FF, IG3_PEOC9_GLPEOC_XFFL_OBJOFST_OBJ_TYPE_OFFSET_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG 0x42C1327C +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD3_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RM_S 16 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RM_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD2_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RME_S 12 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RME_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD1_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_RSVD0_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS 0x42C132C8 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQCTL_REG_RAM_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_AEQEDROPCNT(_i) 0x42C0A000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CQM_GLPE_AEQEDROPCNT_MAX_INDEX_I 1031 +#define IG3_CQM_GLPE_AEQEDROPCNT_RSVD_S 16 +#define IG3_CQM_GLPE_AEQEDROPCNT_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_AEQEDROPCNT_RSVD_S) +#define IG3_CQM_GLPE_AEQEDROPCNT_AEQEDROPCNT_S 0 +#define IG3_CQM_GLPE_AEQEDROPCNT_AEQEDROPCNT_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_AEQEDROPCNT_AEQEDROPCNT_S) +#define IG3_CQM_GLPE_AEQITRMASK(_i) 0x42C0E000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CQM_GLPE_AEQITRMASK_MAX_INDEX_I 1031 +#define IG3_CQM_GLPE_AEQITRMASK_AEQ_ITR_MASK_S 31 +#define IG3_CQM_GLPE_AEQITRMASK_AEQ_ITR_MASK_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQITRMASK_AEQ_ITR_MASK_S) +#define IG3_CQM_GLPE_AEQITRMASK_RSVD_S 0 +#define IG3_CQM_GLPE_AEQITRMASK_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CQM_GLPE_AEQITRMASK_RSVD_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG 0x42C13278 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD3_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RM_S 16 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RM_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD2_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RME_S 12 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RME_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD1_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_RSVD0_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS 0x42C132C4 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_AEQ_CTXT_RAM_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQCTL(_i) 0x42C00000 + ((_i) * 4) /* _i=0...3167 */ +#define IG3_CQM_GLPE_CEQCTL_MAX_INDEX_I 3167 +#define IG3_CQM_GLPE_CEQCTL_RSVD1_S 31 +#define IG3_CQM_GLPE_CEQCTL_RSVD1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_RSVD1_S) +#define IG3_CQM_GLPE_CEQCTL_CAUSE_ENA_S 30 +#define IG3_CQM_GLPE_CEQCTL_CAUSE_ENA_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_CAUSE_ENA_S) +#define IG3_CQM_GLPE_CEQCTL_RSVD0_S 15 +#define IG3_CQM_GLPE_CEQCTL_RSVD0_M RDMA_MASK3(32, 0x7FFF, IG3_CQM_GLPE_CEQCTL_RSVD0_S) +#define IG3_CQM_GLPE_CEQCTL_ITR_INDX_S 13 +#define IG3_CQM_GLPE_CEQCTL_ITR_INDX_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQCTL_ITR_INDX_S) +#define IG3_CQM_GLPE_CEQCTL_MSIX_INDX_S 0 +#define IG3_CQM_GLPE_CEQCTL_MSIX_INDX_M RDMA_MASK3(32, 0x1FFF, IG3_CQM_GLPE_CEQCTL_MSIX_INDX_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG 0x42C13284 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RM_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RME_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS 0x42C132D0 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQCTL_REG_RAM_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQEDROPCNT(_i) 0x42C08000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CQM_GLPE_CEQEDROPCNT_MAX_INDEX_I 1031 +#define IG3_CQM_GLPE_CEQEDROPCNT_RSVD_S 16 +#define IG3_CQM_GLPE_CEQEDROPCNT_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_CEQEDROPCNT_RSVD_S) +#define IG3_CQM_GLPE_CEQEDROPCNT_CEQEDROPCNT_S 0 +#define IG3_CQM_GLPE_CEQEDROPCNT_CEQEDROPCNT_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_CEQEDROPCNT_CEQEDROPCNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG 0x42C13288 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQE_RAM_0_CFG_RM_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_RME_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_0_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS 0x42C132D4 +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_0_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQE_RAM_0_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQE_RAM_0_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_0_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_0_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG 0x42C1328C +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQE_RAM_1_CFG_RM_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_RME_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_1_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS 0x42C132D8 +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_1_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQE_RAM_1_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQE_RAM_1_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_1_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_1_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG 0x42C13290 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQE_RAM_2_CFG_RM_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_RME_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_2_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS 0x42C132DC +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_2_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQE_RAM_2_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQE_RAM_2_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_2_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_2_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG 0x42C13294 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQE_RAM_3_CFG_RM_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_RME_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_3_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS 0x42C132E0 +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_3_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQE_RAM_3_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQE_RAM_3_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_3_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_3_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG 0x42C13298 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQE_RAM_4_CFG_RM_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_RME_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_4_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS 0x42C132E4 +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_4_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQE_RAM_4_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQE_RAM_4_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_4_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_4_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG 0x42C1329C +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQE_RAM_5_CFG_RM_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_RME_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_5_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS 0x42C132E8 +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_5_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQE_RAM_5_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQE_RAM_5_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_5_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_5_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG 0x42C132A0 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQE_RAM_6_CFG_RM_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_RME_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_6_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS 0x42C132EC +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_6_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQE_RAM_6_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQE_RAM_6_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_6_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_6_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG 0x42C132A4 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQE_RAM_7_CFG_RM_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_RME_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_7_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS 0x42C132F0 +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQE_RAM_7_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQE_RAM_7_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQE_RAM_7_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQE_RAM_7_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQE_RAM_7_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CEQITRMASK(_i) 0x42C10000 + ((_i) * 4) /* _i=0...3167 */ +#define IG3_CQM_GLPE_CEQITRMASK_MAX_INDEX_I 3167 +#define IG3_CQM_GLPE_CEQITRMASK_CEQ_ITR_MASK_S 31 +#define IG3_CQM_GLPE_CEQITRMASK_CEQ_ITR_MASK_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQITRMASK_CEQ_ITR_MASK_S) +#define IG3_CQM_GLPE_CEQITRMASK_RSVD_S 0 +#define IG3_CQM_GLPE_CEQITRMASK_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CQM_GLPE_CEQITRMASK_RSVD_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG 0x42C13280 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RM_S 16 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RM_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RME_S 12 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RME_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS 0x42C132CC +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CEQ_CTXT_RAM_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CQEDROPCNT(_i) 0x42C06000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CQM_GLPE_CQEDROPCNT_MAX_INDEX_I 1031 +#define IG3_CQM_GLPE_CQEDROPCNT_RSVD_S 16 +#define IG3_CQM_GLPE_CQEDROPCNT_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_CQEDROPCNT_RSVD_S) +#define IG3_CQM_GLPE_CQEDROPCNT_CQEDROPCNT_S 0 +#define IG3_CQM_GLPE_CQEDROPCNT_CQEDROPCNT_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_CQEDROPCNT_CQEDROPCNT_S) +#define IG3_CQM_GLPE_CQE_TSCTL(_i) 0x42C0C000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CQM_GLPE_CQE_TSCTL_MAX_INDEX_I 1031 +#define IG3_CQM_GLPE_CQE_TSCTL_ENABLE_S 31 +#define IG3_CQM_GLPE_CQE_TSCTL_ENABLE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQE_TSCTL_ENABLE_S) +#define IG3_CQM_GLPE_CQE_TSCTL_RSVD0_S 5 +#define IG3_CQM_GLPE_CQE_TSCTL_RSVD0_M RDMA_MASK3(32, 0x3FFFFFF, IG3_CQM_GLPE_CQE_TSCTL_RSVD0_S) +#define IG3_CQM_GLPE_CQE_TSCTL_SHIFT_CNT_S 0 +#define IG3_CQM_GLPE_CQE_TSCTL_SHIFT_CNT_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CQE_TSCTL_SHIFT_CNT_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_BUS_INDEX 0x42C13390 +#define IG3_CQM_GLPE_CQM_BOB_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL 0x42C13380 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_RESERVED_31_10_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_TRIG_OP_S 8 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_TRIG_OP_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_FREEZE_RESET_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_CTRL_FREEZE_SET_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_FREEZE_ON_CNT_VAL 0x42C133A0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_OBS_BUS 0x42C133C0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT0 0x42C133E0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT0_CNT0_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT1_0 0x42C133E8 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT1_1 0x42C133EC +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL 0x42C133D8 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CQM_BOB_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_CTRL 0x42C133B8 +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_GAP 0x42C133A8 +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_RC_GAP_RC_GAP_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_TRNS 0x42C133B0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS 0x42C13388 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_RESERVED_31_8_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_I_FREEZE_S 6 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_I_FREEZE_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_READY_S 5 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_READY_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_VALID_S 4 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_VALID_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_BOB_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_TRANS_CNT 0x42C13398 +#define IG3_CQM_GLPE_CQM_BOB_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_TRIG_MASK 0x42C133C8 +#define IG3_CQM_GLPE_CQM_BOB_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_CQM_GLPE_CQM_BOB_BOB_TRIG_VALUE 0x42C133D0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_BOB_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_BOB_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_COUNT 0x42C13438 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_CMD 0x42C1344C +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_DATA_H 0x42C13458 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_DATA_L 0x42C13454 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_PTR 0x42C13450 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_CMD 0x42C1343C +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_DATA_H 0x42C13448 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_DATA_L 0x42C13444 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_PTR 0x42C13440 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQM_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_CONTROL 0x42C13400 +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD1_S 25 +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD2_S 17 +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD2_S) +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD3_S 9 +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD3_S) +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_BYPASS_S 8 +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_CONTROL_BYPASS_S) +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD4_S 1 +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CQM_DTM_CONTROL_RSVD4_S) +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_CQM_GLPE_CQM_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_CONTROL_LOCAL_EN_S) +#define IG3_CQM_GLPE_CQM_DTM_ECC_COR_ERR 0x42C13468 +#define IG3_CQM_GLPE_CQM_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_CQM_GLPE_CQM_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQM_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_CQM_GLPE_CQM_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_CQM_GLPE_CQM_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_DTM_ECC_COR_ERR_CNT_S) +#define IG3_CQM_GLPE_CQM_DTM_ECC_UNCOR_ERR 0x42C13464 +#define IG3_CQM_GLPE_CQM_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CQM_GLPE_CQM_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQM_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CQM_GLPE_CQM_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CQM_GLPE_CQM_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_CQM_GLPE_CQM_DTM_GROUP_CFG 0x42C1340C +#define IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_CQM_GLPE_CQM_DTM_LOG_CFG 0x42C13410 +#define IG3_CQM_GLPE_CQM_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_CQM_GLPE_CQM_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_CQM_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_CQM_GLPE_CQM_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_CQM_GLPE_CQM_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CQM_GLPE_CQM_DTM_LOG_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_LOG_CFG_MODE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_DTM_LOG_CFG_MODE_S) +#define IG3_CQM_GLPE_CQM_DTM_LOG_MASK 0x42C13418 +#define IG3_CQM_GLPE_CQM_DTM_LOG_MASK_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_LOG_MASK_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_LOG_PATTERN 0x42C13414 +#define IG3_CQM_GLPE_CQM_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_LOG_PATTERN_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG 0x42C13404 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_STS 0x42C13408 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_CQM_GLPE_CQM_DTM_MAIN_STS_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CQM_DTM_MAIN_STS_RSVD2_S) +#define IG3_CQM_GLPE_CQM_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_CQM_GLPE_CQM_DTM_TIMESTAMP 0x42C13430 +#define IG3_CQM_GLPE_CQM_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_TIMESTAMP_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_TIMESTAMP_ROLLOVER 0x42C13434 +#define IG3_CQM_GLPE_CQM_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG 0x42C1345C +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS 0x42C13460 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG 0x42C1341C +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_MODE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CQM_DTM_TRIG_CFG_MODE_S) +#define IG3_CQM_GLPE_CQM_DTM_TRIG_COUNT 0x42C13428 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_TRIG_COUNT_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_TRIG_MASK 0x42C13424 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_TRIG_MASK_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_TRIG_PATTERN 0x42C13420 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_CQM_GLPE_CQM_DTM_TRIG_TIMESTAMP 0x42C1342C +#define IG3_CQM_GLPE_CQM_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_CQM_GLPE_CQM_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CQM_GLPE_CQM_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_CQM_GLPE_CQM_ECC_COR_ERR 0x42C13314 +#define IG3_CQM_GLPE_CQM_ECC_COR_ERR_RSVD_S 12 +#define IG3_CQM_GLPE_CQM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQM_ECC_COR_ERR_RSVD_S) +#define IG3_CQM_GLPE_CQM_ECC_COR_ERR_CNT_S 0 +#define IG3_CQM_GLPE_CQM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_ECC_COR_ERR_CNT_S) +#define IG3_CQM_GLPE_CQM_ECC_UNCOR_ERR 0x42C13310 +#define IG3_CQM_GLPE_CQM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CQM_GLPE_CQM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CQM_GLPE_CQM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CQM_GLPE_CQM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_ECC_UNCOR_ERR_CNT_S) +#define IG3_CQM_GLPE_CQM_FLR_RX_MKR_CNT 0x42C13230 +#define IG3_CQM_GLPE_CQM_FLR_RX_MKR_CNT_RSVD_S 8 +#define IG3_CQM_GLPE_CQM_FLR_RX_MKR_CNT_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CQM_GLPE_CQM_FLR_RX_MKR_CNT_RSVD_S) +#define IG3_CQM_GLPE_CQM_FLR_RX_MKR_CNT_COUNT_S 0 +#define IG3_CQM_GLPE_CQM_FLR_RX_MKR_CNT_COUNT_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_FLR_RX_MKR_CNT_COUNT_S) +#define IG3_CQM_GLPE_CQM_FLR_TXCMP_MKR_CNT 0x42C1322C +#define IG3_CQM_GLPE_CQM_FLR_TXCMP_MKR_CNT_RSVD_S 8 +#define IG3_CQM_GLPE_CQM_FLR_TXCMP_MKR_CNT_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_CQM_GLPE_CQM_FLR_TXCMP_MKR_CNT_RSVD_S) +#define IG3_CQM_GLPE_CQM_FLR_TXCMP_MKR_CNT_COUNT_S 0 +#define IG3_CQM_GLPE_CQM_FLR_TXCMP_MKR_CNT_COUNT_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_CQM_FLR_TXCMP_MKR_CNT_COUNT_S) +#define IG3_CQM_GLPE_CQM_FLUSH_MKR_CNT 0x42C13228 +#define IG3_CQM_GLPE_CQM_FLUSH_MKR_CNT_RSVD_S 16 +#define IG3_CQM_GLPE_CQM_FLUSH_MKR_CNT_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_CQM_FLUSH_MKR_CNT_RSVD_S) +#define IG3_CQM_GLPE_CQM_FLUSH_MKR_CNT_MKR_CNT_S 0 +#define IG3_CQM_GLPE_CQM_FLUSH_MKR_CNT_MKR_CNT_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_CQM_FLUSH_MKR_CNT_MKR_CNT_S) +#define IG3_CQM_GLPE_CQM_FUNC_INVALIDATE 0x42C13200 +#define IG3_CQM_GLPE_CQM_FUNC_INVALIDATE_ENABLE_S 31 +#define IG3_CQM_GLPE_CQM_FUNC_INVALIDATE_ENABLE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_FUNC_INVALIDATE_ENABLE_S) +#define IG3_CQM_GLPE_CQM_FUNC_INVALIDATE_RSVD_S 20 +#define IG3_CQM_GLPE_CQM_FUNC_INVALIDATE_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_CQM_GLPE_CQM_FUNC_INVALIDATE_RSVD_S) +#define IG3_CQM_GLPE_CQM_FUNC_INVALIDATE_FUNC_TRIPLET_S 0 +#define IG3_CQM_GLPE_CQM_FUNC_INVALIDATE_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQM_FUNC_INVALIDATE_FUNC_TRIPLET_S) +#define IG3_CQM_GLPE_CQM_ORDERING_DOMAIN 0x42C13274 +#define IG3_CQM_GLPE_CQM_ORDERING_DOMAIN_RSVD0_S 3 +#define IG3_CQM_GLPE_CQM_ORDERING_DOMAIN_RSVD0_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_CQM_GLPE_CQM_ORDERING_DOMAIN_RSVD0_S) +#define IG3_CQM_GLPE_CQM_ORDERING_DOMAIN_ORDERING_DOMAIN_S 0 +#define IG3_CQM_GLPE_CQM_ORDERING_DOMAIN_ORDERING_DOMAIN_M RDMA_MASK3(32, 0x7, IG3_CQM_GLPE_CQM_ORDERING_DOMAIN_ORDERING_DOMAIN_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG 0x42C132B4 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD3_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RM_S 16 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RM_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD2_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RME_S 12 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RME_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD1_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_RSVD0_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_TRANS_RAM_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_CQM_XLR_DROP_HI(_i) 0x42C13254 + ((_i) * 4) /* _i=0...7 */ +#define IG3_CQM_GLPE_CQM_XLR_DROP_HI_MAX_INDEX_I 7 +#define IG3_CQM_GLPE_CQM_XLR_DROP_HI_EN_S 31 +#define IG3_CQM_GLPE_CQM_XLR_DROP_HI_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CQM_XLR_DROP_HI_EN_S) +#define IG3_CQM_GLPE_CQM_XLR_DROP_HI_RSVD0_S 12 +#define IG3_CQM_GLPE_CQM_XLR_DROP_HI_RSVD0_M RDMA_MASK3(32, 0x7FFFF, IG3_CQM_GLPE_CQM_XLR_DROP_HI_RSVD0_S) +#define IG3_CQM_GLPE_CQM_XLR_DROP_HI_PMF_S 0 +#define IG3_CQM_GLPE_CQM_XLR_DROP_HI_PMF_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_XLR_DROP_HI_PMF_S) +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO(_i) 0x42C13234 + ((_i) * 4) /* _i=0...7 */ +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO_MAX_INDEX_I 7 +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO_RSVD_S 20 +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_XLR_DROP_LO_RSVD_S) +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO_VDEFVFTYPE_S 18 +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO_VDEFVFTYPE_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQM_XLR_DROP_LO_VDEFVFTYPE_S) +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO_VF_S 6 +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO_VF_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQM_XLR_DROP_LO_VF_S) +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO_PF_S 0 +#define IG3_CQM_GLPE_CQM_XLR_DROP_LO_PF_M RDMA_MASK3(32, 0x3F, IG3_CQM_GLPE_CQM_XLR_DROP_LO_PF_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER 0x42C13208 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_LOCK_EN_S 31 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_LOCK_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_LOCK_EN_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_LOCK_ACTIVE_S 30 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_LOCK_ACTIVE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_LOCK_ACTIVE_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_RSVD_S 20 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_RSVD_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_VDEFVFTYPE_S 18 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_VDEFVFTYPE_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_VDEFVFTYPE_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_VF_S 6 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_VF_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_VF_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_PF_S 0 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_PF_M RDMA_MASK3(32, 0x3F, IG3_CQM_GLPE_CQP_CQ_LOCK0_LOWER_PF_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_UPPER 0x42C13204 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_UPPER_RSVD_S 20 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_UPPER_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQP_CQ_LOCK0_UPPER_RSVD_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_UPPER_CQID_S 0 +#define IG3_CQM_GLPE_CQP_CQ_LOCK0_UPPER_CQID_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQP_CQ_LOCK0_UPPER_CQID_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER 0x42C13210 +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_LOCK_EN_S 31 +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_LOCK_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_LOCK_EN_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_LOCK_ACTIVE_S 30 +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_LOCK_ACTIVE_M RDMA_BIT2(32, IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_LOCK_ACTIVE_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_RSVD_S 20 +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_RSVD_M RDMA_MASK3(32, 0x3FF, IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_RSVD_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_VDEFVFTYPE_S 18 +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_VDEFVFTYPE_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_VDEFVFTYPE_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_VF_S 6 +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_VF_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_VF_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_PF_S 0 +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_PF_M RDMA_MASK3(32, 0x3F, IG3_CQM_GLPE_CQP_CQ_LOCK1_LOWER_PF_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_UPPER 0x42C1320C +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_UPPER_RSVD_S 20 +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_UPPER_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CQM_GLPE_CQP_CQ_LOCK1_UPPER_RSVD_S) +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_UPPER_CQID_S 0 +#define IG3_CQM_GLPE_CQP_CQ_LOCK1_UPPER_CQID_M RDMA_MASK3(32, 0xFFFFF, IG3_CQM_GLPE_CQP_CQ_LOCK1_UPPER_CQID_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG 0x42C132B8 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD3_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RM_S 16 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RM_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD2_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RME_S 12 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RME_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD1_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_RSVD0_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS 0x42C13304 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_0_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG 0x42C132BC +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD3_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RM_S 16 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RM_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD2_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RME_S 12 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RME_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD1_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_RSVD0_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS 0x42C13308 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_1_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG 0x42C132C0 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD3_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RM_S 16 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RM_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD2_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RME_S 12 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RME_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD1_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_RSVD0_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS 0x42C1330C +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_DROP_REG_RAM_2_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_HOME0_PARTITION 0x42C13214 +#define IG3_CQM_GLPE_HOME0_PARTITION_RSVD_S 16 +#define IG3_CQM_GLPE_HOME0_PARTITION_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_HOME0_PARTITION_RSVD_S) +#define IG3_CQM_GLPE_HOME0_PARTITION_MAXPERDBHOME_S 8 +#define IG3_CQM_GLPE_HOME0_PARTITION_MAXPERDBHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME0_PARTITION_MAXPERDBHOME_S) +#define IG3_CQM_GLPE_HOME0_PARTITION_MAXPERCQHOME_S 0 +#define IG3_CQM_GLPE_HOME0_PARTITION_MAXPERCQHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME0_PARTITION_MAXPERCQHOME_S) +#define IG3_CQM_GLPE_HOME1_PARTITION 0x42C13218 +#define IG3_CQM_GLPE_HOME1_PARTITION_RSVD_S 16 +#define IG3_CQM_GLPE_HOME1_PARTITION_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_HOME1_PARTITION_RSVD_S) +#define IG3_CQM_GLPE_HOME1_PARTITION_MAXPERDBHOME_S 8 +#define IG3_CQM_GLPE_HOME1_PARTITION_MAXPERDBHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME1_PARTITION_MAXPERDBHOME_S) +#define IG3_CQM_GLPE_HOME1_PARTITION_MAXPERCQHOME_S 0 +#define IG3_CQM_GLPE_HOME1_PARTITION_MAXPERCQHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME1_PARTITION_MAXPERCQHOME_S) +#define IG3_CQM_GLPE_HOME2_PARTITION 0x42C1321C +#define IG3_CQM_GLPE_HOME2_PARTITION_RSVD_S 16 +#define IG3_CQM_GLPE_HOME2_PARTITION_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_HOME2_PARTITION_RSVD_S) +#define IG3_CQM_GLPE_HOME2_PARTITION_MAXPERDBHOME_S 8 +#define IG3_CQM_GLPE_HOME2_PARTITION_MAXPERDBHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME2_PARTITION_MAXPERDBHOME_S) +#define IG3_CQM_GLPE_HOME2_PARTITION_MAXPERCQHOME_S 0 +#define IG3_CQM_GLPE_HOME2_PARTITION_MAXPERCQHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME2_PARTITION_MAXPERCQHOME_S) +#define IG3_CQM_GLPE_HOME3_PARTITION 0x42C13220 +#define IG3_CQM_GLPE_HOME3_PARTITION_RSVD_S 16 +#define IG3_CQM_GLPE_HOME3_PARTITION_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_HOME3_PARTITION_RSVD_S) +#define IG3_CQM_GLPE_HOME3_PARTITION_MAXPERDBHOME_S 8 +#define IG3_CQM_GLPE_HOME3_PARTITION_MAXPERDBHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME3_PARTITION_MAXPERDBHOME_S) +#define IG3_CQM_GLPE_HOME3_PARTITION_MAXPERCQHOME_S 0 +#define IG3_CQM_GLPE_HOME3_PARTITION_MAXPERCQHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME3_PARTITION_MAXPERCQHOME_S) +#define IG3_CQM_GLPE_HOME4_PARTITION 0x42C13224 +#define IG3_CQM_GLPE_HOME4_PARTITION_RSVD_S 16 +#define IG3_CQM_GLPE_HOME4_PARTITION_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_CQM_GLPE_HOME4_PARTITION_RSVD_S) +#define IG3_CQM_GLPE_HOME4_PARTITION_MAXPERDBHOME_S 8 +#define IG3_CQM_GLPE_HOME4_PARTITION_MAXPERDBHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME4_PARTITION_MAXPERDBHOME_S) +#define IG3_CQM_GLPE_HOME4_PARTITION_MAXPERCQHOME_S 0 +#define IG3_CQM_GLPE_HOME4_PARTITION_MAXPERCQHOME_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_HOME4_PARTITION_MAXPERCQHOME_S) +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS 0x42C13300 +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CQM_TRANS_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG 0x42C132A8 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD3_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RM_S 16 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RM_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD2_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RME_S 12 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RME_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD1_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_RSVD0_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS 0x42C132F4 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_CTXT_RAM_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG 0x42C132AC +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD3_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RM_S 16 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RM_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD2_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RME_S 12 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RME_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD1_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_RSVD0_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS 0x42C132F8 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_HSM_RAM_STATUS_ECC_ERR_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG 0x42C132B0 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_INST_NUM_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD3_S 20 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD3_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RM_S 16 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RM_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD2_S 14 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD2_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_POWER_GATE_EN_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RME_S 12 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RME_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RME_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD1_S 10 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD1_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ERR_CNT_S 9 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ERR_CNT_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_FIX_CNT_S 8 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_FIX_CNT_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD0_S 6 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_RSVD0_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_MASK_INT_S 5 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_MASK_INT_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_LS_BYPASS_S 4 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_LS_BYPASS_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_LS_FORCE_S 3 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_LS_FORCE_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_INVERT_2_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_INVERT_1_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_EN_S 0 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_CFG_ECC_EN_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS 0x42C132FC +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_RSVD1_S 30 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_RSVD1_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_RSVD0_S 4 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_RSVD0_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_INIT_DONE_S 2 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_INIT_DONE_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_ECC_FIX_S 1 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_ECC_FIX_S) +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_ECC_ERR_S 0 +#define IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CQM_GLPE_SPAD_PAL_RAM_STATUS_ECC_ERR_S) +#define IG3_CQM_PMFPE_AEQCTL(_i) 0x42C04000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_CQM_PMFPE_AEQCTL_MAX_INDEX_I 1031 +#define IG3_CQM_PMFPE_AEQCTL_RSVD1_S 31 +#define IG3_CQM_PMFPE_AEQCTL_RSVD1_M RDMA_BIT2(32, IG3_CQM_PMFPE_AEQCTL_RSVD1_S) +#define IG3_CQM_PMFPE_AEQCTL_CAUSE_ENA_S 30 +#define IG3_CQM_PMFPE_AEQCTL_CAUSE_ENA_M RDMA_BIT2(32, IG3_CQM_PMFPE_AEQCTL_CAUSE_ENA_S) +#define IG3_CQM_PMFPE_AEQCTL_RSVD0_S 15 +#define IG3_CQM_PMFPE_AEQCTL_RSVD0_M RDMA_MASK3(32, 0x7FFF, IG3_CQM_PMFPE_AEQCTL_RSVD0_S) +#define IG3_CQM_PMFPE_AEQCTL_ITR_INDX_S 13 +#define IG3_CQM_PMFPE_AEQCTL_ITR_INDX_M RDMA_MASK3(32, 0x3, IG3_CQM_PMFPE_AEQCTL_ITR_INDX_S) +#define IG3_CQM_PMFPE_AEQCTL_MSIX_INDX_S 0 +#define IG3_CQM_PMFPE_AEQCTL_MSIX_INDX_M RDMA_MASK3(32, 0x1FFF, IG3_CQM_PMFPE_AEQCTL_MSIX_INDX_S) +#define IG3_DBL_GLPE_CEQPART_CTRL0 0x42C2004C +#define IG3_DBL_GLPE_CEQPART_CTRL0_BUSY_S 31 +#define IG3_DBL_GLPE_CEQPART_CTRL0_BUSY_M RDMA_BIT2(32, IG3_DBL_GLPE_CEQPART_CTRL0_BUSY_S) +#define IG3_DBL_GLPE_CEQPART_CTRL0_RSVD1_S 19 +#define IG3_DBL_GLPE_CEQPART_CTRL0_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_CEQPART_CTRL0_RSVD1_S) +#define IG3_DBL_GLPE_CEQPART_CTRL0_ADDR_S 8 +#define IG3_DBL_GLPE_CEQPART_CTRL0_ADDR_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_CEQPART_CTRL0_ADDR_S) +#define IG3_DBL_GLPE_CEQPART_CTRL0_RSVD0_S 3 +#define IG3_DBL_GLPE_CEQPART_CTRL0_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_CEQPART_CTRL0_RSVD0_S) +#define IG3_DBL_GLPE_CEQPART_CTRL0_OP_S 0 +#define IG3_DBL_GLPE_CEQPART_CTRL0_OP_M RDMA_MASK3(32, 0x7, IG3_DBL_GLPE_CEQPART_CTRL0_OP_S) +#define IG3_DBL_GLPE_CEQPART_CTRL1 0x42C20050 +#define IG3_DBL_GLPE_CEQPART_CTRL1_VALID_MASK_S 31 +#define IG3_DBL_GLPE_CEQPART_CTRL1_VALID_MASK_M RDMA_BIT2(32, IG3_DBL_GLPE_CEQPART_CTRL1_VALID_MASK_S) +#define IG3_DBL_GLPE_CEQPART_CTRL1_VALID_S 30 +#define IG3_DBL_GLPE_CEQPART_CTRL1_VALID_M RDMA_BIT2(32, IG3_DBL_GLPE_CEQPART_CTRL1_VALID_S) +#define IG3_DBL_GLPE_CEQPART_CTRL1_PMF_MASK_S 29 +#define IG3_DBL_GLPE_CEQPART_CTRL1_PMF_MASK_M RDMA_BIT2(32, IG3_DBL_GLPE_CEQPART_CTRL1_PMF_MASK_S) +#define IG3_DBL_GLPE_CEQPART_CTRL1_RSVD1_S 27 +#define IG3_DBL_GLPE_CEQPART_CTRL1_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_CEQPART_CTRL1_RSVD1_S) +#define IG3_DBL_GLPE_CEQPART_CTRL1_PMF_S 16 +#define IG3_DBL_GLPE_CEQPART_CTRL1_PMF_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_CEQPART_CTRL1_PMF_S) +#define IG3_DBL_GLPE_CEQPART_CTRL1_UNIT_MASK_S 15 +#define IG3_DBL_GLPE_CEQPART_CTRL1_UNIT_MASK_M RDMA_BIT2(32, IG3_DBL_GLPE_CEQPART_CTRL1_UNIT_MASK_S) +#define IG3_DBL_GLPE_CEQPART_CTRL1_RSVD0_S 7 +#define IG3_DBL_GLPE_CEQPART_CTRL1_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_CEQPART_CTRL1_RSVD0_S) +#define IG3_DBL_GLPE_CEQPART_CTRL1_UNIT_S 0 +#define IG3_DBL_GLPE_CEQPART_CTRL1_UNIT_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_CEQPART_CTRL1_UNIT_S) +#define IG3_DBL_GLPE_CEQPART_DATA0 0x42C20054 +#define IG3_DBL_GLPE_CEQPART_DATA0_RSVD1_S 30 +#define IG3_DBL_GLPE_CEQPART_DATA0_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_CEQPART_DATA0_RSVD1_S) +#define IG3_DBL_GLPE_CEQPART_DATA0_HITCNT_S 19 +#define IG3_DBL_GLPE_CEQPART_DATA0_HITCNT_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_CEQPART_DATA0_HITCNT_S) +#define IG3_DBL_GLPE_CEQPART_DATA0_ADDR_S 8 +#define IG3_DBL_GLPE_CEQPART_DATA0_ADDR_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_CEQPART_DATA0_ADDR_S) +#define IG3_DBL_GLPE_CEQPART_DATA0_RSVD0_S 0 +#define IG3_DBL_GLPE_CEQPART_DATA0_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_CEQPART_DATA0_RSVD0_S) +#define IG3_DBL_GLPE_CEQPART_DATA1 0x42C20058 +#define IG3_DBL_GLPE_CEQPART_DATA1_RSVD1_S 31 +#define IG3_DBL_GLPE_CEQPART_DATA1_RSVD1_M RDMA_BIT2(32, IG3_DBL_GLPE_CEQPART_DATA1_RSVD1_S) +#define IG3_DBL_GLPE_CEQPART_DATA1_VALID_S 30 +#define IG3_DBL_GLPE_CEQPART_DATA1_VALID_M RDMA_BIT2(32, IG3_DBL_GLPE_CEQPART_DATA1_VALID_S) +#define IG3_DBL_GLPE_CEQPART_DATA1_ERROR_S 29 +#define IG3_DBL_GLPE_CEQPART_DATA1_ERROR_M RDMA_BIT2(32, IG3_DBL_GLPE_CEQPART_DATA1_ERROR_S) +#define IG3_DBL_GLPE_CEQPART_DATA1_HIT_S 28 +#define IG3_DBL_GLPE_CEQPART_DATA1_HIT_M RDMA_BIT2(32, IG3_DBL_GLPE_CEQPART_DATA1_HIT_S) +#define IG3_DBL_GLPE_CEQPART_DATA1_PMF_S 16 +#define IG3_DBL_GLPE_CEQPART_DATA1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_CEQPART_DATA1_PMF_S) +#define IG3_DBL_GLPE_CEQPART_DATA1_RSVD0_S 7 +#define IG3_DBL_GLPE_CEQPART_DATA1_RSVD0_M RDMA_MASK3(32, 0x1FF, IG3_DBL_GLPE_CEQPART_DATA1_RSVD0_S) +#define IG3_DBL_GLPE_CEQPART_DATA1_UNIT_S 0 +#define IG3_DBL_GLPE_CEQPART_DATA1_UNIT_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_CEQPART_DATA1_UNIT_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG 0x42C200A8 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_INST_NUM_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD3_S 20 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD3_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RM_S 16 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RM_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD2_S 14 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD2_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_POWER_GATE_EN_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RME_S 12 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RME_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RME_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD1_S 10 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD1_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ERR_CNT_S 9 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ERR_CNT_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_FIX_CNT_S 8 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_FIX_CNT_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD0_S 6 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_RSVD0_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_MASK_INT_S 5 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_MASK_INT_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_LS_BYPASS_S 4 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_LS_BYPASS_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_LS_FORCE_S 3 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_LS_FORCE_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_INVERT_2_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_INVERT_1_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_EN_S 0 +#define IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_CFG_ECC_EN_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS 0x42C200AC +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_RSVD1_S 30 +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_RSVD1_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_RSVD0_S 4 +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_RSVD0_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_INIT_DONE_S 2 +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_INIT_DONE_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_ECC_FIX_S 1 +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_ECC_FIX_S) +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_ECC_ERR_S 0 +#define IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DBL_GLPE_CQ_DBA_MEM_STATUS_ECC_ERR_S) +#define IG3_DBL_GLPE_DBA_CTRL0 0x42C20014 +#define IG3_DBL_GLPE_DBA_CTRL0_DONE_S 31 +#define IG3_DBL_GLPE_DBA_CTRL0_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBA_CTRL0_DONE_S) +#define IG3_DBL_GLPE_DBA_CTRL0_WR_S 30 +#define IG3_DBL_GLPE_DBA_CTRL0_WR_M RDMA_BIT2(32, IG3_DBL_GLPE_DBA_CTRL0_WR_S) +#define IG3_DBL_GLPE_DBA_CTRL0_SEL_S 29 +#define IG3_DBL_GLPE_DBA_CTRL0_SEL_M RDMA_BIT2(32, IG3_DBL_GLPE_DBA_CTRL0_SEL_S) +#define IG3_DBL_GLPE_DBA_CTRL0_RSVD2_S 28 +#define IG3_DBL_GLPE_DBA_CTRL0_RSVD2_M RDMA_BIT2(32, IG3_DBL_GLPE_DBA_CTRL0_RSVD2_S) +#define IG3_DBL_GLPE_DBA_CTRL0_WRDATA_EN_S 26 +#define IG3_DBL_GLPE_DBA_CTRL0_WRDATA_EN_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBA_CTRL0_WRDATA_EN_S) +#define IG3_DBL_GLPE_DBA_CTRL0_WRDATA_S 24 +#define IG3_DBL_GLPE_DBA_CTRL0_WRDATA_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBA_CTRL0_WRDATA_S) +#define IG3_DBL_GLPE_DBA_CTRL0_RSVD1_S 18 +#define IG3_DBL_GLPE_DBA_CTRL0_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_DBL_GLPE_DBA_CTRL0_RSVD1_S) +#define IG3_DBL_GLPE_DBA_CTRL0_RDDATA_S 16 +#define IG3_DBL_GLPE_DBA_CTRL0_RDDATA_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBA_CTRL0_RDDATA_S) +#define IG3_DBL_GLPE_DBA_CTRL0_RSVD0_S 15 +#define IG3_DBL_GLPE_DBA_CTRL0_RSVD0_M RDMA_BIT2(32, IG3_DBL_GLPE_DBA_CTRL0_RSVD0_S) +#define IG3_DBL_GLPE_DBA_CTRL0_HOSTID_S 12 +#define IG3_DBL_GLPE_DBA_CTRL0_HOSTID_M RDMA_MASK3(32, 0x7, IG3_DBL_GLPE_DBA_CTRL0_HOSTID_S) +#define IG3_DBL_GLPE_DBA_CTRL0_PMF_S 0 +#define IG3_DBL_GLPE_DBA_CTRL0_PMF_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBA_CTRL0_PMF_S) +#define IG3_DBL_GLPE_DBA_CTRL1 0x42C20018 +#define IG3_DBL_GLPE_DBA_CTRL1_RSVD_S 25 +#define IG3_DBL_GLPE_DBA_CTRL1_RSVD_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_DBA_CTRL1_RSVD_S) +#define IG3_DBL_GLPE_DBA_CTRL1_QID_S 0 +#define IG3_DBL_GLPE_DBA_CTRL1_QID_M RDMA_MASK3(32, 0x1FFFFFF, IG3_DBL_GLPE_DBA_CTRL1_QID_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_BUS_INDEX 0x42C20190 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL 0x42C20180 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_RESERVED_31_10_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_TRIG_OP_S 8 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_TRIG_OP_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_FREEZE_RESET_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_CTRL_FREEZE_SET_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_FREEZE_ON_CNT_VAL 0x42C201A0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_OBS_BUS 0x42C201C0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT0 0x42C201E0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT0_CNT0_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT1_0 0x42C201E8 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT1_1 0x42C201EC +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL 0x42C201D8 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_DBL_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_CTRL 0x42C201B8 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_GAP 0x42C201A8 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_RC_GAP_RC_GAP_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_TRNS 0x42C201B0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS 0x42C20188 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_RESERVED_31_8_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_I_FREEZE_S 6 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_I_FREEZE_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_READY_S 5 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_READY_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_VALID_S 4 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_VALID_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB0_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_TRANS_CNT 0x42C20198 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_TRIG_MASK 0x42C201C8 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_DBL_GLPE_DBL_BOB0_BOB_TRIG_VALUE 0x42C201D0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_BUS_INDEX 0x42C20210 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL 0x42C20200 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_RESERVED_31_10_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_TRIG_OP_S 8 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_TRIG_OP_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_FREEZE_RESET_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_CTRL_FREEZE_SET_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_FREEZE_ON_CNT_VAL 0x42C20220 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_OBS_BUS 0x42C20240 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT0 0x42C20260 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT0_CNT0_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT1_0 0x42C20268 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT1_1 0x42C2026C +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL 0x42C20258 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_DBL_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_CTRL 0x42C20238 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_GAP 0x42C20228 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_RC_GAP_RC_GAP_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_TRNS 0x42C20230 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS 0x42C20208 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_RESERVED_31_8_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_I_FREEZE_S 6 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_I_FREEZE_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_READY_S 5 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_READY_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_VALID_S 4 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_VALID_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_BOB1_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_TRANS_CNT 0x42C20218 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_TRIG_MASK 0x42C20248 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_DBL_GLPE_DBL_BOB1_BOB_TRIG_VALUE 0x42C20250 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_DBL_GLPE_DBL_CONFIG 0x42C20000 +#define IG3_DBL_GLPE_DBL_CONFIG_RSVD_S 2 +#define IG3_DBL_GLPE_DBL_CONFIG_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_DBL_GLPE_DBL_CONFIG_RSVD_S) +#define IG3_DBL_GLPE_DBL_CONFIG_DP_CONFIG_S 0 +#define IG3_DBL_GLPE_DBL_CONFIG_DP_CONFIG_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBL_CONFIG_DP_CONFIG_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_COUNT 0x42C20138 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_CMD 0x42C2014C +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_DATA_H 0x42C20158 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_DATA_L 0x42C20154 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_PTR 0x42C20150 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_CMD 0x42C2013C +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_DATA_H 0x42C20148 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_DATA_L 0x42C20144 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_PTR 0x42C20140 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DBL_GLPE_DBL_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_CONTROL 0x42C20100 +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD1_S 25 +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD2_S 17 +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD2_S) +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD3_S 9 +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD3_S) +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_BYPASS_S 8 +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_CONTROL_BYPASS_S) +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD4_S 1 +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_DBL_DTM_CONTROL_RSVD4_S) +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_DBL_GLPE_DBL_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_CONTROL_LOCAL_EN_S) +#define IG3_DBL_GLPE_DBL_DTM_ECC_COR_ERR 0x42C20168 +#define IG3_DBL_GLPE_DBL_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_DBL_GLPE_DBL_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DBL_GLPE_DBL_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_DBL_GLPE_DBL_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_DBL_GLPE_DBL_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBL_DTM_ECC_COR_ERR_CNT_S) +#define IG3_DBL_GLPE_DBL_DTM_ECC_UNCOR_ERR 0x42C20164 +#define IG3_DBL_GLPE_DBL_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DBL_GLPE_DBL_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DBL_GLPE_DBL_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DBL_GLPE_DBL_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DBL_GLPE_DBL_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBL_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_DBL_GLPE_DBL_DTM_GROUP_CFG 0x42C2010C +#define IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_DBL_GLPE_DBL_DTM_LOG_CFG 0x42C20110 +#define IG3_DBL_GLPE_DBL_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_DBL_GLPE_DBL_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_DBL_GLPE_DBL_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_DBL_GLPE_DBL_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_DBL_GLPE_DBL_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_DBL_GLPE_DBL_DTM_LOG_CFG_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_LOG_CFG_MODE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBL_DTM_LOG_CFG_MODE_S) +#define IG3_DBL_GLPE_DBL_DTM_LOG_MASK 0x42C20118 +#define IG3_DBL_GLPE_DBL_DTM_LOG_MASK_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_LOG_MASK_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_LOG_PATTERN 0x42C20114 +#define IG3_DBL_GLPE_DBL_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_LOG_PATTERN_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG 0x42C20104 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_RSVD2_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_RSVD3_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_STS 0x42C20108 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_DBL_GLPE_DBL_DTM_MAIN_STS_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_DBL_DTM_MAIN_STS_RSVD2_S) +#define IG3_DBL_GLPE_DBL_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_DBL_GLPE_DBL_DTM_TIMESTAMP 0x42C20130 +#define IG3_DBL_GLPE_DBL_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_TIMESTAMP_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_TIMESTAMP_ROLLOVER 0x42C20134 +#define IG3_DBL_GLPE_DBL_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG 0x42C2015C +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS 0x42C20160 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DBL_GLPE_DBL_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG 0x42C2011C +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_RSVD1_S) +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_RSVD2_S) +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_MODE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_DBL_DTM_TRIG_CFG_MODE_S) +#define IG3_DBL_GLPE_DBL_DTM_TRIG_COUNT 0x42C20128 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_TRIG_COUNT_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_TRIG_MASK 0x42C20124 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_TRIG_MASK_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_TRIG_PATTERN 0x42C20120 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_DBL_GLPE_DBL_DTM_TRIG_TIMESTAMP 0x42C2012C +#define IG3_DBL_GLPE_DBL_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_DBL_GLPE_DBL_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DBL_GLPE_DBL_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_DBL_GLPE_DBL_ECC_COR_ERR 0x42C200BC +#define IG3_DBL_GLPE_DBL_ECC_COR_ERR_RSVD_S 12 +#define IG3_DBL_GLPE_DBL_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DBL_GLPE_DBL_ECC_COR_ERR_RSVD_S) +#define IG3_DBL_GLPE_DBL_ECC_COR_ERR_CNT_S 0 +#define IG3_DBL_GLPE_DBL_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBL_ECC_COR_ERR_CNT_S) +#define IG3_DBL_GLPE_DBL_ECC_UNCOR_ERR 0x42C200B8 +#define IG3_DBL_GLPE_DBL_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DBL_GLPE_DBL_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DBL_GLPE_DBL_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DBL_GLPE_DBL_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DBL_GLPE_DBL_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBL_ECC_UNCOR_ERR_CNT_S) +#define IG3_DBL_GLPE_DBPT_CTRL 0x42C20020 +#define IG3_DBL_GLPE_DBPT_CTRL_BUSY_S 31 +#define IG3_DBL_GLPE_DBPT_CTRL_BUSY_M RDMA_BIT2(32, IG3_DBL_GLPE_DBPT_CTRL_BUSY_S) +#define IG3_DBL_GLPE_DBPT_CTRL_RSVD1_S 27 +#define IG3_DBL_GLPE_DBPT_CTRL_RSVD1_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_DBPT_CTRL_RSVD1_S) +#define IG3_DBL_GLPE_DBPT_CTRL_DBPTIDX_S 16 +#define IG3_DBL_GLPE_DBPT_CTRL_DBPTIDX_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_DBPT_CTRL_DBPTIDX_S) +#define IG3_DBL_GLPE_DBPT_CTRL_RSVD0_S 1 +#define IG3_DBL_GLPE_DBPT_CTRL_RSVD0_M RDMA_MASK3(32, 0x7FFF, IG3_DBL_GLPE_DBPT_CTRL_RSVD0_S) +#define IG3_DBL_GLPE_DBPT_CTRL_WR_S 0 +#define IG3_DBL_GLPE_DBPT_CTRL_WR_M RDMA_BIT2(32, IG3_DBL_GLPE_DBPT_CTRL_WR_S) +#define IG3_DBL_GLPE_DBPT_DATA0 0x42C20024 +#define IG3_DBL_GLPE_DBPT_DATA0_PAGE_TYPE_S 28 +#define IG3_DBL_GLPE_DBPT_DATA0_PAGE_TYPE_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_DBPT_DATA0_PAGE_TYPE_S) +#define IG3_DBL_GLPE_DBPT_DATA0_VSI_S 16 +#define IG3_DBL_GLPE_DBPT_DATA0_VSI_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBPT_DATA0_VSI_S) +#define IG3_DBL_GLPE_DBPT_DATA0_TC_S 11 +#define IG3_DBL_GLPE_DBPT_DATA0_TC_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_DBPT_DATA0_TC_S) +#define IG3_DBL_GLPE_DBPT_DATA0_PHY_PORT_S 8 +#define IG3_DBL_GLPE_DBPT_DATA0_PHY_PORT_M RDMA_MASK3(32, 0x7, IG3_DBL_GLPE_DBPT_DATA0_PHY_PORT_S) +#define IG3_DBL_GLPE_DBPT_DATA0_RSVD0_S 7 +#define IG3_DBL_GLPE_DBPT_DATA0_RSVD0_M RDMA_BIT2(32, IG3_DBL_GLPE_DBPT_DATA0_RSVD0_S) +#define IG3_DBL_GLPE_DBPT_DATA0_CREDIT_INDEX_S 0 +#define IG3_DBL_GLPE_DBPT_DATA0_CREDIT_INDEX_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_DBPT_DATA0_CREDIT_INDEX_S) +#define IG3_DBL_GLPE_DBPT_DATA1 0x42C20028 +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_S 31 +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_S) +#define IG3_DBL_GLPE_DBPT_DATA1_RSVD_S 23 +#define IG3_DBL_GLPE_DBPT_DATA1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBPT_DATA1_RSVD_S) +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_HOSTID_S 20 +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_HOSTID_M RDMA_MASK3(32, 0x7, IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_HOSTID_S) +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_VDEV_VF_TYPE_S 18 +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_VDEV_VF_TYPE_S) +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_VDEV_VF_S 6 +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_VDEV_VF_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_VDEV_VF_S) +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_PF_S 0 +#define IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_PF_M RDMA_MASK3(32, 0x3F, IG3_DBL_GLPE_DBPT_DATA1_VALIDATE_PF_S) +#define IG3_DBL_GLPE_DBPT_DATA2 0x42C2002C +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_S 31 +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_M RDMA_BIT2(32, IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_S) +#define IG3_DBL_GLPE_DBPT_DATA2_RSVD_S 23 +#define IG3_DBL_GLPE_DBPT_DATA2_RSVD_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DBPT_DATA2_RSVD_S) +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_HOSTID_S 20 +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_HOSTID_M RDMA_MASK3(32, 0x7, IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_HOSTID_S) +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_VDEV_VF_TYPE_S 18 +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_VDEV_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_VDEV_VF_TYPE_S) +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_VDEV_VF_S 6 +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_VDEV_VF_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_VDEV_VF_S) +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_PF_S 0 +#define IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_PF_M RDMA_MASK3(32, 0x3F, IG3_DBL_GLPE_DBPT_DATA2_OVERRIDE_PF_S) +#define IG3_DBL_GLPE_DESTROY_QP_HIGH(_i) 0x42C2000C + ((_i) * 4) /* _i=0...1 */ +#define IG3_DBL_GLPE_DESTROY_QP_HIGH_MAX_INDEX_I 1 +#define IG3_DBL_GLPE_DESTROY_QP_HIGH_VALID_S 31 +#define IG3_DBL_GLPE_DESTROY_QP_HIGH_VALID_M RDMA_BIT2(32, IG3_DBL_GLPE_DESTROY_QP_HIGH_VALID_S) +#define IG3_DBL_GLPE_DESTROY_QP_HIGH_RSVD_S 12 +#define IG3_DBL_GLPE_DESTROY_QP_HIGH_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_DBL_GLPE_DESTROY_QP_HIGH_RSVD_S) +#define IG3_DBL_GLPE_DESTROY_QP_HIGH_PMF_S 0 +#define IG3_DBL_GLPE_DESTROY_QP_HIGH_PMF_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_DESTROY_QP_HIGH_PMF_S) +#define IG3_DBL_GLPE_DESTROY_QP_LOW(_i) 0x42C20004 + ((_i) * 4) /* _i=0...1 */ +#define IG3_DBL_GLPE_DESTROY_QP_LOW_MAX_INDEX_I 1 +#define IG3_DBL_GLPE_DESTROY_QP_LOW_RSVD_S 24 +#define IG3_DBL_GLPE_DESTROY_QP_LOW_RSVD_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_DESTROY_QP_LOW_RSVD_S) +#define IG3_DBL_GLPE_DESTROY_QP_LOW_Q_NUM_S 0 +#define IG3_DBL_GLPE_DESTROY_QP_LOW_Q_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_DBL_GLPE_DESTROY_QP_LOW_Q_NUM_S) +#define IG3_DBL_GLPE_PRLCT_CTRL 0x42C20030 +#define IG3_DBL_GLPE_PRLCT_CTRL_BUSY_S 31 +#define IG3_DBL_GLPE_PRLCT_CTRL_BUSY_M RDMA_BIT2(32, IG3_DBL_GLPE_PRLCT_CTRL_BUSY_S) +#define IG3_DBL_GLPE_PRLCT_CTRL_RSVD2_S 28 +#define IG3_DBL_GLPE_PRLCT_CTRL_RSVD2_M RDMA_MASK3(32, 0x7, IG3_DBL_GLPE_PRLCT_CTRL_RSVD2_S) +#define IG3_DBL_GLPE_PRLCT_CTRL_RL_S 16 +#define IG3_DBL_GLPE_PRLCT_CTRL_RL_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_PRLCT_CTRL_RL_S) +#define IG3_DBL_GLPE_PRLCT_CTRL_RSVD1_S 15 +#define IG3_DBL_GLPE_PRLCT_CTRL_RSVD1_M RDMA_BIT2(32, IG3_DBL_GLPE_PRLCT_CTRL_RSVD1_S) +#define IG3_DBL_GLPE_PRLCT_CTRL_TABLE_INDEX_S 8 +#define IG3_DBL_GLPE_PRLCT_CTRL_TABLE_INDEX_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_PRLCT_CTRL_TABLE_INDEX_S) +#define IG3_DBL_GLPE_PRLCT_CTRL_RSVD0_S 1 +#define IG3_DBL_GLPE_PRLCT_CTRL_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_PRLCT_CTRL_RSVD0_S) +#define IG3_DBL_GLPE_PRLCT_CTRL_WR_S 0 +#define IG3_DBL_GLPE_PRLCT_CTRL_WR_M RDMA_BIT2(32, IG3_DBL_GLPE_PRLCT_CTRL_WR_S) +#define IG3_DBL_GLPE_PRLCT_DATA 0x42C20034 +#define IG3_DBL_GLPE_PRLCT_DATA_VALID_S 31 +#define IG3_DBL_GLPE_PRLCT_DATA_VALID_M RDMA_BIT2(32, IG3_DBL_GLPE_PRLCT_DATA_VALID_S) +#define IG3_DBL_GLPE_PRLCT_DATA_RSVD2_S 23 +#define IG3_DBL_GLPE_PRLCT_DATA_RSVD2_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_PRLCT_DATA_RSVD2_S) +#define IG3_DBL_GLPE_PRLCT_DATA_QUANTA_CREDITS_S 16 +#define IG3_DBL_GLPE_PRLCT_DATA_QUANTA_CREDITS_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_PRLCT_DATA_QUANTA_CREDITS_S) +#define IG3_DBL_GLPE_PRLCT_DATA_RSVD1_S 15 +#define IG3_DBL_GLPE_PRLCT_DATA_RSVD1_M RDMA_BIT2(32, IG3_DBL_GLPE_PRLCT_DATA_RSVD1_S) +#define IG3_DBL_GLPE_PRLCT_DATA_CREDIT_WATERMARK2_S 8 +#define IG3_DBL_GLPE_PRLCT_DATA_CREDIT_WATERMARK2_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_PRLCT_DATA_CREDIT_WATERMARK2_S) +#define IG3_DBL_GLPE_PRLCT_DATA_RSVD0_S 7 +#define IG3_DBL_GLPE_PRLCT_DATA_RSVD0_M RDMA_BIT2(32, IG3_DBL_GLPE_PRLCT_DATA_RSVD0_S) +#define IG3_DBL_GLPE_PRLCT_DATA_CREDIT_WATERMARK1_S 0 +#define IG3_DBL_GLPE_PRLCT_DATA_CREDIT_WATERMARK1_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_PRLCT_DATA_CREDIT_WATERMARK1_S) +#define IG3_DBL_GLPE_PRLCT_DATA1 0x42C20038 +#define IG3_DBL_GLPE_PRLCT_DATA1_RSVD_S 16 +#define IG3_DBL_GLPE_PRLCT_DATA1_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_DBL_GLPE_PRLCT_DATA1_RSVD_S) +#define IG3_DBL_GLPE_PRLCT_DATA1_ERLID_S 0 +#define IG3_DBL_GLPE_PRLCT_DATA1_ERLID_M RDMA_MASK3(32, 0xFFFF, IG3_DBL_GLPE_PRLCT_DATA1_ERLID_S) +#define IG3_DBL_GLPE_PSHINVACCESSTRC(_i) 0x42C20068 + ((_i) * 4) /* _i=0...7 */ +#define IG3_DBL_GLPE_PSHINVACCESSTRC_MAX_INDEX_I 7 +#define IG3_DBL_GLPE_PSHINVACCESSTRC_VALID_S 31 +#define IG3_DBL_GLPE_PSHINVACCESSTRC_VALID_M RDMA_BIT2(32, IG3_DBL_GLPE_PSHINVACCESSTRC_VALID_S) +#define IG3_DBL_GLPE_PSHINVACCESSTRC_RSVD_S 29 +#define IG3_DBL_GLPE_PSHINVACCESSTRC_RSVD_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PSHINVACCESSTRC_RSVD_S) +#define IG3_DBL_GLPE_PSHINVACCESSTRC_PAGEIDX_S 16 +#define IG3_DBL_GLPE_PSHINVACCESSTRC_PAGEIDX_M RDMA_MASK3(32, 0x1FFF, IG3_DBL_GLPE_PSHINVACCESSTRC_PAGEIDX_S) +#define IG3_DBL_GLPE_PSHINVACCESSTRC_OFFSETIDX_S 10 +#define IG3_DBL_GLPE_PSHINVACCESSTRC_OFFSETIDX_M RDMA_MASK3(32, 0x3F, IG3_DBL_GLPE_PSHINVACCESSTRC_OFFSETIDX_S) +#define IG3_DBL_GLPE_PSHINVACCESSTRC_PFVFFLAG_S 8 +#define IG3_DBL_GLPE_PSHINVACCESSTRC_PFVFFLAG_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PSHINVACCESSTRC_PFVFFLAG_S) +#define IG3_DBL_GLPE_PSHINVACCESSTRC_VFIDX_S 0 +#define IG3_DBL_GLPE_PSHINVACCESSTRC_VFIDX_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_PSHINVACCESSTRC_VFIDX_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG 0x42C20088 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD3_S 20 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD3_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RM_S 16 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RM_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD2_S 14 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD2_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RME_S 12 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RME_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD1_S 10 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD1_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ERR_CNT_S 9 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ERR_CNT_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_FIX_CNT_S 8 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_FIX_CNT_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD0_S 6 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_RSVD0_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_MASK_INT_S 5 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_MASK_INT_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_LS_BYPASS_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_LS_FORCE_S 3 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_LS_FORCE_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_EN_S 0 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_CFG_ECC_EN_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS 0x42C2008C +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_RSVD1_S 30 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_RSVD1_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_RSVD0_S 4 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_RSVD0_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_INIT_DONE_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_ECC_FIX_S) +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER0_MEM_STATUS_ECC_ERR_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG 0x42C20090 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD3_S 20 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD3_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RM_S 16 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RM_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD2_S 14 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD2_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RME_S 12 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RME_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD1_S 10 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD1_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ERR_CNT_S 9 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ERR_CNT_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_FIX_CNT_S 8 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_FIX_CNT_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD0_S 6 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_RSVD0_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_MASK_INT_S 5 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_MASK_INT_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_LS_BYPASS_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_LS_FORCE_S 3 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_LS_FORCE_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_EN_S 0 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_CFG_ECC_EN_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS 0x42C20094 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_RSVD1_S 30 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_RSVD1_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_RSVD0_S 4 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_RSVD0_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_INIT_DONE_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_ECC_FIX_S) +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_BUFFER1_MEM_STATUS_ECC_ERR_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG 0x42C20098 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD3_S 20 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD3_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RM_S 16 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RM_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD2_S 14 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD2_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RME_S 12 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RME_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD1_S 10 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD1_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ERR_CNT_S 9 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ERR_CNT_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_FIX_CNT_S 8 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_FIX_CNT_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD0_S 6 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_RSVD0_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_MASK_INT_S 5 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_MASK_INT_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_LS_BYPASS_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_LS_FORCE_S 3 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_LS_FORCE_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_EN_S 0 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_CFG_ECC_EN_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS 0x42C2009C +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_RSVD1_S 30 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_RSVD1_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_RSVD0_S 4 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_RSVD0_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_INIT_DONE_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_ECC_FIX_S) +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DBL_GLPE_PUSH_DBPT_MEM_STATUS_ECC_ERR_S) +#define IG3_DBL_GLPE_PUSH_GCPERIOD 0x42C2001C +#define IG3_DBL_GLPE_PUSH_GCPERIOD_PERIOD_S 10 +#define IG3_DBL_GLPE_PUSH_GCPERIOD_PERIOD_M RDMA_MASK3(32, 0x3FFFFF, IG3_DBL_GLPE_PUSH_GCPERIOD_PERIOD_S) +#define IG3_DBL_GLPE_PUSH_GCPERIOD_LOBITS_S 0 +#define IG3_DBL_GLPE_PUSH_GCPERIOD_LOBITS_M RDMA_MASK3(32, 0x3FF, IG3_DBL_GLPE_PUSH_GCPERIOD_LOBITS_S) +#define IG3_DBL_GLPE_PUSH_SCHED_CONFIG 0x42C2005C +#define IG3_DBL_GLPE_PUSH_SCHED_CONFIG_RSVD_S 14 +#define IG3_DBL_GLPE_PUSH_SCHED_CONFIG_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_DBL_GLPE_PUSH_SCHED_CONFIG_RSVD_S) +#define IG3_DBL_GLPE_PUSH_SCHED_CONFIG_QUANTA_S 0 +#define IG3_DBL_GLPE_PUSH_SCHED_CONFIG_QUANTA_M RDMA_MASK3(32, 0x3FFF, IG3_DBL_GLPE_PUSH_SCHED_CONFIG_QUANTA_S) +#define IG3_DBL_GLPE_QPART_CTRL0 0x42C2003C +#define IG3_DBL_GLPE_QPART_CTRL0_BUSY_S 31 +#define IG3_DBL_GLPE_QPART_CTRL0_BUSY_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_CTRL0_BUSY_S) +#define IG3_DBL_GLPE_QPART_CTRL0_RSVD1_S 19 +#define IG3_DBL_GLPE_QPART_CTRL0_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_QPART_CTRL0_RSVD1_S) +#define IG3_DBL_GLPE_QPART_CTRL0_ADDR_S 8 +#define IG3_DBL_GLPE_QPART_CTRL0_ADDR_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_QPART_CTRL0_ADDR_S) +#define IG3_DBL_GLPE_QPART_CTRL0_RSVD0_S 3 +#define IG3_DBL_GLPE_QPART_CTRL0_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_QPART_CTRL0_RSVD0_S) +#define IG3_DBL_GLPE_QPART_CTRL0_OP_S 0 +#define IG3_DBL_GLPE_QPART_CTRL0_OP_M RDMA_MASK3(32, 0x7, IG3_DBL_GLPE_QPART_CTRL0_OP_S) +#define IG3_DBL_GLPE_QPART_CTRL1 0x42C20040 +#define IG3_DBL_GLPE_QPART_CTRL1_VALID_MASK_S 31 +#define IG3_DBL_GLPE_QPART_CTRL1_VALID_MASK_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_CTRL1_VALID_MASK_S) +#define IG3_DBL_GLPE_QPART_CTRL1_VALID_S 30 +#define IG3_DBL_GLPE_QPART_CTRL1_VALID_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_CTRL1_VALID_S) +#define IG3_DBL_GLPE_QPART_CTRL1_PMF_MASK_S 29 +#define IG3_DBL_GLPE_QPART_CTRL1_PMF_MASK_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_CTRL1_PMF_MASK_S) +#define IG3_DBL_GLPE_QPART_CTRL1_RSVD1_S 27 +#define IG3_DBL_GLPE_QPART_CTRL1_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_QPART_CTRL1_RSVD1_S) +#define IG3_DBL_GLPE_QPART_CTRL1_PMF_S 16 +#define IG3_DBL_GLPE_QPART_CTRL1_PMF_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_QPART_CTRL1_PMF_S) +#define IG3_DBL_GLPE_QPART_CTRL1_QUEUE_MASK_S 15 +#define IG3_DBL_GLPE_QPART_CTRL1_QUEUE_MASK_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_CTRL1_QUEUE_MASK_S) +#define IG3_DBL_GLPE_QPART_CTRL1_RSVD0_S 11 +#define IG3_DBL_GLPE_QPART_CTRL1_RSVD0_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_QPART_CTRL1_RSVD0_S) +#define IG3_DBL_GLPE_QPART_CTRL1_QUEUE_S 0 +#define IG3_DBL_GLPE_QPART_CTRL1_QUEUE_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_QPART_CTRL1_QUEUE_S) +#define IG3_DBL_GLPE_QPART_DATA0 0x42C20044 +#define IG3_DBL_GLPE_QPART_DATA0_RSVD1_S 31 +#define IG3_DBL_GLPE_QPART_DATA0_RSVD1_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_DATA0_RSVD1_S) +#define IG3_DBL_GLPE_QPART_DATA0_HITCNT_S 19 +#define IG3_DBL_GLPE_QPART_DATA0_HITCNT_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_QPART_DATA0_HITCNT_S) +#define IG3_DBL_GLPE_QPART_DATA0_ADDR_S 8 +#define IG3_DBL_GLPE_QPART_DATA0_ADDR_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_QPART_DATA0_ADDR_S) +#define IG3_DBL_GLPE_QPART_DATA0_RSVD0_S 0 +#define IG3_DBL_GLPE_QPART_DATA0_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_QPART_DATA0_RSVD0_S) +#define IG3_DBL_GLPE_QPART_DATA1 0x42C20048 +#define IG3_DBL_GLPE_QPART_DATA1_RSVD1_S 31 +#define IG3_DBL_GLPE_QPART_DATA1_RSVD1_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_DATA1_RSVD1_S) +#define IG3_DBL_GLPE_QPART_DATA1_VALID_S 30 +#define IG3_DBL_GLPE_QPART_DATA1_VALID_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_DATA1_VALID_S) +#define IG3_DBL_GLPE_QPART_DATA1_ERROR_S 29 +#define IG3_DBL_GLPE_QPART_DATA1_ERROR_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_DATA1_ERROR_S) +#define IG3_DBL_GLPE_QPART_DATA1_HIT_S 28 +#define IG3_DBL_GLPE_QPART_DATA1_HIT_M RDMA_BIT2(32, IG3_DBL_GLPE_QPART_DATA1_HIT_S) +#define IG3_DBL_GLPE_QPART_DATA1_PMF_S 16 +#define IG3_DBL_GLPE_QPART_DATA1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_QPART_DATA1_PMF_S) +#define IG3_DBL_GLPE_QPART_DATA1_RSVD0_S 11 +#define IG3_DBL_GLPE_QPART_DATA1_RSVD0_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_QPART_DATA1_RSVD0_S) +#define IG3_DBL_GLPE_QPART_DATA1_QUEUE_S 0 +#define IG3_DBL_GLPE_QPART_DATA1_QUEUE_M RDMA_MASK3(32, 0x7FF, IG3_DBL_GLPE_QPART_DATA1_QUEUE_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG 0x42C200A0 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_INST_NUM_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD3_S 20 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD3_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RM_S 16 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_QP_DBA_MEM_CFG_RM_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD2_S 14 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD2_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_POWER_GATE_EN_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RME_S 12 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RME_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_RME_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD1_S 10 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD1_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ERR_CNT_S 9 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_ERR_CNT_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_FIX_CNT_S 8 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_FIX_CNT_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD0_S 6 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_QP_DBA_MEM_CFG_RSVD0_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_MASK_INT_S 5 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_MASK_INT_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_LS_BYPASS_S 4 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_LS_BYPASS_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_LS_FORCE_S 3 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_LS_FORCE_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_INVERT_2_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_INVERT_1_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_EN_S 0 +#define IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_CFG_ECC_EN_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS 0x42C200A4 +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_RSVD1_S 30 +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_QP_DBA_MEM_STATUS_RSVD1_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DBL_GLPE_QP_DBA_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_RSVD0_S 4 +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_QP_DBA_MEM_STATUS_RSVD0_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_INIT_DONE_S 2 +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_STATUS_INIT_DONE_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_ECC_FIX_S 1 +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_STATUS_ECC_FIX_S) +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_ECC_ERR_S 0 +#define IG3_DBL_GLPE_QP_DBA_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DBL_GLPE_QP_DBA_MEM_STATUS_ECC_ERR_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL 0x42C20060 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_BUSY_S 31 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_BUSY_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_BUSY_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_RSVD1_S 26 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_RSVD1_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_RSVD1_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_MAPIDX_S 16 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_MAPIDX_M RDMA_MASK3(32, 0x3FF, IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_MAPIDX_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_RSVD0_S 1 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_RSVD0_M RDMA_MASK3(32, 0x7FFF, IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_RSVD0_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_WR_S 0 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_WR_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_CTRL_WR_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA 0x42C20064 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_RSVD1_S 29 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_RSVD1_M RDMA_MASK3(32, 0x7, IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_RSVD1_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_BASE_S 16 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_BASE_M RDMA_MASK3(32, 0x1FFF, IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_BASE_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_RSVD0_S 4 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_RSVD0_M RDMA_MASK3(32, 0xFFF, IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_RSVD0_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_SIZE_S 0 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_SIZE_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_VF_DBPAGE_MAP_DATA_SIZE_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG 0x42C200B0 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_INST_NUM_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD3_S 20 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD3_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RM_S 16 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RM_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD2_S 14 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD2_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_POWER_GATE_EN_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RME_S 12 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RME_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RME_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD1_S 10 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD1_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ERR_CNT_S 9 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ERR_CNT_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_FIX_CNT_S 8 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_FIX_CNT_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD0_S 6 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_RSVD0_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_MASK_INT_S 5 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_MASK_INT_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_LS_BYPASS_S 4 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_LS_BYPASS_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_LS_FORCE_S 3 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_LS_FORCE_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_INVERT_2_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_INVERT_1_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_EN_S 0 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_CFG_ECC_EN_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS 0x42C200B4 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_RSVD1_S 30 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_RSVD1_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_RSVD0_S 4 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_RSVD0_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_INIT_DONE_S 2 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_INIT_DONE_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_ECC_FIX_S 1 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_ECC_FIX_S) +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_ECC_ERR_S 0 +#define IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DBL_GLPE_VF_DBPAGE_MAP_MEM_STATUS_ECC_ERR_S) +#define IG3_RHI_CQM_CLIENT_CRED_HOST(_i) 0x42C30014 + ((_i) * 4) /* _i=0...4 */ +#define IG3_RHI_CQM_CLIENT_CRED_HOST_MAX_INDEX_I 4 +#define IG3_RHI_CQM_CLIENT_CRED_HOST_RSVD_S 16 +#define IG3_RHI_CQM_CLIENT_CRED_HOST_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_RHI_CQM_CLIENT_CRED_HOST_RSVD_S) +#define IG3_RHI_CQM_CLIENT_CRED_HOST_DATA_CRED_S 8 +#define IG3_RHI_CQM_CLIENT_CRED_HOST_DATA_CRED_M RDMA_MASK3(32, 0xFF, IG3_RHI_CQM_CLIENT_CRED_HOST_DATA_CRED_S) +#define IG3_RHI_CQM_CLIENT_CRED_HOST_CMD_CRED_S 0 +#define IG3_RHI_CQM_CLIENT_CRED_HOST_CMD_CRED_M RDMA_MASK3(32, 0xFF, IG3_RHI_CQM_CLIENT_CRED_HOST_CMD_CRED_S) +#define IG3_RHI_CQM_CMD_MEM_CFG 0x42C300F0 +#define IG3_RHI_CQM_CMD_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_RHI_CQM_CMD_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RHI_CQM_CMD_MEM_CFG_ECC_INST_NUM_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_RSVD3_S 20 +#define IG3_RHI_CQM_CMD_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RHI_CQM_CMD_MEM_CFG_RSVD3_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_RM_S 16 +#define IG3_RHI_CQM_CMD_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RHI_CQM_CMD_MEM_CFG_RM_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_RSVD2_S 14 +#define IG3_RHI_CQM_CMD_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RHI_CQM_CMD_MEM_CFG_RSVD2_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_RHI_CQM_CMD_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_POWER_GATE_EN_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_RME_S 12 +#define IG3_RHI_CQM_CMD_MEM_CFG_RME_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_RME_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_RSVD1_S 10 +#define IG3_RHI_CQM_CMD_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_CQM_CMD_MEM_CFG_RSVD1_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_ERR_CNT_S 9 +#define IG3_RHI_CQM_CMD_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_ERR_CNT_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_FIX_CNT_S 8 +#define IG3_RHI_CQM_CMD_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_FIX_CNT_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_RSVD0_S 6 +#define IG3_RHI_CQM_CMD_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RHI_CQM_CMD_MEM_CFG_RSVD0_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_MASK_INT_S 5 +#define IG3_RHI_CQM_CMD_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_MASK_INT_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_LS_BYPASS_S 4 +#define IG3_RHI_CQM_CMD_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_LS_BYPASS_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_LS_FORCE_S 3 +#define IG3_RHI_CQM_CMD_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_LS_FORCE_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_RHI_CQM_CMD_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_ECC_INVERT_2_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_RHI_CQM_CMD_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_ECC_INVERT_1_S) +#define IG3_RHI_CQM_CMD_MEM_CFG_ECC_EN_S 0 +#define IG3_RHI_CQM_CMD_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_CFG_ECC_EN_S) +#define IG3_RHI_CQM_CMD_MEM_STATUS 0x42C300EC +#define IG3_RHI_CQM_CMD_MEM_STATUS_RSVD1_S 30 +#define IG3_RHI_CQM_CMD_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_CQM_CMD_MEM_STATUS_RSVD1_S) +#define IG3_RHI_CQM_CMD_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RHI_CQM_CMD_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RHI_CQM_CMD_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RHI_CQM_CMD_MEM_STATUS_RSVD0_S 4 +#define IG3_RHI_CQM_CMD_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RHI_CQM_CMD_MEM_STATUS_RSVD0_S) +#define IG3_RHI_CQM_CMD_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RHI_CQM_CMD_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RHI_CQM_CMD_MEM_STATUS_INIT_DONE_S 2 +#define IG3_RHI_CQM_CMD_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_STATUS_INIT_DONE_S) +#define IG3_RHI_CQM_CMD_MEM_STATUS_ECC_FIX_S 1 +#define IG3_RHI_CQM_CMD_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_STATUS_ECC_FIX_S) +#define IG3_RHI_CQM_CMD_MEM_STATUS_ECC_ERR_S 0 +#define IG3_RHI_CQM_CMD_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RHI_CQM_CMD_MEM_STATUS_ECC_ERR_S) +#define IG3_RHI_CQM_DATA_MEM_CFG 0x42C300F8 +#define IG3_RHI_CQM_DATA_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_RHI_CQM_DATA_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RHI_CQM_DATA_MEM_CFG_ECC_INST_NUM_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_RSVD3_S 20 +#define IG3_RHI_CQM_DATA_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RHI_CQM_DATA_MEM_CFG_RSVD3_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_RM_S 16 +#define IG3_RHI_CQM_DATA_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RHI_CQM_DATA_MEM_CFG_RM_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_RSVD2_S 14 +#define IG3_RHI_CQM_DATA_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RHI_CQM_DATA_MEM_CFG_RSVD2_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_RHI_CQM_DATA_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_POWER_GATE_EN_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_RME_S 12 +#define IG3_RHI_CQM_DATA_MEM_CFG_RME_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_RME_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_RSVD1_S 10 +#define IG3_RHI_CQM_DATA_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_CQM_DATA_MEM_CFG_RSVD1_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_ERR_CNT_S 9 +#define IG3_RHI_CQM_DATA_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_ERR_CNT_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_FIX_CNT_S 8 +#define IG3_RHI_CQM_DATA_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_FIX_CNT_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_RSVD0_S 6 +#define IG3_RHI_CQM_DATA_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RHI_CQM_DATA_MEM_CFG_RSVD0_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_MASK_INT_S 5 +#define IG3_RHI_CQM_DATA_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_MASK_INT_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_LS_BYPASS_S 4 +#define IG3_RHI_CQM_DATA_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_LS_BYPASS_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_LS_FORCE_S 3 +#define IG3_RHI_CQM_DATA_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_LS_FORCE_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_RHI_CQM_DATA_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_ECC_INVERT_2_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_RHI_CQM_DATA_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_ECC_INVERT_1_S) +#define IG3_RHI_CQM_DATA_MEM_CFG_ECC_EN_S 0 +#define IG3_RHI_CQM_DATA_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_CFG_ECC_EN_S) +#define IG3_RHI_CQM_DATA_MEM_STATUS 0x42C300F4 +#define IG3_RHI_CQM_DATA_MEM_STATUS_RSVD1_S 30 +#define IG3_RHI_CQM_DATA_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_CQM_DATA_MEM_STATUS_RSVD1_S) +#define IG3_RHI_CQM_DATA_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RHI_CQM_DATA_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RHI_CQM_DATA_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RHI_CQM_DATA_MEM_STATUS_RSVD0_S 4 +#define IG3_RHI_CQM_DATA_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RHI_CQM_DATA_MEM_STATUS_RSVD0_S) +#define IG3_RHI_CQM_DATA_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RHI_CQM_DATA_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RHI_CQM_DATA_MEM_STATUS_INIT_DONE_S 2 +#define IG3_RHI_CQM_DATA_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_STATUS_INIT_DONE_S) +#define IG3_RHI_CQM_DATA_MEM_STATUS_ECC_FIX_S 1 +#define IG3_RHI_CQM_DATA_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_STATUS_ECC_FIX_S) +#define IG3_RHI_CQM_DATA_MEM_STATUS_ECC_ERR_S 0 +#define IG3_RHI_CQM_DATA_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RHI_CQM_DATA_MEM_STATUS_ECC_ERR_S) +#define IG3_RHI_DEST_ARB_EN_MODE 0x42C3003C +#define IG3_RHI_DEST_ARB_EN_MODE_RSVD_S 2 +#define IG3_RHI_DEST_ARB_EN_MODE_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_RHI_DEST_ARB_EN_MODE_RSVD_S) +#define IG3_RHI_DEST_ARB_EN_MODE_ARB_MODE_S 0 +#define IG3_RHI_DEST_ARB_EN_MODE_ARB_MODE_M RDMA_MASK3(32, 0x3, IG3_RHI_DEST_ARB_EN_MODE_ARB_MODE_S) +#define IG3_RHI_DEST_SPRR_ARB(_i) 0x42C30040 + ((_i) * 4) /* _i=0...2 */ +#define IG3_RHI_DEST_SPRR_ARB_MAX_INDEX_I 2 +#define IG3_RHI_DEST_SPRR_ARB_RSVD_S 4 +#define IG3_RHI_DEST_SPRR_ARB_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_RHI_DEST_SPRR_ARB_RSVD_S) +#define IG3_RHI_DEST_SPRR_ARB_SPRR_WEIGHT_S 0 +#define IG3_RHI_DEST_SPRR_ARB_SPRR_WEIGHT_M RDMA_MASK3(32, 0xF, IG3_RHI_DEST_SPRR_ARB_SPRR_WEIGHT_S) +#define IG3_RHI_DEST_WRR_ARB(_i) 0x42C3004C + ((_i) * 4) /* _i=0...2 */ +#define IG3_RHI_DEST_WRR_ARB_MAX_INDEX_I 2 +#define IG3_RHI_DEST_WRR_ARB_RSVD_S 14 +#define IG3_RHI_DEST_WRR_ARB_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_RHI_DEST_WRR_ARB_RSVD_S) +#define IG3_RHI_DEST_WRR_ARB_WRR_WEIGHT_CRED_S 4 +#define IG3_RHI_DEST_WRR_ARB_WRR_WEIGHT_CRED_M RDMA_MASK3(32, 0x3FF, IG3_RHI_DEST_WRR_ARB_WRR_WEIGHT_CRED_S) +#define IG3_RHI_DEST_WRR_ARB_WRR_WEIGHT_S 0 +#define IG3_RHI_DEST_WRR_ARB_WRR_WEIGHT_M RDMA_MASK3(32, 0xF, IG3_RHI_DEST_WRR_ARB_WRR_WEIGHT_S) +#define IG3_RHI_GKT_ARB_EN_MODE 0x42C30058 +#define IG3_RHI_GKT_ARB_EN_MODE_RSVD_S 2 +#define IG3_RHI_GKT_ARB_EN_MODE_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_RHI_GKT_ARB_EN_MODE_RSVD_S) +#define IG3_RHI_GKT_ARB_EN_MODE_ARB_MODE_S 0 +#define IG3_RHI_GKT_ARB_EN_MODE_ARB_MODE_M RDMA_MASK3(32, 0x3, IG3_RHI_GKT_ARB_EN_MODE_ARB_MODE_S) +#define IG3_RHI_GKT_MASK_CRED 0x42C300D4 +#define IG3_RHI_GKT_MASK_CRED_RSVD_S 9 +#define IG3_RHI_GKT_MASK_CRED_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_RHI_GKT_MASK_CRED_RSVD_S) +#define IG3_RHI_GKT_MASK_CRED_MASK_DATA_CRED_S 1 +#define IG3_RHI_GKT_MASK_CRED_MASK_DATA_CRED_M RDMA_MASK3(32, 0xFF, IG3_RHI_GKT_MASK_CRED_MASK_DATA_CRED_S) +#define IG3_RHI_GKT_MASK_CRED_MASK_EN_S 0 +#define IG3_RHI_GKT_MASK_CRED_MASK_EN_M RDMA_BIT2(32, IG3_RHI_GKT_MASK_CRED_MASK_EN_S) +#define IG3_RHI_GKT_SPRR_ARB(_i) 0x42C3005C + ((_i) * 4) /* _i=0...14 */ +#define IG3_RHI_GKT_SPRR_ARB_MAX_INDEX_I 14 +#define IG3_RHI_GKT_SPRR_ARB_RSVD_S 4 +#define IG3_RHI_GKT_SPRR_ARB_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_RHI_GKT_SPRR_ARB_RSVD_S) +#define IG3_RHI_GKT_SPRR_ARB_SPRR_WEIGHT_S 0 +#define IG3_RHI_GKT_SPRR_ARB_SPRR_WEIGHT_M RDMA_MASK3(32, 0xF, IG3_RHI_GKT_SPRR_ARB_SPRR_WEIGHT_S) +#define IG3_RHI_GKT_WRR_ARB(_i) 0x42C30098 + ((_i) * 4) /* _i=0...14 */ +#define IG3_RHI_GKT_WRR_ARB_MAX_INDEX_I 14 +#define IG3_RHI_GKT_WRR_ARB_RSVD_S 14 +#define IG3_RHI_GKT_WRR_ARB_RSVD_M RDMA_MASK3(32, 0x3FFFF, IG3_RHI_GKT_WRR_ARB_RSVD_S) +#define IG3_RHI_GKT_WRR_ARB_WRR_WEIGHT_CRED_S 4 +#define IG3_RHI_GKT_WRR_ARB_WRR_WEIGHT_CRED_M RDMA_MASK3(32, 0x3FF, IG3_RHI_GKT_WRR_ARB_WRR_WEIGHT_CRED_S) +#define IG3_RHI_GKT_WRR_ARB_WRR_WEIGHT_S 0 +#define IG3_RHI_GKT_WRR_ARB_WRR_WEIGHT_M RDMA_MASK3(32, 0xF, IG3_RHI_GKT_WRR_ARB_WRR_WEIGHT_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_BUS_INDEX 0x42C30210 +#define IG3_RHI_GLPE_RHI_BOB_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL 0x42C30200 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_TRIG_OP_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_CTRL_FREEZE_SET_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_FREEZE_ON_CNT_VAL 0x42C30220 +#define IG3_RHI_GLPE_RHI_BOB_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_OBS_BUS 0x42C30240 +#define IG3_RHI_GLPE_RHI_BOB_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT0 0x42C30260 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT0_CNT0_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT1_0 0x42C30268 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT1_1 0x42C3026C +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL 0x42C30258 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RHI_GLPE_RHI_BOB_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_CTRL 0x42C30238 +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_GAP 0x42C30228 +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_RC_GAP_RC_GAP_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_TRNS 0x42C30230 +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS 0x42C30208 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_I_FREEZE_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_READY_S 5 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_READY_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_VALID_S 4 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_VALID_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_BOB_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_TRANS_CNT 0x42C30218 +#define IG3_RHI_GLPE_RHI_BOB_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_TRIG_MASK 0x42C30248 +#define IG3_RHI_GLPE_RHI_BOB_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RHI_GLPE_RHI_BOB_BOB_TRIG_VALUE 0x42C30250 +#define IG3_RHI_GLPE_RHI_BOB_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_BOB_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_BOB_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_COUNT 0x42C301B8 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_CMD 0x42C301CC +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_DATA_H 0x42C301D8 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_DATA_L 0x42C301D4 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_PTR 0x42C301D0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_CMD 0x42C301BC +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_DATA_H 0x42C301C8 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_DATA_L 0x42C301C4 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_PTR 0x42C301C0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RHI_GLPE_RHI_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_CONTROL 0x42C30180 +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD1_S 25 +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD2_S 17 +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD2_S) +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD3_S 9 +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD3_S) +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_BYPASS_S 8 +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_CONTROL_BYPASS_S) +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD4_S 1 +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_RHI_GLPE_RHI_DTM_CONTROL_RSVD4_S) +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_RHI_GLPE_RHI_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_CONTROL_LOCAL_EN_S) +#define IG3_RHI_GLPE_RHI_DTM_ECC_COR_ERR 0x42C301E8 +#define IG3_RHI_GLPE_RHI_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_RHI_GLPE_RHI_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RHI_GLPE_RHI_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_RHI_GLPE_RHI_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_RHI_GLPE_RHI_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RHI_GLPE_RHI_DTM_ECC_COR_ERR_CNT_S) +#define IG3_RHI_GLPE_RHI_DTM_ECC_UNCOR_ERR 0x42C301E4 +#define IG3_RHI_GLPE_RHI_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_RHI_GLPE_RHI_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RHI_GLPE_RHI_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_RHI_GLPE_RHI_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_RHI_GLPE_RHI_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RHI_GLPE_RHI_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_RHI_GLPE_RHI_DTM_GROUP_CFG 0x42C3018C +#define IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RHI_GLPE_RHI_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_RHI_GLPE_RHI_DTM_LOG_CFG 0x42C30190 +#define IG3_RHI_GLPE_RHI_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_RHI_GLPE_RHI_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_RHI_GLPE_RHI_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_RHI_GLPE_RHI_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_RHI_GLPE_RHI_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_RHI_GLPE_RHI_DTM_LOG_CFG_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_LOG_CFG_MODE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_RHI_GLPE_RHI_DTM_LOG_CFG_MODE_S) +#define IG3_RHI_GLPE_RHI_DTM_LOG_MASK 0x42C30198 +#define IG3_RHI_GLPE_RHI_DTM_LOG_MASK_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_LOG_MASK_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_LOG_PATTERN 0x42C30194 +#define IG3_RHI_GLPE_RHI_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_LOG_PATTERN_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG 0x42C30184 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_RSVD2_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_RSVD3_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_STS 0x42C30188 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_RHI_GLPE_RHI_DTM_MAIN_STS_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RHI_GLPE_RHI_DTM_MAIN_STS_RSVD2_S) +#define IG3_RHI_GLPE_RHI_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_RHI_GLPE_RHI_DTM_TIMESTAMP 0x42C301B0 +#define IG3_RHI_GLPE_RHI_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_TIMESTAMP_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_TIMESTAMP_ROLLOVER 0x42C301B4 +#define IG3_RHI_GLPE_RHI_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG 0x42C301DC +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS 0x42C301E0 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RHI_GLPE_RHI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG 0x42C3019C +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_RSVD1_S) +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_RSVD2_S) +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_MODE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_RHI_GLPE_RHI_DTM_TRIG_CFG_MODE_S) +#define IG3_RHI_GLPE_RHI_DTM_TRIG_COUNT 0x42C301A8 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_TRIG_COUNT_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_TRIG_MASK 0x42C301A4 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_TRIG_MASK_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_TRIG_PATTERN 0x42C301A0 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_RHI_GLPE_RHI_DTM_TRIG_TIMESTAMP 0x42C301AC +#define IG3_RHI_GLPE_RHI_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_RHI_GLPE_RHI_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RHI_GLPE_RHI_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_RHI_PMAT_CLIENT_CRED_HOST(_i) 0x42C30028 + ((_i) * 4) /* _i=0...4 */ +#define IG3_RHI_PMAT_CLIENT_CRED_HOST_MAX_INDEX_I 4 +#define IG3_RHI_PMAT_CLIENT_CRED_HOST_RSVD_S 16 +#define IG3_RHI_PMAT_CLIENT_CRED_HOST_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_RHI_PMAT_CLIENT_CRED_HOST_RSVD_S) +#define IG3_RHI_PMAT_CLIENT_CRED_HOST_DATA_CRED_S 8 +#define IG3_RHI_PMAT_CLIENT_CRED_HOST_DATA_CRED_M RDMA_MASK3(32, 0xFF, IG3_RHI_PMAT_CLIENT_CRED_HOST_DATA_CRED_S) +#define IG3_RHI_PMAT_CLIENT_CRED_HOST_CMD_CRED_S 0 +#define IG3_RHI_PMAT_CLIENT_CRED_HOST_CMD_CRED_M RDMA_MASK3(32, 0xFF, IG3_RHI_PMAT_CLIENT_CRED_HOST_CMD_CRED_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG 0x42C30100 +#define IG3_RHI_PMAT_CMD_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_RHI_PMAT_CMD_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RHI_PMAT_CMD_MEM_CFG_ECC_INST_NUM_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_RSVD3_S 20 +#define IG3_RHI_PMAT_CMD_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RHI_PMAT_CMD_MEM_CFG_RSVD3_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_RM_S 16 +#define IG3_RHI_PMAT_CMD_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RHI_PMAT_CMD_MEM_CFG_RM_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_RSVD2_S 14 +#define IG3_RHI_PMAT_CMD_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RHI_PMAT_CMD_MEM_CFG_RSVD2_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_RHI_PMAT_CMD_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_POWER_GATE_EN_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_RME_S 12 +#define IG3_RHI_PMAT_CMD_MEM_CFG_RME_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_RME_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_RSVD1_S 10 +#define IG3_RHI_PMAT_CMD_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_PMAT_CMD_MEM_CFG_RSVD1_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_ERR_CNT_S 9 +#define IG3_RHI_PMAT_CMD_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_ERR_CNT_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_FIX_CNT_S 8 +#define IG3_RHI_PMAT_CMD_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_FIX_CNT_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_RSVD0_S 6 +#define IG3_RHI_PMAT_CMD_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RHI_PMAT_CMD_MEM_CFG_RSVD0_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_MASK_INT_S 5 +#define IG3_RHI_PMAT_CMD_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_MASK_INT_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_LS_BYPASS_S 4 +#define IG3_RHI_PMAT_CMD_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_LS_BYPASS_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_LS_FORCE_S 3 +#define IG3_RHI_PMAT_CMD_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_LS_FORCE_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_RHI_PMAT_CMD_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_ECC_INVERT_2_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_RHI_PMAT_CMD_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_ECC_INVERT_1_S) +#define IG3_RHI_PMAT_CMD_MEM_CFG_ECC_EN_S 0 +#define IG3_RHI_PMAT_CMD_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_CFG_ECC_EN_S) +#define IG3_RHI_PMAT_CMD_MEM_STATUS 0x42C300FC +#define IG3_RHI_PMAT_CMD_MEM_STATUS_RSVD1_S 30 +#define IG3_RHI_PMAT_CMD_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_PMAT_CMD_MEM_STATUS_RSVD1_S) +#define IG3_RHI_PMAT_CMD_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RHI_PMAT_CMD_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RHI_PMAT_CMD_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RHI_PMAT_CMD_MEM_STATUS_RSVD0_S 4 +#define IG3_RHI_PMAT_CMD_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RHI_PMAT_CMD_MEM_STATUS_RSVD0_S) +#define IG3_RHI_PMAT_CMD_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RHI_PMAT_CMD_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RHI_PMAT_CMD_MEM_STATUS_INIT_DONE_S 2 +#define IG3_RHI_PMAT_CMD_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_STATUS_INIT_DONE_S) +#define IG3_RHI_PMAT_CMD_MEM_STATUS_ECC_FIX_S 1 +#define IG3_RHI_PMAT_CMD_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_STATUS_ECC_FIX_S) +#define IG3_RHI_PMAT_CMD_MEM_STATUS_ECC_ERR_S 0 +#define IG3_RHI_PMAT_CMD_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RHI_PMAT_CMD_MEM_STATUS_ECC_ERR_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG 0x42C30108 +#define IG3_RHI_PMAT_DATA_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_RHI_PMAT_DATA_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RHI_PMAT_DATA_MEM_CFG_ECC_INST_NUM_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_RSVD3_S 20 +#define IG3_RHI_PMAT_DATA_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RHI_PMAT_DATA_MEM_CFG_RSVD3_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_RM_S 16 +#define IG3_RHI_PMAT_DATA_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RHI_PMAT_DATA_MEM_CFG_RM_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_RSVD2_S 14 +#define IG3_RHI_PMAT_DATA_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RHI_PMAT_DATA_MEM_CFG_RSVD2_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_RHI_PMAT_DATA_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_POWER_GATE_EN_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_RME_S 12 +#define IG3_RHI_PMAT_DATA_MEM_CFG_RME_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_RME_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_RSVD1_S 10 +#define IG3_RHI_PMAT_DATA_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_PMAT_DATA_MEM_CFG_RSVD1_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_ERR_CNT_S 9 +#define IG3_RHI_PMAT_DATA_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_ERR_CNT_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_FIX_CNT_S 8 +#define IG3_RHI_PMAT_DATA_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_FIX_CNT_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_RSVD0_S 6 +#define IG3_RHI_PMAT_DATA_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RHI_PMAT_DATA_MEM_CFG_RSVD0_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_MASK_INT_S 5 +#define IG3_RHI_PMAT_DATA_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_MASK_INT_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_LS_BYPASS_S 4 +#define IG3_RHI_PMAT_DATA_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_LS_BYPASS_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_LS_FORCE_S 3 +#define IG3_RHI_PMAT_DATA_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_LS_FORCE_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_RHI_PMAT_DATA_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_ECC_INVERT_2_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_RHI_PMAT_DATA_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_ECC_INVERT_1_S) +#define IG3_RHI_PMAT_DATA_MEM_CFG_ECC_EN_S 0 +#define IG3_RHI_PMAT_DATA_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_CFG_ECC_EN_S) +#define IG3_RHI_PMAT_DATA_MEM_STATUS 0x42C30104 +#define IG3_RHI_PMAT_DATA_MEM_STATUS_RSVD1_S 30 +#define IG3_RHI_PMAT_DATA_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_PMAT_DATA_MEM_STATUS_RSVD1_S) +#define IG3_RHI_PMAT_DATA_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RHI_PMAT_DATA_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RHI_PMAT_DATA_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RHI_PMAT_DATA_MEM_STATUS_RSVD0_S 4 +#define IG3_RHI_PMAT_DATA_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RHI_PMAT_DATA_MEM_STATUS_RSVD0_S) +#define IG3_RHI_PMAT_DATA_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RHI_PMAT_DATA_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RHI_PMAT_DATA_MEM_STATUS_INIT_DONE_S 2 +#define IG3_RHI_PMAT_DATA_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_STATUS_INIT_DONE_S) +#define IG3_RHI_PMAT_DATA_MEM_STATUS_ECC_FIX_S 1 +#define IG3_RHI_PMAT_DATA_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_STATUS_ECC_FIX_S) +#define IG3_RHI_PMAT_DATA_MEM_STATUS_ECC_ERR_S 0 +#define IG3_RHI_PMAT_DATA_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RHI_PMAT_DATA_MEM_STATUS_ECC_ERR_S) +#define IG3_RHI_RHA_CLIENT_CRED_HOST(_i) 0x42C30000 + ((_i) * 4) /* _i=0...4 */ +#define IG3_RHI_RHA_CLIENT_CRED_HOST_MAX_INDEX_I 4 +#define IG3_RHI_RHA_CLIENT_CRED_HOST_RSVD_S 16 +#define IG3_RHI_RHA_CLIENT_CRED_HOST_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_RHI_RHA_CLIENT_CRED_HOST_RSVD_S) +#define IG3_RHI_RHA_CLIENT_CRED_HOST_DATA_CRED_S 8 +#define IG3_RHI_RHA_CLIENT_CRED_HOST_DATA_CRED_M RDMA_MASK3(32, 0xFF, IG3_RHI_RHA_CLIENT_CRED_HOST_DATA_CRED_S) +#define IG3_RHI_RHA_CLIENT_CRED_HOST_CMD_CRED_S 0 +#define IG3_RHI_RHA_CLIENT_CRED_HOST_CMD_CRED_M RDMA_MASK3(32, 0xFF, IG3_RHI_RHA_CLIENT_CRED_HOST_CMD_CRED_S) +#define IG3_RHI_RHA_CMD_MEM_CFG 0x42C300E0 +#define IG3_RHI_RHA_CMD_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_RHI_RHA_CMD_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RHI_RHA_CMD_MEM_CFG_ECC_INST_NUM_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_RSVD3_S 20 +#define IG3_RHI_RHA_CMD_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RHI_RHA_CMD_MEM_CFG_RSVD3_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_RM_S 16 +#define IG3_RHI_RHA_CMD_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RHI_RHA_CMD_MEM_CFG_RM_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_RSVD2_S 14 +#define IG3_RHI_RHA_CMD_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RHI_RHA_CMD_MEM_CFG_RSVD2_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_RHI_RHA_CMD_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_POWER_GATE_EN_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_RME_S 12 +#define IG3_RHI_RHA_CMD_MEM_CFG_RME_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_RME_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_RSVD1_S 10 +#define IG3_RHI_RHA_CMD_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_RHA_CMD_MEM_CFG_RSVD1_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_ERR_CNT_S 9 +#define IG3_RHI_RHA_CMD_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_ERR_CNT_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_FIX_CNT_S 8 +#define IG3_RHI_RHA_CMD_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_FIX_CNT_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_RSVD0_S 6 +#define IG3_RHI_RHA_CMD_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RHI_RHA_CMD_MEM_CFG_RSVD0_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_MASK_INT_S 5 +#define IG3_RHI_RHA_CMD_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_MASK_INT_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_LS_BYPASS_S 4 +#define IG3_RHI_RHA_CMD_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_LS_BYPASS_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_LS_FORCE_S 3 +#define IG3_RHI_RHA_CMD_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_LS_FORCE_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_RHI_RHA_CMD_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_ECC_INVERT_2_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_RHI_RHA_CMD_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_ECC_INVERT_1_S) +#define IG3_RHI_RHA_CMD_MEM_CFG_ECC_EN_S 0 +#define IG3_RHI_RHA_CMD_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_CFG_ECC_EN_S) +#define IG3_RHI_RHA_CMD_MEM_STATUS 0x42C300DC +#define IG3_RHI_RHA_CMD_MEM_STATUS_RSVD1_S 30 +#define IG3_RHI_RHA_CMD_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_RHA_CMD_MEM_STATUS_RSVD1_S) +#define IG3_RHI_RHA_CMD_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RHI_RHA_CMD_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RHI_RHA_CMD_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RHI_RHA_CMD_MEM_STATUS_RSVD0_S 4 +#define IG3_RHI_RHA_CMD_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RHI_RHA_CMD_MEM_STATUS_RSVD0_S) +#define IG3_RHI_RHA_CMD_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RHI_RHA_CMD_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RHI_RHA_CMD_MEM_STATUS_INIT_DONE_S 2 +#define IG3_RHI_RHA_CMD_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_STATUS_INIT_DONE_S) +#define IG3_RHI_RHA_CMD_MEM_STATUS_ECC_FIX_S 1 +#define IG3_RHI_RHA_CMD_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_STATUS_ECC_FIX_S) +#define IG3_RHI_RHA_CMD_MEM_STATUS_ECC_ERR_S 0 +#define IG3_RHI_RHA_CMD_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RHI_RHA_CMD_MEM_STATUS_ECC_ERR_S) +#define IG3_RHI_RHA_DATA_MEM_CFG 0x42C300E8 +#define IG3_RHI_RHA_DATA_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_RHI_RHA_DATA_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RHI_RHA_DATA_MEM_CFG_ECC_INST_NUM_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_RSVD3_S 20 +#define IG3_RHI_RHA_DATA_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RHI_RHA_DATA_MEM_CFG_RSVD3_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_RM_S 16 +#define IG3_RHI_RHA_DATA_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RHI_RHA_DATA_MEM_CFG_RM_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_RSVD2_S 14 +#define IG3_RHI_RHA_DATA_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RHI_RHA_DATA_MEM_CFG_RSVD2_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_RHI_RHA_DATA_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_POWER_GATE_EN_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_RME_S 12 +#define IG3_RHI_RHA_DATA_MEM_CFG_RME_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_RME_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_RSVD1_S 10 +#define IG3_RHI_RHA_DATA_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_RHA_DATA_MEM_CFG_RSVD1_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_ERR_CNT_S 9 +#define IG3_RHI_RHA_DATA_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_ERR_CNT_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_FIX_CNT_S 8 +#define IG3_RHI_RHA_DATA_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_FIX_CNT_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_RSVD0_S 6 +#define IG3_RHI_RHA_DATA_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RHI_RHA_DATA_MEM_CFG_RSVD0_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_MASK_INT_S 5 +#define IG3_RHI_RHA_DATA_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_MASK_INT_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_LS_BYPASS_S 4 +#define IG3_RHI_RHA_DATA_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_LS_BYPASS_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_LS_FORCE_S 3 +#define IG3_RHI_RHA_DATA_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_LS_FORCE_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_RHI_RHA_DATA_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_ECC_INVERT_2_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_RHI_RHA_DATA_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_ECC_INVERT_1_S) +#define IG3_RHI_RHA_DATA_MEM_CFG_ECC_EN_S 0 +#define IG3_RHI_RHA_DATA_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_CFG_ECC_EN_S) +#define IG3_RHI_RHA_DATA_MEM_STATUS 0x42C300E4 +#define IG3_RHI_RHA_DATA_MEM_STATUS_RSVD1_S 30 +#define IG3_RHI_RHA_DATA_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RHI_RHA_DATA_MEM_STATUS_RSVD1_S) +#define IG3_RHI_RHA_DATA_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RHI_RHA_DATA_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RHI_RHA_DATA_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RHI_RHA_DATA_MEM_STATUS_RSVD0_S 4 +#define IG3_RHI_RHA_DATA_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RHI_RHA_DATA_MEM_STATUS_RSVD0_S) +#define IG3_RHI_RHA_DATA_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RHI_RHA_DATA_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RHI_RHA_DATA_MEM_STATUS_INIT_DONE_S 2 +#define IG3_RHI_RHA_DATA_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_STATUS_INIT_DONE_S) +#define IG3_RHI_RHA_DATA_MEM_STATUS_ECC_FIX_S 1 +#define IG3_RHI_RHA_DATA_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_STATUS_ECC_FIX_S) +#define IG3_RHI_RHA_DATA_MEM_STATUS_ECC_ERR_S 0 +#define IG3_RHI_RHA_DATA_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RHI_RHA_DATA_MEM_STATUS_ECC_ERR_S) +#define IG3_RHI_RHI_AUTOLOAD_DONE 0x42C300D8 +#define IG3_RHI_RHI_AUTOLOAD_DONE_RSVD_S 4 +#define IG3_RHI_RHI_AUTOLOAD_DONE_RSVD_M RDMA_MASK3(32, 0xFFFFFFF, IG3_RHI_RHI_AUTOLOAD_DONE_RSVD_S) +#define IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_MASK_S 3 +#define IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_MASK_M RDMA_BIT2(32, IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_MASK_S) +#define IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_GKT_ARB_S 2 +#define IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_GKT_ARB_M RDMA_BIT2(32, IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_GKT_ARB_S) +#define IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_DEST_ARB_S 1 +#define IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_DEST_ARB_M RDMA_BIT2(32, IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_DEST_ARB_S) +#define IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_CRED_S 0 +#define IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_CRED_M RDMA_BIT2(32, IG3_RHI_RHI_AUTOLOAD_DONE_AUTOLOAD_DONE_CRED_S) +#define IG3_RHI_RHI_ECC_COR_ERR 0x42C30110 +#define IG3_RHI_RHI_ECC_COR_ERR_RSVD_S 12 +#define IG3_RHI_RHI_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RHI_RHI_ECC_COR_ERR_RSVD_S) +#define IG3_RHI_RHI_ECC_COR_ERR_CNT_S 0 +#define IG3_RHI_RHI_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RHI_RHI_ECC_COR_ERR_CNT_S) +#define IG3_RHI_RHI_ECC_UNCOR_ERR 0x42C3010C +#define IG3_RHI_RHI_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_RHI_RHI_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RHI_RHI_ECC_UNCOR_ERR_RSVD_S) +#define IG3_RHI_RHI_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_RHI_RHI_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RHI_RHI_ECC_UNCOR_ERR_CNT_S) +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST 0x42C40008 +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_RSV3_S 24 +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_RSV3_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_AXI_RD_CONST_RSV3_S) +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_RSV2_S 16 +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_RSV2_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_AXI_RD_CONST_RSV2_S) +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARMMUSECSID_S 15 +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARMMUSECSID_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARMMUSECSID_S) +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARTRACE_S 14 +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARTRACE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARTRACE_S) +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARDOMAIN_S 12 +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARDOMAIN_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARDOMAIN_S) +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARSNOOP_S 8 +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARSNOOP_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARSNOOP_S) +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARQOS_S 4 +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARQOS_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARQOS_S) +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARCACHE_S 0 +#define IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARCACHE_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_AXI_RD_CONST_ARCACHE_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0 0x42C40000 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPIDEN_S 31 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPIDEN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPIDEN_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPID_S 26 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPID_M RDMA_MASK3(32, 0x1F, IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPID_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHNIDEN_S 25 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHNIDEN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHNIDEN_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHNID_S 14 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHNID_M RDMA_MASK3(32, 0x7FF, IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSTASHNID_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWDOMAIN_S 12 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWDOMAIN_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWDOMAIN_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSNOOP_S 8 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSNOOP_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWSNOOP_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWQOS_S 4 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWQOS_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWQOS_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWCACHE_S 0 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWCACHE_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_AXI_WR_CONST0_AWCACHE_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1 0x42C40004 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV3_S 24 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV3_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV3_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV2_S 16 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV2_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV2_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV1_S 8 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV1_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV1_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV0_S 4 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV0_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_RSV0_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_WUSER_S 3 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_WUSER_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_WUSER_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_WTRACE_S 2 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_WTRACE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_WTRACE_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_AWMMUSECSID_S 1 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_AWMMUSECSID_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_AWMMUSECSID_S) +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_AWTRACE_S 0 +#define IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_AWTRACE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_AXI_WR_CONST1_AWTRACE_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_BUS_INDEX 0x42C40110 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL 0x42C40100 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_FREEZE_ON_CNT_VAL 0x42C40120 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_OBS_BUS 0x42C40140 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT0 0x42C40160 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT1_0 0x42C40168 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT1_1 0x42C4016C +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL 0x42C40158 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_CTRL 0x42C40138 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_GAP 0x42C40128 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_TRNS 0x42C40130 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS 0x42C40108 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_READY_S 5 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_READY_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_VALID_S 4 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_VALID_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_TRANS_CNT 0x42C40118 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_TRIG_MASK 0x42C40148 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_TRIG_VALUE 0x42C40150 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_BUS_INDEX 0x42C40190 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL 0x42C40180 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_FREEZE_ON_CNT_VAL 0x42C401A0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_OBS_BUS 0x42C401C0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT0 0x42C401E0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT1_0 0x42C401E8 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT1_1 0x42C401EC +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL 0x42C401D8 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_CTRL 0x42C401B8 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_GAP 0x42C401A8 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_TRNS 0x42C401B0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS 0x42C40188 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_READY_S 5 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_READY_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_VALID_S 4 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_VALID_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_TRANS_CNT 0x42C40198 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_TRIG_MASK 0x42C401C8 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_TRIG_VALUE 0x42C401D0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_BUS_INDEX 0x42C40210 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL 0x42C40200 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_FREEZE_ON_CNT_VAL 0x42C40220 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_OBS_BUS 0x42C40240 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT0 0x42C40260 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT1_0 0x42C40268 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT1_1 0x42C4026C +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL 0x42C40258 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_CTRL 0x42C40238 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_GAP 0x42C40228 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_TRNS 0x42C40230 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS 0x42C40208 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_READY_S 5 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_READY_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_VALID_S 4 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_VALID_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_TRANS_CNT 0x42C40218 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_TRIG_MASK 0x42C40248 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_TRIG_VALUE 0x42C40250 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_BUS_INDEX 0x42C40290 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL 0x42C40280 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_FREEZE_ON_CNT_VAL 0x42C402A0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_OBS_BUS 0x42C402C0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT0 0x42C402E0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT1_0 0x42C402E8 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT1_1 0x42C402EC +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL 0x42C402D8 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_CTRL 0x42C402B8 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_GAP 0x42C402A8 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_TRNS 0x42C402B0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS 0x42C40288 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_READY_S 5 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_READY_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_VALID_S 4 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_VALID_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_TRANS_CNT 0x42C40298 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_TRIG_MASK 0x42C402C8 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_TRIG_VALUE 0x42C402D0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_BUS_INDEX 0x42C40310 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL 0x42C40300 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_FREEZE_ON_CNT_VAL 0x42C40320 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_OBS_BUS 0x42C40340 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT0 0x42C40360 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT1_0 0x42C40368 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT1_1 0x42C4036C +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL 0x42C40358 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_CTRL 0x42C40338 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_GAP 0x42C40328 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_TRNS 0x42C40330 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS 0x42C40308 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_READY_S 5 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_READY_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_VALID_S 4 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_VALID_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_TRANS_CNT 0x42C40318 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_TRIG_MASK 0x42C40348 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_TRIG_VALUE 0x42C40350 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_BOB4_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_BOB4_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_COUNT 0x42C400B8 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_CMD 0x42C400CC +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_DATA_H 0x42C400D8 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_DATA_L 0x42C400D4 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_PTR 0x42C400D0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_CMD 0x42C400BC +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_DATA_H 0x42C400C8 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_DATA_L 0x42C400C4 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_PTR 0x42C400C0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI0_GLPE_RMI_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL 0x42C40080 +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD1_S 25 +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD2_S 17 +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD2_S) +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD3_S 9 +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD3_S) +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_BYPASS_S 8 +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_CONTROL_BYPASS_S) +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD4_S 1 +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_RMI0_GLPE_RMI_DTM_CONTROL_RSVD4_S) +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_CONTROL_LOCAL_EN_S) +#define IG3_RMI0_GLPE_RMI_DTM_ECC_COR_ERR 0x42C400E8 +#define IG3_RMI0_GLPE_RMI_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_RMI0_GLPE_RMI_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI0_GLPE_RMI_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_RMI0_GLPE_RMI_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RMI0_GLPE_RMI_DTM_ECC_COR_ERR_CNT_S) +#define IG3_RMI0_GLPE_RMI_DTM_ECC_UNCOR_ERR 0x42C400E4 +#define IG3_RMI0_GLPE_RMI_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_RMI0_GLPE_RMI_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI0_GLPE_RMI_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_RMI0_GLPE_RMI_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RMI0_GLPE_RMI_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG 0x42C4008C +#define IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_RMI0_GLPE_RMI_DTM_LOG_CFG 0x42C40090 +#define IG3_RMI0_GLPE_RMI_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_RMI0_GLPE_RMI_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_RMI0_GLPE_RMI_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_RMI0_GLPE_RMI_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_RMI0_GLPE_RMI_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_RMI0_GLPE_RMI_DTM_LOG_CFG_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_LOG_CFG_MODE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_DTM_LOG_CFG_MODE_S) +#define IG3_RMI0_GLPE_RMI_DTM_LOG_MASK 0x42C40098 +#define IG3_RMI0_GLPE_RMI_DTM_LOG_MASK_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_LOG_MASK_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_LOG_PATTERN 0x42C40094 +#define IG3_RMI0_GLPE_RMI_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_LOG_PATTERN_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG 0x42C40084 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_RSVD2_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_RSVD3_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_STS 0x42C40088 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_RSVD2_S) +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TIMESTAMP 0x42C400B0 +#define IG3_RMI0_GLPE_RMI_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_TIMESTAMP_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TIMESTAMP_ROLLOVER 0x42C400B4 +#define IG3_RMI0_GLPE_RMI_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG 0x42C400DC +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS 0x42C400E0 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI0_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG 0x42C4009C +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_RSVD1_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_RSVD2_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_MODE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_RMI0_GLPE_RMI_DTM_TRIG_CFG_MODE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_COUNT 0x42C400A8 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_TRIG_COUNT_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_MASK 0x42C400A4 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_TRIG_MASK_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_PATTERN 0x42C400A0 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_TIMESTAMP 0x42C400AC +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_RMI0_GLPE_RMI_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI0_GLPE_RMI_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_RMI0_RHI_ECC_COR_ERR 0x42C40030 +#define IG3_RMI0_RHI_ECC_COR_ERR_RSVD_S 12 +#define IG3_RMI0_RHI_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI0_RHI_ECC_COR_ERR_RSVD_S) +#define IG3_RMI0_RHI_ECC_COR_ERR_CNT_S 0 +#define IG3_RMI0_RHI_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RMI0_RHI_ECC_COR_ERR_CNT_S) +#define IG3_RMI0_RHI_ECC_UNCOR_ERR 0x42C4002C +#define IG3_RMI0_RHI_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_RMI0_RHI_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI0_RHI_ECC_UNCOR_ERR_RSVD_S) +#define IG3_RMI0_RHI_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_RMI0_RHI_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RMI0_RHI_ECC_UNCOR_ERR_CNT_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG 0x42C40020 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_INST_NUM_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD3_S 20 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD3_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RM_S 16 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI0_RMI_CMD_CREDITS_CFG_RM_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD2_S 14 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD2_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_POWER_GATE_EN_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RME_S 12 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RME_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_RME_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD1_S 10 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD1_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ERR_CNT_S 9 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_ERR_CNT_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_FIX_CNT_S 8 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_FIX_CNT_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD0_S 6 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_CMD_CREDITS_CFG_RSVD0_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_MASK_INT_S 5 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_MASK_INT_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_LS_BYPASS_S 4 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_LS_BYPASS_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_LS_FORCE_S 3 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_LS_FORCE_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_INVERT_2_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_INVERT_1_S) +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_EN_S 0 +#define IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_CFG_ECC_EN_S) +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS 0x42C4001C +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_RSVD1_S 30 +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_CMD_CREDITS_STATUS_RSVD1_S) +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI0_RMI_CMD_CREDITS_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_RSVD0_S 4 +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI0_RMI_CMD_CREDITS_STATUS_RSVD0_S) +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_INIT_DONE_S 2 +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_STATUS_INIT_DONE_S) +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_ECC_FIX_S 1 +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_STATUS_ECC_FIX_S) +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_ECC_ERR_S 0 +#define IG3_RMI0_RMI_CMD_CREDITS_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI0_RMI_CMD_CREDITS_STATUS_ECC_ERR_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG 0x42C40028 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_INST_NUM_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD3_S 20 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD3_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RM_S 16 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI0_RMI_DATA_CREDITS_CFG_RM_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD2_S 14 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD2_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_POWER_GATE_EN_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RME_S 12 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RME_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_RME_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD1_S 10 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD1_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ERR_CNT_S 9 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_ERR_CNT_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_FIX_CNT_S 8 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_FIX_CNT_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD0_S 6 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_DATA_CREDITS_CFG_RSVD0_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_MASK_INT_S 5 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_MASK_INT_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_LS_BYPASS_S 4 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_LS_BYPASS_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_LS_FORCE_S 3 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_LS_FORCE_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_INVERT_2_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_INVERT_1_S) +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_EN_S 0 +#define IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_CFG_ECC_EN_S) +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS 0x42C40024 +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_RSVD1_S 30 +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_DATA_CREDITS_STATUS_RSVD1_S) +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI0_RMI_DATA_CREDITS_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_RSVD0_S 4 +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI0_RMI_DATA_CREDITS_STATUS_RSVD0_S) +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_INIT_DONE_S 2 +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_STATUS_INIT_DONE_S) +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_ECC_FIX_S 1 +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_STATUS_ECC_FIX_S) +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_ECC_ERR_S 0 +#define IG3_RMI0_RMI_DATA_CREDITS_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI0_RMI_DATA_CREDITS_STATUS_ECC_ERR_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG 0x42C40010 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_INST_NUM_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD3_S 20 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD3_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RM_S 16 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RM_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD2_S 14 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD2_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_POWER_GATE_EN_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RME_S 12 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RME_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RME_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD1_S 10 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD1_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ERR_CNT_S 9 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ERR_CNT_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_FIX_CNT_S 8 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_FIX_CNT_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD0_S 6 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_RSVD0_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_MASK_INT_S 5 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_MASK_INT_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_LS_BYPASS_S 4 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_LS_BYPASS_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_LS_FORCE_S 3 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_LS_FORCE_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_2_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_1_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_EN_S 0 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_CFG_ECC_EN_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS 0x42C4000C +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_RSVD1_S 30 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_RSVD1_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_RSVD0_S 4 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_RSVD0_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_INIT_DONE_S 2 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_INIT_DONE_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_ECC_FIX_S 1 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_ECC_FIX_S) +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_ECC_ERR_S 0 +#define IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_LEFT_DATA_STATUS_ECC_ERR_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG 0x42C40018 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_INST_NUM_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD3_S 20 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD3_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RM_S 16 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RM_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD2_S 14 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD2_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_POWER_GATE_EN_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RME_S 12 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RME_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RME_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD1_S 10 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD1_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ERR_CNT_S 9 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ERR_CNT_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_FIX_CNT_S 8 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_FIX_CNT_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD0_S 6 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_RSVD0_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_MASK_INT_S 5 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_MASK_INT_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_LS_BYPASS_S 4 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_LS_BYPASS_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_LS_FORCE_S 3 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_LS_FORCE_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_2_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_1_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_EN_S 0 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_CFG_ECC_EN_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS 0x42C40014 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_RSVD1_S 30 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_RSVD1_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_RSVD0_S 4 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_RSVD0_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_INIT_DONE_S 2 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_INIT_DONE_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_ECC_FIX_S 1 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_ECC_FIX_S) +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERR_S 0 +#define IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI0_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERR_S) +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST 0x42C50008 +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_RSV3_S 24 +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_RSV3_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_AXI_RD_CONST_RSV3_S) +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_RSV2_S 16 +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_RSV2_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_AXI_RD_CONST_RSV2_S) +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARMMUSECSID_S 15 +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARMMUSECSID_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARMMUSECSID_S) +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARTRACE_S 14 +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARTRACE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARTRACE_S) +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARDOMAIN_S 12 +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARDOMAIN_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARDOMAIN_S) +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARSNOOP_S 8 +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARSNOOP_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARSNOOP_S) +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARQOS_S 4 +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARQOS_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARQOS_S) +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARCACHE_S 0 +#define IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARCACHE_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_AXI_RD_CONST_ARCACHE_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0 0x42C50000 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPIDEN_S 31 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPIDEN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPIDEN_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPID_S 26 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPID_M RDMA_MASK3(32, 0x1F, IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHLPID_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHNIDEN_S 25 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHNIDEN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHNIDEN_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHNID_S 14 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHNID_M RDMA_MASK3(32, 0x7FF, IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSTASHNID_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWDOMAIN_S 12 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWDOMAIN_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWDOMAIN_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSNOOP_S 8 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSNOOP_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWSNOOP_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWQOS_S 4 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWQOS_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWQOS_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWCACHE_S 0 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWCACHE_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_AXI_WR_CONST0_AWCACHE_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1 0x42C50004 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV3_S 24 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV3_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV3_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV2_S 16 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV2_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV2_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV1_S 8 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV1_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV1_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV0_S 4 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV0_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_RSV0_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_WUSER_S 3 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_WUSER_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_WUSER_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_WTRACE_S 2 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_WTRACE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_WTRACE_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_AWMMUSECSID_S 1 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_AWMMUSECSID_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_AWMMUSECSID_S) +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_AWTRACE_S 0 +#define IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_AWTRACE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_AXI_WR_CONST1_AWTRACE_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_BUS_INDEX 0x42C50110 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL 0x42C50100 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_FREEZE_ON_CNT_VAL 0x42C50120 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_OBS_BUS 0x42C50140 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT0 0x42C50160 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT1_0 0x42C50168 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT1_1 0x42C5016C +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL 0x42C50158 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB0_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_CTRL 0x42C50138 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_GAP 0x42C50128 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_TRNS 0x42C50130 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS 0x42C50108 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_READY_S 5 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_READY_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_VALID_S 4 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_VALID_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB0_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_TRANS_CNT 0x42C50118 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_TRIG_MASK 0x42C50148 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_TRIG_VALUE 0x42C50150 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB0_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_BUS_INDEX 0x42C50190 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL 0x42C50180 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_FREEZE_ON_CNT_VAL 0x42C501A0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_OBS_BUS 0x42C501C0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT0 0x42C501E0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT1_0 0x42C501E8 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT1_1 0x42C501EC +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL 0x42C501D8 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB1_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_CTRL 0x42C501B8 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_GAP 0x42C501A8 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_TRNS 0x42C501B0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS 0x42C50188 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_READY_S 5 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_READY_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_VALID_S 4 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_VALID_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB1_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_TRANS_CNT 0x42C50198 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_TRIG_MASK 0x42C501C8 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_TRIG_VALUE 0x42C501D0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB1_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_BUS_INDEX 0x42C50210 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL 0x42C50200 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_FREEZE_ON_CNT_VAL 0x42C50220 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_OBS_BUS 0x42C50240 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT0 0x42C50260 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT1_0 0x42C50268 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT1_1 0x42C5026C +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL 0x42C50258 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB2_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_CTRL 0x42C50238 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_GAP 0x42C50228 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_TRNS 0x42C50230 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS 0x42C50208 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_READY_S 5 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_READY_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_VALID_S 4 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_VALID_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB2_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_TRANS_CNT 0x42C50218 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_TRIG_MASK 0x42C50248 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_TRIG_VALUE 0x42C50250 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB2_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_BUS_INDEX 0x42C50290 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL 0x42C50280 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_FREEZE_ON_CNT_VAL 0x42C502A0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_OBS_BUS 0x42C502C0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT0 0x42C502E0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT1_0 0x42C502E8 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT1_1 0x42C502EC +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL 0x42C502D8 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB3_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_CTRL 0x42C502B8 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_GAP 0x42C502A8 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_TRNS 0x42C502B0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS 0x42C50288 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_READY_S 5 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_READY_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_VALID_S 4 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_VALID_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB3_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_TRANS_CNT 0x42C50298 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_TRIG_MASK 0x42C502C8 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_TRIG_VALUE 0x42C502D0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB3_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_BUS_INDEX 0x42C50310 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_BUS_INDEX_BUS_INDEX_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_BUS_INDEX_BUS_INDEX_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_BUS_INDEX_BUS_INDEX_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL 0x42C50300 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_RESERVED_31_10_S 10 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_RESERVED_31_10_M RDMA_MASK3(32, 0x3FFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_RESERVED_31_10_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_TRIG_OP_S 8 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_TRIG_OP_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_TRIG_OP_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_VLD_RDY_FRZ_EN_S 7 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_VLD_RDY_FRZ_EN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_VLD_RDY_FRZ_EN_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_EN_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_EN_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_EN_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_COUNT_ONLY_TRIG_S 5 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_COUNT_ONLY_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_COUNT_ONLY_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_READ_INPUT_BUS_S 4 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_READ_INPUT_BUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_READ_INPUT_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_EN_FRZ_ON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_RESET_S 1 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_RESET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_RESET_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_SET_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_SET_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_CTRL_FREEZE_SET_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_FREEZE_ON_CNT_VAL 0x42C50320 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_FREEZE_ON_CNT_VAL_FREEZE_ON_CNT_VAL_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_OBS_BUS 0x42C50340 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_OBS_BUS_OBS_BUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_OBS_BUS_OBS_BUS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_OBS_BUS_OBS_BUS_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT0 0x42C50360 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT0_CNT0_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT0_CNT0_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT0_CNT0_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT1_0 0x42C50368 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT1_0_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT1_0_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT1_0_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT1_1 0x42C5036C +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT1_1_CNT1_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT1_1_CNT1_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CNT1_1_CNT1_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL 0x42C50358 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_RESERVED_31_16_S 16 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_RESERVED_31_16_M RDMA_MASK3(32, 0xFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_RESERVED_31_16_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_WIN_S 8 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_WIN_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_WIN_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT1_CFG_S 4 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT1_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT1_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT0_CFG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT0_CFG_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_BOB4_BOB_PERF_CTRL_PERF_CNT0_CFG_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_CTRL 0x42C50338 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_CTRL_RESERVED_31_1_S 1 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_CTRL_RESERVED_31_1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_CTRL_RESERVED_31_1_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_CTRL_RC_TRIG_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_CTRL_RC_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_CTRL_RC_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_GAP 0x42C50328 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_GAP_RC_GAP_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_GAP_RC_GAP_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_GAP_RC_GAP_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_TRNS 0x42C50330 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_TRNS_RC_TRNS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_TRNS_RC_TRNS_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_RC_TRNS_RC_TRNS_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS 0x42C50308 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_RESERVED_31_8_S 8 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_RESERVED_31_8_M RDMA_MASK3(32, 0xFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_RESERVED_31_8_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_IFRZ_S 7 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_IFRZ_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_IFRZ_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_I_FREEZE_S 6 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_I_FREEZE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_I_FREEZE_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_READY_S 5 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_READY_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_READY_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_VALID_S 4 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_VALID_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_VALID_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_CNT_S 3 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_TRIG_S 2 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_UPON_TRIG_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S 1 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_SET_BY_SW_FLAG_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_STATUS_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_STATUS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_BOB4_BOB_STATUS_FREEZE_STATUS_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_TRANS_CNT 0x42C50318 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_TRANS_CNT_TRANS_CNT_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_TRANS_CNT_TRANS_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_TRANS_CNT_TRANS_CNT_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_TRIG_MASK 0x42C50348 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_TRIG_MASK_TRIG_MASK_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_TRIG_MASK_TRIG_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_TRIG_MASK_TRIG_MASK_S) +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_TRIG_VALUE 0x42C50350 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_TRIG_VALUE_TRIG_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_BOB4_BOB_TRIG_VALUE_TRIG_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_BOB4_BOB_TRIG_VALUE_TRIG_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_COUNT 0x42C500B8 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_CMD 0x42C500CC +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_DATA_H 0x42C500D8 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_DATA_L 0x42C500D4 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_PTR 0x42C500D0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_CMD 0x42C500BC +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_DATA_H 0x42C500C8 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_DATA_L 0x42C500C4 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_PTR 0x42C500C0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI1_GLPE_RMI_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL 0x42C50080 +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD1_S 25 +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD2_S 17 +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD2_S) +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD3_S 9 +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD3_S) +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_BYPASS_S 8 +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_CONTROL_BYPASS_S) +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD4_S 1 +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_RMI1_GLPE_RMI_DTM_CONTROL_RSVD4_S) +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_CONTROL_LOCAL_EN_S) +#define IG3_RMI1_GLPE_RMI_DTM_ECC_COR_ERR 0x42C500E8 +#define IG3_RMI1_GLPE_RMI_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_RMI1_GLPE_RMI_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI1_GLPE_RMI_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_RMI1_GLPE_RMI_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RMI1_GLPE_RMI_DTM_ECC_COR_ERR_CNT_S) +#define IG3_RMI1_GLPE_RMI_DTM_ECC_UNCOR_ERR 0x42C500E4 +#define IG3_RMI1_GLPE_RMI_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_RMI1_GLPE_RMI_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI1_GLPE_RMI_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_RMI1_GLPE_RMI_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RMI1_GLPE_RMI_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG 0x42C5008C +#define IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_RMI1_GLPE_RMI_DTM_LOG_CFG 0x42C50090 +#define IG3_RMI1_GLPE_RMI_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_RMI1_GLPE_RMI_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_RMI1_GLPE_RMI_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_RMI1_GLPE_RMI_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_RMI1_GLPE_RMI_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_RMI1_GLPE_RMI_DTM_LOG_CFG_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_LOG_CFG_MODE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_DTM_LOG_CFG_MODE_S) +#define IG3_RMI1_GLPE_RMI_DTM_LOG_MASK 0x42C50098 +#define IG3_RMI1_GLPE_RMI_DTM_LOG_MASK_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_LOG_MASK_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_LOG_PATTERN 0x42C50094 +#define IG3_RMI1_GLPE_RMI_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_LOG_PATTERN_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG 0x42C50084 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_RSVD2_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_RSVD3_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_STS 0x42C50088 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_RSVD2_S) +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TIMESTAMP 0x42C500B0 +#define IG3_RMI1_GLPE_RMI_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_TIMESTAMP_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TIMESTAMP_ROLLOVER 0x42C500B4 +#define IG3_RMI1_GLPE_RMI_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG 0x42C500DC +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS 0x42C500E0 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI1_GLPE_RMI_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG 0x42C5009C +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_RSVD1_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_RSVD2_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_MODE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_RMI1_GLPE_RMI_DTM_TRIG_CFG_MODE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_COUNT 0x42C500A8 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_TRIG_COUNT_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_MASK 0x42C500A4 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_TRIG_MASK_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_PATTERN 0x42C500A0 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_TIMESTAMP 0x42C500AC +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_RMI1_GLPE_RMI_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_RMI1_GLPE_RMI_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_RMI1_RHI_ECC_COR_ERR 0x42C50030 +#define IG3_RMI1_RHI_ECC_COR_ERR_RSVD_S 12 +#define IG3_RMI1_RHI_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI1_RHI_ECC_COR_ERR_RSVD_S) +#define IG3_RMI1_RHI_ECC_COR_ERR_CNT_S 0 +#define IG3_RMI1_RHI_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RMI1_RHI_ECC_COR_ERR_CNT_S) +#define IG3_RMI1_RHI_ECC_UNCOR_ERR 0x42C5002C +#define IG3_RMI1_RHI_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_RMI1_RHI_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_RMI1_RHI_ECC_UNCOR_ERR_RSVD_S) +#define IG3_RMI1_RHI_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_RMI1_RHI_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_RMI1_RHI_ECC_UNCOR_ERR_CNT_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG 0x42C50020 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_INST_NUM_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD3_S 20 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD3_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RM_S 16 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI1_RMI_CMD_CREDITS_CFG_RM_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD2_S 14 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD2_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_POWER_GATE_EN_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RME_S 12 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RME_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_RME_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD1_S 10 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD1_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ERR_CNT_S 9 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_ERR_CNT_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_FIX_CNT_S 8 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_FIX_CNT_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD0_S 6 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_CMD_CREDITS_CFG_RSVD0_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_MASK_INT_S 5 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_MASK_INT_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_LS_BYPASS_S 4 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_LS_BYPASS_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_LS_FORCE_S 3 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_LS_FORCE_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_INVERT_2_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_INVERT_1_S) +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_EN_S 0 +#define IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_CFG_ECC_EN_S) +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS 0x42C5001C +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_RSVD1_S 30 +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_CMD_CREDITS_STATUS_RSVD1_S) +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI1_RMI_CMD_CREDITS_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_RSVD0_S 4 +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI1_RMI_CMD_CREDITS_STATUS_RSVD0_S) +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_INIT_DONE_S 2 +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_STATUS_INIT_DONE_S) +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_ECC_FIX_S 1 +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_STATUS_ECC_FIX_S) +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_ECC_ERR_S 0 +#define IG3_RMI1_RMI_CMD_CREDITS_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI1_RMI_CMD_CREDITS_STATUS_ECC_ERR_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG 0x42C50028 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_INST_NUM_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD3_S 20 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD3_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RM_S 16 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI1_RMI_DATA_CREDITS_CFG_RM_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD2_S 14 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD2_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_POWER_GATE_EN_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RME_S 12 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RME_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_RME_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD1_S 10 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD1_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ERR_CNT_S 9 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_ERR_CNT_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_FIX_CNT_S 8 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_FIX_CNT_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD0_S 6 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_DATA_CREDITS_CFG_RSVD0_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_MASK_INT_S 5 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_MASK_INT_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_LS_BYPASS_S 4 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_LS_BYPASS_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_LS_FORCE_S 3 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_LS_FORCE_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_INVERT_2_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_INVERT_1_S) +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_EN_S 0 +#define IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_CFG_ECC_EN_S) +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS 0x42C50024 +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_RSVD1_S 30 +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_DATA_CREDITS_STATUS_RSVD1_S) +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI1_RMI_DATA_CREDITS_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_RSVD0_S 4 +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI1_RMI_DATA_CREDITS_STATUS_RSVD0_S) +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_INIT_DONE_S 2 +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_STATUS_INIT_DONE_S) +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_ECC_FIX_S 1 +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_STATUS_ECC_FIX_S) +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_ECC_ERR_S 0 +#define IG3_RMI1_RMI_DATA_CREDITS_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI1_RMI_DATA_CREDITS_STATUS_ECC_ERR_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG 0x42C50010 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_INST_NUM_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD3_S 20 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD3_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RM_S 16 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RM_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD2_S 14 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD2_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_POWER_GATE_EN_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RME_S 12 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RME_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RME_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD1_S 10 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD1_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ERR_CNT_S 9 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ERR_CNT_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_FIX_CNT_S 8 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_FIX_CNT_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD0_S 6 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_RSVD0_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_MASK_INT_S 5 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_MASK_INT_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_LS_BYPASS_S 4 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_LS_BYPASS_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_LS_FORCE_S 3 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_LS_FORCE_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_2_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_INVERT_1_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_EN_S 0 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_CFG_ECC_EN_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS 0x42C5000C +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_RSVD1_S 30 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_RSVD1_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_RSVD0_S 4 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_RSVD0_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_INIT_DONE_S 2 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_INIT_DONE_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_ECC_FIX_S 1 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_ECC_FIX_S) +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_ECC_ERR_S 0 +#define IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_LEFT_DATA_STATUS_ECC_ERR_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG 0x42C50018 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_INST_NUM_S 25 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_INST_NUM_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD3_S 20 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD3_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RM_S 16 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RM_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD2_S 14 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD2_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_POWER_GATE_EN_S 13 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_POWER_GATE_EN_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RME_S 12 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RME_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RME_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD1_S 10 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD1_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ERR_CNT_S 9 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ERR_CNT_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_FIX_CNT_S 8 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_FIX_CNT_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD0_S 6 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_RSVD0_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_MASK_INT_S 5 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_MASK_INT_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_MASK_INT_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_LS_BYPASS_S 4 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_LS_BYPASS_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_LS_FORCE_S 3 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_LS_FORCE_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_2_S 2 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_2_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_1_S 1 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_INVERT_1_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_EN_S 0 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_EN_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_CFG_ECC_EN_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS 0x42C50014 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_RSVD1_S 30 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_RSVD1_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_RSVD0_S 4 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_RSVD0_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_INIT_DONE_S 2 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_INIT_DONE_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_ECC_FIX_S 1 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_ECC_FIX_S) +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERR_S 0 +#define IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_RMI1_RMI_RESP_RIGHT_DATA_STATUS_ECC_ERR_S) +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG(_i) 0x43002000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG_MAX_INDEX_I 1031 +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG_RSVD2_S 31 +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG_RSVD2_M RDMA_BIT2(32, IG3_PRX0_GLPE_CC_DCQCN1_CFG_RSVD2_S) +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG_DCQCN_F_S 28 +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG_DCQCN_F_M RDMA_MASK3(32, 0x7, IG3_PRX0_GLPE_CC_DCQCN1_CFG_DCQCN_F_S) +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG_RSVD1_S 25 +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_PRX0_GLPE_CC_DCQCN1_CFG_RSVD1_S) +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG_DCQCN_B_S 0 +#define IG3_PRX0_GLPE_CC_DCQCN1_CFG_DCQCN_B_M RDMA_MASK3(32, 0x1FFFFFF, IG3_PRX0_GLPE_CC_DCQCN1_CFG_DCQCN_B_S) +#define IG3_PRX0_GLPE_CC_DCQCN2_CFG(_i) 0x43004000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX0_GLPE_CC_DCQCN2_CFG_MAX_INDEX_I 1031 +#define IG3_PRX0_GLPE_CC_DCQCN2_CFG_RSVD_S 16 +#define IG3_PRX0_GLPE_CC_DCQCN2_CFG_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PRX0_GLPE_CC_DCQCN2_CFG_RSVD_S) +#define IG3_PRX0_GLPE_CC_DCQCN2_CFG_DCQCN_T_S 0 +#define IG3_PRX0_GLPE_CC_DCQCN2_CFG_DCQCN_T_M RDMA_MASK3(32, 0xFFFF, IG3_PRX0_GLPE_CC_DCQCN2_CFG_DCQCN_T_S) +#define IG3_PRX0_GLPE_CC_TIMELY_CFG(_i) 0x43000000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX0_GLPE_CC_TIMELY_CFG_MAX_INDEX_I 1031 +#define IG3_PRX0_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S 16 +#define IG3_PRX0_GLPE_CC_TIMELY_CFG_RAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX0_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S) +#define IG3_PRX0_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S 0 +#define IG3_PRX0_GLPE_CC_TIMELY_CFG_HAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX0_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S) +#define IG3_PRX0_GLPE_PRX_CONFIG 0x43005020 +#define IG3_PRX0_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S 24 +#define IG3_PRX0_GLPE_PRX_CONFIG_REORDER_CNT_MAX_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S) +#define IG3_PRX0_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S 16 +#define IG3_PRX0_GLPE_PRX_CONFIG_REORDER_CNT_MIN_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S) +#define IG3_PRX0_GLPE_PRX_CONFIG_RSVD1_S 12 +#define IG3_PRX0_GLPE_PRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PRX0_GLPE_PRX_CONFIG_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S 8 +#define IG3_PRX0_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_M RDMA_MASK3(32, 0xF, IG3_PRX0_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S) +#define IG3_PRX0_GLPE_PRX_CONFIG_RSVD0_S 5 +#define IG3_PRX0_GLPE_PRX_CONFIG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PRX0_GLPE_PRX_CONFIG_RSVD0_S) +#define IG3_PRX0_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S 4 +#define IG3_PRX0_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S) +#define IG3_PRX0_GLPE_PRX_CONFIG_ONE_HP_TILE_S 3 +#define IG3_PRX0_GLPE_PRX_CONFIG_ONE_HP_TILE_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_CONFIG_ONE_HP_TILE_S) +#define IG3_PRX0_GLPE_PRX_CONFIG_DIS_RREC_S 2 +#define IG3_PRX0_GLPE_PRX_CONFIG_DIS_RREC_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_CONFIG_DIS_RREC_S) +#define IG3_PRX0_GLPE_PRX_CONFIG_DIS_QR_STALL_S 1 +#define IG3_PRX0_GLPE_PRX_CONFIG_DIS_QR_STALL_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_CONFIG_DIS_QR_STALL_S) +#define IG3_PRX0_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S 0 +#define IG3_PRX0_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_COUNT 0x430050B8 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_CMD 0x430050CC +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_DATA_H 0x430050D8 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_DATA_L 0x430050D4 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_PTR 0x430050D0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_CMD 0x430050BC +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_DATA_H 0x430050C8 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_DATA_L 0x430050C4 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_PTR 0x430050C0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX0_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL 0x43005080 +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD2_S) +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD3_S) +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_CONTROL_BYPASS_S) +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PRX0_GLPE_PRX_DTM_CONTROL_RSVD4_S) +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PRX0_GLPE_PRX_DTM_ECC_COR_ERR 0x430050E8 +#define IG3_PRX0_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PRX0_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX0_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PRX0_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX0_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PRX0_GLPE_PRX_DTM_ECC_UNCOR_ERR 0x430050E4 +#define IG3_PRX0_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PRX0_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX0_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PRX0_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX0_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG 0x4300508C +#define IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PRX0_GLPE_PRX_DTM_LOG_CFG 0x43005090 +#define IG3_PRX0_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PRX0_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PRX0_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PRX0_GLPE_PRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PRX0_GLPE_PRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PRX0_GLPE_PRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PRX0_GLPE_PRX_DTM_LOG_CFG_MODE_S) +#define IG3_PRX0_GLPE_PRX_DTM_LOG_MASK 0x43005098 +#define IG3_PRX0_GLPE_PRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_LOG_MASK_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_LOG_PATTERN 0x43005094 +#define IG3_PRX0_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG 0x43005084 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_STS 0x43005088 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TIMESTAMP 0x430050B0 +#define IG3_PRX0_GLPE_PRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER 0x430050B4 +#define IG3_PRX0_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG 0x430050DC +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS 0x430050E0 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG 0x4300509C +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PRX0_GLPE_PRX_DTM_TRIG_CFG_MODE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_COUNT 0x430050A8 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_MASK 0x430050A4 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_PATTERN 0x430050A0 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_TIMESTAMP 0x430050AC +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PRX0_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX0_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_CTL 0x43005024 +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S 12 +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S) +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S 0 +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S) +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA 0x43005028 +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S 31 +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S) +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S 30 +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_M RDMA_BIT2(32, IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S) +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S 24 +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S) +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S 20 +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S) +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S 0 +#define IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX0_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S) +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL 0x43008018 +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S 21 +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_M RDMA_MASK3(32, 0x7FF, IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S) +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S 16 +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S) +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S 13 +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S 8 +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S) +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S 5 +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S) +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S 0 +#define IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX0_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S) +#define IG3_WRX0_GLPE_WRX_CONFIG 0x43008000 +#define IG3_WRX0_GLPE_WRX_CONFIG_RSVD_S 8 +#define IG3_WRX0_GLPE_WRX_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WRX0_GLPE_WRX_CONFIG_RSVD_S) +#define IG3_WRX0_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S 5 +#define IG3_WRX0_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_M RDMA_MASK3(32, 0x7, IG3_WRX0_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S) +#define IG3_WRX0_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S 4 +#define IG3_WRX0_GLPE_WRX_CONFIG_DIS_WQE_CACHE_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S) +#define IG3_WRX0_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S 3 +#define IG3_WRX0_GLPE_WRX_CONFIG_DROP_OOO_IMMED_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S) +#define IG3_WRX0_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S 2 +#define IG3_WRX0_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S) +#define IG3_WRX0_GLPE_WRX_CONFIG_DIS_Q1_AE_S 1 +#define IG3_WRX0_GLPE_WRX_CONFIG_DIS_Q1_AE_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_CONFIG_DIS_Q1_AE_S) +#define IG3_WRX0_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S 0 +#define IG3_WRX0_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S) +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS 0x43008014 +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_RSVD2_S 11 +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_RSVD2_M RDMA_MASK3(32, 0x1FFFFF, IG3_WRX0_GLPE_WRX_DOMAIN_IDS_RSVD2_S) +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S 8 +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX0_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S) +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_RSVD1_S 7 +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_RSVD1_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DOMAIN_IDS_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S 4 +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX0_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S) +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_RSVD0_S 3 +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_RSVD0_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DOMAIN_IDS_RSVD0_S) +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S 0 +#define IG3_WRX0_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX0_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_COUNT 0x430080B8 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_CMD 0x430080CC +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_DATA_H 0x430080D8 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_DATA_L 0x430080D4 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_PTR 0x430080D0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_CMD 0x430080BC +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_DATA_H 0x430080C8 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_DATA_L 0x430080C4 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_PTR 0x430080C0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX0_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL 0x43008080 +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD2_S) +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD3_S) +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_CONTROL_BYPASS_S) +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WRX0_GLPE_WRX_DTM_CONTROL_RSVD4_S) +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WRX0_GLPE_WRX_DTM_ECC_COR_ERR 0x430080E8 +#define IG3_WRX0_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WRX0_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX0_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WRX0_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX0_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WRX0_GLPE_WRX_DTM_ECC_UNCOR_ERR 0x430080E4 +#define IG3_WRX0_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WRX0_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX0_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WRX0_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX0_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG 0x4300808C +#define IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX0_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WRX0_GLPE_WRX_DTM_LOG_CFG 0x43008090 +#define IG3_WRX0_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WRX0_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WRX0_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WRX0_GLPE_WRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WRX0_GLPE_WRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WRX0_GLPE_WRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WRX0_GLPE_WRX_DTM_LOG_CFG_MODE_S) +#define IG3_WRX0_GLPE_WRX_DTM_LOG_MASK 0x43008098 +#define IG3_WRX0_GLPE_WRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_LOG_MASK_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_LOG_PATTERN 0x43008094 +#define IG3_WRX0_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG 0x43008084 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_STS 0x43008088 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TIMESTAMP 0x430080B0 +#define IG3_WRX0_GLPE_WRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER 0x430080B4 +#define IG3_WRX0_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG 0x430080DC +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS 0x430080E0 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG 0x4300809C +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WRX0_GLPE_WRX_DTM_TRIG_CFG_MODE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_COUNT 0x430080A8 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_MASK 0x430080A4 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_PATTERN 0x430080A0 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_TIMESTAMP 0x430080AC +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WRX0_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHHI 0x43008020 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WRX0_GLPE_WRX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX0_GLPE_WRX_FWQPFLUSHHI_QPID_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WRX0_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO 0x4300801C +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_BUSY_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WRX0_GLPE_WRX_FWQPFLUSHLO_PMF_S) +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_CTRL 0x43008004 +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S 7 +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x1FFFFFF, IG3_WRX0_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S) +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S 0 +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_M RDMA_MASK3(32, 0x7F, IG3_WRX0_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S) +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA0 0x43008008 +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA0_DATA_S 0 +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA0_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA0_DATA_S) +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA1 0x4300800C +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA1_DATA_S 0 +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA1_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA1_DATA_S) +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA2 0x43008010 +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA2_DATA_S 0 +#define IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA2_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX0_GLPE_WRX_RQ_CACHE_DATA2_DATA_S) +#define IG3_SQC0_GLPE_SQC_CONFIG 0x43008470 +#define IG3_SQC0_GLPE_SQC_CONFIG_RSVD_S 6 +#define IG3_SQC0_GLPE_SQC_CONFIG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_SQC0_GLPE_SQC_CONFIG_RSVD_S) +#define IG3_SQC0_GLPE_SQC_CONFIG_DBL_INDV_DIS_S 3 +#define IG3_SQC0_GLPE_SQC_CONFIG_DBL_INDV_DIS_M RDMA_MASK3(32, 0x7, IG3_SQC0_GLPE_SQC_CONFIG_DBL_INDV_DIS_S) +#define IG3_SQC0_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S 2 +#define IG3_SQC0_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_SQC0_GLPE_SQC_CONFIG_DBL_DIS_S 1 +#define IG3_SQC0_GLPE_SQC_CONFIG_DBL_DIS_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_CONFIG_DBL_DIS_S) +#define IG3_SQC0_GLPE_SQC_CONFIG_COALESCE_DIS_S 0 +#define IG3_SQC0_GLPE_SQC_CONFIG_COALESCE_DIS_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_CONFIG_COALESCE_DIS_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_COUNT 0x430084B8 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_CMD 0x430084CC +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_DATA_H 0x430084D8 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_DATA_L 0x430084D4 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_PTR 0x430084D0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_CMD 0x430084BC +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_DATA_H 0x430084C8 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_DATA_L 0x430084C4 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_PTR 0x430084C0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC0_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL 0x43008480 +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD1_S 25 +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD2_S 17 +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD2_S) +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD3_S 9 +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD3_S) +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_BYPASS_S 8 +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_CONTROL_BYPASS_S) +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD4_S 1 +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SQC0_GLPE_SQC_DTM_CONTROL_RSVD4_S) +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SQC0_GLPE_SQC_DTM_ECC_COR_ERR 0x430084E8 +#define IG3_SQC0_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC0_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC0_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SQC0_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SQC0_GLPE_SQC_DTM_ECC_UNCOR_ERR 0x430084E4 +#define IG3_SQC0_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC0_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC0_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC0_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG 0x4300848C +#define IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC0_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SQC0_GLPE_SQC_DTM_LOG_CFG 0x43008490 +#define IG3_SQC0_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SQC0_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SQC0_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SQC0_GLPE_SQC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SQC0_GLPE_SQC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SQC0_GLPE_SQC_DTM_LOG_CFG_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_LOG_CFG_MODE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SQC0_GLPE_SQC_DTM_LOG_CFG_MODE_S) +#define IG3_SQC0_GLPE_SQC_DTM_LOG_MASK 0x43008498 +#define IG3_SQC0_GLPE_SQC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_LOG_MASK_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_LOG_PATTERN 0x43008494 +#define IG3_SQC0_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG 0x43008484 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_STS 0x43008488 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_RSVD2_S) +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TIMESTAMP 0x430084B0 +#define IG3_SQC0_GLPE_SQC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_TIMESTAMP_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER 0x430084B4 +#define IG3_SQC0_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG 0x430084DC +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS 0x430084E0 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG 0x4300849C +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SQC0_GLPE_SQC_DTM_TRIG_CFG_MODE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_COUNT 0x430084A8 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_MASK 0x430084A4 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_TRIG_MASK_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_PATTERN 0x430084A0 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_TIMESTAMP 0x430084AC +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SQC0_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC0_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI 0x43008460 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S 26 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S 6 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S 0 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO 0x43008464 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S 31 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S 29 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S 26 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S) +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S 0 +#define IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S) +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI(_i) 0x43008420 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_MAX_INDEX_I 7 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S 26 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S) +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_QPID_S 6 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_QPID_S) +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S 0 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC0_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S) +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO(_i) 0x43008400 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_MAX_INDEX_I 7 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_EN_S 31 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_EN_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_EN_S) +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S 29 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S) +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S 26 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S) +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S 24 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S) +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S 12 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S) +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_PMF_S 0 +#define IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_FWFLUSHDROPLO_PMF_S) +#define IG3_SQC0_GLPE_SQC_FWSYNCRESP(_i) 0x43008468 + ((_i) * 4) /* _i=0...1 */ +#define IG3_SQC0_GLPE_SQC_FWSYNCRESP_MAX_INDEX_I 1 +#define IG3_SQC0_GLPE_SQC_FWSYNCRESP_RSVD_S 18 +#define IG3_SQC0_GLPE_SQC_FWSYNCRESP_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_SQC0_GLPE_SQC_FWSYNCRESP_RSVD_S) +#define IG3_SQC0_GLPE_SQC_FWSYNCRESP_COUNT_S 8 +#define IG3_SQC0_GLPE_SQC_FWSYNCRESP_COUNT_M RDMA_MASK3(32, 0x3FF, IG3_SQC0_GLPE_SQC_FWSYNCRESP_COUNT_S) +#define IG3_SQC0_GLPE_SQC_FWSYNCRESP_TAG_S 0 +#define IG3_SQC0_GLPE_SQC_FWSYNCRESP_TAG_M RDMA_MASK3(32, 0xFF, IG3_SQC0_GLPE_SQC_FWSYNCRESP_TAG_S) +#define IG3_SQC0_GLPE_SQC_XLR_DROP(_i) 0x43008440 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC0_GLPE_SQC_XLR_DROP_MAX_INDEX_I 7 +#define IG3_SQC0_GLPE_SQC_XLR_DROP_EN_S 31 +#define IG3_SQC0_GLPE_SQC_XLR_DROP_EN_M RDMA_BIT2(32, IG3_SQC0_GLPE_SQC_XLR_DROP_EN_S) +#define IG3_SQC0_GLPE_SQC_XLR_DROP_RSVD0_S 12 +#define IG3_SQC0_GLPE_SQC_XLR_DROP_RSVD0_M RDMA_MASK3(32, 0x7FFFF, IG3_SQC0_GLPE_SQC_XLR_DROP_RSVD0_S) +#define IG3_SQC0_GLPE_SQC_XLR_DROP_PMF_S 0 +#define IG3_SQC0_GLPE_SQC_XLR_DROP_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_GLPE_SQC_XLR_DROP_PMF_S) +#define IG3_SQC0_SQC_ECC_COR_ERR 0x43008514 +#define IG3_SQC0_SQC_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC0_SQC_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC0_SQC_ECC_COR_ERR_RSVD_S) +#define IG3_SQC0_SQC_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC0_SQC_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_SQC_ECC_COR_ERR_CNT_S) +#define IG3_SQC0_SQC_ECC_UNCOR_ERR 0x43008510 +#define IG3_SQC0_SQC_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC0_SQC_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC0_SQC_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC0_SQC_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC0_SQC_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC0_SQC_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG 0x43008500 +#define IG3_SQC0_SQC_WRK_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC0_SQC_WRK_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC0_SQC_WRK_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_RSVD3_S 20 +#define IG3_SQC0_SQC_WRK_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC0_SQC_WRK_RAM_CFG_RSVD3_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_RM_S 16 +#define IG3_SQC0_SQC_WRK_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC0_SQC_WRK_RAM_CFG_RM_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_RSVD2_S 14 +#define IG3_SQC0_SQC_WRK_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC0_SQC_WRK_RAM_CFG_RSVD2_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC0_SQC_WRK_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_RME_S 12 +#define IG3_SQC0_SQC_WRK_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_RME_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_RSVD1_S 10 +#define IG3_SQC0_SQC_WRK_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC0_SQC_WRK_RAM_CFG_RSVD1_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC0_SQC_WRK_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_ERR_CNT_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC0_SQC_WRK_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_FIX_CNT_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_RSVD0_S 6 +#define IG3_SQC0_SQC_WRK_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC0_SQC_WRK_RAM_CFG_RSVD0_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC0_SQC_WRK_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_MASK_INT_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC0_SQC_WRK_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC0_SQC_WRK_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_LS_FORCE_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC0_SQC_WRK_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC0_SQC_WRK_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC0_SQC_WRK_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC0_SQC_WRK_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_CFG_ECC_EN_S) +#define IG3_SQC0_SQC_WRK_RAM_STATUS 0x43008504 +#define IG3_SQC0_SQC_WRK_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC0_SQC_WRK_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC0_SQC_WRK_RAM_STATUS_RSVD1_S) +#define IG3_SQC0_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC0_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC0_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC0_SQC_WRK_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC0_SQC_WRK_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC0_SQC_WRK_RAM_STATUS_RSVD0_S) +#define IG3_SQC0_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC0_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC0_SQC_WRK_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC0_SQC_WRK_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC0_SQC_WRK_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC0_SQC_WRK_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC0_SQC_WRK_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC0_SQC_WRK_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC0_SQC_WRK_RAM_STATUS_ECC_ERR_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG 0x43008508 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD3_S 20 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD3_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RM_S 16 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC0_SQC_XBUF_RAM_CFG_RM_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD2_S 14 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD2_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RME_S 12 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_RME_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD1_S 10 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD1_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_ERR_CNT_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_FIX_CNT_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD0_S 6 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC0_SQC_XBUF_RAM_CFG_RSVD0_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_MASK_INT_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_LS_FORCE_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_CFG_ECC_EN_S) +#define IG3_SQC0_SQC_XBUF_RAM_STATUS 0x4300850C +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC0_SQC_XBUF_RAM_STATUS_RSVD1_S) +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC0_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC0_SQC_XBUF_RAM_STATUS_RSVD0_S) +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC0_SQC_XBUF_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC0_SQC_XBUF_RAM_STATUS_ECC_ERR_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DOMAIN_ID 0x43008804 +#define IG3_SFPRX0_GLPE_SFP_RX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPRX0_GLPE_SFP_RX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DOMAIN_ID_RSVD_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPRX0_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_COUNT 0x430088B8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_CMD 0x430088CC +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H 0x430088D8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L 0x430088D4 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_PTR 0x430088D0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_CMD 0x430088BC +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H 0x430088C8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L 0x430088C4 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_PTR 0x430088C0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL 0x43008880 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_COR_ERR 0x430088E8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR 0x430088E4 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG 0x4300888C +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG 0x43008890 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_MASK 0x43008898 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_PATTERN 0x43008894 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG 0x43008884 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS 0x43008888 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TIMESTAMP 0x430088B0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER 0x430088B4 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG 0x430088DC +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS 0x430088E0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG 0x4300889C +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_COUNT 0x430088A8 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_MASK 0x430088A4 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_PATTERN 0x430088A0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP 0x430088AC +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR 0x43008800 +#define IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S 31 +#define IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR_REQ_M RDMA_BIT2(32, IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S) +#define IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S 12 +#define IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S) +#define IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX0_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S) +#define IG3_SFPRX0_GLPE_SFP_RX_PER_MEM 0x43008808 +#define IG3_SFPRX0_GLPE_SFP_RX_PER_MEM_RSVD_S 3 +#define IG3_SFPRX0_GLPE_SFP_RX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX0_GLPE_SFP_RX_PER_MEM_RSVD_S) +#define IG3_SFPRX0_GLPE_SFP_RX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPRX0_GLPE_SFP_RX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPRX0_GLPE_SFP_RX_PER_MEM_PER_TYPE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG 0x43008C08 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS 0x43008C0C +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_COR_ERR 0x43008C34 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR 0x43008C30 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG 0x43008C18 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS 0x43008C1C +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG 0x43008C20 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS 0x43008C24 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG 0x43008C00 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS 0x43008C04 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG 0x43008C28 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS 0x43008C2C +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG 0x43008C10 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS 0x43008C14 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG 0x43008C48 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS 0x43008C4C +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG 0x43008C40 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS 0x43008C44 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG 0x43008C78 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS 0x43008C7C +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG 0x43008C50 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS 0x43008C54 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG 0x43008C58 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS 0x43008C5C +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR 0x43008C84 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR 0x43008C80 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG 0x43008C70 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS 0x43008C74 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG 0x43008C60 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS 0x43008C64 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG 0x43008C68 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS 0x43008C6C +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG 0x43008C38 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS 0x43008C3C +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_COR_ERR 0x43008CCC +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR 0x43008CC8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG 0x43008CD8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS 0x43008CDC +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL 0x43008C90 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA 0x43008C94 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG 0x43008C88 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS 0x43008C8C +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL 0x43008CA0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA 0x43008CA4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG 0x43008C98 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS 0x43008C9C +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL 0x43008CB0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA 0x43008CB4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG 0x43008CA8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS 0x43008CAC +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL 0x43008CC0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA 0x43008CC4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG 0x43008CB8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS 0x43008CBC +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG 0x43008CD0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS 0x43008CD4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_WTX0_GLPE_WTX_1USCOUNT 0x43010010 +#define IG3_WTX0_GLPE_WTX_1USCOUNT_CNT_S 0 +#define IG3_WTX0_GLPE_WTX_1USCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_1USCOUNT_CNT_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0 0x43010120 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1 0x43010124 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2 0x43010128 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG3 0x4301012C +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG4 0x43010130 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG 0x43010020 +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD3_S 24 +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD3_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD3_S) +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD2_S 20 +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD2_S) +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S 16 +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S) +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD1_S 12 +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S 8 +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S) +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD0_S 4 +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD0_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_ARB_CONFIG_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S 0 +#define IG3_WTX0_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0 0x430100F8 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1 0x430100FC +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2 0x43010100 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG3 0x43010104 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG4 0x43010108 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG 0x4301017C +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX 0x43010180 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_CNPCOUNT 0x43010014 +#define IG3_WTX0_GLPE_WTX_CNPCOUNT_CNT_S 0 +#define IG3_WTX0_GLPE_WTX_CNPCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_CNPCOUNT_CNT_S) +#define IG3_WTX0_GLPE_WTX_CONFIG 0x4301000C +#define IG3_WTX0_GLPE_WTX_CONFIG_RSVD1_S 28 +#define IG3_WTX0_GLPE_WTX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_CONFIG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_CONFIG_SQ_HSM_ORD_S 25 +#define IG3_WTX0_GLPE_WTX_CONFIG_SQ_HSM_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_CONFIG_SQ_HSM_ORD_S) +#define IG3_WTX0_GLPE_WTX_CONFIG_SQ_WQE_ORD_S 22 +#define IG3_WTX0_GLPE_WTX_CONFIG_SQ_WQE_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_CONFIG_SQ_WQE_ORD_S) +#define IG3_WTX0_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S 21 +#define IG3_WTX0_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S) +#define IG3_WTX0_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S 20 +#define IG3_WTX0_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_WTX0_GLPE_WTX_CONFIG_RSVD0_S 4 +#define IG3_WTX0_GLPE_WTX_CONFIG_RSVD0_M RDMA_MASK3(32, 0xFFFF, IG3_WTX0_GLPE_WTX_CONFIG_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S 3 +#define IG3_WTX0_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S) +#define IG3_WTX0_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S 2 +#define IG3_WTX0_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S) +#define IG3_WTX0_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S 1 +#define IG3_WTX0_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S) +#define IG3_WTX0_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S 0 +#define IG3_WTX0_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG0 0x4301003C +#define IG3_WTX0_GLPE_WTX_CTCONFIG0_RSVD_S 21 +#define IG3_WTX0_GLPE_WTX_CTCONFIG0_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX0_GLPE_WTX_CTCONFIG0_RSVD_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG0_SCHED_S 0 +#define IG3_WTX0_GLPE_WTX_CTCONFIG0_SCHED_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX0_GLPE_WTX_CTCONFIG0_SCHED_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG1 0x43010040 +#define IG3_WTX0_GLPE_WTX_CTCONFIG1_RSVD_S 21 +#define IG3_WTX0_GLPE_WTX_CTCONFIG1_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX0_GLPE_WTX_CTCONFIG1_RSVD_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG1_VMRL_S 0 +#define IG3_WTX0_GLPE_WTX_CTCONFIG1_VMRL_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX0_GLPE_WTX_CTCONFIG1_VMRL_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG2 0x43010044 +#define IG3_WTX0_GLPE_WTX_CTCONFIG2_RSVD_S 30 +#define IG3_WTX0_GLPE_WTX_CTCONFIG2_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_CTCONFIG2_RSVD_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S 16 +#define IG3_WTX0_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S 0 +#define IG3_WTX0_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX0_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG3 0x43010048 +#define IG3_WTX0_GLPE_WTX_CTCONFIG3_RSVD_S 30 +#define IG3_WTX0_GLPE_WTX_CTCONFIG3_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_CTCONFIG3_RSVD_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S 16 +#define IG3_WTX0_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S 0 +#define IG3_WTX0_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX0_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG4 0x4301004C +#define IG3_WTX0_GLPE_WTX_CTCONFIG4_RSVD_S 30 +#define IG3_WTX0_GLPE_WTX_CTCONFIG4_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_CTCONFIG4_RSVD_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S 16 +#define IG3_WTX0_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S 0 +#define IG3_WTX0_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX0_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG5 0x43010050 +#define IG3_WTX0_GLPE_WTX_CTCONFIG5_RSVD_S 20 +#define IG3_WTX0_GLPE_WTX_CTCONFIG5_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_CTCONFIG5_RSVD_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG5_BMPKT_S 0 +#define IG3_WTX0_GLPE_WTX_CTCONFIG5_BMPKT_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX0_GLPE_WTX_CTCONFIG5_BMPKT_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG6 0x43010054 +#define IG3_WTX0_GLPE_WTX_CTCONFIG6_RSVD_S 13 +#define IG3_WTX0_GLPE_WTX_CTCONFIG6_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_WTX0_GLPE_WTX_CTCONFIG6_RSVD_S) +#define IG3_WTX0_GLPE_WTX_CTCONFIG6_BMHDR_S 0 +#define IG3_WTX0_GLPE_WTX_CTCONFIG6_BMHDR_M RDMA_MASK3(32, 0x1FFF, IG3_WTX0_GLPE_WTX_CTCONFIG6_BMHDR_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_COUNT 0x43010238 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_CMD 0x4301024C +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_DATA_H 0x43010258 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_DATA_L 0x43010254 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_PTR 0x43010250 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_CMD 0x4301023C +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_DATA_H 0x43010248 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_DATA_L 0x43010244 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_PTR 0x43010240 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX0_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL 0x43010200 +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD2_S) +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD3_S) +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_CONTROL_BYPASS_S) +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WTX0_GLPE_WTX_DTM_CONTROL_RSVD4_S) +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WTX0_GLPE_WTX_DTM_ECC_COR_ERR 0x43010268 +#define IG3_WTX0_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX0_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WTX0_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WTX0_GLPE_WTX_DTM_ECC_UNCOR_ERR 0x43010264 +#define IG3_WTX0_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX0_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WTX0_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG 0x4301020C +#define IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WTX0_GLPE_WTX_DTM_LOG_CFG 0x43010210 +#define IG3_WTX0_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WTX0_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WTX0_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WTX0_GLPE_WTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WTX0_GLPE_WTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_DTM_LOG_CFG_MODE_S) +#define IG3_WTX0_GLPE_WTX_DTM_LOG_MASK 0x43010218 +#define IG3_WTX0_GLPE_WTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_LOG_MASK_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_LOG_PATTERN 0x43010214 +#define IG3_WTX0_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG 0x43010204 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_STS 0x43010208 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TIMESTAMP 0x43010230 +#define IG3_WTX0_GLPE_WTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER 0x43010234 +#define IG3_WTX0_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG 0x4301025C +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS 0x43010260 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG 0x4301021C +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_DTM_TRIG_CFG_MODE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_COUNT 0x43010228 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_MASK 0x43010224 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_PATTERN 0x43010220 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_TIMESTAMP 0x4301022C +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WTX0_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG 0x4301014C +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG 0x43010150 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX 0x43010154 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHHI 0x4301005C +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX0_GLPE_WTX_FWQPFLUSHHI_QPID_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO 0x43010058 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_BUSY_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_FWQPFLUSHLO_PMF_S) +#define IG3_WTX0_GLPE_WTX_HOST_READ_CONFIG 0x43010038 +#define IG3_WTX0_GLPE_WTX_HOST_READ_CONFIG_RSVD_S 8 +#define IG3_WTX0_GLPE_WTX_HOST_READ_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_HOST_READ_CONFIG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S 0 +#define IG3_WTX0_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0 0x4301010C +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1 0x43010110 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2 0x43010114 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG3 0x43010118 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG4 0x4301011C +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG 0x4301018C +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX 0x43010190 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG 0x43010194 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX 0x43010198 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG 0x43010184 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX 0x43010188 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0 0x43010090 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1 0x43010094 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2 0x43010098 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG3 0x4301009C +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG4 0x430100A0 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0 0x43010060 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1 0x43010064 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2 0x43010068 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG3 0x4301006C +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG4 0x43010070 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG5 0x43010074 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0 0x43010078 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1 0x4301007C +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2 0x43010080 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG3 0x43010084 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG4 0x43010088 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG5 0x4301008C +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG 0x43010134 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG 0x43010138 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX 0x4301013C +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG 0x43010140 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG 0x43010144 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX 0x43010148 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG 0x43010164 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG 0x43010168 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX 0x4301016C +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG 0x43010158 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG 0x4301015C +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX 0x43010160 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0 0x430100E4 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1 0x430100E8 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2 0x430100EC +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG3 0x430100F0 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG4 0x430100F4 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0 0x430100D0 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1 0x430100D4 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2 0x430100D8 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG3 0x430100DC +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG4 0x430100E0 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED(_i) 0x43010000 + ((_i) * 4) /* _i=0...2 */ +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_MAX_INDEX_I 2 +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S 24 +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD3_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S) +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S 16 +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD2_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S) +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S 8 +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S) +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S 0 +#define IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD0_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0 0x430100A4 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1 0x430100A8 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2 0x430100AC +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG3 0x430100B0 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG4 0x430100B4 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG5 0x430100B8 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG0 0x43010024 +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S 24 +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S) +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S 16 +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S) +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S 8 +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S) +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S) +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG1 0x43010028 +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG1_RSVD_S 8 +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_CONFIG1_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S) +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0 0x4301002C +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S 24 +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S) +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S 16 +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S) +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S 8 +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S) +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S) +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS1 0x43010030 +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S 8 +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0 0x430100BC +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1 0x430100C0 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2 0x430100C4 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG3 0x430100C8 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG4 0x430100CC +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S) +#define IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL 0x43010034 +#define IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S 16 +#define IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S 8 +#define IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S) +#define IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S) +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL 0x43010018 +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S 20 +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S 16 +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_M RDMA_MASK3(32, 0xF, IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S) +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S 10 +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S 8 +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_M RDMA_MASK3(32, 0x3, IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S) +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_M RDMA_MASK3(32, 0xFF, IG3_WTX0_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S) +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_DATA 0x4301001C +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_DATA_DATA_S 0 +#define IG3_WTX0_GLPE_WTX_SPAD_STAT_DATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX0_GLPE_WTX_SPAD_STAT_DATA_DATA_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG 0x43010170 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG 0x43010174 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX 0x43010178 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX0_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_PTX0_GLPE_ARPCONTROL 0x4301400C +#define IG3_PTX0_GLPE_ARPCONTROL_ARP_LOCK_ACK_S 31 +#define IG3_PTX0_GLPE_ARPCONTROL_ARP_LOCK_ACK_M RDMA_BIT2(32, IG3_PTX0_GLPE_ARPCONTROL_ARP_LOCK_ACK_S) +#define IG3_PTX0_GLPE_ARPCONTROL_ARP_LOCK_REQ_S 30 +#define IG3_PTX0_GLPE_ARPCONTROL_ARP_LOCK_REQ_M RDMA_BIT2(32, IG3_PTX0_GLPE_ARPCONTROL_ARP_LOCK_REQ_S) +#define IG3_PTX0_GLPE_ARPCONTROL_RSVD_S 16 +#define IG3_PTX0_GLPE_ARPCONTROL_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_PTX0_GLPE_ARPCONTROL_RSVD_S) +#define IG3_PTX0_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S 0 +#define IG3_PTX0_GLPE_ARPCONTROL_ARP_LOCK_INDEX_M RDMA_MASK3(32, 0xFFFF, IG3_PTX0_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S) +#define IG3_PTX0_GLPE_CRT_CONFIG0 0x43014010 +#define IG3_PTX0_GLPE_CRT_CONFIG0_RSVD_S 25 +#define IG3_PTX0_GLPE_CRT_CONFIG0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_CRT_CONFIG0_RSVD_S) +#define IG3_PTX0_GLPE_CRT_CONFIG0_QP_FC_EN_S 24 +#define IG3_PTX0_GLPE_CRT_CONFIG0_QP_FC_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_CRT_CONFIG0_QP_FC_EN_S) +#define IG3_PTX0_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S 16 +#define IG3_PTX0_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S) +#define IG3_PTX0_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S 8 +#define IG3_PTX0_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S) +#define IG3_PTX0_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S 0 +#define IG3_PTX0_GLPE_CRT_CONFIG0_TX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S) +#define IG3_PTX0_GLPE_CRT_CONFIG1 0x43014014 +#define IG3_PTX0_GLPE_CRT_CONFIG1_RSVD_S 19 +#define IG3_PTX0_GLPE_CRT_CONFIG1_RSVD_M RDMA_MASK3(32, 0x1FFF, IG3_PTX0_GLPE_CRT_CONFIG1_RSVD_S) +#define IG3_PTX0_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S 16 +#define IG3_PTX0_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_M RDMA_MASK3(32, 0x7, IG3_PTX0_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S) +#define IG3_PTX0_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S 8 +#define IG3_PTX0_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S) +#define IG3_PTX0_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S 0 +#define IG3_PTX0_GLPE_CRT_CONFIG1_RX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S) +#define IG3_PTX0_GLPE_MAX_INLINE_DATA 0x43014000 +#define IG3_PTX0_GLPE_MAX_INLINE_DATA_RSVD_S 8 +#define IG3_PTX0_GLPE_MAX_INLINE_DATA_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX0_GLPE_MAX_INLINE_DATA_RSVD_S) +#define IG3_PTX0_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S 0 +#define IG3_PTX0_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S) +#define IG3_PTX0_GLPE_MAX_TCP_ACKS 0x43014004 +#define IG3_PTX0_GLPE_MAX_TCP_ACKS_RSVD_S 8 +#define IG3_PTX0_GLPE_MAX_TCP_ACKS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX0_GLPE_MAX_TCP_ACKS_RSVD_S) +#define IG3_PTX0_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S 0 +#define IG3_PTX0_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0 0x43014018 +#define IG3_PTX0_GLPE_PTX_CONFIG0_RSVD_31_S 31 +#define IG3_PTX0_GLPE_PTX_CONFIG0_RSVD_31_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_RSVD_31_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S 30 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S 29 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S 28 +#define IG3_PTX0_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S 27 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S 26 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S 22 +#define IG3_PTX0_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_M RDMA_MASK3(32, 0xF, IG3_PTX0_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S 21 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S 20 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_RSVD_19_S 19 +#define IG3_PTX0_GLPE_PTX_CONFIG0_RSVD_19_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_RSVD_19_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S 18 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S 17 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S 16 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S 15 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S 14 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_RSVD_13_7_S 7 +#define IG3_PTX0_GLPE_PTX_CONFIG0_RSVD_13_7_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_PTX_CONFIG0_RSVD_13_7_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_UDP_CS_EN_S 6 +#define IG3_PTX0_GLPE_PTX_CONFIG0_UDP_CS_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_UDP_CS_EN_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S 5 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_Q1_PACING_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S 4 +#define IG3_PTX0_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S 3 +#define IG3_PTX0_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S 1 +#define IG3_PTX0_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S) +#define IG3_PTX0_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S 0 +#define IG3_PTX0_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S) +#define IG3_PTX0_GLPE_PTX_CONFIG1 0x4301401C +#define IG3_PTX0_GLPE_PTX_CONFIG1_RSVD_S 24 +#define IG3_PTX0_GLPE_PTX_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_CONFIG1_RSVD_S) +#define IG3_PTX0_GLPE_PTX_CONFIG1_ACKREQ_PACING_S 21 +#define IG3_PTX0_GLPE_PTX_CONFIG1_ACKREQ_PACING_M RDMA_MASK3(32, 0x7, IG3_PTX0_GLPE_PTX_CONFIG1_ACKREQ_PACING_S) +#define IG3_PTX0_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S 16 +#define IG3_PTX0_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_M RDMA_MASK3(32, 0x1F, IG3_PTX0_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S) +#define IG3_PTX0_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S 0 +#define IG3_PTX0_GLPE_PTX_CONFIG1_Q1_PACING_MULT_M RDMA_MASK3(32, 0xFFFF, IG3_PTX0_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S) +#define IG3_PTX0_GLPE_PTX_CONFIG2 0x43014020 +#define IG3_PTX0_GLPE_PTX_CONFIG2_SEND2CPU_S 0 +#define IG3_PTX0_GLPE_PTX_CONFIG2_SEND2CPU_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_CONFIG2_SEND2CPU_S) +#define IG3_PTX0_GLPE_PTX_CRT_XMIT_PTR 0x4301402C +#define IG3_PTX0_GLPE_PTX_CRT_XMIT_PTR_RSVD_S 8 +#define IG3_PTX0_GLPE_PTX_CRT_XMIT_PTR_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX0_GLPE_PTX_CRT_XMIT_PTR_RSVD_S) +#define IG3_PTX0_GLPE_PTX_CRT_XMIT_PTR_COUNT_S 0 +#define IG3_PTX0_GLPE_PTX_CRT_XMIT_PTR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_CRT_XMIT_PTR_COUNT_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_COUNT 0x43014138 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_CMD 0x4301414C +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_DATA_H 0x43014158 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_DATA_L 0x43014154 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_PTR 0x43014150 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_CMD 0x4301413C +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_DATA_H 0x43014148 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_DATA_L 0x43014144 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_PTR 0x43014140 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX0_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL 0x43014100 +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD2_S) +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD3_S) +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_CONTROL_BYPASS_S) +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_PTX_DTM_CONTROL_RSVD4_S) +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PTX0_GLPE_PTX_DTM_ECC_COR_ERR 0x43014168 +#define IG3_PTX0_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PTX0_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX0_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PTX0_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PTX0_GLPE_PTX_DTM_ECC_UNCOR_ERR 0x43014164 +#define IG3_PTX0_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PTX0_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX0_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PTX0_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG 0x4301410C +#define IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PTX0_GLPE_PTX_DTM_LOG_CFG 0x43014110 +#define IG3_PTX0_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PTX0_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PTX0_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PTX0_GLPE_PTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PTX0_GLPE_PTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PTX0_GLPE_PTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_DTM_LOG_CFG_MODE_S) +#define IG3_PTX0_GLPE_PTX_DTM_LOG_MASK 0x43014118 +#define IG3_PTX0_GLPE_PTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_LOG_MASK_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_LOG_PATTERN 0x43014114 +#define IG3_PTX0_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG 0x43014104 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_STS 0x43014108 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TIMESTAMP 0x43014130 +#define IG3_PTX0_GLPE_PTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER 0x43014134 +#define IG3_PTX0_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG 0x4301415C +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS 0x43014160 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG 0x4301411C +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PTX0_GLPE_PTX_DTM_TRIG_CFG_MODE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_COUNT 0x43014128 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_MASK 0x43014124 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_PATTERN 0x43014120 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_TIMESTAMP 0x4301412C +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PTX0_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHHI 0x43014028 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_PTX0_GLPE_PTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX0_GLPE_PTX_FWQPFLUSHHI_QPID_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX0_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO 0x43014024 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_BUSY_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_FWQPFLUSHLO_PMF_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0 0x43014044 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_TAG_S 16 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_TAG_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_MODE_S 11 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_MODE_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1 0x43014048 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_PMF_S 0 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG1_PMF_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2 0x4301404C +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2_QPID_S 6 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2_QPID_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG3 0x43014050 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG4 0x43014054 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0 0x43014058 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_TAG_S 16 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_TAG_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_MODE_S 11 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_MODE_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1 0x4301405C +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_PMF_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG1_PMF_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2 0x43014060 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2_QPID_S 6 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2_QPID_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG3 0x43014064 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG4 0x43014068 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT0 0x43014078 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S 1 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT1 0x4301407C +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT2 0x43014080 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE0 0x4301406C +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S 1 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE1 0x43014070 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S 24 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE2 0x43014074 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S 24 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S) +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S 0 +#define IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX0_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0 0x43014030 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S 16 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S 11 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1 0x43014034 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S 0 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2 0x43014038 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S 6 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG3 0x4301403C +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG4 0x43014040 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX0_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S) +#define IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD 0x43014008 +#define IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S 25 +#define IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S) +#define IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S 24 +#define IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_M RDMA_BIT2(32, IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S) +#define IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S 0 +#define IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX0_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_COUNT 0x430144B8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_CMD 0x430144CC +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_DATA_H 0x430144D8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_DATA_L 0x430144D4 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_PTR 0x430144D0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_CMD 0x430144BC +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_DATA_H 0x430144C8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_DATA_L 0x430144C4 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_PTR 0x430144C0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL 0x43014480 +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD2_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD3_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_BYPASS_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_RSVD4_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_COR_ERR 0x430144E8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX0_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_UNCOR_ERR 0x430144E4 +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX0_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG 0x4301448C +#define IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX0_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG 0x43014490 +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX0_GLPE_SFPT_DTM_LOG_CFG_MODE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_MASK 0x43014498 +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_PATTERN 0x43014494 +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG 0x43014484 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS 0x43014488 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TIMESTAMP 0x430144B0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER 0x430144B4 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG 0x430144DC +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS 0x430144E0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPTX0_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG 0x4301449C +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_COUNT 0x430144A8 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_MASK 0x430144A4 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_PATTERN 0x430144A0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_TIMESTAMP 0x430144AC +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX0_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPTX0_GLPE_SFP_TX_DOMAIN_ID 0x43014400 +#define IG3_SFPTX0_GLPE_SFP_TX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPTX0_GLPE_SFP_TX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX0_GLPE_SFP_TX_DOMAIN_ID_RSVD_S) +#define IG3_SFPTX0_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPTX0_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPTX0_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPTX0_GLPE_SFP_TX_PER_MEM 0x43014404 +#define IG3_SFPTX0_GLPE_SFP_TX_PER_MEM_RSVD_S 3 +#define IG3_SFPTX0_GLPE_SFP_TX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX0_GLPE_SFP_TX_PER_MEM_RSVD_S) +#define IG3_SFPTX0_GLPE_SFP_TX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPTX0_GLPE_SFP_TX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPTX0_GLPE_SFP_TX_PER_MEM_PER_TYPE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG 0x43014800 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS 0x43014804 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG 0x43014810 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS 0x43014814 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_COR_ERR 0x43014834 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR 0x43014830 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG 0x43014818 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS 0x4301481C +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG 0x43014808 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS 0x4301480C +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG 0x43014828 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS 0x4301482C +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG 0x43014820 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS 0x43014824 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG 0x43014840 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS 0x43014844 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG 0x43014848 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS 0x4301484C +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG 0x43014850 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS 0x43014854 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG 0x43014858 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS 0x4301485C +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR 0x4301487C +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR 0x43014878 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG 0x43014860 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS 0x43014864 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG 0x43014868 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS 0x4301486C +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG 0x43014870 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS 0x43014874 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG 0x43014838 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS 0x4301483C +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL 0x430148C8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S 31 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_DATA 0x430148CC +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG 0x430148C0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS 0x430148C4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_COR_ERR 0x430148E4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR 0x430148E0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL 0x430148D8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S 31 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA 0x430148DC +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG 0x430148D0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS 0x430148D4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL 0x43014888 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA 0x4301488C +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG 0x43014880 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS 0x43014884 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL 0x43014898 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA 0x4301489C +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG 0x43014890 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS 0x43014894 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL 0x430148A8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA 0x430148AC +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG 0x430148A0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS 0x430148A4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL 0x430148B8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA 0x430148BC +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG 0x430148B0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS 0x430148B4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE0_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_DRX0_GLPE_DRX_CONFIG 0x43020800 +#define IG3_DRX0_GLPE_DRX_CONFIG_RSVD1_S 3 +#define IG3_DRX0_GLPE_DRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_DRX0_GLPE_DRX_CONFIG_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_CONFIG_CRC_MASK_S 0 +#define IG3_DRX0_GLPE_DRX_CONFIG_CRC_MASK_M RDMA_MASK3(32, 0x7, IG3_DRX0_GLPE_DRX_CONFIG_CRC_MASK_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_COUNT 0x430208B8 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_CMD 0x430208CC +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_DATA_H 0x430208D8 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_DATA_L 0x430208D4 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_PTR 0x430208D0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_CMD 0x430208BC +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_DATA_H 0x430208C8 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_DATA_L 0x430208C4 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_PTR 0x430208C0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX0_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL 0x43020880 +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD2_S) +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD3_S) +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_CONTROL_BYPASS_S) +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_DRX0_GLPE_DRX_DTM_CONTROL_RSVD4_S) +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_DRX0_GLPE_DRX_DTM_ECC_COR_ERR 0x430208E8 +#define IG3_DRX0_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX0_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX0_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_DRX0_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX0_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_DRX0_GLPE_DRX_DTM_ECC_UNCOR_ERR 0x430208E4 +#define IG3_DRX0_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX0_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX0_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX0_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX0_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG 0x4302088C +#define IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX0_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_DRX0_GLPE_DRX_DTM_LOG_CFG 0x43020890 +#define IG3_DRX0_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_DRX0_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_DRX0_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_DRX0_GLPE_DRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_DRX0_GLPE_DRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_DRX0_GLPE_DRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_DRX_DTM_LOG_CFG_MODE_S) +#define IG3_DRX0_GLPE_DRX_DTM_LOG_MASK 0x43020898 +#define IG3_DRX0_GLPE_DRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_LOG_MASK_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_LOG_PATTERN 0x43020894 +#define IG3_DRX0_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG 0x43020884 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_STS 0x43020888 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TIMESTAMP 0x430208B0 +#define IG3_DRX0_GLPE_DRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER 0x430208B4 +#define IG3_DRX0_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG 0x430208DC +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS 0x430208E0 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX0_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG 0x4302089C +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_DRX0_GLPE_DRX_DTM_TRIG_CFG_MODE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_COUNT 0x430208A8 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_MASK 0x430208A4 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_PATTERN 0x430208A0 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_TIMESTAMP 0x430208AC +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_DRX0_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX0_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_DRX0_GLPE_DRX_ECC_COR_ERR 0x43020804 +#define IG3_DRX0_GLPE_DRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX0_GLPE_DRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX0_GLPE_DRX_ECC_COR_ERR_RSVD_S) +#define IG3_DRX0_GLPE_DRX_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX0_GLPE_DRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX0_GLPE_DRX_ECC_COR_ERR_CNT_S) +#define IG3_DRX0_GLPE_DRX_ECC_UNCOR_ERR 0x43020808 +#define IG3_DRX0_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX0_GLPE_DRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX0_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX0_GLPE_DRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX0_GLPE_DRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX0_GLPE_DRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX0_GLPE_PBUF_CFG 0x4302080C +#define IG3_DRX0_GLPE_PBUF_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX0_GLPE_PBUF_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX0_GLPE_PBUF_CFG_ECC_INST_NUM_S) +#define IG3_DRX0_GLPE_PBUF_CFG_RSVD3_S 20 +#define IG3_DRX0_GLPE_PBUF_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX0_GLPE_PBUF_CFG_RSVD3_S) +#define IG3_DRX0_GLPE_PBUF_CFG_RM_S 16 +#define IG3_DRX0_GLPE_PBUF_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX0_GLPE_PBUF_CFG_RM_S) +#define IG3_DRX0_GLPE_PBUF_CFG_RSVD2_S 14 +#define IG3_DRX0_GLPE_PBUF_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_PBUF_CFG_RSVD2_S) +#define IG3_DRX0_GLPE_PBUF_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX0_GLPE_PBUF_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_POWER_GATE_EN_S) +#define IG3_DRX0_GLPE_PBUF_CFG_RME_S 12 +#define IG3_DRX0_GLPE_PBUF_CFG_RME_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_RME_S) +#define IG3_DRX0_GLPE_PBUF_CFG_RSVD1_S 10 +#define IG3_DRX0_GLPE_PBUF_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_PBUF_CFG_RSVD1_S) +#define IG3_DRX0_GLPE_PBUF_CFG_ERR_CNT_S 9 +#define IG3_DRX0_GLPE_PBUF_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_ERR_CNT_S) +#define IG3_DRX0_GLPE_PBUF_CFG_FIX_CNT_S 8 +#define IG3_DRX0_GLPE_PBUF_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_FIX_CNT_S) +#define IG3_DRX0_GLPE_PBUF_CFG_RSVD0_S 6 +#define IG3_DRX0_GLPE_PBUF_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_PBUF_CFG_RSVD0_S) +#define IG3_DRX0_GLPE_PBUF_CFG_MASK_INT_S 5 +#define IG3_DRX0_GLPE_PBUF_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_MASK_INT_S) +#define IG3_DRX0_GLPE_PBUF_CFG_LS_BYPASS_S 4 +#define IG3_DRX0_GLPE_PBUF_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_LS_BYPASS_S) +#define IG3_DRX0_GLPE_PBUF_CFG_LS_FORCE_S 3 +#define IG3_DRX0_GLPE_PBUF_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_LS_FORCE_S) +#define IG3_DRX0_GLPE_PBUF_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX0_GLPE_PBUF_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_ECC_INVERT_2_S) +#define IG3_DRX0_GLPE_PBUF_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX0_GLPE_PBUF_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_ECC_INVERT_1_S) +#define IG3_DRX0_GLPE_PBUF_CFG_ECC_EN_S 0 +#define IG3_DRX0_GLPE_PBUF_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_CFG_ECC_EN_S) +#define IG3_DRX0_GLPE_PBUF_STATUS 0x43020810 +#define IG3_DRX0_GLPE_PBUF_STATUS_RSVD1_S 30 +#define IG3_DRX0_GLPE_PBUF_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX0_GLPE_PBUF_STATUS_RSVD1_S) +#define IG3_DRX0_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX0_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX0_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX0_GLPE_PBUF_STATUS_RSVD0_S 4 +#define IG3_DRX0_GLPE_PBUF_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX0_GLPE_PBUF_STATUS_RSVD0_S) +#define IG3_DRX0_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX0_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX0_GLPE_PBUF_STATUS_INIT_DONE_S 2 +#define IG3_DRX0_GLPE_PBUF_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_STATUS_INIT_DONE_S) +#define IG3_DRX0_GLPE_PBUF_STATUS_ECC_FIX_S 1 +#define IG3_DRX0_GLPE_PBUF_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_STATUS_ECC_FIX_S) +#define IG3_DRX0_GLPE_PBUF_STATUS_ECC_ERR_S 0 +#define IG3_DRX0_GLPE_PBUF_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX0_GLPE_PBUF_STATUS_ECC_ERR_S) +#define IG3_CMPE0_CMPE_ECC_COR_ERR 0x43020D3C +#define IG3_CMPE0_CMPE_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE0_CMPE_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_CMPE_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE0_CMPE_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE0_CMPE_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_CMPE_ECC_COR_ERR_CNT_S) +#define IG3_CMPE0_CMPE_ECC_UNCOR_ERR 0x43020D38 +#define IG3_CMPE0_CMPE_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE0_CMPE_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_CMPE_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE0_CMPE_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE0_CMPE_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_CMPE_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE0_GLCM_PECLSADDR 0x43020C84 +#define IG3_CMPE0_GLCM_PECLSADDR_RSVD_S 9 +#define IG3_CMPE0_GLCM_PECLSADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE0_GLCM_PECLSADDR_RSVD_S) +#define IG3_CMPE0_GLCM_PECLSADDR_CLS_ADDR_S 0 +#define IG3_CMPE0_GLCM_PECLSADDR_CLS_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE0_GLCM_PECLSADDR_CLS_ADDR_S) +#define IG3_CMPE0_GLCM_PECLSDATA0 0x43020C88 +#define IG3_CMPE0_GLCM_PECLSDATA0_CLS_DATA_S 0 +#define IG3_CMPE0_GLCM_PECLSDATA0_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLCM_PECLSDATA0_CLS_DATA_S) +#define IG3_CMPE0_GLCM_PECLSDATA1 0x43020C8C +#define IG3_CMPE0_GLCM_PECLSDATA1_CLS_DATA_S 0 +#define IG3_CMPE0_GLCM_PECLSDATA1_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLCM_PECLSDATA1_CLS_DATA_S) +#define IG3_CMPE0_GLCM_PECLSDATA2 0x43020C90 +#define IG3_CMPE0_GLCM_PECLSDATA2_CLS_DATA_S 0 +#define IG3_CMPE0_GLCM_PECLSDATA2_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLCM_PECLSDATA2_CLS_DATA_S) +#define IG3_CMPE0_GLCM_PECONFIG 0x43020C80 +#define IG3_CMPE0_GLCM_PECONFIG_DBGMUX_EN_S 31 +#define IG3_CMPE0_GLCM_PECONFIG_DBGMUX_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_DBGMUX_EN_S) +#define IG3_CMPE0_GLCM_PECONFIG_RSVD13_S 30 +#define IG3_CMPE0_GLCM_PECONFIG_RSVD13_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_RSVD13_S) +#define IG3_CMPE0_GLCM_PECONFIG_DBGMUX_SEL_HI_S 25 +#define IG3_CMPE0_GLCM_PECONFIG_DBGMUX_SEL_HI_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PECONFIG_DBGMUX_SEL_HI_S) +#define IG3_CMPE0_GLCM_PECONFIG_DBGMUX_SEL_LO_S 20 +#define IG3_CMPE0_GLCM_PECONFIG_DBGMUX_SEL_LO_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PECONFIG_DBGMUX_SEL_LO_S) +#define IG3_CMPE0_GLCM_PECONFIG_RSVD10_S 17 +#define IG3_CMPE0_GLCM_PECONFIG_RSVD10_M RDMA_MASK3(32, 0x7, IG3_CMPE0_GLCM_PECONFIG_RSVD10_S) +#define IG3_CMPE0_GLCM_PECONFIG_DBG_WRSEL_S 16 +#define IG3_CMPE0_GLCM_PECONFIG_DBG_WRSEL_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_DBG_WRSEL_S) +#define IG3_CMPE0_GLCM_PECONFIG_DBG_DWSEL_S 14 +#define IG3_CMPE0_GLCM_PECONFIG_DBG_DWSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PECONFIG_DBG_DWSEL_S) +#define IG3_CMPE0_GLCM_PECONFIG_DBG_DPSEL_S 12 +#define IG3_CMPE0_GLCM_PECONFIG_DBG_DPSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PECONFIG_DBG_DPSEL_S) +#define IG3_CMPE0_GLCM_PECONFIG_RSVD6_S 7 +#define IG3_CMPE0_GLCM_PECONFIG_RSVD6_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PECONFIG_RSVD6_S) +#define IG3_CMPE0_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S 6 +#define IG3_CMPE0_GLCM_PECONFIG_DISABLE_CTXT_PACKING_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S) +#define IG3_CMPE0_GLCM_PECONFIG_DISABLE_LSA_S 5 +#define IG3_CMPE0_GLCM_PECONFIG_DISABLE_LSA_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_DISABLE_LSA_S) +#define IG3_CMPE0_GLCM_PECONFIG_ENABLE_CRC_S 4 +#define IG3_CMPE0_GLCM_PECONFIG_ENABLE_CRC_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_ENABLE_CRC_S) +#define IG3_CMPE0_GLCM_PECONFIG_DISABLE_RESCHEDULE_S 3 +#define IG3_CMPE0_GLCM_PECONFIG_DISABLE_RESCHEDULE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_DISABLE_RESCHEDULE_S) +#define IG3_CMPE0_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S 2 +#define IG3_CMPE0_GLCM_PECONFIG_DISABLE_PACKET_COUNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S) +#define IG3_CMPE0_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S 1 +#define IG3_CMPE0_GLCM_PECONFIG_GLOBAL_LOCK_MODE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S) +#define IG3_CMPE0_GLCM_PECONFIG_RSVD1_S 0 +#define IG3_CMPE0_GLCM_PECONFIG_RSVD1_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECONFIG_RSVD1_S) +#define IG3_CMPE0_GLCM_PECTXDGCTL 0x43020CC8 +#define IG3_CMPE0_GLCM_PECTXDGCTL_RSVD_S 12 +#define IG3_CMPE0_GLCM_PECTXDGCTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_GLCM_PECTXDGCTL_RSVD_S) +#define IG3_CMPE0_GLCM_PECTXDGCTL_PKTCNT_S 10 +#define IG3_CMPE0_GLCM_PECTXDGCTL_PKTCNT_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PECTXDGCTL_PKTCNT_S) +#define IG3_CMPE0_GLCM_PECTXDGCTL_OP_CODE_S 8 +#define IG3_CMPE0_GLCM_PECTXDGCTL_OP_CODE_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PECTXDGCTL_OP_CODE_S) +#define IG3_CMPE0_GLCM_PECTXDGCTL_ALLOCATE_S 7 +#define IG3_CMPE0_GLCM_PECTXDGCTL_ALLOCATE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECTXDGCTL_ALLOCATE_S) +#define IG3_CMPE0_GLCM_PECTXDGCTL_WRITEBACK_S 6 +#define IG3_CMPE0_GLCM_PECTXDGCTL_WRITEBACK_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECTXDGCTL_WRITEBACK_S) +#define IG3_CMPE0_GLCM_PECTXDGCTL_INVALIDATE_S 5 +#define IG3_CMPE0_GLCM_PECTXDGCTL_INVALIDATE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECTXDGCTL_INVALIDATE_S) +#define IG3_CMPE0_GLCM_PECTXDGCTL_SUB_LINE_S 0 +#define IG3_CMPE0_GLCM_PECTXDGCTL_SUB_LINE_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PECTXDGCTL_SUB_LINE_S) +#define IG3_CMPE0_GLCM_PECTXDGDATA(_i) 0x43020CCC + ((_i) * 4) /* _i=0...3 */ +#define IG3_CMPE0_GLCM_PECTXDGDATA_MAX_INDEX_I 3 +#define IG3_CMPE0_GLCM_PECTXDGDATA_DATA_S 0 +#define IG3_CMPE0_GLCM_PECTXDGDATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLCM_PECTXDGDATA_DATA_S) +#define IG3_CMPE0_GLCM_PECTXDGFN 0x43020CC0 +#define IG3_CMPE0_GLCM_PECTXDGFN_RSVD_S 20 +#define IG3_CMPE0_GLCM_PECTXDGFN_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLCM_PECTXDGFN_RSVD_S) +#define IG3_CMPE0_GLCM_PECTXDGFN_FUNC_TRIPLET_S 0 +#define IG3_CMPE0_GLCM_PECTXDGFN_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_GLCM_PECTXDGFN_FUNC_TRIPLET_S) +#define IG3_CMPE0_GLCM_PECTXDGQP 0x43020CC4 +#define IG3_CMPE0_GLCM_PECTXDGQP_RSVD_S 24 +#define IG3_CMPE0_GLCM_PECTXDGQP_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PECTXDGQP_RSVD_S) +#define IG3_CMPE0_GLCM_PECTXDGQP_QUEUE_NUM_S 0 +#define IG3_CMPE0_GLCM_PECTXDGQP_QUEUE_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE0_GLCM_PECTXDGQP_QUEUE_NUM_S) +#define IG3_CMPE0_GLCM_PECTXDGSTAT 0x43020CDC +#define IG3_CMPE0_GLCM_PECTXDGSTAT_RSVD_S 2 +#define IG3_CMPE0_GLCM_PECTXDGSTAT_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE0_GLCM_PECTXDGSTAT_RSVD_S) +#define IG3_CMPE0_GLCM_PECTXDGSTAT_CTX_MISS_S 1 +#define IG3_CMPE0_GLCM_PECTXDGSTAT_CTX_MISS_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECTXDGSTAT_CTX_MISS_S) +#define IG3_CMPE0_GLCM_PECTXDGSTAT_CTX_DONE_S 0 +#define IG3_CMPE0_GLCM_PECTXDGSTAT_CTX_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PECTXDGSTAT_CTX_DONE_S) +#define IG3_CMPE0_GLCM_PEDATAREQHI 0x43020CB4 +#define IG3_CMPE0_GLCM_PEDATAREQHI_RSVD_S 24 +#define IG3_CMPE0_GLCM_PEDATAREQHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PEDATAREQHI_RSVD_S) +#define IG3_CMPE0_GLCM_PEDATAREQHI_DATAREQHI_S 0 +#define IG3_CMPE0_GLCM_PEDATAREQHI_DATAREQHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE0_GLCM_PEDATAREQHI_DATAREQHI_S) +#define IG3_CMPE0_GLCM_PEDATAREQLO 0x43020CB0 +#define IG3_CMPE0_GLCM_PEDATAREQLO_DATAREQLOW_S 0 +#define IG3_CMPE0_GLCM_PEDATAREQLO_DATAREQLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLCM_PEDATAREQLO_DATAREQLOW_S) +#define IG3_CMPE0_GLCM_PEDATASTALLHI 0x43020CBC +#define IG3_CMPE0_GLCM_PEDATASTALLHI_RSVD_S 24 +#define IG3_CMPE0_GLCM_PEDATASTALLHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PEDATASTALLHI_RSVD_S) +#define IG3_CMPE0_GLCM_PEDATASTALLHI_DATASTALLHI_S 0 +#define IG3_CMPE0_GLCM_PEDATASTALLHI_DATASTALLHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE0_GLCM_PEDATASTALLHI_DATASTALLHI_S) +#define IG3_CMPE0_GLCM_PEDATASTALLLO 0x43020CB8 +#define IG3_CMPE0_GLCM_PEDATASTALLLO_DATASTALLLOW_S 0 +#define IG3_CMPE0_GLCM_PEDATASTALLLO_DATASTALLLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLCM_PEDATASTALLLO_DATASTALLLOW_S) +#define IG3_CMPE0_GLCM_PELOCKTBLADDR 0x43020C9C +#define IG3_CMPE0_GLCM_PELOCKTBLADDR_RSVD_S 5 +#define IG3_CMPE0_GLCM_PELOCKTBLADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_CMPE0_GLCM_PELOCKTBLADDR_RSVD_S) +#define IG3_CMPE0_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S 0 +#define IG3_CMPE0_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S) +#define IG3_CMPE0_GLCM_PELOCKTBLDATA0 0x43020CA0 +#define IG3_CMPE0_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S 31 +#define IG3_CMPE0_GLCM_PELOCKTBLDATA0_GPLOCKSEL_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S) +#define IG3_CMPE0_GLCM_PELOCKTBLDATA0_RSVD_S 24 +#define IG3_CMPE0_GLCM_PELOCKTBLDATA0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PELOCKTBLDATA0_RSVD_S) +#define IG3_CMPE0_GLCM_PELOCKTBLDATA0_QPID_S 0 +#define IG3_CMPE0_GLCM_PELOCKTBLDATA0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE0_GLCM_PELOCKTBLDATA0_QPID_S) +#define IG3_CMPE0_GLCM_PELOCKTBLDATA1 0x43020CA4 +#define IG3_CMPE0_GLCM_PELOCKTBLDATA1_RSVD_S 20 +#define IG3_CMPE0_GLCM_PELOCKTBLDATA1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLCM_PELOCKTBLDATA1_RSVD_S) +#define IG3_CMPE0_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S 0 +#define IG3_CMPE0_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S) +#define IG3_CMPE0_GLCM_PELOCKTBLDATA2 0x43020CA8 +#define IG3_CMPE0_GLCM_PELOCKTBLDATA2_LOCKSEL_S 0 +#define IG3_CMPE0_GLCM_PELOCKTBLDATA2_LOCKSEL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLCM_PELOCKTBLDATA2_LOCKSEL_S) +#define IG3_CMPE0_GLCM_PEPKTCNTADDR 0x43020C94 +#define IG3_CMPE0_GLCM_PEPKTCNTADDR_RSVD_S 9 +#define IG3_CMPE0_GLCM_PEPKTCNTADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE0_GLCM_PEPKTCNTADDR_RSVD_S) +#define IG3_CMPE0_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S 0 +#define IG3_CMPE0_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE0_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S) +#define IG3_CMPE0_GLCM_PEPKTCNTDATA 0x43020C98 +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_RSVD1_S 18 +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE0_GLCM_PEPKTCNTDATA_RSVD1_S) +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_RLRSP_STATE_S 16 +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_RLRSP_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PEPKTCNTDATA_RLRSP_STATE_S) +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_RSVD0_S 14 +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PEPKTCNTDATA_RSVD0_S) +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_RLREQ_STATE_S 12 +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_RLREQ_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PEPKTCNTDATA_RLREQ_STATE_S) +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_PKTCNT_S 1 +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_PKTCNT_M RDMA_MASK3(32, 0x7FF, IG3_CMPE0_GLCM_PEPKTCNTDATA_PKTCNT_S) +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_DONE_S 0 +#define IG3_CMPE0_GLCM_PEPKTCNTDATA_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PEPKTCNTDATA_DONE_S) +#define IG3_CMPE0_GLCM_PESTATSCTL 0x43020CAC +#define IG3_CMPE0_GLCM_PESTATSCTL_RSVD_S 2 +#define IG3_CMPE0_GLCM_PESTATSCTL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE0_GLCM_PESTATSCTL_RSVD_S) +#define IG3_CMPE0_GLCM_PESTATSCTL_ENABLE_S 1 +#define IG3_CMPE0_GLCM_PESTATSCTL_ENABLE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PESTATSCTL_ENABLE_S) +#define IG3_CMPE0_GLCM_PESTATSCTL_CLEAR_S 0 +#define IG3_CMPE0_GLCM_PESTATSCTL_CLEAR_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PESTATSCTL_CLEAR_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG 0x43020D00 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RM_S 16 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RM_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RME_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RME_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS 0x43020D04 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG 0x43020D08 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RM_S 16 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RM_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RME_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RME_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS 0x43020D0C +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG 0x43020D10 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RM_S 16 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RM_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RME_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RME_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS 0x43020D14 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG 0x43020D18 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RM_S 16 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RM_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RME_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RME_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS 0x43020D1C +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG 0x43020D20 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RM_S 16 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RM_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RME_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RME_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS 0x43020D24 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE0_GLCM_PE_CACHESIZE 0x43020CE4 +#define IG3_CMPE0_GLCM_PE_CACHESIZE_RSVD_S 26 +#define IG3_CMPE0_GLCM_PE_CACHESIZE_RSVD_M RDMA_MASK3(32, 0x3F, IG3_CMPE0_GLCM_PE_CACHESIZE_RSVD_S) +#define IG3_CMPE0_GLCM_PE_CACHESIZE_WAYS_S 16 +#define IG3_CMPE0_GLCM_PE_CACHESIZE_WAYS_M RDMA_MASK3(32, 0x3FF, IG3_CMPE0_GLCM_PE_CACHESIZE_WAYS_S) +#define IG3_CMPE0_GLCM_PE_CACHESIZE_SETS_S 12 +#define IG3_CMPE0_GLCM_PE_CACHESIZE_SETS_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLCM_PE_CACHESIZE_SETS_S) +#define IG3_CMPE0_GLCM_PE_CACHESIZE_WORD_SIZE_S 0 +#define IG3_CMPE0_GLCM_PE_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLCM_PE_CACHESIZE_WORD_SIZE_S) +#define IG3_CMPE0_GLCM_PE_DPC_COMP 0x43020CF4 +#define IG3_CMPE0_GLCM_PE_DPC_COMP_RSVD_S 13 +#define IG3_CMPE0_GLCM_PE_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_CMPE0_GLCM_PE_DPC_COMP_RSVD_S) +#define IG3_CMPE0_GLCM_PE_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_CMPE0_GLCM_PE_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_DPC_COMP_COMP_FTYPE_S) +#define IG3_CMPE0_GLCM_PE_DPC_COMP_COMP_FNUM_S 1 +#define IG3_CMPE0_GLCM_PE_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE0_GLCM_PE_DPC_COMP_COMP_FNUM_S) +#define IG3_CMPE0_GLCM_PE_DPC_COMP_COMP_VALID_S 0 +#define IG3_CMPE0_GLCM_PE_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_DPC_COMP_COMP_VALID_S) +#define IG3_CMPE0_GLCM_PE_DPC_REQ 0x43020CF0 +#define IG3_CMPE0_GLCM_PE_DPC_REQ_RSVD_S 12 +#define IG3_CMPE0_GLCM_PE_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_GLCM_PE_DPC_REQ_RSVD_S) +#define IG3_CMPE0_GLCM_PE_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_CMPE0_GLCM_PE_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_DPC_REQ_REQ_FTYPE_S) +#define IG3_CMPE0_GLCM_PE_DPC_REQ_REQ_FNUM_S 0 +#define IG3_CMPE0_GLCM_PE_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE0_GLCM_PE_DPC_REQ_REQ_FNUM_S) +#define IG3_CMPE0_GLCM_PE_E2E_FC 0x43020CF8 +#define IG3_CMPE0_GLCM_PE_E2E_FC_RSVD1_S 22 +#define IG3_CMPE0_GLCM_PE_E2E_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE0_GLCM_PE_E2E_FC_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE0_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE0_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE0_GLCM_PE_E2E_FC_RSVD0_S 9 +#define IG3_CMPE0_GLCM_PE_E2E_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PE_E2E_FC_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE0_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE0_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG 0x43020D28 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RM_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RME_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS 0x43020D2C +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG 0x43020D30 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RM_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RME_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS 0x43020D34 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE0_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE0_GLCM_PE_IF_FC 0x43020CFC +#define IG3_CMPE0_GLCM_PE_IF_FC_RSVD1_S 22 +#define IG3_CMPE0_GLCM_PE_IF_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE0_GLCM_PE_IF_FC_RSVD1_S) +#define IG3_CMPE0_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE0_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE0_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE0_GLCM_PE_IF_FC_RSVD0_S 9 +#define IG3_CMPE0_GLCM_PE_IF_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLCM_PE_IF_FC_RSVD0_S) +#define IG3_CMPE0_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE0_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE0_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE0_GLCM_PE_MAXOSR 0x43020CE0 +#define IG3_CMPE0_GLCM_PE_MAXOSR_RSVD_S 6 +#define IG3_CMPE0_GLCM_PE_MAXOSR_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_CMPE0_GLCM_PE_MAXOSR_RSVD_S) +#define IG3_CMPE0_GLCM_PE_MAXOSR_MAXOSR_S 0 +#define IG3_CMPE0_GLCM_PE_MAXOSR_MAXOSR_M RDMA_MASK3(32, 0x3F, IG3_CMPE0_GLCM_PE_MAXOSR_MAXOSR_S) +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL0 0x43020CE8 +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL0_RSVD_S 24 +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL0_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLCM_PE_RLDDBGCTL0_RSVD_S) +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL0_QPID_S 0 +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE0_GLCM_PE_RLDDBGCTL0_QPID_S) +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL1 0x43020CEC +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL1_RSVD_S 20 +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLCM_PE_RLDDBGCTL1_RSVD_S) +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S 18 +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S) +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S 6 +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S) +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL1_PF_NUM_S 0 +#define IG3_CMPE0_GLCM_PE_RLDDBGCTL1_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_CMPE0_GLCM_PE_RLDDBGCTL1_PF_NUM_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_COUNT 0x43020DB8 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_CMD 0x43020DCC +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_DATA_H 0x43020DD8 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_DATA_L 0x43020DD4 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_PTR 0x43020DD0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_CMD 0x43020DBC +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_DATA_H 0x43020DC8 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_DATA_L 0x43020DC4 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_PTR 0x43020DC0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL 0x43020D80 +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD1_S 25 +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD2_S 17 +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD2_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD3_S 9 +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD3_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_BYPASS_S 8 +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_BYPASS_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD4_S 1 +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_RSVD4_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_COR_ERR 0x43020DE8 +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_UNCOR_ERR 0x43020DE4 +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG 0x43020D8C +#define IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG 0x43020D90 +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG_MODE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLPE_CMPE_DTM_LOG_CFG_MODE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_MASK 0x43020D98 +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_MASK_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_LOG_MASK_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_PATTERN 0x43020D94 +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG 0x43020D84 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS 0x43020D88 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TIMESTAMP 0x43020DB0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER 0x43020DB4 +#define IG3_CMPE0_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG 0x43020DDC +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS 0x43020DE0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE0_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG 0x43020D9C +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_MODE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_CMPE0_GLPE_CMPE_DTM_TRIG_CFG_MODE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_COUNT 0x43020DA8 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_MASK 0x43020DA4 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_PATTERN 0x43020DA0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_TIMESTAMP 0x43020DAC +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE0_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE0_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0(_i) 0x43020C00 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_MAX_INDEX_I 15 +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_RSVD1_S 18 +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE0_PFCM_PE_CRCERRINFO0_RSVD1_S) +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S 16 +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE0_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S) +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S 4 +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE0_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S) +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_RSVD0_S 1 +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_RSVD0_M RDMA_MASK3(32, 0x7, IG3_CMPE0_PFCM_PE_CRCERRINFO0_RSVD0_S) +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S 0 +#define IG3_CMPE0_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_M RDMA_BIT2(32, IG3_CMPE0_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S) +#define IG3_CMPE0_PFCM_PE_CRCERRINFO1(_i) 0x43020C40 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE0_PFCM_PE_CRCERRINFO1_MAX_INDEX_I 15 +#define IG3_CMPE0_PFCM_PE_CRCERRINFO1_RSVD_S 24 +#define IG3_CMPE0_PFCM_PE_CRCERRINFO1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE0_PFCM_PE_CRCERRINFO1_RSVD_S) +#define IG3_CMPE0_PFCM_PE_CRCERRINFO1_Q_NUM_S 0 +#define IG3_CMPE0_PFCM_PE_CRCERRINFO1_Q_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE0_PFCM_PE_CRCERRINFO1_Q_NUM_S) +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG(_i) 0x43402000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG_MAX_INDEX_I 1031 +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG_RSVD2_S 31 +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG_RSVD2_M RDMA_BIT2(32, IG3_PRX1_GLPE_CC_DCQCN1_CFG_RSVD2_S) +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG_DCQCN_F_S 28 +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG_DCQCN_F_M RDMA_MASK3(32, 0x7, IG3_PRX1_GLPE_CC_DCQCN1_CFG_DCQCN_F_S) +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG_RSVD1_S 25 +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_PRX1_GLPE_CC_DCQCN1_CFG_RSVD1_S) +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG_DCQCN_B_S 0 +#define IG3_PRX1_GLPE_CC_DCQCN1_CFG_DCQCN_B_M RDMA_MASK3(32, 0x1FFFFFF, IG3_PRX1_GLPE_CC_DCQCN1_CFG_DCQCN_B_S) +#define IG3_PRX1_GLPE_CC_DCQCN2_CFG(_i) 0x43404000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX1_GLPE_CC_DCQCN2_CFG_MAX_INDEX_I 1031 +#define IG3_PRX1_GLPE_CC_DCQCN2_CFG_RSVD_S 16 +#define IG3_PRX1_GLPE_CC_DCQCN2_CFG_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PRX1_GLPE_CC_DCQCN2_CFG_RSVD_S) +#define IG3_PRX1_GLPE_CC_DCQCN2_CFG_DCQCN_T_S 0 +#define IG3_PRX1_GLPE_CC_DCQCN2_CFG_DCQCN_T_M RDMA_MASK3(32, 0xFFFF, IG3_PRX1_GLPE_CC_DCQCN2_CFG_DCQCN_T_S) +#define IG3_PRX1_GLPE_CC_TIMELY_CFG(_i) 0x43400000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX1_GLPE_CC_TIMELY_CFG_MAX_INDEX_I 1031 +#define IG3_PRX1_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S 16 +#define IG3_PRX1_GLPE_CC_TIMELY_CFG_RAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX1_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S) +#define IG3_PRX1_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S 0 +#define IG3_PRX1_GLPE_CC_TIMELY_CFG_HAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX1_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S) +#define IG3_PRX1_GLPE_PRX_CONFIG 0x43405020 +#define IG3_PRX1_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S 24 +#define IG3_PRX1_GLPE_PRX_CONFIG_REORDER_CNT_MAX_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S) +#define IG3_PRX1_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S 16 +#define IG3_PRX1_GLPE_PRX_CONFIG_REORDER_CNT_MIN_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S) +#define IG3_PRX1_GLPE_PRX_CONFIG_RSVD1_S 12 +#define IG3_PRX1_GLPE_PRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PRX1_GLPE_PRX_CONFIG_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S 8 +#define IG3_PRX1_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_M RDMA_MASK3(32, 0xF, IG3_PRX1_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S) +#define IG3_PRX1_GLPE_PRX_CONFIG_RSVD0_S 5 +#define IG3_PRX1_GLPE_PRX_CONFIG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PRX1_GLPE_PRX_CONFIG_RSVD0_S) +#define IG3_PRX1_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S 4 +#define IG3_PRX1_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S) +#define IG3_PRX1_GLPE_PRX_CONFIG_ONE_HP_TILE_S 3 +#define IG3_PRX1_GLPE_PRX_CONFIG_ONE_HP_TILE_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_CONFIG_ONE_HP_TILE_S) +#define IG3_PRX1_GLPE_PRX_CONFIG_DIS_RREC_S 2 +#define IG3_PRX1_GLPE_PRX_CONFIG_DIS_RREC_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_CONFIG_DIS_RREC_S) +#define IG3_PRX1_GLPE_PRX_CONFIG_DIS_QR_STALL_S 1 +#define IG3_PRX1_GLPE_PRX_CONFIG_DIS_QR_STALL_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_CONFIG_DIS_QR_STALL_S) +#define IG3_PRX1_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S 0 +#define IG3_PRX1_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_COUNT 0x434050B8 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_CMD 0x434050CC +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_DATA_H 0x434050D8 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_DATA_L 0x434050D4 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_PTR 0x434050D0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_CMD 0x434050BC +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_DATA_H 0x434050C8 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_DATA_L 0x434050C4 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_PTR 0x434050C0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX1_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL 0x43405080 +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD2_S) +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD3_S) +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_CONTROL_BYPASS_S) +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PRX1_GLPE_PRX_DTM_CONTROL_RSVD4_S) +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PRX1_GLPE_PRX_DTM_ECC_COR_ERR 0x434050E8 +#define IG3_PRX1_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PRX1_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX1_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PRX1_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX1_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PRX1_GLPE_PRX_DTM_ECC_UNCOR_ERR 0x434050E4 +#define IG3_PRX1_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PRX1_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX1_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PRX1_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX1_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG 0x4340508C +#define IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PRX1_GLPE_PRX_DTM_LOG_CFG 0x43405090 +#define IG3_PRX1_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PRX1_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PRX1_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PRX1_GLPE_PRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PRX1_GLPE_PRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PRX1_GLPE_PRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PRX1_GLPE_PRX_DTM_LOG_CFG_MODE_S) +#define IG3_PRX1_GLPE_PRX_DTM_LOG_MASK 0x43405098 +#define IG3_PRX1_GLPE_PRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_LOG_MASK_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_LOG_PATTERN 0x43405094 +#define IG3_PRX1_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG 0x43405084 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_STS 0x43405088 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TIMESTAMP 0x434050B0 +#define IG3_PRX1_GLPE_PRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER 0x434050B4 +#define IG3_PRX1_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG 0x434050DC +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS 0x434050E0 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG 0x4340509C +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PRX1_GLPE_PRX_DTM_TRIG_CFG_MODE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_COUNT 0x434050A8 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_MASK 0x434050A4 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_PATTERN 0x434050A0 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_TIMESTAMP 0x434050AC +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PRX1_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX1_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_CTL 0x43405024 +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S 12 +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S) +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S 0 +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S) +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA 0x43405028 +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S 31 +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S) +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S 30 +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_M RDMA_BIT2(32, IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S) +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S 24 +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S) +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S 20 +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S) +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S 0 +#define IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX1_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S) +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL 0x43408018 +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S 21 +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_M RDMA_MASK3(32, 0x7FF, IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S) +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S 16 +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S) +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S 13 +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S 8 +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S) +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S 5 +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S) +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S 0 +#define IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX1_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S) +#define IG3_WRX1_GLPE_WRX_CONFIG 0x43408000 +#define IG3_WRX1_GLPE_WRX_CONFIG_RSVD_S 8 +#define IG3_WRX1_GLPE_WRX_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WRX1_GLPE_WRX_CONFIG_RSVD_S) +#define IG3_WRX1_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S 5 +#define IG3_WRX1_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_M RDMA_MASK3(32, 0x7, IG3_WRX1_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S) +#define IG3_WRX1_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S 4 +#define IG3_WRX1_GLPE_WRX_CONFIG_DIS_WQE_CACHE_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S) +#define IG3_WRX1_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S 3 +#define IG3_WRX1_GLPE_WRX_CONFIG_DROP_OOO_IMMED_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S) +#define IG3_WRX1_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S 2 +#define IG3_WRX1_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S) +#define IG3_WRX1_GLPE_WRX_CONFIG_DIS_Q1_AE_S 1 +#define IG3_WRX1_GLPE_WRX_CONFIG_DIS_Q1_AE_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_CONFIG_DIS_Q1_AE_S) +#define IG3_WRX1_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S 0 +#define IG3_WRX1_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S) +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS 0x43408014 +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_RSVD2_S 11 +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_RSVD2_M RDMA_MASK3(32, 0x1FFFFF, IG3_WRX1_GLPE_WRX_DOMAIN_IDS_RSVD2_S) +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S 8 +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX1_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S) +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_RSVD1_S 7 +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_RSVD1_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DOMAIN_IDS_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S 4 +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX1_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S) +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_RSVD0_S 3 +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_RSVD0_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DOMAIN_IDS_RSVD0_S) +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S 0 +#define IG3_WRX1_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX1_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_COUNT 0x434080B8 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_CMD 0x434080CC +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_DATA_H 0x434080D8 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_DATA_L 0x434080D4 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_PTR 0x434080D0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_CMD 0x434080BC +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_DATA_H 0x434080C8 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_DATA_L 0x434080C4 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_PTR 0x434080C0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX1_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL 0x43408080 +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD2_S) +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD3_S) +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_CONTROL_BYPASS_S) +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WRX1_GLPE_WRX_DTM_CONTROL_RSVD4_S) +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WRX1_GLPE_WRX_DTM_ECC_COR_ERR 0x434080E8 +#define IG3_WRX1_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WRX1_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX1_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WRX1_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX1_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WRX1_GLPE_WRX_DTM_ECC_UNCOR_ERR 0x434080E4 +#define IG3_WRX1_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WRX1_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX1_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WRX1_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX1_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG 0x4340808C +#define IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX1_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WRX1_GLPE_WRX_DTM_LOG_CFG 0x43408090 +#define IG3_WRX1_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WRX1_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WRX1_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WRX1_GLPE_WRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WRX1_GLPE_WRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WRX1_GLPE_WRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WRX1_GLPE_WRX_DTM_LOG_CFG_MODE_S) +#define IG3_WRX1_GLPE_WRX_DTM_LOG_MASK 0x43408098 +#define IG3_WRX1_GLPE_WRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_LOG_MASK_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_LOG_PATTERN 0x43408094 +#define IG3_WRX1_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG 0x43408084 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_STS 0x43408088 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TIMESTAMP 0x434080B0 +#define IG3_WRX1_GLPE_WRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER 0x434080B4 +#define IG3_WRX1_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG 0x434080DC +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS 0x434080E0 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG 0x4340809C +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WRX1_GLPE_WRX_DTM_TRIG_CFG_MODE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_COUNT 0x434080A8 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_MASK 0x434080A4 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_PATTERN 0x434080A0 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_TIMESTAMP 0x434080AC +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WRX1_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHHI 0x43408020 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WRX1_GLPE_WRX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX1_GLPE_WRX_FWQPFLUSHHI_QPID_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WRX1_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO 0x4340801C +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_BUSY_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WRX1_GLPE_WRX_FWQPFLUSHLO_PMF_S) +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_CTRL 0x43408004 +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S 7 +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x1FFFFFF, IG3_WRX1_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S) +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S 0 +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_M RDMA_MASK3(32, 0x7F, IG3_WRX1_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S) +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA0 0x43408008 +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA0_DATA_S 0 +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA0_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA0_DATA_S) +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA1 0x4340800C +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA1_DATA_S 0 +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA1_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA1_DATA_S) +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA2 0x43408010 +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA2_DATA_S 0 +#define IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA2_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX1_GLPE_WRX_RQ_CACHE_DATA2_DATA_S) +#define IG3_SQC1_GLPE_SQC_CONFIG 0x43408470 +#define IG3_SQC1_GLPE_SQC_CONFIG_RSVD_S 6 +#define IG3_SQC1_GLPE_SQC_CONFIG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_SQC1_GLPE_SQC_CONFIG_RSVD_S) +#define IG3_SQC1_GLPE_SQC_CONFIG_DBL_INDV_DIS_S 3 +#define IG3_SQC1_GLPE_SQC_CONFIG_DBL_INDV_DIS_M RDMA_MASK3(32, 0x7, IG3_SQC1_GLPE_SQC_CONFIG_DBL_INDV_DIS_S) +#define IG3_SQC1_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S 2 +#define IG3_SQC1_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_SQC1_GLPE_SQC_CONFIG_DBL_DIS_S 1 +#define IG3_SQC1_GLPE_SQC_CONFIG_DBL_DIS_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_CONFIG_DBL_DIS_S) +#define IG3_SQC1_GLPE_SQC_CONFIG_COALESCE_DIS_S 0 +#define IG3_SQC1_GLPE_SQC_CONFIG_COALESCE_DIS_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_CONFIG_COALESCE_DIS_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_COUNT 0x434084B8 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_CMD 0x434084CC +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_DATA_H 0x434084D8 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_DATA_L 0x434084D4 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_PTR 0x434084D0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_CMD 0x434084BC +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_DATA_H 0x434084C8 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_DATA_L 0x434084C4 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_PTR 0x434084C0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC1_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL 0x43408480 +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD1_S 25 +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD2_S 17 +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD2_S) +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD3_S 9 +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD3_S) +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_BYPASS_S 8 +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_CONTROL_BYPASS_S) +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD4_S 1 +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SQC1_GLPE_SQC_DTM_CONTROL_RSVD4_S) +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SQC1_GLPE_SQC_DTM_ECC_COR_ERR 0x434084E8 +#define IG3_SQC1_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC1_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC1_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SQC1_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SQC1_GLPE_SQC_DTM_ECC_UNCOR_ERR 0x434084E4 +#define IG3_SQC1_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC1_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC1_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC1_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG 0x4340848C +#define IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC1_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SQC1_GLPE_SQC_DTM_LOG_CFG 0x43408490 +#define IG3_SQC1_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SQC1_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SQC1_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SQC1_GLPE_SQC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SQC1_GLPE_SQC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SQC1_GLPE_SQC_DTM_LOG_CFG_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_LOG_CFG_MODE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SQC1_GLPE_SQC_DTM_LOG_CFG_MODE_S) +#define IG3_SQC1_GLPE_SQC_DTM_LOG_MASK 0x43408498 +#define IG3_SQC1_GLPE_SQC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_LOG_MASK_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_LOG_PATTERN 0x43408494 +#define IG3_SQC1_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG 0x43408484 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_STS 0x43408488 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_RSVD2_S) +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TIMESTAMP 0x434084B0 +#define IG3_SQC1_GLPE_SQC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_TIMESTAMP_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER 0x434084B4 +#define IG3_SQC1_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG 0x434084DC +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS 0x434084E0 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG 0x4340849C +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SQC1_GLPE_SQC_DTM_TRIG_CFG_MODE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_COUNT 0x434084A8 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_MASK 0x434084A4 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_TRIG_MASK_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_PATTERN 0x434084A0 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_TIMESTAMP 0x434084AC +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SQC1_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC1_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI 0x43408460 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S 26 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S 6 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S 0 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO 0x43408464 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S 31 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S 29 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S 26 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S) +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S 0 +#define IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S) +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI(_i) 0x43408420 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_MAX_INDEX_I 7 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S 26 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S) +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_QPID_S 6 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_QPID_S) +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S 0 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC1_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S) +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO(_i) 0x43408400 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_MAX_INDEX_I 7 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_EN_S 31 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_EN_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_EN_S) +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S 29 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S) +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S 26 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S) +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S 24 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S) +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S 12 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S) +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_PMF_S 0 +#define IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_FWFLUSHDROPLO_PMF_S) +#define IG3_SQC1_GLPE_SQC_FWSYNCRESP(_i) 0x43408468 + ((_i) * 4) /* _i=0...1 */ +#define IG3_SQC1_GLPE_SQC_FWSYNCRESP_MAX_INDEX_I 1 +#define IG3_SQC1_GLPE_SQC_FWSYNCRESP_RSVD_S 18 +#define IG3_SQC1_GLPE_SQC_FWSYNCRESP_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_SQC1_GLPE_SQC_FWSYNCRESP_RSVD_S) +#define IG3_SQC1_GLPE_SQC_FWSYNCRESP_COUNT_S 8 +#define IG3_SQC1_GLPE_SQC_FWSYNCRESP_COUNT_M RDMA_MASK3(32, 0x3FF, IG3_SQC1_GLPE_SQC_FWSYNCRESP_COUNT_S) +#define IG3_SQC1_GLPE_SQC_FWSYNCRESP_TAG_S 0 +#define IG3_SQC1_GLPE_SQC_FWSYNCRESP_TAG_M RDMA_MASK3(32, 0xFF, IG3_SQC1_GLPE_SQC_FWSYNCRESP_TAG_S) +#define IG3_SQC1_GLPE_SQC_XLR_DROP(_i) 0x43408440 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC1_GLPE_SQC_XLR_DROP_MAX_INDEX_I 7 +#define IG3_SQC1_GLPE_SQC_XLR_DROP_EN_S 31 +#define IG3_SQC1_GLPE_SQC_XLR_DROP_EN_M RDMA_BIT2(32, IG3_SQC1_GLPE_SQC_XLR_DROP_EN_S) +#define IG3_SQC1_GLPE_SQC_XLR_DROP_RSVD0_S 12 +#define IG3_SQC1_GLPE_SQC_XLR_DROP_RSVD0_M RDMA_MASK3(32, 0x7FFFF, IG3_SQC1_GLPE_SQC_XLR_DROP_RSVD0_S) +#define IG3_SQC1_GLPE_SQC_XLR_DROP_PMF_S 0 +#define IG3_SQC1_GLPE_SQC_XLR_DROP_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_GLPE_SQC_XLR_DROP_PMF_S) +#define IG3_SQC1_SQC_ECC_COR_ERR 0x43408514 +#define IG3_SQC1_SQC_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC1_SQC_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC1_SQC_ECC_COR_ERR_RSVD_S) +#define IG3_SQC1_SQC_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC1_SQC_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_SQC_ECC_COR_ERR_CNT_S) +#define IG3_SQC1_SQC_ECC_UNCOR_ERR 0x43408510 +#define IG3_SQC1_SQC_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC1_SQC_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC1_SQC_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC1_SQC_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC1_SQC_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC1_SQC_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG 0x43408500 +#define IG3_SQC1_SQC_WRK_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC1_SQC_WRK_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC1_SQC_WRK_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_RSVD3_S 20 +#define IG3_SQC1_SQC_WRK_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC1_SQC_WRK_RAM_CFG_RSVD3_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_RM_S 16 +#define IG3_SQC1_SQC_WRK_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC1_SQC_WRK_RAM_CFG_RM_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_RSVD2_S 14 +#define IG3_SQC1_SQC_WRK_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC1_SQC_WRK_RAM_CFG_RSVD2_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC1_SQC_WRK_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_RME_S 12 +#define IG3_SQC1_SQC_WRK_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_RME_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_RSVD1_S 10 +#define IG3_SQC1_SQC_WRK_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC1_SQC_WRK_RAM_CFG_RSVD1_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC1_SQC_WRK_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_ERR_CNT_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC1_SQC_WRK_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_FIX_CNT_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_RSVD0_S 6 +#define IG3_SQC1_SQC_WRK_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC1_SQC_WRK_RAM_CFG_RSVD0_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC1_SQC_WRK_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_MASK_INT_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC1_SQC_WRK_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC1_SQC_WRK_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_LS_FORCE_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC1_SQC_WRK_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC1_SQC_WRK_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC1_SQC_WRK_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC1_SQC_WRK_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_CFG_ECC_EN_S) +#define IG3_SQC1_SQC_WRK_RAM_STATUS 0x43408504 +#define IG3_SQC1_SQC_WRK_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC1_SQC_WRK_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC1_SQC_WRK_RAM_STATUS_RSVD1_S) +#define IG3_SQC1_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC1_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC1_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC1_SQC_WRK_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC1_SQC_WRK_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC1_SQC_WRK_RAM_STATUS_RSVD0_S) +#define IG3_SQC1_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC1_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC1_SQC_WRK_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC1_SQC_WRK_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC1_SQC_WRK_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC1_SQC_WRK_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC1_SQC_WRK_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC1_SQC_WRK_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC1_SQC_WRK_RAM_STATUS_ECC_ERR_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG 0x43408508 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD3_S 20 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD3_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RM_S 16 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC1_SQC_XBUF_RAM_CFG_RM_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD2_S 14 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD2_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RME_S 12 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_RME_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD1_S 10 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD1_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_ERR_CNT_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_FIX_CNT_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD0_S 6 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC1_SQC_XBUF_RAM_CFG_RSVD0_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_MASK_INT_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_LS_FORCE_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_CFG_ECC_EN_S) +#define IG3_SQC1_SQC_XBUF_RAM_STATUS 0x4340850C +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC1_SQC_XBUF_RAM_STATUS_RSVD1_S) +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC1_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC1_SQC_XBUF_RAM_STATUS_RSVD0_S) +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC1_SQC_XBUF_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC1_SQC_XBUF_RAM_STATUS_ECC_ERR_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DOMAIN_ID 0x43408804 +#define IG3_SFPRX1_GLPE_SFP_RX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPRX1_GLPE_SFP_RX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DOMAIN_ID_RSVD_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPRX1_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_COUNT 0x434088B8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_CMD 0x434088CC +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H 0x434088D8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L 0x434088D4 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_PTR 0x434088D0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_CMD 0x434088BC +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H 0x434088C8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L 0x434088C4 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_PTR 0x434088C0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL 0x43408880 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_COR_ERR 0x434088E8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR 0x434088E4 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG 0x4340888C +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG 0x43408890 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_MASK 0x43408898 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_PATTERN 0x43408894 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG 0x43408884 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS 0x43408888 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TIMESTAMP 0x434088B0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER 0x434088B4 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG 0x434088DC +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS 0x434088E0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG 0x4340889C +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_COUNT 0x434088A8 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_MASK 0x434088A4 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_PATTERN 0x434088A0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP 0x434088AC +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR 0x43408800 +#define IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S 31 +#define IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR_REQ_M RDMA_BIT2(32, IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S) +#define IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S 12 +#define IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S) +#define IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX1_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S) +#define IG3_SFPRX1_GLPE_SFP_RX_PER_MEM 0x43408808 +#define IG3_SFPRX1_GLPE_SFP_RX_PER_MEM_RSVD_S 3 +#define IG3_SFPRX1_GLPE_SFP_RX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX1_GLPE_SFP_RX_PER_MEM_RSVD_S) +#define IG3_SFPRX1_GLPE_SFP_RX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPRX1_GLPE_SFP_RX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPRX1_GLPE_SFP_RX_PER_MEM_PER_TYPE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG 0x43408C08 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS 0x43408C0C +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_COR_ERR 0x43408C34 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR 0x43408C30 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG 0x43408C18 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS 0x43408C1C +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG 0x43408C20 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS 0x43408C24 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG 0x43408C00 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS 0x43408C04 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG 0x43408C28 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS 0x43408C2C +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG 0x43408C10 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS 0x43408C14 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG 0x43408C48 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS 0x43408C4C +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG 0x43408C40 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS 0x43408C44 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG 0x43408C78 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS 0x43408C7C +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG 0x43408C50 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS 0x43408C54 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG 0x43408C58 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS 0x43408C5C +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR 0x43408C84 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR 0x43408C80 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG 0x43408C70 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS 0x43408C74 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG 0x43408C60 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS 0x43408C64 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG 0x43408C68 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS 0x43408C6C +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG 0x43408C38 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS 0x43408C3C +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_COR_ERR 0x43408CCC +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR 0x43408CC8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG 0x43408CD8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS 0x43408CDC +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL 0x43408C90 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA 0x43408C94 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG 0x43408C88 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS 0x43408C8C +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL 0x43408CA0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA 0x43408CA4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG 0x43408C98 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS 0x43408C9C +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL 0x43408CB0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA 0x43408CB4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG 0x43408CA8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS 0x43408CAC +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL 0x43408CC0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA 0x43408CC4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG 0x43408CB8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS 0x43408CBC +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG 0x43408CD0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS 0x43408CD4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_WTX1_GLPE_WTX_1USCOUNT 0x43410010 +#define IG3_WTX1_GLPE_WTX_1USCOUNT_CNT_S 0 +#define IG3_WTX1_GLPE_WTX_1USCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_1USCOUNT_CNT_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0 0x43410120 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1 0x43410124 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2 0x43410128 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG3 0x4341012C +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG4 0x43410130 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG 0x43410020 +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD3_S 24 +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD3_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD3_S) +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD2_S 20 +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD2_S) +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S 16 +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S) +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD1_S 12 +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S 8 +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S) +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD0_S 4 +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD0_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_ARB_CONFIG_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S 0 +#define IG3_WTX1_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0 0x434100F8 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1 0x434100FC +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2 0x43410100 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG3 0x43410104 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG4 0x43410108 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG 0x4341017C +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX 0x43410180 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_CNPCOUNT 0x43410014 +#define IG3_WTX1_GLPE_WTX_CNPCOUNT_CNT_S 0 +#define IG3_WTX1_GLPE_WTX_CNPCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_CNPCOUNT_CNT_S) +#define IG3_WTX1_GLPE_WTX_CONFIG 0x4341000C +#define IG3_WTX1_GLPE_WTX_CONFIG_RSVD1_S 28 +#define IG3_WTX1_GLPE_WTX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_CONFIG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_CONFIG_SQ_HSM_ORD_S 25 +#define IG3_WTX1_GLPE_WTX_CONFIG_SQ_HSM_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_CONFIG_SQ_HSM_ORD_S) +#define IG3_WTX1_GLPE_WTX_CONFIG_SQ_WQE_ORD_S 22 +#define IG3_WTX1_GLPE_WTX_CONFIG_SQ_WQE_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_CONFIG_SQ_WQE_ORD_S) +#define IG3_WTX1_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S 21 +#define IG3_WTX1_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S) +#define IG3_WTX1_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S 20 +#define IG3_WTX1_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_WTX1_GLPE_WTX_CONFIG_RSVD0_S 4 +#define IG3_WTX1_GLPE_WTX_CONFIG_RSVD0_M RDMA_MASK3(32, 0xFFFF, IG3_WTX1_GLPE_WTX_CONFIG_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S 3 +#define IG3_WTX1_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S) +#define IG3_WTX1_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S 2 +#define IG3_WTX1_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S) +#define IG3_WTX1_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S 1 +#define IG3_WTX1_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S) +#define IG3_WTX1_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S 0 +#define IG3_WTX1_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG0 0x4341003C +#define IG3_WTX1_GLPE_WTX_CTCONFIG0_RSVD_S 21 +#define IG3_WTX1_GLPE_WTX_CTCONFIG0_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX1_GLPE_WTX_CTCONFIG0_RSVD_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG0_SCHED_S 0 +#define IG3_WTX1_GLPE_WTX_CTCONFIG0_SCHED_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX1_GLPE_WTX_CTCONFIG0_SCHED_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG1 0x43410040 +#define IG3_WTX1_GLPE_WTX_CTCONFIG1_RSVD_S 21 +#define IG3_WTX1_GLPE_WTX_CTCONFIG1_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX1_GLPE_WTX_CTCONFIG1_RSVD_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG1_VMRL_S 0 +#define IG3_WTX1_GLPE_WTX_CTCONFIG1_VMRL_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX1_GLPE_WTX_CTCONFIG1_VMRL_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG2 0x43410044 +#define IG3_WTX1_GLPE_WTX_CTCONFIG2_RSVD_S 30 +#define IG3_WTX1_GLPE_WTX_CTCONFIG2_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_CTCONFIG2_RSVD_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S 16 +#define IG3_WTX1_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S 0 +#define IG3_WTX1_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX1_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG3 0x43410048 +#define IG3_WTX1_GLPE_WTX_CTCONFIG3_RSVD_S 30 +#define IG3_WTX1_GLPE_WTX_CTCONFIG3_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_CTCONFIG3_RSVD_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S 16 +#define IG3_WTX1_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S 0 +#define IG3_WTX1_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX1_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG4 0x4341004C +#define IG3_WTX1_GLPE_WTX_CTCONFIG4_RSVD_S 30 +#define IG3_WTX1_GLPE_WTX_CTCONFIG4_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_CTCONFIG4_RSVD_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S 16 +#define IG3_WTX1_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S 0 +#define IG3_WTX1_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX1_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG5 0x43410050 +#define IG3_WTX1_GLPE_WTX_CTCONFIG5_RSVD_S 20 +#define IG3_WTX1_GLPE_WTX_CTCONFIG5_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_CTCONFIG5_RSVD_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG5_BMPKT_S 0 +#define IG3_WTX1_GLPE_WTX_CTCONFIG5_BMPKT_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX1_GLPE_WTX_CTCONFIG5_BMPKT_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG6 0x43410054 +#define IG3_WTX1_GLPE_WTX_CTCONFIG6_RSVD_S 13 +#define IG3_WTX1_GLPE_WTX_CTCONFIG6_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_WTX1_GLPE_WTX_CTCONFIG6_RSVD_S) +#define IG3_WTX1_GLPE_WTX_CTCONFIG6_BMHDR_S 0 +#define IG3_WTX1_GLPE_WTX_CTCONFIG6_BMHDR_M RDMA_MASK3(32, 0x1FFF, IG3_WTX1_GLPE_WTX_CTCONFIG6_BMHDR_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_COUNT 0x43410238 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_CMD 0x4341024C +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_DATA_H 0x43410258 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_DATA_L 0x43410254 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_PTR 0x43410250 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_CMD 0x4341023C +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_DATA_H 0x43410248 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_DATA_L 0x43410244 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_PTR 0x43410240 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX1_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL 0x43410200 +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD2_S) +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD3_S) +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_CONTROL_BYPASS_S) +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WTX1_GLPE_WTX_DTM_CONTROL_RSVD4_S) +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WTX1_GLPE_WTX_DTM_ECC_COR_ERR 0x43410268 +#define IG3_WTX1_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX1_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WTX1_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WTX1_GLPE_WTX_DTM_ECC_UNCOR_ERR 0x43410264 +#define IG3_WTX1_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX1_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WTX1_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG 0x4341020C +#define IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WTX1_GLPE_WTX_DTM_LOG_CFG 0x43410210 +#define IG3_WTX1_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WTX1_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WTX1_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WTX1_GLPE_WTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WTX1_GLPE_WTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_DTM_LOG_CFG_MODE_S) +#define IG3_WTX1_GLPE_WTX_DTM_LOG_MASK 0x43410218 +#define IG3_WTX1_GLPE_WTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_LOG_MASK_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_LOG_PATTERN 0x43410214 +#define IG3_WTX1_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG 0x43410204 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_STS 0x43410208 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TIMESTAMP 0x43410230 +#define IG3_WTX1_GLPE_WTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER 0x43410234 +#define IG3_WTX1_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG 0x4341025C +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS 0x43410260 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG 0x4341021C +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_DTM_TRIG_CFG_MODE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_COUNT 0x43410228 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_MASK 0x43410224 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_PATTERN 0x43410220 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_TIMESTAMP 0x4341022C +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WTX1_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG 0x4341014C +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG 0x43410150 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX 0x43410154 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHHI 0x4341005C +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX1_GLPE_WTX_FWQPFLUSHHI_QPID_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO 0x43410058 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_BUSY_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_FWQPFLUSHLO_PMF_S) +#define IG3_WTX1_GLPE_WTX_HOST_READ_CONFIG 0x43410038 +#define IG3_WTX1_GLPE_WTX_HOST_READ_CONFIG_RSVD_S 8 +#define IG3_WTX1_GLPE_WTX_HOST_READ_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_HOST_READ_CONFIG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S 0 +#define IG3_WTX1_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0 0x4341010C +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1 0x43410110 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2 0x43410114 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG3 0x43410118 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG4 0x4341011C +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG 0x4341018C +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX 0x43410190 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG 0x43410194 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX 0x43410198 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG 0x43410184 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX 0x43410188 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0 0x43410090 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1 0x43410094 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2 0x43410098 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG3 0x4341009C +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG4 0x434100A0 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0 0x43410060 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1 0x43410064 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2 0x43410068 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG3 0x4341006C +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG4 0x43410070 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG5 0x43410074 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0 0x43410078 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1 0x4341007C +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2 0x43410080 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG3 0x43410084 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG4 0x43410088 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG5 0x4341008C +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG 0x43410134 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG 0x43410138 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX 0x4341013C +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG 0x43410140 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG 0x43410144 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX 0x43410148 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG 0x43410164 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG 0x43410168 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX 0x4341016C +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG 0x43410158 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG 0x4341015C +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX 0x43410160 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0 0x434100E4 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1 0x434100E8 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2 0x434100EC +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG3 0x434100F0 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG4 0x434100F4 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0 0x434100D0 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1 0x434100D4 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2 0x434100D8 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG3 0x434100DC +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG4 0x434100E0 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED(_i) 0x43410000 + ((_i) * 4) /* _i=0...2 */ +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_MAX_INDEX_I 2 +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S 24 +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD3_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S) +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S 16 +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD2_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S) +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S 8 +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S) +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S 0 +#define IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD0_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0 0x434100A4 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1 0x434100A8 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2 0x434100AC +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG3 0x434100B0 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG4 0x434100B4 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG5 0x434100B8 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG0 0x43410024 +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S 24 +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S) +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S 16 +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S) +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S 8 +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S) +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S) +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG1 0x43410028 +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG1_RSVD_S 8 +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_CONFIG1_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S) +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0 0x4341002C +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S 24 +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S) +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S 16 +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S) +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S 8 +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S) +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S) +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS1 0x43410030 +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S 8 +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0 0x434100BC +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1 0x434100C0 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2 0x434100C4 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG3 0x434100C8 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG4 0x434100CC +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S) +#define IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL 0x43410034 +#define IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S 16 +#define IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S 8 +#define IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S) +#define IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S) +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL 0x43410018 +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S 20 +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S 16 +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_M RDMA_MASK3(32, 0xF, IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S) +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S 10 +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S 8 +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_M RDMA_MASK3(32, 0x3, IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S) +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_M RDMA_MASK3(32, 0xFF, IG3_WTX1_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S) +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_DATA 0x4341001C +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_DATA_DATA_S 0 +#define IG3_WTX1_GLPE_WTX_SPAD_STAT_DATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX1_GLPE_WTX_SPAD_STAT_DATA_DATA_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG 0x43410170 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG 0x43410174 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX 0x43410178 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX1_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_PTX1_GLPE_ARPCONTROL 0x4341400C +#define IG3_PTX1_GLPE_ARPCONTROL_ARP_LOCK_ACK_S 31 +#define IG3_PTX1_GLPE_ARPCONTROL_ARP_LOCK_ACK_M RDMA_BIT2(32, IG3_PTX1_GLPE_ARPCONTROL_ARP_LOCK_ACK_S) +#define IG3_PTX1_GLPE_ARPCONTROL_ARP_LOCK_REQ_S 30 +#define IG3_PTX1_GLPE_ARPCONTROL_ARP_LOCK_REQ_M RDMA_BIT2(32, IG3_PTX1_GLPE_ARPCONTROL_ARP_LOCK_REQ_S) +#define IG3_PTX1_GLPE_ARPCONTROL_RSVD_S 16 +#define IG3_PTX1_GLPE_ARPCONTROL_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_PTX1_GLPE_ARPCONTROL_RSVD_S) +#define IG3_PTX1_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S 0 +#define IG3_PTX1_GLPE_ARPCONTROL_ARP_LOCK_INDEX_M RDMA_MASK3(32, 0xFFFF, IG3_PTX1_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S) +#define IG3_PTX1_GLPE_CRT_CONFIG0 0x43414010 +#define IG3_PTX1_GLPE_CRT_CONFIG0_RSVD_S 25 +#define IG3_PTX1_GLPE_CRT_CONFIG0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_CRT_CONFIG0_RSVD_S) +#define IG3_PTX1_GLPE_CRT_CONFIG0_QP_FC_EN_S 24 +#define IG3_PTX1_GLPE_CRT_CONFIG0_QP_FC_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_CRT_CONFIG0_QP_FC_EN_S) +#define IG3_PTX1_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S 16 +#define IG3_PTX1_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S) +#define IG3_PTX1_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S 8 +#define IG3_PTX1_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S) +#define IG3_PTX1_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S 0 +#define IG3_PTX1_GLPE_CRT_CONFIG0_TX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S) +#define IG3_PTX1_GLPE_CRT_CONFIG1 0x43414014 +#define IG3_PTX1_GLPE_CRT_CONFIG1_RSVD_S 19 +#define IG3_PTX1_GLPE_CRT_CONFIG1_RSVD_M RDMA_MASK3(32, 0x1FFF, IG3_PTX1_GLPE_CRT_CONFIG1_RSVD_S) +#define IG3_PTX1_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S 16 +#define IG3_PTX1_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_M RDMA_MASK3(32, 0x7, IG3_PTX1_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S) +#define IG3_PTX1_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S 8 +#define IG3_PTX1_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S) +#define IG3_PTX1_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S 0 +#define IG3_PTX1_GLPE_CRT_CONFIG1_RX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S) +#define IG3_PTX1_GLPE_MAX_INLINE_DATA 0x43414000 +#define IG3_PTX1_GLPE_MAX_INLINE_DATA_RSVD_S 8 +#define IG3_PTX1_GLPE_MAX_INLINE_DATA_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX1_GLPE_MAX_INLINE_DATA_RSVD_S) +#define IG3_PTX1_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S 0 +#define IG3_PTX1_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S) +#define IG3_PTX1_GLPE_MAX_TCP_ACKS 0x43414004 +#define IG3_PTX1_GLPE_MAX_TCP_ACKS_RSVD_S 8 +#define IG3_PTX1_GLPE_MAX_TCP_ACKS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX1_GLPE_MAX_TCP_ACKS_RSVD_S) +#define IG3_PTX1_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S 0 +#define IG3_PTX1_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0 0x43414018 +#define IG3_PTX1_GLPE_PTX_CONFIG0_RSVD_31_S 31 +#define IG3_PTX1_GLPE_PTX_CONFIG0_RSVD_31_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_RSVD_31_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S 30 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S 29 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S 28 +#define IG3_PTX1_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S 27 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S 26 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S 22 +#define IG3_PTX1_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_M RDMA_MASK3(32, 0xF, IG3_PTX1_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S 21 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S 20 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_RSVD_19_S 19 +#define IG3_PTX1_GLPE_PTX_CONFIG0_RSVD_19_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_RSVD_19_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S 18 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S 17 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S 16 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S 15 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S 14 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_RSVD_13_7_S 7 +#define IG3_PTX1_GLPE_PTX_CONFIG0_RSVD_13_7_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_PTX_CONFIG0_RSVD_13_7_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_UDP_CS_EN_S 6 +#define IG3_PTX1_GLPE_PTX_CONFIG0_UDP_CS_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_UDP_CS_EN_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S 5 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_Q1_PACING_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S 4 +#define IG3_PTX1_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S 3 +#define IG3_PTX1_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S 1 +#define IG3_PTX1_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S) +#define IG3_PTX1_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S 0 +#define IG3_PTX1_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S) +#define IG3_PTX1_GLPE_PTX_CONFIG1 0x4341401C +#define IG3_PTX1_GLPE_PTX_CONFIG1_RSVD_S 24 +#define IG3_PTX1_GLPE_PTX_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_CONFIG1_RSVD_S) +#define IG3_PTX1_GLPE_PTX_CONFIG1_ACKREQ_PACING_S 21 +#define IG3_PTX1_GLPE_PTX_CONFIG1_ACKREQ_PACING_M RDMA_MASK3(32, 0x7, IG3_PTX1_GLPE_PTX_CONFIG1_ACKREQ_PACING_S) +#define IG3_PTX1_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S 16 +#define IG3_PTX1_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_M RDMA_MASK3(32, 0x1F, IG3_PTX1_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S) +#define IG3_PTX1_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S 0 +#define IG3_PTX1_GLPE_PTX_CONFIG1_Q1_PACING_MULT_M RDMA_MASK3(32, 0xFFFF, IG3_PTX1_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S) +#define IG3_PTX1_GLPE_PTX_CONFIG2 0x43414020 +#define IG3_PTX1_GLPE_PTX_CONFIG2_SEND2CPU_S 0 +#define IG3_PTX1_GLPE_PTX_CONFIG2_SEND2CPU_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_CONFIG2_SEND2CPU_S) +#define IG3_PTX1_GLPE_PTX_CRT_XMIT_PTR 0x4341402C +#define IG3_PTX1_GLPE_PTX_CRT_XMIT_PTR_RSVD_S 8 +#define IG3_PTX1_GLPE_PTX_CRT_XMIT_PTR_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX1_GLPE_PTX_CRT_XMIT_PTR_RSVD_S) +#define IG3_PTX1_GLPE_PTX_CRT_XMIT_PTR_COUNT_S 0 +#define IG3_PTX1_GLPE_PTX_CRT_XMIT_PTR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_CRT_XMIT_PTR_COUNT_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_COUNT 0x43414138 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_CMD 0x4341414C +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_DATA_H 0x43414158 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_DATA_L 0x43414154 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_PTR 0x43414150 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_CMD 0x4341413C +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_DATA_H 0x43414148 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_DATA_L 0x43414144 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_PTR 0x43414140 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX1_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL 0x43414100 +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD2_S) +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD3_S) +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_CONTROL_BYPASS_S) +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_PTX_DTM_CONTROL_RSVD4_S) +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PTX1_GLPE_PTX_DTM_ECC_COR_ERR 0x43414168 +#define IG3_PTX1_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PTX1_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX1_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PTX1_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PTX1_GLPE_PTX_DTM_ECC_UNCOR_ERR 0x43414164 +#define IG3_PTX1_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PTX1_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX1_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PTX1_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG 0x4341410C +#define IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PTX1_GLPE_PTX_DTM_LOG_CFG 0x43414110 +#define IG3_PTX1_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PTX1_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PTX1_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PTX1_GLPE_PTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PTX1_GLPE_PTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PTX1_GLPE_PTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_DTM_LOG_CFG_MODE_S) +#define IG3_PTX1_GLPE_PTX_DTM_LOG_MASK 0x43414118 +#define IG3_PTX1_GLPE_PTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_LOG_MASK_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_LOG_PATTERN 0x43414114 +#define IG3_PTX1_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG 0x43414104 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_STS 0x43414108 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TIMESTAMP 0x43414130 +#define IG3_PTX1_GLPE_PTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER 0x43414134 +#define IG3_PTX1_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG 0x4341415C +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS 0x43414160 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG 0x4341411C +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PTX1_GLPE_PTX_DTM_TRIG_CFG_MODE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_COUNT 0x43414128 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_MASK 0x43414124 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_PATTERN 0x43414120 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_TIMESTAMP 0x4341412C +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PTX1_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHHI 0x43414028 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_PTX1_GLPE_PTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX1_GLPE_PTX_FWQPFLUSHHI_QPID_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX1_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO 0x43414024 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_BUSY_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_FWQPFLUSHLO_PMF_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0 0x43414044 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_TAG_S 16 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_TAG_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_MODE_S 11 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_MODE_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1 0x43414048 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_PMF_S 0 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG1_PMF_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2 0x4341404C +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2_QPID_S 6 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2_QPID_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG3 0x43414050 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG4 0x43414054 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0 0x43414058 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_TAG_S 16 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_TAG_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_MODE_S 11 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_MODE_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1 0x4341405C +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_PMF_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG1_PMF_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2 0x43414060 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2_QPID_S 6 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2_QPID_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG3 0x43414064 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG4 0x43414068 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT0 0x43414078 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S 1 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT1 0x4341407C +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT2 0x43414080 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE0 0x4341406C +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S 1 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE1 0x43414070 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S 24 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE2 0x43414074 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S 24 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S) +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S 0 +#define IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX1_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0 0x43414030 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S 16 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S 11 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1 0x43414034 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S 0 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2 0x43414038 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S 6 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG3 0x4341403C +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG4 0x43414040 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX1_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S) +#define IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD 0x43414008 +#define IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S 25 +#define IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S) +#define IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S 24 +#define IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_M RDMA_BIT2(32, IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S) +#define IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S 0 +#define IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX1_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_COUNT 0x434144B8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_CMD 0x434144CC +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_DATA_H 0x434144D8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_DATA_L 0x434144D4 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_PTR 0x434144D0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_CMD 0x434144BC +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_DATA_H 0x434144C8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_DATA_L 0x434144C4 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_PTR 0x434144C0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL 0x43414480 +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD2_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD3_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_BYPASS_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_RSVD4_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_COR_ERR 0x434144E8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX1_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_UNCOR_ERR 0x434144E4 +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX1_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG 0x4341448C +#define IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX1_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG 0x43414490 +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX1_GLPE_SFPT_DTM_LOG_CFG_MODE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_MASK 0x43414498 +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_PATTERN 0x43414494 +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG 0x43414484 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS 0x43414488 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TIMESTAMP 0x434144B0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER 0x434144B4 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG 0x434144DC +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS 0x434144E0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPTX1_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG 0x4341449C +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_COUNT 0x434144A8 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_MASK 0x434144A4 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_PATTERN 0x434144A0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_TIMESTAMP 0x434144AC +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX1_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPTX1_GLPE_SFP_TX_DOMAIN_ID 0x43414400 +#define IG3_SFPTX1_GLPE_SFP_TX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPTX1_GLPE_SFP_TX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX1_GLPE_SFP_TX_DOMAIN_ID_RSVD_S) +#define IG3_SFPTX1_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPTX1_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPTX1_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPTX1_GLPE_SFP_TX_PER_MEM 0x43414404 +#define IG3_SFPTX1_GLPE_SFP_TX_PER_MEM_RSVD_S 3 +#define IG3_SFPTX1_GLPE_SFP_TX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX1_GLPE_SFP_TX_PER_MEM_RSVD_S) +#define IG3_SFPTX1_GLPE_SFP_TX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPTX1_GLPE_SFP_TX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPTX1_GLPE_SFP_TX_PER_MEM_PER_TYPE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG 0x43414800 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS 0x43414804 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG 0x43414810 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS 0x43414814 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_COR_ERR 0x43414834 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR 0x43414830 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG 0x43414818 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS 0x4341481C +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG 0x43414808 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS 0x4341480C +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG 0x43414828 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS 0x4341482C +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG 0x43414820 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS 0x43414824 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG 0x43414840 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS 0x43414844 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG 0x43414848 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS 0x4341484C +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG 0x43414850 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS 0x43414854 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG 0x43414858 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS 0x4341485C +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR 0x4341487C +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR 0x43414878 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG 0x43414860 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS 0x43414864 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG 0x43414868 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS 0x4341486C +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG 0x43414870 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS 0x43414874 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG 0x43414838 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS 0x4341483C +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL 0x434148C8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S 31 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_DATA 0x434148CC +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG 0x434148C0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS 0x434148C4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_COR_ERR 0x434148E4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR 0x434148E0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL 0x434148D8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S 31 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA 0x434148DC +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG 0x434148D0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS 0x434148D4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL 0x43414888 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA 0x4341488C +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG 0x43414880 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS 0x43414884 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL 0x43414898 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA 0x4341489C +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG 0x43414890 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS 0x43414894 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL 0x434148A8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA 0x434148AC +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG 0x434148A0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS 0x434148A4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL 0x434148B8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA 0x434148BC +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG 0x434148B0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS 0x434148B4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE1_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_DRX1_GLPE_DRX_CONFIG 0x43420000 +#define IG3_DRX1_GLPE_DRX_CONFIG_RSVD1_S 3 +#define IG3_DRX1_GLPE_DRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_DRX1_GLPE_DRX_CONFIG_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_CONFIG_CRC_MASK_S 0 +#define IG3_DRX1_GLPE_DRX_CONFIG_CRC_MASK_M RDMA_MASK3(32, 0x7, IG3_DRX1_GLPE_DRX_CONFIG_CRC_MASK_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_COUNT 0x434200B8 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_CMD 0x434200CC +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_DATA_H 0x434200D8 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_DATA_L 0x434200D4 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_PTR 0x434200D0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_CMD 0x434200BC +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_DATA_H 0x434200C8 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_DATA_L 0x434200C4 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_PTR 0x434200C0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX1_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL 0x43420080 +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD2_S) +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD3_S) +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_CONTROL_BYPASS_S) +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_DRX1_GLPE_DRX_DTM_CONTROL_RSVD4_S) +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_DRX1_GLPE_DRX_DTM_ECC_COR_ERR 0x434200E8 +#define IG3_DRX1_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX1_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX1_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_DRX1_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX1_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_DRX1_GLPE_DRX_DTM_ECC_UNCOR_ERR 0x434200E4 +#define IG3_DRX1_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX1_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX1_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX1_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX1_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG 0x4342008C +#define IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX1_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_DRX1_GLPE_DRX_DTM_LOG_CFG 0x43420090 +#define IG3_DRX1_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_DRX1_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_DRX1_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_DRX1_GLPE_DRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_DRX1_GLPE_DRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_DRX1_GLPE_DRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_DRX_DTM_LOG_CFG_MODE_S) +#define IG3_DRX1_GLPE_DRX_DTM_LOG_MASK 0x43420098 +#define IG3_DRX1_GLPE_DRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_LOG_MASK_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_LOG_PATTERN 0x43420094 +#define IG3_DRX1_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG 0x43420084 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_STS 0x43420088 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TIMESTAMP 0x434200B0 +#define IG3_DRX1_GLPE_DRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER 0x434200B4 +#define IG3_DRX1_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG 0x434200DC +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS 0x434200E0 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX1_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG 0x4342009C +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_DRX1_GLPE_DRX_DTM_TRIG_CFG_MODE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_COUNT 0x434200A8 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_MASK 0x434200A4 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_PATTERN 0x434200A0 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_TIMESTAMP 0x434200AC +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_DRX1_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX1_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_DRX1_GLPE_DRX_ECC_COR_ERR 0x43420004 +#define IG3_DRX1_GLPE_DRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX1_GLPE_DRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX1_GLPE_DRX_ECC_COR_ERR_RSVD_S) +#define IG3_DRX1_GLPE_DRX_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX1_GLPE_DRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX1_GLPE_DRX_ECC_COR_ERR_CNT_S) +#define IG3_DRX1_GLPE_DRX_ECC_UNCOR_ERR 0x43420008 +#define IG3_DRX1_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX1_GLPE_DRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX1_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX1_GLPE_DRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX1_GLPE_DRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX1_GLPE_DRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX1_GLPE_PBUF_CFG 0x4342000C +#define IG3_DRX1_GLPE_PBUF_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX1_GLPE_PBUF_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX1_GLPE_PBUF_CFG_ECC_INST_NUM_S) +#define IG3_DRX1_GLPE_PBUF_CFG_RSVD3_S 20 +#define IG3_DRX1_GLPE_PBUF_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX1_GLPE_PBUF_CFG_RSVD3_S) +#define IG3_DRX1_GLPE_PBUF_CFG_RM_S 16 +#define IG3_DRX1_GLPE_PBUF_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX1_GLPE_PBUF_CFG_RM_S) +#define IG3_DRX1_GLPE_PBUF_CFG_RSVD2_S 14 +#define IG3_DRX1_GLPE_PBUF_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_PBUF_CFG_RSVD2_S) +#define IG3_DRX1_GLPE_PBUF_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX1_GLPE_PBUF_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_POWER_GATE_EN_S) +#define IG3_DRX1_GLPE_PBUF_CFG_RME_S 12 +#define IG3_DRX1_GLPE_PBUF_CFG_RME_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_RME_S) +#define IG3_DRX1_GLPE_PBUF_CFG_RSVD1_S 10 +#define IG3_DRX1_GLPE_PBUF_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_PBUF_CFG_RSVD1_S) +#define IG3_DRX1_GLPE_PBUF_CFG_ERR_CNT_S 9 +#define IG3_DRX1_GLPE_PBUF_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_ERR_CNT_S) +#define IG3_DRX1_GLPE_PBUF_CFG_FIX_CNT_S 8 +#define IG3_DRX1_GLPE_PBUF_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_FIX_CNT_S) +#define IG3_DRX1_GLPE_PBUF_CFG_RSVD0_S 6 +#define IG3_DRX1_GLPE_PBUF_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_PBUF_CFG_RSVD0_S) +#define IG3_DRX1_GLPE_PBUF_CFG_MASK_INT_S 5 +#define IG3_DRX1_GLPE_PBUF_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_MASK_INT_S) +#define IG3_DRX1_GLPE_PBUF_CFG_LS_BYPASS_S 4 +#define IG3_DRX1_GLPE_PBUF_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_LS_BYPASS_S) +#define IG3_DRX1_GLPE_PBUF_CFG_LS_FORCE_S 3 +#define IG3_DRX1_GLPE_PBUF_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_LS_FORCE_S) +#define IG3_DRX1_GLPE_PBUF_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX1_GLPE_PBUF_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_ECC_INVERT_2_S) +#define IG3_DRX1_GLPE_PBUF_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX1_GLPE_PBUF_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_ECC_INVERT_1_S) +#define IG3_DRX1_GLPE_PBUF_CFG_ECC_EN_S 0 +#define IG3_DRX1_GLPE_PBUF_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_CFG_ECC_EN_S) +#define IG3_DRX1_GLPE_PBUF_STATUS 0x43420010 +#define IG3_DRX1_GLPE_PBUF_STATUS_RSVD1_S 30 +#define IG3_DRX1_GLPE_PBUF_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX1_GLPE_PBUF_STATUS_RSVD1_S) +#define IG3_DRX1_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX1_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX1_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX1_GLPE_PBUF_STATUS_RSVD0_S 4 +#define IG3_DRX1_GLPE_PBUF_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX1_GLPE_PBUF_STATUS_RSVD0_S) +#define IG3_DRX1_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX1_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX1_GLPE_PBUF_STATUS_INIT_DONE_S 2 +#define IG3_DRX1_GLPE_PBUF_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_STATUS_INIT_DONE_S) +#define IG3_DRX1_GLPE_PBUF_STATUS_ECC_FIX_S 1 +#define IG3_DRX1_GLPE_PBUF_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_STATUS_ECC_FIX_S) +#define IG3_DRX1_GLPE_PBUF_STATUS_ECC_ERR_S 0 +#define IG3_DRX1_GLPE_PBUF_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX1_GLPE_PBUF_STATUS_ECC_ERR_S) +#define IG3_CMPE1_CMPE_ECC_COR_ERR 0x4342053C +#define IG3_CMPE1_CMPE_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE1_CMPE_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_CMPE_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE1_CMPE_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE1_CMPE_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_CMPE_ECC_COR_ERR_CNT_S) +#define IG3_CMPE1_CMPE_ECC_UNCOR_ERR 0x43420538 +#define IG3_CMPE1_CMPE_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE1_CMPE_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_CMPE_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE1_CMPE_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE1_CMPE_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_CMPE_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE1_GLCM_PECLSADDR 0x43420484 +#define IG3_CMPE1_GLCM_PECLSADDR_RSVD_S 9 +#define IG3_CMPE1_GLCM_PECLSADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE1_GLCM_PECLSADDR_RSVD_S) +#define IG3_CMPE1_GLCM_PECLSADDR_CLS_ADDR_S 0 +#define IG3_CMPE1_GLCM_PECLSADDR_CLS_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE1_GLCM_PECLSADDR_CLS_ADDR_S) +#define IG3_CMPE1_GLCM_PECLSDATA0 0x43420488 +#define IG3_CMPE1_GLCM_PECLSDATA0_CLS_DATA_S 0 +#define IG3_CMPE1_GLCM_PECLSDATA0_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLCM_PECLSDATA0_CLS_DATA_S) +#define IG3_CMPE1_GLCM_PECLSDATA1 0x4342048C +#define IG3_CMPE1_GLCM_PECLSDATA1_CLS_DATA_S 0 +#define IG3_CMPE1_GLCM_PECLSDATA1_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLCM_PECLSDATA1_CLS_DATA_S) +#define IG3_CMPE1_GLCM_PECLSDATA2 0x43420490 +#define IG3_CMPE1_GLCM_PECLSDATA2_CLS_DATA_S 0 +#define IG3_CMPE1_GLCM_PECLSDATA2_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLCM_PECLSDATA2_CLS_DATA_S) +#define IG3_CMPE1_GLCM_PECONFIG 0x43420480 +#define IG3_CMPE1_GLCM_PECONFIG_DBGMUX_EN_S 31 +#define IG3_CMPE1_GLCM_PECONFIG_DBGMUX_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_DBGMUX_EN_S) +#define IG3_CMPE1_GLCM_PECONFIG_RSVD13_S 30 +#define IG3_CMPE1_GLCM_PECONFIG_RSVD13_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_RSVD13_S) +#define IG3_CMPE1_GLCM_PECONFIG_DBGMUX_SEL_HI_S 25 +#define IG3_CMPE1_GLCM_PECONFIG_DBGMUX_SEL_HI_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PECONFIG_DBGMUX_SEL_HI_S) +#define IG3_CMPE1_GLCM_PECONFIG_DBGMUX_SEL_LO_S 20 +#define IG3_CMPE1_GLCM_PECONFIG_DBGMUX_SEL_LO_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PECONFIG_DBGMUX_SEL_LO_S) +#define IG3_CMPE1_GLCM_PECONFIG_RSVD10_S 17 +#define IG3_CMPE1_GLCM_PECONFIG_RSVD10_M RDMA_MASK3(32, 0x7, IG3_CMPE1_GLCM_PECONFIG_RSVD10_S) +#define IG3_CMPE1_GLCM_PECONFIG_DBG_WRSEL_S 16 +#define IG3_CMPE1_GLCM_PECONFIG_DBG_WRSEL_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_DBG_WRSEL_S) +#define IG3_CMPE1_GLCM_PECONFIG_DBG_DWSEL_S 14 +#define IG3_CMPE1_GLCM_PECONFIG_DBG_DWSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PECONFIG_DBG_DWSEL_S) +#define IG3_CMPE1_GLCM_PECONFIG_DBG_DPSEL_S 12 +#define IG3_CMPE1_GLCM_PECONFIG_DBG_DPSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PECONFIG_DBG_DPSEL_S) +#define IG3_CMPE1_GLCM_PECONFIG_RSVD6_S 7 +#define IG3_CMPE1_GLCM_PECONFIG_RSVD6_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PECONFIG_RSVD6_S) +#define IG3_CMPE1_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S 6 +#define IG3_CMPE1_GLCM_PECONFIG_DISABLE_CTXT_PACKING_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S) +#define IG3_CMPE1_GLCM_PECONFIG_DISABLE_LSA_S 5 +#define IG3_CMPE1_GLCM_PECONFIG_DISABLE_LSA_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_DISABLE_LSA_S) +#define IG3_CMPE1_GLCM_PECONFIG_ENABLE_CRC_S 4 +#define IG3_CMPE1_GLCM_PECONFIG_ENABLE_CRC_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_ENABLE_CRC_S) +#define IG3_CMPE1_GLCM_PECONFIG_DISABLE_RESCHEDULE_S 3 +#define IG3_CMPE1_GLCM_PECONFIG_DISABLE_RESCHEDULE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_DISABLE_RESCHEDULE_S) +#define IG3_CMPE1_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S 2 +#define IG3_CMPE1_GLCM_PECONFIG_DISABLE_PACKET_COUNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S) +#define IG3_CMPE1_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S 1 +#define IG3_CMPE1_GLCM_PECONFIG_GLOBAL_LOCK_MODE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S) +#define IG3_CMPE1_GLCM_PECONFIG_RSVD1_S 0 +#define IG3_CMPE1_GLCM_PECONFIG_RSVD1_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECONFIG_RSVD1_S) +#define IG3_CMPE1_GLCM_PECTXDGCTL 0x434204C8 +#define IG3_CMPE1_GLCM_PECTXDGCTL_RSVD_S 12 +#define IG3_CMPE1_GLCM_PECTXDGCTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_GLCM_PECTXDGCTL_RSVD_S) +#define IG3_CMPE1_GLCM_PECTXDGCTL_PKTCNT_S 10 +#define IG3_CMPE1_GLCM_PECTXDGCTL_PKTCNT_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PECTXDGCTL_PKTCNT_S) +#define IG3_CMPE1_GLCM_PECTXDGCTL_OP_CODE_S 8 +#define IG3_CMPE1_GLCM_PECTXDGCTL_OP_CODE_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PECTXDGCTL_OP_CODE_S) +#define IG3_CMPE1_GLCM_PECTXDGCTL_ALLOCATE_S 7 +#define IG3_CMPE1_GLCM_PECTXDGCTL_ALLOCATE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECTXDGCTL_ALLOCATE_S) +#define IG3_CMPE1_GLCM_PECTXDGCTL_WRITEBACK_S 6 +#define IG3_CMPE1_GLCM_PECTXDGCTL_WRITEBACK_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECTXDGCTL_WRITEBACK_S) +#define IG3_CMPE1_GLCM_PECTXDGCTL_INVALIDATE_S 5 +#define IG3_CMPE1_GLCM_PECTXDGCTL_INVALIDATE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECTXDGCTL_INVALIDATE_S) +#define IG3_CMPE1_GLCM_PECTXDGCTL_SUB_LINE_S 0 +#define IG3_CMPE1_GLCM_PECTXDGCTL_SUB_LINE_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PECTXDGCTL_SUB_LINE_S) +#define IG3_CMPE1_GLCM_PECTXDGDATA(_i) 0x434204CC + ((_i) * 4) /* _i=0...3 */ +#define IG3_CMPE1_GLCM_PECTXDGDATA_MAX_INDEX_I 3 +#define IG3_CMPE1_GLCM_PECTXDGDATA_DATA_S 0 +#define IG3_CMPE1_GLCM_PECTXDGDATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLCM_PECTXDGDATA_DATA_S) +#define IG3_CMPE1_GLCM_PECTXDGFN 0x434204C0 +#define IG3_CMPE1_GLCM_PECTXDGFN_RSVD_S 20 +#define IG3_CMPE1_GLCM_PECTXDGFN_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLCM_PECTXDGFN_RSVD_S) +#define IG3_CMPE1_GLCM_PECTXDGFN_FUNC_TRIPLET_S 0 +#define IG3_CMPE1_GLCM_PECTXDGFN_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_GLCM_PECTXDGFN_FUNC_TRIPLET_S) +#define IG3_CMPE1_GLCM_PECTXDGQP 0x434204C4 +#define IG3_CMPE1_GLCM_PECTXDGQP_RSVD_S 24 +#define IG3_CMPE1_GLCM_PECTXDGQP_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PECTXDGQP_RSVD_S) +#define IG3_CMPE1_GLCM_PECTXDGQP_QUEUE_NUM_S 0 +#define IG3_CMPE1_GLCM_PECTXDGQP_QUEUE_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE1_GLCM_PECTXDGQP_QUEUE_NUM_S) +#define IG3_CMPE1_GLCM_PECTXDGSTAT 0x434204DC +#define IG3_CMPE1_GLCM_PECTXDGSTAT_RSVD_S 2 +#define IG3_CMPE1_GLCM_PECTXDGSTAT_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE1_GLCM_PECTXDGSTAT_RSVD_S) +#define IG3_CMPE1_GLCM_PECTXDGSTAT_CTX_MISS_S 1 +#define IG3_CMPE1_GLCM_PECTXDGSTAT_CTX_MISS_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECTXDGSTAT_CTX_MISS_S) +#define IG3_CMPE1_GLCM_PECTXDGSTAT_CTX_DONE_S 0 +#define IG3_CMPE1_GLCM_PECTXDGSTAT_CTX_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PECTXDGSTAT_CTX_DONE_S) +#define IG3_CMPE1_GLCM_PEDATAREQHI 0x434204B4 +#define IG3_CMPE1_GLCM_PEDATAREQHI_RSVD_S 24 +#define IG3_CMPE1_GLCM_PEDATAREQHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PEDATAREQHI_RSVD_S) +#define IG3_CMPE1_GLCM_PEDATAREQHI_DATAREQHI_S 0 +#define IG3_CMPE1_GLCM_PEDATAREQHI_DATAREQHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE1_GLCM_PEDATAREQHI_DATAREQHI_S) +#define IG3_CMPE1_GLCM_PEDATAREQLO 0x434204B0 +#define IG3_CMPE1_GLCM_PEDATAREQLO_DATAREQLOW_S 0 +#define IG3_CMPE1_GLCM_PEDATAREQLO_DATAREQLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLCM_PEDATAREQLO_DATAREQLOW_S) +#define IG3_CMPE1_GLCM_PEDATASTALLHI 0x434204BC +#define IG3_CMPE1_GLCM_PEDATASTALLHI_RSVD_S 24 +#define IG3_CMPE1_GLCM_PEDATASTALLHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PEDATASTALLHI_RSVD_S) +#define IG3_CMPE1_GLCM_PEDATASTALLHI_DATASTALLHI_S 0 +#define IG3_CMPE1_GLCM_PEDATASTALLHI_DATASTALLHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE1_GLCM_PEDATASTALLHI_DATASTALLHI_S) +#define IG3_CMPE1_GLCM_PEDATASTALLLO 0x434204B8 +#define IG3_CMPE1_GLCM_PEDATASTALLLO_DATASTALLLOW_S 0 +#define IG3_CMPE1_GLCM_PEDATASTALLLO_DATASTALLLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLCM_PEDATASTALLLO_DATASTALLLOW_S) +#define IG3_CMPE1_GLCM_PELOCKTBLADDR 0x4342049C +#define IG3_CMPE1_GLCM_PELOCKTBLADDR_RSVD_S 5 +#define IG3_CMPE1_GLCM_PELOCKTBLADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_CMPE1_GLCM_PELOCKTBLADDR_RSVD_S) +#define IG3_CMPE1_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S 0 +#define IG3_CMPE1_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S) +#define IG3_CMPE1_GLCM_PELOCKTBLDATA0 0x434204A0 +#define IG3_CMPE1_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S 31 +#define IG3_CMPE1_GLCM_PELOCKTBLDATA0_GPLOCKSEL_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S) +#define IG3_CMPE1_GLCM_PELOCKTBLDATA0_RSVD_S 24 +#define IG3_CMPE1_GLCM_PELOCKTBLDATA0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PELOCKTBLDATA0_RSVD_S) +#define IG3_CMPE1_GLCM_PELOCKTBLDATA0_QPID_S 0 +#define IG3_CMPE1_GLCM_PELOCKTBLDATA0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE1_GLCM_PELOCKTBLDATA0_QPID_S) +#define IG3_CMPE1_GLCM_PELOCKTBLDATA1 0x434204A4 +#define IG3_CMPE1_GLCM_PELOCKTBLDATA1_RSVD_S 20 +#define IG3_CMPE1_GLCM_PELOCKTBLDATA1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLCM_PELOCKTBLDATA1_RSVD_S) +#define IG3_CMPE1_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S 0 +#define IG3_CMPE1_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S) +#define IG3_CMPE1_GLCM_PELOCKTBLDATA2 0x434204A8 +#define IG3_CMPE1_GLCM_PELOCKTBLDATA2_LOCKSEL_S 0 +#define IG3_CMPE1_GLCM_PELOCKTBLDATA2_LOCKSEL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLCM_PELOCKTBLDATA2_LOCKSEL_S) +#define IG3_CMPE1_GLCM_PEPKTCNTADDR 0x43420494 +#define IG3_CMPE1_GLCM_PEPKTCNTADDR_RSVD_S 9 +#define IG3_CMPE1_GLCM_PEPKTCNTADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE1_GLCM_PEPKTCNTADDR_RSVD_S) +#define IG3_CMPE1_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S 0 +#define IG3_CMPE1_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE1_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S) +#define IG3_CMPE1_GLCM_PEPKTCNTDATA 0x43420498 +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_RSVD1_S 18 +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE1_GLCM_PEPKTCNTDATA_RSVD1_S) +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_RLRSP_STATE_S 16 +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_RLRSP_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PEPKTCNTDATA_RLRSP_STATE_S) +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_RSVD0_S 14 +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PEPKTCNTDATA_RSVD0_S) +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_RLREQ_STATE_S 12 +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_RLREQ_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PEPKTCNTDATA_RLREQ_STATE_S) +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_PKTCNT_S 1 +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_PKTCNT_M RDMA_MASK3(32, 0x7FF, IG3_CMPE1_GLCM_PEPKTCNTDATA_PKTCNT_S) +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_DONE_S 0 +#define IG3_CMPE1_GLCM_PEPKTCNTDATA_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PEPKTCNTDATA_DONE_S) +#define IG3_CMPE1_GLCM_PESTATSCTL 0x434204AC +#define IG3_CMPE1_GLCM_PESTATSCTL_RSVD_S 2 +#define IG3_CMPE1_GLCM_PESTATSCTL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE1_GLCM_PESTATSCTL_RSVD_S) +#define IG3_CMPE1_GLCM_PESTATSCTL_ENABLE_S 1 +#define IG3_CMPE1_GLCM_PESTATSCTL_ENABLE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PESTATSCTL_ENABLE_S) +#define IG3_CMPE1_GLCM_PESTATSCTL_CLEAR_S 0 +#define IG3_CMPE1_GLCM_PESTATSCTL_CLEAR_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PESTATSCTL_CLEAR_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG 0x43420500 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RM_S 16 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RM_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RME_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RME_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS 0x43420504 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG 0x43420508 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RM_S 16 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RM_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RME_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RME_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS 0x4342050C +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG 0x43420510 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RM_S 16 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RM_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RME_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RME_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS 0x43420514 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG 0x43420518 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RM_S 16 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RM_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RME_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RME_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS 0x4342051C +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG 0x43420520 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RM_S 16 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RM_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RME_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RME_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS 0x43420524 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE1_GLCM_PE_CACHESIZE 0x434204E4 +#define IG3_CMPE1_GLCM_PE_CACHESIZE_RSVD_S 26 +#define IG3_CMPE1_GLCM_PE_CACHESIZE_RSVD_M RDMA_MASK3(32, 0x3F, IG3_CMPE1_GLCM_PE_CACHESIZE_RSVD_S) +#define IG3_CMPE1_GLCM_PE_CACHESIZE_WAYS_S 16 +#define IG3_CMPE1_GLCM_PE_CACHESIZE_WAYS_M RDMA_MASK3(32, 0x3FF, IG3_CMPE1_GLCM_PE_CACHESIZE_WAYS_S) +#define IG3_CMPE1_GLCM_PE_CACHESIZE_SETS_S 12 +#define IG3_CMPE1_GLCM_PE_CACHESIZE_SETS_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLCM_PE_CACHESIZE_SETS_S) +#define IG3_CMPE1_GLCM_PE_CACHESIZE_WORD_SIZE_S 0 +#define IG3_CMPE1_GLCM_PE_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLCM_PE_CACHESIZE_WORD_SIZE_S) +#define IG3_CMPE1_GLCM_PE_DPC_COMP 0x434204F4 +#define IG3_CMPE1_GLCM_PE_DPC_COMP_RSVD_S 13 +#define IG3_CMPE1_GLCM_PE_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_CMPE1_GLCM_PE_DPC_COMP_RSVD_S) +#define IG3_CMPE1_GLCM_PE_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_CMPE1_GLCM_PE_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_DPC_COMP_COMP_FTYPE_S) +#define IG3_CMPE1_GLCM_PE_DPC_COMP_COMP_FNUM_S 1 +#define IG3_CMPE1_GLCM_PE_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE1_GLCM_PE_DPC_COMP_COMP_FNUM_S) +#define IG3_CMPE1_GLCM_PE_DPC_COMP_COMP_VALID_S 0 +#define IG3_CMPE1_GLCM_PE_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_DPC_COMP_COMP_VALID_S) +#define IG3_CMPE1_GLCM_PE_DPC_REQ 0x434204F0 +#define IG3_CMPE1_GLCM_PE_DPC_REQ_RSVD_S 12 +#define IG3_CMPE1_GLCM_PE_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_GLCM_PE_DPC_REQ_RSVD_S) +#define IG3_CMPE1_GLCM_PE_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_CMPE1_GLCM_PE_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_DPC_REQ_REQ_FTYPE_S) +#define IG3_CMPE1_GLCM_PE_DPC_REQ_REQ_FNUM_S 0 +#define IG3_CMPE1_GLCM_PE_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE1_GLCM_PE_DPC_REQ_REQ_FNUM_S) +#define IG3_CMPE1_GLCM_PE_E2E_FC 0x434204F8 +#define IG3_CMPE1_GLCM_PE_E2E_FC_RSVD1_S 22 +#define IG3_CMPE1_GLCM_PE_E2E_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE1_GLCM_PE_E2E_FC_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE1_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE1_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE1_GLCM_PE_E2E_FC_RSVD0_S 9 +#define IG3_CMPE1_GLCM_PE_E2E_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PE_E2E_FC_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE1_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE1_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG 0x43420528 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RM_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RME_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS 0x4342052C +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG 0x43420530 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RM_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RME_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS 0x43420534 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE1_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE1_GLCM_PE_IF_FC 0x434204FC +#define IG3_CMPE1_GLCM_PE_IF_FC_RSVD1_S 22 +#define IG3_CMPE1_GLCM_PE_IF_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE1_GLCM_PE_IF_FC_RSVD1_S) +#define IG3_CMPE1_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE1_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE1_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE1_GLCM_PE_IF_FC_RSVD0_S 9 +#define IG3_CMPE1_GLCM_PE_IF_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLCM_PE_IF_FC_RSVD0_S) +#define IG3_CMPE1_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE1_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE1_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE1_GLCM_PE_MAXOSR 0x434204E0 +#define IG3_CMPE1_GLCM_PE_MAXOSR_RSVD_S 6 +#define IG3_CMPE1_GLCM_PE_MAXOSR_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_CMPE1_GLCM_PE_MAXOSR_RSVD_S) +#define IG3_CMPE1_GLCM_PE_MAXOSR_MAXOSR_S 0 +#define IG3_CMPE1_GLCM_PE_MAXOSR_MAXOSR_M RDMA_MASK3(32, 0x3F, IG3_CMPE1_GLCM_PE_MAXOSR_MAXOSR_S) +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL0 0x434204E8 +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL0_RSVD_S 24 +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL0_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLCM_PE_RLDDBGCTL0_RSVD_S) +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL0_QPID_S 0 +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE1_GLCM_PE_RLDDBGCTL0_QPID_S) +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL1 0x434204EC +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL1_RSVD_S 20 +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLCM_PE_RLDDBGCTL1_RSVD_S) +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S 18 +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S) +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S 6 +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S) +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL1_PF_NUM_S 0 +#define IG3_CMPE1_GLCM_PE_RLDDBGCTL1_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_CMPE1_GLCM_PE_RLDDBGCTL1_PF_NUM_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_COUNT 0x434205B8 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_CMD 0x434205CC +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_DATA_H 0x434205D8 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_DATA_L 0x434205D4 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_PTR 0x434205D0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_CMD 0x434205BC +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_DATA_H 0x434205C8 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_DATA_L 0x434205C4 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_PTR 0x434205C0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL 0x43420580 +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD1_S 25 +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD2_S 17 +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD2_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD3_S 9 +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD3_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_BYPASS_S 8 +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_BYPASS_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD4_S 1 +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_RSVD4_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_COR_ERR 0x434205E8 +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_UNCOR_ERR 0x434205E4 +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG 0x4342058C +#define IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG 0x43420590 +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG_MODE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLPE_CMPE_DTM_LOG_CFG_MODE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_MASK 0x43420598 +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_MASK_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_LOG_MASK_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_PATTERN 0x43420594 +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG 0x43420584 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS 0x43420588 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TIMESTAMP 0x434205B0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER 0x434205B4 +#define IG3_CMPE1_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG 0x434205DC +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS 0x434205E0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE1_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG 0x4342059C +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_MODE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_CMPE1_GLPE_CMPE_DTM_TRIG_CFG_MODE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_COUNT 0x434205A8 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_MASK 0x434205A4 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_PATTERN 0x434205A0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_TIMESTAMP 0x434205AC +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE1_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE1_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0(_i) 0x43420400 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_MAX_INDEX_I 15 +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_RSVD1_S 18 +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE1_PFCM_PE_CRCERRINFO0_RSVD1_S) +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S 16 +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE1_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S) +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S 4 +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE1_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S) +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_RSVD0_S 1 +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_RSVD0_M RDMA_MASK3(32, 0x7, IG3_CMPE1_PFCM_PE_CRCERRINFO0_RSVD0_S) +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S 0 +#define IG3_CMPE1_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_M RDMA_BIT2(32, IG3_CMPE1_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S) +#define IG3_CMPE1_PFCM_PE_CRCERRINFO1(_i) 0x43420440 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE1_PFCM_PE_CRCERRINFO1_MAX_INDEX_I 15 +#define IG3_CMPE1_PFCM_PE_CRCERRINFO1_RSVD_S 24 +#define IG3_CMPE1_PFCM_PE_CRCERRINFO1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE1_PFCM_PE_CRCERRINFO1_RSVD_S) +#define IG3_CMPE1_PFCM_PE_CRCERRINFO1_Q_NUM_S 0 +#define IG3_CMPE1_PFCM_PE_CRCERRINFO1_Q_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE1_PFCM_PE_CRCERRINFO1_Q_NUM_S) +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG(_i) 0x43802000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG_MAX_INDEX_I 1031 +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG_RSVD2_S 31 +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG_RSVD2_M RDMA_BIT2(32, IG3_PRX2_GLPE_CC_DCQCN1_CFG_RSVD2_S) +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG_DCQCN_F_S 28 +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG_DCQCN_F_M RDMA_MASK3(32, 0x7, IG3_PRX2_GLPE_CC_DCQCN1_CFG_DCQCN_F_S) +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG_RSVD1_S 25 +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_PRX2_GLPE_CC_DCQCN1_CFG_RSVD1_S) +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG_DCQCN_B_S 0 +#define IG3_PRX2_GLPE_CC_DCQCN1_CFG_DCQCN_B_M RDMA_MASK3(32, 0x1FFFFFF, IG3_PRX2_GLPE_CC_DCQCN1_CFG_DCQCN_B_S) +#define IG3_PRX2_GLPE_CC_DCQCN2_CFG(_i) 0x43804000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX2_GLPE_CC_DCQCN2_CFG_MAX_INDEX_I 1031 +#define IG3_PRX2_GLPE_CC_DCQCN2_CFG_RSVD_S 16 +#define IG3_PRX2_GLPE_CC_DCQCN2_CFG_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PRX2_GLPE_CC_DCQCN2_CFG_RSVD_S) +#define IG3_PRX2_GLPE_CC_DCQCN2_CFG_DCQCN_T_S 0 +#define IG3_PRX2_GLPE_CC_DCQCN2_CFG_DCQCN_T_M RDMA_MASK3(32, 0xFFFF, IG3_PRX2_GLPE_CC_DCQCN2_CFG_DCQCN_T_S) +#define IG3_PRX2_GLPE_CC_TIMELY_CFG(_i) 0x43800000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX2_GLPE_CC_TIMELY_CFG_MAX_INDEX_I 1031 +#define IG3_PRX2_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S 16 +#define IG3_PRX2_GLPE_CC_TIMELY_CFG_RAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX2_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S) +#define IG3_PRX2_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S 0 +#define IG3_PRX2_GLPE_CC_TIMELY_CFG_HAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX2_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S) +#define IG3_PRX2_GLPE_PRX_CONFIG 0x43805020 +#define IG3_PRX2_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S 24 +#define IG3_PRX2_GLPE_PRX_CONFIG_REORDER_CNT_MAX_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S) +#define IG3_PRX2_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S 16 +#define IG3_PRX2_GLPE_PRX_CONFIG_REORDER_CNT_MIN_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S) +#define IG3_PRX2_GLPE_PRX_CONFIG_RSVD1_S 12 +#define IG3_PRX2_GLPE_PRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PRX2_GLPE_PRX_CONFIG_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S 8 +#define IG3_PRX2_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_M RDMA_MASK3(32, 0xF, IG3_PRX2_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S) +#define IG3_PRX2_GLPE_PRX_CONFIG_RSVD0_S 5 +#define IG3_PRX2_GLPE_PRX_CONFIG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PRX2_GLPE_PRX_CONFIG_RSVD0_S) +#define IG3_PRX2_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S 4 +#define IG3_PRX2_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S) +#define IG3_PRX2_GLPE_PRX_CONFIG_ONE_HP_TILE_S 3 +#define IG3_PRX2_GLPE_PRX_CONFIG_ONE_HP_TILE_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_CONFIG_ONE_HP_TILE_S) +#define IG3_PRX2_GLPE_PRX_CONFIG_DIS_RREC_S 2 +#define IG3_PRX2_GLPE_PRX_CONFIG_DIS_RREC_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_CONFIG_DIS_RREC_S) +#define IG3_PRX2_GLPE_PRX_CONFIG_DIS_QR_STALL_S 1 +#define IG3_PRX2_GLPE_PRX_CONFIG_DIS_QR_STALL_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_CONFIG_DIS_QR_STALL_S) +#define IG3_PRX2_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S 0 +#define IG3_PRX2_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_COUNT 0x438050B8 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_CMD 0x438050CC +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_DATA_H 0x438050D8 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_DATA_L 0x438050D4 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_PTR 0x438050D0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_CMD 0x438050BC +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_DATA_H 0x438050C8 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_DATA_L 0x438050C4 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_PTR 0x438050C0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX2_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL 0x43805080 +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD2_S) +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD3_S) +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_CONTROL_BYPASS_S) +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PRX2_GLPE_PRX_DTM_CONTROL_RSVD4_S) +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PRX2_GLPE_PRX_DTM_ECC_COR_ERR 0x438050E8 +#define IG3_PRX2_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PRX2_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX2_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PRX2_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX2_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PRX2_GLPE_PRX_DTM_ECC_UNCOR_ERR 0x438050E4 +#define IG3_PRX2_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PRX2_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX2_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PRX2_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX2_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG 0x4380508C +#define IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PRX2_GLPE_PRX_DTM_LOG_CFG 0x43805090 +#define IG3_PRX2_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PRX2_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PRX2_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PRX2_GLPE_PRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PRX2_GLPE_PRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PRX2_GLPE_PRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PRX2_GLPE_PRX_DTM_LOG_CFG_MODE_S) +#define IG3_PRX2_GLPE_PRX_DTM_LOG_MASK 0x43805098 +#define IG3_PRX2_GLPE_PRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_LOG_MASK_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_LOG_PATTERN 0x43805094 +#define IG3_PRX2_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG 0x43805084 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_STS 0x43805088 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TIMESTAMP 0x438050B0 +#define IG3_PRX2_GLPE_PRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER 0x438050B4 +#define IG3_PRX2_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG 0x438050DC +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS 0x438050E0 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG 0x4380509C +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PRX2_GLPE_PRX_DTM_TRIG_CFG_MODE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_COUNT 0x438050A8 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_MASK 0x438050A4 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_PATTERN 0x438050A0 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_TIMESTAMP 0x438050AC +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PRX2_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX2_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_CTL 0x43805024 +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S 12 +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S) +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S 0 +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S) +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA 0x43805028 +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S 31 +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S) +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S 30 +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_M RDMA_BIT2(32, IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S) +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S 24 +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S) +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S 20 +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S) +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S 0 +#define IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX2_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S) +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL 0x43808018 +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S 21 +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_M RDMA_MASK3(32, 0x7FF, IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S) +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S 16 +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S) +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S 13 +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S 8 +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S) +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S 5 +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S) +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S 0 +#define IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX2_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S) +#define IG3_WRX2_GLPE_WRX_CONFIG 0x43808000 +#define IG3_WRX2_GLPE_WRX_CONFIG_RSVD_S 8 +#define IG3_WRX2_GLPE_WRX_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WRX2_GLPE_WRX_CONFIG_RSVD_S) +#define IG3_WRX2_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S 5 +#define IG3_WRX2_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_M RDMA_MASK3(32, 0x7, IG3_WRX2_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S) +#define IG3_WRX2_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S 4 +#define IG3_WRX2_GLPE_WRX_CONFIG_DIS_WQE_CACHE_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S) +#define IG3_WRX2_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S 3 +#define IG3_WRX2_GLPE_WRX_CONFIG_DROP_OOO_IMMED_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S) +#define IG3_WRX2_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S 2 +#define IG3_WRX2_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S) +#define IG3_WRX2_GLPE_WRX_CONFIG_DIS_Q1_AE_S 1 +#define IG3_WRX2_GLPE_WRX_CONFIG_DIS_Q1_AE_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_CONFIG_DIS_Q1_AE_S) +#define IG3_WRX2_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S 0 +#define IG3_WRX2_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S) +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS 0x43808014 +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_RSVD2_S 11 +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_RSVD2_M RDMA_MASK3(32, 0x1FFFFF, IG3_WRX2_GLPE_WRX_DOMAIN_IDS_RSVD2_S) +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S 8 +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX2_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S) +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_RSVD1_S 7 +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_RSVD1_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DOMAIN_IDS_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S 4 +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX2_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S) +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_RSVD0_S 3 +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_RSVD0_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DOMAIN_IDS_RSVD0_S) +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S 0 +#define IG3_WRX2_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX2_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_COUNT 0x438080B8 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_CMD 0x438080CC +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_DATA_H 0x438080D8 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_DATA_L 0x438080D4 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_PTR 0x438080D0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_CMD 0x438080BC +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_DATA_H 0x438080C8 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_DATA_L 0x438080C4 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_PTR 0x438080C0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX2_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL 0x43808080 +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD2_S) +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD3_S) +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_CONTROL_BYPASS_S) +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WRX2_GLPE_WRX_DTM_CONTROL_RSVD4_S) +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WRX2_GLPE_WRX_DTM_ECC_COR_ERR 0x438080E8 +#define IG3_WRX2_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WRX2_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX2_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WRX2_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX2_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WRX2_GLPE_WRX_DTM_ECC_UNCOR_ERR 0x438080E4 +#define IG3_WRX2_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WRX2_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX2_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WRX2_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX2_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG 0x4380808C +#define IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX2_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WRX2_GLPE_WRX_DTM_LOG_CFG 0x43808090 +#define IG3_WRX2_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WRX2_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WRX2_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WRX2_GLPE_WRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WRX2_GLPE_WRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WRX2_GLPE_WRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WRX2_GLPE_WRX_DTM_LOG_CFG_MODE_S) +#define IG3_WRX2_GLPE_WRX_DTM_LOG_MASK 0x43808098 +#define IG3_WRX2_GLPE_WRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_LOG_MASK_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_LOG_PATTERN 0x43808094 +#define IG3_WRX2_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG 0x43808084 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_STS 0x43808088 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TIMESTAMP 0x438080B0 +#define IG3_WRX2_GLPE_WRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER 0x438080B4 +#define IG3_WRX2_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG 0x438080DC +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS 0x438080E0 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG 0x4380809C +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WRX2_GLPE_WRX_DTM_TRIG_CFG_MODE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_COUNT 0x438080A8 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_MASK 0x438080A4 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_PATTERN 0x438080A0 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_TIMESTAMP 0x438080AC +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WRX2_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHHI 0x43808020 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WRX2_GLPE_WRX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX2_GLPE_WRX_FWQPFLUSHHI_QPID_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WRX2_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO 0x4380801C +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_BUSY_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WRX2_GLPE_WRX_FWQPFLUSHLO_PMF_S) +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_CTRL 0x43808004 +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S 7 +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x1FFFFFF, IG3_WRX2_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S) +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S 0 +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_M RDMA_MASK3(32, 0x7F, IG3_WRX2_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S) +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA0 0x43808008 +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA0_DATA_S 0 +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA0_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA0_DATA_S) +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA1 0x4380800C +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA1_DATA_S 0 +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA1_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA1_DATA_S) +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA2 0x43808010 +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA2_DATA_S 0 +#define IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA2_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX2_GLPE_WRX_RQ_CACHE_DATA2_DATA_S) +#define IG3_SQC2_GLPE_SQC_CONFIG 0x43808470 +#define IG3_SQC2_GLPE_SQC_CONFIG_RSVD_S 6 +#define IG3_SQC2_GLPE_SQC_CONFIG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_SQC2_GLPE_SQC_CONFIG_RSVD_S) +#define IG3_SQC2_GLPE_SQC_CONFIG_DBL_INDV_DIS_S 3 +#define IG3_SQC2_GLPE_SQC_CONFIG_DBL_INDV_DIS_M RDMA_MASK3(32, 0x7, IG3_SQC2_GLPE_SQC_CONFIG_DBL_INDV_DIS_S) +#define IG3_SQC2_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S 2 +#define IG3_SQC2_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_SQC2_GLPE_SQC_CONFIG_DBL_DIS_S 1 +#define IG3_SQC2_GLPE_SQC_CONFIG_DBL_DIS_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_CONFIG_DBL_DIS_S) +#define IG3_SQC2_GLPE_SQC_CONFIG_COALESCE_DIS_S 0 +#define IG3_SQC2_GLPE_SQC_CONFIG_COALESCE_DIS_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_CONFIG_COALESCE_DIS_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_COUNT 0x438084B8 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_CMD 0x438084CC +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_DATA_H 0x438084D8 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_DATA_L 0x438084D4 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_PTR 0x438084D0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_CMD 0x438084BC +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_DATA_H 0x438084C8 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_DATA_L 0x438084C4 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_PTR 0x438084C0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC2_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL 0x43808480 +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD1_S 25 +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD2_S 17 +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD2_S) +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD3_S 9 +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD3_S) +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_BYPASS_S 8 +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_CONTROL_BYPASS_S) +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD4_S 1 +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SQC2_GLPE_SQC_DTM_CONTROL_RSVD4_S) +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SQC2_GLPE_SQC_DTM_ECC_COR_ERR 0x438084E8 +#define IG3_SQC2_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC2_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC2_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SQC2_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SQC2_GLPE_SQC_DTM_ECC_UNCOR_ERR 0x438084E4 +#define IG3_SQC2_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC2_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC2_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC2_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG 0x4380848C +#define IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC2_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SQC2_GLPE_SQC_DTM_LOG_CFG 0x43808490 +#define IG3_SQC2_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SQC2_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SQC2_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SQC2_GLPE_SQC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SQC2_GLPE_SQC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SQC2_GLPE_SQC_DTM_LOG_CFG_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_LOG_CFG_MODE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SQC2_GLPE_SQC_DTM_LOG_CFG_MODE_S) +#define IG3_SQC2_GLPE_SQC_DTM_LOG_MASK 0x43808498 +#define IG3_SQC2_GLPE_SQC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_LOG_MASK_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_LOG_PATTERN 0x43808494 +#define IG3_SQC2_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG 0x43808484 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_STS 0x43808488 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_RSVD2_S) +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TIMESTAMP 0x438084B0 +#define IG3_SQC2_GLPE_SQC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_TIMESTAMP_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER 0x438084B4 +#define IG3_SQC2_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG 0x438084DC +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS 0x438084E0 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG 0x4380849C +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SQC2_GLPE_SQC_DTM_TRIG_CFG_MODE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_COUNT 0x438084A8 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_MASK 0x438084A4 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_TRIG_MASK_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_PATTERN 0x438084A0 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_TIMESTAMP 0x438084AC +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SQC2_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC2_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI 0x43808460 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S 26 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S 6 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S 0 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO 0x43808464 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S 31 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S 29 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S 26 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S) +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S 0 +#define IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S) +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI(_i) 0x43808420 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_MAX_INDEX_I 7 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S 26 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S) +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_QPID_S 6 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_QPID_S) +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S 0 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC2_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S) +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO(_i) 0x43808400 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_MAX_INDEX_I 7 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_EN_S 31 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_EN_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_EN_S) +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S 29 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S) +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S 26 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S) +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S 24 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S) +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S 12 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S) +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_PMF_S 0 +#define IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_FWFLUSHDROPLO_PMF_S) +#define IG3_SQC2_GLPE_SQC_FWSYNCRESP(_i) 0x43808468 + ((_i) * 4) /* _i=0...1 */ +#define IG3_SQC2_GLPE_SQC_FWSYNCRESP_MAX_INDEX_I 1 +#define IG3_SQC2_GLPE_SQC_FWSYNCRESP_RSVD_S 18 +#define IG3_SQC2_GLPE_SQC_FWSYNCRESP_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_SQC2_GLPE_SQC_FWSYNCRESP_RSVD_S) +#define IG3_SQC2_GLPE_SQC_FWSYNCRESP_COUNT_S 8 +#define IG3_SQC2_GLPE_SQC_FWSYNCRESP_COUNT_M RDMA_MASK3(32, 0x3FF, IG3_SQC2_GLPE_SQC_FWSYNCRESP_COUNT_S) +#define IG3_SQC2_GLPE_SQC_FWSYNCRESP_TAG_S 0 +#define IG3_SQC2_GLPE_SQC_FWSYNCRESP_TAG_M RDMA_MASK3(32, 0xFF, IG3_SQC2_GLPE_SQC_FWSYNCRESP_TAG_S) +#define IG3_SQC2_GLPE_SQC_XLR_DROP(_i) 0x43808440 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC2_GLPE_SQC_XLR_DROP_MAX_INDEX_I 7 +#define IG3_SQC2_GLPE_SQC_XLR_DROP_EN_S 31 +#define IG3_SQC2_GLPE_SQC_XLR_DROP_EN_M RDMA_BIT2(32, IG3_SQC2_GLPE_SQC_XLR_DROP_EN_S) +#define IG3_SQC2_GLPE_SQC_XLR_DROP_RSVD0_S 12 +#define IG3_SQC2_GLPE_SQC_XLR_DROP_RSVD0_M RDMA_MASK3(32, 0x7FFFF, IG3_SQC2_GLPE_SQC_XLR_DROP_RSVD0_S) +#define IG3_SQC2_GLPE_SQC_XLR_DROP_PMF_S 0 +#define IG3_SQC2_GLPE_SQC_XLR_DROP_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_GLPE_SQC_XLR_DROP_PMF_S) +#define IG3_SQC2_SQC_ECC_COR_ERR 0x43808514 +#define IG3_SQC2_SQC_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC2_SQC_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC2_SQC_ECC_COR_ERR_RSVD_S) +#define IG3_SQC2_SQC_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC2_SQC_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_SQC_ECC_COR_ERR_CNT_S) +#define IG3_SQC2_SQC_ECC_UNCOR_ERR 0x43808510 +#define IG3_SQC2_SQC_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC2_SQC_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC2_SQC_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC2_SQC_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC2_SQC_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC2_SQC_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG 0x43808500 +#define IG3_SQC2_SQC_WRK_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC2_SQC_WRK_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC2_SQC_WRK_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_RSVD3_S 20 +#define IG3_SQC2_SQC_WRK_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC2_SQC_WRK_RAM_CFG_RSVD3_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_RM_S 16 +#define IG3_SQC2_SQC_WRK_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC2_SQC_WRK_RAM_CFG_RM_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_RSVD2_S 14 +#define IG3_SQC2_SQC_WRK_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC2_SQC_WRK_RAM_CFG_RSVD2_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC2_SQC_WRK_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_RME_S 12 +#define IG3_SQC2_SQC_WRK_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_RME_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_RSVD1_S 10 +#define IG3_SQC2_SQC_WRK_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC2_SQC_WRK_RAM_CFG_RSVD1_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC2_SQC_WRK_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_ERR_CNT_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC2_SQC_WRK_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_FIX_CNT_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_RSVD0_S 6 +#define IG3_SQC2_SQC_WRK_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC2_SQC_WRK_RAM_CFG_RSVD0_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC2_SQC_WRK_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_MASK_INT_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC2_SQC_WRK_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC2_SQC_WRK_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_LS_FORCE_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC2_SQC_WRK_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC2_SQC_WRK_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC2_SQC_WRK_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC2_SQC_WRK_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_CFG_ECC_EN_S) +#define IG3_SQC2_SQC_WRK_RAM_STATUS 0x43808504 +#define IG3_SQC2_SQC_WRK_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC2_SQC_WRK_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC2_SQC_WRK_RAM_STATUS_RSVD1_S) +#define IG3_SQC2_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC2_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC2_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC2_SQC_WRK_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC2_SQC_WRK_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC2_SQC_WRK_RAM_STATUS_RSVD0_S) +#define IG3_SQC2_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC2_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC2_SQC_WRK_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC2_SQC_WRK_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC2_SQC_WRK_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC2_SQC_WRK_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC2_SQC_WRK_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC2_SQC_WRK_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC2_SQC_WRK_RAM_STATUS_ECC_ERR_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG 0x43808508 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD3_S 20 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD3_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RM_S 16 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC2_SQC_XBUF_RAM_CFG_RM_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD2_S 14 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD2_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RME_S 12 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_RME_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD1_S 10 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD1_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_ERR_CNT_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_FIX_CNT_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD0_S 6 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC2_SQC_XBUF_RAM_CFG_RSVD0_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_MASK_INT_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_LS_FORCE_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_CFG_ECC_EN_S) +#define IG3_SQC2_SQC_XBUF_RAM_STATUS 0x4380850C +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC2_SQC_XBUF_RAM_STATUS_RSVD1_S) +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC2_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC2_SQC_XBUF_RAM_STATUS_RSVD0_S) +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC2_SQC_XBUF_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC2_SQC_XBUF_RAM_STATUS_ECC_ERR_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DOMAIN_ID 0x43808804 +#define IG3_SFPRX2_GLPE_SFP_RX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPRX2_GLPE_SFP_RX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DOMAIN_ID_RSVD_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPRX2_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_COUNT 0x438088B8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_CMD 0x438088CC +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H 0x438088D8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L 0x438088D4 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_PTR 0x438088D0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_CMD 0x438088BC +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H 0x438088C8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L 0x438088C4 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_PTR 0x438088C0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL 0x43808880 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_COR_ERR 0x438088E8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR 0x438088E4 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG 0x4380888C +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG 0x43808890 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_MASK 0x43808898 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_PATTERN 0x43808894 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG 0x43808884 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS 0x43808888 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TIMESTAMP 0x438088B0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER 0x438088B4 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG 0x438088DC +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS 0x438088E0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG 0x4380889C +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_COUNT 0x438088A8 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_MASK 0x438088A4 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_PATTERN 0x438088A0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP 0x438088AC +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR 0x43808800 +#define IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S 31 +#define IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR_REQ_M RDMA_BIT2(32, IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S) +#define IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S 12 +#define IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S) +#define IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX2_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S) +#define IG3_SFPRX2_GLPE_SFP_RX_PER_MEM 0x43808808 +#define IG3_SFPRX2_GLPE_SFP_RX_PER_MEM_RSVD_S 3 +#define IG3_SFPRX2_GLPE_SFP_RX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX2_GLPE_SFP_RX_PER_MEM_RSVD_S) +#define IG3_SFPRX2_GLPE_SFP_RX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPRX2_GLPE_SFP_RX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPRX2_GLPE_SFP_RX_PER_MEM_PER_TYPE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG 0x43808C08 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS 0x43808C0C +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_COR_ERR 0x43808C34 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR 0x43808C30 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG 0x43808C18 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS 0x43808C1C +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG 0x43808C20 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS 0x43808C24 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG 0x43808C00 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS 0x43808C04 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG 0x43808C28 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS 0x43808C2C +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG 0x43808C10 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS 0x43808C14 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG 0x43808C48 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS 0x43808C4C +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG 0x43808C40 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS 0x43808C44 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG 0x43808C78 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS 0x43808C7C +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG 0x43808C50 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS 0x43808C54 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG 0x43808C58 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS 0x43808C5C +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR 0x43808C84 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR 0x43808C80 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG 0x43808C70 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS 0x43808C74 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG 0x43808C60 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS 0x43808C64 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG 0x43808C68 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS 0x43808C6C +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG 0x43808C38 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS 0x43808C3C +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_COR_ERR 0x43808CCC +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR 0x43808CC8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG 0x43808CD8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS 0x43808CDC +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL 0x43808C90 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA 0x43808C94 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG 0x43808C88 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS 0x43808C8C +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL 0x43808CA0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA 0x43808CA4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG 0x43808C98 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS 0x43808C9C +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL 0x43808CB0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA 0x43808CB4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG 0x43808CA8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS 0x43808CAC +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL 0x43808CC0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA 0x43808CC4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG 0x43808CB8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS 0x43808CBC +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG 0x43808CD0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS 0x43808CD4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_WTX2_GLPE_WTX_1USCOUNT 0x43810010 +#define IG3_WTX2_GLPE_WTX_1USCOUNT_CNT_S 0 +#define IG3_WTX2_GLPE_WTX_1USCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_1USCOUNT_CNT_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0 0x43810120 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1 0x43810124 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2 0x43810128 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG3 0x4381012C +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG4 0x43810130 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG 0x43810020 +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD3_S 24 +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD3_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD3_S) +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD2_S 20 +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD2_S) +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S 16 +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S) +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD1_S 12 +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S 8 +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S) +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD0_S 4 +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD0_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_ARB_CONFIG_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S 0 +#define IG3_WTX2_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0 0x438100F8 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1 0x438100FC +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2 0x43810100 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG3 0x43810104 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG4 0x43810108 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG 0x4381017C +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX 0x43810180 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_CNPCOUNT 0x43810014 +#define IG3_WTX2_GLPE_WTX_CNPCOUNT_CNT_S 0 +#define IG3_WTX2_GLPE_WTX_CNPCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_CNPCOUNT_CNT_S) +#define IG3_WTX2_GLPE_WTX_CONFIG 0x4381000C +#define IG3_WTX2_GLPE_WTX_CONFIG_RSVD1_S 28 +#define IG3_WTX2_GLPE_WTX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_CONFIG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_CONFIG_SQ_HSM_ORD_S 25 +#define IG3_WTX2_GLPE_WTX_CONFIG_SQ_HSM_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_CONFIG_SQ_HSM_ORD_S) +#define IG3_WTX2_GLPE_WTX_CONFIG_SQ_WQE_ORD_S 22 +#define IG3_WTX2_GLPE_WTX_CONFIG_SQ_WQE_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_CONFIG_SQ_WQE_ORD_S) +#define IG3_WTX2_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S 21 +#define IG3_WTX2_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S) +#define IG3_WTX2_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S 20 +#define IG3_WTX2_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_WTX2_GLPE_WTX_CONFIG_RSVD0_S 4 +#define IG3_WTX2_GLPE_WTX_CONFIG_RSVD0_M RDMA_MASK3(32, 0xFFFF, IG3_WTX2_GLPE_WTX_CONFIG_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S 3 +#define IG3_WTX2_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S) +#define IG3_WTX2_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S 2 +#define IG3_WTX2_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S) +#define IG3_WTX2_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S 1 +#define IG3_WTX2_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S) +#define IG3_WTX2_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S 0 +#define IG3_WTX2_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG0 0x4381003C +#define IG3_WTX2_GLPE_WTX_CTCONFIG0_RSVD_S 21 +#define IG3_WTX2_GLPE_WTX_CTCONFIG0_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX2_GLPE_WTX_CTCONFIG0_RSVD_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG0_SCHED_S 0 +#define IG3_WTX2_GLPE_WTX_CTCONFIG0_SCHED_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX2_GLPE_WTX_CTCONFIG0_SCHED_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG1 0x43810040 +#define IG3_WTX2_GLPE_WTX_CTCONFIG1_RSVD_S 21 +#define IG3_WTX2_GLPE_WTX_CTCONFIG1_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX2_GLPE_WTX_CTCONFIG1_RSVD_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG1_VMRL_S 0 +#define IG3_WTX2_GLPE_WTX_CTCONFIG1_VMRL_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX2_GLPE_WTX_CTCONFIG1_VMRL_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG2 0x43810044 +#define IG3_WTX2_GLPE_WTX_CTCONFIG2_RSVD_S 30 +#define IG3_WTX2_GLPE_WTX_CTCONFIG2_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_CTCONFIG2_RSVD_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S 16 +#define IG3_WTX2_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S 0 +#define IG3_WTX2_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX2_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG3 0x43810048 +#define IG3_WTX2_GLPE_WTX_CTCONFIG3_RSVD_S 30 +#define IG3_WTX2_GLPE_WTX_CTCONFIG3_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_CTCONFIG3_RSVD_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S 16 +#define IG3_WTX2_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S 0 +#define IG3_WTX2_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX2_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG4 0x4381004C +#define IG3_WTX2_GLPE_WTX_CTCONFIG4_RSVD_S 30 +#define IG3_WTX2_GLPE_WTX_CTCONFIG4_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_CTCONFIG4_RSVD_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S 16 +#define IG3_WTX2_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S 0 +#define IG3_WTX2_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX2_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG5 0x43810050 +#define IG3_WTX2_GLPE_WTX_CTCONFIG5_RSVD_S 20 +#define IG3_WTX2_GLPE_WTX_CTCONFIG5_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_CTCONFIG5_RSVD_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG5_BMPKT_S 0 +#define IG3_WTX2_GLPE_WTX_CTCONFIG5_BMPKT_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX2_GLPE_WTX_CTCONFIG5_BMPKT_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG6 0x43810054 +#define IG3_WTX2_GLPE_WTX_CTCONFIG6_RSVD_S 13 +#define IG3_WTX2_GLPE_WTX_CTCONFIG6_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_WTX2_GLPE_WTX_CTCONFIG6_RSVD_S) +#define IG3_WTX2_GLPE_WTX_CTCONFIG6_BMHDR_S 0 +#define IG3_WTX2_GLPE_WTX_CTCONFIG6_BMHDR_M RDMA_MASK3(32, 0x1FFF, IG3_WTX2_GLPE_WTX_CTCONFIG6_BMHDR_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_COUNT 0x43810238 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_CMD 0x4381024C +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_DATA_H 0x43810258 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_DATA_L 0x43810254 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_PTR 0x43810250 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_CMD 0x4381023C +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_DATA_H 0x43810248 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_DATA_L 0x43810244 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_PTR 0x43810240 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX2_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL 0x43810200 +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD2_S) +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD3_S) +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_CONTROL_BYPASS_S) +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WTX2_GLPE_WTX_DTM_CONTROL_RSVD4_S) +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WTX2_GLPE_WTX_DTM_ECC_COR_ERR 0x43810268 +#define IG3_WTX2_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX2_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WTX2_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WTX2_GLPE_WTX_DTM_ECC_UNCOR_ERR 0x43810264 +#define IG3_WTX2_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX2_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WTX2_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG 0x4381020C +#define IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WTX2_GLPE_WTX_DTM_LOG_CFG 0x43810210 +#define IG3_WTX2_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WTX2_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WTX2_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WTX2_GLPE_WTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WTX2_GLPE_WTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_DTM_LOG_CFG_MODE_S) +#define IG3_WTX2_GLPE_WTX_DTM_LOG_MASK 0x43810218 +#define IG3_WTX2_GLPE_WTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_LOG_MASK_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_LOG_PATTERN 0x43810214 +#define IG3_WTX2_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG 0x43810204 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_STS 0x43810208 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TIMESTAMP 0x43810230 +#define IG3_WTX2_GLPE_WTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER 0x43810234 +#define IG3_WTX2_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG 0x4381025C +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS 0x43810260 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG 0x4381021C +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_DTM_TRIG_CFG_MODE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_COUNT 0x43810228 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_MASK 0x43810224 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_PATTERN 0x43810220 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_TIMESTAMP 0x4381022C +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WTX2_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG 0x4381014C +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG 0x43810150 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX 0x43810154 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHHI 0x4381005C +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX2_GLPE_WTX_FWQPFLUSHHI_QPID_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO 0x43810058 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_BUSY_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_FWQPFLUSHLO_PMF_S) +#define IG3_WTX2_GLPE_WTX_HOST_READ_CONFIG 0x43810038 +#define IG3_WTX2_GLPE_WTX_HOST_READ_CONFIG_RSVD_S 8 +#define IG3_WTX2_GLPE_WTX_HOST_READ_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_HOST_READ_CONFIG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S 0 +#define IG3_WTX2_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0 0x4381010C +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1 0x43810110 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2 0x43810114 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG3 0x43810118 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG4 0x4381011C +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG 0x4381018C +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX 0x43810190 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG 0x43810194 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX 0x43810198 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG 0x43810184 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX 0x43810188 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0 0x43810090 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1 0x43810094 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2 0x43810098 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG3 0x4381009C +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG4 0x438100A0 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0 0x43810060 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1 0x43810064 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2 0x43810068 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG3 0x4381006C +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG4 0x43810070 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG5 0x43810074 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0 0x43810078 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1 0x4381007C +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2 0x43810080 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG3 0x43810084 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG4 0x43810088 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG5 0x4381008C +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG 0x43810134 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG 0x43810138 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX 0x4381013C +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG 0x43810140 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG 0x43810144 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX 0x43810148 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG 0x43810164 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG 0x43810168 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX 0x4381016C +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG 0x43810158 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG 0x4381015C +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX 0x43810160 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0 0x438100E4 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1 0x438100E8 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2 0x438100EC +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG3 0x438100F0 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG4 0x438100F4 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0 0x438100D0 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1 0x438100D4 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2 0x438100D8 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG3 0x438100DC +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG4 0x438100E0 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED(_i) 0x43810000 + ((_i) * 4) /* _i=0...2 */ +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_MAX_INDEX_I 2 +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S 24 +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD3_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S) +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S 16 +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD2_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S) +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S 8 +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S) +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S 0 +#define IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD0_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0 0x438100A4 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1 0x438100A8 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2 0x438100AC +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG3 0x438100B0 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG4 0x438100B4 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG5 0x438100B8 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG0 0x43810024 +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S 24 +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S) +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S 16 +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S) +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S 8 +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S) +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S) +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG1 0x43810028 +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG1_RSVD_S 8 +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_CONFIG1_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S) +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0 0x4381002C +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S 24 +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S) +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S 16 +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S) +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S 8 +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S) +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S) +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS1 0x43810030 +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S 8 +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0 0x438100BC +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1 0x438100C0 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2 0x438100C4 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG3 0x438100C8 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG4 0x438100CC +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S) +#define IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL 0x43810034 +#define IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S 16 +#define IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S 8 +#define IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S) +#define IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S) +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL 0x43810018 +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S 20 +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S 16 +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_M RDMA_MASK3(32, 0xF, IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S) +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S 10 +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S 8 +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_M RDMA_MASK3(32, 0x3, IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S) +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_M RDMA_MASK3(32, 0xFF, IG3_WTX2_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S) +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_DATA 0x4381001C +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_DATA_DATA_S 0 +#define IG3_WTX2_GLPE_WTX_SPAD_STAT_DATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX2_GLPE_WTX_SPAD_STAT_DATA_DATA_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG 0x43810170 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG 0x43810174 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX 0x43810178 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX2_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_PTX2_GLPE_ARPCONTROL 0x4381400C +#define IG3_PTX2_GLPE_ARPCONTROL_ARP_LOCK_ACK_S 31 +#define IG3_PTX2_GLPE_ARPCONTROL_ARP_LOCK_ACK_M RDMA_BIT2(32, IG3_PTX2_GLPE_ARPCONTROL_ARP_LOCK_ACK_S) +#define IG3_PTX2_GLPE_ARPCONTROL_ARP_LOCK_REQ_S 30 +#define IG3_PTX2_GLPE_ARPCONTROL_ARP_LOCK_REQ_M RDMA_BIT2(32, IG3_PTX2_GLPE_ARPCONTROL_ARP_LOCK_REQ_S) +#define IG3_PTX2_GLPE_ARPCONTROL_RSVD_S 16 +#define IG3_PTX2_GLPE_ARPCONTROL_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_PTX2_GLPE_ARPCONTROL_RSVD_S) +#define IG3_PTX2_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S 0 +#define IG3_PTX2_GLPE_ARPCONTROL_ARP_LOCK_INDEX_M RDMA_MASK3(32, 0xFFFF, IG3_PTX2_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S) +#define IG3_PTX2_GLPE_CRT_CONFIG0 0x43814010 +#define IG3_PTX2_GLPE_CRT_CONFIG0_RSVD_S 25 +#define IG3_PTX2_GLPE_CRT_CONFIG0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_CRT_CONFIG0_RSVD_S) +#define IG3_PTX2_GLPE_CRT_CONFIG0_QP_FC_EN_S 24 +#define IG3_PTX2_GLPE_CRT_CONFIG0_QP_FC_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_CRT_CONFIG0_QP_FC_EN_S) +#define IG3_PTX2_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S 16 +#define IG3_PTX2_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S) +#define IG3_PTX2_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S 8 +#define IG3_PTX2_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S) +#define IG3_PTX2_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S 0 +#define IG3_PTX2_GLPE_CRT_CONFIG0_TX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S) +#define IG3_PTX2_GLPE_CRT_CONFIG1 0x43814014 +#define IG3_PTX2_GLPE_CRT_CONFIG1_RSVD_S 19 +#define IG3_PTX2_GLPE_CRT_CONFIG1_RSVD_M RDMA_MASK3(32, 0x1FFF, IG3_PTX2_GLPE_CRT_CONFIG1_RSVD_S) +#define IG3_PTX2_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S 16 +#define IG3_PTX2_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_M RDMA_MASK3(32, 0x7, IG3_PTX2_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S) +#define IG3_PTX2_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S 8 +#define IG3_PTX2_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S) +#define IG3_PTX2_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S 0 +#define IG3_PTX2_GLPE_CRT_CONFIG1_RX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S) +#define IG3_PTX2_GLPE_MAX_INLINE_DATA 0x43814000 +#define IG3_PTX2_GLPE_MAX_INLINE_DATA_RSVD_S 8 +#define IG3_PTX2_GLPE_MAX_INLINE_DATA_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX2_GLPE_MAX_INLINE_DATA_RSVD_S) +#define IG3_PTX2_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S 0 +#define IG3_PTX2_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S) +#define IG3_PTX2_GLPE_MAX_TCP_ACKS 0x43814004 +#define IG3_PTX2_GLPE_MAX_TCP_ACKS_RSVD_S 8 +#define IG3_PTX2_GLPE_MAX_TCP_ACKS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX2_GLPE_MAX_TCP_ACKS_RSVD_S) +#define IG3_PTX2_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S 0 +#define IG3_PTX2_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0 0x43814018 +#define IG3_PTX2_GLPE_PTX_CONFIG0_RSVD_31_S 31 +#define IG3_PTX2_GLPE_PTX_CONFIG0_RSVD_31_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_RSVD_31_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S 30 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S 29 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S 28 +#define IG3_PTX2_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S 27 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S 26 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S 22 +#define IG3_PTX2_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_M RDMA_MASK3(32, 0xF, IG3_PTX2_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S 21 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S 20 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_RSVD_19_S 19 +#define IG3_PTX2_GLPE_PTX_CONFIG0_RSVD_19_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_RSVD_19_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S 18 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S 17 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S 16 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S 15 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S 14 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_RSVD_13_7_S 7 +#define IG3_PTX2_GLPE_PTX_CONFIG0_RSVD_13_7_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_PTX_CONFIG0_RSVD_13_7_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_UDP_CS_EN_S 6 +#define IG3_PTX2_GLPE_PTX_CONFIG0_UDP_CS_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_UDP_CS_EN_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S 5 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_Q1_PACING_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S 4 +#define IG3_PTX2_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S 3 +#define IG3_PTX2_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S 1 +#define IG3_PTX2_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S) +#define IG3_PTX2_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S 0 +#define IG3_PTX2_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S) +#define IG3_PTX2_GLPE_PTX_CONFIG1 0x4381401C +#define IG3_PTX2_GLPE_PTX_CONFIG1_RSVD_S 24 +#define IG3_PTX2_GLPE_PTX_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_CONFIG1_RSVD_S) +#define IG3_PTX2_GLPE_PTX_CONFIG1_ACKREQ_PACING_S 21 +#define IG3_PTX2_GLPE_PTX_CONFIG1_ACKREQ_PACING_M RDMA_MASK3(32, 0x7, IG3_PTX2_GLPE_PTX_CONFIG1_ACKREQ_PACING_S) +#define IG3_PTX2_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S 16 +#define IG3_PTX2_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_M RDMA_MASK3(32, 0x1F, IG3_PTX2_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S) +#define IG3_PTX2_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S 0 +#define IG3_PTX2_GLPE_PTX_CONFIG1_Q1_PACING_MULT_M RDMA_MASK3(32, 0xFFFF, IG3_PTX2_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S) +#define IG3_PTX2_GLPE_PTX_CONFIG2 0x43814020 +#define IG3_PTX2_GLPE_PTX_CONFIG2_SEND2CPU_S 0 +#define IG3_PTX2_GLPE_PTX_CONFIG2_SEND2CPU_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_CONFIG2_SEND2CPU_S) +#define IG3_PTX2_GLPE_PTX_CRT_XMIT_PTR 0x4381402C +#define IG3_PTX2_GLPE_PTX_CRT_XMIT_PTR_RSVD_S 8 +#define IG3_PTX2_GLPE_PTX_CRT_XMIT_PTR_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX2_GLPE_PTX_CRT_XMIT_PTR_RSVD_S) +#define IG3_PTX2_GLPE_PTX_CRT_XMIT_PTR_COUNT_S 0 +#define IG3_PTX2_GLPE_PTX_CRT_XMIT_PTR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_CRT_XMIT_PTR_COUNT_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_COUNT 0x43814138 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_CMD 0x4381414C +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_DATA_H 0x43814158 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_DATA_L 0x43814154 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_PTR 0x43814150 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_CMD 0x4381413C +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_DATA_H 0x43814148 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_DATA_L 0x43814144 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_PTR 0x43814140 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX2_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL 0x43814100 +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD2_S) +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD3_S) +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_CONTROL_BYPASS_S) +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_PTX_DTM_CONTROL_RSVD4_S) +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PTX2_GLPE_PTX_DTM_ECC_COR_ERR 0x43814168 +#define IG3_PTX2_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PTX2_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX2_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PTX2_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PTX2_GLPE_PTX_DTM_ECC_UNCOR_ERR 0x43814164 +#define IG3_PTX2_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PTX2_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX2_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PTX2_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG 0x4381410C +#define IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PTX2_GLPE_PTX_DTM_LOG_CFG 0x43814110 +#define IG3_PTX2_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PTX2_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PTX2_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PTX2_GLPE_PTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PTX2_GLPE_PTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PTX2_GLPE_PTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_DTM_LOG_CFG_MODE_S) +#define IG3_PTX2_GLPE_PTX_DTM_LOG_MASK 0x43814118 +#define IG3_PTX2_GLPE_PTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_LOG_MASK_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_LOG_PATTERN 0x43814114 +#define IG3_PTX2_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG 0x43814104 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_STS 0x43814108 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TIMESTAMP 0x43814130 +#define IG3_PTX2_GLPE_PTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER 0x43814134 +#define IG3_PTX2_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG 0x4381415C +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS 0x43814160 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG 0x4381411C +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PTX2_GLPE_PTX_DTM_TRIG_CFG_MODE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_COUNT 0x43814128 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_MASK 0x43814124 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_PATTERN 0x43814120 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_TIMESTAMP 0x4381412C +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PTX2_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHHI 0x43814028 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_PTX2_GLPE_PTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX2_GLPE_PTX_FWQPFLUSHHI_QPID_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX2_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO 0x43814024 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_BUSY_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_FWQPFLUSHLO_PMF_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0 0x43814044 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_TAG_S 16 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_TAG_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_MODE_S 11 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_MODE_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1 0x43814048 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_PMF_S 0 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG1_PMF_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2 0x4381404C +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2_QPID_S 6 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2_QPID_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG3 0x43814050 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG4 0x43814054 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0 0x43814058 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_TAG_S 16 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_TAG_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_MODE_S 11 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_MODE_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1 0x4381405C +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_PMF_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG1_PMF_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2 0x43814060 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2_QPID_S 6 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2_QPID_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG3 0x43814064 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG4 0x43814068 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT0 0x43814078 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S 1 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT1 0x4381407C +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT2 0x43814080 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE0 0x4381406C +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S 1 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE1 0x43814070 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S 24 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE2 0x43814074 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S 24 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S) +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S 0 +#define IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX2_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0 0x43814030 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S 16 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S 11 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1 0x43814034 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S 0 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2 0x43814038 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S 6 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG3 0x4381403C +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG4 0x43814040 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX2_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S) +#define IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD 0x43814008 +#define IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S 25 +#define IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S) +#define IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S 24 +#define IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_M RDMA_BIT2(32, IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S) +#define IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S 0 +#define IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX2_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_COUNT 0x438144B8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_CMD 0x438144CC +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_DATA_H 0x438144D8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_DATA_L 0x438144D4 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_PTR 0x438144D0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_CMD 0x438144BC +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_DATA_H 0x438144C8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_DATA_L 0x438144C4 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_PTR 0x438144C0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL 0x43814480 +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD2_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD3_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_BYPASS_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_RSVD4_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_COR_ERR 0x438144E8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX2_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_UNCOR_ERR 0x438144E4 +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX2_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG 0x4381448C +#define IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX2_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG 0x43814490 +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX2_GLPE_SFPT_DTM_LOG_CFG_MODE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_MASK 0x43814498 +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_PATTERN 0x43814494 +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG 0x43814484 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS 0x43814488 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TIMESTAMP 0x438144B0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER 0x438144B4 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG 0x438144DC +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS 0x438144E0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPTX2_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG 0x4381449C +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_COUNT 0x438144A8 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_MASK 0x438144A4 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_PATTERN 0x438144A0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_TIMESTAMP 0x438144AC +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX2_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPTX2_GLPE_SFP_TX_DOMAIN_ID 0x43814400 +#define IG3_SFPTX2_GLPE_SFP_TX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPTX2_GLPE_SFP_TX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX2_GLPE_SFP_TX_DOMAIN_ID_RSVD_S) +#define IG3_SFPTX2_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPTX2_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPTX2_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPTX2_GLPE_SFP_TX_PER_MEM 0x43814404 +#define IG3_SFPTX2_GLPE_SFP_TX_PER_MEM_RSVD_S 3 +#define IG3_SFPTX2_GLPE_SFP_TX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX2_GLPE_SFP_TX_PER_MEM_RSVD_S) +#define IG3_SFPTX2_GLPE_SFP_TX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPTX2_GLPE_SFP_TX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPTX2_GLPE_SFP_TX_PER_MEM_PER_TYPE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG 0x43814800 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS 0x43814804 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG 0x43814810 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS 0x43814814 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_COR_ERR 0x43814834 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR 0x43814830 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG 0x43814818 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS 0x4381481C +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG 0x43814808 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS 0x4381480C +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG 0x43814828 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS 0x4381482C +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG 0x43814820 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS 0x43814824 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG 0x43814840 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS 0x43814844 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG 0x43814848 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS 0x4381484C +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG 0x43814850 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS 0x43814854 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG 0x43814858 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS 0x4381485C +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR 0x4381487C +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR 0x43814878 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG 0x43814860 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS 0x43814864 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG 0x43814868 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS 0x4381486C +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG 0x43814870 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS 0x43814874 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG 0x43814838 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS 0x4381483C +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL 0x438148C8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S 31 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_DATA 0x438148CC +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG 0x438148C0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS 0x438148C4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_COR_ERR 0x438148E4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR 0x438148E0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL 0x438148D8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S 31 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA 0x438148DC +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG 0x438148D0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS 0x438148D4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL 0x43814888 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA 0x4381488C +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG 0x43814880 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS 0x43814884 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL 0x43814898 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA 0x4381489C +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG 0x43814890 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS 0x43814894 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL 0x438148A8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA 0x438148AC +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG 0x438148A0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS 0x438148A4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL 0x438148B8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA 0x438148BC +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG 0x438148B0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS 0x438148B4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE2_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_DRX2_GLPE_DRX_CONFIG 0x43820000 +#define IG3_DRX2_GLPE_DRX_CONFIG_RSVD1_S 3 +#define IG3_DRX2_GLPE_DRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_DRX2_GLPE_DRX_CONFIG_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_CONFIG_CRC_MASK_S 0 +#define IG3_DRX2_GLPE_DRX_CONFIG_CRC_MASK_M RDMA_MASK3(32, 0x7, IG3_DRX2_GLPE_DRX_CONFIG_CRC_MASK_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_COUNT 0x438200B8 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_CMD 0x438200CC +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_DATA_H 0x438200D8 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_DATA_L 0x438200D4 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_PTR 0x438200D0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_CMD 0x438200BC +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_DATA_H 0x438200C8 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_DATA_L 0x438200C4 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_PTR 0x438200C0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX2_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL 0x43820080 +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD2_S) +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD3_S) +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_CONTROL_BYPASS_S) +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_DRX2_GLPE_DRX_DTM_CONTROL_RSVD4_S) +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_DRX2_GLPE_DRX_DTM_ECC_COR_ERR 0x438200E8 +#define IG3_DRX2_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX2_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX2_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_DRX2_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX2_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_DRX2_GLPE_DRX_DTM_ECC_UNCOR_ERR 0x438200E4 +#define IG3_DRX2_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX2_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX2_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX2_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX2_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG 0x4382008C +#define IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX2_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_DRX2_GLPE_DRX_DTM_LOG_CFG 0x43820090 +#define IG3_DRX2_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_DRX2_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_DRX2_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_DRX2_GLPE_DRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_DRX2_GLPE_DRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_DRX2_GLPE_DRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_DRX_DTM_LOG_CFG_MODE_S) +#define IG3_DRX2_GLPE_DRX_DTM_LOG_MASK 0x43820098 +#define IG3_DRX2_GLPE_DRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_LOG_MASK_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_LOG_PATTERN 0x43820094 +#define IG3_DRX2_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG 0x43820084 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_STS 0x43820088 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TIMESTAMP 0x438200B0 +#define IG3_DRX2_GLPE_DRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER 0x438200B4 +#define IG3_DRX2_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG 0x438200DC +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS 0x438200E0 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX2_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG 0x4382009C +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_DRX2_GLPE_DRX_DTM_TRIG_CFG_MODE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_COUNT 0x438200A8 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_MASK 0x438200A4 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_PATTERN 0x438200A0 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_TIMESTAMP 0x438200AC +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_DRX2_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX2_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_DRX2_GLPE_DRX_ECC_COR_ERR 0x43820004 +#define IG3_DRX2_GLPE_DRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX2_GLPE_DRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX2_GLPE_DRX_ECC_COR_ERR_RSVD_S) +#define IG3_DRX2_GLPE_DRX_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX2_GLPE_DRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX2_GLPE_DRX_ECC_COR_ERR_CNT_S) +#define IG3_DRX2_GLPE_DRX_ECC_UNCOR_ERR 0x43820008 +#define IG3_DRX2_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX2_GLPE_DRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX2_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX2_GLPE_DRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX2_GLPE_DRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX2_GLPE_DRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX2_GLPE_PBUF_CFG 0x4382000C +#define IG3_DRX2_GLPE_PBUF_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX2_GLPE_PBUF_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX2_GLPE_PBUF_CFG_ECC_INST_NUM_S) +#define IG3_DRX2_GLPE_PBUF_CFG_RSVD3_S 20 +#define IG3_DRX2_GLPE_PBUF_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX2_GLPE_PBUF_CFG_RSVD3_S) +#define IG3_DRX2_GLPE_PBUF_CFG_RM_S 16 +#define IG3_DRX2_GLPE_PBUF_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX2_GLPE_PBUF_CFG_RM_S) +#define IG3_DRX2_GLPE_PBUF_CFG_RSVD2_S 14 +#define IG3_DRX2_GLPE_PBUF_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_PBUF_CFG_RSVD2_S) +#define IG3_DRX2_GLPE_PBUF_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX2_GLPE_PBUF_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_POWER_GATE_EN_S) +#define IG3_DRX2_GLPE_PBUF_CFG_RME_S 12 +#define IG3_DRX2_GLPE_PBUF_CFG_RME_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_RME_S) +#define IG3_DRX2_GLPE_PBUF_CFG_RSVD1_S 10 +#define IG3_DRX2_GLPE_PBUF_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_PBUF_CFG_RSVD1_S) +#define IG3_DRX2_GLPE_PBUF_CFG_ERR_CNT_S 9 +#define IG3_DRX2_GLPE_PBUF_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_ERR_CNT_S) +#define IG3_DRX2_GLPE_PBUF_CFG_FIX_CNT_S 8 +#define IG3_DRX2_GLPE_PBUF_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_FIX_CNT_S) +#define IG3_DRX2_GLPE_PBUF_CFG_RSVD0_S 6 +#define IG3_DRX2_GLPE_PBUF_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_PBUF_CFG_RSVD0_S) +#define IG3_DRX2_GLPE_PBUF_CFG_MASK_INT_S 5 +#define IG3_DRX2_GLPE_PBUF_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_MASK_INT_S) +#define IG3_DRX2_GLPE_PBUF_CFG_LS_BYPASS_S 4 +#define IG3_DRX2_GLPE_PBUF_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_LS_BYPASS_S) +#define IG3_DRX2_GLPE_PBUF_CFG_LS_FORCE_S 3 +#define IG3_DRX2_GLPE_PBUF_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_LS_FORCE_S) +#define IG3_DRX2_GLPE_PBUF_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX2_GLPE_PBUF_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_ECC_INVERT_2_S) +#define IG3_DRX2_GLPE_PBUF_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX2_GLPE_PBUF_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_ECC_INVERT_1_S) +#define IG3_DRX2_GLPE_PBUF_CFG_ECC_EN_S 0 +#define IG3_DRX2_GLPE_PBUF_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_CFG_ECC_EN_S) +#define IG3_DRX2_GLPE_PBUF_STATUS 0x43820010 +#define IG3_DRX2_GLPE_PBUF_STATUS_RSVD1_S 30 +#define IG3_DRX2_GLPE_PBUF_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX2_GLPE_PBUF_STATUS_RSVD1_S) +#define IG3_DRX2_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX2_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX2_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX2_GLPE_PBUF_STATUS_RSVD0_S 4 +#define IG3_DRX2_GLPE_PBUF_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX2_GLPE_PBUF_STATUS_RSVD0_S) +#define IG3_DRX2_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX2_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX2_GLPE_PBUF_STATUS_INIT_DONE_S 2 +#define IG3_DRX2_GLPE_PBUF_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_STATUS_INIT_DONE_S) +#define IG3_DRX2_GLPE_PBUF_STATUS_ECC_FIX_S 1 +#define IG3_DRX2_GLPE_PBUF_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_STATUS_ECC_FIX_S) +#define IG3_DRX2_GLPE_PBUF_STATUS_ECC_ERR_S 0 +#define IG3_DRX2_GLPE_PBUF_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX2_GLPE_PBUF_STATUS_ECC_ERR_S) +#define IG3_CMPE2_CMPE_ECC_COR_ERR 0x4382053C +#define IG3_CMPE2_CMPE_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE2_CMPE_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_CMPE_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE2_CMPE_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE2_CMPE_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_CMPE_ECC_COR_ERR_CNT_S) +#define IG3_CMPE2_CMPE_ECC_UNCOR_ERR 0x43820538 +#define IG3_CMPE2_CMPE_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE2_CMPE_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_CMPE_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE2_CMPE_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE2_CMPE_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_CMPE_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE2_GLCM_PECLSADDR 0x43820484 +#define IG3_CMPE2_GLCM_PECLSADDR_RSVD_S 9 +#define IG3_CMPE2_GLCM_PECLSADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE2_GLCM_PECLSADDR_RSVD_S) +#define IG3_CMPE2_GLCM_PECLSADDR_CLS_ADDR_S 0 +#define IG3_CMPE2_GLCM_PECLSADDR_CLS_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE2_GLCM_PECLSADDR_CLS_ADDR_S) +#define IG3_CMPE2_GLCM_PECLSDATA0 0x43820488 +#define IG3_CMPE2_GLCM_PECLSDATA0_CLS_DATA_S 0 +#define IG3_CMPE2_GLCM_PECLSDATA0_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLCM_PECLSDATA0_CLS_DATA_S) +#define IG3_CMPE2_GLCM_PECLSDATA1 0x4382048C +#define IG3_CMPE2_GLCM_PECLSDATA1_CLS_DATA_S 0 +#define IG3_CMPE2_GLCM_PECLSDATA1_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLCM_PECLSDATA1_CLS_DATA_S) +#define IG3_CMPE2_GLCM_PECLSDATA2 0x43820490 +#define IG3_CMPE2_GLCM_PECLSDATA2_CLS_DATA_S 0 +#define IG3_CMPE2_GLCM_PECLSDATA2_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLCM_PECLSDATA2_CLS_DATA_S) +#define IG3_CMPE2_GLCM_PECONFIG 0x43820480 +#define IG3_CMPE2_GLCM_PECONFIG_DBGMUX_EN_S 31 +#define IG3_CMPE2_GLCM_PECONFIG_DBGMUX_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_DBGMUX_EN_S) +#define IG3_CMPE2_GLCM_PECONFIG_RSVD13_S 30 +#define IG3_CMPE2_GLCM_PECONFIG_RSVD13_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_RSVD13_S) +#define IG3_CMPE2_GLCM_PECONFIG_DBGMUX_SEL_HI_S 25 +#define IG3_CMPE2_GLCM_PECONFIG_DBGMUX_SEL_HI_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PECONFIG_DBGMUX_SEL_HI_S) +#define IG3_CMPE2_GLCM_PECONFIG_DBGMUX_SEL_LO_S 20 +#define IG3_CMPE2_GLCM_PECONFIG_DBGMUX_SEL_LO_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PECONFIG_DBGMUX_SEL_LO_S) +#define IG3_CMPE2_GLCM_PECONFIG_RSVD10_S 17 +#define IG3_CMPE2_GLCM_PECONFIG_RSVD10_M RDMA_MASK3(32, 0x7, IG3_CMPE2_GLCM_PECONFIG_RSVD10_S) +#define IG3_CMPE2_GLCM_PECONFIG_DBG_WRSEL_S 16 +#define IG3_CMPE2_GLCM_PECONFIG_DBG_WRSEL_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_DBG_WRSEL_S) +#define IG3_CMPE2_GLCM_PECONFIG_DBG_DWSEL_S 14 +#define IG3_CMPE2_GLCM_PECONFIG_DBG_DWSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PECONFIG_DBG_DWSEL_S) +#define IG3_CMPE2_GLCM_PECONFIG_DBG_DPSEL_S 12 +#define IG3_CMPE2_GLCM_PECONFIG_DBG_DPSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PECONFIG_DBG_DPSEL_S) +#define IG3_CMPE2_GLCM_PECONFIG_RSVD6_S 7 +#define IG3_CMPE2_GLCM_PECONFIG_RSVD6_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PECONFIG_RSVD6_S) +#define IG3_CMPE2_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S 6 +#define IG3_CMPE2_GLCM_PECONFIG_DISABLE_CTXT_PACKING_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S) +#define IG3_CMPE2_GLCM_PECONFIG_DISABLE_LSA_S 5 +#define IG3_CMPE2_GLCM_PECONFIG_DISABLE_LSA_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_DISABLE_LSA_S) +#define IG3_CMPE2_GLCM_PECONFIG_ENABLE_CRC_S 4 +#define IG3_CMPE2_GLCM_PECONFIG_ENABLE_CRC_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_ENABLE_CRC_S) +#define IG3_CMPE2_GLCM_PECONFIG_DISABLE_RESCHEDULE_S 3 +#define IG3_CMPE2_GLCM_PECONFIG_DISABLE_RESCHEDULE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_DISABLE_RESCHEDULE_S) +#define IG3_CMPE2_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S 2 +#define IG3_CMPE2_GLCM_PECONFIG_DISABLE_PACKET_COUNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S) +#define IG3_CMPE2_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S 1 +#define IG3_CMPE2_GLCM_PECONFIG_GLOBAL_LOCK_MODE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S) +#define IG3_CMPE2_GLCM_PECONFIG_RSVD1_S 0 +#define IG3_CMPE2_GLCM_PECONFIG_RSVD1_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECONFIG_RSVD1_S) +#define IG3_CMPE2_GLCM_PECTXDGCTL 0x438204C8 +#define IG3_CMPE2_GLCM_PECTXDGCTL_RSVD_S 12 +#define IG3_CMPE2_GLCM_PECTXDGCTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_GLCM_PECTXDGCTL_RSVD_S) +#define IG3_CMPE2_GLCM_PECTXDGCTL_PKTCNT_S 10 +#define IG3_CMPE2_GLCM_PECTXDGCTL_PKTCNT_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PECTXDGCTL_PKTCNT_S) +#define IG3_CMPE2_GLCM_PECTXDGCTL_OP_CODE_S 8 +#define IG3_CMPE2_GLCM_PECTXDGCTL_OP_CODE_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PECTXDGCTL_OP_CODE_S) +#define IG3_CMPE2_GLCM_PECTXDGCTL_ALLOCATE_S 7 +#define IG3_CMPE2_GLCM_PECTXDGCTL_ALLOCATE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECTXDGCTL_ALLOCATE_S) +#define IG3_CMPE2_GLCM_PECTXDGCTL_WRITEBACK_S 6 +#define IG3_CMPE2_GLCM_PECTXDGCTL_WRITEBACK_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECTXDGCTL_WRITEBACK_S) +#define IG3_CMPE2_GLCM_PECTXDGCTL_INVALIDATE_S 5 +#define IG3_CMPE2_GLCM_PECTXDGCTL_INVALIDATE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECTXDGCTL_INVALIDATE_S) +#define IG3_CMPE2_GLCM_PECTXDGCTL_SUB_LINE_S 0 +#define IG3_CMPE2_GLCM_PECTXDGCTL_SUB_LINE_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PECTXDGCTL_SUB_LINE_S) +#define IG3_CMPE2_GLCM_PECTXDGDATA(_i) 0x438204CC + ((_i) * 4) /* _i=0...3 */ +#define IG3_CMPE2_GLCM_PECTXDGDATA_MAX_INDEX_I 3 +#define IG3_CMPE2_GLCM_PECTXDGDATA_DATA_S 0 +#define IG3_CMPE2_GLCM_PECTXDGDATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLCM_PECTXDGDATA_DATA_S) +#define IG3_CMPE2_GLCM_PECTXDGFN 0x438204C0 +#define IG3_CMPE2_GLCM_PECTXDGFN_RSVD_S 20 +#define IG3_CMPE2_GLCM_PECTXDGFN_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLCM_PECTXDGFN_RSVD_S) +#define IG3_CMPE2_GLCM_PECTXDGFN_FUNC_TRIPLET_S 0 +#define IG3_CMPE2_GLCM_PECTXDGFN_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_GLCM_PECTXDGFN_FUNC_TRIPLET_S) +#define IG3_CMPE2_GLCM_PECTXDGQP 0x438204C4 +#define IG3_CMPE2_GLCM_PECTXDGQP_RSVD_S 24 +#define IG3_CMPE2_GLCM_PECTXDGQP_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PECTXDGQP_RSVD_S) +#define IG3_CMPE2_GLCM_PECTXDGQP_QUEUE_NUM_S 0 +#define IG3_CMPE2_GLCM_PECTXDGQP_QUEUE_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE2_GLCM_PECTXDGQP_QUEUE_NUM_S) +#define IG3_CMPE2_GLCM_PECTXDGSTAT 0x438204DC +#define IG3_CMPE2_GLCM_PECTXDGSTAT_RSVD_S 2 +#define IG3_CMPE2_GLCM_PECTXDGSTAT_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE2_GLCM_PECTXDGSTAT_RSVD_S) +#define IG3_CMPE2_GLCM_PECTXDGSTAT_CTX_MISS_S 1 +#define IG3_CMPE2_GLCM_PECTXDGSTAT_CTX_MISS_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECTXDGSTAT_CTX_MISS_S) +#define IG3_CMPE2_GLCM_PECTXDGSTAT_CTX_DONE_S 0 +#define IG3_CMPE2_GLCM_PECTXDGSTAT_CTX_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PECTXDGSTAT_CTX_DONE_S) +#define IG3_CMPE2_GLCM_PEDATAREQHI 0x438204B4 +#define IG3_CMPE2_GLCM_PEDATAREQHI_RSVD_S 24 +#define IG3_CMPE2_GLCM_PEDATAREQHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PEDATAREQHI_RSVD_S) +#define IG3_CMPE2_GLCM_PEDATAREQHI_DATAREQHI_S 0 +#define IG3_CMPE2_GLCM_PEDATAREQHI_DATAREQHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE2_GLCM_PEDATAREQHI_DATAREQHI_S) +#define IG3_CMPE2_GLCM_PEDATAREQLO 0x438204B0 +#define IG3_CMPE2_GLCM_PEDATAREQLO_DATAREQLOW_S 0 +#define IG3_CMPE2_GLCM_PEDATAREQLO_DATAREQLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLCM_PEDATAREQLO_DATAREQLOW_S) +#define IG3_CMPE2_GLCM_PEDATASTALLHI 0x438204BC +#define IG3_CMPE2_GLCM_PEDATASTALLHI_RSVD_S 24 +#define IG3_CMPE2_GLCM_PEDATASTALLHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PEDATASTALLHI_RSVD_S) +#define IG3_CMPE2_GLCM_PEDATASTALLHI_DATASTALLHI_S 0 +#define IG3_CMPE2_GLCM_PEDATASTALLHI_DATASTALLHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE2_GLCM_PEDATASTALLHI_DATASTALLHI_S) +#define IG3_CMPE2_GLCM_PEDATASTALLLO 0x438204B8 +#define IG3_CMPE2_GLCM_PEDATASTALLLO_DATASTALLLOW_S 0 +#define IG3_CMPE2_GLCM_PEDATASTALLLO_DATASTALLLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLCM_PEDATASTALLLO_DATASTALLLOW_S) +#define IG3_CMPE2_GLCM_PELOCKTBLADDR 0x4382049C +#define IG3_CMPE2_GLCM_PELOCKTBLADDR_RSVD_S 5 +#define IG3_CMPE2_GLCM_PELOCKTBLADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_CMPE2_GLCM_PELOCKTBLADDR_RSVD_S) +#define IG3_CMPE2_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S 0 +#define IG3_CMPE2_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S) +#define IG3_CMPE2_GLCM_PELOCKTBLDATA0 0x438204A0 +#define IG3_CMPE2_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S 31 +#define IG3_CMPE2_GLCM_PELOCKTBLDATA0_GPLOCKSEL_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S) +#define IG3_CMPE2_GLCM_PELOCKTBLDATA0_RSVD_S 24 +#define IG3_CMPE2_GLCM_PELOCKTBLDATA0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PELOCKTBLDATA0_RSVD_S) +#define IG3_CMPE2_GLCM_PELOCKTBLDATA0_QPID_S 0 +#define IG3_CMPE2_GLCM_PELOCKTBLDATA0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE2_GLCM_PELOCKTBLDATA0_QPID_S) +#define IG3_CMPE2_GLCM_PELOCKTBLDATA1 0x438204A4 +#define IG3_CMPE2_GLCM_PELOCKTBLDATA1_RSVD_S 20 +#define IG3_CMPE2_GLCM_PELOCKTBLDATA1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLCM_PELOCKTBLDATA1_RSVD_S) +#define IG3_CMPE2_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S 0 +#define IG3_CMPE2_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S) +#define IG3_CMPE2_GLCM_PELOCKTBLDATA2 0x438204A8 +#define IG3_CMPE2_GLCM_PELOCKTBLDATA2_LOCKSEL_S 0 +#define IG3_CMPE2_GLCM_PELOCKTBLDATA2_LOCKSEL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLCM_PELOCKTBLDATA2_LOCKSEL_S) +#define IG3_CMPE2_GLCM_PEPKTCNTADDR 0x43820494 +#define IG3_CMPE2_GLCM_PEPKTCNTADDR_RSVD_S 9 +#define IG3_CMPE2_GLCM_PEPKTCNTADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE2_GLCM_PEPKTCNTADDR_RSVD_S) +#define IG3_CMPE2_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S 0 +#define IG3_CMPE2_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE2_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S) +#define IG3_CMPE2_GLCM_PEPKTCNTDATA 0x43820498 +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_RSVD1_S 18 +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE2_GLCM_PEPKTCNTDATA_RSVD1_S) +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_RLRSP_STATE_S 16 +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_RLRSP_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PEPKTCNTDATA_RLRSP_STATE_S) +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_RSVD0_S 14 +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PEPKTCNTDATA_RSVD0_S) +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_RLREQ_STATE_S 12 +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_RLREQ_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PEPKTCNTDATA_RLREQ_STATE_S) +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_PKTCNT_S 1 +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_PKTCNT_M RDMA_MASK3(32, 0x7FF, IG3_CMPE2_GLCM_PEPKTCNTDATA_PKTCNT_S) +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_DONE_S 0 +#define IG3_CMPE2_GLCM_PEPKTCNTDATA_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PEPKTCNTDATA_DONE_S) +#define IG3_CMPE2_GLCM_PESTATSCTL 0x438204AC +#define IG3_CMPE2_GLCM_PESTATSCTL_RSVD_S 2 +#define IG3_CMPE2_GLCM_PESTATSCTL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE2_GLCM_PESTATSCTL_RSVD_S) +#define IG3_CMPE2_GLCM_PESTATSCTL_ENABLE_S 1 +#define IG3_CMPE2_GLCM_PESTATSCTL_ENABLE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PESTATSCTL_ENABLE_S) +#define IG3_CMPE2_GLCM_PESTATSCTL_CLEAR_S 0 +#define IG3_CMPE2_GLCM_PESTATSCTL_CLEAR_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PESTATSCTL_CLEAR_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG 0x43820500 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RM_S 16 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RM_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RME_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RME_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS 0x43820504 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG 0x43820508 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RM_S 16 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RM_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RME_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RME_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS 0x4382050C +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG 0x43820510 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RM_S 16 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RM_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RME_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RME_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS 0x43820514 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG 0x43820518 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RM_S 16 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RM_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RME_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RME_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS 0x4382051C +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG 0x43820520 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RM_S 16 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RM_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RME_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RME_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS 0x43820524 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE2_GLCM_PE_CACHESIZE 0x438204E4 +#define IG3_CMPE2_GLCM_PE_CACHESIZE_RSVD_S 26 +#define IG3_CMPE2_GLCM_PE_CACHESIZE_RSVD_M RDMA_MASK3(32, 0x3F, IG3_CMPE2_GLCM_PE_CACHESIZE_RSVD_S) +#define IG3_CMPE2_GLCM_PE_CACHESIZE_WAYS_S 16 +#define IG3_CMPE2_GLCM_PE_CACHESIZE_WAYS_M RDMA_MASK3(32, 0x3FF, IG3_CMPE2_GLCM_PE_CACHESIZE_WAYS_S) +#define IG3_CMPE2_GLCM_PE_CACHESIZE_SETS_S 12 +#define IG3_CMPE2_GLCM_PE_CACHESIZE_SETS_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLCM_PE_CACHESIZE_SETS_S) +#define IG3_CMPE2_GLCM_PE_CACHESIZE_WORD_SIZE_S 0 +#define IG3_CMPE2_GLCM_PE_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLCM_PE_CACHESIZE_WORD_SIZE_S) +#define IG3_CMPE2_GLCM_PE_DPC_COMP 0x438204F4 +#define IG3_CMPE2_GLCM_PE_DPC_COMP_RSVD_S 13 +#define IG3_CMPE2_GLCM_PE_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_CMPE2_GLCM_PE_DPC_COMP_RSVD_S) +#define IG3_CMPE2_GLCM_PE_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_CMPE2_GLCM_PE_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_DPC_COMP_COMP_FTYPE_S) +#define IG3_CMPE2_GLCM_PE_DPC_COMP_COMP_FNUM_S 1 +#define IG3_CMPE2_GLCM_PE_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE2_GLCM_PE_DPC_COMP_COMP_FNUM_S) +#define IG3_CMPE2_GLCM_PE_DPC_COMP_COMP_VALID_S 0 +#define IG3_CMPE2_GLCM_PE_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_DPC_COMP_COMP_VALID_S) +#define IG3_CMPE2_GLCM_PE_DPC_REQ 0x438204F0 +#define IG3_CMPE2_GLCM_PE_DPC_REQ_RSVD_S 12 +#define IG3_CMPE2_GLCM_PE_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_GLCM_PE_DPC_REQ_RSVD_S) +#define IG3_CMPE2_GLCM_PE_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_CMPE2_GLCM_PE_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_DPC_REQ_REQ_FTYPE_S) +#define IG3_CMPE2_GLCM_PE_DPC_REQ_REQ_FNUM_S 0 +#define IG3_CMPE2_GLCM_PE_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE2_GLCM_PE_DPC_REQ_REQ_FNUM_S) +#define IG3_CMPE2_GLCM_PE_E2E_FC 0x438204F8 +#define IG3_CMPE2_GLCM_PE_E2E_FC_RSVD1_S 22 +#define IG3_CMPE2_GLCM_PE_E2E_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE2_GLCM_PE_E2E_FC_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE2_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE2_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE2_GLCM_PE_E2E_FC_RSVD0_S 9 +#define IG3_CMPE2_GLCM_PE_E2E_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PE_E2E_FC_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE2_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE2_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG 0x43820528 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RM_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RME_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS 0x4382052C +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG 0x43820530 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RM_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RME_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS 0x43820534 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE2_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE2_GLCM_PE_IF_FC 0x438204FC +#define IG3_CMPE2_GLCM_PE_IF_FC_RSVD1_S 22 +#define IG3_CMPE2_GLCM_PE_IF_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE2_GLCM_PE_IF_FC_RSVD1_S) +#define IG3_CMPE2_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE2_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE2_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE2_GLCM_PE_IF_FC_RSVD0_S 9 +#define IG3_CMPE2_GLCM_PE_IF_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLCM_PE_IF_FC_RSVD0_S) +#define IG3_CMPE2_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE2_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE2_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE2_GLCM_PE_MAXOSR 0x438204E0 +#define IG3_CMPE2_GLCM_PE_MAXOSR_RSVD_S 6 +#define IG3_CMPE2_GLCM_PE_MAXOSR_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_CMPE2_GLCM_PE_MAXOSR_RSVD_S) +#define IG3_CMPE2_GLCM_PE_MAXOSR_MAXOSR_S 0 +#define IG3_CMPE2_GLCM_PE_MAXOSR_MAXOSR_M RDMA_MASK3(32, 0x3F, IG3_CMPE2_GLCM_PE_MAXOSR_MAXOSR_S) +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL0 0x438204E8 +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL0_RSVD_S 24 +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL0_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLCM_PE_RLDDBGCTL0_RSVD_S) +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL0_QPID_S 0 +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE2_GLCM_PE_RLDDBGCTL0_QPID_S) +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL1 0x438204EC +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL1_RSVD_S 20 +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLCM_PE_RLDDBGCTL1_RSVD_S) +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S 18 +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S) +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S 6 +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S) +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL1_PF_NUM_S 0 +#define IG3_CMPE2_GLCM_PE_RLDDBGCTL1_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_CMPE2_GLCM_PE_RLDDBGCTL1_PF_NUM_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_COUNT 0x438205B8 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_CMD 0x438205CC +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_DATA_H 0x438205D8 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_DATA_L 0x438205D4 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_PTR 0x438205D0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_CMD 0x438205BC +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_DATA_H 0x438205C8 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_DATA_L 0x438205C4 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_PTR 0x438205C0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL 0x43820580 +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD1_S 25 +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD2_S 17 +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD2_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD3_S 9 +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD3_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_BYPASS_S 8 +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_BYPASS_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD4_S 1 +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_RSVD4_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_COR_ERR 0x438205E8 +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_UNCOR_ERR 0x438205E4 +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG 0x4382058C +#define IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG 0x43820590 +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG_MODE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLPE_CMPE_DTM_LOG_CFG_MODE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_MASK 0x43820598 +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_MASK_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_LOG_MASK_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_PATTERN 0x43820594 +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG 0x43820584 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS 0x43820588 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TIMESTAMP 0x438205B0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER 0x438205B4 +#define IG3_CMPE2_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG 0x438205DC +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS 0x438205E0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE2_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG 0x4382059C +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_MODE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_CMPE2_GLPE_CMPE_DTM_TRIG_CFG_MODE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_COUNT 0x438205A8 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_MASK 0x438205A4 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_PATTERN 0x438205A0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_TIMESTAMP 0x438205AC +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE2_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE2_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0(_i) 0x43820400 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_MAX_INDEX_I 15 +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_RSVD1_S 18 +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE2_PFCM_PE_CRCERRINFO0_RSVD1_S) +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S 16 +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE2_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S) +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S 4 +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE2_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S) +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_RSVD0_S 1 +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_RSVD0_M RDMA_MASK3(32, 0x7, IG3_CMPE2_PFCM_PE_CRCERRINFO0_RSVD0_S) +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S 0 +#define IG3_CMPE2_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_M RDMA_BIT2(32, IG3_CMPE2_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S) +#define IG3_CMPE2_PFCM_PE_CRCERRINFO1(_i) 0x43820440 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE2_PFCM_PE_CRCERRINFO1_MAX_INDEX_I 15 +#define IG3_CMPE2_PFCM_PE_CRCERRINFO1_RSVD_S 24 +#define IG3_CMPE2_PFCM_PE_CRCERRINFO1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE2_PFCM_PE_CRCERRINFO1_RSVD_S) +#define IG3_CMPE2_PFCM_PE_CRCERRINFO1_Q_NUM_S 0 +#define IG3_CMPE2_PFCM_PE_CRCERRINFO1_Q_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE2_PFCM_PE_CRCERRINFO1_Q_NUM_S) +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG(_i) 0x43C02000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG_MAX_INDEX_I 1031 +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG_RSVD2_S 31 +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG_RSVD2_M RDMA_BIT2(32, IG3_PRX3_GLPE_CC_DCQCN1_CFG_RSVD2_S) +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG_DCQCN_F_S 28 +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG_DCQCN_F_M RDMA_MASK3(32, 0x7, IG3_PRX3_GLPE_CC_DCQCN1_CFG_DCQCN_F_S) +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG_RSVD1_S 25 +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_PRX3_GLPE_CC_DCQCN1_CFG_RSVD1_S) +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG_DCQCN_B_S 0 +#define IG3_PRX3_GLPE_CC_DCQCN1_CFG_DCQCN_B_M RDMA_MASK3(32, 0x1FFFFFF, IG3_PRX3_GLPE_CC_DCQCN1_CFG_DCQCN_B_S) +#define IG3_PRX3_GLPE_CC_DCQCN2_CFG(_i) 0x43C04000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX3_GLPE_CC_DCQCN2_CFG_MAX_INDEX_I 1031 +#define IG3_PRX3_GLPE_CC_DCQCN2_CFG_RSVD_S 16 +#define IG3_PRX3_GLPE_CC_DCQCN2_CFG_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PRX3_GLPE_CC_DCQCN2_CFG_RSVD_S) +#define IG3_PRX3_GLPE_CC_DCQCN2_CFG_DCQCN_T_S 0 +#define IG3_PRX3_GLPE_CC_DCQCN2_CFG_DCQCN_T_M RDMA_MASK3(32, 0xFFFF, IG3_PRX3_GLPE_CC_DCQCN2_CFG_DCQCN_T_S) +#define IG3_PRX3_GLPE_CC_TIMELY_CFG(_i) 0x43C00000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX3_GLPE_CC_TIMELY_CFG_MAX_INDEX_I 1031 +#define IG3_PRX3_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S 16 +#define IG3_PRX3_GLPE_CC_TIMELY_CFG_RAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX3_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S) +#define IG3_PRX3_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S 0 +#define IG3_PRX3_GLPE_CC_TIMELY_CFG_HAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX3_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S) +#define IG3_PRX3_GLPE_PRX_CONFIG 0x43C05020 +#define IG3_PRX3_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S 24 +#define IG3_PRX3_GLPE_PRX_CONFIG_REORDER_CNT_MAX_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S) +#define IG3_PRX3_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S 16 +#define IG3_PRX3_GLPE_PRX_CONFIG_REORDER_CNT_MIN_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S) +#define IG3_PRX3_GLPE_PRX_CONFIG_RSVD1_S 12 +#define IG3_PRX3_GLPE_PRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PRX3_GLPE_PRX_CONFIG_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S 8 +#define IG3_PRX3_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_M RDMA_MASK3(32, 0xF, IG3_PRX3_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S) +#define IG3_PRX3_GLPE_PRX_CONFIG_RSVD0_S 5 +#define IG3_PRX3_GLPE_PRX_CONFIG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PRX3_GLPE_PRX_CONFIG_RSVD0_S) +#define IG3_PRX3_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S 4 +#define IG3_PRX3_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S) +#define IG3_PRX3_GLPE_PRX_CONFIG_ONE_HP_TILE_S 3 +#define IG3_PRX3_GLPE_PRX_CONFIG_ONE_HP_TILE_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_CONFIG_ONE_HP_TILE_S) +#define IG3_PRX3_GLPE_PRX_CONFIG_DIS_RREC_S 2 +#define IG3_PRX3_GLPE_PRX_CONFIG_DIS_RREC_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_CONFIG_DIS_RREC_S) +#define IG3_PRX3_GLPE_PRX_CONFIG_DIS_QR_STALL_S 1 +#define IG3_PRX3_GLPE_PRX_CONFIG_DIS_QR_STALL_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_CONFIG_DIS_QR_STALL_S) +#define IG3_PRX3_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S 0 +#define IG3_PRX3_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_COUNT 0x43C050B8 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_CMD 0x43C050CC +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_DATA_H 0x43C050D8 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_DATA_L 0x43C050D4 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_PTR 0x43C050D0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_CMD 0x43C050BC +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_DATA_H 0x43C050C8 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_DATA_L 0x43C050C4 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_PTR 0x43C050C0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX3_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL 0x43C05080 +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD2_S) +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD3_S) +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_CONTROL_BYPASS_S) +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PRX3_GLPE_PRX_DTM_CONTROL_RSVD4_S) +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PRX3_GLPE_PRX_DTM_ECC_COR_ERR 0x43C050E8 +#define IG3_PRX3_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PRX3_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX3_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PRX3_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX3_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PRX3_GLPE_PRX_DTM_ECC_UNCOR_ERR 0x43C050E4 +#define IG3_PRX3_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PRX3_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX3_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PRX3_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX3_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG 0x43C0508C +#define IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PRX3_GLPE_PRX_DTM_LOG_CFG 0x43C05090 +#define IG3_PRX3_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PRX3_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PRX3_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PRX3_GLPE_PRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PRX3_GLPE_PRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PRX3_GLPE_PRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PRX3_GLPE_PRX_DTM_LOG_CFG_MODE_S) +#define IG3_PRX3_GLPE_PRX_DTM_LOG_MASK 0x43C05098 +#define IG3_PRX3_GLPE_PRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_LOG_MASK_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_LOG_PATTERN 0x43C05094 +#define IG3_PRX3_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG 0x43C05084 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_STS 0x43C05088 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TIMESTAMP 0x43C050B0 +#define IG3_PRX3_GLPE_PRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER 0x43C050B4 +#define IG3_PRX3_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG 0x43C050DC +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS 0x43C050E0 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG 0x43C0509C +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PRX3_GLPE_PRX_DTM_TRIG_CFG_MODE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_COUNT 0x43C050A8 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_MASK 0x43C050A4 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_PATTERN 0x43C050A0 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_TIMESTAMP 0x43C050AC +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PRX3_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX3_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_CTL 0x43C05024 +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S 12 +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S) +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S 0 +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S) +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA 0x43C05028 +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S 31 +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S) +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S 30 +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_M RDMA_BIT2(32, IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S) +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S 24 +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S) +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S 20 +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S) +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S 0 +#define IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX3_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S) +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL 0x43C08018 +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S 21 +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_M RDMA_MASK3(32, 0x7FF, IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S) +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S 16 +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S) +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S 13 +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S 8 +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S) +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S 5 +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S) +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S 0 +#define IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX3_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S) +#define IG3_WRX3_GLPE_WRX_CONFIG 0x43C08000 +#define IG3_WRX3_GLPE_WRX_CONFIG_RSVD_S 8 +#define IG3_WRX3_GLPE_WRX_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WRX3_GLPE_WRX_CONFIG_RSVD_S) +#define IG3_WRX3_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S 5 +#define IG3_WRX3_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_M RDMA_MASK3(32, 0x7, IG3_WRX3_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S) +#define IG3_WRX3_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S 4 +#define IG3_WRX3_GLPE_WRX_CONFIG_DIS_WQE_CACHE_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S) +#define IG3_WRX3_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S 3 +#define IG3_WRX3_GLPE_WRX_CONFIG_DROP_OOO_IMMED_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S) +#define IG3_WRX3_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S 2 +#define IG3_WRX3_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S) +#define IG3_WRX3_GLPE_WRX_CONFIG_DIS_Q1_AE_S 1 +#define IG3_WRX3_GLPE_WRX_CONFIG_DIS_Q1_AE_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_CONFIG_DIS_Q1_AE_S) +#define IG3_WRX3_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S 0 +#define IG3_WRX3_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S) +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS 0x43C08014 +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_RSVD2_S 11 +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_RSVD2_M RDMA_MASK3(32, 0x1FFFFF, IG3_WRX3_GLPE_WRX_DOMAIN_IDS_RSVD2_S) +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S 8 +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX3_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S) +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_RSVD1_S 7 +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_RSVD1_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DOMAIN_IDS_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S 4 +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX3_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S) +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_RSVD0_S 3 +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_RSVD0_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DOMAIN_IDS_RSVD0_S) +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S 0 +#define IG3_WRX3_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX3_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_COUNT 0x43C080B8 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_CMD 0x43C080CC +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_DATA_H 0x43C080D8 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_DATA_L 0x43C080D4 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_PTR 0x43C080D0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_CMD 0x43C080BC +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_DATA_H 0x43C080C8 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_DATA_L 0x43C080C4 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_PTR 0x43C080C0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX3_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL 0x43C08080 +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD2_S) +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD3_S) +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_CONTROL_BYPASS_S) +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WRX3_GLPE_WRX_DTM_CONTROL_RSVD4_S) +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WRX3_GLPE_WRX_DTM_ECC_COR_ERR 0x43C080E8 +#define IG3_WRX3_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WRX3_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX3_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WRX3_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX3_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WRX3_GLPE_WRX_DTM_ECC_UNCOR_ERR 0x43C080E4 +#define IG3_WRX3_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WRX3_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX3_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WRX3_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX3_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG 0x43C0808C +#define IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX3_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WRX3_GLPE_WRX_DTM_LOG_CFG 0x43C08090 +#define IG3_WRX3_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WRX3_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WRX3_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WRX3_GLPE_WRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WRX3_GLPE_WRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WRX3_GLPE_WRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WRX3_GLPE_WRX_DTM_LOG_CFG_MODE_S) +#define IG3_WRX3_GLPE_WRX_DTM_LOG_MASK 0x43C08098 +#define IG3_WRX3_GLPE_WRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_LOG_MASK_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_LOG_PATTERN 0x43C08094 +#define IG3_WRX3_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG 0x43C08084 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_STS 0x43C08088 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TIMESTAMP 0x43C080B0 +#define IG3_WRX3_GLPE_WRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER 0x43C080B4 +#define IG3_WRX3_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG 0x43C080DC +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS 0x43C080E0 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG 0x43C0809C +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WRX3_GLPE_WRX_DTM_TRIG_CFG_MODE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_COUNT 0x43C080A8 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_MASK 0x43C080A4 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_PATTERN 0x43C080A0 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_TIMESTAMP 0x43C080AC +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WRX3_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHHI 0x43C08020 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WRX3_GLPE_WRX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX3_GLPE_WRX_FWQPFLUSHHI_QPID_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WRX3_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO 0x43C0801C +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_BUSY_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WRX3_GLPE_WRX_FWQPFLUSHLO_PMF_S) +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_CTRL 0x43C08004 +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S 7 +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x1FFFFFF, IG3_WRX3_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S) +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S 0 +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_M RDMA_MASK3(32, 0x7F, IG3_WRX3_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S) +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA0 0x43C08008 +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA0_DATA_S 0 +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA0_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA0_DATA_S) +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA1 0x43C0800C +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA1_DATA_S 0 +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA1_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA1_DATA_S) +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA2 0x43C08010 +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA2_DATA_S 0 +#define IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA2_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX3_GLPE_WRX_RQ_CACHE_DATA2_DATA_S) +#define IG3_SQC3_GLPE_SQC_CONFIG 0x43C08470 +#define IG3_SQC3_GLPE_SQC_CONFIG_RSVD_S 6 +#define IG3_SQC3_GLPE_SQC_CONFIG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_SQC3_GLPE_SQC_CONFIG_RSVD_S) +#define IG3_SQC3_GLPE_SQC_CONFIG_DBL_INDV_DIS_S 3 +#define IG3_SQC3_GLPE_SQC_CONFIG_DBL_INDV_DIS_M RDMA_MASK3(32, 0x7, IG3_SQC3_GLPE_SQC_CONFIG_DBL_INDV_DIS_S) +#define IG3_SQC3_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S 2 +#define IG3_SQC3_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_SQC3_GLPE_SQC_CONFIG_DBL_DIS_S 1 +#define IG3_SQC3_GLPE_SQC_CONFIG_DBL_DIS_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_CONFIG_DBL_DIS_S) +#define IG3_SQC3_GLPE_SQC_CONFIG_COALESCE_DIS_S 0 +#define IG3_SQC3_GLPE_SQC_CONFIG_COALESCE_DIS_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_CONFIG_COALESCE_DIS_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_COUNT 0x43C084B8 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_CMD 0x43C084CC +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_DATA_H 0x43C084D8 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_DATA_L 0x43C084D4 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_PTR 0x43C084D0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_CMD 0x43C084BC +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_DATA_H 0x43C084C8 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_DATA_L 0x43C084C4 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_PTR 0x43C084C0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC3_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL 0x43C08480 +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD1_S 25 +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD2_S 17 +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD2_S) +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD3_S 9 +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD3_S) +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_BYPASS_S 8 +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_CONTROL_BYPASS_S) +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD4_S 1 +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SQC3_GLPE_SQC_DTM_CONTROL_RSVD4_S) +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SQC3_GLPE_SQC_DTM_ECC_COR_ERR 0x43C084E8 +#define IG3_SQC3_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC3_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC3_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SQC3_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SQC3_GLPE_SQC_DTM_ECC_UNCOR_ERR 0x43C084E4 +#define IG3_SQC3_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC3_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC3_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC3_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG 0x43C0848C +#define IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC3_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SQC3_GLPE_SQC_DTM_LOG_CFG 0x43C08490 +#define IG3_SQC3_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SQC3_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SQC3_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SQC3_GLPE_SQC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SQC3_GLPE_SQC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SQC3_GLPE_SQC_DTM_LOG_CFG_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_LOG_CFG_MODE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SQC3_GLPE_SQC_DTM_LOG_CFG_MODE_S) +#define IG3_SQC3_GLPE_SQC_DTM_LOG_MASK 0x43C08498 +#define IG3_SQC3_GLPE_SQC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_LOG_MASK_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_LOG_PATTERN 0x43C08494 +#define IG3_SQC3_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG 0x43C08484 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_STS 0x43C08488 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_RSVD2_S) +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TIMESTAMP 0x43C084B0 +#define IG3_SQC3_GLPE_SQC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_TIMESTAMP_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER 0x43C084B4 +#define IG3_SQC3_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG 0x43C084DC +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS 0x43C084E0 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG 0x43C0849C +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SQC3_GLPE_SQC_DTM_TRIG_CFG_MODE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_COUNT 0x43C084A8 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_MASK 0x43C084A4 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_TRIG_MASK_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_PATTERN 0x43C084A0 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_TIMESTAMP 0x43C084AC +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SQC3_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC3_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI 0x43C08460 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S 26 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S 6 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S 0 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO 0x43C08464 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S 31 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S 29 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S 26 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S) +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S 0 +#define IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S) +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI(_i) 0x43C08420 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_MAX_INDEX_I 7 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S 26 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S) +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_QPID_S 6 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_QPID_S) +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S 0 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC3_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S) +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO(_i) 0x43C08400 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_MAX_INDEX_I 7 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_EN_S 31 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_EN_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_EN_S) +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S 29 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S) +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S 26 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S) +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S 24 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S) +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S 12 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S) +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_PMF_S 0 +#define IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_FWFLUSHDROPLO_PMF_S) +#define IG3_SQC3_GLPE_SQC_FWSYNCRESP(_i) 0x43C08468 + ((_i) * 4) /* _i=0...1 */ +#define IG3_SQC3_GLPE_SQC_FWSYNCRESP_MAX_INDEX_I 1 +#define IG3_SQC3_GLPE_SQC_FWSYNCRESP_RSVD_S 18 +#define IG3_SQC3_GLPE_SQC_FWSYNCRESP_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_SQC3_GLPE_SQC_FWSYNCRESP_RSVD_S) +#define IG3_SQC3_GLPE_SQC_FWSYNCRESP_COUNT_S 8 +#define IG3_SQC3_GLPE_SQC_FWSYNCRESP_COUNT_M RDMA_MASK3(32, 0x3FF, IG3_SQC3_GLPE_SQC_FWSYNCRESP_COUNT_S) +#define IG3_SQC3_GLPE_SQC_FWSYNCRESP_TAG_S 0 +#define IG3_SQC3_GLPE_SQC_FWSYNCRESP_TAG_M RDMA_MASK3(32, 0xFF, IG3_SQC3_GLPE_SQC_FWSYNCRESP_TAG_S) +#define IG3_SQC3_GLPE_SQC_XLR_DROP(_i) 0x43C08440 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC3_GLPE_SQC_XLR_DROP_MAX_INDEX_I 7 +#define IG3_SQC3_GLPE_SQC_XLR_DROP_EN_S 31 +#define IG3_SQC3_GLPE_SQC_XLR_DROP_EN_M RDMA_BIT2(32, IG3_SQC3_GLPE_SQC_XLR_DROP_EN_S) +#define IG3_SQC3_GLPE_SQC_XLR_DROP_RSVD0_S 12 +#define IG3_SQC3_GLPE_SQC_XLR_DROP_RSVD0_M RDMA_MASK3(32, 0x7FFFF, IG3_SQC3_GLPE_SQC_XLR_DROP_RSVD0_S) +#define IG3_SQC3_GLPE_SQC_XLR_DROP_PMF_S 0 +#define IG3_SQC3_GLPE_SQC_XLR_DROP_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_GLPE_SQC_XLR_DROP_PMF_S) +#define IG3_SQC3_SQC_ECC_COR_ERR 0x43C08514 +#define IG3_SQC3_SQC_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC3_SQC_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC3_SQC_ECC_COR_ERR_RSVD_S) +#define IG3_SQC3_SQC_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC3_SQC_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_SQC_ECC_COR_ERR_CNT_S) +#define IG3_SQC3_SQC_ECC_UNCOR_ERR 0x43C08510 +#define IG3_SQC3_SQC_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC3_SQC_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC3_SQC_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC3_SQC_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC3_SQC_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC3_SQC_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG 0x43C08500 +#define IG3_SQC3_SQC_WRK_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC3_SQC_WRK_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC3_SQC_WRK_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_RSVD3_S 20 +#define IG3_SQC3_SQC_WRK_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC3_SQC_WRK_RAM_CFG_RSVD3_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_RM_S 16 +#define IG3_SQC3_SQC_WRK_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC3_SQC_WRK_RAM_CFG_RM_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_RSVD2_S 14 +#define IG3_SQC3_SQC_WRK_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC3_SQC_WRK_RAM_CFG_RSVD2_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC3_SQC_WRK_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_RME_S 12 +#define IG3_SQC3_SQC_WRK_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_RME_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_RSVD1_S 10 +#define IG3_SQC3_SQC_WRK_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC3_SQC_WRK_RAM_CFG_RSVD1_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC3_SQC_WRK_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_ERR_CNT_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC3_SQC_WRK_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_FIX_CNT_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_RSVD0_S 6 +#define IG3_SQC3_SQC_WRK_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC3_SQC_WRK_RAM_CFG_RSVD0_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC3_SQC_WRK_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_MASK_INT_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC3_SQC_WRK_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC3_SQC_WRK_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_LS_FORCE_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC3_SQC_WRK_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC3_SQC_WRK_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC3_SQC_WRK_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC3_SQC_WRK_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_CFG_ECC_EN_S) +#define IG3_SQC3_SQC_WRK_RAM_STATUS 0x43C08504 +#define IG3_SQC3_SQC_WRK_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC3_SQC_WRK_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC3_SQC_WRK_RAM_STATUS_RSVD1_S) +#define IG3_SQC3_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC3_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC3_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC3_SQC_WRK_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC3_SQC_WRK_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC3_SQC_WRK_RAM_STATUS_RSVD0_S) +#define IG3_SQC3_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC3_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC3_SQC_WRK_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC3_SQC_WRK_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC3_SQC_WRK_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC3_SQC_WRK_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC3_SQC_WRK_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC3_SQC_WRK_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC3_SQC_WRK_RAM_STATUS_ECC_ERR_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG 0x43C08508 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD3_S 20 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD3_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RM_S 16 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC3_SQC_XBUF_RAM_CFG_RM_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD2_S 14 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD2_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RME_S 12 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_RME_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD1_S 10 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD1_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_ERR_CNT_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_FIX_CNT_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD0_S 6 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC3_SQC_XBUF_RAM_CFG_RSVD0_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_MASK_INT_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_LS_FORCE_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_CFG_ECC_EN_S) +#define IG3_SQC3_SQC_XBUF_RAM_STATUS 0x43C0850C +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC3_SQC_XBUF_RAM_STATUS_RSVD1_S) +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC3_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC3_SQC_XBUF_RAM_STATUS_RSVD0_S) +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC3_SQC_XBUF_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC3_SQC_XBUF_RAM_STATUS_ECC_ERR_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DOMAIN_ID 0x43C08804 +#define IG3_SFPRX3_GLPE_SFP_RX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPRX3_GLPE_SFP_RX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DOMAIN_ID_RSVD_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPRX3_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_COUNT 0x43C088B8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_CMD 0x43C088CC +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H 0x43C088D8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L 0x43C088D4 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_PTR 0x43C088D0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_CMD 0x43C088BC +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H 0x43C088C8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L 0x43C088C4 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_PTR 0x43C088C0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL 0x43C08880 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_COR_ERR 0x43C088E8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR 0x43C088E4 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG 0x43C0888C +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG 0x43C08890 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_MASK 0x43C08898 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_PATTERN 0x43C08894 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG 0x43C08884 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS 0x43C08888 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TIMESTAMP 0x43C088B0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER 0x43C088B4 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG 0x43C088DC +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS 0x43C088E0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG 0x43C0889C +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_COUNT 0x43C088A8 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_MASK 0x43C088A4 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_PATTERN 0x43C088A0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP 0x43C088AC +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR 0x43C08800 +#define IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S 31 +#define IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR_REQ_M RDMA_BIT2(32, IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S) +#define IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S 12 +#define IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S) +#define IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX3_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S) +#define IG3_SFPRX3_GLPE_SFP_RX_PER_MEM 0x43C08808 +#define IG3_SFPRX3_GLPE_SFP_RX_PER_MEM_RSVD_S 3 +#define IG3_SFPRX3_GLPE_SFP_RX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX3_GLPE_SFP_RX_PER_MEM_RSVD_S) +#define IG3_SFPRX3_GLPE_SFP_RX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPRX3_GLPE_SFP_RX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPRX3_GLPE_SFP_RX_PER_MEM_PER_TYPE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG 0x43C08C08 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS 0x43C08C0C +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_COR_ERR 0x43C08C34 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR 0x43C08C30 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG 0x43C08C18 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS 0x43C08C1C +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG 0x43C08C20 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS 0x43C08C24 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG 0x43C08C00 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS 0x43C08C04 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG 0x43C08C28 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS 0x43C08C2C +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG 0x43C08C10 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS 0x43C08C14 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG 0x43C08C48 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS 0x43C08C4C +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG 0x43C08C40 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS 0x43C08C44 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG 0x43C08C78 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS 0x43C08C7C +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG 0x43C08C50 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS 0x43C08C54 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG 0x43C08C58 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS 0x43C08C5C +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR 0x43C08C84 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR 0x43C08C80 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG 0x43C08C70 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS 0x43C08C74 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG 0x43C08C60 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS 0x43C08C64 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG 0x43C08C68 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS 0x43C08C6C +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG 0x43C08C38 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS 0x43C08C3C +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_COR_ERR 0x43C08CCC +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR 0x43C08CC8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG 0x43C08CD8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS 0x43C08CDC +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL 0x43C08C90 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA 0x43C08C94 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG 0x43C08C88 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS 0x43C08C8C +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL 0x43C08CA0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA 0x43C08CA4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG 0x43C08C98 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS 0x43C08C9C +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL 0x43C08CB0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA 0x43C08CB4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG 0x43C08CA8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS 0x43C08CAC +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL 0x43C08CC0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA 0x43C08CC4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG 0x43C08CB8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS 0x43C08CBC +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG 0x43C08CD0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS 0x43C08CD4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_WTX3_GLPE_WTX_1USCOUNT 0x43C10010 +#define IG3_WTX3_GLPE_WTX_1USCOUNT_CNT_S 0 +#define IG3_WTX3_GLPE_WTX_1USCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_1USCOUNT_CNT_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0 0x43C10120 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1 0x43C10124 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2 0x43C10128 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG3 0x43C1012C +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG4 0x43C10130 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG 0x43C10020 +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD3_S 24 +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD3_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD3_S) +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD2_S 20 +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD2_S) +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S 16 +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S) +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD1_S 12 +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S 8 +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S) +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD0_S 4 +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD0_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_ARB_CONFIG_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S 0 +#define IG3_WTX3_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0 0x43C100F8 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1 0x43C100FC +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2 0x43C10100 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG3 0x43C10104 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG4 0x43C10108 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG 0x43C1017C +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX 0x43C10180 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_CNPCOUNT 0x43C10014 +#define IG3_WTX3_GLPE_WTX_CNPCOUNT_CNT_S 0 +#define IG3_WTX3_GLPE_WTX_CNPCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_CNPCOUNT_CNT_S) +#define IG3_WTX3_GLPE_WTX_CONFIG 0x43C1000C +#define IG3_WTX3_GLPE_WTX_CONFIG_RSVD1_S 28 +#define IG3_WTX3_GLPE_WTX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_CONFIG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_CONFIG_SQ_HSM_ORD_S 25 +#define IG3_WTX3_GLPE_WTX_CONFIG_SQ_HSM_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_CONFIG_SQ_HSM_ORD_S) +#define IG3_WTX3_GLPE_WTX_CONFIG_SQ_WQE_ORD_S 22 +#define IG3_WTX3_GLPE_WTX_CONFIG_SQ_WQE_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_CONFIG_SQ_WQE_ORD_S) +#define IG3_WTX3_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S 21 +#define IG3_WTX3_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S) +#define IG3_WTX3_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S 20 +#define IG3_WTX3_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_WTX3_GLPE_WTX_CONFIG_RSVD0_S 4 +#define IG3_WTX3_GLPE_WTX_CONFIG_RSVD0_M RDMA_MASK3(32, 0xFFFF, IG3_WTX3_GLPE_WTX_CONFIG_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S 3 +#define IG3_WTX3_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S) +#define IG3_WTX3_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S 2 +#define IG3_WTX3_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S) +#define IG3_WTX3_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S 1 +#define IG3_WTX3_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S) +#define IG3_WTX3_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S 0 +#define IG3_WTX3_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG0 0x43C1003C +#define IG3_WTX3_GLPE_WTX_CTCONFIG0_RSVD_S 21 +#define IG3_WTX3_GLPE_WTX_CTCONFIG0_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX3_GLPE_WTX_CTCONFIG0_RSVD_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG0_SCHED_S 0 +#define IG3_WTX3_GLPE_WTX_CTCONFIG0_SCHED_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX3_GLPE_WTX_CTCONFIG0_SCHED_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG1 0x43C10040 +#define IG3_WTX3_GLPE_WTX_CTCONFIG1_RSVD_S 21 +#define IG3_WTX3_GLPE_WTX_CTCONFIG1_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX3_GLPE_WTX_CTCONFIG1_RSVD_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG1_VMRL_S 0 +#define IG3_WTX3_GLPE_WTX_CTCONFIG1_VMRL_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX3_GLPE_WTX_CTCONFIG1_VMRL_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG2 0x43C10044 +#define IG3_WTX3_GLPE_WTX_CTCONFIG2_RSVD_S 30 +#define IG3_WTX3_GLPE_WTX_CTCONFIG2_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_CTCONFIG2_RSVD_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S 16 +#define IG3_WTX3_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S 0 +#define IG3_WTX3_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX3_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG3 0x43C10048 +#define IG3_WTX3_GLPE_WTX_CTCONFIG3_RSVD_S 30 +#define IG3_WTX3_GLPE_WTX_CTCONFIG3_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_CTCONFIG3_RSVD_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S 16 +#define IG3_WTX3_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S 0 +#define IG3_WTX3_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX3_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG4 0x43C1004C +#define IG3_WTX3_GLPE_WTX_CTCONFIG4_RSVD_S 30 +#define IG3_WTX3_GLPE_WTX_CTCONFIG4_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_CTCONFIG4_RSVD_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S 16 +#define IG3_WTX3_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S 0 +#define IG3_WTX3_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX3_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG5 0x43C10050 +#define IG3_WTX3_GLPE_WTX_CTCONFIG5_RSVD_S 20 +#define IG3_WTX3_GLPE_WTX_CTCONFIG5_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_CTCONFIG5_RSVD_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG5_BMPKT_S 0 +#define IG3_WTX3_GLPE_WTX_CTCONFIG5_BMPKT_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX3_GLPE_WTX_CTCONFIG5_BMPKT_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG6 0x43C10054 +#define IG3_WTX3_GLPE_WTX_CTCONFIG6_RSVD_S 13 +#define IG3_WTX3_GLPE_WTX_CTCONFIG6_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_WTX3_GLPE_WTX_CTCONFIG6_RSVD_S) +#define IG3_WTX3_GLPE_WTX_CTCONFIG6_BMHDR_S 0 +#define IG3_WTX3_GLPE_WTX_CTCONFIG6_BMHDR_M RDMA_MASK3(32, 0x1FFF, IG3_WTX3_GLPE_WTX_CTCONFIG6_BMHDR_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_COUNT 0x43C10238 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_CMD 0x43C1024C +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_DATA_H 0x43C10258 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_DATA_L 0x43C10254 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_PTR 0x43C10250 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_CMD 0x43C1023C +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_DATA_H 0x43C10248 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_DATA_L 0x43C10244 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_PTR 0x43C10240 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX3_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL 0x43C10200 +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD2_S) +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD3_S) +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_CONTROL_BYPASS_S) +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WTX3_GLPE_WTX_DTM_CONTROL_RSVD4_S) +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WTX3_GLPE_WTX_DTM_ECC_COR_ERR 0x43C10268 +#define IG3_WTX3_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX3_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WTX3_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WTX3_GLPE_WTX_DTM_ECC_UNCOR_ERR 0x43C10264 +#define IG3_WTX3_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX3_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WTX3_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG 0x43C1020C +#define IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WTX3_GLPE_WTX_DTM_LOG_CFG 0x43C10210 +#define IG3_WTX3_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WTX3_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WTX3_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WTX3_GLPE_WTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WTX3_GLPE_WTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_DTM_LOG_CFG_MODE_S) +#define IG3_WTX3_GLPE_WTX_DTM_LOG_MASK 0x43C10218 +#define IG3_WTX3_GLPE_WTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_LOG_MASK_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_LOG_PATTERN 0x43C10214 +#define IG3_WTX3_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG 0x43C10204 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_STS 0x43C10208 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TIMESTAMP 0x43C10230 +#define IG3_WTX3_GLPE_WTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER 0x43C10234 +#define IG3_WTX3_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG 0x43C1025C +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS 0x43C10260 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG 0x43C1021C +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_DTM_TRIG_CFG_MODE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_COUNT 0x43C10228 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_MASK 0x43C10224 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_PATTERN 0x43C10220 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_TIMESTAMP 0x43C1022C +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WTX3_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG 0x43C1014C +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG 0x43C10150 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX 0x43C10154 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHHI 0x43C1005C +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX3_GLPE_WTX_FWQPFLUSHHI_QPID_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO 0x43C10058 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_BUSY_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_FWQPFLUSHLO_PMF_S) +#define IG3_WTX3_GLPE_WTX_HOST_READ_CONFIG 0x43C10038 +#define IG3_WTX3_GLPE_WTX_HOST_READ_CONFIG_RSVD_S 8 +#define IG3_WTX3_GLPE_WTX_HOST_READ_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_HOST_READ_CONFIG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S 0 +#define IG3_WTX3_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0 0x43C1010C +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1 0x43C10110 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2 0x43C10114 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG3 0x43C10118 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG4 0x43C1011C +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG 0x43C1018C +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX 0x43C10190 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG 0x43C10194 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX 0x43C10198 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG 0x43C10184 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX 0x43C10188 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0 0x43C10090 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1 0x43C10094 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2 0x43C10098 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG3 0x43C1009C +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG4 0x43C100A0 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0 0x43C10060 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1 0x43C10064 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2 0x43C10068 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG3 0x43C1006C +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG4 0x43C10070 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG5 0x43C10074 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0 0x43C10078 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1 0x43C1007C +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2 0x43C10080 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG3 0x43C10084 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG4 0x43C10088 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG5 0x43C1008C +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG 0x43C10134 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG 0x43C10138 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX 0x43C1013C +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG 0x43C10140 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG 0x43C10144 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX 0x43C10148 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG 0x43C10164 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG 0x43C10168 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX 0x43C1016C +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG 0x43C10158 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG 0x43C1015C +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX 0x43C10160 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0 0x43C100E4 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1 0x43C100E8 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2 0x43C100EC +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG3 0x43C100F0 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG4 0x43C100F4 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0 0x43C100D0 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1 0x43C100D4 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2 0x43C100D8 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG3 0x43C100DC +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG4 0x43C100E0 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED(_i) 0x43C10000 + ((_i) * 4) /* _i=0...2 */ +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_MAX_INDEX_I 2 +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S 24 +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD3_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S) +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S 16 +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD2_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S) +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S 8 +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S) +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S 0 +#define IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD0_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0 0x43C100A4 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1 0x43C100A8 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2 0x43C100AC +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG3 0x43C100B0 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG4 0x43C100B4 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG5 0x43C100B8 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG0 0x43C10024 +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S 24 +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S) +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S 16 +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S) +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S 8 +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S) +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S) +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG1 0x43C10028 +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG1_RSVD_S 8 +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_CONFIG1_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S) +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0 0x43C1002C +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S 24 +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S) +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S 16 +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S) +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S 8 +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S) +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S) +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS1 0x43C10030 +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S 8 +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0 0x43C100BC +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1 0x43C100C0 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2 0x43C100C4 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG3 0x43C100C8 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG4 0x43C100CC +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S) +#define IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL 0x43C10034 +#define IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S 16 +#define IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S 8 +#define IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S) +#define IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S) +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL 0x43C10018 +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S 20 +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S 16 +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_M RDMA_MASK3(32, 0xF, IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S) +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S 10 +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S 8 +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_M RDMA_MASK3(32, 0x3, IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S) +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_M RDMA_MASK3(32, 0xFF, IG3_WTX3_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S) +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_DATA 0x43C1001C +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_DATA_DATA_S 0 +#define IG3_WTX3_GLPE_WTX_SPAD_STAT_DATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX3_GLPE_WTX_SPAD_STAT_DATA_DATA_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG 0x43C10170 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG 0x43C10174 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX 0x43C10178 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX3_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_PTX3_GLPE_ARPCONTROL 0x43C1400C +#define IG3_PTX3_GLPE_ARPCONTROL_ARP_LOCK_ACK_S 31 +#define IG3_PTX3_GLPE_ARPCONTROL_ARP_LOCK_ACK_M RDMA_BIT2(32, IG3_PTX3_GLPE_ARPCONTROL_ARP_LOCK_ACK_S) +#define IG3_PTX3_GLPE_ARPCONTROL_ARP_LOCK_REQ_S 30 +#define IG3_PTX3_GLPE_ARPCONTROL_ARP_LOCK_REQ_M RDMA_BIT2(32, IG3_PTX3_GLPE_ARPCONTROL_ARP_LOCK_REQ_S) +#define IG3_PTX3_GLPE_ARPCONTROL_RSVD_S 16 +#define IG3_PTX3_GLPE_ARPCONTROL_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_PTX3_GLPE_ARPCONTROL_RSVD_S) +#define IG3_PTX3_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S 0 +#define IG3_PTX3_GLPE_ARPCONTROL_ARP_LOCK_INDEX_M RDMA_MASK3(32, 0xFFFF, IG3_PTX3_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S) +#define IG3_PTX3_GLPE_CRT_CONFIG0 0x43C14010 +#define IG3_PTX3_GLPE_CRT_CONFIG0_RSVD_S 25 +#define IG3_PTX3_GLPE_CRT_CONFIG0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_CRT_CONFIG0_RSVD_S) +#define IG3_PTX3_GLPE_CRT_CONFIG0_QP_FC_EN_S 24 +#define IG3_PTX3_GLPE_CRT_CONFIG0_QP_FC_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_CRT_CONFIG0_QP_FC_EN_S) +#define IG3_PTX3_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S 16 +#define IG3_PTX3_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S) +#define IG3_PTX3_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S 8 +#define IG3_PTX3_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S) +#define IG3_PTX3_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S 0 +#define IG3_PTX3_GLPE_CRT_CONFIG0_TX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S) +#define IG3_PTX3_GLPE_CRT_CONFIG1 0x43C14014 +#define IG3_PTX3_GLPE_CRT_CONFIG1_RSVD_S 19 +#define IG3_PTX3_GLPE_CRT_CONFIG1_RSVD_M RDMA_MASK3(32, 0x1FFF, IG3_PTX3_GLPE_CRT_CONFIG1_RSVD_S) +#define IG3_PTX3_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S 16 +#define IG3_PTX3_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_M RDMA_MASK3(32, 0x7, IG3_PTX3_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S) +#define IG3_PTX3_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S 8 +#define IG3_PTX3_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S) +#define IG3_PTX3_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S 0 +#define IG3_PTX3_GLPE_CRT_CONFIG1_RX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S) +#define IG3_PTX3_GLPE_MAX_INLINE_DATA 0x43C14000 +#define IG3_PTX3_GLPE_MAX_INLINE_DATA_RSVD_S 8 +#define IG3_PTX3_GLPE_MAX_INLINE_DATA_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX3_GLPE_MAX_INLINE_DATA_RSVD_S) +#define IG3_PTX3_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S 0 +#define IG3_PTX3_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S) +#define IG3_PTX3_GLPE_MAX_TCP_ACKS 0x43C14004 +#define IG3_PTX3_GLPE_MAX_TCP_ACKS_RSVD_S 8 +#define IG3_PTX3_GLPE_MAX_TCP_ACKS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX3_GLPE_MAX_TCP_ACKS_RSVD_S) +#define IG3_PTX3_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S 0 +#define IG3_PTX3_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0 0x43C14018 +#define IG3_PTX3_GLPE_PTX_CONFIG0_RSVD_31_S 31 +#define IG3_PTX3_GLPE_PTX_CONFIG0_RSVD_31_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_RSVD_31_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S 30 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S 29 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S 28 +#define IG3_PTX3_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S 27 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S 26 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S 22 +#define IG3_PTX3_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_M RDMA_MASK3(32, 0xF, IG3_PTX3_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S 21 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S 20 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_RSVD_19_S 19 +#define IG3_PTX3_GLPE_PTX_CONFIG0_RSVD_19_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_RSVD_19_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S 18 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S 17 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S 16 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S 15 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S 14 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_RSVD_13_7_S 7 +#define IG3_PTX3_GLPE_PTX_CONFIG0_RSVD_13_7_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_PTX_CONFIG0_RSVD_13_7_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_UDP_CS_EN_S 6 +#define IG3_PTX3_GLPE_PTX_CONFIG0_UDP_CS_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_UDP_CS_EN_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S 5 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_Q1_PACING_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S 4 +#define IG3_PTX3_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S 3 +#define IG3_PTX3_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S 1 +#define IG3_PTX3_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S) +#define IG3_PTX3_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S 0 +#define IG3_PTX3_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S) +#define IG3_PTX3_GLPE_PTX_CONFIG1 0x43C1401C +#define IG3_PTX3_GLPE_PTX_CONFIG1_RSVD_S 24 +#define IG3_PTX3_GLPE_PTX_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_CONFIG1_RSVD_S) +#define IG3_PTX3_GLPE_PTX_CONFIG1_ACKREQ_PACING_S 21 +#define IG3_PTX3_GLPE_PTX_CONFIG1_ACKREQ_PACING_M RDMA_MASK3(32, 0x7, IG3_PTX3_GLPE_PTX_CONFIG1_ACKREQ_PACING_S) +#define IG3_PTX3_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S 16 +#define IG3_PTX3_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_M RDMA_MASK3(32, 0x1F, IG3_PTX3_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S) +#define IG3_PTX3_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S 0 +#define IG3_PTX3_GLPE_PTX_CONFIG1_Q1_PACING_MULT_M RDMA_MASK3(32, 0xFFFF, IG3_PTX3_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S) +#define IG3_PTX3_GLPE_PTX_CONFIG2 0x43C14020 +#define IG3_PTX3_GLPE_PTX_CONFIG2_SEND2CPU_S 0 +#define IG3_PTX3_GLPE_PTX_CONFIG2_SEND2CPU_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_CONFIG2_SEND2CPU_S) +#define IG3_PTX3_GLPE_PTX_CRT_XMIT_PTR 0x43C1402C +#define IG3_PTX3_GLPE_PTX_CRT_XMIT_PTR_RSVD_S 8 +#define IG3_PTX3_GLPE_PTX_CRT_XMIT_PTR_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX3_GLPE_PTX_CRT_XMIT_PTR_RSVD_S) +#define IG3_PTX3_GLPE_PTX_CRT_XMIT_PTR_COUNT_S 0 +#define IG3_PTX3_GLPE_PTX_CRT_XMIT_PTR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_CRT_XMIT_PTR_COUNT_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_COUNT 0x43C14138 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_CMD 0x43C1414C +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_DATA_H 0x43C14158 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_DATA_L 0x43C14154 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_PTR 0x43C14150 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_CMD 0x43C1413C +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_DATA_H 0x43C14148 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_DATA_L 0x43C14144 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_PTR 0x43C14140 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX3_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL 0x43C14100 +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD2_S) +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD3_S) +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_CONTROL_BYPASS_S) +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_PTX_DTM_CONTROL_RSVD4_S) +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PTX3_GLPE_PTX_DTM_ECC_COR_ERR 0x43C14168 +#define IG3_PTX3_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PTX3_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX3_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PTX3_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PTX3_GLPE_PTX_DTM_ECC_UNCOR_ERR 0x43C14164 +#define IG3_PTX3_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PTX3_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX3_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PTX3_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG 0x43C1410C +#define IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PTX3_GLPE_PTX_DTM_LOG_CFG 0x43C14110 +#define IG3_PTX3_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PTX3_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PTX3_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PTX3_GLPE_PTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PTX3_GLPE_PTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PTX3_GLPE_PTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_DTM_LOG_CFG_MODE_S) +#define IG3_PTX3_GLPE_PTX_DTM_LOG_MASK 0x43C14118 +#define IG3_PTX3_GLPE_PTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_LOG_MASK_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_LOG_PATTERN 0x43C14114 +#define IG3_PTX3_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG 0x43C14104 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_STS 0x43C14108 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TIMESTAMP 0x43C14130 +#define IG3_PTX3_GLPE_PTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER 0x43C14134 +#define IG3_PTX3_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG 0x43C1415C +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS 0x43C14160 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG 0x43C1411C +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PTX3_GLPE_PTX_DTM_TRIG_CFG_MODE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_COUNT 0x43C14128 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_MASK 0x43C14124 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_PATTERN 0x43C14120 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_TIMESTAMP 0x43C1412C +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PTX3_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHHI 0x43C14028 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_PTX3_GLPE_PTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX3_GLPE_PTX_FWQPFLUSHHI_QPID_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX3_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO 0x43C14024 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_BUSY_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_FWQPFLUSHLO_PMF_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0 0x43C14044 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_TAG_S 16 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_TAG_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_MODE_S 11 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_MODE_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1 0x43C14048 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_PMF_S 0 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG1_PMF_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2 0x43C1404C +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2_QPID_S 6 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2_QPID_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG3 0x43C14050 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG4 0x43C14054 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0 0x43C14058 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_TAG_S 16 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_TAG_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_MODE_S 11 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_MODE_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1 0x43C1405C +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_PMF_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG1_PMF_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2 0x43C14060 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2_QPID_S 6 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2_QPID_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG3 0x43C14064 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG4 0x43C14068 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT0 0x43C14078 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S 1 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT1 0x43C1407C +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT2 0x43C14080 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE0 0x43C1406C +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S 1 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE1 0x43C14070 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S 24 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE2 0x43C14074 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S 24 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S) +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S 0 +#define IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX3_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0 0x43C14030 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S 16 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S 11 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1 0x43C14034 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S 0 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2 0x43C14038 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S 6 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG3 0x43C1403C +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG4 0x43C14040 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX3_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S) +#define IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD 0x43C14008 +#define IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S 25 +#define IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S) +#define IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S 24 +#define IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_M RDMA_BIT2(32, IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S) +#define IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S 0 +#define IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX3_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_COUNT 0x43C144B8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_CMD 0x43C144CC +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_DATA_H 0x43C144D8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_DATA_L 0x43C144D4 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_PTR 0x43C144D0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_CMD 0x43C144BC +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_DATA_H 0x43C144C8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_DATA_L 0x43C144C4 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_PTR 0x43C144C0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL 0x43C14480 +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD2_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD3_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_BYPASS_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_RSVD4_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_COR_ERR 0x43C144E8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX3_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_UNCOR_ERR 0x43C144E4 +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX3_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG 0x43C1448C +#define IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX3_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG 0x43C14490 +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX3_GLPE_SFPT_DTM_LOG_CFG_MODE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_MASK 0x43C14498 +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_PATTERN 0x43C14494 +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG 0x43C14484 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS 0x43C14488 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TIMESTAMP 0x43C144B0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER 0x43C144B4 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG 0x43C144DC +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS 0x43C144E0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPTX3_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG 0x43C1449C +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_COUNT 0x43C144A8 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_MASK 0x43C144A4 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_PATTERN 0x43C144A0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_TIMESTAMP 0x43C144AC +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX3_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPTX3_GLPE_SFP_TX_DOMAIN_ID 0x43C14400 +#define IG3_SFPTX3_GLPE_SFP_TX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPTX3_GLPE_SFP_TX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX3_GLPE_SFP_TX_DOMAIN_ID_RSVD_S) +#define IG3_SFPTX3_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPTX3_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPTX3_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPTX3_GLPE_SFP_TX_PER_MEM 0x43C14404 +#define IG3_SFPTX3_GLPE_SFP_TX_PER_MEM_RSVD_S 3 +#define IG3_SFPTX3_GLPE_SFP_TX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX3_GLPE_SFP_TX_PER_MEM_RSVD_S) +#define IG3_SFPTX3_GLPE_SFP_TX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPTX3_GLPE_SFP_TX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPTX3_GLPE_SFP_TX_PER_MEM_PER_TYPE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG 0x43C14800 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS 0x43C14804 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG 0x43C14810 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS 0x43C14814 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_COR_ERR 0x43C14834 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR 0x43C14830 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG 0x43C14818 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS 0x43C1481C +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG 0x43C14808 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS 0x43C1480C +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG 0x43C14828 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS 0x43C1482C +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG 0x43C14820 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS 0x43C14824 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG 0x43C14840 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS 0x43C14844 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG 0x43C14848 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS 0x43C1484C +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG 0x43C14850 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS 0x43C14854 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG 0x43C14858 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS 0x43C1485C +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR 0x43C1487C +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR 0x43C14878 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG 0x43C14860 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS 0x43C14864 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG 0x43C14868 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS 0x43C1486C +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG 0x43C14870 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS 0x43C14874 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG 0x43C14838 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS 0x43C1483C +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL 0x43C148C8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S 31 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_DATA 0x43C148CC +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG 0x43C148C0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS 0x43C148C4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_COR_ERR 0x43C148E4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR 0x43C148E0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL 0x43C148D8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S 31 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA 0x43C148DC +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG 0x43C148D0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS 0x43C148D4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL 0x43C14888 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA 0x43C1488C +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG 0x43C14880 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS 0x43C14884 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL 0x43C14898 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA 0x43C1489C +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG 0x43C14890 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS 0x43C14894 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL 0x43C148A8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA 0x43C148AC +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG 0x43C148A0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS 0x43C148A4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL 0x43C148B8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA 0x43C148BC +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG 0x43C148B0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS 0x43C148B4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE3_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_DRX3_GLPE_DRX_CONFIG 0x43C20000 +#define IG3_DRX3_GLPE_DRX_CONFIG_RSVD1_S 3 +#define IG3_DRX3_GLPE_DRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_DRX3_GLPE_DRX_CONFIG_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_CONFIG_CRC_MASK_S 0 +#define IG3_DRX3_GLPE_DRX_CONFIG_CRC_MASK_M RDMA_MASK3(32, 0x7, IG3_DRX3_GLPE_DRX_CONFIG_CRC_MASK_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_COUNT 0x43C200B8 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_CMD 0x43C200CC +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_DATA_H 0x43C200D8 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_DATA_L 0x43C200D4 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_PTR 0x43C200D0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_CMD 0x43C200BC +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_DATA_H 0x43C200C8 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_DATA_L 0x43C200C4 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_PTR 0x43C200C0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX3_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL 0x43C20080 +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD2_S) +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD3_S) +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_CONTROL_BYPASS_S) +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_DRX3_GLPE_DRX_DTM_CONTROL_RSVD4_S) +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_DRX3_GLPE_DRX_DTM_ECC_COR_ERR 0x43C200E8 +#define IG3_DRX3_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX3_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX3_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_DRX3_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX3_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_DRX3_GLPE_DRX_DTM_ECC_UNCOR_ERR 0x43C200E4 +#define IG3_DRX3_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX3_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX3_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX3_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX3_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG 0x43C2008C +#define IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX3_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_DRX3_GLPE_DRX_DTM_LOG_CFG 0x43C20090 +#define IG3_DRX3_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_DRX3_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_DRX3_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_DRX3_GLPE_DRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_DRX3_GLPE_DRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_DRX3_GLPE_DRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_DRX_DTM_LOG_CFG_MODE_S) +#define IG3_DRX3_GLPE_DRX_DTM_LOG_MASK 0x43C20098 +#define IG3_DRX3_GLPE_DRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_LOG_MASK_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_LOG_PATTERN 0x43C20094 +#define IG3_DRX3_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG 0x43C20084 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_STS 0x43C20088 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TIMESTAMP 0x43C200B0 +#define IG3_DRX3_GLPE_DRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER 0x43C200B4 +#define IG3_DRX3_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG 0x43C200DC +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS 0x43C200E0 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX3_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG 0x43C2009C +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_DRX3_GLPE_DRX_DTM_TRIG_CFG_MODE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_COUNT 0x43C200A8 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_MASK 0x43C200A4 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_PATTERN 0x43C200A0 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_TIMESTAMP 0x43C200AC +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_DRX3_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX3_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_DRX3_GLPE_DRX_ECC_COR_ERR 0x43C20004 +#define IG3_DRX3_GLPE_DRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX3_GLPE_DRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX3_GLPE_DRX_ECC_COR_ERR_RSVD_S) +#define IG3_DRX3_GLPE_DRX_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX3_GLPE_DRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX3_GLPE_DRX_ECC_COR_ERR_CNT_S) +#define IG3_DRX3_GLPE_DRX_ECC_UNCOR_ERR 0x43C20008 +#define IG3_DRX3_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX3_GLPE_DRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX3_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX3_GLPE_DRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX3_GLPE_DRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX3_GLPE_DRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX3_GLPE_PBUF_CFG 0x43C2000C +#define IG3_DRX3_GLPE_PBUF_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX3_GLPE_PBUF_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX3_GLPE_PBUF_CFG_ECC_INST_NUM_S) +#define IG3_DRX3_GLPE_PBUF_CFG_RSVD3_S 20 +#define IG3_DRX3_GLPE_PBUF_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX3_GLPE_PBUF_CFG_RSVD3_S) +#define IG3_DRX3_GLPE_PBUF_CFG_RM_S 16 +#define IG3_DRX3_GLPE_PBUF_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX3_GLPE_PBUF_CFG_RM_S) +#define IG3_DRX3_GLPE_PBUF_CFG_RSVD2_S 14 +#define IG3_DRX3_GLPE_PBUF_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_PBUF_CFG_RSVD2_S) +#define IG3_DRX3_GLPE_PBUF_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX3_GLPE_PBUF_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_POWER_GATE_EN_S) +#define IG3_DRX3_GLPE_PBUF_CFG_RME_S 12 +#define IG3_DRX3_GLPE_PBUF_CFG_RME_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_RME_S) +#define IG3_DRX3_GLPE_PBUF_CFG_RSVD1_S 10 +#define IG3_DRX3_GLPE_PBUF_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_PBUF_CFG_RSVD1_S) +#define IG3_DRX3_GLPE_PBUF_CFG_ERR_CNT_S 9 +#define IG3_DRX3_GLPE_PBUF_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_ERR_CNT_S) +#define IG3_DRX3_GLPE_PBUF_CFG_FIX_CNT_S 8 +#define IG3_DRX3_GLPE_PBUF_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_FIX_CNT_S) +#define IG3_DRX3_GLPE_PBUF_CFG_RSVD0_S 6 +#define IG3_DRX3_GLPE_PBUF_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_PBUF_CFG_RSVD0_S) +#define IG3_DRX3_GLPE_PBUF_CFG_MASK_INT_S 5 +#define IG3_DRX3_GLPE_PBUF_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_MASK_INT_S) +#define IG3_DRX3_GLPE_PBUF_CFG_LS_BYPASS_S 4 +#define IG3_DRX3_GLPE_PBUF_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_LS_BYPASS_S) +#define IG3_DRX3_GLPE_PBUF_CFG_LS_FORCE_S 3 +#define IG3_DRX3_GLPE_PBUF_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_LS_FORCE_S) +#define IG3_DRX3_GLPE_PBUF_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX3_GLPE_PBUF_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_ECC_INVERT_2_S) +#define IG3_DRX3_GLPE_PBUF_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX3_GLPE_PBUF_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_ECC_INVERT_1_S) +#define IG3_DRX3_GLPE_PBUF_CFG_ECC_EN_S 0 +#define IG3_DRX3_GLPE_PBUF_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_CFG_ECC_EN_S) +#define IG3_DRX3_GLPE_PBUF_STATUS 0x43C20010 +#define IG3_DRX3_GLPE_PBUF_STATUS_RSVD1_S 30 +#define IG3_DRX3_GLPE_PBUF_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX3_GLPE_PBUF_STATUS_RSVD1_S) +#define IG3_DRX3_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX3_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX3_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX3_GLPE_PBUF_STATUS_RSVD0_S 4 +#define IG3_DRX3_GLPE_PBUF_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX3_GLPE_PBUF_STATUS_RSVD0_S) +#define IG3_DRX3_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX3_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX3_GLPE_PBUF_STATUS_INIT_DONE_S 2 +#define IG3_DRX3_GLPE_PBUF_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_STATUS_INIT_DONE_S) +#define IG3_DRX3_GLPE_PBUF_STATUS_ECC_FIX_S 1 +#define IG3_DRX3_GLPE_PBUF_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_STATUS_ECC_FIX_S) +#define IG3_DRX3_GLPE_PBUF_STATUS_ECC_ERR_S 0 +#define IG3_DRX3_GLPE_PBUF_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX3_GLPE_PBUF_STATUS_ECC_ERR_S) +#define IG3_CMPE3_CMPE_ECC_COR_ERR 0x43C2053C +#define IG3_CMPE3_CMPE_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE3_CMPE_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_CMPE_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE3_CMPE_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE3_CMPE_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_CMPE_ECC_COR_ERR_CNT_S) +#define IG3_CMPE3_CMPE_ECC_UNCOR_ERR 0x43C20538 +#define IG3_CMPE3_CMPE_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE3_CMPE_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_CMPE_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE3_CMPE_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE3_CMPE_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_CMPE_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE3_GLCM_PECLSADDR 0x43C20484 +#define IG3_CMPE3_GLCM_PECLSADDR_RSVD_S 9 +#define IG3_CMPE3_GLCM_PECLSADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE3_GLCM_PECLSADDR_RSVD_S) +#define IG3_CMPE3_GLCM_PECLSADDR_CLS_ADDR_S 0 +#define IG3_CMPE3_GLCM_PECLSADDR_CLS_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE3_GLCM_PECLSADDR_CLS_ADDR_S) +#define IG3_CMPE3_GLCM_PECLSDATA0 0x43C20488 +#define IG3_CMPE3_GLCM_PECLSDATA0_CLS_DATA_S 0 +#define IG3_CMPE3_GLCM_PECLSDATA0_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLCM_PECLSDATA0_CLS_DATA_S) +#define IG3_CMPE3_GLCM_PECLSDATA1 0x43C2048C +#define IG3_CMPE3_GLCM_PECLSDATA1_CLS_DATA_S 0 +#define IG3_CMPE3_GLCM_PECLSDATA1_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLCM_PECLSDATA1_CLS_DATA_S) +#define IG3_CMPE3_GLCM_PECLSDATA2 0x43C20490 +#define IG3_CMPE3_GLCM_PECLSDATA2_CLS_DATA_S 0 +#define IG3_CMPE3_GLCM_PECLSDATA2_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLCM_PECLSDATA2_CLS_DATA_S) +#define IG3_CMPE3_GLCM_PECONFIG 0x43C20480 +#define IG3_CMPE3_GLCM_PECONFIG_DBGMUX_EN_S 31 +#define IG3_CMPE3_GLCM_PECONFIG_DBGMUX_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_DBGMUX_EN_S) +#define IG3_CMPE3_GLCM_PECONFIG_RSVD13_S 30 +#define IG3_CMPE3_GLCM_PECONFIG_RSVD13_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_RSVD13_S) +#define IG3_CMPE3_GLCM_PECONFIG_DBGMUX_SEL_HI_S 25 +#define IG3_CMPE3_GLCM_PECONFIG_DBGMUX_SEL_HI_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PECONFIG_DBGMUX_SEL_HI_S) +#define IG3_CMPE3_GLCM_PECONFIG_DBGMUX_SEL_LO_S 20 +#define IG3_CMPE3_GLCM_PECONFIG_DBGMUX_SEL_LO_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PECONFIG_DBGMUX_SEL_LO_S) +#define IG3_CMPE3_GLCM_PECONFIG_RSVD10_S 17 +#define IG3_CMPE3_GLCM_PECONFIG_RSVD10_M RDMA_MASK3(32, 0x7, IG3_CMPE3_GLCM_PECONFIG_RSVD10_S) +#define IG3_CMPE3_GLCM_PECONFIG_DBG_WRSEL_S 16 +#define IG3_CMPE3_GLCM_PECONFIG_DBG_WRSEL_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_DBG_WRSEL_S) +#define IG3_CMPE3_GLCM_PECONFIG_DBG_DWSEL_S 14 +#define IG3_CMPE3_GLCM_PECONFIG_DBG_DWSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PECONFIG_DBG_DWSEL_S) +#define IG3_CMPE3_GLCM_PECONFIG_DBG_DPSEL_S 12 +#define IG3_CMPE3_GLCM_PECONFIG_DBG_DPSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PECONFIG_DBG_DPSEL_S) +#define IG3_CMPE3_GLCM_PECONFIG_RSVD6_S 7 +#define IG3_CMPE3_GLCM_PECONFIG_RSVD6_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PECONFIG_RSVD6_S) +#define IG3_CMPE3_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S 6 +#define IG3_CMPE3_GLCM_PECONFIG_DISABLE_CTXT_PACKING_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S) +#define IG3_CMPE3_GLCM_PECONFIG_DISABLE_LSA_S 5 +#define IG3_CMPE3_GLCM_PECONFIG_DISABLE_LSA_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_DISABLE_LSA_S) +#define IG3_CMPE3_GLCM_PECONFIG_ENABLE_CRC_S 4 +#define IG3_CMPE3_GLCM_PECONFIG_ENABLE_CRC_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_ENABLE_CRC_S) +#define IG3_CMPE3_GLCM_PECONFIG_DISABLE_RESCHEDULE_S 3 +#define IG3_CMPE3_GLCM_PECONFIG_DISABLE_RESCHEDULE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_DISABLE_RESCHEDULE_S) +#define IG3_CMPE3_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S 2 +#define IG3_CMPE3_GLCM_PECONFIG_DISABLE_PACKET_COUNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S) +#define IG3_CMPE3_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S 1 +#define IG3_CMPE3_GLCM_PECONFIG_GLOBAL_LOCK_MODE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S) +#define IG3_CMPE3_GLCM_PECONFIG_RSVD1_S 0 +#define IG3_CMPE3_GLCM_PECONFIG_RSVD1_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECONFIG_RSVD1_S) +#define IG3_CMPE3_GLCM_PECTXDGCTL 0x43C204C8 +#define IG3_CMPE3_GLCM_PECTXDGCTL_RSVD_S 12 +#define IG3_CMPE3_GLCM_PECTXDGCTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_GLCM_PECTXDGCTL_RSVD_S) +#define IG3_CMPE3_GLCM_PECTXDGCTL_PKTCNT_S 10 +#define IG3_CMPE3_GLCM_PECTXDGCTL_PKTCNT_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PECTXDGCTL_PKTCNT_S) +#define IG3_CMPE3_GLCM_PECTXDGCTL_OP_CODE_S 8 +#define IG3_CMPE3_GLCM_PECTXDGCTL_OP_CODE_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PECTXDGCTL_OP_CODE_S) +#define IG3_CMPE3_GLCM_PECTXDGCTL_ALLOCATE_S 7 +#define IG3_CMPE3_GLCM_PECTXDGCTL_ALLOCATE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECTXDGCTL_ALLOCATE_S) +#define IG3_CMPE3_GLCM_PECTXDGCTL_WRITEBACK_S 6 +#define IG3_CMPE3_GLCM_PECTXDGCTL_WRITEBACK_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECTXDGCTL_WRITEBACK_S) +#define IG3_CMPE3_GLCM_PECTXDGCTL_INVALIDATE_S 5 +#define IG3_CMPE3_GLCM_PECTXDGCTL_INVALIDATE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECTXDGCTL_INVALIDATE_S) +#define IG3_CMPE3_GLCM_PECTXDGCTL_SUB_LINE_S 0 +#define IG3_CMPE3_GLCM_PECTXDGCTL_SUB_LINE_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PECTXDGCTL_SUB_LINE_S) +#define IG3_CMPE3_GLCM_PECTXDGDATA(_i) 0x43C204CC + ((_i) * 4) /* _i=0...3 */ +#define IG3_CMPE3_GLCM_PECTXDGDATA_MAX_INDEX_I 3 +#define IG3_CMPE3_GLCM_PECTXDGDATA_DATA_S 0 +#define IG3_CMPE3_GLCM_PECTXDGDATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLCM_PECTXDGDATA_DATA_S) +#define IG3_CMPE3_GLCM_PECTXDGFN 0x43C204C0 +#define IG3_CMPE3_GLCM_PECTXDGFN_RSVD_S 20 +#define IG3_CMPE3_GLCM_PECTXDGFN_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLCM_PECTXDGFN_RSVD_S) +#define IG3_CMPE3_GLCM_PECTXDGFN_FUNC_TRIPLET_S 0 +#define IG3_CMPE3_GLCM_PECTXDGFN_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_GLCM_PECTXDGFN_FUNC_TRIPLET_S) +#define IG3_CMPE3_GLCM_PECTXDGQP 0x43C204C4 +#define IG3_CMPE3_GLCM_PECTXDGQP_RSVD_S 24 +#define IG3_CMPE3_GLCM_PECTXDGQP_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PECTXDGQP_RSVD_S) +#define IG3_CMPE3_GLCM_PECTXDGQP_QUEUE_NUM_S 0 +#define IG3_CMPE3_GLCM_PECTXDGQP_QUEUE_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE3_GLCM_PECTXDGQP_QUEUE_NUM_S) +#define IG3_CMPE3_GLCM_PECTXDGSTAT 0x43C204DC +#define IG3_CMPE3_GLCM_PECTXDGSTAT_RSVD_S 2 +#define IG3_CMPE3_GLCM_PECTXDGSTAT_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE3_GLCM_PECTXDGSTAT_RSVD_S) +#define IG3_CMPE3_GLCM_PECTXDGSTAT_CTX_MISS_S 1 +#define IG3_CMPE3_GLCM_PECTXDGSTAT_CTX_MISS_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECTXDGSTAT_CTX_MISS_S) +#define IG3_CMPE3_GLCM_PECTXDGSTAT_CTX_DONE_S 0 +#define IG3_CMPE3_GLCM_PECTXDGSTAT_CTX_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PECTXDGSTAT_CTX_DONE_S) +#define IG3_CMPE3_GLCM_PEDATAREQHI 0x43C204B4 +#define IG3_CMPE3_GLCM_PEDATAREQHI_RSVD_S 24 +#define IG3_CMPE3_GLCM_PEDATAREQHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PEDATAREQHI_RSVD_S) +#define IG3_CMPE3_GLCM_PEDATAREQHI_DATAREQHI_S 0 +#define IG3_CMPE3_GLCM_PEDATAREQHI_DATAREQHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE3_GLCM_PEDATAREQHI_DATAREQHI_S) +#define IG3_CMPE3_GLCM_PEDATAREQLO 0x43C204B0 +#define IG3_CMPE3_GLCM_PEDATAREQLO_DATAREQLOW_S 0 +#define IG3_CMPE3_GLCM_PEDATAREQLO_DATAREQLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLCM_PEDATAREQLO_DATAREQLOW_S) +#define IG3_CMPE3_GLCM_PEDATASTALLHI 0x43C204BC +#define IG3_CMPE3_GLCM_PEDATASTALLHI_RSVD_S 24 +#define IG3_CMPE3_GLCM_PEDATASTALLHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PEDATASTALLHI_RSVD_S) +#define IG3_CMPE3_GLCM_PEDATASTALLHI_DATASTALLHI_S 0 +#define IG3_CMPE3_GLCM_PEDATASTALLHI_DATASTALLHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE3_GLCM_PEDATASTALLHI_DATASTALLHI_S) +#define IG3_CMPE3_GLCM_PEDATASTALLLO 0x43C204B8 +#define IG3_CMPE3_GLCM_PEDATASTALLLO_DATASTALLLOW_S 0 +#define IG3_CMPE3_GLCM_PEDATASTALLLO_DATASTALLLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLCM_PEDATASTALLLO_DATASTALLLOW_S) +#define IG3_CMPE3_GLCM_PELOCKTBLADDR 0x43C2049C +#define IG3_CMPE3_GLCM_PELOCKTBLADDR_RSVD_S 5 +#define IG3_CMPE3_GLCM_PELOCKTBLADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_CMPE3_GLCM_PELOCKTBLADDR_RSVD_S) +#define IG3_CMPE3_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S 0 +#define IG3_CMPE3_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S) +#define IG3_CMPE3_GLCM_PELOCKTBLDATA0 0x43C204A0 +#define IG3_CMPE3_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S 31 +#define IG3_CMPE3_GLCM_PELOCKTBLDATA0_GPLOCKSEL_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S) +#define IG3_CMPE3_GLCM_PELOCKTBLDATA0_RSVD_S 24 +#define IG3_CMPE3_GLCM_PELOCKTBLDATA0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PELOCKTBLDATA0_RSVD_S) +#define IG3_CMPE3_GLCM_PELOCKTBLDATA0_QPID_S 0 +#define IG3_CMPE3_GLCM_PELOCKTBLDATA0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE3_GLCM_PELOCKTBLDATA0_QPID_S) +#define IG3_CMPE3_GLCM_PELOCKTBLDATA1 0x43C204A4 +#define IG3_CMPE3_GLCM_PELOCKTBLDATA1_RSVD_S 20 +#define IG3_CMPE3_GLCM_PELOCKTBLDATA1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLCM_PELOCKTBLDATA1_RSVD_S) +#define IG3_CMPE3_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S 0 +#define IG3_CMPE3_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S) +#define IG3_CMPE3_GLCM_PELOCKTBLDATA2 0x43C204A8 +#define IG3_CMPE3_GLCM_PELOCKTBLDATA2_LOCKSEL_S 0 +#define IG3_CMPE3_GLCM_PELOCKTBLDATA2_LOCKSEL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLCM_PELOCKTBLDATA2_LOCKSEL_S) +#define IG3_CMPE3_GLCM_PEPKTCNTADDR 0x43C20494 +#define IG3_CMPE3_GLCM_PEPKTCNTADDR_RSVD_S 9 +#define IG3_CMPE3_GLCM_PEPKTCNTADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE3_GLCM_PEPKTCNTADDR_RSVD_S) +#define IG3_CMPE3_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S 0 +#define IG3_CMPE3_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE3_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S) +#define IG3_CMPE3_GLCM_PEPKTCNTDATA 0x43C20498 +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_RSVD1_S 18 +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE3_GLCM_PEPKTCNTDATA_RSVD1_S) +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_RLRSP_STATE_S 16 +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_RLRSP_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PEPKTCNTDATA_RLRSP_STATE_S) +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_RSVD0_S 14 +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PEPKTCNTDATA_RSVD0_S) +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_RLREQ_STATE_S 12 +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_RLREQ_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PEPKTCNTDATA_RLREQ_STATE_S) +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_PKTCNT_S 1 +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_PKTCNT_M RDMA_MASK3(32, 0x7FF, IG3_CMPE3_GLCM_PEPKTCNTDATA_PKTCNT_S) +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_DONE_S 0 +#define IG3_CMPE3_GLCM_PEPKTCNTDATA_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PEPKTCNTDATA_DONE_S) +#define IG3_CMPE3_GLCM_PESTATSCTL 0x43C204AC +#define IG3_CMPE3_GLCM_PESTATSCTL_RSVD_S 2 +#define IG3_CMPE3_GLCM_PESTATSCTL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE3_GLCM_PESTATSCTL_RSVD_S) +#define IG3_CMPE3_GLCM_PESTATSCTL_ENABLE_S 1 +#define IG3_CMPE3_GLCM_PESTATSCTL_ENABLE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PESTATSCTL_ENABLE_S) +#define IG3_CMPE3_GLCM_PESTATSCTL_CLEAR_S 0 +#define IG3_CMPE3_GLCM_PESTATSCTL_CLEAR_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PESTATSCTL_CLEAR_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG 0x43C20500 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RM_S 16 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RM_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RME_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RME_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS 0x43C20504 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG 0x43C20508 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RM_S 16 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RM_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RME_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RME_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS 0x43C2050C +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG 0x43C20510 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RM_S 16 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RM_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RME_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RME_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS 0x43C20514 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG 0x43C20518 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RM_S 16 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RM_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RME_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RME_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS 0x43C2051C +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG 0x43C20520 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RM_S 16 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RM_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RME_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RME_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS 0x43C20524 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE3_GLCM_PE_CACHESIZE 0x43C204E4 +#define IG3_CMPE3_GLCM_PE_CACHESIZE_RSVD_S 26 +#define IG3_CMPE3_GLCM_PE_CACHESIZE_RSVD_M RDMA_MASK3(32, 0x3F, IG3_CMPE3_GLCM_PE_CACHESIZE_RSVD_S) +#define IG3_CMPE3_GLCM_PE_CACHESIZE_WAYS_S 16 +#define IG3_CMPE3_GLCM_PE_CACHESIZE_WAYS_M RDMA_MASK3(32, 0x3FF, IG3_CMPE3_GLCM_PE_CACHESIZE_WAYS_S) +#define IG3_CMPE3_GLCM_PE_CACHESIZE_SETS_S 12 +#define IG3_CMPE3_GLCM_PE_CACHESIZE_SETS_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLCM_PE_CACHESIZE_SETS_S) +#define IG3_CMPE3_GLCM_PE_CACHESIZE_WORD_SIZE_S 0 +#define IG3_CMPE3_GLCM_PE_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLCM_PE_CACHESIZE_WORD_SIZE_S) +#define IG3_CMPE3_GLCM_PE_DPC_COMP 0x43C204F4 +#define IG3_CMPE3_GLCM_PE_DPC_COMP_RSVD_S 13 +#define IG3_CMPE3_GLCM_PE_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_CMPE3_GLCM_PE_DPC_COMP_RSVD_S) +#define IG3_CMPE3_GLCM_PE_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_CMPE3_GLCM_PE_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_DPC_COMP_COMP_FTYPE_S) +#define IG3_CMPE3_GLCM_PE_DPC_COMP_COMP_FNUM_S 1 +#define IG3_CMPE3_GLCM_PE_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE3_GLCM_PE_DPC_COMP_COMP_FNUM_S) +#define IG3_CMPE3_GLCM_PE_DPC_COMP_COMP_VALID_S 0 +#define IG3_CMPE3_GLCM_PE_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_DPC_COMP_COMP_VALID_S) +#define IG3_CMPE3_GLCM_PE_DPC_REQ 0x43C204F0 +#define IG3_CMPE3_GLCM_PE_DPC_REQ_RSVD_S 12 +#define IG3_CMPE3_GLCM_PE_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_GLCM_PE_DPC_REQ_RSVD_S) +#define IG3_CMPE3_GLCM_PE_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_CMPE3_GLCM_PE_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_DPC_REQ_REQ_FTYPE_S) +#define IG3_CMPE3_GLCM_PE_DPC_REQ_REQ_FNUM_S 0 +#define IG3_CMPE3_GLCM_PE_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE3_GLCM_PE_DPC_REQ_REQ_FNUM_S) +#define IG3_CMPE3_GLCM_PE_E2E_FC 0x43C204F8 +#define IG3_CMPE3_GLCM_PE_E2E_FC_RSVD1_S 22 +#define IG3_CMPE3_GLCM_PE_E2E_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE3_GLCM_PE_E2E_FC_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE3_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE3_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE3_GLCM_PE_E2E_FC_RSVD0_S 9 +#define IG3_CMPE3_GLCM_PE_E2E_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PE_E2E_FC_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE3_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE3_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG 0x43C20528 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RM_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RME_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS 0x43C2052C +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG 0x43C20530 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RM_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RME_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS 0x43C20534 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE3_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE3_GLCM_PE_IF_FC 0x43C204FC +#define IG3_CMPE3_GLCM_PE_IF_FC_RSVD1_S 22 +#define IG3_CMPE3_GLCM_PE_IF_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE3_GLCM_PE_IF_FC_RSVD1_S) +#define IG3_CMPE3_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE3_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE3_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE3_GLCM_PE_IF_FC_RSVD0_S 9 +#define IG3_CMPE3_GLCM_PE_IF_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLCM_PE_IF_FC_RSVD0_S) +#define IG3_CMPE3_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE3_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE3_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE3_GLCM_PE_MAXOSR 0x43C204E0 +#define IG3_CMPE3_GLCM_PE_MAXOSR_RSVD_S 6 +#define IG3_CMPE3_GLCM_PE_MAXOSR_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_CMPE3_GLCM_PE_MAXOSR_RSVD_S) +#define IG3_CMPE3_GLCM_PE_MAXOSR_MAXOSR_S 0 +#define IG3_CMPE3_GLCM_PE_MAXOSR_MAXOSR_M RDMA_MASK3(32, 0x3F, IG3_CMPE3_GLCM_PE_MAXOSR_MAXOSR_S) +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL0 0x43C204E8 +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL0_RSVD_S 24 +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL0_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLCM_PE_RLDDBGCTL0_RSVD_S) +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL0_QPID_S 0 +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE3_GLCM_PE_RLDDBGCTL0_QPID_S) +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL1 0x43C204EC +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL1_RSVD_S 20 +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLCM_PE_RLDDBGCTL1_RSVD_S) +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S 18 +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S) +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S 6 +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S) +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL1_PF_NUM_S 0 +#define IG3_CMPE3_GLCM_PE_RLDDBGCTL1_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_CMPE3_GLCM_PE_RLDDBGCTL1_PF_NUM_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_COUNT 0x43C205B8 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_CMD 0x43C205CC +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_DATA_H 0x43C205D8 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_DATA_L 0x43C205D4 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_PTR 0x43C205D0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_CMD 0x43C205BC +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_DATA_H 0x43C205C8 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_DATA_L 0x43C205C4 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_PTR 0x43C205C0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL 0x43C20580 +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD1_S 25 +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD2_S 17 +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD2_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD3_S 9 +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD3_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_BYPASS_S 8 +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_BYPASS_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD4_S 1 +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_RSVD4_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_COR_ERR 0x43C205E8 +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_UNCOR_ERR 0x43C205E4 +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG 0x43C2058C +#define IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG 0x43C20590 +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG_MODE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLPE_CMPE_DTM_LOG_CFG_MODE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_MASK 0x43C20598 +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_MASK_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_LOG_MASK_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_PATTERN 0x43C20594 +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG 0x43C20584 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS 0x43C20588 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TIMESTAMP 0x43C205B0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER 0x43C205B4 +#define IG3_CMPE3_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG 0x43C205DC +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS 0x43C205E0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE3_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG 0x43C2059C +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_MODE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_CMPE3_GLPE_CMPE_DTM_TRIG_CFG_MODE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_COUNT 0x43C205A8 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_MASK 0x43C205A4 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_PATTERN 0x43C205A0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_TIMESTAMP 0x43C205AC +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE3_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE3_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0(_i) 0x43C20400 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_MAX_INDEX_I 15 +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_RSVD1_S 18 +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE3_PFCM_PE_CRCERRINFO0_RSVD1_S) +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S 16 +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE3_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S) +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S 4 +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE3_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S) +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_RSVD0_S 1 +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_RSVD0_M RDMA_MASK3(32, 0x7, IG3_CMPE3_PFCM_PE_CRCERRINFO0_RSVD0_S) +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S 0 +#define IG3_CMPE3_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_M RDMA_BIT2(32, IG3_CMPE3_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S) +#define IG3_CMPE3_PFCM_PE_CRCERRINFO1(_i) 0x43C20440 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE3_PFCM_PE_CRCERRINFO1_MAX_INDEX_I 15 +#define IG3_CMPE3_PFCM_PE_CRCERRINFO1_RSVD_S 24 +#define IG3_CMPE3_PFCM_PE_CRCERRINFO1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE3_PFCM_PE_CRCERRINFO1_RSVD_S) +#define IG3_CMPE3_PFCM_PE_CRCERRINFO1_Q_NUM_S 0 +#define IG3_CMPE3_PFCM_PE_CRCERRINFO1_Q_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE3_PFCM_PE_CRCERRINFO1_Q_NUM_S) +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG(_i) 0x44002000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG_MAX_INDEX_I 1031 +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG_RSVD2_S 31 +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG_RSVD2_M RDMA_BIT2(32, IG3_PRX4_GLPE_CC_DCQCN1_CFG_RSVD2_S) +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG_DCQCN_F_S 28 +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG_DCQCN_F_M RDMA_MASK3(32, 0x7, IG3_PRX4_GLPE_CC_DCQCN1_CFG_DCQCN_F_S) +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG_RSVD1_S 25 +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_PRX4_GLPE_CC_DCQCN1_CFG_RSVD1_S) +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG_DCQCN_B_S 0 +#define IG3_PRX4_GLPE_CC_DCQCN1_CFG_DCQCN_B_M RDMA_MASK3(32, 0x1FFFFFF, IG3_PRX4_GLPE_CC_DCQCN1_CFG_DCQCN_B_S) +#define IG3_PRX4_GLPE_CC_DCQCN2_CFG(_i) 0x44004000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX4_GLPE_CC_DCQCN2_CFG_MAX_INDEX_I 1031 +#define IG3_PRX4_GLPE_CC_DCQCN2_CFG_RSVD_S 16 +#define IG3_PRX4_GLPE_CC_DCQCN2_CFG_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_PRX4_GLPE_CC_DCQCN2_CFG_RSVD_S) +#define IG3_PRX4_GLPE_CC_DCQCN2_CFG_DCQCN_T_S 0 +#define IG3_PRX4_GLPE_CC_DCQCN2_CFG_DCQCN_T_M RDMA_MASK3(32, 0xFFFF, IG3_PRX4_GLPE_CC_DCQCN2_CFG_DCQCN_T_S) +#define IG3_PRX4_GLPE_CC_TIMELY_CFG(_i) 0x44000000 + ((_i) * 4) /* _i=0...1031 */ +#define IG3_PRX4_GLPE_CC_TIMELY_CFG_MAX_INDEX_I 1031 +#define IG3_PRX4_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S 16 +#define IG3_PRX4_GLPE_CC_TIMELY_CFG_RAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX4_GLPE_CC_TIMELY_CFG_RAI_FACTOR_S) +#define IG3_PRX4_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S 0 +#define IG3_PRX4_GLPE_CC_TIMELY_CFG_HAI_FACTOR_M RDMA_MASK3(32, 0xFFFF, IG3_PRX4_GLPE_CC_TIMELY_CFG_HAI_FACTOR_S) +#define IG3_PRX4_GLPE_PRX_CONFIG 0x44005020 +#define IG3_PRX4_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S 24 +#define IG3_PRX4_GLPE_PRX_CONFIG_REORDER_CNT_MAX_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_CONFIG_REORDER_CNT_MAX_S) +#define IG3_PRX4_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S 16 +#define IG3_PRX4_GLPE_PRX_CONFIG_REORDER_CNT_MIN_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_CONFIG_REORDER_CNT_MIN_S) +#define IG3_PRX4_GLPE_PRX_CONFIG_RSVD1_S 12 +#define IG3_PRX4_GLPE_PRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_PRX4_GLPE_PRX_CONFIG_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S 8 +#define IG3_PRX4_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_M RDMA_MASK3(32, 0xF, IG3_PRX4_GLPE_PRX_CONFIG_HOLD_CTXT_CNT_MAX_S) +#define IG3_PRX4_GLPE_PRX_CONFIG_RSVD0_S 5 +#define IG3_PRX4_GLPE_PRX_CONFIG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PRX4_GLPE_PRX_CONFIG_RSVD0_S) +#define IG3_PRX4_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S 4 +#define IG3_PRX4_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_CONFIG_UDA_LEGACY_MODE_S) +#define IG3_PRX4_GLPE_PRX_CONFIG_ONE_HP_TILE_S 3 +#define IG3_PRX4_GLPE_PRX_CONFIG_ONE_HP_TILE_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_CONFIG_ONE_HP_TILE_S) +#define IG3_PRX4_GLPE_PRX_CONFIG_DIS_RREC_S 2 +#define IG3_PRX4_GLPE_PRX_CONFIG_DIS_RREC_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_CONFIG_DIS_RREC_S) +#define IG3_PRX4_GLPE_PRX_CONFIG_DIS_QR_STALL_S 1 +#define IG3_PRX4_GLPE_PRX_CONFIG_DIS_QR_STALL_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_CONFIG_DIS_QR_STALL_S) +#define IG3_PRX4_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S 0 +#define IG3_PRX4_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_CONFIG_DROP_1BYTE_ZWP_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_COUNT 0x440050B8 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_CMD 0x440050CC +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_DATA_H 0x440050D8 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_DATA_L 0x440050D4 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_PTR 0x440050D0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_CMD 0x440050BC +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_DATA_H 0x440050C8 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_DATA_L 0x440050C4 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_PTR 0x440050C0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX4_GLPE_PRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL 0x44005080 +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD2_S) +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD3_S) +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_CONTROL_BYPASS_S) +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PRX4_GLPE_PRX_DTM_CONTROL_RSVD4_S) +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PRX4_GLPE_PRX_DTM_ECC_COR_ERR 0x440050E8 +#define IG3_PRX4_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PRX4_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX4_GLPE_PRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PRX4_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX4_GLPE_PRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PRX4_GLPE_PRX_DTM_ECC_UNCOR_ERR 0x440050E4 +#define IG3_PRX4_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PRX4_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX4_GLPE_PRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PRX4_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PRX4_GLPE_PRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG 0x4400508C +#define IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PRX4_GLPE_PRX_DTM_LOG_CFG 0x44005090 +#define IG3_PRX4_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PRX4_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PRX4_GLPE_PRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PRX4_GLPE_PRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PRX4_GLPE_PRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PRX4_GLPE_PRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PRX4_GLPE_PRX_DTM_LOG_CFG_MODE_S) +#define IG3_PRX4_GLPE_PRX_DTM_LOG_MASK 0x44005098 +#define IG3_PRX4_GLPE_PRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_LOG_MASK_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_LOG_PATTERN 0x44005094 +#define IG3_PRX4_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG 0x44005084 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_STS 0x44005088 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TIMESTAMP 0x440050B0 +#define IG3_PRX4_GLPE_PRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER 0x440050B4 +#define IG3_PRX4_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG 0x440050DC +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS 0x440050E0 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG 0x4400509C +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PRX4_GLPE_PRX_DTM_TRIG_CFG_MODE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_COUNT 0x440050A8 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_MASK 0x440050A4 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_PATTERN 0x440050A0 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_TIMESTAMP 0x440050AC +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PRX4_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PRX4_GLPE_PRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_CTL 0x44005024 +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S 12 +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_CTL_RSVD_S) +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S 0 +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_CTL_VDEV_NUM_S) +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA 0x44005028 +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S 31 +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_VALID_S) +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S 30 +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_M RDMA_BIT2(32, IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD1_S) +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S 24 +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_PF_NUM_S) +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S 20 +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_M RDMA_MASK3(32, 0xF, IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_RSVD0_S) +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S 0 +#define IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PRX4_GLPE_PRX_ROCEVMQP1LUT_DATA_QPID_S) +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL 0x44008018 +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S 21 +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_M RDMA_MASK3(32, 0x7FF, IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD2_S) +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S 16 +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REM_DATA_Q1_ENDIAN_CTL_S) +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S 13 +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S 8 +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_RSP_ENDIAN_CTL_S) +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S 5 +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_RSVD0_S) +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S 0 +#define IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_M RDMA_MASK3(32, 0x1F, IG3_WRX4_GLPE_WRX_ATOMIC_ENDIAN_CTL_HOST_ATOMIC_REQ_ENDIAN_CTL_S) +#define IG3_WRX4_GLPE_WRX_CONFIG 0x44008000 +#define IG3_WRX4_GLPE_WRX_CONFIG_RSVD_S 8 +#define IG3_WRX4_GLPE_WRX_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WRX4_GLPE_WRX_CONFIG_RSVD_S) +#define IG3_WRX4_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S 5 +#define IG3_WRX4_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_M RDMA_MASK3(32, 0x7, IG3_WRX4_GLPE_WRX_CONFIG_NUM_PROCESS_UNDER_LOCK_S) +#define IG3_WRX4_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S 4 +#define IG3_WRX4_GLPE_WRX_CONFIG_DIS_WQE_CACHE_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_CONFIG_DIS_WQE_CACHE_S) +#define IG3_WRX4_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S 3 +#define IG3_WRX4_GLPE_WRX_CONFIG_DROP_OOO_IMMED_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_CONFIG_DROP_OOO_IMMED_S) +#define IG3_WRX4_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S 2 +#define IG3_WRX4_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_CONFIG_DIS_DUP_RREQ_RCVD_S) +#define IG3_WRX4_GLPE_WRX_CONFIG_DIS_Q1_AE_S 1 +#define IG3_WRX4_GLPE_WRX_CONFIG_DIS_Q1_AE_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_CONFIG_DIS_Q1_AE_S) +#define IG3_WRX4_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S 0 +#define IG3_WRX4_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_CONFIG_DROP_INV_IN_REXMIT_S) +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS 0x44008014 +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_RSVD2_S 11 +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_RSVD2_M RDMA_MASK3(32, 0x1FFFFF, IG3_WRX4_GLPE_WRX_DOMAIN_IDS_RSVD2_S) +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S 8 +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX4_GLPE_WRX_DOMAIN_IDS_WRITE_DOMAIN_ID_S) +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_RSVD1_S 7 +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_RSVD1_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DOMAIN_IDS_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S 4 +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX4_GLPE_WRX_DOMAIN_IDS_WQE_DOMAIN_ID_S) +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_RSVD0_S 3 +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_RSVD0_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DOMAIN_IDS_RSVD0_S) +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S 0 +#define IG3_WRX4_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_WRX4_GLPE_WRX_DOMAIN_IDS_ATOMIC_DOMAIN_ID_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_COUNT 0x440080B8 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_CMD 0x440080CC +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_DATA_H 0x440080D8 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_DATA_L 0x440080D4 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_PTR 0x440080D0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_CMD 0x440080BC +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_DATA_H 0x440080C8 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_DATA_L 0x440080C4 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_PTR 0x440080C0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX4_GLPE_WRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL 0x44008080 +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD2_S) +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD3_S) +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_CONTROL_BYPASS_S) +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WRX4_GLPE_WRX_DTM_CONTROL_RSVD4_S) +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WRX4_GLPE_WRX_DTM_ECC_COR_ERR 0x440080E8 +#define IG3_WRX4_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WRX4_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX4_GLPE_WRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WRX4_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX4_GLPE_WRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WRX4_GLPE_WRX_DTM_ECC_UNCOR_ERR 0x440080E4 +#define IG3_WRX4_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WRX4_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX4_GLPE_WRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WRX4_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WRX4_GLPE_WRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG 0x4400808C +#define IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WRX4_GLPE_WRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WRX4_GLPE_WRX_DTM_LOG_CFG 0x44008090 +#define IG3_WRX4_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WRX4_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WRX4_GLPE_WRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WRX4_GLPE_WRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WRX4_GLPE_WRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WRX4_GLPE_WRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WRX4_GLPE_WRX_DTM_LOG_CFG_MODE_S) +#define IG3_WRX4_GLPE_WRX_DTM_LOG_MASK 0x44008098 +#define IG3_WRX4_GLPE_WRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_LOG_MASK_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_LOG_PATTERN 0x44008094 +#define IG3_WRX4_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG 0x44008084 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_STS 0x44008088 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TIMESTAMP 0x440080B0 +#define IG3_WRX4_GLPE_WRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER 0x440080B4 +#define IG3_WRX4_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG 0x440080DC +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS 0x440080E0 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG 0x4400809C +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WRX4_GLPE_WRX_DTM_TRIG_CFG_MODE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_COUNT 0x440080A8 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_MASK 0x440080A4 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_PATTERN 0x440080A0 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_TIMESTAMP 0x440080AC +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WRX4_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHHI 0x44008020 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WRX4_GLPE_WRX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WRX4_GLPE_WRX_FWQPFLUSHHI_QPID_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WRX4_GLPE_WRX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO 0x4400801C +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_BUSY_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WRX4_GLPE_WRX_FWQPFLUSHLO_PMF_S) +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_CTRL 0x44008004 +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S 7 +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_CTRL_RSVD_M RDMA_MASK3(32, 0x1FFFFFF, IG3_WRX4_GLPE_WRX_RQ_CACHE_CTRL_RSVD_S) +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S 0 +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_M RDMA_MASK3(32, 0x7F, IG3_WRX4_GLPE_WRX_RQ_CACHE_CTRL_WQE_IDX_S) +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA0 0x44008008 +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA0_DATA_S 0 +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA0_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA0_DATA_S) +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA1 0x4400800C +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA1_DATA_S 0 +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA1_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA1_DATA_S) +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA2 0x44008010 +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA2_DATA_S 0 +#define IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA2_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WRX4_GLPE_WRX_RQ_CACHE_DATA2_DATA_S) +#define IG3_SQC4_GLPE_SQC_CONFIG 0x44008470 +#define IG3_SQC4_GLPE_SQC_CONFIG_RSVD_S 6 +#define IG3_SQC4_GLPE_SQC_CONFIG_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_SQC4_GLPE_SQC_CONFIG_RSVD_S) +#define IG3_SQC4_GLPE_SQC_CONFIG_DBL_INDV_DIS_S 3 +#define IG3_SQC4_GLPE_SQC_CONFIG_DBL_INDV_DIS_M RDMA_MASK3(32, 0x7, IG3_SQC4_GLPE_SQC_CONFIG_DBL_INDV_DIS_S) +#define IG3_SQC4_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S 2 +#define IG3_SQC4_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_SQC4_GLPE_SQC_CONFIG_DBL_DIS_S 1 +#define IG3_SQC4_GLPE_SQC_CONFIG_DBL_DIS_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_CONFIG_DBL_DIS_S) +#define IG3_SQC4_GLPE_SQC_CONFIG_COALESCE_DIS_S 0 +#define IG3_SQC4_GLPE_SQC_CONFIG_COALESCE_DIS_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_CONFIG_COALESCE_DIS_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_COUNT 0x440084B8 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_CMD 0x440084CC +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_DATA_H 0x440084D8 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_DATA_L 0x440084D4 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_PTR 0x440084D0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_CMD 0x440084BC +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_DATA_H 0x440084C8 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_DATA_L 0x440084C4 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_PTR 0x440084C0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC4_GLPE_SQC_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL 0x44008480 +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD1_S 25 +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD2_S 17 +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD2_S) +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD3_S 9 +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD3_S) +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_BYPASS_S 8 +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_CONTROL_BYPASS_S) +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD4_S 1 +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SQC4_GLPE_SQC_DTM_CONTROL_RSVD4_S) +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SQC4_GLPE_SQC_DTM_ECC_COR_ERR 0x440084E8 +#define IG3_SQC4_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC4_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC4_GLPE_SQC_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SQC4_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SQC4_GLPE_SQC_DTM_ECC_UNCOR_ERR 0x440084E4 +#define IG3_SQC4_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC4_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC4_GLPE_SQC_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC4_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG 0x4400848C +#define IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SQC4_GLPE_SQC_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SQC4_GLPE_SQC_DTM_LOG_CFG 0x44008490 +#define IG3_SQC4_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SQC4_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SQC4_GLPE_SQC_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SQC4_GLPE_SQC_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SQC4_GLPE_SQC_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SQC4_GLPE_SQC_DTM_LOG_CFG_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_LOG_CFG_MODE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SQC4_GLPE_SQC_DTM_LOG_CFG_MODE_S) +#define IG3_SQC4_GLPE_SQC_DTM_LOG_MASK 0x44008498 +#define IG3_SQC4_GLPE_SQC_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_LOG_MASK_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_LOG_PATTERN 0x44008494 +#define IG3_SQC4_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG 0x44008484 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_STS 0x44008488 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_RSVD2_S) +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TIMESTAMP 0x440084B0 +#define IG3_SQC4_GLPE_SQC_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_TIMESTAMP_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER 0x440084B4 +#define IG3_SQC4_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG 0x440084DC +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS 0x440084E0 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG 0x4400849C +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SQC4_GLPE_SQC_DTM_TRIG_CFG_MODE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_COUNT 0x440084A8 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_MASK 0x440084A4 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_TRIG_MASK_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_PATTERN 0x440084A0 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_TIMESTAMP 0x440084AC +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SQC4_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SQC4_GLPE_SQC_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI 0x44008460 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S 26 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI_RSVD0_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S 6 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI_QPID_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S 0 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHHI_PF_NUM_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO 0x44008464 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S 31 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_BUSY_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_REQ_TYPE_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S 29 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_RSVD0_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S 26 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_HOSTID_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_VM_VF_NUM_S) +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S 0 +#define IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_FWFLRQPFLUSHLO_PMF_S) +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI(_i) 0x44008420 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_MAX_INDEX_I 7 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S 26 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_RSVD0_S) +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_QPID_S 6 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_QPID_S) +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S 0 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_SQC4_GLPE_SQC_FWFLUSHDROPHI_PF_NUM_S) +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO(_i) 0x44008400 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_MAX_INDEX_I 7 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_EN_S 31 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_EN_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_EN_S) +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S 29 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_RSVD0_S) +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S 26 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_HOSTID_S) +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S 24 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_VM_VF_TYPE_S) +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S 12 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_VM_VF_NUM_S) +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_PMF_S 0 +#define IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_FWFLUSHDROPLO_PMF_S) +#define IG3_SQC4_GLPE_SQC_FWSYNCRESP(_i) 0x44008468 + ((_i) * 4) /* _i=0...1 */ +#define IG3_SQC4_GLPE_SQC_FWSYNCRESP_MAX_INDEX_I 1 +#define IG3_SQC4_GLPE_SQC_FWSYNCRESP_RSVD_S 18 +#define IG3_SQC4_GLPE_SQC_FWSYNCRESP_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_SQC4_GLPE_SQC_FWSYNCRESP_RSVD_S) +#define IG3_SQC4_GLPE_SQC_FWSYNCRESP_COUNT_S 8 +#define IG3_SQC4_GLPE_SQC_FWSYNCRESP_COUNT_M RDMA_MASK3(32, 0x3FF, IG3_SQC4_GLPE_SQC_FWSYNCRESP_COUNT_S) +#define IG3_SQC4_GLPE_SQC_FWSYNCRESP_TAG_S 0 +#define IG3_SQC4_GLPE_SQC_FWSYNCRESP_TAG_M RDMA_MASK3(32, 0xFF, IG3_SQC4_GLPE_SQC_FWSYNCRESP_TAG_S) +#define IG3_SQC4_GLPE_SQC_XLR_DROP(_i) 0x44008440 + ((_i) * 4) /* _i=0...7 */ +#define IG3_SQC4_GLPE_SQC_XLR_DROP_MAX_INDEX_I 7 +#define IG3_SQC4_GLPE_SQC_XLR_DROP_EN_S 31 +#define IG3_SQC4_GLPE_SQC_XLR_DROP_EN_M RDMA_BIT2(32, IG3_SQC4_GLPE_SQC_XLR_DROP_EN_S) +#define IG3_SQC4_GLPE_SQC_XLR_DROP_RSVD0_S 12 +#define IG3_SQC4_GLPE_SQC_XLR_DROP_RSVD0_M RDMA_MASK3(32, 0x7FFFF, IG3_SQC4_GLPE_SQC_XLR_DROP_RSVD0_S) +#define IG3_SQC4_GLPE_SQC_XLR_DROP_PMF_S 0 +#define IG3_SQC4_GLPE_SQC_XLR_DROP_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_GLPE_SQC_XLR_DROP_PMF_S) +#define IG3_SQC4_SQC_ECC_COR_ERR 0x44008514 +#define IG3_SQC4_SQC_ECC_COR_ERR_RSVD_S 12 +#define IG3_SQC4_SQC_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC4_SQC_ECC_COR_ERR_RSVD_S) +#define IG3_SQC4_SQC_ECC_COR_ERR_CNT_S 0 +#define IG3_SQC4_SQC_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_SQC_ECC_COR_ERR_CNT_S) +#define IG3_SQC4_SQC_ECC_UNCOR_ERR 0x44008510 +#define IG3_SQC4_SQC_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SQC4_SQC_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SQC4_SQC_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SQC4_SQC_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SQC4_SQC_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SQC4_SQC_ECC_UNCOR_ERR_CNT_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG 0x44008500 +#define IG3_SQC4_SQC_WRK_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC4_SQC_WRK_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC4_SQC_WRK_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_RSVD3_S 20 +#define IG3_SQC4_SQC_WRK_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC4_SQC_WRK_RAM_CFG_RSVD3_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_RM_S 16 +#define IG3_SQC4_SQC_WRK_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC4_SQC_WRK_RAM_CFG_RM_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_RSVD2_S 14 +#define IG3_SQC4_SQC_WRK_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC4_SQC_WRK_RAM_CFG_RSVD2_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC4_SQC_WRK_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_RME_S 12 +#define IG3_SQC4_SQC_WRK_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_RME_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_RSVD1_S 10 +#define IG3_SQC4_SQC_WRK_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC4_SQC_WRK_RAM_CFG_RSVD1_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC4_SQC_WRK_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_ERR_CNT_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC4_SQC_WRK_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_FIX_CNT_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_RSVD0_S 6 +#define IG3_SQC4_SQC_WRK_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC4_SQC_WRK_RAM_CFG_RSVD0_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC4_SQC_WRK_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_MASK_INT_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC4_SQC_WRK_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC4_SQC_WRK_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_LS_FORCE_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC4_SQC_WRK_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC4_SQC_WRK_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC4_SQC_WRK_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC4_SQC_WRK_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_CFG_ECC_EN_S) +#define IG3_SQC4_SQC_WRK_RAM_STATUS 0x44008504 +#define IG3_SQC4_SQC_WRK_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC4_SQC_WRK_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC4_SQC_WRK_RAM_STATUS_RSVD1_S) +#define IG3_SQC4_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC4_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC4_SQC_WRK_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC4_SQC_WRK_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC4_SQC_WRK_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC4_SQC_WRK_RAM_STATUS_RSVD0_S) +#define IG3_SQC4_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC4_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC4_SQC_WRK_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC4_SQC_WRK_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC4_SQC_WRK_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC4_SQC_WRK_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC4_SQC_WRK_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC4_SQC_WRK_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC4_SQC_WRK_RAM_STATUS_ECC_ERR_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG 0x44008508 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S 25 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_INST_NUM_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD3_S 20 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD3_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RM_S 16 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SQC4_SQC_XBUF_RAM_CFG_RM_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD2_S 14 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD2_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S 13 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_POWER_GATE_EN_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RME_S 12 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RME_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_RME_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD1_S 10 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD1_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ERR_CNT_S 9 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_ERR_CNT_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_FIX_CNT_S 8 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_FIX_CNT_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD0_S 6 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SQC4_SQC_XBUF_RAM_CFG_RSVD0_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_MASK_INT_S 5 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_MASK_INT_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_LS_BYPASS_S 4 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_LS_BYPASS_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_LS_FORCE_S 3 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_LS_FORCE_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S 2 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_INVERT_2_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S 1 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_INVERT_1_S) +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_EN_S 0 +#define IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_CFG_ECC_EN_S) +#define IG3_SQC4_SQC_XBUF_RAM_STATUS 0x4400850C +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_RSVD1_S 30 +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SQC4_SQC_XBUF_RAM_STATUS_RSVD1_S) +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SQC4_SQC_XBUF_RAM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_RSVD0_S 4 +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SQC4_SQC_XBUF_RAM_STATUS_RSVD0_S) +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_INIT_DONE_S 2 +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_STATUS_INIT_DONE_S) +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_ECC_FIX_S 1 +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_STATUS_ECC_FIX_S) +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_ECC_ERR_S 0 +#define IG3_SQC4_SQC_XBUF_RAM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SQC4_SQC_XBUF_RAM_STATUS_ECC_ERR_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DOMAIN_ID 0x44008804 +#define IG3_SFPRX4_GLPE_SFP_RX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPRX4_GLPE_SFP_RX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DOMAIN_ID_RSVD_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPRX4_GLPE_SFP_RX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_COUNT 0x440088B8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_CMD 0x440088CC +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H 0x440088D8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L 0x440088D4 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_PTR 0x440088D0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_CMD 0x440088BC +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H 0x440088C8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L 0x440088C4 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_PTR 0x440088C0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL 0x44008880 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD2_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD3_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_BYPASS_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_RSVD4_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_COR_ERR 0x440088E8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR 0x440088E4 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG 0x4400888C +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG 0x44008890 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_CFG_MODE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_MASK 0x44008898 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_PATTERN 0x44008894 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG 0x44008884 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS 0x44008888 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TIMESTAMP 0x440088B0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER 0x440088B4 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG 0x440088DC +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS 0x440088E0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG 0x4400889C +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_COUNT 0x440088A8 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_MASK 0x440088A4 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_PATTERN 0x440088A0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP 0x440088AC +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR 0x44008800 +#define IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S 31 +#define IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR_REQ_M RDMA_BIT2(32, IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR_REQ_S) +#define IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S 12 +#define IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR_RSVD_S) +#define IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR_PMF_M RDMA_MASK3(32, 0xFFF, IG3_SFPRX4_GLPE_SFP_RX_ERR_TBL_CLR_PMF_S) +#define IG3_SFPRX4_GLPE_SFP_RX_PER_MEM 0x44008808 +#define IG3_SFPRX4_GLPE_SFP_RX_PER_MEM_RSVD_S 3 +#define IG3_SFPRX4_GLPE_SFP_RX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPRX4_GLPE_SFP_RX_PER_MEM_RSVD_S) +#define IG3_SFPRX4_GLPE_SFP_RX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPRX4_GLPE_SFP_RX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPRX4_GLPE_SFP_RX_PER_MEM_PER_TYPE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG 0x44008C08 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS 0x44008C0C +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_CC_CFG_CSR_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_COR_ERR 0x44008C34 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR 0x44008C30 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG 0x44008C18 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS 0x44008C1C +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_BUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG 0x44008C20 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS 0x44008C24 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_HDR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG 0x44008C00 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS 0x44008C04 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_INPUT_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG 0x44008C28 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS 0x44008C2C +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_RCB_CMD_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG 0x44008C10 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS 0x44008C14 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_PRX_ROCEVMQP1LUT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG 0x44008C48 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS 0x44008C4C +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG 0x44008C40 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS 0x44008C44 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG 0x44008C78 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS 0x44008C7C +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG 0x44008C50 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS 0x44008C54 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG 0x44008C58 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS 0x44008C5C +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR 0x44008C84 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_COR_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR 0x44008C80 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG 0x44008C70 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS 0x44008C74 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG 0x44008C60 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS 0x44008C64 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG 0x44008C68 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS 0x44008C6C +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG 0x44008C38 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS 0x44008C3C +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_SFPR_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_COR_ERR 0x44008CCC +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_COR_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR 0x44008CC8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG 0x44008CD8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS 0x44008CDC +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SFPR_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL 0x44008C90 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA 0x44008C94 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG 0x44008C88 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS 0x44008C8C +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL 0x44008CA0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA 0x44008CA4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG 0x44008C98 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS 0x44008C9C +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL 0x44008CB0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA 0x44008CB4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG 0x44008CA8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS 0x44008CAC +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL 0x44008CC0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA 0x44008CC4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG 0x44008CB8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS 0x44008CBC +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG 0x44008CD0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD3_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S 16 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RM_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RME_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS 0x44008CD4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_RX_SHCTL_GLPE_WRX_WQE_FIFO_MEM_STATUS_ECC_ERR_S) +#define IG3_WTX4_GLPE_WTX_1USCOUNT 0x44010010 +#define IG3_WTX4_GLPE_WTX_1USCOUNT_CNT_S 0 +#define IG3_WTX4_GLPE_WTX_1USCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_1USCOUNT_CNT_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0 0x44010120 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1 0x44010124 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2 0x44010128 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG3 0x4401012C +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG4 0x44010130 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_ABORT_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG 0x44010020 +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD3_S 24 +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD3_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD3_S) +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD2_S 20 +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD2_S) +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S 16 +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_ARB_CONFIG_SCHD_RSP_ARB_WGHT_S) +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD1_S 12 +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S 8 +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_ARB_CONFIG_SCHD_REQ_ARB_WGHT_S) +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD0_S 4 +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD0_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_ARB_CONFIG_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S 0 +#define IG3_WTX4_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_ARB_CONFIG_PUSH_ARB_WGHT_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0 0x440100F8 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1 0x440100FC +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2 0x44010100 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG3 0x44010104 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG4 0x44010108 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG 0x4401017C +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX 0x44010180 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_CMP_UPDATE_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_CNPCOUNT 0x44010014 +#define IG3_WTX4_GLPE_WTX_CNPCOUNT_CNT_S 0 +#define IG3_WTX4_GLPE_WTX_CNPCOUNT_CNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_CNPCOUNT_CNT_S) +#define IG3_WTX4_GLPE_WTX_CONFIG 0x4401000C +#define IG3_WTX4_GLPE_WTX_CONFIG_RSVD1_S 28 +#define IG3_WTX4_GLPE_WTX_CONFIG_RSVD1_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_CONFIG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_CONFIG_SQ_HSM_ORD_S 25 +#define IG3_WTX4_GLPE_WTX_CONFIG_SQ_HSM_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_CONFIG_SQ_HSM_ORD_S) +#define IG3_WTX4_GLPE_WTX_CONFIG_SQ_WQE_ORD_S 22 +#define IG3_WTX4_GLPE_WTX_CONFIG_SQ_WQE_ORD_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_CONFIG_SQ_WQE_ORD_S) +#define IG3_WTX4_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S 21 +#define IG3_WTX4_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CONFIG_SQ_SLOW_START_EN_S) +#define IG3_WTX4_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S 20 +#define IG3_WTX4_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CONFIG_CRT_XMIT_RAM_EN_S) +#define IG3_WTX4_GLPE_WTX_CONFIG_RSVD0_S 4 +#define IG3_WTX4_GLPE_WTX_CONFIG_RSVD0_M RDMA_MASK3(32, 0xFFFF, IG3_WTX4_GLPE_WTX_CONFIG_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S 3 +#define IG3_WTX4_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CONFIG_PTX_SPAD_CACHE_EN_S) +#define IG3_WTX4_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S 2 +#define IG3_WTX4_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CONFIG_SHDW_WRITE_RLX_ORD_S) +#define IG3_WTX4_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S 1 +#define IG3_WTX4_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CONFIG_TX_Q1_PACK_EN_S) +#define IG3_WTX4_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S 0 +#define IG3_WTX4_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_CONFIG_TX_SPAD_CACHE_EN_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG0 0x4401003C +#define IG3_WTX4_GLPE_WTX_CTCONFIG0_RSVD_S 21 +#define IG3_WTX4_GLPE_WTX_CTCONFIG0_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX4_GLPE_WTX_CTCONFIG0_RSVD_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG0_SCHED_S 0 +#define IG3_WTX4_GLPE_WTX_CTCONFIG0_SCHED_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX4_GLPE_WTX_CTCONFIG0_SCHED_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG1 0x44010040 +#define IG3_WTX4_GLPE_WTX_CTCONFIG1_RSVD_S 21 +#define IG3_WTX4_GLPE_WTX_CTCONFIG1_RSVD_M RDMA_MASK3(32, 0x7FF, IG3_WTX4_GLPE_WTX_CTCONFIG1_RSVD_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG1_VMRL_S 0 +#define IG3_WTX4_GLPE_WTX_CTCONFIG1_VMRL_M RDMA_MASK3(32, 0x1FFFFF, IG3_WTX4_GLPE_WTX_CTCONFIG1_VMRL_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG2 0x44010044 +#define IG3_WTX4_GLPE_WTX_CTCONFIG2_RSVD_S 30 +#define IG3_WTX4_GLPE_WTX_CTCONFIG2_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_CTCONFIG2_RSVD_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S 16 +#define IG3_WTX4_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_CTCONFIG2_CRTREQTXPKT_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S 0 +#define IG3_WTX4_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX4_GLPE_WTX_CTCONFIG2_CRTREQTXBUF_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG3 0x44010048 +#define IG3_WTX4_GLPE_WTX_CTCONFIG3_RSVD_S 30 +#define IG3_WTX4_GLPE_WTX_CTCONFIG3_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_CTCONFIG3_RSVD_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S 16 +#define IG3_WTX4_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_CTCONFIG3_CRTREQRXPKT_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S 0 +#define IG3_WTX4_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX4_GLPE_WTX_CTCONFIG3_CRTREQRXBUF_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG4 0x4401004C +#define IG3_WTX4_GLPE_WTX_CTCONFIG4_RSVD_S 30 +#define IG3_WTX4_GLPE_WTX_CTCONFIG4_RSVD_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_CTCONFIG4_RSVD_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S 16 +#define IG3_WTX4_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_CTCONFIG4_CRTRSPTXPKT_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S 0 +#define IG3_WTX4_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_M RDMA_MASK3(32, 0xFFFF, IG3_WTX4_GLPE_WTX_CTCONFIG4_CRTRSPTXBUF_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG5 0x44010050 +#define IG3_WTX4_GLPE_WTX_CTCONFIG5_RSVD_S 20 +#define IG3_WTX4_GLPE_WTX_CTCONFIG5_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_CTCONFIG5_RSVD_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG5_BMPKT_S 0 +#define IG3_WTX4_GLPE_WTX_CTCONFIG5_BMPKT_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX4_GLPE_WTX_CTCONFIG5_BMPKT_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG6 0x44010054 +#define IG3_WTX4_GLPE_WTX_CTCONFIG6_RSVD_S 13 +#define IG3_WTX4_GLPE_WTX_CTCONFIG6_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_WTX4_GLPE_WTX_CTCONFIG6_RSVD_S) +#define IG3_WTX4_GLPE_WTX_CTCONFIG6_BMHDR_S 0 +#define IG3_WTX4_GLPE_WTX_CTCONFIG6_BMHDR_M RDMA_MASK3(32, 0x1FFF, IG3_WTX4_GLPE_WTX_CTCONFIG6_BMHDR_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_COUNT 0x44010238 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_CMD 0x4401024C +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_DATA_H 0x44010258 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_DATA_L 0x44010254 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_PTR 0x44010250 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_CMD 0x4401023C +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_DATA_H 0x44010248 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_DATA_L 0x44010244 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_PTR 0x44010240 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX4_GLPE_WTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL 0x44010200 +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD2_S) +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD3_S) +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_CONTROL_BYPASS_S) +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_WTX4_GLPE_WTX_DTM_CONTROL_RSVD4_S) +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_WTX4_GLPE_WTX_DTM_ECC_COR_ERR 0x44010268 +#define IG3_WTX4_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX4_GLPE_WTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_WTX4_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_WTX4_GLPE_WTX_DTM_ECC_UNCOR_ERR 0x44010264 +#define IG3_WTX4_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX4_GLPE_WTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_WTX4_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG 0x4401020C +#define IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_WTX4_GLPE_WTX_DTM_LOG_CFG 0x44010210 +#define IG3_WTX4_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_WTX4_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_WTX4_GLPE_WTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_WTX4_GLPE_WTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_WTX4_GLPE_WTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_DTM_LOG_CFG_MODE_S) +#define IG3_WTX4_GLPE_WTX_DTM_LOG_MASK 0x44010218 +#define IG3_WTX4_GLPE_WTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_LOG_MASK_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_LOG_PATTERN 0x44010214 +#define IG3_WTX4_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG 0x44010204 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_STS 0x44010208 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TIMESTAMP 0x44010230 +#define IG3_WTX4_GLPE_WTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER 0x44010234 +#define IG3_WTX4_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG 0x4401025C +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS 0x44010260 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG 0x4401021C +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_DTM_TRIG_CFG_MODE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_COUNT 0x44010228 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_MASK 0x44010224 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_PATTERN 0x44010220 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_TIMESTAMP 0x4401022C +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_WTX4_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG 0x4401014C +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_FTHRESH_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_CFG_DEPTH_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG 0x44010150 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX 0x44010154 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_FLM_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHHI 0x4401005C +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_WTX4_GLPE_WTX_FWQPFLUSHHI_QPID_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO 0x44010058 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_BUSY_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_FWQPFLUSHLO_PMF_S) +#define IG3_WTX4_GLPE_WTX_HOST_READ_CONFIG 0x44010038 +#define IG3_WTX4_GLPE_WTX_HOST_READ_CONFIG_RSVD_S 8 +#define IG3_WTX4_GLPE_WTX_HOST_READ_CONFIG_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_HOST_READ_CONFIG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S 0 +#define IG3_WTX4_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_HOST_READ_CONFIG_RD_DEPTH_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0 0x4401010C +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1 0x44010110 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2 0x44010114 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG3 0x44010118 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG4 0x4401011C +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_OC_CMP_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG 0x4401018C +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX 0x44010190 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_OC_DATA_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG 0x44010194 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX 0x44010198 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_OC_ERR_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG 0x44010184 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX 0x44010188 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_OC_TAG_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0 0x44010090 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1 0x44010094 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2 0x44010098 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG3 0x4401009C +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG4 0x440100A0 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_PUSH_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0 0x44010060 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1 0x44010064 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2 0x44010068 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG3 0x4401006C +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG4 0x44010070 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG5 0x44010074 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_REQ_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0 0x44010078 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1 0x4401007C +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2 0x44010080 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG3 0x44010084 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG4 0x44010088 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG5 0x4401008C +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG5_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_RSP_IF_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG 0x44010134 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_FTHRESH_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_CFG_DEPTH_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG 0x44010138 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX 0x4401013C +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SCHD_REQ_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG 0x44010140 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_FTHRESH_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_CFG_DEPTH_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG 0x44010144 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX 0x44010148 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SCHD_RSP_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG 0x44010164 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_FTHRESH_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_CFG_DEPTH_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG 0x44010168 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX 0x4401016C +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_FLM_INFO_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG 0x44010158 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_FTHRESH_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_CFG_DEPTH_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG 0x4401015C +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX 0x44010160 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_PAL_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0 0x440100E4 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1 0x440100E8 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2 0x440100EC +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG3 0x440100F0 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG4 0x440100F4 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_SM_PTX_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0 0x440100D0 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1 0x440100D4 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2 0x440100D8 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG3 0x440100DC +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG4 0x440100E0 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_SM_WQE_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED(_i) 0x44010000 + ((_i) * 4) /* _i=0...2 */ +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_MAX_INDEX_I 2 +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S 24 +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD3_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD3_S) +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S 16 +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD2_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD2_S) +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S 8 +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD1_S) +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S 0 +#define IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD0_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPADS_ASSIGNED_SPAD0_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0 0x440100A4 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1 0x440100A8 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2 0x440100AC +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG3 0x440100B0 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG4 0x440100B4 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG5 0x440100B8 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S 1 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_ASGN_DTM_TRIG5_DEALLOC_MASK_S) +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG0 0x44010024 +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S 24 +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_CQP_MAX_S) +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S 16 +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_RSP_MAX_S) +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S 8 +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_REQ_MAX_S) +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_CONFIG0_PUSH_MAX_S) +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG1 0x44010028 +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG1_RSVD_S 8 +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_CONFIG1_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_CONFIG1_FLR_MAX_S) +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0 0x4401002C +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S 24 +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_CQP_COUNT_S) +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S 16 +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_RSP_COUNT_S) +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S 8 +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_REQ_COUNT_S) +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS0_PUSH_COUNT_S) +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS1 0x44010030 +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S 8 +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS1_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_DEPTH_STATUS1_FLR_COUNT_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0 0x440100BC +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S 24 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S 16 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S 14 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S 11 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_MODE_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_TAG_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_QPID_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PMF_EN_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1 0x440100C0 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S 29 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S 26 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_HOSTID_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG1_PMF_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2 0x440100C4 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S 30 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S 6 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2_QPID_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG2_PF_NUM_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG3 0x440100C8 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG3_THRESHOLD_S) +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG4 0x440100CC +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_INTF_DTM_TRIG4_COUNT_S) +#define IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL 0x44010034 +#define IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S 16 +#define IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_M RDMA_MASK3(32, 0xFFFF, IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S 8 +#define IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_NXTPTR_S) +#define IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_QUEUE_PTR_CTL_QUEUE_PTR_S) +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL 0x44010018 +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S 20 +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S 16 +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_M RDMA_MASK3(32, 0xF, IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_SPAD_WR_DATA_S) +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S 10 +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S 8 +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_M RDMA_MASK3(32, 0x3, IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_SEL_S) +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_M RDMA_MASK3(32, 0xFF, IG3_WTX4_GLPE_WTX_SPAD_STAT_CTL_SPAD_PORT_ID_S) +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_DATA 0x4401001C +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_DATA_DATA_S 0 +#define IG3_WTX4_GLPE_WTX_SPAD_STAT_DATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_WTX4_GLPE_WTX_SPAD_STAT_DATA_DATA_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG 0x44010170 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S 29 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD1_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S 28 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_EN_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S 16 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_FTHRESH_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S 13 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_M RDMA_MASK3(32, 0x7, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_RSVD0_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S 12 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_EN_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S 0 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_CFG_DEPTH_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG 0x44010174 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_FULL_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_OVF_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_UDF_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_NUM_ENTRIES_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX 0x44010178 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S 31 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_FULL_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S 30 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_EMPTY_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S 29 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NFULL_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S 28 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NEMPTY_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S 27 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_OVF_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S 26 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_M RDMA_BIT2(32, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_UDF_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S 12 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_RSVD_S) +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S 0 +#define IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_M RDMA_MASK3(32, 0xFFF, IG3_WTX4_GLPE_WTX_SPIF_CT_TRAN_FIFO_DBG_MAX_NUM_ENTRIES_S) +#define IG3_PTX4_GLPE_ARPCONTROL 0x4401400C +#define IG3_PTX4_GLPE_ARPCONTROL_ARP_LOCK_ACK_S 31 +#define IG3_PTX4_GLPE_ARPCONTROL_ARP_LOCK_ACK_M RDMA_BIT2(32, IG3_PTX4_GLPE_ARPCONTROL_ARP_LOCK_ACK_S) +#define IG3_PTX4_GLPE_ARPCONTROL_ARP_LOCK_REQ_S 30 +#define IG3_PTX4_GLPE_ARPCONTROL_ARP_LOCK_REQ_M RDMA_BIT2(32, IG3_PTX4_GLPE_ARPCONTROL_ARP_LOCK_REQ_S) +#define IG3_PTX4_GLPE_ARPCONTROL_RSVD_S 16 +#define IG3_PTX4_GLPE_ARPCONTROL_RSVD_M RDMA_MASK3(32, 0x3FFF, IG3_PTX4_GLPE_ARPCONTROL_RSVD_S) +#define IG3_PTX4_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S 0 +#define IG3_PTX4_GLPE_ARPCONTROL_ARP_LOCK_INDEX_M RDMA_MASK3(32, 0xFFFF, IG3_PTX4_GLPE_ARPCONTROL_ARP_LOCK_INDEX_S) +#define IG3_PTX4_GLPE_CRT_CONFIG0 0x44014010 +#define IG3_PTX4_GLPE_CRT_CONFIG0_RSVD_S 25 +#define IG3_PTX4_GLPE_CRT_CONFIG0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_CRT_CONFIG0_RSVD_S) +#define IG3_PTX4_GLPE_CRT_CONFIG0_QP_FC_EN_S 24 +#define IG3_PTX4_GLPE_CRT_CONFIG0_QP_FC_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_CRT_CONFIG0_QP_FC_EN_S) +#define IG3_PTX4_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S 16 +#define IG3_PTX4_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_CRT_CONFIG0_TX_OFFSET_PKT_S) +#define IG3_PTX4_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S 8 +#define IG3_PTX4_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_CRT_CONFIG0_TX_OFFSET_PMD_S) +#define IG3_PTX4_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S 0 +#define IG3_PTX4_GLPE_CRT_CONFIG0_TX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_CRT_CONFIG0_TX_BUF_SIZE_S) +#define IG3_PTX4_GLPE_CRT_CONFIG1 0x44014014 +#define IG3_PTX4_GLPE_CRT_CONFIG1_RSVD_S 19 +#define IG3_PTX4_GLPE_CRT_CONFIG1_RSVD_M RDMA_MASK3(32, 0x1FFF, IG3_PTX4_GLPE_CRT_CONFIG1_RSVD_S) +#define IG3_PTX4_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S 16 +#define IG3_PTX4_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_M RDMA_MASK3(32, 0x7, IG3_PTX4_GLPE_CRT_CONFIG1_RX_PMD_BUF_CNT_S) +#define IG3_PTX4_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S 8 +#define IG3_PTX4_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_CRT_CONFIG1_RX_OFFSET_PKT_S) +#define IG3_PTX4_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S 0 +#define IG3_PTX4_GLPE_CRT_CONFIG1_RX_BUF_SIZE_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_CRT_CONFIG1_RX_BUF_SIZE_S) +#define IG3_PTX4_GLPE_MAX_INLINE_DATA 0x44014000 +#define IG3_PTX4_GLPE_MAX_INLINE_DATA_RSVD_S 8 +#define IG3_PTX4_GLPE_MAX_INLINE_DATA_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX4_GLPE_MAX_INLINE_DATA_RSVD_S) +#define IG3_PTX4_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S 0 +#define IG3_PTX4_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_MAX_INLINE_DATA_MAX_INLINE_DATA_S) +#define IG3_PTX4_GLPE_MAX_TCP_ACKS 0x44014004 +#define IG3_PTX4_GLPE_MAX_TCP_ACKS_RSVD_S 8 +#define IG3_PTX4_GLPE_MAX_TCP_ACKS_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX4_GLPE_MAX_TCP_ACKS_RSVD_S) +#define IG3_PTX4_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S 0 +#define IG3_PTX4_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_MAX_TCP_ACKS_MAX_TCP_ACKS_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0 0x44014018 +#define IG3_PTX4_GLPE_PTX_CONFIG0_RSVD_31_S 31 +#define IG3_PTX4_GLPE_PTX_CONFIG0_RSVD_31_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_RSVD_31_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S 30 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_WQE_INV_ADDL_LINES_AE_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S 29 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_QUANTA_ABORT_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S 28 +#define IG3_PTX4_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_SET_BOTH_ACKREQ_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S 27 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_IW_ID_WR_MO_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S 26 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_XMIT_WR64_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S 22 +#define IG3_PTX4_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_M RDMA_MASK3(32, 0xF, IG3_PTX4_GLPE_PTX_CONFIG0_CTXT_LOCK_WQE_LIM_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S 21 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_MRKR_CALC_OPT_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S 20 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_CMP_COALESCE_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_RSVD_19_S 19 +#define IG3_PTX4_GLPE_PTX_CONFIG0_RSVD_19_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_RSVD_19_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S 18 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_CMP_SNOOP_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S 17 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_1WQE_FRAG_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S 16 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_SNDMAX_ACKS_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S 15 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_XMIT_WR_FIFO_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S 14 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_CTXT_RELEASE_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_RSVD_13_7_S 7 +#define IG3_PTX4_GLPE_PTX_CONFIG0_RSVD_13_7_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_PTX_CONFIG0_RSVD_13_7_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_UDP_CS_EN_S 6 +#define IG3_PTX4_GLPE_PTX_CONFIG0_UDP_CS_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_UDP_CS_EN_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S 5 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_Q1_PACING_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_Q1_PACING_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S 4 +#define IG3_PTX4_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_POLICY_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S 3 +#define IG3_PTX4_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_DIS_DUP_RREQ_FILTER_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S 1 +#define IG3_PTX4_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_CONFIG0_ROCE_DUP_RRESP_OP_POLICY_S) +#define IG3_PTX4_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S 0 +#define IG3_PTX4_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_CONFIG0_ROCE_TRIM_RREQ_EN_S) +#define IG3_PTX4_GLPE_PTX_CONFIG1 0x4401401C +#define IG3_PTX4_GLPE_PTX_CONFIG1_RSVD_S 24 +#define IG3_PTX4_GLPE_PTX_CONFIG1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_CONFIG1_RSVD_S) +#define IG3_PTX4_GLPE_PTX_CONFIG1_ACKREQ_PACING_S 21 +#define IG3_PTX4_GLPE_PTX_CONFIG1_ACKREQ_PACING_M RDMA_MASK3(32, 0x7, IG3_PTX4_GLPE_PTX_CONFIG1_ACKREQ_PACING_S) +#define IG3_PTX4_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S 16 +#define IG3_PTX4_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_M RDMA_MASK3(32, 0x1F, IG3_PTX4_GLPE_PTX_CONFIG1_CWND_SHIFT_VAL_S) +#define IG3_PTX4_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S 0 +#define IG3_PTX4_GLPE_PTX_CONFIG1_Q1_PACING_MULT_M RDMA_MASK3(32, 0xFFFF, IG3_PTX4_GLPE_PTX_CONFIG1_Q1_PACING_MULT_S) +#define IG3_PTX4_GLPE_PTX_CONFIG2 0x44014020 +#define IG3_PTX4_GLPE_PTX_CONFIG2_SEND2CPU_S 0 +#define IG3_PTX4_GLPE_PTX_CONFIG2_SEND2CPU_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_CONFIG2_SEND2CPU_S) +#define IG3_PTX4_GLPE_PTX_CRT_XMIT_PTR 0x4401402C +#define IG3_PTX4_GLPE_PTX_CRT_XMIT_PTR_RSVD_S 8 +#define IG3_PTX4_GLPE_PTX_CRT_XMIT_PTR_RSVD_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX4_GLPE_PTX_CRT_XMIT_PTR_RSVD_S) +#define IG3_PTX4_GLPE_PTX_CRT_XMIT_PTR_COUNT_S 0 +#define IG3_PTX4_GLPE_PTX_CRT_XMIT_PTR_COUNT_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_CRT_XMIT_PTR_COUNT_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_COUNT 0x44014138 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_CMD 0x4401414C +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_DATA_H 0x44014158 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_DATA_L 0x44014154 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_PTR 0x44014150 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_CMD 0x4401413C +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_DATA_H 0x44014148 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_DATA_L 0x44014144 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_PTR 0x44014140 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX4_GLPE_PTX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL 0x44014100 +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD1_S 25 +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD2_S 17 +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD2_S) +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD3_S 9 +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD3_S) +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_BYPASS_S 8 +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_CONTROL_BYPASS_S) +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD4_S 1 +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_PTX_DTM_CONTROL_RSVD4_S) +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_PTX4_GLPE_PTX_DTM_ECC_COR_ERR 0x44014168 +#define IG3_PTX4_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_PTX4_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX4_GLPE_PTX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_PTX4_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_PTX4_GLPE_PTX_DTM_ECC_UNCOR_ERR 0x44014164 +#define IG3_PTX4_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_PTX4_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX4_GLPE_PTX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_PTX4_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG 0x4401410C +#define IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_PTX4_GLPE_PTX_DTM_LOG_CFG 0x44014110 +#define IG3_PTX4_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_PTX4_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_PTX4_GLPE_PTX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_PTX4_GLPE_PTX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_PTX4_GLPE_PTX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_PTX4_GLPE_PTX_DTM_LOG_CFG_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_LOG_CFG_MODE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_DTM_LOG_CFG_MODE_S) +#define IG3_PTX4_GLPE_PTX_DTM_LOG_MASK 0x44014118 +#define IG3_PTX4_GLPE_PTX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_LOG_MASK_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_LOG_PATTERN 0x44014114 +#define IG3_PTX4_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG 0x44014104 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_STS 0x44014108 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_RSVD2_S) +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TIMESTAMP 0x44014130 +#define IG3_PTX4_GLPE_PTX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_TIMESTAMP_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER 0x44014134 +#define IG3_PTX4_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG 0x4401415C +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS 0x44014160 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG 0x4401411C +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_PTX4_GLPE_PTX_DTM_TRIG_CFG_MODE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_COUNT 0x44014128 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_MASK 0x44014124 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_TRIG_MASK_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_PATTERN 0x44014120 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_TIMESTAMP 0x4401412C +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_PTX4_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHHI 0x44014028 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHHI_RSVD0_S 26 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHHI_RSVD0_M RDMA_MASK3(32, 0x3F, IG3_PTX4_GLPE_PTX_FWQPFLUSHHI_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHHI_QPID_S 6 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHHI_QPID_M RDMA_MASK3(32, 0xFFFFF, IG3_PTX4_GLPE_PTX_FWQPFLUSHHI_QPID_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S 0 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHHI_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX4_GLPE_PTX_FWQPFLUSHHI_PF_NUM_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO 0x44014024 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_BUSY_S 31 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_BUSY_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_BUSY_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S 30 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_REQ_TYPE_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_RSVD0_S 29 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_RSVD0_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_HOSTID_S 26 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_HOSTID_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S 24 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_VM_VF_TYPE_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S 12 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_VM_VF_NUM_S) +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_PMF_S 0 +#define IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_FWQPFLUSHLO_PMF_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0 0x44014044 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_TAG_S 16 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_TAG_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_MODE_S 11 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_MODE_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1 0x44014048 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_HOSTID_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_PMF_S 0 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG1_PMF_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2 0x4401404C +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2_QPID_S 6 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2_QPID_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG3 0x44014050 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG4 0x44014054 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_ST0_DTM_TRIG4_COUNT_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0 0x44014058 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_TAG_S 16 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_TAG_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_MODE_S 11 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_MODE_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1 0x4401405C +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_HOSTID_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_PMF_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG1_PMF_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2 0x44014060 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2_QPID_S 6 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2_QPID_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG3 0x44014064 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG4 0x44014068 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG4_COUNT_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT0 0x44014078 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S 1 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT0_RSVD_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT0_PKT_TYPE_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT1 0x4401407C +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT1_RSN_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT2 0x44014080 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_CRT2_RSN_MASK_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE0 0x4401406C +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S 1 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE0_RSVD_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE0_PKT_TYPE_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE1 0x44014070 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S 24 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE1_RSVD_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE1_PSN_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE2 0x44014074 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S 24 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE2_RSVD_S) +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S 0 +#define IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX4_GLPE_PTX_ST1_DTM_TRIG_ROCE2_PSN_MASK_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0 0x44014030 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S 24 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD1_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S 16 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_M RDMA_MASK3(32, 0xFF, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S 14 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S 13 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_ALL_TYPES_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S 11 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_MODE_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S 10 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_NOT_MATCH_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S 9 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_TAG_EN_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S 8 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_QPID_EN_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S 7 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_TYPE_EN_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S 6 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_VM_VF_NUM_EN_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S 5 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_PF_NUM_EN_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S 4 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_HOSTID_EN_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S 3 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_PMF_EN_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S 2 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_FLR_MATCH_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S 1 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_FLUSH_MATCH_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S 0 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_M RDMA_BIT2(32, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG0_PKT_MATCH_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1 0x44014034 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S 29 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_M RDMA_MASK3(32, 0x7, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S 26 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_M RDMA_MASK3(32, 0x7, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_HOSTID_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S 24 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_TYPE_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S 12 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_VM_VF_NUM_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S 0 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_M RDMA_MASK3(32, 0xFFF, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG1_PMF_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2 0x44014038 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S 30 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_M RDMA_MASK3(32, 0x3, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2_RSVD0_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S 6 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2_QPID_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S 0 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG2_PF_NUM_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG3 0x4401403C +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S 0 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG3_THRESHOLD_S) +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG4 0x44014040 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S 0 +#define IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_PTX4_GLPE_PTX_WTX_IF_DTM_TRIG4_COUNT_S) +#define IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD 0x44014008 +#define IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S 25 +#define IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD_RSVD_M RDMA_MASK3(32, 0x7F, IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD_RSVD_S) +#define IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S 24 +#define IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_M RDMA_BIT2(32, IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_PSN_S) +#define IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S 0 +#define IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_M RDMA_MASK3(32, 0xFFFFFF, IG3_PTX4_GLPE_TIMELY_STALL_THRESHOLD_TIMELY_THRESH_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_COUNT 0x440144B8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_CMD 0x440144CC +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_DATA_H 0x440144D8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_DATA_L 0x440144D4 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_PTR 0x440144D0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_CMD 0x440144BC +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_DATA_H 0x440144C8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_DATA_L 0x440144C4 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_PTR 0x440144C0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL 0x44014480 +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD1_S 25 +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD2_S 17 +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD2_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD3_S 9 +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD3_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_BYPASS_S 8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_BYPASS_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD4_S 1 +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_RSVD4_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_CONTROL_LOCAL_EN_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_COR_ERR 0x440144E8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX4_GLPE_SFPT_DTM_ECC_COR_ERR_CNT_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_UNCOR_ERR 0x440144E4 +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_SFPTX4_GLPE_SFPT_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG 0x4401448C +#define IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_SFPTX4_GLPE_SFPT_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG 0x44014490 +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG_MODE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX4_GLPE_SFPT_DTM_LOG_CFG_MODE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_MASK 0x44014498 +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_MASK_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_LOG_MASK_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_PATTERN 0x44014494 +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_LOG_PATTERN_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG 0x44014484 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_RSVD2_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_RSVD3_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS 0x44014488 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_RSVD2_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TIMESTAMP 0x440144B0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_TIMESTAMP_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER 0x440144B4 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG 0x440144DC +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS 0x440144E0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_SFPTX4_GLPE_SFPT_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG 0x4401449C +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_RSVD1_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_RSVD2_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_MODE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_CFG_MODE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_COUNT 0x440144A8 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_COUNT_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_MASK 0x440144A4 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_MASK_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_PATTERN 0x440144A0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_TIMESTAMP 0x440144AC +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_SFPTX4_GLPE_SFPT_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_SFPTX4_GLPE_SFP_TX_DOMAIN_ID 0x44014400 +#define IG3_SFPTX4_GLPE_SFP_TX_DOMAIN_ID_RSVD_S 3 +#define IG3_SFPTX4_GLPE_SFP_TX_DOMAIN_ID_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX4_GLPE_SFP_TX_DOMAIN_ID_RSVD_S) +#define IG3_SFPTX4_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S 0 +#define IG3_SFPTX4_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_M RDMA_MASK3(32, 0x7, IG3_SFPTX4_GLPE_SFP_TX_DOMAIN_ID_DOMAIN_ID_S) +#define IG3_SFPTX4_GLPE_SFP_TX_PER_MEM 0x44014404 +#define IG3_SFPTX4_GLPE_SFP_TX_PER_MEM_RSVD_S 3 +#define IG3_SFPTX4_GLPE_SFP_TX_PER_MEM_RSVD_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_SFPTX4_GLPE_SFP_TX_PER_MEM_RSVD_S) +#define IG3_SFPTX4_GLPE_SFP_TX_PER_MEM_PER_TYPE_S 0 +#define IG3_SFPTX4_GLPE_SFP_TX_PER_MEM_PER_TYPE_M RDMA_MASK3(32, 0x7, IG3_SFPTX4_GLPE_SFP_TX_PER_MEM_PER_TYPE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG 0x44014800 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS 0x44014804 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_AH_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG 0x44014810 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS 0x44014814 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_ARP_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_COR_ERR 0x44014834 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR 0x44014830 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG 0x44014818 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS 0x4401481C +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_FIFO01_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG 0x44014808 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS 0x4401480C +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_HO_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG 0x44014828 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS 0x4401482C +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_Q1OC_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG 0x44014820 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS 0x44014824 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_PTX_XMIT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG 0x44014840 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS 0x44014844 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG 0x44014848 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS 0x4401484C +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_AMP_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG 0x44014850 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS 0x44014854 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG 0x44014858 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS 0x4401485C +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_DBUF_TAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR 0x4401487C +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_COR_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR 0x44014878 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG 0x44014860 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS 0x44014864 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_FRAG_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG 0x44014868 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS 0x4401486C +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CMP_QUE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG 0x44014870 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS 0x44014874 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_PAL_CNTXT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG 0x44014838 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS 0x4401483C +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_SFPT_WQE_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL 0x440148C8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S 31 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RD_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_CTL_ADR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_DATA 0x440148CC +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_DBG_DATA_RD_DW_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG 0x440148C0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS 0x440148C4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_CT_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_COR_ERR 0x440148E4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_COR_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR 0x440148E0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_ECC_UNCOR_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL 0x440148D8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S 31 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RD_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_CTL_ADR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA 0x440148DC +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_DBG_DATA_RD_DW_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG 0x440148D0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS 0x440148D4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_Q1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL 0x44014888 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S 31 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RD_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_CTL_ADR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA 0x4401488C +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_DBG_DATA_RD_DW_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG 0x44014880 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS 0x44014884 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_0_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL 0x44014898 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S 31 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RD_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_CTL_ADR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA 0x4401489C +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_DBG_DATA_RD_DW_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG 0x44014890 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS 0x44014894 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_1_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL 0x440148A8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S 31 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RD_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_CTL_ADR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA 0x440148AC +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_DBG_DATA_RD_DW_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG 0x440148A0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS 0x440148A4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_2_MEM_STATUS_ECC_ERR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL 0x440148B8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S 31 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RD_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S 26 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_RSVD_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S 18 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_DW_SEL_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_CTL_ADR_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA 0x440148BC +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_DBG_DATA_RD_DW_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG 0x440148B0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INST_NUM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S 20 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD3_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S 16 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RM_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S 14 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_POWER_GATE_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RME_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S 10 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S 9 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ERR_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S 8 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_FIX_CNT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S 6 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S 5 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_MASK_INT_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_BYPASS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_LS_FORCE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_2_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_INVERT_1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_CFG_ECC_EN_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS 0x440148B4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S 30 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD1_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S 4 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_RSVD0_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S 2 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_INIT_DONE_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S 1 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_FIX_S) +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S 0 +#define IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_TILE4_TX_SHCTL_GLPE_WTX_SPAD_3_MEM_STATUS_ECC_ERR_S) +#define IG3_DRX4_GLPE_DRX_CONFIG 0x44020000 +#define IG3_DRX4_GLPE_DRX_CONFIG_RSVD1_S 3 +#define IG3_DRX4_GLPE_DRX_CONFIG_RSVD1_M RDMA_MASK3(32, 0x1FFFFFFF, IG3_DRX4_GLPE_DRX_CONFIG_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_CONFIG_CRC_MASK_S 0 +#define IG3_DRX4_GLPE_DRX_CONFIG_CRC_MASK_M RDMA_MASK3(32, 0x7, IG3_DRX4_GLPE_DRX_CONFIG_CRC_MASK_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_COUNT 0x440200B8 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_CMD 0x440200CC +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_DATA_H 0x440200D8 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_DATA_L 0x440200D4 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_PTR 0x440200D0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_CMD 0x440200BC +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_DATA_H 0x440200C8 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_DATA_L 0x440200C4 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_PTR 0x440200C0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX4_GLPE_DRX_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL 0x44020080 +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD1_S 25 +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD2_S 17 +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD2_S) +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD3_S 9 +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD3_S) +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_BYPASS_S 8 +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_CONTROL_BYPASS_S) +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD4_S 1 +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_DRX4_GLPE_DRX_DTM_CONTROL_RSVD4_S) +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_CONTROL_LOCAL_EN_S) +#define IG3_DRX4_GLPE_DRX_DTM_ECC_COR_ERR 0x440200E8 +#define IG3_DRX4_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX4_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX4_GLPE_DRX_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_DRX4_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX4_GLPE_DRX_DTM_ECC_COR_ERR_CNT_S) +#define IG3_DRX4_GLPE_DRX_DTM_ECC_UNCOR_ERR 0x440200E4 +#define IG3_DRX4_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX4_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX4_GLPE_DRX_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX4_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX4_GLPE_DRX_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG 0x4402008C +#define IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_DRX4_GLPE_DRX_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_DRX4_GLPE_DRX_DTM_LOG_CFG 0x44020090 +#define IG3_DRX4_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_DRX4_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_DRX4_GLPE_DRX_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_DRX4_GLPE_DRX_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_DRX4_GLPE_DRX_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_DRX4_GLPE_DRX_DTM_LOG_CFG_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_LOG_CFG_MODE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_DRX_DTM_LOG_CFG_MODE_S) +#define IG3_DRX4_GLPE_DRX_DTM_LOG_MASK 0x44020098 +#define IG3_DRX4_GLPE_DRX_DTM_LOG_MASK_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_LOG_MASK_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_LOG_PATTERN 0x44020094 +#define IG3_DRX4_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_LOG_PATTERN_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG 0x44020084 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_RSVD2_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_RSVD3_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_STS 0x44020088 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_RSVD2_S) +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TIMESTAMP 0x440200B0 +#define IG3_DRX4_GLPE_DRX_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_TIMESTAMP_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER 0x440200B4 +#define IG3_DRX4_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG 0x440200DC +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS 0x440200E0 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX4_GLPE_DRX_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG 0x4402009C +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_RSVD1_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_RSVD2_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_MODE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_DRX4_GLPE_DRX_DTM_TRIG_CFG_MODE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_COUNT 0x440200A8 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_TRIG_COUNT_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_MASK 0x440200A4 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_TRIG_MASK_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_PATTERN 0x440200A0 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_TIMESTAMP 0x440200AC +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_DRX4_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_DRX4_GLPE_DRX_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_DRX4_GLPE_DRX_ECC_COR_ERR 0x44020004 +#define IG3_DRX4_GLPE_DRX_ECC_COR_ERR_RSVD_S 12 +#define IG3_DRX4_GLPE_DRX_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX4_GLPE_DRX_ECC_COR_ERR_RSVD_S) +#define IG3_DRX4_GLPE_DRX_ECC_COR_ERR_CNT_S 0 +#define IG3_DRX4_GLPE_DRX_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX4_GLPE_DRX_ECC_COR_ERR_CNT_S) +#define IG3_DRX4_GLPE_DRX_ECC_UNCOR_ERR 0x44020008 +#define IG3_DRX4_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_DRX4_GLPE_DRX_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_DRX4_GLPE_DRX_ECC_UNCOR_ERR_RSVD_S) +#define IG3_DRX4_GLPE_DRX_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_DRX4_GLPE_DRX_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_DRX4_GLPE_DRX_ECC_UNCOR_ERR_CNT_S) +#define IG3_DRX4_GLPE_PBUF_CFG 0x4402000C +#define IG3_DRX4_GLPE_PBUF_CFG_ECC_INST_NUM_S 25 +#define IG3_DRX4_GLPE_PBUF_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_DRX4_GLPE_PBUF_CFG_ECC_INST_NUM_S) +#define IG3_DRX4_GLPE_PBUF_CFG_RSVD3_S 20 +#define IG3_DRX4_GLPE_PBUF_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_DRX4_GLPE_PBUF_CFG_RSVD3_S) +#define IG3_DRX4_GLPE_PBUF_CFG_RM_S 16 +#define IG3_DRX4_GLPE_PBUF_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_DRX4_GLPE_PBUF_CFG_RM_S) +#define IG3_DRX4_GLPE_PBUF_CFG_RSVD2_S 14 +#define IG3_DRX4_GLPE_PBUF_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_PBUF_CFG_RSVD2_S) +#define IG3_DRX4_GLPE_PBUF_CFG_POWER_GATE_EN_S 13 +#define IG3_DRX4_GLPE_PBUF_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_POWER_GATE_EN_S) +#define IG3_DRX4_GLPE_PBUF_CFG_RME_S 12 +#define IG3_DRX4_GLPE_PBUF_CFG_RME_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_RME_S) +#define IG3_DRX4_GLPE_PBUF_CFG_RSVD1_S 10 +#define IG3_DRX4_GLPE_PBUF_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_PBUF_CFG_RSVD1_S) +#define IG3_DRX4_GLPE_PBUF_CFG_ERR_CNT_S 9 +#define IG3_DRX4_GLPE_PBUF_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_ERR_CNT_S) +#define IG3_DRX4_GLPE_PBUF_CFG_FIX_CNT_S 8 +#define IG3_DRX4_GLPE_PBUF_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_FIX_CNT_S) +#define IG3_DRX4_GLPE_PBUF_CFG_RSVD0_S 6 +#define IG3_DRX4_GLPE_PBUF_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_PBUF_CFG_RSVD0_S) +#define IG3_DRX4_GLPE_PBUF_CFG_MASK_INT_S 5 +#define IG3_DRX4_GLPE_PBUF_CFG_MASK_INT_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_MASK_INT_S) +#define IG3_DRX4_GLPE_PBUF_CFG_LS_BYPASS_S 4 +#define IG3_DRX4_GLPE_PBUF_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_LS_BYPASS_S) +#define IG3_DRX4_GLPE_PBUF_CFG_LS_FORCE_S 3 +#define IG3_DRX4_GLPE_PBUF_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_LS_FORCE_S) +#define IG3_DRX4_GLPE_PBUF_CFG_ECC_INVERT_2_S 2 +#define IG3_DRX4_GLPE_PBUF_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_ECC_INVERT_2_S) +#define IG3_DRX4_GLPE_PBUF_CFG_ECC_INVERT_1_S 1 +#define IG3_DRX4_GLPE_PBUF_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_ECC_INVERT_1_S) +#define IG3_DRX4_GLPE_PBUF_CFG_ECC_EN_S 0 +#define IG3_DRX4_GLPE_PBUF_CFG_ECC_EN_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_CFG_ECC_EN_S) +#define IG3_DRX4_GLPE_PBUF_STATUS 0x44020010 +#define IG3_DRX4_GLPE_PBUF_STATUS_RSVD1_S 30 +#define IG3_DRX4_GLPE_PBUF_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_DRX4_GLPE_PBUF_STATUS_RSVD1_S) +#define IG3_DRX4_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_DRX4_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_DRX4_GLPE_PBUF_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_DRX4_GLPE_PBUF_STATUS_RSVD0_S 4 +#define IG3_DRX4_GLPE_PBUF_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_DRX4_GLPE_PBUF_STATUS_RSVD0_S) +#define IG3_DRX4_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_DRX4_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_DRX4_GLPE_PBUF_STATUS_INIT_DONE_S 2 +#define IG3_DRX4_GLPE_PBUF_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_STATUS_INIT_DONE_S) +#define IG3_DRX4_GLPE_PBUF_STATUS_ECC_FIX_S 1 +#define IG3_DRX4_GLPE_PBUF_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_STATUS_ECC_FIX_S) +#define IG3_DRX4_GLPE_PBUF_STATUS_ECC_ERR_S 0 +#define IG3_DRX4_GLPE_PBUF_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_DRX4_GLPE_PBUF_STATUS_ECC_ERR_S) +#define IG3_CMPE4_CMPE_ECC_COR_ERR 0x4402053C +#define IG3_CMPE4_CMPE_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE4_CMPE_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_CMPE_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE4_CMPE_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE4_CMPE_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_CMPE_ECC_COR_ERR_CNT_S) +#define IG3_CMPE4_CMPE_ECC_UNCOR_ERR 0x44020538 +#define IG3_CMPE4_CMPE_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE4_CMPE_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_CMPE_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE4_CMPE_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE4_CMPE_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_CMPE_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE4_GLCM_PECLSADDR 0x44020484 +#define IG3_CMPE4_GLCM_PECLSADDR_RSVD_S 9 +#define IG3_CMPE4_GLCM_PECLSADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE4_GLCM_PECLSADDR_RSVD_S) +#define IG3_CMPE4_GLCM_PECLSADDR_CLS_ADDR_S 0 +#define IG3_CMPE4_GLCM_PECLSADDR_CLS_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE4_GLCM_PECLSADDR_CLS_ADDR_S) +#define IG3_CMPE4_GLCM_PECLSDATA0 0x44020488 +#define IG3_CMPE4_GLCM_PECLSDATA0_CLS_DATA_S 0 +#define IG3_CMPE4_GLCM_PECLSDATA0_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLCM_PECLSDATA0_CLS_DATA_S) +#define IG3_CMPE4_GLCM_PECLSDATA1 0x4402048C +#define IG3_CMPE4_GLCM_PECLSDATA1_CLS_DATA_S 0 +#define IG3_CMPE4_GLCM_PECLSDATA1_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLCM_PECLSDATA1_CLS_DATA_S) +#define IG3_CMPE4_GLCM_PECLSDATA2 0x44020490 +#define IG3_CMPE4_GLCM_PECLSDATA2_CLS_DATA_S 0 +#define IG3_CMPE4_GLCM_PECLSDATA2_CLS_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLCM_PECLSDATA2_CLS_DATA_S) +#define IG3_CMPE4_GLCM_PECONFIG 0x44020480 +#define IG3_CMPE4_GLCM_PECONFIG_DBGMUX_EN_S 31 +#define IG3_CMPE4_GLCM_PECONFIG_DBGMUX_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_DBGMUX_EN_S) +#define IG3_CMPE4_GLCM_PECONFIG_RSVD13_S 30 +#define IG3_CMPE4_GLCM_PECONFIG_RSVD13_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_RSVD13_S) +#define IG3_CMPE4_GLCM_PECONFIG_DBGMUX_SEL_HI_S 25 +#define IG3_CMPE4_GLCM_PECONFIG_DBGMUX_SEL_HI_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PECONFIG_DBGMUX_SEL_HI_S) +#define IG3_CMPE4_GLCM_PECONFIG_DBGMUX_SEL_LO_S 20 +#define IG3_CMPE4_GLCM_PECONFIG_DBGMUX_SEL_LO_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PECONFIG_DBGMUX_SEL_LO_S) +#define IG3_CMPE4_GLCM_PECONFIG_RSVD10_S 17 +#define IG3_CMPE4_GLCM_PECONFIG_RSVD10_M RDMA_MASK3(32, 0x7, IG3_CMPE4_GLCM_PECONFIG_RSVD10_S) +#define IG3_CMPE4_GLCM_PECONFIG_DBG_WRSEL_S 16 +#define IG3_CMPE4_GLCM_PECONFIG_DBG_WRSEL_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_DBG_WRSEL_S) +#define IG3_CMPE4_GLCM_PECONFIG_DBG_DWSEL_S 14 +#define IG3_CMPE4_GLCM_PECONFIG_DBG_DWSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PECONFIG_DBG_DWSEL_S) +#define IG3_CMPE4_GLCM_PECONFIG_DBG_DPSEL_S 12 +#define IG3_CMPE4_GLCM_PECONFIG_DBG_DPSEL_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PECONFIG_DBG_DPSEL_S) +#define IG3_CMPE4_GLCM_PECONFIG_RSVD6_S 7 +#define IG3_CMPE4_GLCM_PECONFIG_RSVD6_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PECONFIG_RSVD6_S) +#define IG3_CMPE4_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S 6 +#define IG3_CMPE4_GLCM_PECONFIG_DISABLE_CTXT_PACKING_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_DISABLE_CTXT_PACKING_S) +#define IG3_CMPE4_GLCM_PECONFIG_DISABLE_LSA_S 5 +#define IG3_CMPE4_GLCM_PECONFIG_DISABLE_LSA_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_DISABLE_LSA_S) +#define IG3_CMPE4_GLCM_PECONFIG_ENABLE_CRC_S 4 +#define IG3_CMPE4_GLCM_PECONFIG_ENABLE_CRC_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_ENABLE_CRC_S) +#define IG3_CMPE4_GLCM_PECONFIG_DISABLE_RESCHEDULE_S 3 +#define IG3_CMPE4_GLCM_PECONFIG_DISABLE_RESCHEDULE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_DISABLE_RESCHEDULE_S) +#define IG3_CMPE4_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S 2 +#define IG3_CMPE4_GLCM_PECONFIG_DISABLE_PACKET_COUNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_DISABLE_PACKET_COUNT_S) +#define IG3_CMPE4_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S 1 +#define IG3_CMPE4_GLCM_PECONFIG_GLOBAL_LOCK_MODE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_GLOBAL_LOCK_MODE_S) +#define IG3_CMPE4_GLCM_PECONFIG_RSVD1_S 0 +#define IG3_CMPE4_GLCM_PECONFIG_RSVD1_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECONFIG_RSVD1_S) +#define IG3_CMPE4_GLCM_PECTXDGCTL 0x440204C8 +#define IG3_CMPE4_GLCM_PECTXDGCTL_RSVD_S 12 +#define IG3_CMPE4_GLCM_PECTXDGCTL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_GLCM_PECTXDGCTL_RSVD_S) +#define IG3_CMPE4_GLCM_PECTXDGCTL_PKTCNT_S 10 +#define IG3_CMPE4_GLCM_PECTXDGCTL_PKTCNT_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PECTXDGCTL_PKTCNT_S) +#define IG3_CMPE4_GLCM_PECTXDGCTL_OP_CODE_S 8 +#define IG3_CMPE4_GLCM_PECTXDGCTL_OP_CODE_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PECTXDGCTL_OP_CODE_S) +#define IG3_CMPE4_GLCM_PECTXDGCTL_ALLOCATE_S 7 +#define IG3_CMPE4_GLCM_PECTXDGCTL_ALLOCATE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECTXDGCTL_ALLOCATE_S) +#define IG3_CMPE4_GLCM_PECTXDGCTL_WRITEBACK_S 6 +#define IG3_CMPE4_GLCM_PECTXDGCTL_WRITEBACK_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECTXDGCTL_WRITEBACK_S) +#define IG3_CMPE4_GLCM_PECTXDGCTL_INVALIDATE_S 5 +#define IG3_CMPE4_GLCM_PECTXDGCTL_INVALIDATE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECTXDGCTL_INVALIDATE_S) +#define IG3_CMPE4_GLCM_PECTXDGCTL_SUB_LINE_S 0 +#define IG3_CMPE4_GLCM_PECTXDGCTL_SUB_LINE_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PECTXDGCTL_SUB_LINE_S) +#define IG3_CMPE4_GLCM_PECTXDGDATA(_i) 0x440204CC + ((_i) * 4) /* _i=0...3 */ +#define IG3_CMPE4_GLCM_PECTXDGDATA_MAX_INDEX_I 3 +#define IG3_CMPE4_GLCM_PECTXDGDATA_DATA_S 0 +#define IG3_CMPE4_GLCM_PECTXDGDATA_DATA_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLCM_PECTXDGDATA_DATA_S) +#define IG3_CMPE4_GLCM_PECTXDGFN 0x440204C0 +#define IG3_CMPE4_GLCM_PECTXDGFN_RSVD_S 20 +#define IG3_CMPE4_GLCM_PECTXDGFN_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLCM_PECTXDGFN_RSVD_S) +#define IG3_CMPE4_GLCM_PECTXDGFN_FUNC_TRIPLET_S 0 +#define IG3_CMPE4_GLCM_PECTXDGFN_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_GLCM_PECTXDGFN_FUNC_TRIPLET_S) +#define IG3_CMPE4_GLCM_PECTXDGQP 0x440204C4 +#define IG3_CMPE4_GLCM_PECTXDGQP_RSVD_S 24 +#define IG3_CMPE4_GLCM_PECTXDGQP_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PECTXDGQP_RSVD_S) +#define IG3_CMPE4_GLCM_PECTXDGQP_QUEUE_NUM_S 0 +#define IG3_CMPE4_GLCM_PECTXDGQP_QUEUE_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE4_GLCM_PECTXDGQP_QUEUE_NUM_S) +#define IG3_CMPE4_GLCM_PECTXDGSTAT 0x440204DC +#define IG3_CMPE4_GLCM_PECTXDGSTAT_RSVD_S 2 +#define IG3_CMPE4_GLCM_PECTXDGSTAT_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE4_GLCM_PECTXDGSTAT_RSVD_S) +#define IG3_CMPE4_GLCM_PECTXDGSTAT_CTX_MISS_S 1 +#define IG3_CMPE4_GLCM_PECTXDGSTAT_CTX_MISS_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECTXDGSTAT_CTX_MISS_S) +#define IG3_CMPE4_GLCM_PECTXDGSTAT_CTX_DONE_S 0 +#define IG3_CMPE4_GLCM_PECTXDGSTAT_CTX_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PECTXDGSTAT_CTX_DONE_S) +#define IG3_CMPE4_GLCM_PEDATAREQHI 0x440204B4 +#define IG3_CMPE4_GLCM_PEDATAREQHI_RSVD_S 24 +#define IG3_CMPE4_GLCM_PEDATAREQHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PEDATAREQHI_RSVD_S) +#define IG3_CMPE4_GLCM_PEDATAREQHI_DATAREQHI_S 0 +#define IG3_CMPE4_GLCM_PEDATAREQHI_DATAREQHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE4_GLCM_PEDATAREQHI_DATAREQHI_S) +#define IG3_CMPE4_GLCM_PEDATAREQLO 0x440204B0 +#define IG3_CMPE4_GLCM_PEDATAREQLO_DATAREQLOW_S 0 +#define IG3_CMPE4_GLCM_PEDATAREQLO_DATAREQLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLCM_PEDATAREQLO_DATAREQLOW_S) +#define IG3_CMPE4_GLCM_PEDATASTALLHI 0x440204BC +#define IG3_CMPE4_GLCM_PEDATASTALLHI_RSVD_S 24 +#define IG3_CMPE4_GLCM_PEDATASTALLHI_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PEDATASTALLHI_RSVD_S) +#define IG3_CMPE4_GLCM_PEDATASTALLHI_DATASTALLHI_S 0 +#define IG3_CMPE4_GLCM_PEDATASTALLHI_DATASTALLHI_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE4_GLCM_PEDATASTALLHI_DATASTALLHI_S) +#define IG3_CMPE4_GLCM_PEDATASTALLLO 0x440204B8 +#define IG3_CMPE4_GLCM_PEDATASTALLLO_DATASTALLLOW_S 0 +#define IG3_CMPE4_GLCM_PEDATASTALLLO_DATASTALLLOW_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLCM_PEDATASTALLLO_DATASTALLLOW_S) +#define IG3_CMPE4_GLCM_PELOCKTBLADDR 0x4402049C +#define IG3_CMPE4_GLCM_PELOCKTBLADDR_RSVD_S 5 +#define IG3_CMPE4_GLCM_PELOCKTBLADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFFF, IG3_CMPE4_GLCM_PELOCKTBLADDR_RSVD_S) +#define IG3_CMPE4_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S 0 +#define IG3_CMPE4_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PELOCKTBLADDR_LOCKTBL_ADDR_S) +#define IG3_CMPE4_GLCM_PELOCKTBLDATA0 0x440204A0 +#define IG3_CMPE4_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S 31 +#define IG3_CMPE4_GLCM_PELOCKTBLDATA0_GPLOCKSEL_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PELOCKTBLDATA0_GPLOCKSEL_S) +#define IG3_CMPE4_GLCM_PELOCKTBLDATA0_RSVD_S 24 +#define IG3_CMPE4_GLCM_PELOCKTBLDATA0_RSVD_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PELOCKTBLDATA0_RSVD_S) +#define IG3_CMPE4_GLCM_PELOCKTBLDATA0_QPID_S 0 +#define IG3_CMPE4_GLCM_PELOCKTBLDATA0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE4_GLCM_PELOCKTBLDATA0_QPID_S) +#define IG3_CMPE4_GLCM_PELOCKTBLDATA1 0x440204A4 +#define IG3_CMPE4_GLCM_PELOCKTBLDATA1_RSVD_S 20 +#define IG3_CMPE4_GLCM_PELOCKTBLDATA1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLCM_PELOCKTBLDATA1_RSVD_S) +#define IG3_CMPE4_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S 0 +#define IG3_CMPE4_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_GLCM_PELOCKTBLDATA1_FUNC_TRIPLET_S) +#define IG3_CMPE4_GLCM_PELOCKTBLDATA2 0x440204A8 +#define IG3_CMPE4_GLCM_PELOCKTBLDATA2_LOCKSEL_S 0 +#define IG3_CMPE4_GLCM_PELOCKTBLDATA2_LOCKSEL_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLCM_PELOCKTBLDATA2_LOCKSEL_S) +#define IG3_CMPE4_GLCM_PEPKTCNTADDR 0x44020494 +#define IG3_CMPE4_GLCM_PEPKTCNTADDR_RSVD_S 9 +#define IG3_CMPE4_GLCM_PEPKTCNTADDR_RSVD_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE4_GLCM_PEPKTCNTADDR_RSVD_S) +#define IG3_CMPE4_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S 0 +#define IG3_CMPE4_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_M RDMA_MASK3(32, 0x1FF, IG3_CMPE4_GLCM_PEPKTCNTADDR_PKTCNT_ADDR_S) +#define IG3_CMPE4_GLCM_PEPKTCNTDATA 0x44020498 +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_RSVD1_S 18 +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE4_GLCM_PEPKTCNTDATA_RSVD1_S) +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_RLRSP_STATE_S 16 +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_RLRSP_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PEPKTCNTDATA_RLRSP_STATE_S) +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_RSVD0_S 14 +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PEPKTCNTDATA_RSVD0_S) +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_RLREQ_STATE_S 12 +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_RLREQ_STATE_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PEPKTCNTDATA_RLREQ_STATE_S) +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_PKTCNT_S 1 +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_PKTCNT_M RDMA_MASK3(32, 0x7FF, IG3_CMPE4_GLCM_PEPKTCNTDATA_PKTCNT_S) +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_DONE_S 0 +#define IG3_CMPE4_GLCM_PEPKTCNTDATA_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PEPKTCNTDATA_DONE_S) +#define IG3_CMPE4_GLCM_PESTATSCTL 0x440204AC +#define IG3_CMPE4_GLCM_PESTATSCTL_RSVD_S 2 +#define IG3_CMPE4_GLCM_PESTATSCTL_RSVD_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_CMPE4_GLCM_PESTATSCTL_RSVD_S) +#define IG3_CMPE4_GLCM_PESTATSCTL_ENABLE_S 1 +#define IG3_CMPE4_GLCM_PESTATSCTL_ENABLE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PESTATSCTL_ENABLE_S) +#define IG3_CMPE4_GLCM_PESTATSCTL_CLEAR_S 0 +#define IG3_CMPE4_GLCM_PESTATSCTL_CLEAR_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PESTATSCTL_CLEAR_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG 0x44020500 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RM_S 16 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RM_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RME_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RME_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS 0x44020504 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG 0x44020508 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RM_S 16 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RM_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RME_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RME_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS 0x4402050C +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE0_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG 0x44020510 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD3_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RM_S 16 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RM_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD2_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RME_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RME_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_MASK_INT_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_CFG_ECC_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS 0x44020514 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_0_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG 0x44020518 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD3_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RM_S 16 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RM_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD2_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RME_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RME_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_MASK_INT_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_CFG_ECC_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS 0x4402051C +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE1_1_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG 0x44020520 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD3_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RM_S 16 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RM_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD2_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RME_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RME_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_MASK_INT_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_CFG_ECC_EN_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS 0x44020524 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_CACHE2_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE4_GLCM_PE_CACHESIZE 0x440204E4 +#define IG3_CMPE4_GLCM_PE_CACHESIZE_RSVD_S 26 +#define IG3_CMPE4_GLCM_PE_CACHESIZE_RSVD_M RDMA_MASK3(32, 0x3F, IG3_CMPE4_GLCM_PE_CACHESIZE_RSVD_S) +#define IG3_CMPE4_GLCM_PE_CACHESIZE_WAYS_S 16 +#define IG3_CMPE4_GLCM_PE_CACHESIZE_WAYS_M RDMA_MASK3(32, 0x3FF, IG3_CMPE4_GLCM_PE_CACHESIZE_WAYS_S) +#define IG3_CMPE4_GLCM_PE_CACHESIZE_SETS_S 12 +#define IG3_CMPE4_GLCM_PE_CACHESIZE_SETS_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLCM_PE_CACHESIZE_SETS_S) +#define IG3_CMPE4_GLCM_PE_CACHESIZE_WORD_SIZE_S 0 +#define IG3_CMPE4_GLCM_PE_CACHESIZE_WORD_SIZE_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLCM_PE_CACHESIZE_WORD_SIZE_S) +#define IG3_CMPE4_GLCM_PE_DPC_COMP 0x440204F4 +#define IG3_CMPE4_GLCM_PE_DPC_COMP_RSVD_S 13 +#define IG3_CMPE4_GLCM_PE_DPC_COMP_RSVD_M RDMA_MASK3(32, 0x7FFFF, IG3_CMPE4_GLCM_PE_DPC_COMP_RSVD_S) +#define IG3_CMPE4_GLCM_PE_DPC_COMP_COMP_FTYPE_S 11 +#define IG3_CMPE4_GLCM_PE_DPC_COMP_COMP_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_DPC_COMP_COMP_FTYPE_S) +#define IG3_CMPE4_GLCM_PE_DPC_COMP_COMP_FNUM_S 1 +#define IG3_CMPE4_GLCM_PE_DPC_COMP_COMP_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE4_GLCM_PE_DPC_COMP_COMP_FNUM_S) +#define IG3_CMPE4_GLCM_PE_DPC_COMP_COMP_VALID_S 0 +#define IG3_CMPE4_GLCM_PE_DPC_COMP_COMP_VALID_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_DPC_COMP_COMP_VALID_S) +#define IG3_CMPE4_GLCM_PE_DPC_REQ 0x440204F0 +#define IG3_CMPE4_GLCM_PE_DPC_REQ_RSVD_S 12 +#define IG3_CMPE4_GLCM_PE_DPC_REQ_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_GLCM_PE_DPC_REQ_RSVD_S) +#define IG3_CMPE4_GLCM_PE_DPC_REQ_REQ_FTYPE_S 10 +#define IG3_CMPE4_GLCM_PE_DPC_REQ_REQ_FTYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_DPC_REQ_REQ_FTYPE_S) +#define IG3_CMPE4_GLCM_PE_DPC_REQ_REQ_FNUM_S 0 +#define IG3_CMPE4_GLCM_PE_DPC_REQ_REQ_FNUM_M RDMA_MASK3(32, 0x3FF, IG3_CMPE4_GLCM_PE_DPC_REQ_REQ_FNUM_S) +#define IG3_CMPE4_GLCM_PE_E2E_FC 0x440204F8 +#define IG3_CMPE4_GLCM_PE_E2E_FC_RSVD1_S 22 +#define IG3_CMPE4_GLCM_PE_E2E_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE4_GLCM_PE_E2E_FC_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE4_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE4_GLCM_PE_E2E_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE4_GLCM_PE_E2E_FC_RSVD0_S 9 +#define IG3_CMPE4_GLCM_PE_E2E_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PE_E2E_FC_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE4_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE4_GLCM_PE_E2E_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG 0x44020528 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RM_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RME_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS 0x4402052C +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_EVICTBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG 0x44020530 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_INST_NUM_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S 20 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD3_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RM_S 16 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RM_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S 14 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD2_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_POWER_GATE_EN_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RME_S 12 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RME_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RME_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S 10 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S 9 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ERR_CNT_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S 8 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_FIX_CNT_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S 6 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S 5 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_MASK_INT_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S 4 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_LS_BYPASS_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S 3 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_LS_FORCE_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_2_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_INVERT_1_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S 0 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_CFG_ECC_EN_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS 0x44020534 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S 30 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S 4 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S 2 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_INIT_DONE_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S 1 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_ECC_FIX_S) +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S 0 +#define IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE4_GLCM_PE_FILLBUF_MEM_STATUS_ECC_ERR_S) +#define IG3_CMPE4_GLCM_PE_IF_FC 0x440204FC +#define IG3_CMPE4_GLCM_PE_IF_FC_RSVD1_S 22 +#define IG3_CMPE4_GLCM_PE_IF_FC_RSVD1_M RDMA_MASK3(32, 0x3FF, IG3_CMPE4_GLCM_PE_IF_FC_RSVD1_S) +#define IG3_CMPE4_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S 16 +#define IG3_CMPE4_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_M RDMA_MASK3(32, 0x3F, IG3_CMPE4_GLCM_PE_IF_FC_HMC_FC_THRESHOLD_S) +#define IG3_CMPE4_GLCM_PE_IF_FC_RSVD0_S 9 +#define IG3_CMPE4_GLCM_PE_IF_FC_RSVD0_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLCM_PE_IF_FC_RSVD0_S) +#define IG3_CMPE4_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S 0 +#define IG3_CMPE4_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_M RDMA_MASK3(32, 0x1FF, IG3_CMPE4_GLCM_PE_IF_FC_CMPE_FC_THRESHOLD_S) +#define IG3_CMPE4_GLCM_PE_MAXOSR 0x440204E0 +#define IG3_CMPE4_GLCM_PE_MAXOSR_RSVD_S 6 +#define IG3_CMPE4_GLCM_PE_MAXOSR_RSVD_M RDMA_MASK3(32, 0x3FFFFFF, IG3_CMPE4_GLCM_PE_MAXOSR_RSVD_S) +#define IG3_CMPE4_GLCM_PE_MAXOSR_MAXOSR_S 0 +#define IG3_CMPE4_GLCM_PE_MAXOSR_MAXOSR_M RDMA_MASK3(32, 0x3F, IG3_CMPE4_GLCM_PE_MAXOSR_MAXOSR_S) +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL0 0x440204E8 +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL0_RSVD_S 24 +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL0_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLCM_PE_RLDDBGCTL0_RSVD_S) +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL0_QPID_S 0 +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL0_QPID_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE4_GLCM_PE_RLDDBGCTL0_QPID_S) +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL1 0x440204EC +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL1_RSVD_S 20 +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL1_RSVD_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLCM_PE_RLDDBGCTL1_RSVD_S) +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S 18 +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLCM_PE_RLDDBGCTL1_VM_VF_TYPE_S) +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S 6 +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLCM_PE_RLDDBGCTL1_VM_VF_NUM_S) +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL1_PF_NUM_S 0 +#define IG3_CMPE4_GLCM_PE_RLDDBGCTL1_PF_NUM_M RDMA_MASK3(32, 0x3F, IG3_CMPE4_GLCM_PE_RLDDBGCTL1_PF_NUM_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_COUNT 0x440205B8 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S 20 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_COUNT_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_COUNT_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_CMD 0x440205CC +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S 1 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_CMD_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_CMD_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_DATA_H 0x440205D8 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_DATA_H_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_DATA_L 0x440205D4 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_DATA_L_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_PTR 0x440205D0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S 20 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_PTR_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_RD_PTR_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_CMD 0x440205BC +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S 1 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_CMD_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_CMD_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_DATA_H 0x440205C8 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_DATA_H_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_DATA_L 0x440205C4 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_DATA_L_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_PTR 0x440205C0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S 20 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_PTR_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_BUFFER_WR_PTR_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL 0x44020580 +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD1_S 25 +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD1_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S 24 +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_SOFT_CLEAR_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD2_S 17 +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD2_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S 16 +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_FORCE_TRIG_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD3_S 9 +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD3_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD3_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_BYPASS_S 8 +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_BYPASS_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_BYPASS_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD4_S 1 +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD4_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_RSVD4_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_CONTROL_LOCAL_EN_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_COR_ERR 0x440205E8 +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S 12 +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_ECC_COR_ERR_RSVD_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLPE_CMPE_DTM_ECC_COR_ERR_CNT_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_UNCOR_ERR 0x440205E4 +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S 12 +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_ECC_UNCOR_ERR_RSVD_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_GLPE_CMPE_DTM_ECC_UNCOR_ERR_CNT_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG 0x4402058C +#define IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S 24 +#define IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S 16 +#define IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_TRIG_GROUP_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S 8 +#define IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_LOG_MSGROUP_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLPE_CMPE_DTM_GROUP_CFG_LOG_LSGROUP_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG 0x44020590 +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S 16 +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_M RDMA_MASK3(32, 0xFFFF, IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG_LOG_POST_TRIG_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S 2 +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG_MODE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG_MODE_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLPE_CMPE_DTM_LOG_CFG_MODE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_MASK 0x44020598 +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_MASK_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_LOG_MASK_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_PATTERN 0x44020594 +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_LOG_PATTERN_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG 0x44020584 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S 26 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_M RDMA_MASK3(32, 0x3F, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S 24 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_EXTMODE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S 17 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_RSVD2_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S 16 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_TIMESTAMP_DIS_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S 1 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_M RDMA_MASK3(32, 0x7FFF, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_RSVD3_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_CFG_EXT_TRIGOUT_DIS_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS 0x44020588 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S 9 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_RSVD1_M RDMA_MASK3(32, 0x7FFFFF, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S 8 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_TRACE_ERR_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S 1 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_RSVD2_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_RSVD2_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_MAIN_STS_TRACE_DONE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TIMESTAMP 0x440205B0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_TIMESTAMP_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER 0x440205B4 +#define IG3_CMPE4_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_TIMESTAMP_ROLLOVER_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG 0x440205DC +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S 25 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_M RDMA_MASK3(32, 0x7F, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INST_NUM_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S 20 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_M RDMA_MASK3(32, 0x1F, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD3_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S 16 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RM_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S 14 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD2_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S 13 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_POWER_GATE_EN_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S 12 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RME_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S 10 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S 9 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ERR_CNT_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S 8 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_FIX_CNT_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S 6 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_RSVD0_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S 5 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_MASK_INT_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S 4 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_BYPASS_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S 3 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_LS_FORCE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S 2 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_2_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S 1 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_INVERT_1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_CFG_ECC_EN_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS 0x440205E0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S 30 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_M RDMA_MASK3(32, 0x3, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S 12 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_M RDMA_MASK3(32, 0x3FFFF, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERROR_ADDRESS_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S 4 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_RSVD0_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S 3 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_GLOBAL_INIT_DONE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S 2 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_INIT_DONE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S 1 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_FIX_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_M RDMA_BIT2(32, IG3_CMPE4_GLPE_CMPE_DTM_TRACE_BUFFER_STATUS_ECC_ERR_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG 0x4402059C +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S 24 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_RSVD1_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S 16 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_EVENT_WIDTH_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S 8 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_COUNTDOWN_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S 4 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_RSVD2_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_MODE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_MODE_M RDMA_MASK3(32, 0xF, IG3_CMPE4_GLPE_CMPE_DTM_TRIG_CFG_MODE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_COUNT 0x440205A8 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_TRIG_COUNT_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_MASK 0x440205A4 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_MASK_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_TRIG_MASK_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_PATTERN 0x440205A0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_TRIG_PATTERN_VALUE_S) +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_TIMESTAMP 0x440205AC +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S 0 +#define IG3_CMPE4_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_M RDMA_MASK3(32, 0xFFFFFFFF, IG3_CMPE4_GLPE_CMPE_DTM_TRIG_TIMESTAMP_VALUE_S) +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0(_i) 0x44020400 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_MAX_INDEX_I 15 +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_RSVD1_S 18 +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_RSVD1_M RDMA_MASK3(32, 0x3FFF, IG3_CMPE4_PFCM_PE_CRCERRINFO0_RSVD1_S) +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S 16 +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_M RDMA_MASK3(32, 0x3, IG3_CMPE4_PFCM_PE_CRCERRINFO0_VM_VF_TYPE_S) +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S 4 +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_VM_VF_NUM_M RDMA_MASK3(32, 0xFFF, IG3_CMPE4_PFCM_PE_CRCERRINFO0_VM_VF_NUM_S) +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_RSVD0_S 1 +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_RSVD0_M RDMA_MASK3(32, 0x7, IG3_CMPE4_PFCM_PE_CRCERRINFO0_RSVD0_S) +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S 0 +#define IG3_CMPE4_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_M RDMA_BIT2(32, IG3_CMPE4_PFCM_PE_CRCERRINFO0_ERROR_DETECTED_S) +#define IG3_CMPE4_PFCM_PE_CRCERRINFO1(_i) 0x44020440 + ((_i) * 4) /* _i=0...15 */ +#define IG3_CMPE4_PFCM_PE_CRCERRINFO1_MAX_INDEX_I 15 +#define IG3_CMPE4_PFCM_PE_CRCERRINFO1_RSVD_S 24 +#define IG3_CMPE4_PFCM_PE_CRCERRINFO1_RSVD_M RDMA_MASK3(32, 0xFF, IG3_CMPE4_PFCM_PE_CRCERRINFO1_RSVD_S) +#define IG3_CMPE4_PFCM_PE_CRCERRINFO1_Q_NUM_S 0 +#define IG3_CMPE4_PFCM_PE_CRCERRINFO1_Q_NUM_M RDMA_MASK3(32, 0xFFFFFF, IG3_CMPE4_PFCM_PE_CRCERRINFO1_Q_NUM_S) +#define IG3_GPV_COMP_ID_0 0x44E01FF0 +#define IG3_GPV_COMP_ID_0_RSVD0_S 8 +#define IG3_GPV_COMP_ID_0_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_COMP_ID_0_RSVD0_S) +#define IG3_GPV_COMP_ID_0_COMP_ID_0_S 0 +#define IG3_GPV_COMP_ID_0_COMP_ID_0_M RDMA_MASK3(32, 0xFF, IG3_GPV_COMP_ID_0_COMP_ID_0_S) +#define IG3_GPV_COMP_ID_1 0x44E01FF4 +#define IG3_GPV_COMP_ID_1_RSVD0_S 8 +#define IG3_GPV_COMP_ID_1_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_COMP_ID_1_RSVD0_S) +#define IG3_GPV_COMP_ID_1_COMP_ID_1_S 0 +#define IG3_GPV_COMP_ID_1_COMP_ID_1_M RDMA_MASK3(32, 0xFF, IG3_GPV_COMP_ID_1_COMP_ID_1_S) +#define IG3_GPV_COMP_ID_2 0x44E01FF8 +#define IG3_GPV_COMP_ID_2_RSVD0_S 8 +#define IG3_GPV_COMP_ID_2_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_COMP_ID_2_RSVD0_S) +#define IG3_GPV_COMP_ID_2_COMP_ID_2_S 0 +#define IG3_GPV_COMP_ID_2_COMP_ID_2_M RDMA_MASK3(32, 0xFF, IG3_GPV_COMP_ID_2_COMP_ID_2_S) +#define IG3_GPV_COMP_ID_3 0x44E01FFC +#define IG3_GPV_COMP_ID_3_RSVD0_S 8 +#define IG3_GPV_COMP_ID_3_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_COMP_ID_3_RSVD0_S) +#define IG3_GPV_COMP_ID_3_COMP_ID_3_S 0 +#define IG3_GPV_COMP_ID_3_COMP_ID_3_M RDMA_MASK3(32, 0xFF, IG3_GPV_COMP_ID_3_COMP_ID_3_S) +#define IG3_GPV_CQP_SLV_FN_MOD 0x44E43108 +#define IG3_GPV_CQP_SLV_FN_MOD_RSVD0_S 2 +#define IG3_GPV_CQP_SLV_FN_MOD_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_GPV_CQP_SLV_FN_MOD_RSVD0_S) +#define IG3_GPV_CQP_SLV_FN_MOD_FN_MOD_S 0 +#define IG3_GPV_CQP_SLV_FN_MOD_FN_MOD_M RDMA_MASK3(32, 0x3, IG3_GPV_CQP_SLV_FN_MOD_FN_MOD_S) +#define IG3_GPV_CQP_SLV_FN_MOD_AHB 0x44E43028 +#define IG3_GPV_CQP_SLV_FN_MOD_AHB_RSVD0_S 2 +#define IG3_GPV_CQP_SLV_FN_MOD_AHB_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_GPV_CQP_SLV_FN_MOD_AHB_RSVD0_S) +#define IG3_GPV_CQP_SLV_FN_MOD_AHB_WR_INC_OVERRIDE_S 1 +#define IG3_GPV_CQP_SLV_FN_MOD_AHB_WR_INC_OVERRIDE_M RDMA_BIT2(32, IG3_GPV_CQP_SLV_FN_MOD_AHB_WR_INC_OVERRIDE_S) +#define IG3_GPV_CQP_SLV_FN_MOD_AHB_RD_INC_OVERRIDE_S 0 +#define IG3_GPV_CQP_SLV_FN_MOD_AHB_RD_INC_OVERRIDE_M RDMA_BIT2(32, IG3_GPV_CQP_SLV_FN_MOD_AHB_RD_INC_OVERRIDE_S) +#define IG3_GPV_NSS_MSTR_FN_MOD_ISS_BM 0x44E02008 +#define IG3_GPV_NSS_MSTR_FN_MOD_ISS_BM_RSVD0_S 2 +#define IG3_GPV_NSS_MSTR_FN_MOD_ISS_BM_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_GPV_NSS_MSTR_FN_MOD_ISS_BM_RSVD0_S) +#define IG3_GPV_NSS_MSTR_FN_MOD_ISS_BM_FN_MOD_ISS_BM_S 0 +#define IG3_GPV_NSS_MSTR_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M RDMA_MASK3(32, 0x3, IG3_GPV_NSS_MSTR_FN_MOD_ISS_BM_FN_MOD_ISS_BM_S) +#define IG3_GPV_NSS_MSTR_SECURITY 0x44E0000C +#define IG3_GPV_NSS_MSTR_SECURITY_RSVD0_S 16 +#define IG3_GPV_NSS_MSTR_SECURITY_RSVD0_M RDMA_MASK3(32, 0xFFFF, IG3_GPV_NSS_MSTR_SECURITY_RSVD0_S) +#define IG3_GPV_NSS_MSTR_SECURITY_SECURITY1_S 0 +#define IG3_GPV_NSS_MSTR_SECURITY_SECURITY1_M RDMA_MASK3(32, 0xFFFF, IG3_GPV_NSS_MSTR_SECURITY_SECURITY1_S) +#define IG3_GPV_NSS_SLV_FN_MOD 0x44E42108 +#define IG3_GPV_NSS_SLV_FN_MOD_RSVD0_S 2 +#define IG3_GPV_NSS_SLV_FN_MOD_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_GPV_NSS_SLV_FN_MOD_RSVD0_S) +#define IG3_GPV_NSS_SLV_FN_MOD_FN_MOD_S 0 +#define IG3_GPV_NSS_SLV_FN_MOD_FN_MOD_M RDMA_MASK3(32, 0x3, IG3_GPV_NSS_SLV_FN_MOD_FN_MOD_S) +#define IG3_GPV_OOP_SLV_FN_MOD 0x44E45108 +#define IG3_GPV_OOP_SLV_FN_MOD_RSVD0_S 2 +#define IG3_GPV_OOP_SLV_FN_MOD_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_GPV_OOP_SLV_FN_MOD_RSVD0_S) +#define IG3_GPV_OOP_SLV_FN_MOD_FN_MOD_S 0 +#define IG3_GPV_OOP_SLV_FN_MOD_FN_MOD_M RDMA_MASK3(32, 0x3, IG3_GPV_OOP_SLV_FN_MOD_FN_MOD_S) +#define IG3_GPV_OOP_SLV_FN_MOD_AHB 0x44E45028 +#define IG3_GPV_OOP_SLV_FN_MOD_AHB_RSVD0_S 2 +#define IG3_GPV_OOP_SLV_FN_MOD_AHB_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_GPV_OOP_SLV_FN_MOD_AHB_RSVD0_S) +#define IG3_GPV_OOP_SLV_FN_MOD_AHB_WR_INC_OVERRIDE_S 1 +#define IG3_GPV_OOP_SLV_FN_MOD_AHB_WR_INC_OVERRIDE_M RDMA_BIT2(32, IG3_GPV_OOP_SLV_FN_MOD_AHB_WR_INC_OVERRIDE_S) +#define IG3_GPV_OOP_SLV_FN_MOD_AHB_RD_INC_OVERRIDE_S 0 +#define IG3_GPV_OOP_SLV_FN_MOD_AHB_RD_INC_OVERRIDE_M RDMA_BIT2(32, IG3_GPV_OOP_SLV_FN_MOD_AHB_RD_INC_OVERRIDE_S) +#define IG3_GPV_PEIP_IB_FN_MOD2 0x44E03024 +#define IG3_GPV_PEIP_IB_FN_MOD2_RSVD0_S 1 +#define IG3_GPV_PEIP_IB_FN_MOD2_RSVD0_M RDMA_MASK3(32, 0x7FFFFFFF, IG3_GPV_PEIP_IB_FN_MOD2_RSVD0_S) +#define IG3_GPV_PEIP_IB_FN_MOD2_BYPASS_MERGE_S 0 +#define IG3_GPV_PEIP_IB_FN_MOD2_BYPASS_MERGE_M RDMA_BIT2(32, IG3_GPV_PEIP_IB_FN_MOD2_BYPASS_MERGE_S) +#define IG3_GPV_PEIP_IB_FN_MOD_ISS_BM 0x44E03008 +#define IG3_GPV_PEIP_IB_FN_MOD_ISS_BM_RSVD0_S 2 +#define IG3_GPV_PEIP_IB_FN_MOD_ISS_BM_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_GPV_PEIP_IB_FN_MOD_ISS_BM_RSVD0_S) +#define IG3_GPV_PEIP_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_S 0 +#define IG3_GPV_PEIP_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_M RDMA_MASK3(32, 0x3, IG3_GPV_PEIP_IB_FN_MOD_ISS_BM_FN_MOD_ISS_BM_S) +#define IG3_GPV_PERIPH_ID_0 0x44E01FE0 +#define IG3_GPV_PERIPH_ID_0_RSVD0_S 8 +#define IG3_GPV_PERIPH_ID_0_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_PERIPH_ID_0_RSVD0_S) +#define IG3_GPV_PERIPH_ID_0_PERIPH_ID_0_S 0 +#define IG3_GPV_PERIPH_ID_0_PERIPH_ID_0_M RDMA_MASK3(32, 0xFF, IG3_GPV_PERIPH_ID_0_PERIPH_ID_0_S) +#define IG3_GPV_PERIPH_ID_1 0x44E01FE4 +#define IG3_GPV_PERIPH_ID_1_RSVD0_S 8 +#define IG3_GPV_PERIPH_ID_1_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_PERIPH_ID_1_RSVD0_S) +#define IG3_GPV_PERIPH_ID_1_PERIPH_ID_1_S 0 +#define IG3_GPV_PERIPH_ID_1_PERIPH_ID_1_M RDMA_MASK3(32, 0xFF, IG3_GPV_PERIPH_ID_1_PERIPH_ID_1_S) +#define IG3_GPV_PERIPH_ID_2 0x44E01FE8 +#define IG3_GPV_PERIPH_ID_2_RSVD0_S 8 +#define IG3_GPV_PERIPH_ID_2_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_PERIPH_ID_2_RSVD0_S) +#define IG3_GPV_PERIPH_ID_2_PERIPH_ID_2_S 0 +#define IG3_GPV_PERIPH_ID_2_PERIPH_ID_2_M RDMA_MASK3(32, 0xFF, IG3_GPV_PERIPH_ID_2_PERIPH_ID_2_S) +#define IG3_GPV_PERIPH_ID_3 0x44E01FEC +#define IG3_GPV_PERIPH_ID_3_RSVD0_S 8 +#define IG3_GPV_PERIPH_ID_3_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_PERIPH_ID_3_RSVD0_S) +#define IG3_GPV_PERIPH_ID_3_REV_AND_S 4 +#define IG3_GPV_PERIPH_ID_3_REV_AND_M RDMA_MASK3(32, 0xF, IG3_GPV_PERIPH_ID_3_REV_AND_S) +#define IG3_GPV_PERIPH_ID_3_CUST_MOD_NUM_S 0 +#define IG3_GPV_PERIPH_ID_3_CUST_MOD_NUM_M RDMA_MASK3(32, 0xF, IG3_GPV_PERIPH_ID_3_CUST_MOD_NUM_S) +#define IG3_GPV_PERIPH_ID_4 0x44E01FD0 +#define IG3_GPV_PERIPH_ID_4_RSVD0_S 8 +#define IG3_GPV_PERIPH_ID_4_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_PERIPH_ID_4_RSVD0_S) +#define IG3_GPV_PERIPH_ID_4_PERIPH_ID_4_S 0 +#define IG3_GPV_PERIPH_ID_4_PERIPH_ID_4_M RDMA_MASK3(32, 0xFF, IG3_GPV_PERIPH_ID_4_PERIPH_ID_4_S) +#define IG3_GPV_PERIPH_ID_5 0x44E01FD4 +#define IG3_GPV_PERIPH_ID_5_RSVD0_S 8 +#define IG3_GPV_PERIPH_ID_5_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_PERIPH_ID_5_RSVD0_S) +#define IG3_GPV_PERIPH_ID_5_PERIPH_ID_5_S 0 +#define IG3_GPV_PERIPH_ID_5_PERIPH_ID_5_M RDMA_MASK3(32, 0xFF, IG3_GPV_PERIPH_ID_5_PERIPH_ID_5_S) +#define IG3_GPV_PERIPH_ID_6 0x44E01FD8 +#define IG3_GPV_PERIPH_ID_6_RSVD0_S 8 +#define IG3_GPV_PERIPH_ID_6_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_PERIPH_ID_6_RSVD0_S) +#define IG3_GPV_PERIPH_ID_6_PERIPH_ID_6_S 0 +#define IG3_GPV_PERIPH_ID_6_PERIPH_ID_6_M RDMA_MASK3(32, 0xFF, IG3_GPV_PERIPH_ID_6_PERIPH_ID_6_S) +#define IG3_GPV_PERIPH_ID_7 0x44E01FDC +#define IG3_GPV_PERIPH_ID_7_RSVD0_S 8 +#define IG3_GPV_PERIPH_ID_7_RSVD0_M RDMA_MASK3(32, 0xFFFFFF, IG3_GPV_PERIPH_ID_7_RSVD0_S) +#define IG3_GPV_PERIPH_ID_7_PERIPH_ID_7_S 0 +#define IG3_GPV_PERIPH_ID_7_PERIPH_ID_7_M RDMA_MASK3(32, 0xFF, IG3_GPV_PERIPH_ID_7_PERIPH_ID_7_S) +#define IG3_GPV_TEP_SLV_FN_MOD 0x44E44108 +#define IG3_GPV_TEP_SLV_FN_MOD_RSVD0_S 2 +#define IG3_GPV_TEP_SLV_FN_MOD_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_GPV_TEP_SLV_FN_MOD_RSVD0_S) +#define IG3_GPV_TEP_SLV_FN_MOD_FN_MOD_S 0 +#define IG3_GPV_TEP_SLV_FN_MOD_FN_MOD_M RDMA_MASK3(32, 0x3, IG3_GPV_TEP_SLV_FN_MOD_FN_MOD_S) +#define IG3_GPV_TEP_SLV_FN_MOD_AHB 0x44E44028 +#define IG3_GPV_TEP_SLV_FN_MOD_AHB_RSVD0_S 2 +#define IG3_GPV_TEP_SLV_FN_MOD_AHB_RSVD0_M RDMA_MASK3(32, 0x3FFFFFFF, IG3_GPV_TEP_SLV_FN_MOD_AHB_RSVD0_S) +#define IG3_GPV_TEP_SLV_FN_MOD_AHB_WR_INC_OVERRIDE_S 1 +#define IG3_GPV_TEP_SLV_FN_MOD_AHB_WR_INC_OVERRIDE_M RDMA_BIT2(32, IG3_GPV_TEP_SLV_FN_MOD_AHB_WR_INC_OVERRIDE_S) +#define IG3_GPV_TEP_SLV_FN_MOD_AHB_RD_INC_OVERRIDE_S 0 +#define IG3_GPV_TEP_SLV_FN_MOD_AHB_RD_INC_OVERRIDE_M RDMA_BIT2(32, IG3_GPV_TEP_SLV_FN_MOD_AHB_RD_INC_OVERRIDE_S) + +#define IG3_VFINT_DYN_CTLN_0 0x00003800 /* from CPK */ +#define IG3_VF_DB_ADDR_OFFSET (64 * 1024) /* from CPK */ + +#define IG3_DB_ADDR_OFFSET (192 * 1024 * 1024) +#define IG3_GLPCI_LBARCTRL 0x0009DE74 /* from CPK */ + +#define IG3_GLINT_BASE 0x08900000 +#define IG3_GLINT_DYN_CTL(_INT) (IG3_GLINT_BASE + ((_INT) * 0x1000)) +#define IG3_GLINT_DYN_CTL_INTENA_S 0 +#define IG3_GLINT_DYN_CTL_INTENA_M BIT(IG3_GLINT_DYN_CTL_INTENA_S) +#define IG3_GLINT_DYN_CTL_CLEARPBA_S 1 +#define IG3_GLINT_DYN_CTL_CLEARPBA_M BIT(IG3_GLINT_DYN_CTL_CLEARPBA_S) +#define IG3_GLINT_DYN_CTL_SWINT_TRIG_S 2 +#define IG3_GLINT_DYN_CTL_SWINT_TRIG_M BIT(IG3_GLINT_DYN_CTL_SWINT_TRIG_S) +#define IG3_GLINT_DYN_CTL_ITR_INDX_S 3 +#define IG3_GLINT_DYN_CTL_INTERVAL_S 5 +#define IG3_GLINT_DYN_CTL_INTERVAL_M BIT(IG3_GLINT_DYN_CTL_INTERVAL_S) +#define IG3_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S 24 +#define IG3_GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(IG3_GLINT_DYN_CTL_SW_ITR_INDX_ENA_S) +#define IG3_GLINT_DYN_CTL_SW_ITR_INDX_S 25 +#define IG3_GLINT_DYN_CTL_SW_ITR_INDX_M BIT(IG3_GLINT_DYN_CTL_SW_ITR_INDX_S) +#define IG3_GLINT_DYN_CTL_INTENA_MSK_S 31 +#define IG3_GLINT_DYN_CTL_INTENA_MSK_M BIT(IG3_GLINT_DYN_CTL_INTENA_MSK_S) +#define IG3_GLINT_ITR(_i, _INT) (IG3_GLINT_BASE + (((_INT)+(((_i)+1) * 4)) * 0x1000)) + +#endif /* IG3RDMA_REGS_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs_apf.h b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs_apf.h new file mode 100644 index 000000000..cacd8a21b --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs_apf.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2018 - 2023 Intel Corporation */ + +#ifndef IG3RDMA_REGS_APF_H +#define IG3RDMA_REGS_APF_H + +#include "irdma.h" + +#define IG3_APF_CCQPEXTSTATUS 0xBC00004 +#define IG3_APF_CCQPEXTSTATUS_RSVD_S 16 +#define IG3_APF_CCQPEXTSTATUS_RSVD_M \ + RDMA_MASK3(32, 0xFFFF, IG3_APF_CCQPEXTSTATUS_RSVD_S) +#define IG3_APF_CCQPEXTSTATUS_DBPT_INDEX_S 0 +#define IG3_APF_CCQPEXTSTATUS_DBPT_INDEX_M \ + RDMA_MASK3(32, 0xFFFF, IG3_APF_CCQPEXTSTATUS_DBPT_INDEX_S) +#define IG3_APF_CCQPHIGH 0xBC0000C +#define IG3_APF_CCQPHIGH_PECCQPHIGH_S 0 +#define IG3_APF_CCQPHIGH_PECCQPHIGH_M \ + RDMA_MASK3(32, 0xFFFFFFFF, IG3_APF_CCQPHIGH_PECCQPHIGH_S) +#define IG3_APF_CCQPLOW 0xBC00008 +#define IG3_APF_CCQPLOW_PECCQPLOW_S 0 +#define IG3_APF_CCQPLOW_PECCQPLOW_M \ + RDMA_MASK3(32, 0xFFFFFFFF, IG3_APF_CCQPLOW_PECCQPLOW_S) +#define IG3_APF_CCQPSTATUS 0xBC00000 +#define IG3_APF_CCQPSTATUS_CCQP_ERR_S 31 +#define IG3_APF_CCQPSTATUS_CCQP_ERR_M \ + RDMA_BIT2(32, IG3_APF_CCQPSTATUS_CCQP_ERR_S) +#define IG3_APF_CCQPSTATUS_RSVD2_S 28 +#define IG3_APF_CCQPSTATUS_RSVD2_M \ + RDMA_MASK3(32, 0x7, IG3_APF_CCQPSTATUS_RSVD2_S) +#define IG3_APF_CCQPSTATUS_RDMA_EN_VFS_S 16 +#define IG3_APF_CCQPSTATUS_RDMA_EN_VFS_M \ + RDMA_MASK3(32, 0xFFF, IG3_APF_CCQPSTATUS_RDMA_EN_VFS_S) +#define IG3_APF_CCQPSTATUS_RSVD1_S 7 +#define IG3_APF_CCQPSTATUS_RSVD1_M \ + RDMA_MASK3(32, 0x1FF, IG3_APF_CCQPSTATUS_RSVD1_S) +#define IG3_APF_CCQPSTATUS_HMC_PROFILE_S 4 +#define IG3_APF_CCQPSTATUS_HMC_PROFILE_M \ + RDMA_MASK3(32, 0x7, IG3_APF_CCQPSTATUS_HMC_PROFILE_S) +#define IG3_APF_CCQPSTATUS_RSVD0_S 1 +#define IG3_APF_CCQPSTATUS_RSVD0_M \ + RDMA_MASK3(32, 0x7, IG3_APF_CCQPSTATUS_RSVD0_S) +#define IG3_APF_CCQPSTATUS_CCQP_DONE_S 0 +#define IG3_APF_CCQPSTATUS_CCQP_DONE_M \ + RDMA_BIT2(32, IG3_APF_CCQPSTATUS_CCQP_DONE_S) +#define IG3_APF_CQPDB 0xBC00014 +#define IG3_APF_CQPDB_RSVD_S 11 +#define IG3_APF_CQPDB_RSVD_M RDMA_MASK3(32, 0x1FFFFF, IG3_APF_CQPDB_RSVD_S) +#define IG3_APF_CQPDB_WQHEAD_S 0 +#define IG3_APF_CQPDB_WQHEAD_M RDMA_MASK3(32, 0x7FF, IG3_APF_CQPDB_WQHEAD_S) +#define IG3_APF_CQPERRCODES 0xBC00010 +#define IG3_APF_CQPERRCODES_CQP_MAJOR_CODE_S 16 +#define IG3_APF_CQPERRCODES_CQP_MAJOR_CODE_M \ + RDMA_MASK3(32, 0xFFFF, IG3_APF_CQPERRCODES_CQP_MAJOR_CODE_S) +#define IG3_APF_CQPERRCODES_CQP_MINOR_CODE_S 0 +#define IG3_APF_CQPERRCODES_CQP_MINOR_CODE_M \ + RDMA_MASK3(32, 0xFFFF, IG3_APF_CQPERRCODES_CQP_MINOR_CODE_S) +#define IG3_APF_CQPTAIL 0xBC00018 +#define IG3_APF_CQPTAIL_CQP_OP_ERR_S 31 +#define IG3_APF_CQPTAIL_CQP_OP_ERR_M RDMA_BIT2(32, IG3_APF_CQPTAIL_CQP_OP_ERR_S) +#define IG3_APF_CQPTAIL_RSVD_S 11 +#define IG3_APF_CQPTAIL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_APF_CQPTAIL_RSVD_S) +#define IG3_APF_CQPTAIL_WQTAIL_S 0 +#define IG3_APF_CQPTAIL_WQTAIL_M RDMA_MASK3(32, 0x7FF, IG3_APF_CQPTAIL_WQTAIL_S) +#define IG3_APF_IPCONFIG0 0xBC00020 +#define IG3_APF_IPCONFIG0_RSVD_S 18 +#define IG3_APF_IPCONFIG0_RSVD_M \ + RDMA_MASK3(32, 0x3FFF, IG3_APF_IPCONFIG0_RSVD_S) +#define IG3_APF_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17 +#define IG3_APF_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M \ + RDMA_BIT2(32, IG3_APF_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S) +#define IG3_APF_IPCONFIG0_USEENTIREIDRANGE_S 16 +#define IG3_APF_IPCONFIG0_USEENTIREIDRANGE_M \ + RDMA_BIT2(32, IG3_APF_IPCONFIG0_USEENTIREIDRANGE_S) +#define IG3_APF_IPCONFIG0_PEIPID_S 0 +#define IG3_APF_IPCONFIG0_PEIPID_M \ + RDMA_MASK3(32, 0xFFFF, IG3_APF_IPCONFIG0_PEIPID_S) +#define IG3_APF_TCPNOWTIMER 0xBC0001C +#define IG3_APF_TCPNOWTIMER_TCP_NOW_S 0 +#define IG3_APF_TCPNOWTIMER_TCP_NOW_M \ + RDMA_MASK3(32, 0xFFFFFFFF, IG3_APF_TCPNOWTIMER_TCP_NOW_S) +#define IG3_APF_DBL_AEQALLOC 0xC0000C0 +#define IG3_APF_DBL_AEQALLOC_AECOUNT_S 0 +#define IG3_APF_DBL_AEQALLOC_AECOUNT_M \ + RDMA_MASK3(32, 0xFFFFFFFF, IG3_APF_DBL_AEQALLOC_AECOUNT_S) +#define IG3_APF_DBL_AEQITRMASK 0xC000C00 +#define IG3_APF_DBL_AEQITRMASK_RESERVED_S 1 +#define IG3_APF_DBL_AEQITRMASK_RESERVED_M \ + RDMA_MASK3(32, 0x7FFFFFFF, IG3_APF_DBL_AEQITRMASK_RESERVED_S) +#define IG3_APF_DBL_AEQITRMASK_AEQ_ITR_MASK_S 0 +#define IG3_APF_DBL_AEQITRMASK_AEQ_ITR_MASK_M \ + RDMA_BIT2(32, IG3_APF_DBL_AEQITRMASK_AEQ_ITR_MASK_S) +#define IG3_APF_DBL_CEQITRMASK 0xC000800 +#define IG3_APF_DBL_CEQITRMASK_CEQ_ITR_MASK_S 31 +#define IG3_APF_DBL_CEQITRMASK_CEQ_ITR_MASK_M \ + RDMA_BIT2(32, IG3_APF_DBL_CEQITRMASK_CEQ_ITR_MASK_S) +#define IG3_APF_DBL_CEQITRMASK_RESERVED2_S 12 +#define IG3_APF_DBL_CEQITRMASK_RESERVED2_M \ + RDMA_MASK3(32, 0x7FFFF, IG3_APF_DBL_CEQITRMASK_RESERVED2_S) +#define IG3_APF_DBL_CEQITRMASK_CEQINDEX_S 0 +#define IG3_APF_DBL_CEQITRMASK_CEQINDEX_M \ + RDMA_MASK3(32, 0xFFF, IG3_APF_DBL_CEQITRMASK_CEQINDEX_S) +#define IG3_APF_DBL_CQACK 0xC000400 +#define IG3_APF_DBL_CQACK_RSVD_S 25 +#define IG3_APF_DBL_CQACK_RSVD_M RDMA_MASK3(32, 0x7F, IG3_APF_DBL_CQACK_RSVD_S) +#define IG3_APF_DBL_CQACK_PECQID_S 0 +#define IG3_APF_DBL_CQACK_PECQID_M \ + RDMA_MASK3(32, 0x1FFFFFF, IG3_APF_DBL_CQACK_PECQID_S) +#define IG3_APF_DBL_CQARM 0xC000040 +#define IG3_APF_DBL_CQARM_RSVD_S 25 +#define IG3_APF_DBL_CQARM_RSVD_M RDMA_MASK3(32, 0x7F, IG3_APF_DBL_CQARM_RSVD_S) +#define IG3_APF_DBL_CQARM_PECQID_S 0 +#define IG3_APF_DBL_CQARM_PECQID_M \ + RDMA_MASK3(32, 0x1FFFFFF, IG3_APF_DBL_CQARM_PECQID_S) +#define IG3_APF_DBL_CQPDB 0xC000100 +#define IG3_APF_DBL_CQPDB_RSVD_S 11 +#define IG3_APF_DBL_CQPDB_RSVD_M \ + RDMA_MASK3(32, 0x1FFFFF, IG3_APF_DBL_CQPDB_RSVD_S) +#define IG3_APF_DBL_CQPDB_CQPHEAD_S 0 +#define IG3_APF_DBL_CQPDB_CQPHEAD_M \ + RDMA_MASK3(32, 0x7FF, IG3_APF_DBL_CQPDB_CQPHEAD_S) +#define IG3_APF_DBL_WQEALLOC 0xC000000 +#define IG3_APF_DBL_WQEALLOC_WQE_DESC_INDEX_S 20 +#define IG3_APF_DBL_WQEALLOC_WQE_DESC_INDEX_M \ + RDMA_MASK3(32, 0xFFF, IG3_APF_DBL_WQEALLOC_WQE_DESC_INDEX_S) +#define IG3_APF_DBL_WQEALLOC_PEQPID_S 0 +#define IG3_APF_DBL_WQEALLOC_PEQPID_M \ + RDMA_MASK3(32, 0xFFFFF, IG3_APF_DBL_WQEALLOC_PEQPID_S) + +#endif /* IG3RDMA_REGS_APF_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs_avf.h b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs_avf.h new file mode 100644 index 000000000..bd816ed0f --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ig3rdma_regs_avf.h @@ -0,0 +1,130 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2019 - 2023 Intel Corporation */ + +#ifndef IG3RDMA_REGS_AVF_H +#define IG3RDMA_REGS_AVF_H + +#include "irdma.h" + +#define IG3_AVF_CCQPEXTSTATUS 0x8C04 +#define IG3_AVF_CCQPEXTSTATUS_RSVD_S 16 +#define IG3_AVF_CCQPEXTSTATUS_RSVD_M \ + RDMA_MASK3(32, 0xFFFF, IG3_AVF_CCQPEXTSTATUS_RSVD_S) +#define IG3_AVF_CCQPEXTSTATUS_DBPT_INDEX_S 0 +#define IG3_AVF_CCQPEXTSTATUS_DBPT_INDEX_M \ + RDMA_MASK3(32, 0xFFFF, IG3_AVF_CCQPEXTSTATUS_DBPT_INDEX_S) +#define IG3_AVF_CCQPHIGH 0x8C0C +#define IG3_AVF_CCQPHIGH_PECCQPHIGH_S 0 +#define IG3_AVF_CCQPHIGH_PECCQPHIGH_M \ + RDMA_MASK3(32, 0xFFFFFFFF, IG3_AVF_CCQPHIGH_PECCQPHIGH_S) +#define IG3_AVF_CCQPLOW 0x8C08 +#define IG3_AVF_CCQPLOW_PECCQPLOW_S 0 +#define IG3_AVF_CCQPLOW_PECCQPLOW_M \ + RDMA_MASK3(32, 0xFFFFFFFF, IG3_AVF_CCQPLOW_PECCQPLOW_S) +#define IG3_AVF_CCQPSTATUS 0x8C00 +#define IG3_AVF_CCQPSTATUS_CCQP_ERR_S 31 +#define IG3_AVF_CCQPSTATUS_CCQP_ERR_M \ + RDMA_BIT2(32, IG3_AVF_CCQPSTATUS_CCQP_ERR_S) +#define IG3_AVF_CCQPSTATUS_RSVD2_S 28 +#define IG3_AVF_CCQPSTATUS_RSVD2_M \ + RDMA_MASK3(32, 0x7, IG3_AVF_CCQPSTATUS_RSVD2_S) +#define IG3_AVF_CCQPSTATUS_RDMA_EN_VFS_S 16 +#define IG3_AVF_CCQPSTATUS_RDMA_EN_VFS_M \ + RDMA_MASK3(32, 0xFFF, IG3_AVF_CCQPSTATUS_RDMA_EN_VFS_S) +#define IG3_AVF_CCQPSTATUS_RSVD1_S 7 +#define IG3_AVF_CCQPSTATUS_RSVD1_M \ + RDMA_MASK3(32, 0x1FF, IG3_AVF_CCQPSTATUS_RSVD1_S) +#define IG3_AVF_CCQPSTATUS_HMC_PROFILE_S 4 +#define IG3_AVF_CCQPSTATUS_HMC_PROFILE_M \ + RDMA_MASK3(32, 0x7, IG3_AVF_CCQPSTATUS_HMC_PROFILE_S) +#define IG3_AVF_CCQPSTATUS_RSVD0_S 1 +#define IG3_AVF_CCQPSTATUS_RSVD0_M \ + RDMA_MASK3(32, 0x7, IG3_AVF_CCQPSTATUS_RSVD0_S) +#define IG3_AVF_CCQPSTATUS_CCQP_DONE_S 0 +#define IG3_AVF_CCQPSTATUS_CCQP_DONE_M \ + RDMA_BIT2(32, IG3_AVF_CCQPSTATUS_CCQP_DONE_S) +#define IG3_AVF_CQPDB 0x8C14 +#define IG3_AVF_CQPDB_RSVD_S 11 +#define IG3_AVF_CQPDB_RSVD_M RDMA_MASK3(32, 0x1FFFFF, IG3_AVF_CQPDB_RSVD_S) +#define IG3_AVF_CQPDB_WQHEAD_S 0 +#define IG3_AVF_CQPDB_WQHEAD_M RDMA_MASK3(32, 0x7FF, IG3_AVF_CQPDB_WQHEAD_S) +#define IG3_AVF_CQPERRCODES 0x8C10 +#define IG3_AVF_CQPERRCODES_CQP_MAJOR_CODE_S 16 +#define IG3_AVF_CQPERRCODES_CQP_MAJOR_CODE_M \ + RDMA_MASK3(32, 0xFFFF, IG3_AVF_CQPERRCODES_CQP_MAJOR_CODE_S) +#define IG3_AVF_CQPERRCODES_CQP_MINOR_CODE_S 0 +#define IG3_AVF_CQPERRCODES_CQP_MINOR_CODE_M \ + RDMA_MASK3(32, 0xFFFF, IG3_AVF_CQPERRCODES_CQP_MINOR_CODE_S) +#define IG3_AVF_CQPTAIL 0x8C18 +#define IG3_AVF_CQPTAIL_CQP_OP_ERR_S 31 +#define IG3_AVF_CQPTAIL_CQP_OP_ERR_M RDMA_BIT2(32, IG3_AVF_CQPTAIL_CQP_OP_ERR_S) +#define IG3_AVF_CQPTAIL_RSVD_S 11 +#define IG3_AVF_CQPTAIL_RSVD_M RDMA_MASK3(32, 0xFFFFF, IG3_AVF_CQPTAIL_RSVD_S) +#define IG3_AVF_CQPTAIL_WQTAIL_S 0 +#define IG3_AVF_CQPTAIL_WQTAIL_M RDMA_MASK3(32, 0x7FF, IG3_AVF_CQPTAIL_WQTAIL_S) +#define IG3_AVF_IPCONFIG0 0x8C20 +#define IG3_AVF_IPCONFIG0_RSVD_S 18 +#define IG3_AVF_IPCONFIG0_RSVD_M \ + RDMA_MASK3(32, 0x3FFF, IG3_AVF_IPCONFIG0_RSVD_S) +#define IG3_AVF_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S 17 +#define IG3_AVF_IPCONFIG0_UDP_SRC_PORT_MASK_EN_M \ + RDMA_BIT2(32, IG3_AVF_IPCONFIG0_UDP_SRC_PORT_MASK_EN_S) +#define IG3_AVF_IPCONFIG0_USEENTIREIDRANGE_S 16 +#define IG3_AVF_IPCONFIG0_USEENTIREIDRANGE_M \ + RDMA_BIT2(32, IG3_AVF_IPCONFIG0_USEENTIREIDRANGE_S) +#define IG3_AVF_IPCONFIG0_PEIPID_S 0 +#define IG3_AVF_IPCONFIG0_PEIPID_M \ + RDMA_MASK3(32, 0xFFFF, IG3_AVF_IPCONFIG0_PEIPID_S) +#define IG3_AVF_TCPNOWTIMER 0x8C1C +#define IG3_AVF_TCPNOWTIMER_TCP_NOW_S 0 +#define IG3_AVF_TCPNOWTIMER_TCP_NOW_M \ + RDMA_MASK3(32, 0xFFFFFFFF, IG3_AVF_TCPNOWTIMER_TCP_NOW_S) +#define IG3_AVF_DBL_AEQALLOC 0x100C0 +#define IG3_AVF_DBL_AEQALLOC_AECOUNT_S 0 +#define IG3_AVF_DBL_AEQALLOC_AECOUNT_M \ + RDMA_MASK3(32, 0xFFFFFFFF, IG3_AVF_DBL_AEQALLOC_AECOUNT_S) +#define IG3_AVF_DBL_AEQITRMASK 0x10C00 +#define IG3_AVF_DBL_AEQITRMASK_RESERVED_S 1 +#define IG3_AVF_DBL_AEQITRMASK_RESERVED_M \ + RDMA_MASK3(32, 0x7FFFFFFF, IG3_AVF_DBL_AEQITRMASK_RESERVED_S) +#define IG3_AVF_DBL_AEQITRMASK_AEQ_ITR_MASK_S 0 +#define IG3_AVF_DBL_AEQITRMASK_AEQ_ITR_MASK_M \ + RDMA_BIT2(32, IG3_AVF_DBL_AEQITRMASK_AEQ_ITR_MASK_S) +#define IG3_AVF_DBL_CEQITRMASK 0x10800 +#define IG3_AVF_DBL_CEQITRMASK_CEQ_ITR_MASK_S 31 +#define IG3_AVF_DBL_CEQITRMASK_CEQ_ITR_MASK_M \ + RDMA_BIT2(32, IG3_AVF_DBL_CEQITRMASK_CEQ_ITR_MASK_S) +#define IG3_AVF_DBL_CEQITRMASK_RESERVED2_S 12 +#define IG3_AVF_DBL_CEQITRMASK_RESERVED2_M \ + RDMA_MASK3(32, 0x7FFFF, IG3_AVF_DBL_CEQITRMASK_RESERVED2_S) +#define IG3_AVF_DBL_CEQITRMASK_CEQINDEX_S 0 +#define IG3_AVF_DBL_CEQITRMASK_CEQINDEX_M \ + RDMA_MASK3(32, 0xFFF, IG3_AVF_DBL_CEQITRMASK_CEQINDEX_S) +#define IG3_AVF_DBL_CQACK 0x10400 +#define IG3_AVF_DBL_CQACK_RSVD_S 25 +#define IG3_AVF_DBL_CQACK_RSVD_M RDMA_MASK3(32, 0x7F, IG3_AVF_DBL_CQACK_RSVD_S) +#define IG3_AVF_DBL_CQACK_PECQID_S 0 +#define IG3_AVF_DBL_CQACK_PECQID_M \ + RDMA_MASK3(32, 0x1FFFFFF, IG3_AVF_DBL_CQACK_PECQID_S) +#define IG3_AVF_DBL_CQARM 0x10040 +#define IG3_AVF_DBL_CQARM_RSVD_S 25 +#define IG3_AVF_DBL_CQARM_RSVD_M RDMA_MASK3(32, 0x7F, IG3_AVF_DBL_CQARM_RSVD_S) +#define IG3_AVF_DBL_CQARM_PECQID_S 0 +#define IG3_AVF_DBL_CQARM_PECQID_M \ + RDMA_MASK3(32, 0x1FFFFFF, IG3_AVF_DBL_CQARM_PECQID_S) +#define IG3_AVF_DBL_CQPDB 0x10100 +#define IG3_AVF_DBL_CQPDB_RSVD_S 11 +#define IG3_AVF_DBL_CQPDB_RSVD_M \ + RDMA_MASK3(32, 0x1FFFFF, IG3_AVF_DBL_CQPDB_RSVD_S) +#define IG3_AVF_DBL_CQPDB_CQPHEAD_S 0 +#define IG3_AVF_DBL_CQPDB_CQPHEAD_M \ + RDMA_MASK3(32, 0x7FF, IG3_AVF_DBL_CQPDB_CQPHEAD_S) +#define IG3_AVF_DBL_WQEALLOC 0x10000 +#define IG3_AVF_DBL_WQEALLOC_WQE_DESC_INDEX_S 20 +#define IG3_AVF_DBL_WQEALLOC_WQE_DESC_INDEX_M \ + RDMA_MASK3(32, 0xFFF, IG3_AVF_DBL_WQEALLOC_WQE_DESC_INDEX_S) +#define IG3_AVF_DBL_WQEALLOC_PEQPID_S 0 +#define IG3_AVF_DBL_WQEALLOC_PEQPID_M \ + RDMA_MASK3(32, 0xFFFFF, IG3_AVF_DBL_WQEALLOC_PEQPID_S) + +#endif /* IG3RDMA_REGS_AVF_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/iidc.h b/drivers/intel/irdma-1.14.33/src/irdma/iidc.h new file mode 100644 index 000000000..98d4c2a05 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/iidc.h @@ -0,0 +1,300 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB-only */ +/* Copyright (C) 2018-2024 Intel Corporation */ + +#ifndef _IIDC_H_ +#define _IIDC_H_ + +#include +#include +#include +#include +#include +#ifdef USE_INTEL_AUX_BUS +#include "linux/auxiliary_bus.h" +#else +#include +#endif /* USE_INTEL_AUX_BUS */ + +/* This major and minor version represent IDC API version information. + * + * The concept of passing an API version should be incorporated into the + * auxiliary drivers' probe handlers to check if they can communicate with the + * core PCI driver. During auxiliary driver probe, auxiliary driver should + * check major and minor version information (via iidc_core_dev_info:ver). If + * the version check fails, the auxiliary driver should fail the probe and log + * an appropriate message. + */ +#define IIDC_MAJOR_VER 10 +#define IIDC_MINOR_VER 3 + +enum iidc_event_type { + IIDC_EVENT_BEFORE_MTU_CHANGE, + IIDC_EVENT_AFTER_MTU_CHANGE, + IIDC_EVENT_BEFORE_TC_CHANGE, + IIDC_EVENT_AFTER_TC_CHANGE, + IIDC_EVENT_VF_RESET, + IIDC_EVENT_LINK_CHNG, + IIDC_EVENT_CRIT_ERR, + IIDC_EVENT_FAILOVER_START, + IIDC_EVENT_FAILOVER_FINISH, + IIDC_EVENT_WARN_RESET, + IIDC_EVENT_NBITS /* must be last */ +}; + +enum iidc_reset_type { + IIDC_PFR, + IIDC_CORER, + IIDC_GLOBR, +}; + +#define IIDC_RDMA_INVALID_PORT 0xFF + +enum iidc_rdma_protocol { + IIDC_RDMA_PROTOCOL_IWARP = BIT(0), + IIDC_RDMA_PROTOCOL_ROCEV2 = BIT(1), +}; + +enum iidc_rdma_gen { + IIDC_RDMA_GEN_RESERVED = 0, + IIDC_RDMA_GEN_1 = 1, + IIDC_RDMA_GEN_2 = 2, + IIDC_RDMA_GEN_3 = 3, +}; + +struct iidc_rdma_caps { + u8 gen; /* Hardware generation */ + u8 protocols; /* bitmap of supported protocols */ +}; +/* This information is needed to handle auxiliary driver probe */ +struct iidc_ver_info { + u16 major; + u16 minor; + u64 support; +}; + +/* Struct to hold per DCB APP info */ +struct iidc_dcb_app_info { + u8 priority; + u8 selector; + u16 prot_id; +}; + +struct iidc_core_dev_info; + +#define IIDC_MAX_USER_PRIORITY 8 +#define IIDC_MAX_APPS 64 +#define IIDC_MAX_DSCP_MAPPING 64 +#define IIDC_VLAN_PFC_MODE 0x0 +#define IIDC_DSCP_PFC_MODE 0x1 + +/* Struct to hold per RDMA Qset info */ +struct iidc_rdma_qset_params { + u32 teid; /* qset TEID */ + u16 qs_handle; /* RDMA driver provides this */ + u16 vport_id; /* VSI index */ + u8 tc; /* TC branch the QSet should belong to */ +}; + +struct iidc_rdma_multi_qset_params { + u32 teid[2]; /* qset TEID(s) */ + u16 qs_handle[2]; /* Provided by RDMA, used in AQ command */ + u8 qset_port[2]; /* port where qset currently resides */ + u16 vport_id; /* VSI Index */ + u8 tc; /* Traffic class the QSet(s) belong to */ + u8 num; /* Number of qsets in this param set (1-2) */ + u8 rdma_port[2]; /* Port for each qset to talk out of */ + u8 active_ports; /* bitmap of which ports are active */ +}; + +struct iidc_qos_info { + u64 tc_ctx; + u8 rel_bw; + u8 prio_type; + u8 egress_virt_up; + u8 ingress_virt_up; +}; + +/* Struct to hold QoS info */ +struct iidc_qos_params { + struct iidc_qos_info tc_info[IEEE_8021QAZ_MAX_TCS]; + u8 up2tc[IIDC_MAX_USER_PRIORITY]; + u8 vport_relative_bw; + u8 vport_priority_type; + u32 num_apps; + u8 pfc_mode; + struct iidc_dcb_app_info apps[IIDC_MAX_APPS]; + u8 dscp_map[IIDC_MAX_DSCP_MAPPING]; + u8 num_tc; +}; + +union iidc_event_info { + /* IIDC_EVENT_AFTER_TC_CHANGE */ + struct iidc_qos_params port_qos; + /* IIDC_EVENT_LINK_CHNG */ + bool link_up; + /* IIDC_EVENT_VF_RESET */ + u32 vf_id; + /* IIDC_EVENT_CRIT_ERR */ + u32 reg; +}; + +struct iidc_event { + DECLARE_BITMAP(type, IIDC_EVENT_NBITS); + union iidc_event_info info; +}; + +/* RDMA queue vector map info */ +struct iidc_qv_info { + u32 v_idx; + u16 ceq_idx; + u16 aeq_idx; + u8 itr_idx; +}; + +struct iidc_qvlist_info { + u32 num_vectors; + struct iidc_qv_info qv_info[1]; +}; + +struct iidc_vf_port_info { + u16 vf_id; + u16 vport_id; + u16 port_vlan_id; + u16 port_vlan_tpid; +}; + +/* Following APIs are implemented by core PCI driver */ +struct iidc_core_ops { + /* APIs to allocate resources such as VEB, VSI, Doorbell queues, + * completion queues, Tx/Rx queues, etc... + */ + int (*alloc_res)(struct iidc_core_dev_info *cdev_info, + struct iidc_rdma_qset_params *qset); + int (*free_res)(struct iidc_core_dev_info *cdev_info, + struct iidc_rdma_qset_params *qset); + + int (*request_reset)(struct iidc_core_dev_info *cdev_info, + enum iidc_reset_type reset_type); + + int (*update_vport_filter)(struct iidc_core_dev_info *cdev_info, + u16 vport_id, bool enable); + int (*get_vf_info)(struct iidc_core_dev_info *cdev_info, u16 vf_id, + struct iidc_vf_port_info *vf_port_info); + int (*vc_send)(struct iidc_core_dev_info *cdev_info, u32 vf_id, u8 *msg, + u16 len); + int (*vc_send_sync)(struct iidc_core_dev_info *cdev_info, u8 *msg, + u16 len, u8 *recv_msg, u16 *recv_len); + int (*vc_queue_vec_map_unmap)(struct iidc_core_dev_info *cdev_info, + struct iidc_qvlist_info *qvl_info, + bool map); + int (*ieps_entry)(struct iidc_core_dev_info *obj, void *arg); + int (*alloc_multi_res)(struct iidc_core_dev_info *cdev_info, + struct iidc_rdma_multi_qset_params *qset); + int (*free_multi_res)(struct iidc_core_dev_info *cdev_info, + struct iidc_rdma_multi_qset_params *qset); +}; + +#define IIDC_RDMA_ROCE_NAME "roce" +#define IIDC_RDMA_IWARP_NAME "iwarp" +#define IIDC_RDMA_ID 0x00000010 +#define IIDC_IEPS_NAME "ieps" +#define IIDC_IEPS_ID 0x00000015 +#define IIDC_MAX_NUM_AUX 5 + +/* The const struct that instantiates cdev_info_id needs to be initialized + * in the .c with the macro ASSIGN_IIDC_INFO. + * For example: + * static const struct cdev_info_id cdev_info_ids[] = ASSIGN_IIDC_INFO; + */ +struct cdev_info_id { + char *name; + int id; +}; + +#define IIDC_RDMA_INFO { .name = IIDC_RDMA_ROCE_NAME, .id = IIDC_RDMA_ID }, +#define IIDC_IEPS_INFO { .name = IIDC_IEPS_NAME, .id = IIDC_IEPS_ID }, + +#define ASSIGN_IIDC_INFO \ +{ \ + IIDC_IEPS_INFO \ + IIDC_RDMA_INFO \ +} + +enum iidc_function_type { + IIDC_FUNCTION_TYPE_PF, + IIDC_FUNCTION_TYPE_VF, +}; + +/* Structure representing auxiliary driver tailored information about the core + * PCI dev, each auxiliary driver using the IIDC interface will have an + * instance of this struct dedicated to it. + */ +struct iidc_core_dev_info { + struct pci_dev *pdev; /* PCI device of corresponding to main function */ + struct auxiliary_device *adev; + /* KVA / Linear address corresponding to BAR0 of underlying + * pci_device. + */ + u8 __iomem *hw_addr; + int cdev_info_id; + struct iidc_ver_info ver; + + /* Opaque pointer for aux driver specific data tracking. This memory + * will be alloc'd and freed by the auxiliary driver and used for + * private data accessible only to the specific auxiliary driver. + * It is stored here so that when this struct is passed to the + * auxiliary driver via an IIDC call, the data can be accessed + * at that time. + */ + void *auxiliary_priv; + + enum iidc_function_type ftype; + u16 vport_id; + /* Current active RDMA protocol */ + enum iidc_rdma_protocol rdma_protocol; + + struct iidc_qos_params qos_info; + struct net_device *netdev; + + struct msix_entry *msix_entries; + u16 msix_count; /* How many vectors are reserved for this device */ + struct iidc_rdma_caps rdma_caps; + /* Following struct contains function pointers to be initialized + * by core PCI driver and called by auxiliary driver + */ + const struct iidc_core_ops *ops; + u8 pf_id; + u8 main_pf_port; + u8 rdma_active_port; +#define IIDC_RDMA_PRIMARY_PORT 0x1 +#define IIDC_RDMA_SECONDARY_PORT 0x2 +#define IIDC_RDMA_BOTH_PORT 0x3 + u8 rdma_ports[2]; + u8 bond_aa; /* is 1 if the bond is a supported active-active mode */ + u8 rdma_port_bitmap; /* bitmap of port's link on active-active bond */ +}; + +struct iidc_auxiliary_dev { + struct auxiliary_device adev; + struct iidc_core_dev_info *cdev_info; +}; + +/* structure representing the auxiliary driver. This struct is to be + * allocated and populated by the auxiliary driver's owner. The core PCI + * driver will access these ops by performing a container_of on the + * auxiliary_device->dev.driver. + */ +struct iidc_auxiliary_drv { + struct auxiliary_driver adrv; + /* This event_handler is meant to be a blocking call. For instance, + * when a BEFORE_MTU_CHANGE event comes in, the event_handler will not + * return until the auxiliary driver is ready for the MTU change to + * happen. + */ + void (*event_handler)(struct iidc_core_dev_info *cdev_info, + struct iidc_event *event); + int (*vc_receive)(struct iidc_core_dev_info *cdev_info, u32 vf_id, + u8 *msg, u16 len); +}; + +#endif /* _IIDC_H_*/ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/irdma-abi.h b/drivers/intel/irdma-1.14.33/src/irdma/irdma-abi.h new file mode 100644 index 000000000..f3250bc84 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/irdma-abi.h @@ -0,0 +1,144 @@ +/* SPDX-License-Identifier: (GPL-2.0 WITH Linux-syscall-note) OR Linux-OpenIB) */ +/* + * Copyright (c) 2006 - 2022 Intel Corporation. All rights reserved. + * Copyright (c) 2005 Topspin Communications. All rights reserved. + * Copyright (c) 2005 Cisco Systems. All rights reserved. + * Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved. + */ + +#ifndef IRDMA_ABI_H +#define IRDMA_ABI_H + +#include + +/* irdma must support legacy GEN_1 i40iw kernel + * and user-space whose last ABI ver is 5 + */ +#define IRDMA_ABI_VER 5 + +enum irdma_memreg_type { + IRDMA_MEMREG_TYPE_MEM = 0, + IRDMA_MEMREG_TYPE_QP = 1, + IRDMA_MEMREG_TYPE_CQ = 2, + IRDMA_MEMREG_TYPE_SRQ = 3, +}; + +enum { + IRDMA_ALLOC_UCTX_USE_RAW_ATTR = 1 << 0, + IRDMA_ALLOC_UCTX_MIN_HW_WQ_SIZE = 1 << 1, + IRDMA_ALLOC_UCTX_MAX_HW_SRQ_QUANTA = 1 << 2, + IRDMA_SUPPORT_WQE_FORMAT_V2 = 1 << 3, + IRDMA_SUPPORT_MAX_HW_PUSH_LEN = 1 << 4, +}; + +enum { + IRDMA_CREATE_QP_USE_START_WQE_IDX = 1 << 0, +}; + +struct irdma_alloc_ucontext_req { + __u32 rsvd32; + __u8 userspace_ver; + __u8 rsvd8[3]; + __aligned_u64 comp_mask; +}; + +struct irdma_alloc_ucontext_resp { + __u32 max_pds; + __u32 max_qps; + __u32 wq_size; /* size of the WQs (SQ+RQ) in the mmaped area */ + __u8 kernel_ver; + __u8 rsvd[3]; + __aligned_u64 feature_flags; + __aligned_u64 db_mmap_key; + __u32 max_hw_wq_frags; + __u32 max_hw_read_sges; + __u32 max_hw_inline; + __u32 max_hw_rq_quanta; + __u32 max_hw_wq_quanta; + __u32 min_hw_cq_size; + __u32 max_hw_cq_size; + __u16 max_hw_sq_chunk; + __u8 hw_rev; + __u8 rsvd2; + __aligned_u64 comp_mask; + __u16 min_hw_wq_size; + __u32 max_hw_srq_quanta; + __u16 max_hw_push_len; +}; + +struct irdma_alloc_pd_resp { + __u32 pd_id; + __u8 rsvd[4]; +}; + +struct irdma_resize_cq_req { + __aligned_u64 user_cq_buffer; +}; + +struct irdma_create_cq_req { + __aligned_u64 user_cq_buf; + __aligned_u64 user_shadow_area; +}; + +struct irdma_create_srq_req { + __aligned_u64 user_srq_buf; + __aligned_u64 user_shadow_area; +}; + +struct irdma_create_srq_resp { + __u32 srq_id; + __u32 srq_size; +}; + +struct irdma_create_qp_req { + __aligned_u64 user_wqe_bufs; + __aligned_u64 user_compl_ctx; + __aligned_u64 comp_mask; +}; + +struct irdma_mem_reg_req { + __u16 reg_type; /* enum irdma_memreg_type */ + __u16 cq_pages; + __u16 rq_pages; + __u16 sq_pages; +}; + +struct irdma_modify_qp_req { + __u8 sq_flush; + __u8 rq_flush; + __u8 rsvd[6]; +}; + +struct irdma_create_cq_resp { + __u32 cq_id; + __u32 cq_size; +}; + +struct irdma_create_qp_resp { + __u32 qp_id; + __u32 actual_sq_size; + __u32 actual_rq_size; + __u32 irdma_drv_opt; + __u16 push_idx; + __u8 lsmm; + __u8 rsvd; + __u32 qp_caps; + __aligned_u64 comp_mask; + __u8 start_wqe_idx; + __u8 rsvd2[7]; +}; + +struct irdma_modify_qp_resp { + __aligned_u64 push_wqe_mmap_key; + __aligned_u64 push_db_mmap_key; + __u16 push_offset; + __u8 push_valid; + __u8 rd_fence_rate; + __u8 rsvd[4]; +}; + +struct irdma_create_ah_resp { + __u32 ah_id; + __u8 rsvd[4]; +}; +#endif /* IRDMA_ABI_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/irdma.h b/drivers/intel/irdma-1.14.33/src/irdma/irdma.h new file mode 100644 index 000000000..e54eaad90 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/irdma.h @@ -0,0 +1,211 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2017 - 2022 Intel Corporation */ +#ifndef IRDMA_H +#define IRDMA_H + +#define RDMA_BIT2(type, a) ((u##type) 1UL << a) +#define RDMA_MASK3(type, mask, shift) ((u##type) mask << shift) +#define MAKEMASK(m, s) ((m) << (s)) + +#define IRDMA_WQEALLOC_WQE_DESC_INDEX_S 20 +#define IRDMA_WQEALLOC_WQE_DESC_INDEX GENMASK(31, 20) + +#define IRDMA_CQPTAIL_WQTAIL_S 0 +#define IRDMA_CQPTAIL_WQTAIL GENMASK(10, 0) +#define IRDMA_CQPTAIL_CQP_OP_ERR_S 31 +#define IRDMA_CQPTAIL_CQP_OP_ERR BIT(31) + +#define IRDMA_CQPERRCODES_CQP_MINOR_CODE_S 0 +#define IRDMA_CQPERRCODES_CQP_MINOR_CODE GENMASK(15, 0) +#define IRDMA_CQPERRCODES_CQP_MAJOR_CODE_S 16 +#define IRDMA_CQPERRCODES_CQP_MAJOR_CODE GENMASK(31, 16) +#define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE_S 4 +#define IRDMA_GLPCI_LBARCTRL_PE_DB_SIZE GENMASK(5, 4) +#define IRDMA_GLINT_RATE_INTERVAL_S 0 +#define IRDMA_GLINT_RATE_INTERVAL GENMASK(4, 0) +#define IRDMA_GLINT_RATE_INTRL_ENA_S 6 +#define IRDMA_GLINT_RATE_INTRL_ENA_M BIT(6) +#define IRDMA_GLINT_RATE_INTRL_ENA BIT(6) + +#define IRDMA_GLINT_DYN_CTL_INTENA_S 0 +#define IRDMA_GLINT_DYN_CTL_INTENA BIT(0) +#define IRDMA_GLINT_DYN_CTL_CLEARPBA_S 1 +#define IRDMA_GLINT_DYN_CTL_CLEARPBA BIT(1) +#define IRDMA_GLINT_DYN_CTL_ITR_INDX_S 3 +#define IRDMA_GLINT_DYN_CTL_ITR_INDX GENMASK(4, 3) +#define IRDMA_GLINT_DYN_CTL_INTERVAL_S 5 +#define IRDMA_GLINT_DYN_CTL_INTERVAL GENMASK(16, 5) +#define IRDMA_GLINT_CEQCTL_ITR_INDX_S 11 +#define IRDMA_GLINT_CEQCTL_ITR_INDX GENMASK(12, 11) +#define IRDMA_GLINT_CEQCTL_CAUSE_ENA_S 30 +#define IRDMA_GLINT_CEQCTL_CAUSE_ENA BIT(30) +#define IRDMA_GLINT_CEQCTL_MSIX_INDX_S 0 +#define IRDMA_GLINT_CEQCTL_MSIX_INDX GENMASK(10, 0) +#define IRDMA_PFINT_AEQCTL_MSIX_INDX_S 0 +#define IRDMA_PFINT_AEQCTL_MSIX_INDX GENMASK(10, 0) +#define IRDMA_PFINT_AEQCTL_ITR_INDX_S 11 +#define IRDMA_PFINT_AEQCTL_ITR_INDX GENMASK(12, 11) +#define IRDMA_PFINT_AEQCTL_CAUSE_ENA_S 30 +#define IRDMA_PFINT_AEQCTL_CAUSE_ENA BIT(30) +#define IRDMA_PFHMC_PDINV_PMSDIDX_S 0 +#define IRDMA_PFHMC_PDINV_PMSDIDX GENMASK(11, 0) +#define IRDMA_PFHMC_PDINV_PMSDPARTSEL_S 15 +#define IRDMA_PFHMC_PDINV_PMSDPARTSEL BIT(15) +#define IRDMA_PFHMC_PDINV_PMPDIDX_S 16 +#define IRDMA_PFHMC_PDINV_PMPDIDX GENMASK(24, 16) +#define IRDMA_PFHMC_SDDATALOW_PMSDVALID_S 0 +#define IRDMA_PFHMC_SDDATALOW_PMSDVALID BIT(0) +#define IRDMA_PFHMC_SDDATALOW_PMSDTYPE_S 1 +#define IRDMA_PFHMC_SDDATALOW_PMSDTYPE BIT(1) +#define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT_S 2 +#define IRDMA_PFHMC_SDDATALOW_PMSDBPCOUNT GENMASK(11, 2) +#define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW_S 12 +#define IRDMA_PFHMC_SDDATALOW_PMSDDATALOW GENMASK(31, 12) +#define IRDMA_PFHMC_SDCMD_PMSDWR_S 31 +#define IRDMA_PFHMC_SDCMD_PMSDWR BIT(31) +#define IRDMA_PFHMC_SDCMD_PMSDPARTSEL_S 15 +#define IRDMA_PFHMC_SDCMD_PMSDPARTSEL BIT(15) + +#define IRDMA_INVALID_CQ_IDX 0xffffffff +#define IRDMA_Q_INVALID_IDX 0xffff + +enum irdma_dyn_idx_t { + IRDMA_IDX_ITR0 = 0, + IRDMA_IDX_ITR1 = 1, + IRDMA_IDX_ITR2 = 2, + IRDMA_IDX_NOITR = 3, +}; + +enum irdma_registers { + IRDMA_CQPTAIL, + IRDMA_CQPDB, + IRDMA_CCQPSTATUS, + IRDMA_CCQPHIGH, + IRDMA_CCQPLOW, + IRDMA_CQARM, + IRDMA_CQACK, + IRDMA_AEQALLOC, + IRDMA_CQPERRCODES, + IRDMA_WQEALLOC, + IRDMA_GLINT_DYN_CTL, + IRDMA_DB_ADDR_OFFSET, + IRDMA_GLPCI_LBARCTRL, + IRDMA_GLPE_CPUSTATUS0, + IRDMA_GLPE_CPUSTATUS1, + IRDMA_GLPE_CPUSTATUS2, + IRDMA_PFINT_AEQCTL, + IRDMA_GLINT_CEQCTL, + IRDMA_VSIQF_PE_CTL1, + IRDMA_PFHMC_PDINV, + IRDMA_GLHMC_VFPDINV, + IRDMA_GLPE_CRITERR, + IRDMA_GLINT_RATE, + IRDMA_MAX_REGS, /* Must be last entry */ +}; + +enum irdma_shifts { + IRDMA_CCQPSTATUS_CCQP_DONE_S, + IRDMA_CCQPSTATUS_CCQP_ERR_S, + IRDMA_CQPSQ_STAG_PDID_S, + IRDMA_CQPSQ_CQ_CEQID_S, + IRDMA_CQPSQ_CQ_CQID_S, + IRDMA_COMMIT_FPM_CQCNT_S, + IRDMA_CQPSQ_UPESD_HMCFNID_S, + IRDMA_MAX_SHIFTS, +}; + +enum irdma_masks { + IRDMA_CCQPSTATUS_CCQP_DONE_M, + IRDMA_CCQPSTATUS_CCQP_ERR_M, + IRDMA_CQPSQ_STAG_PDID_M, + IRDMA_CQPSQ_CQ_CEQID_M, + IRDMA_CQPSQ_CQ_CQID_M, + IRDMA_COMMIT_FPM_CQCNT_M, + IRDMA_CQPSQ_UPESD_HMCFNID_M, + IRDMA_MAX_MASKS, /* Must be last entry */ +}; + +#define IRDMA_MAX_MGS_PER_CTX 8 + +struct irdma_mcast_grp_ctx_entry_info { + u32 qp_id; + bool valid_entry; + u16 dest_port; + u32 use_cnt; +}; + +struct irdma_mcast_grp_info { + u8 dest_mac_addr[ETH_ALEN]; + u16 vlan_id; + u16 hmc_fcn_id; + bool ipv4_valid:1; + bool vlan_valid:1; + u16 mg_id; + u32 no_of_mgs; + u32 dest_ip_addr[4]; + u16 qs_handle; + struct irdma_dma_mem dma_mem_mc; + struct irdma_mcast_grp_ctx_entry_info mg_ctx_info[IRDMA_MAX_MGS_PER_CTX]; +}; + +enum irdma_vers { + IRDMA_GEN_RSVD = 0, + IRDMA_GEN_1 = 1, + IRDMA_GEN_2 = 2, + IRDMA_GEN_3 = 3, + IRDMA_GEN_4 = 4, + IRDMA_GEN_MAX = IRDMA_GEN_4, +}; + +struct irdma_uk_attrs { + u64 feature_flags; + u32 max_hw_wq_frags; + u32 max_hw_read_sges; + u32 max_hw_inline; + u32 max_hw_rq_quanta; + u32 max_hw_wq_quanta; + u32 min_hw_cq_size; + u32 max_hw_cq_size; + u32 max_hw_srq_quanta; + u16 max_hw_push_len; + u16 max_hw_sq_chunk; + u16 min_hw_wq_size; + u8 hw_rev; +}; + +struct irdma_hw_attrs { + struct irdma_uk_attrs uk_attrs; + u64 max_hw_outbound_msg_size; + u64 max_hw_inbound_msg_size; + u64 max_mr_size; + u64 page_size_cap; + u32 min_hw_qp_id; + u32 min_hw_aeq_size; + u32 max_hw_aeq_size; + u32 min_hw_ceq_size; + u32 max_hw_ceq_size; + u32 max_hw_device_pages; + u32 max_hw_vf_fpm_id; + u32 first_hw_vf_fpm_id; + u32 max_hw_ird; + u32 max_hw_ord; + u32 max_hw_wqes; + u32 max_hw_pds; + u32 max_hw_ena_vf_count; + u32 max_qp_wr; + u32 max_pe_ready_count; + u32 max_done_count; + u32 max_sleep_count; + u32 max_cqp_compl_wait_time_ms; + u32 min_hw_srq_id; + u16 max_stat_inst; + u16 max_stat_idx; +}; + +void i40iw_init_hw(struct irdma_sc_dev *dev); +void icrdma_init_hw(struct irdma_sc_dev *dev); +void irdma_check_fc_for_qp(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp); +void ig3rdma_init_hw(struct irdma_sc_dev *dev); +int ig3rdma_post_cqp_create(struct irdma_sc_dev *dev); +void ig3rdma_post_cqp_destroy(struct irdma_sc_dev *dev); +#endif /* IRDMA_H*/ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/irdma_kcompat.c b/drivers/intel/irdma-1.14.33/src/irdma/irdma_kcompat.c new file mode 100644 index 000000000..5abe37e5c --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/irdma_kcompat.c @@ -0,0 +1,4010 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2018 - 2024 Intel Corporation */ +#include "main.h" + +#define IRDMA_ROCE_UDP_ENCAP_VALID_PORT_MIN (0xC000) + +static u16 kc_rdma_flow_label_to_udp_sport(u32 fl) +{ + u32 fl_low = fl & 0x03FFF; + u32 fl_high = fl & 0xFC000; + + fl_low ^= fl_high >> 14; + + return (u16)(fl_low | IRDMA_ROCE_UDP_ENCAP_VALID_PORT_MIN); +} + +#define IRDMA_GRH_FLOWLABEL_MASK (0x000FFFFF) + +static u32 kc_rdma_calc_flow_label(u32 lqpn, u32 rqpn) +{ + u64 fl = (u64)lqpn * rqpn; + + fl ^= fl >> 20; + fl ^= fl >> 40; + + return (u32)(fl & IRDMA_GRH_FLOWLABEL_MASK); +} + +u16 kc_rdma_get_udp_sport(u32 fl, u32 lqpn, u32 rqpn) +{ + if (!fl) + fl = kc_rdma_calc_flow_label(lqpn, rqpn); + return kc_rdma_flow_label_to_udp_sport(fl); +} + +struct dst_entry *irdma_get_fl6_dst(struct sockaddr_in6 *src_addr, + struct sockaddr_in6 *dst_addr) +{ + struct dst_entry *dst = NULL; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39) + struct flowi6 fl6 = {}; + + fl6.daddr = dst_addr->sin6_addr; + fl6.saddr = src_addr->sin6_addr; + if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL) + fl6.flowi6_oif = dst_addr->sin6_scope_id; + + dst = ip6_route_output(&init_net, NULL, &fl6); +#else + struct flowi fl = {}; + + ipv6_addr_copy(&fl.fl6_dst, &dst_addr->sin6_addr); + ipv6_addr_copy(&fl.fl6_src, &src_addr->sin6_addr); + if (ipv6_addr_type(&fl.fl6_dst) & IPV6_ADDR_LINKLOCAL) + fl.oif = dst_addr->sin6_scope_id; + + dst = ip6_route_output(&init_net, NULL, &fl); +#endif /* >= 2.6.39 */ + return dst; +} + +struct neighbour *irdma_get_neigh_ipv6(struct dst_entry *dst, + struct sockaddr_in6 *dst_ipaddr) +{ + struct neighbour *neigh = NULL; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0) + neigh = dst_neigh_lookup(dst, dst_ipaddr); +#elif LINUX_VERSION_CODE > KERNEL_VERSION(3, 0, 0) + neigh = dst->_neighbour; +#else + neigh = dst->neighbour; +#endif /* >= 3.1.0 */ + return neigh; +} + +struct neighbour *irdma_get_neigh_ipv4(struct rtable *rt, __be32 *dst_ipaddr) +{ + struct neighbour *neigh = NULL; + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 1, 0) + neigh = dst_neigh_lookup(&rt->dst, dst_ipaddr); +#elif LINUX_VERSION_CODE > KERNEL_VERSION(3, 0, 0) + neigh = rt->dst._neighbour; +#elif LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) + neigh = rt->u.dst.neighbour; +#else + neigh = rt->dst.neighbour; +#endif /* >= 3.1.0 */ + return neigh; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0) +struct net_device *irdma_netdev_master_upper_dev_get(struct net_device *netdev) +{ + return netdev->master; +} + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) +struct rtable *irdma_ip_route_output(struct net *net, __be32 daddr, + __be32 saddr, u8 tos, int oif) +{ + struct flowi fl = {}; + struct rtable *rt; + int ret; + + fl.nl_u.ip4_u.daddr = daddr; + fl.nl_u.ip4_u.saddr = saddr; + fl.oif = oif; + ret = ip_route_output_key(net, &rt, &fl); + return rt; +} + +#endif /* 2.6.39 */ +#endif /* 3.9.0 */ +#ifdef IB_FW_VERSION_NAME_MAX +void irdma_get_dev_fw_str(struct ib_device *dev, + char *str) +{ + struct irdma_device *iwdev = to_iwdev(dev); + + snprintf(str, IB_FW_VERSION_NAME_MAX, "%u.%u", + irdma_fw_major_ver(&iwdev->rf->sc_dev), + irdma_fw_minor_ver(&iwdev->rf->sc_dev)); +} +#else +void irdma_get_dev_fw_str(struct ib_device *dev, + char *str, + size_t str_len) +{ + struct irdma_device *iwdev = to_iwdev(dev); + + snprintf(str, str_len, "%u.%u", + irdma_fw_major_ver(&iwdev->rf->sc_dev), + irdma_fw_minor_ver(&iwdev->rf->sc_dev)); +} +#endif /* IB_FW_VERSION_NAME_MAX */ + +#ifdef IRDMA_ADD_DEL_GID +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context) +{ + return 0; +} + +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context) +{ + return 0; +} +#endif /* < 4.17.0 */ + +#ifdef IRDMA_ALLOC_MR_VER_1 +/** + * irdma_alloc_mr - register stag for fast memory registration + * @pd: ibpd pointer + * @mr_type: memory for stag registrion + * @max_num_sg: man number of pages + * @udata: user data + */ +struct ib_mr *irdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, + u32 max_num_sg, struct ib_udata *udata) +{ +#elif defined(IRDMA_ALLOC_MR_VER_0) +/** + * irdma_alloc_mr - register stag for fast memory registration + * @pd: ibpd pointer + * @mr_type: memory for stag registrion + * @max_num_sg: man number of pages + */ +struct ib_mr *irdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, + u32 max_num_sg) +{ +#endif + struct irdma_device *iwdev = to_iwdev(pd->device); + struct irdma_pble_alloc *palloc; + struct irdma_pbl *iwpbl; + struct irdma_mr *iwmr; + int status; + u32 stag; + int err_code = -ENOMEM; + + iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL); + if (!iwmr) + return ERR_PTR(-ENOMEM); + + stag = irdma_create_stag(iwdev); + if (!stag) { + err_code = -ENOMEM; + goto err; + } + + iwmr->stag = stag; + iwmr->ibmr.rkey = stag; + iwmr->ibmr.lkey = stag; + iwmr->ibmr.pd = pd; + iwmr->ibmr.device = pd->device; + iwpbl = &iwmr->iwpbl; + iwpbl->iwmr = iwmr; + iwmr->type = IRDMA_MEMREG_TYPE_MEM; + palloc = &iwpbl->pble_alloc; + iwmr->page_cnt = max_num_sg; + /* Assume system PAGE_SIZE as the sg page sizes are unknown. */ + iwmr->len = max_num_sg * PAGE_SIZE; + status = irdma_get_pble(iwdev->rf->pble_rsrc, palloc, iwmr->page_cnt, + false); + if (status) + goto err_get_pble; + + err_code = irdma_hw_alloc_stag(iwdev, iwmr); + if (err_code) + goto err_alloc_stag; + + iwpbl->pbl_allocated = true; + + return &iwmr->ibmr; +err_alloc_stag: + irdma_free_pble(iwdev->rf->pble_rsrc, palloc); +err_get_pble: + irdma_free_stag(iwdev, stag); +err: + kfree(iwmr); + + return ERR_PTR(err_code); +} + +#define IRDMA_ALLOC_UCTX_MIN_REQ_LEN offsetofend(struct irdma_alloc_ucontext_req, rsvd8) +#define IRDMA_ALLOC_UCTX_MIN_RESP_LEN offsetofend(struct irdma_alloc_ucontext_resp, rsvd) +#ifdef ALLOC_UCONTEXT_VER_2 +/** + * irdma_alloc_ucontext - Allocate the user context data structure + * @uctx: context + * @udata: user data + * + * This keeps track of all objects associated with a particular + * user-mode client. + */ +int irdma_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata) +{ + struct ib_device *ibdev = uctx->device; + struct irdma_device *iwdev = to_iwdev(ibdev); + struct irdma_alloc_ucontext_req req = {}; + struct irdma_alloc_ucontext_resp uresp = {}; + struct irdma_ucontext *ucontext = to_ucontext(uctx); + struct irdma_uk_attrs *uk_attrs = &iwdev->rf->sc_dev.hw_attrs.uk_attrs; + + if (udata->inlen < IRDMA_ALLOC_UCTX_MIN_REQ_LEN || + udata->outlen < IRDMA_ALLOC_UCTX_MIN_RESP_LEN) + return -EINVAL; + + if (ib_copy_from_udata(&req, udata, min(sizeof(req), udata->inlen))) + return -EINVAL; + + if (req.userspace_ver < 4 || req.userspace_ver > IRDMA_ABI_VER) + goto ver_error; + + ucontext->iwdev = iwdev; + ucontext->abi_ver = req.userspace_ver; + + if (!(req.comp_mask & IRDMA_SUPPORT_WQE_FORMAT_V2) && + uk_attrs->hw_rev >= IRDMA_GEN_3) + return -EOPNOTSUPP; + + if (req.comp_mask & IRDMA_ALLOC_UCTX_USE_RAW_ATTR) + ucontext->use_raw_attrs = true; + + /* GEN_1 support for libi40iw */ + if (udata->outlen == IRDMA_ALLOC_UCTX_MIN_RESP_LEN) { + if (uk_attrs->hw_rev != IRDMA_GEN_1) + return -EOPNOTSUPP; + + ucontext->legacy_mode = true; + uresp.max_qps = iwdev->rf->max_qp; + uresp.max_pds = iwdev->rf->sc_dev.hw_attrs.max_hw_pds; + uresp.wq_size = iwdev->rf->sc_dev.hw_attrs.max_qp_wr * 2; + uresp.kernel_ver = req.userspace_ver; + if (ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), udata->outlen))) + return -EFAULT; + } else { + u64 bar_off; + + uresp.kernel_ver = IRDMA_ABI_VER; + uresp.feature_flags = uk_attrs->feature_flags; + uresp.max_hw_wq_frags = uk_attrs->max_hw_wq_frags; + uresp.max_hw_read_sges = uk_attrs->max_hw_read_sges; + uresp.max_hw_inline = uk_attrs->max_hw_inline; + uresp.max_hw_rq_quanta = uk_attrs->max_hw_rq_quanta; + uresp.max_hw_wq_quanta = uk_attrs->max_hw_wq_quanta; + uresp.max_hw_sq_chunk = uk_attrs->max_hw_sq_chunk; + uresp.max_hw_cq_size = uk_attrs->max_hw_cq_size; + uresp.min_hw_cq_size = uk_attrs->min_hw_cq_size; + uresp.hw_rev = uk_attrs->hw_rev; + uresp.comp_mask |= IRDMA_ALLOC_UCTX_USE_RAW_ATTR; + uresp.min_hw_wq_size = uk_attrs->min_hw_wq_size; + uresp.comp_mask |= IRDMA_ALLOC_UCTX_MIN_HW_WQ_SIZE; + uresp.max_hw_srq_quanta = uk_attrs->max_hw_srq_quanta; + uresp.comp_mask |= IRDMA_ALLOC_UCTX_MAX_HW_SRQ_QUANTA; + uresp.max_hw_push_len = uk_attrs->max_hw_push_len; + uresp.comp_mask |= IRDMA_SUPPORT_MAX_HW_PUSH_LEN; + + bar_off = + (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET]; +#ifdef RDMA_MMAP_DB_SUPPORT + ucontext->db_mmap_entry = + irdma_user_mmap_entry_insert(ucontext, bar_off, + IRDMA_MMAP_IO_NC, + &uresp.db_mmap_key); +#else + spin_lock_init(&ucontext->mmap_tbl_lock); + ucontext->db_mmap_entry = + irdma_user_mmap_entry_add_hash(ucontext, bar_off, + IRDMA_MMAP_IO_NC, + &uresp.db_mmap_key); +#endif /* RDMA_MMAP_DB_SUPPORT */ + if (!ucontext->db_mmap_entry) { +#ifndef RDMA_MMAP_DB_SUPPORT +#endif + return -ENOMEM; + } + + if (ib_copy_to_udata(udata, &uresp, + min(sizeof(uresp), udata->outlen))) { +#ifdef RDMA_MMAP_DB_SUPPORT + rdma_user_mmap_entry_remove(ucontext->db_mmap_entry); +#else + irdma_user_mmap_entry_del_hash(ucontext->db_mmap_entry); +#endif + return -EFAULT; + } + } + + INIT_LIST_HEAD(&ucontext->cq_reg_mem_list); + spin_lock_init(&ucontext->cq_reg_mem_list_lock); + INIT_LIST_HEAD(&ucontext->qp_reg_mem_list); + spin_lock_init(&ucontext->qp_reg_mem_list_lock); + INIT_LIST_HEAD(&ucontext->srq_reg_mem_list); + spin_lock_init(&ucontext->srq_reg_mem_list_lock); +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) + INIT_LIST_HEAD(&ucontext->vma_list); + mutex_init(&ucontext->vma_list_mutex); +#endif + +#ifdef CONFIG_DEBUG_FS + irdma_dbg_save_ucontext(iwdev, ucontext); +#endif + return 0; + +ver_error: + ibdev_err(&iwdev->ibdev, + "Invalid userspace driver version detected. Detected version %d, should be %d\n", + req.userspace_ver, IRDMA_ABI_VER); + return -EINVAL; +} +#endif + +#ifdef ALLOC_UCONTEXT_VER_1 +/** + * irdma_alloc_ucontext - Allocate the user context data structure + * @ibdev: ib device pointer + * @udata: user data + * + * This keeps track of all objects associated with a particular + * user-mode client. + */ +struct ib_ucontext *irdma_alloc_ucontext(struct ib_device *ibdev, struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ibdev); + struct irdma_alloc_ucontext_req req = {}; + struct irdma_alloc_ucontext_resp uresp = {}; + struct irdma_ucontext *ucontext; + struct irdma_uk_attrs *uk_attrs = &iwdev->rf->sc_dev.hw_attrs.uk_attrs; + + if (udata->inlen < IRDMA_ALLOC_UCTX_MIN_REQ_LEN || + udata->outlen < IRDMA_ALLOC_UCTX_MIN_RESP_LEN) + return ERR_PTR(-EINVAL); + + if (ib_copy_from_udata(&req, udata, min(sizeof(req), udata->inlen))) + return ERR_PTR(-EINVAL); + + if (req.userspace_ver < 4 || req.userspace_ver > IRDMA_ABI_VER) + goto ver_error; + + if (!(req.comp_mask & IRDMA_SUPPORT_WQE_FORMAT_V2) && + uk_attrs->hw_rev >= IRDMA_GEN_3) + return ERR_PTR(-EOPNOTSUPP); + + ucontext = kzalloc(sizeof(*ucontext), GFP_KERNEL); + if (!ucontext) + return ERR_PTR(-ENOMEM); + + ucontext->iwdev = iwdev; + ucontext->abi_ver = req.userspace_ver; + + if (req.comp_mask & IRDMA_ALLOC_UCTX_USE_RAW_ATTR) + ucontext->use_raw_attrs = true; + + /* GEN_1 legacy support with libi40iw */ + if (udata->outlen == IRDMA_ALLOC_UCTX_MIN_RESP_LEN) { + if (uk_attrs->hw_rev != IRDMA_GEN_1) { + kfree(ucontext); + return ERR_PTR(-EOPNOTSUPP); + } + + ucontext->legacy_mode = true; + uresp.max_qps = iwdev->rf->max_qp; + uresp.max_pds = iwdev->rf->sc_dev.hw_attrs.max_hw_pds; + uresp.wq_size = iwdev->rf->sc_dev.hw_attrs.max_qp_wr * 2; + uresp.kernel_ver = req.userspace_ver; + if (ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), udata->outlen))) { + kfree(ucontext); + return ERR_PTR(-EFAULT); + } + } else { + u64 bar_off; + + uresp.kernel_ver = IRDMA_ABI_VER; + uresp.feature_flags = uk_attrs->feature_flags; + uresp.max_hw_wq_frags = uk_attrs->max_hw_wq_frags; + uresp.max_hw_read_sges = uk_attrs->max_hw_read_sges; + uresp.max_hw_inline = uk_attrs->max_hw_inline; + uresp.max_hw_rq_quanta = uk_attrs->max_hw_rq_quanta; + uresp.max_hw_wq_quanta = uk_attrs->max_hw_wq_quanta; + uresp.max_hw_sq_chunk = uk_attrs->max_hw_sq_chunk; + uresp.max_hw_cq_size = uk_attrs->max_hw_cq_size; + uresp.min_hw_cq_size = uk_attrs->min_hw_cq_size; + uresp.hw_rev = uk_attrs->hw_rev; + uresp.comp_mask |= IRDMA_ALLOC_UCTX_USE_RAW_ATTR; + uresp.min_hw_wq_size = uk_attrs->min_hw_wq_size; + uresp.comp_mask |= IRDMA_ALLOC_UCTX_MIN_HW_WQ_SIZE; + uresp.max_hw_srq_quanta = uk_attrs->max_hw_srq_quanta; + uresp.comp_mask |= IRDMA_ALLOC_UCTX_MAX_HW_SRQ_QUANTA; + uresp.max_hw_push_len = uk_attrs->max_hw_push_len; + uresp.comp_mask |= IRDMA_SUPPORT_MAX_HW_PUSH_LEN; + + bar_off = + (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET]; + +#ifdef RDMA_MMAP_DB_SUPPORT + ucontext->db_mmap_entry = + irdma_user_mmap_entry_insert(ucontext, bar_off, + IRDMA_MMAP_IO_NC, + &uresp.db_mmap_key); + +#else + spin_lock_init(&ucontext->mmap_tbl_lock); + ucontext->db_mmap_entry = + irdma_user_mmap_entry_add_hash(ucontext, bar_off, + IRDMA_MMAP_IO_NC, + &uresp.db_mmap_key); +#endif /* RDMA_MMAP_DB_SUPPORT */ + if (!ucontext->db_mmap_entry) { +#ifndef RDMA_MMAP_DB_SUPPORT +#endif + kfree(ucontext); + return ERR_PTR(-ENOMEM); + } + + if (ib_copy_to_udata(udata, &uresp, + min(sizeof(uresp), udata->outlen))) { +#ifdef RDMA_MMAP_DB_SUPPORT + rdma_user_mmap_entry_remove(ucontext->db_mmap_entry); +#else + irdma_user_mmap_entry_del_hash(ucontext->db_mmap_entry); +#endif + kfree(ucontext); + return ERR_PTR(-EFAULT); + } + } + + INIT_LIST_HEAD(&ucontext->cq_reg_mem_list); + spin_lock_init(&ucontext->cq_reg_mem_list_lock); + INIT_LIST_HEAD(&ucontext->qp_reg_mem_list); + spin_lock_init(&ucontext->qp_reg_mem_list_lock); + INIT_LIST_HEAD(&ucontext->srq_reg_mem_list); + spin_lock_init(&ucontext->srq_reg_mem_list_lock); +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) + INIT_LIST_HEAD(&ucontext->vma_list); + mutex_init(&ucontext->vma_list_mutex); +#endif + +#ifdef CONFIG_DEBUG_FS + irdma_dbg_save_ucontext(iwdev, ucontext); +#endif + return &ucontext->ibucontext; + +ver_error: + ibdev_err(&iwdev->ibdev, + "Invalid userspace driver version detected. Detected version %d, should be %d\n", + req.userspace_ver, IRDMA_ABI_VER); + return ERR_PTR(-EINVAL); +} +#endif + +#ifdef DEALLOC_UCONTEXT_VER_2 +/** + * irdma_dealloc_ucontext - deallocate the user context data structure + * @context: user context created during alloc + */ +void irdma_dealloc_ucontext(struct ib_ucontext *context) +{ + struct irdma_ucontext *ucontext = to_ucontext(context); + +#ifdef RDMA_MMAP_DB_SUPPORT + rdma_user_mmap_entry_remove(ucontext->db_mmap_entry); +#else + irdma_user_mmap_entry_del_hash(ucontext->db_mmap_entry); +#endif +#ifdef CONFIG_DEBUG_FS + irdma_dbg_free_ucontext(ucontext); +#endif + + return; +} +#endif + +#ifdef DEALLOC_UCONTEXT_VER_1 +/** + * irdma_dealloc_ucontext - deallocate the user context data structure + * @context: user context created during alloc + */ +int irdma_dealloc_ucontext(struct ib_ucontext *context) +{ + struct irdma_ucontext *ucontext = to_ucontext(context); + +#ifdef RDMA_MMAP_DB_SUPPORT + rdma_user_mmap_entry_remove(ucontext->db_mmap_entry); +#else + irdma_user_mmap_entry_del_hash(ucontext->db_mmap_entry); +#endif +#ifdef CONFIG_DEBUG_FS + irdma_dbg_free_ucontext(ucontext); +#endif + kfree(ucontext); + + return 0; +} +#endif + +#define IRDMA_ALLOC_PD_MIN_RESP_LEN offsetofend(struct irdma_alloc_pd_resp, rsvd) +#ifdef ALLOC_PD_VER_3 +/** + * irdma_alloc_pd - allocate protection domain + * @pd: protection domain + * @udata: user data + */ +int irdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata) +{ + struct irdma_pd *iwpd = to_iwpd(pd); + struct irdma_device *iwdev = to_iwdev(pd->device); + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_alloc_pd_resp uresp = {}; + struct irdma_sc_pd *sc_pd; + u32 pd_id = 0; + int err; + + if (udata && udata->outlen < IRDMA_ALLOC_PD_MIN_RESP_LEN) + return -EINVAL; + + err = irdma_alloc_rsrc(rf, rf->allocated_pds, rf->max_pd, &pd_id, + &rf->next_pd); + if (err) + return err; + + iwpd->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + mutex_init(&iwpd->push_alloc_mutex); + + sc_pd = &iwpd->sc_pd; + if (udata) { + struct irdma_ucontext *ucontext = + rdma_udata_to_drv_context(udata, struct irdma_ucontext, + ibucontext); + + irdma_sc_pd_init(dev, sc_pd, pd_id, ucontext->abi_ver); + uresp.pd_id = pd_id; + if (ib_copy_to_udata(udata, &uresp, + min(sizeof(uresp), udata->outlen))) { + err = -EFAULT; + goto error; + } + } else { + irdma_sc_pd_init(dev, sc_pd, pd_id, IRDMA_ABI_VER); + } + + return 0; + +error: + + irdma_free_rsrc(rf, rf->allocated_pds, pd_id); + + return err; +} +#endif + +#ifdef ALLOC_PD_VER_2 +/** + * irdma_alloc_pd - allocate protection domain + * @pd: protection domain + * @context: user context + * @udata: user data + */ +int irdma_alloc_pd(struct ib_pd *pd, struct ib_ucontext *context, struct ib_udata *udata) +{ + struct irdma_pd *iwpd = to_iwpd(pd); + struct irdma_device *iwdev = to_iwdev(pd->device); + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_alloc_pd_resp uresp = {}; + struct irdma_sc_pd *sc_pd; + u32 pd_id = 0; + int err; + + if (udata && udata->outlen < IRDMA_ALLOC_PD_MIN_RESP_LEN) + return -EINVAL; + + err = irdma_alloc_rsrc(rf, rf->allocated_pds, rf->max_pd, &pd_id, + &rf->next_pd); + if (err) + return err; + + iwpd->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + mutex_init(&iwpd->push_alloc_mutex); + + sc_pd = &iwpd->sc_pd; + if (udata) { + struct irdma_ucontext *ucontext = to_ucontext(context); + + irdma_sc_pd_init(dev, sc_pd, pd_id, ucontext->abi_ver); + uresp.pd_id = pd_id; + if (ib_copy_to_udata(udata, &uresp, + min(sizeof(uresp), udata->outlen))) { + err = -EFAULT; + goto error; + } + } else { + irdma_sc_pd_init(dev, sc_pd, pd_id, IRDMA_ABI_VER); + } + + return 0; + +error: + + irdma_free_rsrc(rf, rf->allocated_pds, pd_id); + + return err; +} +#endif + +#ifdef ALLOC_PD_VER_1 +/** + * irdma_alloc_pd - allocate protection domain + * @ibdev: IB device + * @context: user context + * @udata: user data + */ +struct ib_pd *irdma_alloc_pd(struct ib_device *ibdev, struct ib_ucontext *context, struct ib_udata *udata) +{ + struct irdma_pd *iwpd; + struct irdma_device *iwdev = to_iwdev(ibdev); + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_alloc_pd_resp uresp = {}; + struct irdma_sc_pd *sc_pd; + u32 pd_id = 0; + int err; + + err = irdma_alloc_rsrc(rf, rf->allocated_pds, rf->max_pd, &pd_id, + &rf->next_pd); + if (err) + return ERR_PTR(err); + + iwpd = kzalloc(sizeof(*iwpd), GFP_KERNEL); + if (!iwpd) { + err = -ENOMEM; + goto free_res; + } + + iwpd->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + mutex_init(&iwpd->push_alloc_mutex); + + sc_pd = &iwpd->sc_pd; + if (udata) { + struct irdma_ucontext *ucontext = to_ucontext(context); + + irdma_sc_pd_init(dev, sc_pd, pd_id, ucontext->abi_ver); + uresp.pd_id = pd_id; + if (ib_copy_to_udata(udata, &uresp, + min(sizeof(uresp), udata->outlen))) { + err = -EFAULT; + goto error; + } + } else { + irdma_sc_pd_init(dev, sc_pd, pd_id, IRDMA_ABI_VER); + } + + return &iwpd->ibpd; + +error: + kfree(iwpd); +free_res: + + irdma_free_rsrc(rf, rf->allocated_pds, pd_id); + + return ERR_PTR(err); +} + +#endif + +#ifdef DEALLOC_PD_VER_4 +int irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) +{ + struct irdma_pd *iwpd = to_iwpd(ibpd); + struct irdma_device *iwdev = to_iwdev(ibpd->device); + + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_pds, iwpd->sc_pd.pd_id); + return 0; +} + +#endif + +#ifdef DEALLOC_PD_VER_3 +void irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata) +{ + struct irdma_pd *iwpd = to_iwpd(ibpd); + struct irdma_device *iwdev = to_iwdev(ibpd->device); + + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_pds, iwpd->sc_pd.pd_id); +} + +#endif + +#ifdef DEALLOC_PD_VER_2 +void irdma_dealloc_pd(struct ib_pd *ibpd) +{ + struct irdma_pd *iwpd = to_iwpd(ibpd); + struct irdma_device *iwdev = to_iwdev(ibpd->device); + + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_pds, iwpd->sc_pd.pd_id); +} +#endif + +#ifdef DEALLOC_PD_VER_1 +int irdma_dealloc_pd(struct ib_pd *ibpd) +{ + struct irdma_pd *iwpd = to_iwpd(ibpd); + struct irdma_device *iwdev = to_iwdev(ibpd->device); + + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_pds, iwpd->sc_pd.pd_id); + kfree(iwpd); + return 0; +} +#endif + +static void irdma_fill_ah_info(struct irdma_ah_info *ah_info, + const struct ib_gid_attr *sgid_attr, + union irdma_sockaddr *sgid_addr, + union irdma_sockaddr *dgid_addr, + u8 *dmac, u8 net_type) +{ + if (net_type == RDMA_NETWORK_IPV4) { + ah_info->ipv4_valid = true; + ah_info->dest_ip_addr[0] = + ntohl(dgid_addr->saddr_in.sin_addr.s_addr); + ah_info->src_ip_addr[0] = + ntohl(sgid_addr->saddr_in.sin_addr.s_addr); + ah_info->do_lpbk = irdma_ipv4_is_lpb(ah_info->src_ip_addr[0], + ah_info->dest_ip_addr[0]); + if (ipv4_is_multicast(dgid_addr->saddr_in.sin_addr.s_addr)) { + irdma_mcast_mac_v4(ah_info->dest_ip_addr, dmac); + } + } else { + irdma_copy_ip_ntohl(ah_info->dest_ip_addr, + dgid_addr->saddr_in6.sin6_addr.in6_u.u6_addr32); + irdma_copy_ip_ntohl(ah_info->src_ip_addr, + sgid_addr->saddr_in6.sin6_addr.in6_u.u6_addr32); + ah_info->do_lpbk = irdma_ipv6_is_lpb(ah_info->src_ip_addr, + ah_info->dest_ip_addr); + if (rdma_is_multicast_addr(&dgid_addr->saddr_in6.sin6_addr)) { + irdma_mcast_mac_v6(ah_info->dest_ip_addr, dmac); + } + } +} + +#ifdef SET_ROCE_CM_INFO_VER_3 +static u8 irdma_roce_get_vlan_prio(struct net_device __rcu *ndev_rcu, u8 prio) +{ + struct net_device *ndev; + + rcu_read_lock(); + ndev = rcu_dereference(ndev_rcu); + if (!ndev) + goto exit; + if (is_vlan_dev(ndev)) { + u16 vlan_qos = vlan_dev_get_egress_qos_mask(ndev, prio); + + prio = (vlan_qos & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; + } +exit: + rcu_read_unlock(); + return prio; +} +#else +static inline u8 irdma_roce_get_vlan_prio(struct net_device *ndev, u8 prio) +{ + if (ndev && is_vlan_dev(ndev)) { + u16 vprio = vlan_dev_get_egress_qos_mask(ndev, prio); + + return (vprio & VLAN_PRIO_MASK) >> VLAN_PRIO_SHIFT; + } + return prio; +} + +#endif +static int irdma_create_ah_vlan_tag(struct irdma_device *iwdev, + struct irdma_ah_info *ah_info, + const struct ib_gid_attr *sgid_attr, + u8 *dmac) +{ + u16 vlan_prio; + +#if !defined(CREATE_AH_VER_2) && !defined(CREATE_AH_VER_5) + if (sgid_attr->ndev && is_vlan_dev(sgid_attr->ndev)) + ah_info->vlan_tag = vlan_dev_vlan_id(sgid_attr->ndev); + else + ah_info->vlan_tag = VLAN_N_VID; + +#endif + ah_info->dst_arpindex = irdma_add_arp(iwdev->rf, + ah_info->dest_ip_addr, dmac); + + if (ah_info->dst_arpindex == -1) + return -EINVAL; + + if (ah_info->vlan_tag >= VLAN_N_VID && iwdev->dcb_vlan_mode) + ah_info->vlan_tag = 0; + + if (ah_info->vlan_tag < VLAN_N_VID) { + ah_info->insert_vlan_tag = true; + vlan_prio = (u16)irdma_roce_get_vlan_prio(sgid_attr->ndev, + rt_tos2priority(ah_info->tc_tos)); + ah_info->vlan_tag |= vlan_prio << VLAN_PRIO_SHIFT; + } +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + if (iwdev->roce_dcqcn_en || iwdev->roce_dctcp_en) { + ah_info->tc_tos &= ~ECN_CODE_PT_MASK; + ah_info->tc_tos |= ECN_CODE_PT_VAL; + } +#else + if (iwdev->roce_dcqcn_en) { + ah_info->tc_tos &= ~ECN_CODE_PT_MASK; + ah_info->tc_tos |= ECN_CODE_PT_VAL; + } +#endif + + return 0; +} + +static int irdma_create_ah_wait(struct irdma_pci_f *rf, + struct irdma_sc_ah *sc_ah, bool sleep) +{ + int ret; + + if (!sleep) { + int cnt = rf->sc_dev.hw_attrs.max_cqp_compl_wait_time_ms * + CQP_TIMEOUT_THRESHOLD; + struct irdma_cqp_request *cqp_request = + sc_ah->ah_info.cqp_request; + + do { + irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq); + mdelay(1); + } while (!READ_ONCE(cqp_request->request_done) && --cnt); + + if (cnt && !cqp_request->compl_info.op_ret_val) { + irdma_put_cqp_request(&rf->cqp, cqp_request); + sc_ah->ah_info.ah_valid = true; + } else { + ret = !cnt ? -ETIMEDOUT : -EINVAL; + ibdev_err(&rf->iwdev->ibdev, "CQP create AH error ret = %d opt_ret_val = %d", + ret, cqp_request->compl_info.op_ret_val); + irdma_put_cqp_request(&rf->cqp, cqp_request); + if (!cnt && !rf->reset) { + rf->reset = true; + rf->gen_ops.request_reset(rf); + } + return ret; + } + } + + return 0; +} + +#ifndef CREATE_AH_VER_0 +static bool irdma_ah_exists(struct irdma_device *iwdev, + struct irdma_ah *new_ah) +{ + struct irdma_ah *ah; + u32 save_ah_id = new_ah->sc_ah.ah_info.ah_idx; + u32 key = new_ah->sc_ah.ah_info.dest_ip_addr[0] ^ + new_ah->sc_ah.ah_info.dest_ip_addr[1] ^ + new_ah->sc_ah.ah_info.dest_ip_addr[2] ^ + new_ah->sc_ah.ah_info.dest_ip_addr[3]; + + hash_for_each_possible(iwdev->ah_hash_tbl, ah, list, key) { + /* Set ah_id the same so memcp can work */ + new_ah->sc_ah.ah_info.ah_idx = ah->sc_ah.ah_info.ah_idx; + if (!memcmp(&ah->sc_ah.ah_info, &new_ah->sc_ah.ah_info, + sizeof(ah->sc_ah.ah_info))) { + refcount_inc(&ah->refcnt); + new_ah->parent_ah = ah; + return true; + } + } + new_ah->sc_ah.ah_info.ah_idx = save_ah_id; + /* Add new AH to list */ + ah = kmemdup(new_ah, sizeof(*new_ah), GFP_KERNEL); + if (!ah) + return false; + new_ah->parent_ah = ah; + hash_add(iwdev->ah_hash_tbl, &ah->list, key); + + iwdev->ah_list_cnt++; + if (iwdev->ah_list_cnt > iwdev->ah_list_hwm) + iwdev->ah_list_hwm = iwdev->ah_list_cnt; + refcount_set(&ah->refcnt, 1); + + return false; +} +#endif + +#define IRDMA_CREATE_AH_MIN_RESP_LEN offsetofend(struct irdma_create_ah_resp, rsvd) +#if defined(CREATE_AH_VER_3) || defined(CREATE_AH_VER_4) +/** + * irdma_create_ah_sleepable - create address handle + * @ibpd: Protection Domain for AH + * @attr: address handle attributes + * @sleep: wait for creation + * @udata: user data + * + * returns a pointer to an address handle + */ +static struct ib_ah *irdma_create_ah_sleepable(struct ib_pd *ibpd, + struct rdma_ah_attr *attr, + bool sleep, + struct ib_udata *udata) +{ + struct irdma_pd *pd = to_iwpd(ibpd); + struct irdma_device *iwdev = to_iwdev(ibpd->device); + struct irdma_ah *ah; + const struct ib_gid_attr *sgid_attr; + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_sc_ah *sc_ah; + u32 ah_id = 0; + struct irdma_ah_info *ah_info; + struct irdma_create_ah_resp uresp = {}; + union irdma_sockaddr sgid_addr, dgid_addr; + int err; + u8 dmac[ETH_ALEN]; + + if (udata && udata->outlen < IRDMA_CREATE_AH_MIN_RESP_LEN) + return ERR_PTR(-EINVAL); + + err = irdma_alloc_rsrc(rf, rf->allocated_ahs, + rf->max_ah, &ah_id, &rf->next_ah); + if (err) + return ERR_PTR(err); + + ah = kzalloc(sizeof(*ah), GFP_ATOMIC); + if (!ah) { + irdma_free_rsrc(rf, rf->allocated_ahs, ah_id); + return ERR_PTR(-ENOMEM); + } + + ah->pd = pd; + sc_ah = &ah->sc_ah; + sc_ah->ah_info.ah_idx = ah_id; + sc_ah->ah_info.vsi = &iwdev->vsi; + irdma_sc_init_ah(&rf->sc_dev, sc_ah); + ah->sgid_index = attr->grh.sgid_index; + memcpy(&ah->dgid, &attr->grh.dgid, sizeof(ah->dgid)); + sgid_attr = attr->grh.sgid_attr; + rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid_attr->gid); + rdma_gid2ip((struct sockaddr *)&dgid_addr, &attr->grh.dgid); + ah->av.attrs = *attr; + ah->av.net_type = kc_rdma_gid_attr_network_type(sgid_attr, + sgid_attr.gid_type, + &sgid); + ah_info = &sc_ah->ah_info; + ah_info->ah_idx = ah_id; + ah_info->pd_idx = pd->sc_pd.pd_id; + ether_addr_copy(ah_info->mac_addr, iwdev->netdev->dev_addr); + if (attr->ah_flags & IB_AH_GRH) { + ah_info->flow_label = attr->grh.flow_label; + ah_info->hop_ttl = attr->grh.hop_limit; + ah_info->tc_tos = attr->grh.traffic_class; + } + ether_addr_copy(dmac, attr->roce.dmac); + + irdma_fill_ah_info(ah_info, sgid_attr, &sgid_addr, &dgid_addr, + dmac, ah->av.net_type); + err = irdma_create_ah_vlan_tag(iwdev, ah_info, sgid_attr, dmac); + if (err) + goto err_gid_l2; + + if (sleep) { + mutex_lock(&iwdev->ah_tbl_lock); + if (irdma_ah_exists(iwdev, ah)) { + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, + ah_id); + ah_id = 0; +#ifdef CONFIG_DEBUG_FS + iwdev->ah_reused++; +#endif + goto exit; + } + } + + err = irdma_ah_cqp_op(iwdev->rf, sc_ah, IRDMA_OP_AH_CREATE, + sleep, NULL, sc_ah); + if (err) { + ibdev_dbg(&iwdev->ibdev, "CQP-OP Create AH fail"); + goto err_ah_create; + } + + err = irdma_create_ah_wait(rf, sc_ah, sleep); + if (err) + goto err_gid_l2; + +exit: + if (udata) { + uresp.ah_id = ah->sc_ah.ah_info.ah_idx; + err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), udata->outlen)); + if (err) { + if (!ah->parent_ah || + (ah->parent_ah && refcount_dec_and_test(&ah->parent_ah->refcnt))) { + irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, + IRDMA_OP_AH_DESTROY, false, NULL, ah); + ah_id = ah->sc_ah.ah_info.ah_idx; + goto err_ah_create; + } + goto err_unlock; + } + } + if (sleep) + mutex_unlock(&iwdev->ah_tbl_lock); + + return &ah->ibah; + +err_ah_create: + if (ah->parent_ah) { + hash_del(&ah->parent_ah->list); + kfree(ah->parent_ah); + iwdev->ah_list_cnt--; + } +err_unlock: + if (sleep) + mutex_unlock(&iwdev->ah_tbl_lock); +err_gid_l2: + kfree(ah); + if (ah_id) + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah_id); + + return ERR_PTR(err); +} +#endif + +#ifdef CREATE_AH_VER_3 +/** + * irdma_create_ah - create address handle + * @ibpd: Protection Domain for AH + * @attr: address handle attributes + * @flags: AH flags to wait + * @udata: user data + * + * returns a pointer to an address handle + */ +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, + struct rdma_ah_attr *attr, + u32 flags, + struct ib_udata *udata) +{ + bool sleep = (flags & RDMA_CREATE_AH_SLEEPABLE) != 0; + + return irdma_create_ah_sleepable(ibpd, attr, sleep, udata); +} +#endif +#ifdef CREATE_AH_VER_4 +/** + * irdma_create_ah - create address handle + * @ibpd: ptr to pd + * @attr: address handle attributes + * @udata: user data + * + * returns a pointer to an address handle + */ +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, + struct rdma_ah_attr *attr, + struct ib_udata *udata) +{ + bool sleep = udata ? true : false; + + return irdma_create_ah_sleepable(ibpd, attr, sleep, udata); +} +#endif + +#ifdef CREATE_AH_VER_2 +/** + * irdma_create_ah - create address handle + * @ib_ah: ptr to AH + * @attr: address handle attributes + * @flags: AH flags to wait + * @udata: user data + * + * returns 0 on success, error otherwise + */ +int irdma_create_ah(struct ib_ah *ib_ah, + struct rdma_ah_attr *attr, u32 flags, + struct ib_udata *udata) +#elif defined(CREATE_AH_VER_5) +int irdma_create_ah_v2(struct ib_ah *ib_ah, + struct rdma_ah_attr *attr, u32 flags, + struct ib_udata *udata) +#endif +#if defined(CREATE_AH_VER_2) || defined(CREATE_AH_VER_5) +{ + struct irdma_pd *pd = to_iwpd(ib_ah->pd); + struct irdma_ah *ah = container_of(ib_ah, struct irdma_ah, ibah); + struct irdma_device *iwdev = to_iwdev(ib_ah->pd->device); + const struct ib_gid_attr *sgid_attr; + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_sc_ah *sc_ah; + u32 ah_id = 0; + struct irdma_ah_info *ah_info; + struct irdma_create_ah_resp uresp = {}; + union irdma_sockaddr sgid_addr, dgid_addr; + int err; + u8 dmac[ETH_ALEN]; + bool sleep = (flags & RDMA_CREATE_AH_SLEEPABLE) != 0; + + if (udata && udata->outlen < IRDMA_CREATE_AH_MIN_RESP_LEN) + return -EINVAL; + + err = irdma_alloc_rsrc(rf, rf->allocated_ahs, + rf->max_ah, &ah_id, &rf->next_ah); + + if (err) + return err; + + ah->pd = pd; + sc_ah = &ah->sc_ah; + sc_ah->ah_info.ah_idx = ah_id; + sc_ah->ah_info.vsi = &iwdev->vsi; + irdma_sc_init_ah(&rf->sc_dev, sc_ah); + ah->sgid_index = attr->grh.sgid_index; + memcpy(&ah->dgid, &attr->grh.dgid, sizeof(ah->dgid)); + sgid_attr = attr->grh.sgid_attr; + + rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid_attr->gid); + rdma_gid2ip((struct sockaddr *)&dgid_addr, &attr->grh.dgid); + ah->av.attrs = *attr; + ah->av.net_type = kc_rdma_gid_attr_network_type(sgid_attr, + sgid_attr.gid_type, + &sgid); + + ah_info = &sc_ah->ah_info; + ah_info->ah_idx = ah_id; + ah_info->pd_idx = pd->sc_pd.pd_id; + err = rdma_read_gid_l2_fields(sgid_attr, &ah_info->vlan_tag, + ah_info->mac_addr); + + if (err) + goto err_gid_l2; + + if (attr->ah_flags & IB_AH_GRH) { + ah_info->flow_label = attr->grh.flow_label; + ah_info->hop_ttl = attr->grh.hop_limit; + ah_info->tc_tos = attr->grh.traffic_class; + } + + ether_addr_copy(dmac, attr->roce.dmac); + + irdma_fill_ah_info(ah_info, sgid_attr, &sgid_addr, &dgid_addr, + dmac, ah->av.net_type); + + err = irdma_create_ah_vlan_tag(iwdev, ah_info, sgid_attr, dmac); + if (err) + goto err_gid_l2; + + if (sleep) { + mutex_lock(&iwdev->ah_tbl_lock); + if (irdma_ah_exists(iwdev, ah)) { + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah_id); + ah_id = 0; +#ifdef CONFIG_DEBUG_FS + iwdev->ah_reused++; +#endif + goto exit; + } + } + + err = irdma_ah_cqp_op(iwdev->rf, sc_ah, IRDMA_OP_AH_CREATE, + sleep, NULL, sc_ah); + if (err) { + ibdev_dbg(&iwdev->ibdev, "CQP-OP Create AH fail"); + goto err_ah_create; + } + + err = irdma_create_ah_wait(rf, sc_ah, sleep); + if (err) + goto err_gid_l2; + +exit: + if (udata) { + uresp.ah_id = ah->sc_ah.ah_info.ah_idx; + err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), udata->outlen)); + if (err) { + if (!ah->parent_ah || + (ah->parent_ah && refcount_dec_and_test(&ah->parent_ah->refcnt))) { + irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, + IRDMA_OP_AH_DESTROY, false, NULL, ah); + ah_id = ah->sc_ah.ah_info.ah_idx; + goto err_ah_create; + } + goto err_unlock; + } + } + if (sleep) + mutex_unlock(&iwdev->ah_tbl_lock); + return 0; +err_ah_create: + if (ah->parent_ah) { + hash_del(&ah->parent_ah->list); + kfree(ah->parent_ah); + iwdev->ah_list_cnt--; + } +err_unlock: + if (sleep) + mutex_unlock(&iwdev->ah_tbl_lock); +err_gid_l2: + if (ah_id) + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah_id); + + return err; +} +#endif + +#ifdef CREATE_AH_VER_6 +/** + * irdma_create_ah - create address handle + * @ib_ah: ptr to AH + * @attr: address handle attributes + * @flags: AH flags to wait + * @udata: user data + * + * returns 0 on success, error otherwise + */ +int irdma_create_ah(struct ib_ah *ib_ah, + struct ib_ah_attr *attr, u32 flags, + struct ib_udata *udata) +{ + struct irdma_pd *pd = to_iwpd(ib_ah->pd); + struct irdma_ah *ah = container_of(ib_ah, struct irdma_ah, ibah); + struct irdma_device *iwdev = to_iwdev(ib_ah->pd->device); + union ib_gid sgid; + struct ib_gid_attr sgid_attr; + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_sc_ah *sc_ah; + u32 ah_id = 0; + struct irdma_ah_info *ah_info; + struct irdma_create_ah_resp uresp = {}; + union irdma_sockaddr sgid_addr, dgid_addr; + int err; + u8 dmac[ETH_ALEN]; + bool sleep = (flags & RDMA_CREATE_AH_SLEEPABLE) != 0; + + if (udata && udata->outlen < IRDMA_CREATE_AH_MIN_RESP_LEN) + return -EINVAL; + + err = irdma_alloc_rsrc(rf, rf->allocated_ahs, + rf->max_ah, &ah_id, &rf->next_ah); + + if (err) + return err; + + ah->pd = pd; + sc_ah = &ah->sc_ah; + sc_ah->ah_info.ah_idx = ah_id; + sc_ah->ah_info.vsi = &iwdev->vsi; + irdma_sc_init_ah(&rf->sc_dev, sc_ah); + ah->sgid_index = attr->grh.sgid_index; + memcpy(&ah->dgid, &attr->grh.dgid, sizeof(ah->dgid)); + rcu_read_lock(); + err = ib_get_cached_gid(&iwdev->ibdev, attr->port_num, + attr->grh.sgid_index, &sgid, &sgid_attr); + rcu_read_unlock(); + if (err) { + ibdev_dbg(&iwdev->ibdev, + "VERBS: GID lookup at idx=%d with port=%d failed\n", + attr->grh.sgid_index, attr->port_num); + err = -EINVAL; + goto err_gid_l2; + } + rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid); + rdma_gid2ip((struct sockaddr *)&dgid_addr, &attr->grh.dgid); + ah->av.attrs = *attr; + ah->av.net_type = kc_rdma_gid_attr_network_type(sgid_attr, + sgid_attr.gid_type, + &sgid); + + if (kc_deref_sgid_attr(sgid_attr)) + dev_put(kc_deref_sgid_attr(sgid_attr)); + + ah_info = &sc_ah->ah_info; + ah_info->ah_idx = ah_id; + ah_info->pd_idx = pd->sc_pd.pd_id; + ether_addr_copy(ah_info->mac_addr, iwdev->netdev->dev_addr); + + if (attr->ah_flags & IB_AH_GRH) { + ah_info->flow_label = attr->grh.flow_label; + ah_info->hop_ttl = attr->grh.hop_limit; + ah_info->tc_tos = attr->grh.traffic_class; + } + + ether_addr_copy(dmac, attr->dmac); + + irdma_fill_ah_info(ah_info, &sgid_attr, &sgid_addr, &dgid_addr, + dmac, ah->av.net_type); + + err = irdma_create_ah_vlan_tag(iwdev, ah_info, &sgid_attr, dmac); + if (err) + goto err_gid_l2; + + if (sleep) { + mutex_lock(&iwdev->ah_tbl_lock); + if (irdma_ah_exists(iwdev, ah)) { + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah_id); + ah_id = 0; +#ifdef CONFIG_DEBUG_FS + iwdev->ah_reused++; +#endif + goto exit; + } + } + + err = irdma_ah_cqp_op(iwdev->rf, sc_ah, IRDMA_OP_AH_CREATE, + sleep, NULL, sc_ah); + if (err) { + ibdev_dbg(&iwdev->ibdev, "CQP-OP Create AH fail"); + goto err_ah_create; + } + + err = irdma_create_ah_wait(rf, sc_ah, sleep); + if (err) + goto err_gid_l2; + +exit: + if (udata) { + uresp.ah_id = ah->sc_ah.ah_info.ah_idx; + err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), udata->outlen)); + if (err) { + if (!ah->parent_ah || + (ah->parent_ah && refcount_dec_and_test(&ah->parent_ah->refcnt))) { + irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, + IRDMA_OP_AH_DESTROY, false, NULL, ah); + ah_id = ah->sc_ah.ah_info.ah_idx; + goto err_ah_create; + } + goto err_unlock; + } + } + if (sleep) + mutex_unlock(&iwdev->ah_tbl_lock); + + return 0; +err_ah_create: + if (ah->parent_ah) { + hash_del(&ah->parent_ah->list); + kfree(ah->parent_ah); + iwdev->ah_list_cnt--; + } +err_unlock: + if (sleep) + mutex_unlock(&iwdev->ah_tbl_lock); +err_gid_l2: + if (ah_id) + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah_id); + + return err; +} +#endif /* CREATE_AH_VER_6 */ + +#ifdef CREATE_AH_VER_5 +/** + * irdma_create_ah - create address handle + * @ibah: ptr to AH + * @init_attr: address handle attributes + * @udata: user data + * + * returns a pointer to an address handle + */ +int irdma_create_ah(struct ib_ah *ibah, + struct rdma_ah_init_attr *init_attr, + struct ib_udata *udata) +{ + return irdma_create_ah_v2(ibah, init_attr->ah_attr, init_attr->flags, udata); +} +#endif + +#if defined(ETHER_COPY_VER_1) +void irdma_ether_copy(u8 *dmac, struct ib_ah_attr *attr) +{ + ether_addr_copy(dmac, attr->dmac); +} +#endif + +#if defined(ETHER_COPY_VER_2) +void irdma_ether_copy(u8 *dmac, struct rdma_ah_attr *attr) +{ + ether_addr_copy(dmac, attr->roce.dmac); +} +#endif + +#ifdef IB_IW_MANDATORY_AH_OP +#ifdef CREATE_AH_VER_0 +struct ib_ah *irdma_create_ah_stub(struct ib_pd *ibpd, + struct ib_ah_attr *attr) +#elif defined(CREATE_AH_VER_1_1) +struct ib_ah *irdma_create_ah_stub(struct ib_pd *ibpd, + struct ib_ah_attr *attr, + struct ib_udata *udata) +#elif defined(CREATE_AH_VER_1_2) +struct ib_ah *irdma_create_ah_stub(struct ib_pd *ibpd, + struct rdma_ah_attr *attr, + struct ib_udata *udata) +#elif defined(CREATE_AH_VER_6) +int irdma_create_ah_stub(struct ib_ah *ib_ah, + struct ib_ah_attr *attr, u32 flags, + struct ib_udata *udata) +#endif +{ +#ifdef CREATE_AH_VER_6 + return -ENOSYS; +#else + return ERR_PTR(-ENOSYS); +#endif +} + +#ifdef DESTROY_AH_VER_3 +void irdma_destroy_ah_stub(struct ib_ah *ibah, u32 flags) +{ + return; +} +#else +int irdma_destroy_ah_stub(struct ib_ah *ibah) +{ + return -ENOSYS; +} +#endif + +#endif /* IB_IW_MANDATORY_AH_OP */ +#ifdef CREATE_AH_VER_1_1 +/** + * irdma_create_ah - create address handle + * @ibpd: ptr to pd + * @attr: address handle attributes + * @udata: user data + * + * returns a pointer to an address handle + */ +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, + struct ib_ah_attr *attr, + struct ib_udata *udata) +#elif defined(CREATE_AH_VER_1_2) +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, + struct rdma_ah_attr *attr, + struct ib_udata *udata) +#endif +#if defined(CREATE_AH_VER_1_1) || defined(CREATE_AH_VER_1_2) +{ + struct irdma_pd *pd = to_iwpd(ibpd); + struct irdma_device *iwdev = to_iwdev(ibpd->device); + struct irdma_ah *ah; +#ifdef IB_GET_CACHED_GID + union ib_gid sgid; + struct ib_gid_attr sgid_attr; +#else + const struct ib_gid_attr *sgid_attr; +#endif + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_sc_ah *sc_ah; + u32 ah_id = 0; + struct irdma_ah_info *ah_info; + struct irdma_create_ah_resp uresp = {}; + union irdma_sockaddr sgid_addr, dgid_addr; + int err; + u8 dmac[ETH_ALEN]; + bool sleep = udata ? true : false; + + if (udata && udata->outlen < IRDMA_CREATE_AH_MIN_RESP_LEN) + return ERR_PTR(-EINVAL); + + err = irdma_alloc_rsrc(rf, rf->allocated_ahs, + rf->max_ah, &ah_id, &rf->next_ah); + + if (err) + return ERR_PTR(err); + + ah = kzalloc(sizeof(*ah), GFP_ATOMIC); + if (!ah) { + irdma_free_rsrc(rf, rf->allocated_ahs, ah_id); + return ERR_PTR(-ENOMEM); + } + + ah->pd = pd; + sc_ah = &ah->sc_ah; + sc_ah->ah_info.ah_idx = ah_id; + sc_ah->ah_info.vsi = &iwdev->vsi; + irdma_sc_init_ah(&rf->sc_dev, sc_ah); + ah->sgid_index = attr->grh.sgid_index; + memcpy(&ah->dgid, &attr->grh.dgid, sizeof(ah->dgid)); +#ifdef IB_GET_CACHED_GID + rcu_read_lock(); + err = ib_get_cached_gid(&iwdev->ibdev, attr->port_num, + attr->grh.sgid_index, &sgid, &sgid_attr); + rcu_read_unlock(); + if (err) { + ibdev_dbg(&iwdev->ibdev, + "GID lookup at idx=%d with port=%d failed\n", + attr->grh.sgid_index, attr->port_num); + err = -EINVAL; + goto err_gid_l2; + } + rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid); +#else + sgid_attr = attr->grh.sgid_attr; + rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid_attr->gid); +#endif + rdma_gid2ip((struct sockaddr *)&dgid_addr, &attr->grh.dgid); + ah->av.attrs = *attr; + ah->av.net_type = kc_rdma_gid_attr_network_type(sgid_attr, + sgid_attr.gid_type, + &sgid); + +#ifdef IB_GET_CACHED_GID + if (kc_deref_sgid_attr(sgid_attr)) + dev_put(kc_deref_sgid_attr(sgid_attr)); +#endif + + ah_info = &sc_ah->ah_info; + ah_info->ah_idx = ah_id; + ah_info->pd_idx = pd->sc_pd.pd_id; + + ether_addr_copy(ah_info->mac_addr, iwdev->netdev->dev_addr); + if (attr->ah_flags & IB_AH_GRH) { + ah_info->flow_label = attr->grh.flow_label; + ah_info->hop_ttl = attr->grh.hop_limit; + ah_info->tc_tos = attr->grh.traffic_class; + } + +#if defined(HPM_FBSD) || defined(IB_RESOLVE_ETH_DMAC) + if (udata) { + err = ib_resolve_eth_dmac(ibpd->device, attr); + if (err) + goto err_gid_l2; + } +#endif + irdma_ether_copy(dmac, attr); + +#ifdef IB_GET_CACHED_GID + irdma_fill_ah_info(ah_info, &sgid_attr, &sgid_addr, &dgid_addr, + dmac, ah->av.net_type); + + err = irdma_create_ah_vlan_tag(iwdev, ah_info, &sgid_attr, dmac); +#else /* IB_GET_CACHED_GID */ + irdma_fill_ah_info(ah_info, sgid_attr, &sgid_addr, &dgid_addr, + dmac, ah->av.net_type); + + err = irdma_create_ah_vlan_tag(iwdev, ah_info, sgid_attr, dmac); +#endif /* IB_GET_CACHED_GID */ + if (err) + goto err_gid_l2; + + if (sleep) { + mutex_lock(&iwdev->ah_tbl_lock); + if (irdma_ah_exists(iwdev, ah)) { + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah_id); + ah_id = 0; + #ifdef CONFIG_DEBUG_FS + iwdev->ah_reused++; + #endif + goto exit; + } + } + + err = irdma_ah_cqp_op(iwdev->rf, sc_ah, IRDMA_OP_AH_CREATE, + sleep, NULL, sc_ah); + if (err) { + ibdev_dbg(&iwdev->ibdev, "VERBS: CQP-OP Create AH fail"); + goto err_ah_create; + } + + err = irdma_create_ah_wait(rf, sc_ah, sleep); + if (err) + goto err_gid_l2; + +exit: + if (udata) { + uresp.ah_id = ah->sc_ah.ah_info.ah_idx; + err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), udata->outlen)); + if (err) { + if (!ah->parent_ah || + (ah->parent_ah && refcount_dec_and_test(&ah->parent_ah->refcnt))) { + irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, + IRDMA_OP_AH_DESTROY, false, NULL, ah); + ah_id = ah->sc_ah.ah_info.ah_idx; + goto err_ah_create; + } + goto err_unlock; + } + } + if (sleep) + mutex_unlock(&iwdev->ah_tbl_lock); + + return &ah->ibah; +err_ah_create: + if (ah->parent_ah) { + hash_del(&ah->parent_ah->list); + kfree(ah->parent_ah); + iwdev->ah_list_cnt--; + } +err_unlock: + if (sleep) + mutex_unlock(&iwdev->ah_tbl_lock); +err_gid_l2: + kfree(ah); + if (ah_id) + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah_id); + + return ERR_PTR(err); +} +#endif + +#ifdef CREATE_AH_VER_0 +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, struct ib_ah_attr *attr) +{ + struct irdma_pd *pd = to_iwpd(ibpd); + struct irdma_device *iwdev = to_iwdev(ibpd->device); + struct irdma_ah *ah; + struct irdma_pci_f *rf = iwdev->rf; + union ib_gid sgid; + struct ib_gid_attr sgid_attr; + struct irdma_sc_ah *sc_ah; + u32 ah_id; + struct irdma_ah_info *ah_info; + union irdma_sockaddr sgid_addr, dgid_addr; + int err; + u8 dmac[ETH_ALEN]; + + err = irdma_alloc_rsrc(rf, rf->allocated_ahs, + rf->max_ah, &ah_id, &rf->next_ah); + + if (err) + return ERR_PTR(err); + + ah = kzalloc(sizeof(*ah), GFP_ATOMIC); + if (!ah) { + irdma_free_rsrc(rf, rf->allocated_ahs, ah_id); + return ERR_PTR(-ENOMEM); + } + + ah->pd = pd; + sc_ah = &ah->sc_ah; + sc_ah->ah_info.ah_idx = ah_id; + sc_ah->ah_info.vsi = &iwdev->vsi; + irdma_sc_init_ah(&rf->sc_dev, sc_ah); + ah->sgid_index = attr->grh.sgid_index; + memcpy(&ah->dgid, &attr->grh.dgid, sizeof(ah->dgid)); + rcu_read_lock(); + + err = ib_get_cached_gid(&iwdev->ibdev, attr->port_num, + attr->grh.sgid_index, &sgid, &sgid_attr); + rcu_read_unlock(); + if (err) { + ibdev_dbg(&iwdev->ibdev, + "VERBS: GID lookup at idx=%d with port=%d failed\n", + attr->grh.sgid_index, attr->port_num); + err = -EINVAL; + goto error; + } + rdma_gid2ip((struct sockaddr *)&sgid_addr, &sgid); + rdma_gid2ip((struct sockaddr *)&dgid_addr, &attr->grh.dgid); + ah->av.attrs = *attr; + ah->av.net_type = kc_rdma_gid_attr_network_type(sgid_attr, + sgid_attr.gid_type, + &sgid); + if (kc_deref_sgid_attr(sgid_attr)) + dev_put(kc_deref_sgid_attr(sgid_attr)); + + ah_info = &sc_ah->ah_info; + ah_info->ah_idx = ah_id; + ah_info->pd_idx = pd->sc_pd.pd_id; + + ether_addr_copy(ah_info->mac_addr, iwdev->netdev->dev_addr); + if (attr->ah_flags & IB_AH_GRH) { + ah_info->flow_label = attr->grh.flow_label; + ah_info->hop_ttl = attr->grh.hop_limit; + ah_info->tc_tos = attr->grh.traffic_class; + } + + irdma_ether_copy(dmac, attr); + + irdma_fill_ah_info(ah_info, &sgid_attr, &sgid_addr, &dgid_addr, + dmac, ah->av.net_type); + + err = irdma_create_ah_vlan_tag(iwdev, ah_info, &sgid_attr, dmac); + if (err) + goto error; + + err = irdma_ah_cqp_op(iwdev->rf, sc_ah, IRDMA_OP_AH_CREATE, + false, NULL, sc_ah); + if (err) { + ibdev_dbg(&iwdev->ibdev, + "VERBS: CQP-OP Create AH fail"); + goto error; + } + + err = irdma_create_ah_wait(rf, sc_ah, false); + if (err) + goto error; + + return &ah->ibah; +error: + kfree(ah); + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, ah_id); + return ERR_PTR(err); +} + +#endif +#ifdef CREATE_QP_VER_2 +/** + * irdma_free_qp_rsrc - free up memory resources for qp + * @iwqp: qp ptr (user or kernel) + */ +void irdma_free_qp_rsrc(struct irdma_qp *iwqp) +{ + struct irdma_device *iwdev = iwqp->iwdev; + struct irdma_pci_f *rf = iwdev->rf; + u32 qp_num = iwqp->ibqp.qp_num; + + irdma_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp); + irdma_dealloc_push_page(rf, iwqp); + if (iwqp->sc_qp.vsi) { + irdma_qp_rem_qos(&iwqp->sc_qp); + iwqp->sc_qp.dev->ws_remove(iwqp->sc_qp.vsi, + iwqp->sc_qp.user_pri); + } + + if (qp_num > 2) + irdma_free_rsrc(rf, rf->allocated_qps, qp_num); + dma_free_coherent(rf->sc_dev.hw->device, iwqp->q2_ctx_mem.size, + iwqp->q2_ctx_mem.va, iwqp->q2_ctx_mem.pa); + iwqp->q2_ctx_mem.va = NULL; + dma_free_coherent(rf->sc_dev.hw->device, iwqp->kqp.dma_mem.size, + iwqp->kqp.dma_mem.va, iwqp->kqp.dma_mem.pa); + iwqp->kqp.dma_mem.va = NULL; + kfree(iwqp->kqp.sq_wrid_mem); + kfree(iwqp->kqp.rq_wrid_mem); + kfree(iwqp->sg_list); +} + +/** + * irdma_create_qp - create qp + * @ibqp: ptr of qp + * @init_attr: attributes for qp + * @udata: user data for create qp + */ +int irdma_create_qp(struct ib_qp *ibqp, + struct ib_qp_init_attr *init_attr, + struct ib_udata *udata) +{ +#define IRDMA_CREATE_QP_MIN_REQ_LEN offsetofend(struct irdma_create_qp_req, user_compl_ctx) +#define IRDMA_CREATE_QP_MIN_RESP_LEN offsetofend(struct irdma_create_qp_resp, rsvd) + struct ib_pd *ibpd = ibqp->pd; + struct irdma_pd *iwpd = to_iwpd(ibpd); + struct irdma_device *iwdev = to_iwdev(ibpd->device); + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_qp *iwqp = to_iwqp(ibqp); + struct irdma_create_qp_resp uresp = {}; + u32 qp_num = 0; + u32 next_qp; + int ret; + int err_code; + struct irdma_sc_qp *qp; + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs; + struct irdma_qp_init_info init_info = {}; + struct irdma_qp_host_ctx_info *ctx_info; + struct irdma_srq *iwsrq; + bool srq_valid = false; + u32 srq_id = 0; + + if (init_attr->srq) { + iwsrq = to_iwsrq(init_attr->srq); + srq_valid = true; + srq_id = iwsrq->srq_num; + init_attr->cap.max_recv_sge = uk_attrs->max_hw_wq_frags; + init_attr->cap.max_recv_wr = 4; + init_info.qp_uk_init_info.srq_uk = &iwsrq->sc_srq.srq_uk; + } + err_code = irdma_validate_qp_attrs(init_attr, iwdev); + if (err_code) + return err_code; + + if (udata && (udata->inlen < IRDMA_CREATE_QP_MIN_REQ_LEN || + udata->outlen < IRDMA_CREATE_QP_MIN_RESP_LEN)) + return -EINVAL; + + init_info.vsi = &iwdev->vsi; + init_info.qp_uk_init_info.uk_attrs = uk_attrs; + init_info.qp_uk_init_info.sq_size = init_attr->cap.max_send_wr; + init_info.qp_uk_init_info.rq_size = init_attr->cap.max_recv_wr; + init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge; + init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge; + init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data; + + iwqp->sg_list = kcalloc(uk_attrs->max_hw_wq_frags, sizeof(*iwqp->sg_list), + GFP_KERNEL); + if (!iwqp->sg_list) + return -ENOMEM; + + qp = &iwqp->sc_qp; + qp->qp_uk.back_qp = iwqp; + qp->qp_uk.lock = &iwqp->lock; + qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + + iwqp->iwdev = iwdev; + iwqp->q2_ctx_mem.size = ALIGN(IRDMA_Q2_BUF_SIZE + IRDMA_QP_CTX_SIZE, + 256); + iwqp->q2_ctx_mem.va = dma_alloc_coherent(dev->hw->device, + iwqp->q2_ctx_mem.size, + &iwqp->q2_ctx_mem.pa, + GFP_KERNEL); + if (!iwqp->q2_ctx_mem.va) { + kfree(iwqp->sg_list); + return -ENOMEM; + } + + init_info.q2 = iwqp->q2_ctx_mem.va; + init_info.q2_pa = iwqp->q2_ctx_mem.pa; + init_info.host_ctx = (__le64 *)(init_info.q2 + IRDMA_Q2_BUF_SIZE); + init_info.host_ctx_pa = init_info.q2_pa + IRDMA_Q2_BUF_SIZE; + + if (init_attr->qp_type == IB_QPT_GSI) { + qp_num = 1; + } else { + get_random_bytes(&next_qp, sizeof(next_qp)); + next_qp %= rf->max_qp; + err_code = irdma_alloc_rsrc(rf, rf->allocated_qps, rf->max_qp, + &qp_num, &next_qp); + } + if (err_code) + goto error; + + iwqp->iwpd = iwpd; + iwqp->ibqp.qp_num = qp_num; + qp = &iwqp->sc_qp; + iwqp->iwscq = to_iwcq(init_attr->send_cq); + iwqp->iwrcq = to_iwcq(init_attr->recv_cq); + iwqp->host_ctx.va = init_info.host_ctx; + iwqp->host_ctx.pa = init_info.host_ctx_pa; + iwqp->host_ctx.size = IRDMA_QP_CTX_SIZE; + + init_info.pd = &iwpd->sc_pd; + init_info.qp_uk_init_info.qp_id = qp_num; + if (!rdma_protocol_roce(&iwdev->ibdev, 1)) + init_info.qp_uk_init_info.first_sq_wq = 1; + iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp; + init_waitqueue_head(&iwqp->waitq); + init_waitqueue_head(&iwqp->mod_qp_waitq); + + if (udata) { + init_info.qp_uk_init_info.abi_ver = iwpd->sc_pd.abi_ver; + err_code = irdma_setup_umode_qp(udata, iwdev, iwqp, &init_info, init_attr); + } else { + if (uk_attrs->hw_rev <= IRDMA_GEN_2) + INIT_DELAYED_WORK(&iwqp->dwork_flush, irdma_flush_worker); + init_info.qp_uk_init_info.abi_ver = IRDMA_ABI_VER; + err_code = irdma_setup_kmode_qp(iwdev, iwqp, &init_info, init_attr); + } + + if (err_code) { + ibdev_dbg(&iwdev->ibdev, "setup qp failed\n"); + goto error; + } + + if (rdma_protocol_roce(&iwdev->ibdev, 1)) { + if (init_attr->qp_type == IB_QPT_RC) { + init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_RC; + init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM | + IRDMA_WRITE_WITH_IMM | + IRDMA_ROCE; + } else { + init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_UD; + init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM | + IRDMA_ROCE; + } + } else { + init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_IWARP; + init_info.qp_uk_init_info.qp_caps = IRDMA_WRITE_WITH_IMM; + } + +#ifndef __OFED_4_8__ + if (dev->hw_attrs.uk_attrs.hw_rev > IRDMA_GEN_1) + init_info.qp_uk_init_info.qp_caps |= IRDMA_PUSH_MODE; + +#endif + ret = irdma_sc_qp_init(qp, &init_info); + if (ret) { + err_code = -EPROTO; + ibdev_dbg(&iwdev->ibdev, "qp_init fail\n"); + goto error; + } + + ctx_info = &iwqp->ctx_info; + ctx_info->srq_valid = srq_valid; + ctx_info->srq_id = srq_id; + ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id; + ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id; + + if (rdma_protocol_roce(&iwdev->ibdev, 1)) + irdma_roce_fill_and_set_qpctx_info(iwqp, ctx_info); + else + irdma_iw_fill_and_set_qpctx_info(iwqp, ctx_info); + + err_code = irdma_cqp_create_qp_cmd(iwqp); + if (err_code) + goto error; + + refcount_set(&iwqp->refcnt, 1); + spin_lock_init(&iwqp->lock); + spin_lock_init(&iwqp->sc_qp.pfpdu.lock); + iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0; + rf->qp_table[qp_num] = iwqp; + + if (rdma_protocol_roce(&iwdev->ibdev, 1)) { + if (dev->ws_add(&iwdev->vsi, 0)) { + irdma_cqp_qp_destroy_cmd(&rf->sc_dev, &iwqp->sc_qp); + err_code = -EINVAL; + goto error; + } + + irdma_qp_add_qos(&iwqp->sc_qp); + } + + if (udata) { + /* GEN_1 legacy support with libi40iw does not have expanded uresp struct */ + if (udata->outlen == IRDMA_CREATE_QP_MIN_RESP_LEN) { + uresp.lsmm = 1; + uresp.push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1; + } else { + if (rdma_protocol_iwarp(&iwdev->ibdev, 1)) { + uresp.lsmm = 1; + if (qp->qp_uk.start_wqe_idx) { + uresp.comp_mask |= IRDMA_CREATE_QP_USE_START_WQE_IDX; + uresp.start_wqe_idx = qp->qp_uk.start_wqe_idx; + } + } + } + uresp.actual_sq_size = init_info.qp_uk_init_info.sq_size; + uresp.actual_rq_size = init_info.qp_uk_init_info.rq_size; + uresp.qp_id = qp_num; + uresp.qp_caps = qp->qp_uk.qp_caps; + + err_code = ib_copy_to_udata(udata, &uresp, + min(sizeof(uresp), udata->outlen)); + if (err_code) { + ibdev_dbg(&iwdev->ibdev, "VERBS: copy_to_udata failed\n"); + kc_irdma_destroy_qp(&iwqp->ibqp, udata); + return err_code; + } + } + + init_completion(&iwqp->free_qp); + return 0; + +error: + irdma_free_qp_rsrc(iwqp); + + return err_code; +} +#endif /* CREATE_QP_VER_2 */ +#ifdef CREATE_QP_VER_1 +/** + * irdma_free_qp_rsrc - free up memory resources for qp + * @iwqp: qp ptr (user or kernel) + */ +void irdma_free_qp_rsrc(struct irdma_qp *iwqp) +{ + struct irdma_device *iwdev = iwqp->iwdev; + struct irdma_pci_f *rf = iwdev->rf; + u32 qp_num = iwqp->ibqp.qp_num; + + irdma_ieq_cleanup_qp(iwdev->vsi.ieq, &iwqp->sc_qp); + irdma_dealloc_push_page(rf, iwqp); + if (iwqp->sc_qp.vsi) { + irdma_qp_rem_qos(&iwqp->sc_qp); + iwqp->sc_qp.dev->ws_remove(iwqp->sc_qp.vsi, + iwqp->sc_qp.user_pri); + } + + if (qp_num > 2) + irdma_free_rsrc(rf, rf->allocated_qps, qp_num); + dma_free_coherent(rf->sc_dev.hw->device, iwqp->q2_ctx_mem.size, + iwqp->q2_ctx_mem.va, iwqp->q2_ctx_mem.pa); + iwqp->q2_ctx_mem.va = NULL; + dma_free_coherent(rf->sc_dev.hw->device, iwqp->kqp.dma_mem.size, + iwqp->kqp.dma_mem.va, iwqp->kqp.dma_mem.pa); + iwqp->kqp.dma_mem.va = NULL; + kfree(iwqp->kqp.sq_wrid_mem); + kfree(iwqp->kqp.rq_wrid_mem); + kfree(iwqp->sg_list); + kfree(iwqp); +} + +/** + * irdma_create_qp - create qp + * @ibpd: ptr of pd + * @init_attr: attributes for qp + * @udata: user data for create qp + */ +struct ib_qp *irdma_create_qp(struct ib_pd *ibpd, + struct ib_qp_init_attr *init_attr, + struct ib_udata *udata) +{ +#define IRDMA_CREATE_QP_MIN_REQ_LEN offsetofend(struct irdma_create_qp_req, user_compl_ctx) +#define IRDMA_CREATE_QP_MIN_RESP_LEN offsetofend(struct irdma_create_qp_resp, rsvd) + struct irdma_pd *iwpd = to_iwpd(ibpd); + struct irdma_device *iwdev = to_iwdev(ibpd->device); + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_qp *iwqp; + struct irdma_create_qp_resp uresp = {}; + u32 qp_num = 0; + u32 next_qp; + int ret; + int err_code; + struct irdma_sc_qp *qp; + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs; + struct irdma_qp_init_info init_info = {}; + struct irdma_qp_host_ctx_info *ctx_info; + struct irdma_srq *iwsrq; + bool srq_valid = false; + u32 srq_id = 0; + + if (init_attr->srq) { + iwsrq = to_iwsrq(init_attr->srq); + srq_valid = true; + srq_id = iwsrq->srq_num; + init_attr->cap.max_recv_sge = uk_attrs->max_hw_wq_frags; + init_attr->cap.max_recv_wr = 4; + init_info.qp_uk_init_info.srq_uk = &iwsrq->sc_srq.srq_uk; + } + err_code = irdma_validate_qp_attrs(init_attr, iwdev); + if (err_code) + return ERR_PTR(err_code); + + if (udata && (udata->inlen < IRDMA_CREATE_QP_MIN_REQ_LEN || + udata->outlen < IRDMA_CREATE_QP_MIN_RESP_LEN)) + return ERR_PTR(-EINVAL); + + init_info.vsi = &iwdev->vsi; + init_info.qp_uk_init_info.uk_attrs = uk_attrs; + init_info.qp_uk_init_info.sq_size = init_attr->cap.max_send_wr; + init_info.qp_uk_init_info.rq_size = init_attr->cap.max_recv_wr; + init_info.qp_uk_init_info.max_sq_frag_cnt = init_attr->cap.max_send_sge; + init_info.qp_uk_init_info.max_rq_frag_cnt = init_attr->cap.max_recv_sge; + init_info.qp_uk_init_info.max_inline_data = init_attr->cap.max_inline_data; + + iwqp = kzalloc(sizeof(*iwqp), GFP_KERNEL); + if (!iwqp) + return ERR_PTR(-ENOMEM); + + iwqp->sg_list = kcalloc(uk_attrs->max_hw_wq_frags, sizeof(*iwqp->sg_list), + GFP_KERNEL); + if (!iwqp->sg_list) { + kfree(iwqp); + return ERR_PTR(-ENOMEM); + } + + qp = &iwqp->sc_qp; + qp->qp_uk.back_qp = iwqp; + qp->qp_uk.lock = &iwqp->lock; + qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + + iwqp->iwdev = iwdev; + iwqp->q2_ctx_mem.size = ALIGN(IRDMA_Q2_BUF_SIZE + IRDMA_QP_CTX_SIZE, + 256); + iwqp->q2_ctx_mem.va = dma_alloc_coherent(dev->hw->device, + iwqp->q2_ctx_mem.size, + &iwqp->q2_ctx_mem.pa, + GFP_KERNEL); + if (!iwqp->q2_ctx_mem.va) { + kfree(iwqp->sg_list); + kfree(iwqp); + return ERR_PTR(-ENOMEM); + } + + init_info.q2 = iwqp->q2_ctx_mem.va; + init_info.q2_pa = iwqp->q2_ctx_mem.pa; + init_info.host_ctx = (__le64 *)(init_info.q2 + IRDMA_Q2_BUF_SIZE); + init_info.host_ctx_pa = init_info.q2_pa + IRDMA_Q2_BUF_SIZE; + + if (init_attr->qp_type == IB_QPT_GSI) { + qp_num = 1; + } else { + get_random_bytes(&next_qp, sizeof(next_qp)); + next_qp %= rf->max_qp; + err_code = irdma_alloc_rsrc(rf, rf->allocated_qps, rf->max_qp, + &qp_num, &next_qp); + } + if (err_code) + goto error; + + iwqp->iwpd = iwpd; + iwqp->ibqp.qp_num = qp_num; + qp = &iwqp->sc_qp; + iwqp->iwscq = to_iwcq(init_attr->send_cq); + iwqp->iwrcq = to_iwcq(init_attr->recv_cq); + iwqp->host_ctx.va = init_info.host_ctx; + iwqp->host_ctx.pa = init_info.host_ctx_pa; + iwqp->host_ctx.size = IRDMA_QP_CTX_SIZE; + + init_info.pd = &iwpd->sc_pd; + init_info.qp_uk_init_info.qp_id = qp_num; + if (!rdma_protocol_roce(&iwdev->ibdev, 1)) + init_info.qp_uk_init_info.first_sq_wq = 1; + iwqp->ctx_info.qp_compl_ctx = (uintptr_t)qp; + init_waitqueue_head(&iwqp->waitq); + init_waitqueue_head(&iwqp->mod_qp_waitq); + + if (udata) { + init_info.qp_uk_init_info.abi_ver = iwpd->sc_pd.abi_ver; + err_code = irdma_setup_umode_qp(udata, iwdev, iwqp, &init_info, init_attr); + } else { + if (uk_attrs->hw_rev <= IRDMA_GEN_2) + INIT_DELAYED_WORK(&iwqp->dwork_flush, irdma_flush_worker); + init_info.qp_uk_init_info.abi_ver = IRDMA_ABI_VER; + err_code = irdma_setup_kmode_qp(iwdev, iwqp, &init_info, init_attr); + } + + if (err_code) { + ibdev_dbg(&iwdev->ibdev, "VERBS: setup qp failed\n"); + goto error; + } + + if (rdma_protocol_roce(&iwdev->ibdev, 1)) { + if (init_attr->qp_type == IB_QPT_RC) { + init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_RC; + init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM | + IRDMA_WRITE_WITH_IMM | + IRDMA_ROCE; + } else { + init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_ROCE_UD; + init_info.qp_uk_init_info.qp_caps = IRDMA_SEND_WITH_IMM | + IRDMA_ROCE; + } + } else { + init_info.qp_uk_init_info.type = IRDMA_QP_TYPE_IWARP; + init_info.qp_uk_init_info.qp_caps = IRDMA_WRITE_WITH_IMM; + } + +#ifndef __OFED_4_8__ + if (dev->hw_attrs.uk_attrs.hw_rev > IRDMA_GEN_1) + init_info.qp_uk_init_info.qp_caps |= IRDMA_PUSH_MODE; + +#endif + ret = irdma_sc_qp_init(qp, &init_info); + if (ret) { + err_code = -EPROTO; + ibdev_dbg(&iwdev->ibdev, "VERBS: qp_init fail\n"); + goto error; + } + + ctx_info = &iwqp->ctx_info; + ctx_info->srq_valid = srq_valid; + ctx_info->srq_id = srq_id; + ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id; + ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id; + + if (rdma_protocol_roce(&iwdev->ibdev, 1)) + irdma_roce_fill_and_set_qpctx_info(iwqp, ctx_info); + else + irdma_iw_fill_and_set_qpctx_info(iwqp, ctx_info); + + err_code = irdma_cqp_create_qp_cmd(iwqp); + if (err_code) + goto error; + + refcount_set(&iwqp->refcnt, 1); + spin_lock_init(&iwqp->lock); + spin_lock_init(&iwqp->sc_qp.pfpdu.lock); + iwqp->sig_all = (init_attr->sq_sig_type == IB_SIGNAL_ALL_WR) ? 1 : 0; + rf->qp_table[qp_num] = iwqp; + + if (rdma_protocol_roce(&iwdev->ibdev, 1)) { + if (dev->ws_add(&iwdev->vsi, 0)) { + irdma_cqp_qp_destroy_cmd(&rf->sc_dev, &iwqp->sc_qp); + err_code = -EINVAL; + goto error; + } + + irdma_qp_add_qos(&iwqp->sc_qp); + } + + if (udata) { + /* GEN_1 legacy support with libi40iw does not have expanded uresp struct */ + if (udata->outlen == IRDMA_CREATE_QP_MIN_RESP_LEN) { + uresp.lsmm = 1; + uresp.push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX_GEN_1; + } else { + if (rdma_protocol_iwarp(&iwdev->ibdev, 1)) { + uresp.lsmm = 1; + if (qp->qp_uk.start_wqe_idx) { + uresp.comp_mask |= IRDMA_CREATE_QP_USE_START_WQE_IDX; + uresp.start_wqe_idx = qp->qp_uk.start_wqe_idx; + } + } + } + uresp.actual_sq_size = init_info.qp_uk_init_info.sq_size; + uresp.actual_rq_size = init_info.qp_uk_init_info.rq_size; + uresp.qp_id = qp_num; + uresp.qp_caps = qp->qp_uk.qp_caps; + + err_code = ib_copy_to_udata(udata, &uresp, + min(sizeof(uresp), udata->outlen)); + if (err_code) { + ibdev_dbg(&iwdev->ibdev, "VERBS: copy_to_udata failed\n"); + kc_irdma_destroy_qp(&iwqp->ibqp, udata); + return ERR_PTR(err_code); + } + } + + init_completion(&iwqp->free_qp); + return &iwqp->ibqp; + +error: + irdma_free_qp_rsrc(iwqp); + + return ERR_PTR(err_code); +} + +#endif /* CREATE_QP_VER_1 */ +/** + * irdma_destroy_qp - destroy qp + * @ibqp: qp's ib pointer also to get to device's qp address + * @udata: user data + */ +#ifdef DESTROY_QP_VER_2 +int irdma_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata) +#endif +#if defined(DESTROY_QP_VER_1) +int irdma_destroy_qp(struct ib_qp *ibqp) +#endif +{ + struct irdma_qp *iwqp = to_iwqp(ibqp); + struct irdma_device *iwdev = iwqp->iwdev; + + if (iwqp->sc_qp.qp_uk.destroy_pending) + goto free_rsrc; + iwqp->sc_qp.qp_uk.destroy_pending = true; + + if (iwqp->iwarp_state >= IRDMA_QP_STATE_IDLE) + irdma_modify_qp_to_err(&iwqp->sc_qp); + + if (!iwqp->user_mode) { + if (iwqp->iwscq) { + irdma_clean_cqes(iwqp, iwqp->iwscq); + if (iwqp->iwrcq != iwqp->iwscq) + irdma_clean_cqes(iwqp, iwqp->iwrcq); + } + } + irdma_qp_rem_ref(&iwqp->ibqp); + wait_for_completion(&iwqp->free_qp); + irdma_free_lsmm_rsrc(iwqp); + if (!iwdev->rf->reset && irdma_cqp_qp_destroy_cmd(&iwdev->rf->sc_dev, &iwqp->sc_qp)) + return (iwdev->rf->rdma_ver <= IRDMA_GEN_2 && !iwqp->user_mode) ? 0 : -ENOTRECOVERABLE; +free_rsrc: + irdma_remove_push_mmap_entries(iwqp); + irdma_free_qp_rsrc(iwqp); + + return 0; +} + +/** + * irdma_create_cq - create cq + * @ibcq: CQ allocated + * @attr: attributes for cq + * @udata: user data + */ +#ifdef CREATE_CQ_VER_3 +int irdma_create_cq(struct ib_cq *ibcq, + const struct ib_cq_init_attr *attr, + struct ib_udata *udata) +#elif defined(CREATE_CQ_VER_2) +struct ib_cq *irdma_create_cq(struct ib_device *ibdev, + const struct ib_cq_init_attr *attr, + struct ib_udata *udata) +#elif defined(CREATE_CQ_VER_1) +struct ib_cq *irdma_create_cq(struct ib_device *ibdev, + const struct ib_cq_init_attr *attr, + struct ib_ucontext *context, + struct ib_udata *udata) +#endif +{ +#define IRDMA_CREATE_CQ_MIN_REQ_LEN offsetofend(struct irdma_create_cq_req, user_cq_buf) +#define IRDMA_CREATE_CQ_MIN_RESP_LEN offsetofend(struct irdma_create_cq_resp, cq_size) +#ifdef CREATE_CQ_VER_3 + struct ib_device *ibdev = ibcq->device; +#endif + struct irdma_device *iwdev = to_iwdev(ibdev); + struct irdma_pci_f *rf = iwdev->rf; +#ifdef CREATE_CQ_VER_3 + struct irdma_cq *iwcq = to_iwcq(ibcq); +#else + struct irdma_cq *iwcq; +#endif + u32 cq_num = 0; + struct irdma_sc_cq *cq; + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_cq_init_info info = {}; + int status; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_cq_uk_init_info *ukinfo = &info.cq_uk_init_info; + unsigned long flags; + int err_code; + int entries = attr->cqe; + bool cqe_64byte_ena; + +#ifdef CREATE_CQ_VER_3 + err_code = cq_validate_flags(attr->flags, dev->hw_attrs.uk_attrs.hw_rev); + if (err_code) + return err_code; + + if (udata && (udata->inlen < IRDMA_CREATE_CQ_MIN_REQ_LEN || + udata->outlen < IRDMA_CREATE_CQ_MIN_RESP_LEN)) + return -EINVAL; +#else + err_code = cq_validate_flags(attr->flags, dev->hw_attrs.uk_attrs.hw_rev); + if (err_code) + return ERR_PTR(err_code); + + if (udata && (udata->inlen < IRDMA_CREATE_CQ_MIN_REQ_LEN || + udata->outlen < IRDMA_CREATE_CQ_MIN_RESP_LEN)) + return ERR_PTR(-EINVAL); + + iwcq = kzalloc(sizeof(*iwcq), GFP_KERNEL); + if (!iwcq) + return ERR_PTR(-ENOMEM); +#endif + err_code = irdma_alloc_rsrc(rf, rf->allocated_cqs, rf->max_cq, &cq_num, + &rf->next_cq); + if (err_code) +#ifdef CREATE_CQ_VER_3 + return err_code; +#else + goto error; +#endif + cq = &iwcq->sc_cq; + cq->back_cq = iwcq; + refcount_set(&iwcq->refcnt, 1); + spin_lock_init(&iwcq->lock); + INIT_LIST_HEAD(&iwcq->resize_list); + INIT_LIST_HEAD(&iwcq->cmpl_generated); + info.dev = dev; + ukinfo->cq_size = max(entries, 4); + ukinfo->cq_id = cq_num; + cqe_64byte_ena = (dev->hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_64_BYTE_CQE) ? true : false; + ukinfo->avoid_mem_cflct = cqe_64byte_ena; + iwcq->ibcq.cqe = info.cq_uk_init_info.cq_size; + atomic_set(&iwcq->armed, 0); + if (attr->comp_vector < rf->ceqs_count) + info.ceq_id = attr->comp_vector; + info.ceq_id_valid = true; + info.ceqe_mask = 1; + info.type = IRDMA_CQ_TYPE_IWARP; + info.vsi = &iwdev->vsi; + + if (udata) { + struct irdma_ucontext *ucontext; + struct irdma_create_cq_req req = {}; + struct irdma_cq_mr *cqmr; + struct irdma_pbl *iwpbl; + struct irdma_pbl *iwpbl_shadow; + struct irdma_cq_mr *cqmr_shadow; + + iwcq->user_mode = true; + ucontext = kc_get_ucontext(udata); + + if (ib_copy_from_udata(&req, udata, + min(sizeof(req), udata->inlen))) { + err_code = -EFAULT; + goto cq_free_rsrc; + } + + spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); + iwpbl = irdma_get_pbl((unsigned long)req.user_cq_buf, + &ucontext->cq_reg_mem_list); + spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); + if (!iwpbl) { + err_code = -EPROTO; + goto cq_free_rsrc; + } + iwcq->iwpbl = iwpbl; + iwcq->cq_mem_size = 0; + cqmr = &iwpbl->cq_mr; + + if (rf->sc_dev.hw_attrs.uk_attrs.feature_flags & + IRDMA_FEATURE_CQ_RESIZE && !ucontext->legacy_mode) { + spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); + iwpbl_shadow = irdma_get_pbl((unsigned long)req.user_shadow_area, + &ucontext->cq_reg_mem_list); + spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); + + if (!iwpbl_shadow) { + err_code = -EPROTO; + goto cq_free_rsrc; + } + iwcq->iwpbl_shadow = iwpbl_shadow; + cqmr_shadow = &iwpbl_shadow->cq_mr; + info.shadow_area_pa = cqmr_shadow->cq_pbl.addr; + cqmr->split = true; + } else { + info.shadow_area_pa = cqmr->shadow; + } + if (iwpbl->pbl_allocated) { + info.virtual_map = true; + info.pbl_chunk_size = 1; + info.first_pm_pbl_idx = cqmr->cq_pbl.idx; + } else { + info.cq_base_pa = cqmr->cq_pbl.addr; + } + } else { + /* Kmode allocations */ + int rsize; + + if (entries < 1 || entries > rf->max_cqe) { + err_code = -EINVAL; + goto cq_free_rsrc; + } + + entries++; + if (!cqe_64byte_ena && dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) + entries *= 2; + ukinfo->cq_size = entries; + + if (cqe_64byte_ena) + rsize = info.cq_uk_init_info.cq_size * sizeof(struct irdma_extended_cqe); + else + rsize = info.cq_uk_init_info.cq_size * sizeof(struct irdma_cqe); + iwcq->kmem.size = ALIGN(round_up(rsize, IRDMA_HW_PAGE_SIZE), + IRDMA_HW_PAGE_SIZE); + iwcq->kmem.va = dma_alloc_coherent(dev->hw->device, + iwcq->kmem.size, + &iwcq->kmem.pa, GFP_KERNEL); + if (!iwcq->kmem.va) { + err_code = -ENOMEM; + goto cq_free_rsrc; + } + + iwcq->kmem_shadow.size = ALIGN(IRDMA_SHADOW_AREA_SIZE << 3, + 64); + iwcq->kmem_shadow.va = dma_alloc_coherent(dev->hw->device, + iwcq->kmem_shadow.size, + &iwcq->kmem_shadow.pa, + GFP_KERNEL); + + if (!iwcq->kmem_shadow.va) { + err_code = -ENOMEM; + goto cq_kmem_free; + } + info.shadow_area_pa = iwcq->kmem_shadow.pa; + ukinfo->shadow_area = iwcq->kmem_shadow.va; + ukinfo->cq_base = iwcq->kmem.va; + info.cq_base_pa = iwcq->kmem.pa; + } + + info.shadow_read_threshold = min(info.cq_uk_init_info.cq_size / 2, + (u32)IRDMA_MAX_CQ_READ_THRESH); + if (irdma_sc_cq_init(cq, &info)) { + ibdev_dbg(&iwdev->ibdev, "VERBS: init cq fail\n"); + err_code = -EPROTO; + goto cq_kmem_free; + } + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) { + err_code = -ENOMEM; + goto cq_kmem_free; + } + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = IRDMA_OP_CQ_CREATE; + cqp_info->post_sq = 1; + cqp_info->in.u.cq_create.cq = cq; + cqp_info->in.u.cq_create.check_overflow = true; + cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + if (status) { + err_code = -ENOMEM; + goto cq_kmem_free; + } + + if (udata) { + struct irdma_create_cq_resp resp = {}; + + resp.cq_id = info.cq_uk_init_info.cq_id; + resp.cq_size = info.cq_uk_init_info.cq_size; + if (ib_copy_to_udata(udata, &resp, + min(sizeof(resp), udata->outlen))) { + ibdev_dbg(&iwdev->ibdev, "VERBS: copy to user data\n"); + err_code = -EPROTO; + goto cq_destroy; + } + } + + rf->cq_table[cq_num] = iwcq; + init_completion(&iwcq->free_cq); + +#ifdef CREATE_CQ_VER_3 + return 0; +#else + return &iwcq->ibcq; +#endif +cq_destroy: + irdma_cq_wq_destroy(rf, cq); +cq_kmem_free: + if (!iwcq->user_mode) { + dma_free_coherent(dev->hw->device, iwcq->kmem.size, + iwcq->kmem.va, iwcq->kmem.pa); + iwcq->kmem.va = NULL; + dma_free_coherent(dev->hw->device, iwcq->kmem_shadow.size, + iwcq->kmem_shadow.va, iwcq->kmem_shadow.pa); + iwcq->kmem_shadow.va = NULL; + } +cq_free_rsrc: + irdma_free_rsrc(rf, rf->allocated_cqs, cq_num); +#ifdef CREATE_CQ_VER_3 + return err_code; +#else +error: + kfree(iwcq); + return ERR_PTR(err_code); +#endif +} + +#ifdef NEED_RDMA_UMEM_BLOCK_ITER_NEXT +void kc__rdma_block_iter_start(struct kc_ib_block_iter *biter, + struct scatterlist *sglist, unsigned int nents, + unsigned long pgsz) +{ + memset(biter, 0, sizeof(*biter)); + biter->__sg = sglist; + biter->__sg_nents = nents; + + /* Driver provides best block size to use */ + biter->__pg_bit = __fls(pgsz); +} + +bool kc__rdma_block_iter_next(struct kc_ib_block_iter *biter) +{ + unsigned int block_offset; + unsigned int sg_delta; + + if (!biter->__sg_nents || !biter->__sg) + return false; + + biter->__dma_addr = sg_dma_address(biter->__sg) + biter->__sg_advance; + block_offset = biter->__dma_addr & (BIT_ULL(biter->__pg_bit) - 1); + sg_delta = BIT_ULL(biter->__pg_bit) - block_offset; + + if (sg_dma_len(biter->__sg) - biter->__sg_advance > sg_delta) { + biter->__sg_advance += sg_delta; + } else { + biter->__sg_advance = 0; + biter->__sg = sg_next(biter->__sg); + biter->__sg_nents--; + } + + return true; +} +#endif /* NEED_RDMA_UMEM_BLOCK_ITER_NEXT */ + +#ifdef COPY_USER_PGADDR_VER_1 +void irdma_copy_user_pgaddrs(struct irdma_mr *iwmr, u64 *pbl, + enum irdma_pble_level level) +{ + struct ib_umem *region = iwmr->region; + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + int chunk_pages, entry, i; + struct scatterlist *sg; + u64 pg_addr = 0; + struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; + struct irdma_pble_info *pinfo; + u32 idx = 0; + u32 pbl_cnt = 0; + + pinfo = (level == PBLE_LEVEL_1) ? NULL : palloc->level2.leaf; + for_each_sg(region->sg_head.sgl, sg, region->nmap, entry) { + chunk_pages = DIV_ROUND_UP(sg_dma_len(sg), iwmr->page_size); + if (iwmr->type == IRDMA_MEMREG_TYPE_QP && !iwpbl->qp_mr.sq_page) + iwpbl->qp_mr.sq_page = sg_page(sg); + for (i = 0; i < chunk_pages; i++) { + pg_addr = sg_dma_address(sg) + (i * iwmr->page_size); + if ((entry + i) == 0) + *pbl = pg_addr & iwmr->page_msk; + else if (!(pg_addr & ~iwmr->page_msk)) + *pbl = pg_addr; + else + continue; + if (++pbl_cnt == palloc->total_cnt) + break; + pbl = irdma_next_pbl_addr(pbl, &pinfo, &idx); + } + } +} +#endif + +/** + * irdma_destroy_ah - Destroy address handle + * @ibah: pointer to address handle + * @ah_flags: destroy flags + */ +#if defined(DESTROY_AH_VER_4) +int irdma_destroy_ah(struct ib_ah *ibah, u32 ah_flags) +{ + struct irdma_device *iwdev = to_iwdev(ibah->device); + struct irdma_ah *ah = to_iwah(ibah); + + if (ah->parent_ah) { + mutex_lock(&iwdev->ah_tbl_lock); + if (!refcount_dec_and_test(&ah->parent_ah->refcnt)) { + mutex_unlock(&iwdev->ah_tbl_lock); + return 0; + } + hash_del(&ah->parent_ah->list); + kfree(ah->parent_ah); + iwdev->ah_list_cnt--; + mutex_unlock(&iwdev->ah_tbl_lock); + } + irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY, + false, NULL, ah); + + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, + ah->sc_ah.ah_info.ah_idx); + + return 0; +} +#endif + +#if defined(DESTROY_AH_VER_3) +void irdma_destroy_ah(struct ib_ah *ibah, u32 ah_flags) +{ + struct irdma_device *iwdev = to_iwdev(ibah->device); + struct irdma_ah *ah = to_iwah(ibah); + + if (ah->parent_ah) { + mutex_lock(&iwdev->ah_tbl_lock); + if (!refcount_dec_and_test(&ah->parent_ah->refcnt)) { + mutex_unlock(&iwdev->ah_tbl_lock); + return; + } + hash_del(&ah->parent_ah->list); + kfree(ah->parent_ah); + iwdev->ah_list_cnt--; + mutex_unlock(&iwdev->ah_tbl_lock); + } + irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY, + false, NULL, ah); + + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, + ah->sc_ah.ah_info.ah_idx); +} +#endif + +#if defined(DESTROY_AH_VER_2) +int irdma_destroy_ah(struct ib_ah *ibah, u32 ah_flags) +{ + struct irdma_device *iwdev = to_iwdev(ibah->device); + struct irdma_ah *ah = to_iwah(ibah); + + if (ah->parent_ah) { + mutex_lock(&iwdev->ah_tbl_lock); + if (!refcount_dec_and_test(&ah->parent_ah->refcnt)) { + mutex_unlock(&iwdev->ah_tbl_lock); + goto done; + } + hash_del(&ah->parent_ah->list); + kfree(ah->parent_ah); + iwdev->ah_list_cnt--; + mutex_unlock(&iwdev->ah_tbl_lock); + } + irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY, + false, NULL, ah); + + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, + ah->sc_ah.ah_info.ah_idx); + +done: + kfree(ah); + return 0; +} +#endif + +#if defined(DESTROY_AH_VER_1) +int irdma_destroy_ah(struct ib_ah *ibah) +{ + struct irdma_device *iwdev = to_iwdev(ibah->device); + struct irdma_ah *ah = to_iwah(ibah); + + if (ah->parent_ah) { + mutex_lock(&iwdev->ah_tbl_lock); + if (!refcount_dec_and_test(&ah->parent_ah->refcnt)) { + mutex_unlock(&iwdev->ah_tbl_lock); + goto done; + } + hash_del(&ah->parent_ah->list); + kfree(ah->parent_ah); + iwdev->ah_list_cnt--; + mutex_unlock(&iwdev->ah_tbl_lock); + } + irdma_ah_cqp_op(iwdev->rf, &ah->sc_ah, IRDMA_OP_AH_DESTROY, + false, NULL, ah); + + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_ahs, + ah->sc_ah.ah_info.ah_idx); + +done: + kfree(ah); + return 0; +} +#endif + +#ifdef DEREG_MR_VER_2 +int irdma_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata) +#else +int irdma_dereg_mr(struct ib_mr *ib_mr) +#endif +{ + struct irdma_mr *iwmr = to_iwmr(ib_mr); + struct irdma_device *iwdev = to_iwdev(ib_mr->device); + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + int ret; + + if (iwmr->type != IRDMA_MEMREG_TYPE_MEM) { + if (iwmr->region) { + struct irdma_ucontext *ucontext; +#ifdef DEREG_MR_VER_2 + + ucontext = rdma_udata_to_drv_context(udata, + struct irdma_ucontext, + ibucontext); +#else + struct ib_pd *ibpd = ib_mr->pd; + + ucontext = to_ucontext(ibpd->uobject->context); +#endif + irdma_del_memlist(iwmr, ucontext); + } + goto done; + } + + ret = irdma_hwdereg_mr(ib_mr); + if (ret) + return ret; + + irdma_free_stag(iwdev, iwmr->stag); +done: + if (iwpbl->pbl_allocated) + irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc); + + if (iwmr->region) + ib_umem_release(iwmr->region); + + kfree(iwmr); + + return 0; +} + +#ifdef REREG_MR_VER_1 +/* + * irdma_rereg_user_mr - Re-Register a user memory region + * @ibmr: ib mem to access iwarp mr pointer + * @flags: bit mask to indicate which of the attr's of MR modified + * @start: virtual start address + * @len: length of mr + * @virt: virtual address + * @new access flags: bit mask of access flags + * @new_pd: ptr of pd + * @udata: user data + */ +int irdma_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, u64 len, + u64 virt, int new_access, struct ib_pd *new_pd, + struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ib_mr->device); + struct irdma_mr *iwmr = to_iwmr(ib_mr); + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + int ret; + + if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size) + return -EINVAL; + + if (flags & ~(IB_MR_REREG_TRANS | IB_MR_REREG_PD | IB_MR_REREG_ACCESS)) + return -EOPNOTSUPP; + + ret = irdma_hwdereg_mr(ib_mr); + if (ret) + return ret; + + if (flags & IB_MR_REREG_ACCESS) + iwmr->access = new_access; + + if (flags & IB_MR_REREG_PD) { + iwmr->ibmr.pd = new_pd; + iwmr->ibmr.device = new_pd->device; + } + + if (flags & IB_MR_REREG_TRANS) { + if (iwpbl->pbl_allocated) { + irdma_free_pble(iwdev->rf->pble_rsrc, + &iwpbl->pble_alloc); + iwpbl->pbl_allocated = false; + } + if (iwmr->region) { + ib_umem_release(iwmr->region); + iwmr->region = NULL; + } + + ib_mr = irdma_rereg_mr_trans(iwmr, start, len, virt, udata); + if (IS_ERR(ib_mr)) + return PTR_ERR(ib_mr); + + } else { + ret = irdma_hwreg_mr(iwdev, iwmr, iwmr->access); + if (ret) + return ret; + } + + return 0; +} +#endif +#ifdef REREG_MR_VER_2 +/* + * irdma_rereg_user_mr - Re-Register a user memory region(MR) + * @ibmr: ib mem to access iwarp mr pointer + * @flags: bit mask to indicate which of the attr's of MR modified + * @start: virtual start address + * @len: length of mr + * @virt: virtual address + * @new_access: bit mask of access flags + * @new_pd: ptr of pd + * @udata: user data + * + * Return: + * NULL - Success, existing MR updated + * ERR_PTR - error occurred + */ +struct ib_mr *irdma_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, + u64 len, u64 virt, int new_access, + struct ib_pd *new_pd, + struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ib_mr->device); + struct irdma_mr *iwmr = to_iwmr(ib_mr); + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + int ret; + + if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size) + return ERR_PTR(-EINVAL); + + if (flags & ~(IB_MR_REREG_TRANS | IB_MR_REREG_PD | IB_MR_REREG_ACCESS)) + return ERR_PTR(-EOPNOTSUPP); + + ret = irdma_hwdereg_mr(ib_mr); + if (ret) + return ERR_PTR(ret); + + if (flags & IB_MR_REREG_ACCESS) + iwmr->access = new_access; + + if (flags & IB_MR_REREG_PD) { + iwmr->ibmr.pd = new_pd; + iwmr->ibmr.device = new_pd->device; + } + + if (flags & IB_MR_REREG_TRANS) { + if (iwpbl->pbl_allocated) { + irdma_free_pble(iwdev->rf->pble_rsrc, + &iwpbl->pble_alloc); + iwpbl->pbl_allocated = false; + } + if (iwmr->region) { + ib_umem_release(iwmr->region); + iwmr->region = NULL; + } + + ib_mr = irdma_rereg_mr_trans(iwmr, start, len, virt, udata); + if (IS_ERR(ib_mr)) + return ib_mr; + } else { + ret = irdma_hwreg_mr(iwdev, iwmr, iwmr->access); + if (ret) + return ERR_PTR(ret); + } + + return NULL; +} +#endif +#ifdef SET_ROCE_CM_INFO_VER_3 + +int kc_irdma_set_roce_cm_info(struct irdma_qp *iwqp, struct ib_qp_attr *attr, + u16 *vlan_id) +{ + const struct ib_gid_attr *sgid_attr; + int ret; + struct irdma_av *av = &iwqp->roce_ah.av; + + sgid_attr = attr->ah_attr.grh.sgid_attr; + if (kc_deref_sgid_attr(sgid_attr)) { + ret = rdma_read_gid_l2_fields(sgid_attr, vlan_id, + iwqp->ctx_info.roce_info->mac_addr); + if (ret) + return ret; + } + + av->net_type = kc_rdma_gid_attr_network_type(sgid_attr, + sgid_attr->gid_type, + &sgid); + + rdma_gid2ip((struct sockaddr *)&av->sgid_addr, &sgid_attr->gid); + + iwqp->ctx_info.user_pri = irdma_roce_get_vlan_prio(sgid_attr->ndev, + iwqp->ctx_info.user_pri); + iwqp->sc_qp.user_pri = iwqp->ctx_info.user_pri; + + return 0; +} +#endif + +#ifdef SET_ROCE_CM_INFO_VER_2 +int kc_irdma_set_roce_cm_info(struct irdma_qp *iwqp, struct ib_qp_attr *attr, + u16 *vlan_id) +{ + const struct ib_gid_attr *sgid_attr; + struct irdma_av *av = &iwqp->roce_ah.av; + + sgid_attr = attr->ah_attr.grh.sgid_attr; + if (kc_deref_sgid_attr(sgid_attr)) { + *vlan_id = rdma_vlan_dev_vlan_id(kc_deref_sgid_attr(sgid_attr)); + ether_addr_copy(iwqp->ctx_info.roce_info->mac_addr, + kc_deref_sgid_attr(sgid_attr)->dev_addr); + } + av->net_type = kc_rdma_gid_attr_network_type(sgid_attr, + sgid_attr->gid_type, + &sgid); + rdma_gid2ip((struct sockaddr *)&av->sgid_addr, &sgid_attr->gid); + iwqp->ctx_info.user_pri = irdma_roce_get_vlan_prio(sgid_attr->ndev, + iwqp->ctx_info.user_pri); + iwqp->sc_qp.user_pri = iwqp->ctx_info.user_pri; + + return 0; +} +#endif + +#ifdef SET_ROCE_CM_INFO_VER_1 +int kc_irdma_set_roce_cm_info(struct irdma_qp *iwqp, struct ib_qp_attr *attr, + u16 *vlan_id) +{ + int ret; + union ib_gid sgid; + struct ib_gid_attr sgid_attr; + struct irdma_av *av = &iwqp->roce_ah.av; + + ret = ib_get_cached_gid(iwqp->ibqp.device, attr->ah_attr.port_num, + attr->ah_attr.grh.sgid_index, &sgid, + &sgid_attr); + if (ret) + return ret; + + if (kc_deref_sgid_attr(sgid_attr)) { + *vlan_id = rdma_vlan_dev_vlan_id(kc_deref_sgid_attr(sgid_attr)); + ether_addr_copy(iwqp->ctx_info.roce_info->mac_addr, + kc_deref_sgid_attr(sgid_attr)->dev_addr); + } + + av->net_type = kc_rdma_gid_attr_network_type(sgid_attr, + sgid_attr.gid_type, + &sgid); + rdma_gid2ip((struct sockaddr *)&av->sgid_addr, &sgid); + iwqp->ctx_info.user_pri = irdma_roce_get_vlan_prio(sgid_attr.ndev, + iwqp->ctx_info.user_pri); + dev_put(kc_deref_sgid_attr(sgid_attr)); + iwqp->sc_qp.user_pri = iwqp->ctx_info.user_pri; + + return 0; +} + +#endif +#ifdef IRDMA_DESTROY_CQ_VER_4 +/** + * irdma_destroy_cq - destroy cq + * @ib_cq: cq pointer + * @udata: user data + */ +int irdma_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ib_cq->device); + struct irdma_cq *iwcq = to_iwcq(ib_cq); + struct irdma_sc_cq *cq = &iwcq->sc_cq; + struct irdma_sc_dev *dev = cq->dev; + struct irdma_sc_ceq *ceq = dev->ceq[cq->ceq_id]; + struct irdma_ceq *iwceq = container_of(ceq, struct irdma_ceq, sc_ceq); + unsigned long flags; + + spin_lock_irqsave(&iwcq->lock, flags); + if (!list_empty(&iwcq->cmpl_generated)) + irdma_remove_cmpls_list(iwcq); + if (!list_empty(&iwcq->resize_list)) + irdma_process_resize_list(iwcq, iwdev, NULL); + spin_unlock_irqrestore(&iwcq->lock, flags); + + irdma_cq_rem_ref(ib_cq); + wait_for_completion(&iwcq->free_cq); + + irdma_cq_wq_destroy(iwdev->rf, cq); + + spin_lock_irqsave(&iwceq->ce_lock, flags); + irdma_sc_cleanup_ceqes(cq, ceq); + spin_unlock_irqrestore(&iwceq->ce_lock, flags); + irdma_cq_free_rsrc(iwdev->rf, iwcq); + + return 0; +} + +#endif /* IRDMA_DESTROY_CQ_VER_4 */ +#ifdef IRDMA_DESTROY_CQ_VER_3 +/** + * irdma_destroy_cq - destroy cq + * @ib_cq: cq pointer + * @udata: user data + */ +void irdma_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ib_cq->device); + struct irdma_cq *iwcq = to_iwcq(ib_cq); + struct irdma_sc_cq *cq = &iwcq->sc_cq; + struct irdma_sc_dev *dev = cq->dev; + struct irdma_sc_ceq *ceq = dev->ceq[cq->ceq_id]; + struct irdma_ceq *iwceq = container_of(ceq, struct irdma_ceq, sc_ceq); + unsigned long flags; + + spin_lock_irqsave(&iwcq->lock, flags); + if (!list_empty(&iwcq->cmpl_generated)) + irdma_remove_cmpls_list(iwcq); + if (!list_empty(&iwcq->resize_list)) + irdma_process_resize_list(iwcq, iwdev, NULL); + spin_unlock_irqrestore(&iwcq->lock, flags); + + irdma_cq_rem_ref(ib_cq); + wait_for_completion(&iwcq->free_cq); + + irdma_cq_wq_destroy(iwdev->rf, cq); + + spin_lock_irqsave(&iwceq->ce_lock, flags); + irdma_sc_cleanup_ceqes(cq, ceq); + spin_unlock_irqrestore(&iwceq->ce_lock, flags); + irdma_cq_free_rsrc(iwdev->rf, iwcq); +} + +#endif /* IRDMA_DESTROY_CQ_VER_3 */ +#ifdef IRDMA_DESTROY_CQ_VER_2 +/** + * irdma_destroy_cq - destroy cq + * @ib_cq: cq pointer + * @udata: user data + */ +int irdma_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ib_cq->device); + struct irdma_cq *iwcq = to_iwcq(ib_cq); + struct irdma_sc_cq *cq = &iwcq->sc_cq; + struct irdma_sc_dev *dev = cq->dev; + struct irdma_sc_ceq *ceq = dev->ceq[cq->ceq_id]; + struct irdma_ceq *iwceq = container_of(ceq, struct irdma_ceq, sc_ceq); + unsigned long flags; + + spin_lock_irqsave(&iwcq->lock, flags); + if (!list_empty(&iwcq->cmpl_generated)) + irdma_remove_cmpls_list(iwcq); + if (!list_empty(&iwcq->resize_list)) + irdma_process_resize_list(iwcq, iwdev, NULL); + spin_unlock_irqrestore(&iwcq->lock, flags); + + irdma_cq_rem_ref(ib_cq); + wait_for_completion(&iwcq->free_cq); + + irdma_cq_wq_destroy(iwdev->rf, cq); + + spin_lock_irqsave(&iwceq->ce_lock, flags); + irdma_sc_cleanup_ceqes(cq, ceq); + spin_unlock_irqrestore(&iwceq->ce_lock, flags); + + irdma_cq_free_rsrc(iwdev->rf, iwcq); + kfree(iwcq); + + return 0; +} + +#endif /* IRDMA_DESTROY_CQ_VER_2 */ +#ifdef IRDMA_DESTROY_CQ_VER_1 +/** + * irdma_destroy_cq - destroy cq + * @ib_cq: cq pointer + */ +int irdma_destroy_cq(struct ib_cq *ib_cq) +{ + struct irdma_device *iwdev = to_iwdev(ib_cq->device); + struct irdma_cq *iwcq = to_iwcq(ib_cq); + struct irdma_sc_cq *cq = &iwcq->sc_cq; + struct irdma_sc_dev *dev = cq->dev; + struct irdma_sc_ceq *ceq = dev->ceq[cq->ceq_id]; + struct irdma_ceq *iwceq = container_of(ceq, struct irdma_ceq, sc_ceq); + unsigned long flags; + + spin_lock_irqsave(&iwcq->lock, flags); + if (!list_empty(&iwcq->cmpl_generated)) + irdma_remove_cmpls_list(iwcq); + if (!list_empty(&iwcq->resize_list)) + irdma_process_resize_list(iwcq, iwdev, NULL); + spin_unlock_irqrestore(&iwcq->lock, flags); + + irdma_cq_rem_ref(ib_cq); + wait_for_completion(&iwcq->free_cq); + + irdma_cq_wq_destroy(iwdev->rf, cq); + + spin_lock_irqsave(&iwceq->ce_lock, flags); + irdma_sc_cleanup_ceqes(cq, ceq); + spin_unlock_irqrestore(&iwceq->ce_lock, flags); + + irdma_cq_free_rsrc(iwdev->rf, iwcq); + kfree(iwcq); + + return 0; +} + +#endif /* IRDMA_DESTROY_CQ_VER_1 */ +#ifdef IRDMA_DESTROY_SRQ_VER_3 +/** + * irdma_destroy_srq - destroy srq + * @ibsrq: srq pointer + * @udata: user data + */ +int irdma_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ibsrq->device); + struct irdma_srq *iwsrq = to_iwsrq(ibsrq); + struct irdma_sc_srq *srq = &iwsrq->sc_srq; + + irdma_srq_rem_ref(ibsrq); + wait_for_completion(&iwsrq->free_srq); + + irdma_srq_wq_destroy(iwdev->rf, srq); + irdma_srq_free_rsrc(iwdev->rf, iwsrq); + kfree(iwsrq->sg_list); + return 0; +} + +#endif /* IRDMA_DESTROY_SRQ_VER_3 */ +#ifdef IRDMA_DESTROY_SRQ_VER_2 +/** + * irdma_destroy_srq - destroy srq + * @ibsrq: srq pointer + * @udata: user data + */ +void irdma_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ibsrq->device); + struct irdma_srq *iwsrq = to_iwsrq(ibsrq); + struct irdma_sc_srq *srq = &iwsrq->sc_srq; + + irdma_srq_rem_ref(ibsrq); + wait_for_completion(&iwsrq->free_srq); + + irdma_srq_wq_destroy(iwdev->rf, srq); + irdma_srq_free_rsrc(iwdev->rf, iwsrq); + kfree(iwsrq->sg_list); +} + +#endif /* IRDMA_DESTROY_SRQ_VER_2 */ +#ifdef IRDMA_DESTROY_SRQ_VER_1 +/** + * irdma_destroy_srq - destroy srq + * @ibsrq: srq pointer + */ +int irdma_destroy_srq(struct ib_srq *ibsrq) +{ + struct irdma_device *iwdev = to_iwdev(ibsrq->device); + struct irdma_srq *iwsrq = to_iwsrq(ibsrq); + struct irdma_sc_srq *srq = &iwsrq->sc_srq; + + irdma_srq_rem_ref(ibsrq); + wait_for_completion(&iwsrq->free_srq); + + irdma_srq_wq_destroy(iwdev->rf, srq); + irdma_srq_free_rsrc(iwdev->rf, iwsrq); + kfree(iwsrq->sg_list); + kfree(iwsrq); + return 0; +} + +#endif /* IRDMA_DESTROY_SRQ_VER_1 */ +#ifdef IRDMA_ALLOC_MW_VER_2 +/** + * irdma_alloc_mw - Allocate memory window + * @ibmw: Memory Window + * @udata: user data pointer + */ +int irdma_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ibmw->device); + struct irdma_mr *iwmr = to_iwmw(ibmw); + int err_code; + u32 stag; + + /* This is required for Linux kernels < 5.1, where MW type + * is not validated in ib_uverbs_alloc_mw function. + */ + if (ibmw->type != IB_MW_TYPE_1 && ibmw->type != IB_MW_TYPE_2) + return -EINVAL; + + stag = irdma_create_stag(iwdev); + if (!stag) + return -ENOMEM; + + iwmr->stag = stag; + ibmw->rkey = stag; + + err_code = irdma_hw_alloc_mw(iwdev, iwmr); + if (err_code) { + irdma_free_stag(iwdev, stag); + return err_code; + } + + return 0; +} + +#endif /* IRDMA_ALLOC_MW_VER_2 */ +#ifdef IRDMA_ALLOC_MW_VER_1 +/** + * irdma_alloc_mw - Allocate memory window + * @pd: Protection domain + * @type: Window type + * @udata: user data pointer + */ +struct ib_mw *irdma_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, + struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(pd->device); + struct irdma_mr *iwmr; + int err_code; + u32 stag; + + /* This is required for Linux kernels < 5.1, where MW type + * is not validated in ib_uverbs_alloc_mw function. + */ + if (type != IB_MW_TYPE_1 && type != IB_MW_TYPE_2) + return ERR_PTR(-EINVAL); + + iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL); + if (!iwmr) + return ERR_PTR(-ENOMEM); + + stag = irdma_create_stag(iwdev); + if (!stag) { + kfree(iwmr); + return ERR_PTR(-ENOMEM); + } + + iwmr->stag = stag; + iwmr->ibmw.rkey = stag; + iwmr->ibmw.pd = pd; + iwmr->ibmw.type = type; + iwmr->ibmw.device = pd->device; + + err_code = irdma_hw_alloc_mw(iwdev, iwmr); + if (err_code) { + irdma_free_stag(iwdev, stag); + kfree(iwmr); + return ERR_PTR(err_code); + } + + return &iwmr->ibmw; +} + +#endif /* IRDMA_ALLOC_MW_VER_1 */ +/** + * kc_set_loc_seq_num_mss - Set local seq number and mss + * @cm_node: cm node info + */ +void kc_set_loc_seq_num_mss(struct irdma_cm_node *cm_node) +{ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) + if (cm_node->ipv4) { + cm_node->tcp_cntxt.loc_seq_num = secure_tcp_seq(htonl(cm_node->loc_addr[0]), + htonl(cm_node->rem_addr[0]), + htons(cm_node->loc_port), + htons(cm_node->rem_port)); + if (cm_node->iwdev->vsi.mtu > 1500 && + 2 * cm_node->iwdev->vsi.mtu > cm_node->iwdev->rcv_wnd) + cm_node->tcp_cntxt.mss = 1500 - IRDMA_MTU_TO_MSS_IPV4; + else + cm_node->tcp_cntxt.mss = cm_node->iwdev->vsi.mtu - IRDMA_MTU_TO_MSS_IPV4; + } else if (IS_ENABLED(CONFIG_IPV6)) { + __be32 loc[4] = { + htonl(cm_node->loc_addr[0]), htonl(cm_node->loc_addr[1]), + htonl(cm_node->loc_addr[2]), htonl(cm_node->loc_addr[3]) + }; + __be32 rem[4] = { + htonl(cm_node->rem_addr[0]), htonl(cm_node->rem_addr[1]), + htonl(cm_node->rem_addr[2]), htonl(cm_node->rem_addr[3]) + }; + cm_node->tcp_cntxt.loc_seq_num = secure_tcpv6_seq(loc, rem, + htons(cm_node->loc_port), + htons(cm_node->rem_port)); + if (cm_node->iwdev->vsi.mtu > 1500 && + 2 * cm_node->iwdev->vsi.mtu > cm_node->iwdev->rcv_wnd) + cm_node->tcp_cntxt.mss = 1500 - IRDMA_MTU_TO_MSS_IPV6; + else + cm_node->tcp_cntxt.mss = cm_node->iwdev->vsi.mtu - IRDMA_MTU_TO_MSS_IPV6; + } +#else + cm_node->tcp_cntxt.loc_seq_num = htonl(current_kernel_time().tv_nsec); + if (cm_node->iwdev->vsi.mtu > 1500 && + 2 * cm_node->iwdev->vsi.mtu > cm_node->iwdev->rcv_wnd) + cm_node->tcp_cntxt.mss = (cm_node->ipv4) ? + (1500 - IRDMA_MTU_TO_MSS_IPV4) : + (1500 - IRDMA_MTU_TO_MSS_IPV6); + else + cm_node->tcp_cntxt.mss = (cm_node->ipv4) ? + (cm_node->iwdev->vsi.mtu - IRDMA_MTU_TO_MSS_IPV4) : + (cm_node->iwdev->vsi.mtu - IRDMA_MTU_TO_MSS_IPV6); +#endif +} + +#ifdef VMA_DATA +struct irdma_vma_data { + struct list_head list; + struct vm_area_struct *vma; + struct mutex *vma_list_mutex; /* protect the vma_list */ +}; + +/** + * irdma_vma_open - + * @vma: User VMA + */ +static void irdma_vma_open(struct vm_area_struct *vma) +{ + vma->vm_ops = NULL; +} + +/** + * irdma_vma_close - Remove vma data from vma list + * @vma: User VMA + */ +static void irdma_vma_close(struct vm_area_struct *vma) +{ + struct irdma_vma_data *vma_data; + + vma_data = vma->vm_private_data; + vma->vm_private_data = NULL; + vma_data->vma = NULL; + mutex_lock(vma_data->vma_list_mutex); + list_del(&vma_data->list); + mutex_unlock(vma_data->vma_list_mutex); + kfree(vma_data); +} + +static const struct vm_operations_struct irdma_vm_ops = { + .open = irdma_vma_open, + .close = irdma_vma_close +}; + +/** + * irdma_set_vma_data - Save vma data in context list + * @vma: User VMA + * @context: ib user context + */ +static int irdma_set_vma_data(struct vm_area_struct *vma, + struct irdma_ucontext *context) +{ + struct list_head *vma_head = &context->vma_list; + struct irdma_vma_data *vma_entry; + + vma_entry = kzalloc(sizeof(*vma_entry), GFP_KERNEL); + if (!vma_entry) + return -ENOMEM; + + vma->vm_private_data = vma_entry; + vma->vm_ops = &irdma_vm_ops; + + vma_entry->vma = vma; + vma_entry->vma_list_mutex = &context->vma_list_mutex; + + mutex_lock(&context->vma_list_mutex); + list_add(&vma_entry->list, vma_head); + mutex_unlock(&context->vma_list_mutex); + + return 0; +} + +/** + * irdma_disassociate_ucontext - Disassociate user context + * @context: ib user context + */ +void irdma_disassociate_ucontext(struct ib_ucontext *context) +{ + struct irdma_ucontext *ucontext = to_ucontext(context); + + struct irdma_vma_data *vma_data, *n; + struct vm_area_struct *vma; + + mutex_lock(&ucontext->vma_list_mutex); + list_for_each_entry_safe(vma_data, n, &ucontext->vma_list, list) { + vma = vma_data->vma; + zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE); + + vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE); + vma->vm_ops = NULL; + list_del(&vma_data->list); + kfree(vma_data); + } + mutex_unlock(&ucontext->vma_list_mutex); +} + +int rdma_user_mmap_io(struct ib_ucontext *context, struct vm_area_struct *vma, + unsigned long pfn, unsigned long size, pgprot_t prot) +{ + if (io_remap_pfn_range(vma, + vma->vm_start, + pfn, + size, + prot)) + return -EAGAIN; + + return irdma_set_vma_data(vma, to_ucontext(context)); +} +#else +/** + * irdma_disassociate_ucontext - Disassociate user context + * @context: ib user context + */ +void irdma_disassociate_ucontext(struct ib_ucontext *context) +{ +} +#endif /* RDMA_MMAP_DB_SUPPORT */ + +#ifndef NETDEV_TO_IBDEV_SUPPORT +struct ib_device *ib_device_get_by_netdev(struct net_device *netdev, int driver_id) +{ + struct irdma_device *iwdev; + struct irdma_handler *hdl; + unsigned long flags; + + spin_lock_irqsave(&irdma_handler_lock, flags); + list_for_each_entry(hdl, &irdma_handlers, list) { + iwdev = hdl->iwdev; + if (netdev == iwdev->netdev) { + spin_unlock_irqrestore(&irdma_handler_lock, + flags); + return &iwdev->ibdev; + } + } + spin_unlock_irqrestore(&irdma_handler_lock, flags); + + return NULL; +} + +void ib_unregister_device_put(struct ib_device *device) +{ + ib_unregister_device(device); +} + +#endif /* NETDEV_TO_IBDEV_SUPPORT */ +/** + * irdma_query_gid_roce - Query port GID for Roce + * @ibdev: device pointer from stack + * @port: port number + * @index: Entry index + * @gid: Global ID + */ +#ifdef QUERY_GID_ROCE_V2 +int irdma_query_gid_roce(struct ib_device *ibdev, u32 port, int index, + union ib_gid *gid) +#elif defined(QUERY_GID_ROCE_V1) +int irdma_query_gid_roce(struct ib_device *ibdev, u8 port, int index, + union ib_gid *gid) +#endif +{ + int ret; + + ret = rdma_query_gid(ibdev, port, index, gid); + if (ret == -EAGAIN) { + memcpy(gid, &zgid, sizeof(*gid)); + return 0; + } + + return ret; +} + +/** + * irdma_modify_port - modify port attributes + * @ibdev: device pointer from stack + * @port: port number for query + * @mask: Property mask + * @props: returning device attributes + */ +#ifdef MODIFY_PORT_V2 +int irdma_modify_port(struct ib_device *ibdev, u32 port, int mask, + struct ib_port_modify *props) +#elif defined(MODIFY_PORT_V1) +int irdma_modify_port(struct ib_device *ibdev, u8 port, int mask, + struct ib_port_modify *props) +#endif +{ + if (port > 1) + return -EINVAL; + + return 0; +} + +/** + * irdma_query_pkey - Query partition key + * @ibdev: device pointer from stack + * @port: port number + * @index: index of pkey + * @pkey: pointer to store the pkey + */ +#ifdef QUERY_PKEY_V2 +int irdma_query_pkey(struct ib_device *ibdev, u32 port, u16 index, + u16 *pkey) +#elif defined(QUERY_PKEY_V1) +int irdma_query_pkey(struct ib_device *ibdev, u8 port, u16 index, + u16 *pkey) +#endif +{ + if (index >= IRDMA_PKEY_TBL_SZ) + return -EINVAL; + + *pkey = IRDMA_DEFAULT_PKEY; + return 0; +} + +#ifdef ROCE_PORT_IMMUTABLE_V2 +int irdma_roce_port_immutable(struct ib_device *ibdev, u32 port_num, + struct ib_port_immutable *immutable) +#elif defined(ROCE_PORT_IMMUTABLE_V1) +int irdma_roce_port_immutable(struct ib_device *ibdev, u8 port_num, + struct ib_port_immutable *immutable) +#endif +{ + struct ib_port_attr attr; + int err; + + immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP; + err = ib_query_port(ibdev, port_num, &attr); + if (err) + return err; + + immutable->max_mad_size = IB_MGMT_MAD_SIZE; + immutable->pkey_tbl_len = attr.pkey_tbl_len; + immutable->gid_tbl_len = attr.gid_tbl_len; + + return 0; +} + +#ifdef IW_PORT_IMMUTABLE_V2 +int irdma_iw_port_immutable(struct ib_device *ibdev, u32 port_num, + struct ib_port_immutable *immutable) +#elif defined(IW_PORT_IMMUTABLE_V1) +int irdma_iw_port_immutable(struct ib_device *ibdev, u8 port_num, + struct ib_port_immutable *immutable) +#endif +{ + struct ib_port_attr attr; + int err; + + immutable->core_cap_flags = RDMA_CORE_PORT_IWARP; + err = ib_query_port(ibdev, port_num, &attr); + if (err) + return err; + immutable->gid_tbl_len = 1; + + return 0; +} + +/** + * irdma_query_port - get port attributes + * @ibdev: device pointer from stack + * @port: port number for query + * @props: returning device attributes + */ +#ifdef QUERY_PORT_V2 +int irdma_query_port(struct ib_device *ibdev, u32 port, + struct ib_port_attr *props) +#elif defined(QUERY_PORT_V1) +int irdma_query_port(struct ib_device *ibdev, u8 port, + struct ib_port_attr *props) +#endif +{ + struct irdma_device *iwdev = to_iwdev(ibdev); + struct net_device *netdev = iwdev->netdev; + + /* no need to zero out pros here. done by caller */ + + props->max_mtu = IB_MTU_4096; + props->active_mtu = ib_mtu_int_to_enum(netdev->mtu); + props->lid = 1; + props->lmc = 0; + props->sm_lid = 0; + props->sm_sl = 0; + if (netif_carrier_ok(netdev) && netif_running(netdev)) { + props->state = IB_PORT_ACTIVE; + props->phys_state = IB_PORT_PHYS_STATE_LINK_UP; + } else { + props->state = IB_PORT_DOWN; + props->phys_state = IB_PORT_PHYS_STATE_DISABLED; + } + ib_get_eth_speed(ibdev, port, &props->active_speed, &props->active_width); + + if (rdma_protocol_roce(ibdev, 1)) { + props->gid_tbl_len = 32; + kc_set_props_ip_gid_caps(props); + props->pkey_tbl_len = IRDMA_PKEY_TBL_SZ; + } else { + props->gid_tbl_len = 1; + } + props->qkey_viol_cntr = 0; + props->port_cap_flags |= IB_PORT_CM_SUP | IB_PORT_REINIT_SUP; + props->max_msg_sz = iwdev->rf->sc_dev.hw_attrs.max_hw_outbound_msg_size; + + return 0; +} + +#ifdef ALLOC_HW_STATS_STRUCT_V1 +static const char *const irdma_hw_stat_names[] = { + /* gen1 - 32-bit */ + [IRDMA_HW_STAT_INDEX_IP4RXDISCARD] = "ip4InDiscards", + [IRDMA_HW_STAT_INDEX_IP4RXTRUNC] = "ip4InTruncatedPkts", + [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE] = "ip4OutNoRoutes", + [IRDMA_HW_STAT_INDEX_IP6RXDISCARD] = "ip6InDiscards", + [IRDMA_HW_STAT_INDEX_IP6RXTRUNC] = "ip6InTruncatedPkts", + [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE] = "ip6OutNoRoutes", + [IRDMA_HW_STAT_INDEX_RXVLANERR] = "rxVlanErrors", + /* gen1 - 64-bit */ + [IRDMA_HW_STAT_INDEX_IP4RXOCTS] = "ip4InOctets", + [IRDMA_HW_STAT_INDEX_IP4RXPKTS] = "ip4InPkts", + [IRDMA_HW_STAT_INDEX_IP4RXFRAGS] = "ip4InReasmRqd", + [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS] = "ip4InMcastPkts", + [IRDMA_HW_STAT_INDEX_IP4TXOCTS] = "ip4OutOctets", + [IRDMA_HW_STAT_INDEX_IP4TXPKTS] = "ip4OutPkts", + [IRDMA_HW_STAT_INDEX_IP4TXFRAGS] = "ip4OutSegRqd", + [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS] = "ip4OutMcastPkts", + [IRDMA_HW_STAT_INDEX_IP6RXOCTS] = "ip6InOctets", + [IRDMA_HW_STAT_INDEX_IP6RXPKTS] = "ip6InPkts", + [IRDMA_HW_STAT_INDEX_IP6RXFRAGS] = "ip6InReasmRqd", + [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS] = "ip6InMcastPkts", + [IRDMA_HW_STAT_INDEX_IP6TXOCTS] = "ip6OutOctets", + [IRDMA_HW_STAT_INDEX_IP6TXPKTS] = "ip6OutPkts", + [IRDMA_HW_STAT_INDEX_IP6TXFRAGS] = "ip6OutSegRqd", + [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS] = "ip6OutMcastPkts", + [IRDMA_HW_STAT_INDEX_RDMARXRDS] = "InRdmaReads", + [IRDMA_HW_STAT_INDEX_RDMARXSNDS] = "InRdmaSends", + [IRDMA_HW_STAT_INDEX_RDMARXWRS] = "InRdmaWrites", + [IRDMA_HW_STAT_INDEX_RDMATXRDS] = "OutRdmaReads", + [IRDMA_HW_STAT_INDEX_RDMATXSNDS] = "OutRdmaSends", + [IRDMA_HW_STAT_INDEX_RDMATXWRS] = "OutRdmaWrites", + [IRDMA_HW_STAT_INDEX_RDMAVBND] = "RdmaBnd", + [IRDMA_HW_STAT_INDEX_RDMAVINV] = "RdmaInv", + + /* gen2 - 32-bit */ + [IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED] = "cnpHandled", + [IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED] = "cnpIgnored", + [IRDMA_HW_STAT_INDEX_TXNPCNPSENT] = "cnpSent", + /* gen2 - 64-bit */ + [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS] = "ip4InMcastOctets", + [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS] = "ip4OutMcastOctets", + [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS] = "ip6InMcastOctets", + [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS] = "ip6OutMcastOctets", + [IRDMA_HW_STAT_INDEX_UDPRXPKTS] = "RxUDP", + [IRDMA_HW_STAT_INDEX_UDPTXPKTS] = "TxUDP", + [IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS] = "RxECNMrkd", + [IRDMA_HW_STAT_INDEX_TCPRTXSEG] = "RetransSegs", + [IRDMA_HW_STAT_INDEX_TCPRXOPTERR] = "InOptErrors", + [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR] = "InProtoErrors", + [IRDMA_HW_STAT_INDEX_TCPRXSEGS] = "InSegs", + [IRDMA_HW_STAT_INDEX_TCPTXSEG] = "OutSegs", + + /* gen3 */ + [IRDMA_HW_STAT_INDEX_RNR_SENT] = "RNR sent", + [IRDMA_HW_STAT_INDEX_RNR_RCVD] = "RNR received", + [IRDMA_HW_STAT_INDEX_RDMAORDLMTCNT] = "ord limit count", + [IRDMA_HW_STAT_INDEX_RDMAIRDLMTCNT] = "ird limit count", + [IRDMA_HW_STAT_INDEX_RDMARXATS] = "Rx ATS", + [IRDMA_HW_STAT_INDEX_RDMATXATS] = "Tx ATS", + [IRDMA_HW_STAT_INDEX_NAKSEQERR] = "Nak Sequence Error", + [IRDMA_HW_STAT_INDEX_NAKSEQERR_IMPLIED] = "Nak Sequence Error Implied", + [IRDMA_HW_STAT_INDEX_RTO] = "RTO", + [IRDMA_HW_STAT_INDEX_RXOOOPKTS] = "Rcvd Out of order packets", + [IRDMA_HW_STAT_INDEX_ICRCERR] = "CRC errors", +}; + +#endif /* ALLOC_HW_STATS_STRUCT_V1 */ +#ifdef ALLOC_HW_STATS_V3 +/** + * irdma_alloc_hw_port_stats - Allocate a hw stats structure + * @ibdev: device pointer from stack + * @port_num: port number + */ +struct rdma_hw_stats *irdma_alloc_hw_port_stats(struct ib_device *ibdev, + u32 port_num) +{ +#endif +#ifdef ALLOC_HW_STATS_V2 +/** + * irdma_alloc_hw_stats - Allocate a hw stats structure + * @ibdev: device pointer from stack + * @port_num: port number + */ +struct rdma_hw_stats *irdma_alloc_hw_stats(struct ib_device *ibdev, + u32 port_num) +{ +#endif +#ifdef ALLOC_HW_STATS_V1 +/** + * irdma_alloc_hw_stats - Allocate a hw stats structure + * @ibdev: device pointer from stack + * @port_num: port number + */ +struct rdma_hw_stats *irdma_alloc_hw_stats(struct ib_device *ibdev, + u8 port_num) +{ +#endif + struct irdma_device *iwdev = to_iwdev(ibdev); + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + + int num_counters = dev->hw_attrs.max_stat_idx; + unsigned long lifespan = RDMA_HW_STATS_DEFAULT_LIFESPAN; + + /* + * PFs get the default update lifespan, but VFs only update once + * per second + */ + if (!dev->privileged) + lifespan = 1000; +#ifdef ALLOC_HW_STATS_STRUCT_V2 + return rdma_alloc_hw_stats_struct(irdma_hw_stat_descs, num_counters, + lifespan); +#else + return rdma_alloc_hw_stats_struct(irdma_hw_stat_names, num_counters, + lifespan); +#endif +} + +/** + * irdma_get_hw_stats - Populates the rdma_hw_stats structure + * @ibdev: device pointer from stack + * @stats: stats pointer from stack + * @port_num: port number + * @index: which hw counter the stack is requesting we update + */ +#ifdef GET_HW_STATS_V2 +int irdma_get_hw_stats(struct ib_device *ibdev, + struct rdma_hw_stats *stats, u32 port_num, + int index) +#elif defined(GET_HW_STATS_V1) +int irdma_get_hw_stats(struct ib_device *ibdev, + struct rdma_hw_stats *stats, u8 port_num, + int index) +#endif +{ + struct irdma_device *iwdev = to_iwdev(ibdev); + struct irdma_dev_hw_stats *hw_stats = &iwdev->vsi.pestat->hw_stats; + + if (iwdev->rf->rdma_ver >= IRDMA_GEN_2) + irdma_cqp_gather_stats_cmd(&iwdev->rf->sc_dev, iwdev->vsi.pestat, true); + else + irdma_cqp_gather_stats_gen1(&iwdev->rf->sc_dev, iwdev->vsi.pestat); + + memcpy(&stats->value[0], hw_stats, sizeof(u64) * stats->num_counters); + + return stats->num_counters; +} + +/** + * irdma_query_gid - Query port GID + * @ibdev: device pointer from stack + * @port: port number + * @index: Entry index + * @gid: Global ID + */ +#ifdef QUERY_GID_V2 +int irdma_query_gid(struct ib_device *ibdev, u32 port, int index, + union ib_gid *gid) +#elif defined(QUERY_GID_V1) +int irdma_query_gid(struct ib_device *ibdev, u8 port, int index, + union ib_gid *gid) +#endif +{ + struct irdma_device *iwdev = to_iwdev(ibdev); + + memset(gid->raw, 0, sizeof(gid->raw)); + ether_addr_copy(gid->raw, iwdev->netdev->dev_addr); + + return 0; +} + +#ifdef GET_LINK_LAYER_V2 +enum rdma_link_layer irdma_get_link_layer(struct ib_device *ibdev, + u32 port_num) +#elif defined(GET_LINK_LAYER_V1) +enum rdma_link_layer irdma_get_link_layer(struct ib_device *ibdev, + u8 port_num) +#endif +{ + return IB_LINK_LAYER_ETHERNET; +} + +#ifdef IB_MTU_CONVERSIONS + +inline enum ib_mtu ib_mtu_int_to_enum(int mtu) +{ + if (mtu >= 4096) + return IB_MTU_4096; + else if (mtu >= 2048) + return IB_MTU_2048; + else if (mtu >= 1024) + return IB_MTU_1024; + else if (mtu >= 512) + return IB_MTU_512; + else + return IB_MTU_256; +} +#endif + +#ifdef UVERBS_CMD_MASK +inline void kc_set_roce_uverbs_cmd_mask(struct irdma_device *iwdev) +{ + iwdev->ibdev.uverbs_cmd_mask |= + BIT_ULL(IB_USER_VERBS_CMD_ATTACH_MCAST) | + BIT_ULL(IB_USER_VERBS_CMD_CREATE_AH) | + BIT_ULL(IB_USER_VERBS_CMD_DESTROY_AH) | + BIT_ULL(IB_USER_VERBS_CMD_DETACH_MCAST); +} + +inline void kc_set_rdma_uverbs_cmd_mask(struct irdma_device *iwdev) +{ + iwdev->ibdev.uverbs_cmd_mask = + BIT_ULL(IB_USER_VERBS_CMD_GET_CONTEXT) | + BIT_ULL(IB_USER_VERBS_CMD_QUERY_DEVICE) | + BIT_ULL(IB_USER_VERBS_CMD_QUERY_PORT) | + BIT_ULL(IB_USER_VERBS_CMD_ALLOC_PD) | + BIT_ULL(IB_USER_VERBS_CMD_DEALLOC_PD) | + BIT_ULL(IB_USER_VERBS_CMD_REG_MR) | + BIT_ULL(IB_USER_VERBS_CMD_REREG_MR) | + BIT_ULL(IB_USER_VERBS_CMD_DEREG_MR) | + BIT_ULL(IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) | + BIT_ULL(IB_USER_VERBS_CMD_CREATE_CQ) | + BIT_ULL(IB_USER_VERBS_CMD_RESIZE_CQ) | + BIT_ULL(IB_USER_VERBS_CMD_DESTROY_CQ) | + BIT_ULL(IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) | + BIT_ULL(IB_USER_VERBS_CMD_CREATE_QP) | + BIT_ULL(IB_USER_VERBS_CMD_MODIFY_QP) | + BIT_ULL(IB_USER_VERBS_CMD_QUERY_QP) | + BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ) | + BIT_ULL(IB_USER_VERBS_CMD_DESTROY_QP) | + BIT_ULL(IB_USER_VERBS_CMD_POST_RECV) | + BIT_ULL(IB_USER_VERBS_CMD_POST_SEND); + if (iwdev->rf->rdma_ver >= IRDMA_GEN_3) + iwdev->ibdev.uverbs_cmd_mask |= + BIT_ULL(IB_USER_VERBS_CMD_ALLOC_MW) | + BIT_ULL(IB_USER_VERBS_CMD_BIND_MW) | + BIT_ULL(IB_USER_VERBS_CMD_DEALLOC_MW) | + BIT_ULL(IB_USER_VERBS_CMD_CREATE_SRQ) | + BIT_ULL(IB_USER_VERBS_CMD_MODIFY_SRQ) | + BIT_ULL(IB_USER_VERBS_CMD_QUERY_SRQ) | + BIT_ULL(IB_USER_VERBS_CMD_DESTROY_SRQ) | + BIT_ULL(IB_USER_VERBS_CMD_POST_SRQ_RECV); + iwdev->ibdev.uverbs_ex_cmd_mask = + BIT_ULL(IB_USER_VERBS_EX_CMD_MODIFY_QP) | + BIT_ULL(IB_USER_VERBS_EX_CMD_QUERY_DEVICE); + + if (iwdev->rf->rdma_ver >= IRDMA_GEN_2) + iwdev->ibdev.uverbs_ex_cmd_mask |= BIT_ULL(IB_USER_VERBS_EX_CMD_CREATE_CQ); +} +#endif + +#ifdef ENABLE_DUP_CM_NAME_WA +static DEFINE_IDA(irdma_devname_ida); +void irdma_release_ib_devname(struct irdma_device *iwdev) +{ + if (iwdev->name_id < 0) + return; + ida_simple_remove(&irdma_devname_ida, iwdev->name_id); +} + +char *irdma_set_ib_devname(struct irdma_device *iwdev) +{ + const char *name = iwdev->lag_mode ? "irdma_bond%d" : "irdma%d"; + int i; + + i = ida_alloc(&irdma_devname_ida, GFP_KERNEL); + iwdev->name_id = i; + if (i < 0) + strcpy(iwdev->ib_devname, name); + else + snprintf(iwdev->ib_devname, sizeof(iwdev->ib_devname), name, i); + return iwdev->ib_devname; +} + +#else /* ENABLE_DUP_CM_NAME_WA */ +void irdma_release_ib_devname(struct irdma_device *iwdev) +{ +} + +char *irdma_set_ib_devname(struct irdma_device *iwdev) +{ + const char *name = iwdev->lag_mode ? "irdma_bond%d" : "irdma%d"; + + strcpy(iwdev->ib_devname, name); + + return iwdev->ib_devname; +} +#endif /* ENABLE_DUP_CM_NAME_WA */ +#ifdef IB_GET_ETH_SPEED + +int ib_get_eth_speed(struct ib_device *ibdev, u32 port_num, u8 *speed, u8 *width) +{ + struct net_device *netdev = ibdev->get_netdev(ibdev, port_num); + u32 netdev_speed; + struct ethtool_cmd cmd; + int rc; + + if (!netdev) + return -ENODEV; + + rtnl_lock(); + rc = __ethtool_get_settings(netdev, &cmd); + rtnl_unlock(); + netdev_speed = ethtool_cmd_speed(&cmd); + dev_put(netdev); + + if (rc || netdev_speed == (u32)SPEED_UNKNOWN) { + netdev_speed = SPEED_1000; + pr_warn("%s speed is unknown, defaulting to %u\n", netdev->name, + netdev_speed); + } + if (netdev_speed <= SPEED_1000) { + *width = IB_WIDTH_1X; + *speed = IB_SPEED_SDR; + } else if (netdev_speed <= SPEED_10000) { + *width = IB_WIDTH_1X; + *speed = IB_SPEED_FDR10; + } else if (netdev_speed <= SPEED_20000) { + *width = IB_WIDTH_4X; + *speed = IB_SPEED_DDR; + } else if (netdev_speed <= SPEED_25000) { + *width = IB_WIDTH_1X; + *speed = IB_SPEED_EDR; + } else if (netdev_speed <= SPEED_40000) { + *width = IB_WIDTH_4X; + *speed = IB_SPEED_FDR10; + } else { + *width = IB_WIDTH_4X; + *speed = IB_SPEED_EDR; + } + + return 0; +} +#endif /* IB_GET_ETH_SPEED */ +#ifdef ETHER_ADDR_TO_U64 + +u64 ether_addr_to_u64(const u8 *eth_add) +{ + int idx; + u64 u64_eth_add; + + for (idx = 0, u64_eth_add = 0; idx < ETH_ALEN; idx++) + u64_eth_add = u64_eth_add << 8 | eth_add[idx]; + + return u64_eth_add; +} +#endif /* ETHER_ADDR_TO_U64 */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/irdma_kcompat.h b/drivers/intel/irdma-1.14.33/src/irdma/irdma_kcompat.h new file mode 100644 index 000000000..56e804783 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/irdma_kcompat.h @@ -0,0 +1,847 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2018 - 2024 Intel Corporation */ +#ifndef IRDMA_KCOMPAT_H +#define IRDMA_KCOMPAT_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0) +#include +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(3, 4, 0) +#include +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) +#include +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 4, 0) +#include +#else +#include +#endif + +#if !defined(__OFED_BUILD__) && !defined(__OFED_4_8__) +#include "irdma_kcompat_gen.h" +#endif +#include "distro_ver.h" + +#if defined(__OFED_BUILD__) || defined(__OFED_4_8__) +#include "ofed_kcompat.h" +#elif defined(RHEL_RELEASE_CODE) +#include "rhel_kcompat.h" +#elif defined(CONFIG_SUSE_KERNEL) +#include "suse_kcompat.h" +#elif defined(UTS_UBUNTU_RELEASE_ABI) +#include "ubuntu_kcompat.h" +#elif defined(ORACLE_REL) +#include "oracle_kcompat.h" +#else +#include "linux_kcompat.h" +#endif + +#ifndef MAX_PAGE_ORDER +#define MAX_PAGE_ORDER MAX_ORDER +#endif + +#ifndef IB_QP_ATTR_STANDARD_BITS +#define IB_QP_ATTR_STANDARD_BITS GENMASK(20, 0) +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) +#define ENABLE_DUP_CM_NAME_WA +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) */ + +#define TASKLET_DATA_TYPE unsigned long +#define TASKLET_FUNC_TYPE void (*)(TASKLET_DATA_TYPE) + +#define tasklet_setup(tasklet, callback) \ + tasklet_init((tasklet), (TASKLET_FUNC_TYPE)(callback), \ + (TASKLET_DATA_TYPE)(tasklet)) + +#define from_tasklet(var, callback_tasklet, tasklet_fieldname) \ + container_of(callback_tasklet, typeof(*var), tasklet_fieldname) + +/* Mapping IRDMA driver ID to I40IW till we are in k.org */ +#define RDMA_DRIVER_IRDMA 9 + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)) +#define TIMER_DATA_TYPE unsigned long +#define TIMER_FUNC_TYPE void (*)(TIMER_DATA_TYPE) + +#define timer_setup(timer, callback, flags) \ + __setup_timer((timer), (TIMER_FUNC_TYPE)(callback), \ + (TIMER_DATA_TYPE)(timer), (flags)) + +#define from_timer(var, callback_timer, timer_fieldname) \ + container_of(callback_timer, typeof(*var), timer_fieldname) +#endif /* (LINUX_VERSION_CODE < KERNEL_VERSION(4, 14, 0)) */ + +#if !defined(__OFED_BUILD__) && !defined(__OFED_4_8__) +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0) +#define dma_alloc_coherent dma_zalloc_coherent +#endif +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 0, 0) +#define IB_GET_NETDEV_OP_NOT_DEPRECATED +#endif + +#ifdef USE_KMAP +#define kmap_local_page kmap +#define kunmap_local(sq_base) kunmap(iwqp->page) +#endif + +/*************************QUERY PKEY*********************************************/ +/* https://lore.kernel.org/linux-rdma/9DD61F30A802C4429A01CA4200E302A7010659C72C@fmsmsx124.amr.corp.intel.com/ + * This series removes query pkey callback from iWARP providers as it really + * is not required as per the protocol. Also IB core is updated to not expose + * pkey related sysfs attributes for iw_devices. Prior to 5.9, query pkey is mandatory + * for iWARP providers. + */ +#ifdef IB_IW_PKEY +#ifdef QUERY_PKEY_V1 +static inline int irdma_iw_query_pkey(struct ib_device *ibdev, u8 port, u16 index, + u16 *pkey) +#elif defined(QUERY_PKEY_V2) +static inline int irdma_iw_query_pkey(struct ib_device *ibdev, u32 port, u16 index, + u16 *pkey) +#endif +{ + *pkey = 0; + return 0; +} +#endif +/*******************************************************************************/ + +struct dst_entry *irdma_get_fl6_dst(struct sockaddr_in6 *, struct sockaddr_in6 *); +struct neighbour *irdma_get_neigh_ipv6(struct dst_entry *, struct sockaddr_in6 *); +struct neighbour *irdma_get_neigh_ipv4(struct rtable *, __be32 *); + +struct irdma_mr; +struct irdma_cq; +struct irdma_cq_buf; +struct irdma_srq; +struct irdma_ucontext; +void kc_set_loc_seq_num_mss(struct irdma_cm_node *cm_node); +u32 irdma_create_stag(struct irdma_device *iwdev); +void irdma_free_stag(struct irdma_device *iwdev, u32 stag); +int irdma_hw_alloc_mw(struct irdma_device *iwdev, struct irdma_mr *iwmr); +void irdma_cq_free_rsrc(struct irdma_pci_f *rf, struct irdma_cq *iwcq); +void irdma_srq_free_rsrc(struct irdma_pci_f *rf, struct irdma_srq *iwsrq); +int irdma_process_resize_list(struct irdma_cq *iwcq, struct irdma_device *iwdev, struct irdma_cq_buf *lcqe_buf); + +#ifdef IRDMA_SET_DRIVER_ID +#define kc_set_driver_id(ibdev) ibdev.driver_id = RDMA_DRIVER_I40IW +#else +#define kc_set_driver_id(x) +#endif /* IRDMA_SET_DRIVER_ID */ +/*****************************************************************************/ + + +/*********************************************************/ +#ifndef ether_addr_copy +#define ether_addr_copy(mac_addr, new_mac_addr) memcpy(mac_addr, new_mac_addr, ETH_ALEN) +#endif +#ifndef eth_zero_addr +#define eth_zero_addr(mac_addr) memset(mac_addr, 0x00, ETH_ALEN) +#endif + +#define bitmap_zalloc(nbits, flags) kcalloc(BITS_TO_LONGS(nbits), sizeof(unsigned long), flags) + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 35) +#define irdma_for_each_ipv6_addr(ifp, tmp, idev) list_for_each_entry_safe(ifp, tmp, &idev->addr_list, if_list) +#else +#define irdma_for_each_ipv6_addr(ifp, tmp, idev) for (ifp = idev->addr_list; ifp != NULL; ifp = ifp->if_next) +#endif /* >= 2.6.35 */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 9, 0) +#define netdev_master_upper_dev_get irdma_netdev_master_upper_dev_get +struct net_device *irdma_netdev_master_upper_dev_get(struct net_device *); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 1, 0) +#define neigh_release(neigh) +#endif /* < 3.1.0 */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 39) +#define ip_route_output irdma_ip_route_output +struct rtable *irdma_ip_route_output(struct net *, __be32, __be32, u8, int); +#endif /* < 2.6.39 */ +#endif /* < 3.9.0 */ + +#ifdef IB_FW_VERSION_NAME_MAX +void irdma_get_dev_fw_str(struct ib_device *dev, char *str); +#else +void irdma_get_dev_fw_str(struct ib_device *dev, char *str, size_t str_len); +#endif /* IB_FW_VERSION_NAME_MAX */ + +/*****************************************************************************/ + +struct dst_entry *irdma_get_fl6_dst(struct sockaddr_in6 *src_addr, + struct sockaddr_in6 *dst_addr); +struct neighbour *irdma_get_neigh_ipv6(struct dst_entry *dst, + struct sockaddr_in6 *dst_ipaddr); +struct neighbour *irdma_get_neigh_ipv4(struct rtable *rt, __be32 *dst_ipaddr); + +#ifdef IB_IW_MANDATORY_AH_OP +#ifdef CREATE_AH_VER_0 +struct ib_ah *irdma_create_ah_stub(struct ib_pd *ibpd, + struct ib_ah_attr *attr); +#elif defined(CREATE_AH_VER_1_1) +struct ib_ah *irdma_create_ah_stub(struct ib_pd *ibpd, + struct ib_ah_attr *attr, + struct ib_udata *udata); +#elif defined(CREATE_AH_VER_1_2) +struct ib_ah *irdma_create_ah_stub(struct ib_pd *ibpd, + struct rdma_ah_attr *attr, + struct ib_udata *udata); +#endif + +int irdma_destroy_ah_stub(struct ib_ah *ibah); +#endif /* IB_IW_MANDATORY_AH_OP */ + +#ifdef CREATE_AH_VER_5 +int irdma_create_ah_v2(struct ib_ah *ib_ah, + struct rdma_ah_attr *attr, u32 flags, + struct ib_udata *udata); +int irdma_create_ah(struct ib_ah *ibah, + struct rdma_ah_init_attr *attr, + struct ib_udata *udata); +#endif + +#ifdef CREATE_AH_VER_4 +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, + struct rdma_ah_attr *attr, + struct ib_udata *udata); +#endif + +#ifdef CREATE_AH_VER_3 +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, + struct rdma_ah_attr *attr, + u32 flags, + struct ib_udata *udata); +#endif + +#ifdef CREATE_AH_VER_2 +int irdma_create_ah(struct ib_ah *ib_ah, + struct rdma_ah_attr *attr, u32 flags, + struct ib_udata *udata); +#endif + +#ifdef CREATE_AH_VER_1_1 +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, + struct ib_ah_attr *attr, + struct ib_udata *udata); +void irdma_ether_copy(u8 *dmac, struct ib_ah_attr *attr); +#endif +#if defined(CREATE_AH_VER_1_2) +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, + struct rdma_ah_attr *attr, + struct ib_udata *udata); +void irdma_ether_copy(u8 *dmac, struct rdma_ah_attr *attr); +#endif + +#if defined(CREATE_AH_VER_0) +struct ib_ah *irdma_create_ah(struct ib_pd *ibpd, + struct ib_ah_attr *attr); +#endif + +#ifdef DESTROY_AH_VER_4 +int irdma_destroy_ah(struct ib_ah *ibah, u32 ah_flags); +#endif + +#ifdef DESTROY_AH_VER_3 +void irdma_destroy_ah(struct ib_ah *ibah, u32 flags); +#endif + +#ifdef DESTROY_AH_VER_2 +int irdma_destroy_ah(struct ib_ah *ibah, u32 flags); +#endif + +#ifdef DESTROY_AH_VER_1 +int irdma_destroy_ah(struct ib_ah *ibah); +#endif + +#ifdef CREATE_CQ_VER_3 +int irdma_create_cq(struct ib_cq *ibcq, + const struct ib_cq_init_attr *attr, + struct ib_udata *udata); +#endif + +#ifdef CREATE_CQ_VER_2 +struct ib_cq *irdma_create_cq(struct ib_device *ibdev, + const struct ib_cq_init_attr *attr, + struct ib_udata *udata); +#endif + +#ifdef CREATE_CQ_VER_1 +struct ib_cq *irdma_create_cq(struct ib_device *ibdev, + const struct ib_cq_init_attr *attr, + struct ib_ucontext *context, + struct ib_udata *udata); +#endif + +/* functions called by irdma_create_qp and irdma_free_qp_rsrc */ +int irdma_validate_qp_attrs(struct ib_qp_init_attr *init_attr, + struct irdma_device *iwdev); + +void irdma_setup_virt_qp(struct irdma_device *iwdev, + struct irdma_qp *iwqp, + struct irdma_qp_init_info *init_info); + +int irdma_setup_kmode_qp(struct irdma_device *iwdev, + struct irdma_qp *iwqp, + struct irdma_qp_init_info *info, + struct ib_qp_init_attr *init_attr); + +int irdma_setup_umode_qp(struct ib_udata *udata, + struct irdma_device *iwdev, + struct irdma_qp *iwqp, + struct irdma_qp_init_info *info, + struct ib_qp_init_attr *init_attr); + +void irdma_roce_fill_and_set_qpctx_info(struct irdma_qp *iwqp, + struct irdma_qp_host_ctx_info *ctx_info); + +void irdma_iw_fill_and_set_qpctx_info(struct irdma_qp *iwqp, + struct irdma_qp_host_ctx_info *ctx_info); + +int irdma_cqp_create_qp_cmd(struct irdma_qp *iwqp); + +void irdma_free_qp_rsrc(struct irdma_qp *iwqp); + +void irdma_dealloc_push_page(struct irdma_pci_f *rf, + struct irdma_qp *iwqp); + +#ifdef IRDMA_ALLOC_MW_VER_2 +int irdma_alloc_mw(struct ib_mw *ibmw, struct ib_udata *udata); +#endif + +#ifdef IRDMA_ALLOC_MW_VER_1 +struct ib_mw *irdma_alloc_mw(struct ib_pd *pd, enum ib_mw_type type, + struct ib_udata *udata); +#endif + +#ifdef CREATE_QP_VER_2 +int irdma_create_qp(struct ib_qp *ibqp, + struct ib_qp_init_attr *init_attr, + struct ib_udata *udata); +#endif + +#ifdef CREATE_QP_VER_1 +struct ib_qp *irdma_create_qp(struct ib_pd *ibpd, + struct ib_qp_init_attr *init_attr, + struct ib_udata *udata); +#endif + +int irdma_hw_alloc_stag(struct irdma_device *iwdev, + struct irdma_mr *iwmr); + +#ifdef IRDMA_ALLOC_MR_VER_1 +struct ib_mr *irdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, + u32 max_num_sg, struct ib_udata *udata); +#endif + +#ifdef IRDMA_ALLOC_MR_VER_0 +struct ib_mr *irdma_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type, u32 max_num_sg); +#endif + +#ifdef ALLOC_UCONTEXT_VER_2 +int irdma_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata); +#endif + +#ifdef ALLOC_UCONTEXT_VER_1 +struct ib_ucontext *irdma_alloc_ucontext(struct ib_device *ibdev, struct ib_udata *udata); +#endif + +#ifdef DEALLOC_UCONTEXT_VER_2 +void irdma_dealloc_ucontext(struct ib_ucontext *context); +#endif + +#ifdef DEALLOC_UCONTEXT_VER_1 +int irdma_dealloc_ucontext(struct ib_ucontext *context); +#endif + +#if defined(ETHER_COPY_VER_2) +void irdma_ether_copy(u8 *dmac, struct rdma_ah_attr *attr); +#endif + +#if defined(ETHER_COPY_VER_1) +void irdma_ether_copy(u8 *dmac, struct ib_ah_attr *attr); +#endif + +#ifdef ALLOC_PD_VER_3 +int irdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); +#endif + +#ifdef ALLOC_PD_VER_2 +int irdma_alloc_pd(struct ib_pd *pd, + struct ib_ucontext *context, + struct ib_udata *udata); +#endif + +#ifdef ALLOC_PD_VER_1 +struct ib_pd *irdma_alloc_pd(struct ib_device *ibdev, + struct ib_ucontext *context, + struct ib_udata *udata); +#endif + +#ifdef DEALLOC_PD_VER_4 +int irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata); +#endif + +#ifdef DEALLOC_PD_VER_3 +void irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata); +#endif + +#ifdef DEALLOC_PD_VER_2 +void irdma_dealloc_pd(struct ib_pd *ibpd); +#endif + +#ifdef DEALLOC_PD_VER_1 +int irdma_dealloc_pd(struct ib_pd *ibpd); +#endif + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); + +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#ifdef IRDMA_DESTROY_CQ_VER_4 +int irdma_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); +#endif + +#ifdef IRDMA_DESTROY_CQ_VER_3 +void irdma_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); +#endif + +#ifdef IRDMA_DESTROY_CQ_VER_2 +int irdma_destroy_cq(struct ib_cq *ib_cq, struct ib_udata *udata); +#endif + +#ifdef IRDMA_DESTROY_CQ_VER_1 +int irdma_destroy_cq(struct ib_cq *ib_cq); +#endif + +#ifdef IRDMA_DESTROY_SRQ_VER_3 +int irdma_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); +#endif + +#ifdef IRDMA_DESTROY_SRQ_VER_2 +void irdma_destroy_srq(struct ib_srq *ibsrq, struct ib_udata *udata); +#endif + +#ifdef IRDMA_DESTROY_SRQ_VER_1 +int irdma_destroy_srq(struct ib_srq *ibsrq); +#endif + +#ifdef DESTROY_QP_VER_2 +int irdma_destroy_qp(struct ib_qp *ibqp, struct ib_udata *udata); +#define kc_irdma_destroy_qp(ibqp, udata) irdma_destroy_qp(ibqp, udata) +#endif + +#ifdef DESTROY_QP_VER_1 +int irdma_destroy_qp(struct ib_qp *ibqp); +#define kc_irdma_destroy_qp(ibqp, udata) irdma_destroy_qp(ibqp) +#endif + +#ifdef DEREG_MR_VER_2 +int irdma_dereg_mr(struct ib_mr *ib_mr, struct ib_udata *udata); +#endif + +#ifdef DEREG_MR_VER_1 +int irdma_dereg_mr(struct ib_mr *ib_mr); +#endif + +int irdma_hwdereg_mr(struct ib_mr *ib_mr); + +#ifdef REREG_MR_VER_1 +int irdma_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, u64 len, + u64 virt, int new_access, struct ib_pd *new_pd, + struct ib_udata *udata); +#endif + +#ifdef REREG_MR_VER_2 +struct ib_mr *irdma_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start, + u64 len, u64 virt, int new_access, + struct ib_pd *new_pd, + struct ib_udata *udata); +#endif + +int irdma_hwreg_mr(struct irdma_device *iwdev, struct irdma_mr *iwmr, + u16 access); + +struct ib_mr *irdma_rereg_mr_trans(struct irdma_mr *iwmr, u64 start, u64 len, + u64 virt, struct ib_udata *udata); + +struct irdma_pbl *irdma_get_pbl(unsigned long va, + struct list_head *pbl_list); + +#ifndef HAVE_IB_UMEM_NUM_DMA_BLOCKS +/* Introduced in this series https://lore.kernel.org/linux-rdma/0-v2-270386b7e60b+28f4-umem_1_jgg@nvidia.com/ + * An irdma version helper doing same for older functions with difference that iova is passed in + * as opposed to derived from umem->iova. + */ +static inline size_t irdma_ib_umem_num_dma_blocks(struct ib_umem *umem, unsigned long pgsz, u64 iova) +{ + /* some older OFED distros do not have ALIGN_DOWN */ +#ifndef ALIGN_DOWN +#define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) +#endif + + return (size_t)((ALIGN(iova + umem->length, pgsz) - + ALIGN_DOWN(iova, pgsz))) / pgsz; +} +#endif + +#ifdef NEED_RDMA_UMEM_BLOCK_ITER_NEXT +/* + * IB block DMA iterator + * + * Iterates the DMA-mapped SGL in contiguous memory blocks aligned + * to a HW supported page size. + */ +struct kc_ib_block_iter { + /* internal states */ + struct scatterlist *__sg; /* sg holding the current aligned block */ + dma_addr_t __dma_addr; /* unaligned DMA address of this block */ + size_t __sg_numblocks; /* ib_umem_num_dma_blocks() */ + unsigned int __sg_nents; /* number of SG entries */ + unsigned int __sg_advance; /* number of bytes to advance in sg in next step */ + unsigned int __pg_bit; /* alignment of current block */ +}; + +void kc__rdma_block_iter_start(struct kc_ib_block_iter *biter, + struct scatterlist *sglist, + unsigned int nents, + unsigned long pgsz); +bool kc__rdma_block_iter_next(struct kc_ib_block_iter *biter); + +/** + * rdma_block_iter_dma_address - get the aligned dma address of the current + * block held by the block iterator. + * @biter: block iterator holding the memory block + */ +static inline dma_addr_t +kc_rdma_block_iter_dma_address(struct kc_ib_block_iter *biter) +{ + return biter->__dma_addr & ~(BIT_ULL(biter->__pg_bit) - 1); +} + +/** + * rdma_for_each_block - iterate over contiguous memory blocks of the sg list + * @sglist: sglist to iterate over + * @biter: block iterator holding the memory block + * @nents: maximum number of sg entries to iterate over + * @pgsz: best HW supported page size to use + * + * Callers may use rdma_block_iter_dma_address() to get each + * blocks aligned DMA address. + */ +#define kc_rdma_for_each_block(sglist, biter, nents, pgsz) \ + for (kc__rdma_block_iter_start(biter, sglist, nents, pgsz); \ + kc__rdma_block_iter_next(biter);) + +static inline void +kc__rdma_umem_block_iter_start(struct kc_ib_block_iter *biter, + struct ib_umem *umem, + unsigned long pgsz) +{ +#ifdef HAVE_IB_UMEM_SG_HEAD + kc__rdma_block_iter_start(biter, umem->sg_head.sgl, umem->nmap, + pgsz); +#else + kc__rdma_block_iter_start(biter, umem->sgt_append.sgt.sgl, + umem->sgt_append.sgt.nents, pgsz); +#endif /* HAVE_IB_UMEM_SG_HEAD */ + biter->__sg_advance = ib_umem_offset(umem) & ~(pgsz - 1); +#ifdef HAVE_IB_UMEM_NUM_DMA_BLOCKS + biter->__sg_numblocks = ib_umem_num_dma_blocks(umem, pgsz); +#else + biter->__sg_numblocks = + irdma_ib_umem_num_dma_blocks(umem, pgsz, umem->address); +#endif +} + +static inline bool +kc__rdma_umem_block_iter_next(struct kc_ib_block_iter *biter) +{ + return kc__rdma_block_iter_next(biter) && biter->__sg_numblocks--; +} + + +/** + * rdma_umem_for_each_dma_block - iterate over contiguous DMA blocks of the umem + * @umem: umem to iterate over + * @pgsz: Page size to split the list into + * + * pgsz must be <= PAGE_SIZE or computed by ib_umem_find_best_pgsz(). The + * returned DMA blocks will be aligned to pgsz and span the range: + * ALIGN_DOWN(umem->address, pgsz) to ALIGN(umem->address + umem->length, pgsz) + */ +#define kc_rdma_umem_for_each_dma_block(umem, biter, pgsz) \ + for (kc__rdma_umem_block_iter_start(biter, umem, pgsz); \ + kc__rdma_umem_block_iter_next(biter);) + +#undef rdma_umem_for_each_dma_block +#define rdma_umem_for_each_dma_block kc_rdma_umem_for_each_dma_block +#define ib_block_iter kc_ib_block_iter +#define rdma_block_iter_dma_address kc_rdma_block_iter_dma_address +#define __rdma_umem_block_iter_start kc__rdma_umem_block_iter_start +#define __rdma_block_iter_next kc__rdma_block_iter_next + +#endif /* NEED_RDMA_UMEM_BLOCK_ITER_NEXT */ + + +#ifdef COPY_USER_PGADDR_VER_1 +void irdma_copy_user_pgaddrs(struct irdma_mr *iwmr, u64 *pbl, + enum irdma_pble_level level); +#endif + +void irdma_del_memlist(struct irdma_mr *iwmr, + struct irdma_ucontext *ucontext); + +void irdma_unregister_rdma_device(struct ib_device *ibdev); +#ifndef RDMA_MMAP_DB_SUPPORT +int rdma_user_mmap_io(struct ib_ucontext *ucontext, struct vm_area_struct *vma, + unsigned long pfn, unsigned long size, pgprot_t prot); +#endif +void irdma_release_ib_devname(struct irdma_device *iwdev); +char *irdma_set_ib_devname(struct irdma_device *iwdev); +void irdma_disassociate_ucontext(struct ib_ucontext *context); +int kc_irdma_set_roce_cm_info(struct irdma_qp *iwqp, + struct ib_qp_attr *attr, + u16 *vlan_id); +int kc_irdma_create_sysfs_file(struct ib_device *ibdev); +struct irdma_device *kc_irdma_get_device(struct net_device *netdev); +void kc_irdma_put_device(struct irdma_device *iwdev); +void kc_set_roce_uverbs_cmd_mask(struct irdma_device *iwdev); +void kc_set_rdma_uverbs_cmd_mask(struct irdma_device *iwdev); + +#ifdef QUERY_GID_ROCE_V2 +int irdma_query_gid_roce(struct ib_device *ibdev, u32 port, int index, + union ib_gid *gid); +#elif defined(QUERY_GID_ROCE_V1) +int irdma_query_gid_roce(struct ib_device *ibdev, u8 port, int index, + union ib_gid *gid); +#endif + +#ifdef MODIFY_PORT_V2 +int irdma_modify_port(struct ib_device *ibdev, u32 port, int mask, + struct ib_port_modify *props); +#elif defined(MODIFY_PORT_V1) +int irdma_modify_port(struct ib_device *ibdev, u8 port, int mask, + struct ib_port_modify *props); +#endif + +#ifdef QUERY_PKEY_V2 +int irdma_query_pkey(struct ib_device *ibdev, u32 port, u16 index, + u16 *pkey); +#elif defined(QUERY_PKEY_V1) +int irdma_query_pkey(struct ib_device *ibdev, u8 port, u16 index, + u16 *pkey); +#endif + +#ifdef ROCE_PORT_IMMUTABLE_V2 +int irdma_roce_port_immutable(struct ib_device *ibdev, u32 port_num, + struct ib_port_immutable *immutable); +#elif defined(ROCE_PORT_IMMUTABLE_V1) +int irdma_roce_port_immutable(struct ib_device *ibdev, u8 port_num, + struct ib_port_immutable *immutable); +#endif + +#ifdef IW_PORT_IMMUTABLE_V2 +int irdma_iw_port_immutable(struct ib_device *ibdev, u32 port_num, + struct ib_port_immutable *immutable); +#elif defined(IW_PORT_IMMUTABLE_V1) +int irdma_iw_port_immutable(struct ib_device *ibdev, u8 port_num, + struct ib_port_immutable *immutable); +#endif + +#ifdef ALLOC_HW_STATS_V3 +struct rdma_hw_stats *irdma_alloc_hw_port_stats(struct ib_device *ibdev, + u32 port_num); +#endif +#ifdef ALLOC_HW_STATS_V2 +struct rdma_hw_stats *irdma_alloc_hw_stats(struct ib_device *ibdev, + u32 port_num); +#endif +#ifdef ALLOC_HW_STATS_V1 +struct rdma_hw_stats *irdma_alloc_hw_stats(struct ib_device *ibdev, + u8 port_num); +#endif + +#ifdef GET_HW_STATS_V2 +int irdma_get_hw_stats(struct ib_device *ibdev, + struct rdma_hw_stats *stats, u32 port_num, + int index); +#elif defined(GET_HW_STATS_V1) +int irdma_get_hw_stats(struct ib_device *ibdev, + struct rdma_hw_stats *stats, u8 port_num, + int index); +#endif + +#ifdef QUERY_GID_V2 +int irdma_query_gid(struct ib_device *ibdev, u32 port, int index, + union ib_gid *gid); +#elif defined(QUERY_GID_V1) +int irdma_query_gid(struct ib_device *ibdev, u8 port, int index, + union ib_gid *gid); +#endif + +#ifdef GET_LINK_LAYER_V2 +enum rdma_link_layer irdma_get_link_layer(struct ib_device *ibdev, + u32 port_num); +#elif defined(GET_LINK_LAYER_V1) +enum rdma_link_layer irdma_get_link_layer(struct ib_device *ibdev, + u8 port_num); +#endif + +#ifdef QUERY_PORT_V2 +int irdma_query_port(struct ib_device *ibdev, u32 port, + struct ib_port_attr *props); +#elif defined(QUERY_PORT_V1) +int irdma_query_port(struct ib_device *ibdev, u8 port, + struct ib_port_attr *props); +#endif + +u16 kc_rdma_get_udp_sport(u32 fl, u32 lqpn, u32 rqpn); +void irdma_clean_cqes(struct irdma_qp *iwqp, struct irdma_cq *iwcq); +void irdma_remove_push_mmap_entries(struct irdma_qp *iwqp); +#ifndef NETDEV_TO_IBDEV_SUPPORT +struct ib_device *ib_device_get_by_netdev(struct net_device *ndev, int driver_id); +void ib_unregister_device_put(struct ib_device *device); +#endif + +#if defined(DEREG_MR_VER_2) && defined(HAS_IB_SET_DEVICE_OP) +#define kc_free_lsmm_dereg_mr(iwdev, iwqp) \ + ((iwdev)->ibdev.ops.dereg_mr((iwqp)->lsmm_mr, NULL)) +#elif defined(DEREG_MR_VER_2) && !defined(HAS_IB_SET_DEVICE_OP) +#define kc_free_lsmm_dereg_mr(iwdev, iwqp) \ + ((iwdev)->ibdev.dereg_mr((iwqp)->lsmm_mr, NULL)) +#elif !defined(DEREG_MR_VER_2) && defined(HAS_IB_SET_DEVICE_OP) +#define kc_free_lsmm_dereg_mr(iwdev, iwqp) \ + ((iwdev)->ibdev.ops.dereg_mr((iwqp)->lsmm_mr)) +#else +#define kc_free_lsmm_dereg_mr(iwdev, iwqp) \ + ((iwdev)->ibdev.dereg_mr((iwqp)->lsmm_mr)) +#endif + +static inline int cq_validate_flags(u32 flags, u8 hw_rev) +{ + /* GEN1/2 does not support CQ create flags */ + if (hw_rev <= IRDMA_GEN_2) + return flags ? -EOPNOTSUPP : 0; + + return flags & ~IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION ? -EOPNOTSUPP : 0; +} + +#ifdef COPY_USER_PGADDR_VER_1 +static inline u64 *irdma_next_pbl_addr(u64 *pbl, struct irdma_pble_info **pinfo, + u32 *idx) +{ + *idx += 1; + if (!(*pinfo) || *idx != (*pinfo)->cnt) + return ++pbl; + *idx = 0; + (*pinfo)++; + + return (*pinfo)->addr; +} +#endif /* COPY_USER_PGADDR_VER_1 */ + +#ifdef NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +/* ida_alloc(), ida_alloc_min(), ida_alloc_max(), ida_alloc_range(), and + * ida_free() were added in commit 5ade60dda43c ("ida: add new API"). + * + * Also, using "0" as the "end" argument (3rd argument) to ida_simple_get() is + * considered the max value, which is why it's used in ida_alloc() and + * ida_alloc_min(). + */ +static inline int ida_alloc(struct ida *ida, gfp_t gfp) +{ + return ida_simple_get(ida, 0, 0, gfp); +} + +static inline int ida_alloc_min(struct ida *ida, unsigned int min, gfp_t gfp) +{ + return ida_simple_get(ida, min, 0, gfp); +} + +static inline int ida_alloc_max(struct ida *ida, unsigned int max, gfp_t gfp) +{ + return ida_simple_get(ida, 0, max, gfp); +} + +static inline int +ida_alloc_range(struct ida *ida, unsigned int min, unsigned int max, gfp_t gfp) +{ + return ida_simple_get(ida, min, max, gfp); +} + +static inline void ida_free(struct ida *ida, unsigned int id) +{ + ida_simple_remove(ida, id); +} +#endif /* NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE */ +#ifdef IB_GET_ETH_SPEED +int ib_get_eth_speed(struct ib_device *dev, u32 port_num, u8 *speed, u8 *width); +#endif +#ifdef IRDMA_IRQ_UPDATE_AFFINITY +/** + * irq_update_affinity_hint - Update the affinity hint + * @irq: Interrupt to update + * @m: cpumask pointer (NULL to clear the hint) + * + * Updates the affinity hint, but does not change the affinity of the interrupt. + */ +static inline int +irq_update_affinity_hint(unsigned int irq, const struct cpumask *m) +{ + return irq_set_affinity_hint(irq, m); +} +#endif /* IRDMA_IRQ_UPDATE_AFFINITY */ +#ifdef IRDMA_AUX_GET_SET_DRV_DATA +static inline void *auxiliary_get_drvdata(struct auxiliary_device *auxdev) +{ + return dev_get_drvdata(&auxdev->dev); +} + +static inline void auxiliary_set_drvdata(struct auxiliary_device *auxdev, void *data) +{ + dev_set_drvdata(&auxdev->dev, data); +} +#endif /* IRDMA_AUX_GET_DRV_DATA */ +#endif /* IRDMA_KCOMPAT_H_ */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/kcompat-generator.sh b/drivers/intel/irdma-1.14.33/src/irdma/kcompat-generator.sh new file mode 100644 index 000000000..fffdf4b74 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/kcompat-generator.sh @@ -0,0 +1,336 @@ +# SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +#!/bin/bash + + + +set -Eeuo pipefail + +# This file generates HAVE_ and NEED_ defines for current kernel +# (or KSRC if provided). +# +# It does so by 'gen' function calls (see body of 'gen-devlink' for examples). +# 'gen' could look for various kinds of declarations in provided kernel headers, +# eg look for an enum in one of files specified and check if given enumeration +# (single value) is present. See 'Documentation' or comment above the 'gen' fun +# in the kcompat-lib.sh. + +# Why using bash/awk instead of an old/legacy approach? +# +# The aim is to replicate all the defines provided by human developers +# in the past. Additional bonus is the fact, that we no longer need to care +# about backports done by OS vendors (RHEL, SLES, ORACLE, UBUNTU, more to come). +# We will even work (compile) with only part of backports provided. +# +# To enable smooth transition, especially in time of late fixes, "old" method +# of providing flags should still work as usual. + +# End of intro. +# Find info about coding style/rules at the end of file. +# Most of the implementation is in kcompat-lib.sh, here are actual 'gen' calls. + +export LC_ALL=C +SCRIPT_DIR="$(dirname "${BASH_SOURCE[0]}")" +ORIG_CWD="$(pwd)" +trap 'rc=$?; echo >&2 "$(realpath "$ORIG_CWD/${BASH_SOURCE[0]}"):$LINENO: failed with rc: $rc"' ERR + +# shellcheck source=kcompat-lib.sh +source "$SCRIPT_DIR"/kcompat-lib.sh + +# DO NOT break gen calls below (via \), to make our compat code more grep-able, +# keep them also grouped, first by feature (like DEVLINK), then by .h filename +# finally, keep them sorted within a group (sort by flag name) + +# handy line of DOC copy-pasted form kcompat-lib.sh: +# gen DEFINE if (KIND [METHOD of]) NAME [(matches|lacks) PATTERN|absent] in + +function gen-aux() { + ah='include/linux/auxiliary_bus.h' + mh='include/linux/mod_devicetable.h' + if grep -qE CONFIG_AUXILIARY_BUS.+1 "$CONFFILE"; then + gen HAVE_AUXILIARY_DRIVER_INT_REMOVE if method remove of auxiliary_driver matches 'int' in "$ah" + fi + + # generate HAVE_AUXILIARY_DEVICE_ID only for cases when it's disabled in .config + if ! grep -qE CONFIG_AUXILIARY_BUS.+1 "$CONFFILE"; then + gen HAVE_AUXILIARY_DEVICE_ID if struct auxiliary_device_id in "$mh" + fi +} + +function gen-bitfield() { + bf='include/linux/bitfield.h' + gen HAVE_INCLUDE_BITFIELD if macro FIELD_PREP in "$bf" + gen NEED_BITFIELD_FIELD_FIT if macro FIELD_FIT absent in "$bf" + gen NEED_BITFIELD_FIELD_MAX if macro FIELD_MAX absent in "$bf" +} + +function gen-device() { + dh='include/linux/device.h' + dph='include/linux/dev_printk.h' + gen NEED_BUS_FIND_DEVICE_CONST_DATA if fun bus_find_device lacks 'const void \\*data' in "$dh" + gen NEED_DEV_LEVEL_ONCE if macro dev_level_once absent in "$dh" "$dph" + gen NEED_DEVM_KASPRINTF if fun devm_kasprintf absent in "$dh" + gen NEED_DEVM_kfree if fun devm_kfree absent in "$dh" + gen NEED_DEVM_KVASPRINTF if fun devm_kvasprintf absent in "$dh" + gen NEED_DEVM_KZALLOC if fun devm_kzalloc absent in "$dh" +} + +function gen-devlink() { + dh='include/net/devlink.h' + gen HAVE_DEVLINK_FLASH_UPDATE_BEGIN_END_NOTIFY if fun devlink_flash_update_begin_notify in "$dh" + gen HAVE_DEVLINK_FLASH_UPDATE_PARAMS if struct devlink_flash_update_params in "$dh" + gen HAVE_DEVLINK_FLASH_UPDATE_PARAMS_FW if struct devlink_flash_update_params matches 'struct firmware \\*fw' in "$dh" + gen HAVE_DEVLINK_HEALTH if enum devlink_health_reporter_state in "$dh" + gen HAVE_DEVLINK_HEALTH_DEFAULT_AUTO_RECOVER if fun devlink_health_reporter_create lacks auto_recover in "$dh" + gen HAVE_DEVLINK_HEALTH_OPS_EXTACK if method dump of devlink_health_reporter_ops matches ext_ack in "$dh" + gen HAVE_DEVLINK_INFO_DRIVER_NAME_PUT if fun devlink_info_driver_name_put in "$dh" + gen HAVE_DEVLINK_PARAMS if method validate of devlink_param matches ext_ack in "$dh" + gen HAVE_DEVLINK_PARAMS_PUBLISH if fun devlink_params_publish in "$dh" + gen HAVE_DEVLINK_PORT_NEW if method port_new of devlink_ops in "$dh" + gen HAVE_DEVLINK_PORT_OPS if struct devlink_port_ops in "$dh" + gen HAVE_DEVLINK_PORT_SPLIT if method port_split of devlink_ops in "$dh" + gen HAVE_DEVLINK_PORT_SPLIT_EXTACK if method port_split of devlink_ops matches netlink_ext_ack in "$dh" + gen HAVE_DEVLINK_PORT_SPLIT_PORT_STRUCT if method port_split of devlink_ops matches devlink_port in "$dh" + gen HAVE_DEVLINK_PORT_TYPE_ETH_HAS_NETDEV if fun devlink_port_type_eth_set matches 'struct net_device' in "$dh" + gen HAVE_DEVLINK_RATE_NODE_CREATE if fun devl_rate_node_create in "$dh" + # keep devlink_region_ops body in variable, to not look 4 times for + # exactly the same thing in big file + # please consider it as an example of "how to speed up if needed" + REGION_OPS="$(find-struct-decl devlink_region_ops "$dh")" + gen HAVE_DEVLINK_REGIONS if struct devlink_region_ops in - <<< "$REGION_OPS" + gen HAVE_DEVLINK_REGION_OPS_SNAPSHOT if fun snapshot in - <<< "$REGION_OPS" + gen HAVE_DEVLINK_REGION_OPS_SNAPSHOT_OPS if fun snapshot matches devlink_region_ops in - <<< "$REGION_OPS" + gen HAVE_DEVLINK_REGISTER_SETS_DEV if fun devlink_register matches 'struct device' in "$dh" + gen HAVE_DEVLINK_RELOAD_ENABLE_DISABLE if fun devlink_reload_enable in "$dh" + gen HAVE_DEVLINK_SET_FEATURES if fun devlink_set_features in "$dh" + gen HAVE_DEVL_PORT_REGISTER if fun devl_port_register in "$dh" + + gen HAVE_DEVLINK_PORT_FLAVOUR_PCI_SF if enum devlink_port_flavour matches DEVLINK_PORT_FLAVOUR_PCI_SF in include/uapi/linux/devlink.h + gen HAVE_DEVLINK_RELOAD_ACTION_AND_LIMIT if enum devlink_reload_action matches DEVLINK_RELOAD_ACTION_FW_ACTIVATE in include/uapi/linux/devlink.h + + gen NEED_DEVLINK_RESOURCES_UNREGISTER_NO_RESOURCE if fun devlink_resources_unregister matches 'struct devlink_resource \\*' in "$dh" + gen NEED_DEVLINK_TO_DEV if fun devlink_to_dev absent in "$dh" + gen NEED_DEVLINK_UNLOCKED_RESOURCE if fun devl_resource_size_get absent in "$dh" +} + +function gen-ethtool() { + eth='include/linux/ethtool.h' + ueth='include/uapi/linux/ethtool.h' + gen HAVE_ETHTOOL_COALESCE_EXTACK if method get_coalesce of ethtool_ops matches 'struct kernel_ethtool_coalesce \\*' in "$eth" + gen HAVE_ETHTOOL_EXTENDED_RINGPARAMS if method get_ringparam of ethtool_ops matches 'struct kernel_ethtool_ringparam \\*' in "$eth" + gen NEED_ETHTOOL_SPRINTF if fun ethtool_sprintf absent in "$eth" + gen HAVE_ETHTOOL_FLOW_RSS if macro FLOW_RSS in "$ueth" +} + +function gen-filter() { + fh='include/linux/filter.h' + gen HAVE_XDP_DO_FLUSH if fun xdp_do_flush_map in "$fh" + gen NEED_NO_NETDEV_PROG_XDP_WARN_ACTION if fun bpf_warn_invalid_xdp_action lacks 'struct net_device \\*' in "$fh" +} + +function gen-flow-dissector() { + gen HAVE_FLOW_DISSECTOR_KEY_PPPOE if enum flow_dissector_key_id matches FLOW_DISSECTOR_KEY_PPPOE in include/net/flow_dissector.h include/net/flow_keys.h + # following HAVE ... CVLAN flag is mistakenly named after an enum key, + # but guards code around function call that was introduced later + gen HAVE_FLOW_DISSECTOR_KEY_CVLAN if fun flow_rule_match_cvlan in include/net/flow_offload.h +} + +function gen-gnss() { + cdh='include/linux/cdev.h' + clh='include/linux/device/class.h' + dh='include/linux/device.h' + gh='include/linux/gnss.h' + th='include/uapi/linux/types.h' + fh='include/linux/fs.h' + + gen HAVE_CDEV_DEVICE if fun cdev_device_add in "$cdh" + gen HAVE_DEV_UEVENT_CONST if method dev_uevent of class matches 'const struct device' in "$clh" + gen HAVE_POLL_T if typedef __poll_t in "$th" + gen HAVE_STREAM_OPEN if fun stream_open in "$fh" + # There can be either macro class_create or a function + gen NEED_CLASS_CREATE_WITH_MODULE_PARAM if fun class_create matches 'owner' in "$clh" "$dh" + gen NEED_CLASS_CREATE_WITH_MODULE_PARAM if macro class_create in "$clh" "$dh" + + if ! grep -qE CONFIG_SUSE_KERNEL.+1 "$CONFFILE"; then + gen HAVE_GNSS_MODULE if struct gnss_device in "$gh" + fi +} + +function gen-netdevice() { + ndh='include/linux/netdevice.h' + gen HAVE_NDO_ETH_IOCTL if fun ndo_eth_ioctl in "$ndh" + gen HAVE_NDO_EXTENDED_SET_TX_MAXRATE if method ndo_set_tx_maxrate of net_device_ops_extended in "$ndh" + gen HAVE_NDO_FDB_ADD_VID if method ndo_fdb_del of net_device_ops matches 'u16 vid' in "$ndh" + gen HAVE_NDO_FDB_DEL_EXTACK if method ndo_fdb_del of net_device_ops matches ext_ack in "$ndh" + gen HAVE_NDO_GET_DEVLINK_PORT if method ndo_get_devlink_port of net_device_ops in "$ndh" + gen HAVE_NDO_UDP_TUNNEL_CALLBACK if method ndo_udp_tunnel_add of net_device_ops in "$ndh" + gen HAVE_NETDEV_EXTENDED_MIN_MAX_MTU if struct net_device_extended matches min_mtu in "$ndh" + gen HAVE_NETDEV_MIN_MAX_MTU if struct net_device matches min_mtu in "$ndh" + gen HAVE_NETIF_SET_TSO_MAX if fun netif_set_tso_max_size in "$ndh" + gen HAVE_SET_NETDEV_DEVLINK_PORT if macro SET_NETDEV_DEVLINK_PORT in "$ndh" + gen NEED_NETIF_NAPI_ADD_NO_WEIGHT if fun netif_napi_add matches 'int weight' in "$ndh" + gen NEED_NET_PREFETCH if fun net_prefetch absent in "$ndh" +} + +function gen-pci() { + pcih='include/linux/pci.h' + gen HAVE_PCI_MSIX_ALLOC_IRQ_AT if fun pci_msix_alloc_irq_at in "$pcih" + gen HAVE_PCI_MSIX_CAN_ALLOC_DYN if fun pci_msix_can_alloc_dyn in "$pcih" + gen HAVE_PCI_MSIX_FREE_IRQ if fun pci_msix_free_irq in "$pcih" + gen HAVE_PER_VF_MSIX_SYSFS if method sriov_set_msix_vec_count of pci_driver in "$pcih" + gen HAVE_STRUCT_PCI_DEV_PTM_ENABLED if struct pci_dev matches ptm_enabled in "$pcih" + gen NEED_PCIE_PTM_ENABLED if fun pcie_ptm_enabled absent in "$pcih" + gen NEED_PCI_ENABLE_PTM if fun pci_enable_ptm absent in "$pcih" +} + +function gen-other() { + ush='include/linux/u64_stats_sync.h' + gen NEED_PCI_AER_CLEAR_NONFATAL_STATUS if fun pci_aer_clear_nonfatal_status absent in include/linux/aer.h + gen NEED_BITMAP_COPY_CLEAR_TAIL if fun bitmap_copy_clear_tail absent in include/linux/bitmap.h + gen NEED_BITMAP_FROM_ARR32 if fun bitmap_from_arr32 absent in include/linux/bitmap.h + gen NEED_BITMAP_TO_ARR32 if fun bitmap_to_arr32 absent in include/linux/bitmap.h + gen NEED_ASSIGN_BIT if fun assign_bit absent in include/linux/bitops.h + gen HAVE_COMPLETION_RAW_SPINLOCK if struct completion matches 'struct swait_queue_head' in include/linux/completion.h + gen NEED_DEBUGFS_LOOKUP if fun debugfs_lookup absent in include/linux/debugfs.h + gen NEED_DEBUGFS_LOOKUP_AND_REMOVE if fun debugfs_lookup_and_remove absent in include/linux/debugfs.h + gen NEED_ETH_HW_ADDR_SET if fun eth_hw_addr_set absent in include/linux/etherdevice.h + gen HAVE_HWMON_DEVICE_REGISTER_WITH_INFO if fun hwmon_device_register_with_info in include/linux/hwmon.h + gen NEED_HWMON_CHANNEL_INFO if macro HWMON_CHANNEL_INFO absent in include/linux/hwmon.h + gen HAVE_IOMMU_DEV_FEAT_AUX if enum iommu_dev_features matches IOMMU_DEV_FEAT_AUX in include/linux/iommu.h + gen NEED_DEFINE_STATIC_KEY_FALSE if macro DEFINE_STATIC_KEY_FALSE absent in include/linux/jump_label.h + gen NEED_STATIC_BRANCH_LIKELY if macro static_branch_likely absent in include/linux/jump_label.h + gen HAVE_STRUCT_STATIC_KEY_FALSE if struct static_key_false in include/linux/jump_label.h include/linux/jump_label_type.h + gen NEED_DECLARE_STATIC_KEY_FALSE if macro DECLARE_STATIC_KEY_FALSE absent in include/linux/jump_label.h include/linux/jump_label_type.h + gen NEED_LOWER_16_BITS if macro lower_16_bits absent in include/linux/kernel.h + gen NEED_UPPER_16_BITS if macro upper_16_bits absent in include/linux/kernel.h + gen NEED_MUL_U64_U64_DIV_U64 if fun mul_u64_u64_div_u64 absent in include/linux/math64.h + gen HAVE_MDEV_GET_DRVDATA if fun mdev_get_drvdata in include/linux/mdev.h + gen HAVE_MDEV_REGISTER_PARENT if fun mdev_register_parent in include/linux/mdev.h + gen NEED_DEV_PM_DOMAIN_ATTACH if fun dev_pm_domain_attach absent in include/linux/pm_domain.h include/linux/pm.h + gen NEED_DEV_PM_DOMAIN_DETACH if fun dev_pm_domain_detach absent in include/linux/pm_domain.h include/linux/pm.h + gen NEED_PTP_CLASSIFY_RAW if fun ptp_classify_raw absent in include/linux/ptp_classify.h + gen NEED_PTP_PARSE_HEADER if fun ptp_parse_header absent in include/linux/ptp_classify.h + gen HAVE_PTP_CLOCK_INFO_ADJFINE if method adjfine of ptp_clock_info in include/linux/ptp_clock_kernel.h + gen NEED_DIFF_BY_SCALED_PPM if fun diff_by_scaled_ppm absent in include/linux/ptp_clock_kernel.h + gen NEED_PTP_SYSTEM_TIMESTAMP if fun ptp_read_system_prets absent in include/linux/ptp_clock_kernel.h + gen NEED_DEV_PAGE_IS_REUSABLE if fun dev_page_is_reusable absent in include/linux/skbuff.h + gen NEED_SYSFS_EMIT if fun sysfs_emit absent in include/linux/sysfs.h + gen HAVE_TRACE_ENABLED_SUPPORT if implementation of macro __DECLARE_TRACE matches 'trace_##name##_enabled' in include/linux/tracepoint.h + gen HAVE_U64_STATS_FETCH_BEGIN_IRQ if fun u64_stats_fetch_begin_irq in "$ush" + gen HAVE_U64_STATS_FETCH_RETRY_IRQ if fun u64_stats_fetch_retry_irq in "$ush" + gen NEED_U64_STATS_READ if fun u64_stats_read absent in "$ush" + gen NEED_U64_STATS_SET if fun u64_stats_set absent in "$ush" + gen HAVE_LMV1_SUPPORT if macro VFIO_REGION_TYPE_MIGRATION in include/uapi/linux/vfio.h +} + +function gen-rdma() { + um='include/rdma/ib_umem.h' + iv='include/rdma/ib_verbs.h' + gen HAVE_IB_UMEM_SG_HEAD if struct ib_umem matches sg_head in "$um" + gen NEED_RDMA_UMEM_BLOCK_ITER_NEXT if fun __rdma_umem_block_iter_next absent in "$um" + gen HAVE_IB_UMEM_NUM_DMA_BLOCK if fun ib_umem_num_dma_blocks in "$um" +} + +# all the generations, extracted from main() to keep normal code and various +# prep separated +function gen-all() { + if grep -qE CONFIG_NET_DEVLINK.+1 "$CONFFILE"; then + gen-devlink + fi + gen-netdevice + # code above is covered by unit_tests/test_gold.sh + if [ -n "${JUST_UNIT_TESTING-}" ]; then + return + fi + gen-aux + gen-bitfield + gen-device + gen-ethtool + gen-filter + gen-flow-dissector + gen-gnss + gen-pci + gen-other + gen-rdma +} + +function main() { + # check if caller (like our makefile) wants to redirect output to file + OUT_DEFINE=_IRDMA_KCOMPAT_GEN_H_ + if [ -n "${OUT-}" ]; then + OUT_DEFINE="$(basename $OUT .h)" + OUT_DEFINE="_${OUT_DEFINE^^}_H_" + + # in case OUT exists, we don't want to overwrite it, instead + # write to a temporary copy. + if [ -s "${OUT}" ]; then + TMP_OUT="$(mktemp "${OUT}.XXX")" + trap "rm -f '${TMP_OUT}'" EXIT + + REAL_OUT="${OUT}" + OUT="${TMP_OUT}" + fi + + exec > "$OUT" + # all stdout goes to OUT since now + echo "/* Autogenerated for KSRC=${KSRC-} via $(basename "$0") */" + fi + if [ -d "${KSRC-}" ]; then + cd "${KSRC}" + fi + + # check if KSRC was ok/if we are in proper place to look for headers + if [ -z "$(filter-out-bad-files include/linux/kernel.h)" ]; then + echo >&2 "seems that there are no kernel includes placed in KSRC=${KSRC} + pwd=$(pwd); ls -l:" + ls -l >&2 + exit 8 + fi + + # we need just CONFIG_NET_DEVLINK so far, but it's in .config, required + if [ ! -f "${CONFFILE-}" ]; then + echo >&2 ".config should be passed as env CONFFILE + (and it's not set or not a file)" + exit 9 + fi + + echo "#ifndef $OUT_DEFINE" + echo "#define $OUT_DEFINE" + gen-all + echo "#endif /* $OUT_DEFINE */" + + if [ -n "${OUT-}" ]; then + cd "$ORIG_CWD" + + # Compare and see if anything changed. This avoids updating + # mtime of the file. + if [ -n "${REAL_OUT-}" ]; then + if cmp --silent "${REAL_OUT}" "${TMP_OUT}"; then + # exit now, skipping print of the output since + # there were no changes. the trap should + # cleanup TMP_OUT + exit 0 + fi + + mv -f "${TMP_OUT}" "${REAL_OUT}" + OUT="${REAL_OUT}" + fi + + # dump output, will be visible in CI + if [ -n "${JUST_UNIT_TESTING-}${QUIET_COMPAT-}" ]; then + return + fi + cat -n "$OUT" >&2 + fi +} + +main + +# Coding style: +# - rely on `set -e` handling as much as possible, so: +# - do not use <(bash process substitution) - it breaks error handling; +# - do not put substantial logic in `if`-like statement - it disables error +# handling inside of the conditional (`if big-fun call; then` is substantial) +# - make shellcheck happy - https://www.shellcheck.net +# +# That enables us to move processing out of `if` or `... && ...` statements, +# what finally means that bash error handling (`set -e`) would break on errors. diff --git a/drivers/intel/irdma-1.14.33/src/irdma/kcompat-lib.sh b/drivers/intel/irdma-1.14.33/src/irdma/kcompat-lib.sh new file mode 100644 index 000000000..27e2e2dd0 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/kcompat-lib.sh @@ -0,0 +1,279 @@ +# SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +#!/bin/bash + + + +# to be sourced + +# General shell helpers + +# exit with non-zero exit code; if there is only one param: +# exit with msg $1 and exit code from last command (or 99 if = 0) +# otherwise, exit with $1 and use remaining arguments as msg +function die() { + rc=$? + if [ $# -gt 1 ]; then + rc="$1" + shift + fi + [ "$rc" -ne 0 ] || rc=99 + echo >&2 "$@" + exit $rc +} + +# filter out paths that are not files +# input $@, output via echo; +# note: pass `-` for stdin +# note: outputs nothing if all input files are "bad" (eg. not existing), but it +# is left for caller to decide if this is an erorr condition; +# note: whitespaces are considered "bad" as part of filename, it's an error. +function filter-out-bad-files() { + if [[ $# = 1 && "$1" = '-' ]]; then + echo - + return 0 + fi + if [ $# = 0 ]; then + die 10 "no files passed, use '-' when reading from pipe (|)" + fi + local any=0 diagmsgs=/dev/stderr re=$'[\t \n]' + [ -n "${QUIET_COMPAT-}" ] && diagmsgs=/dev/null + for x in "$@"; do + if [ -e "$x" ]; then + if [[ "$x" =~ $re ]]; then + die 11 "err: filename contains whitespaces: $x." + fi + echo "$x" + any=1 + else + echo >&"$diagmsgs" filtering "$x" out + fi + done + if [ $any = 0 ]; then + echo >&"$diagmsgs" 'all files (for given query) filtered out' + fi +} + +# Basics of regexp explained, as a reference for mostly-C programmers: +# (bash) "regexp-$VAR-regexp" - bash' VARs are placed into "QUOTED" strings +# /\);?$/ - match end of function declaration, $ is end of string +# ^[ \t]* - (heuristic), anything but comment, eg to exclude function docs +# /STH/, /END/ - (awk), print all lines sice STH matched, up to END, inclusive + +# "Whitespace only" +WB='[ \t\n]' + +# Helpers below print the thing that is looked for, for further grep'ping/etc. +# That simplifies process of excluding comments or spares us state machine impl. +# +# We take advantage of current/common linux codebase formatting here. +# +# Functions in this section require input file/s passed as args +# (usually one, but more could be supplied in case of renames in kernel), +# '-' could be used as an (only) file argument to read from stdin/pipe. + +# wrapper over find-something-decl() functions below, to avoid repetition +# pass $what as $1, $end as $2, and $files to look in as rest of args +function find-decl() { + test $# -ge 3 # ensure that there are at least 3 params + local what end files + what="$1" + end="$2" + shift 2 + files="$(filter-out-bad-files "$@")" || die + if [ -z "$files" ]; then + return 0 + fi + # shellcheck disable=SC2086 + awk " + /^$WB*\*/ {next} + $what, $end + " $files +} + +# yield $1 function declaration (signature), don't pass return type in $1 +# looks only in files specified ($2, $3...) +function find-fun-decl() { + test $# -ge 2 + local what end + what="/$WB*([(]\*)?$1$WB*($|[()])/" + end='/\);?$/' + shift + find-decl "$what" "$end" "$@" +} + +# yield $1 enum declaration (type/body) +function find-enum-decl() { + test $# -ge 2 + local what end + what="/^$WB*enum$WB+$1"' \{$/' + end='/\};$/' + shift + find-decl "$what" "$end" "$@" +} + +# yield $1 struct declaration (type/body) +function find-struct-decl() { + test $# -ge 2 + local what end + what="/^$WB*struct$WB+$1"' \{$/' + end='/^\};$/' # that's (^) different from enum-decl + shift + find-decl "$what" "$end" "$@" +} + +# yield first line of $1 macro definition +function find-macro-decl() { + test $# -ge 2 + local what end + # only unindented defines, only whole-word match + what="/^#define$WB+$1"'([ \t\(]|$)/' + end=1 # only first line; use find-macro-implementation-decl for full body + shift + find-decl "$what" "$end" "$@" +} + +# yield full macro implementation +function find-macro-implementation-decl() { + test $# -ge 2 + local what end + # only unindented defines, only whole-word match + what="/^#define$WB+$1"'([ \t\(]|$)/' + # full implementation, until a line not ending in a backslash. + # Does not handle macros with comments embedded within the definition. + end='/[^\\]$/' + shift + find-decl "$what" "$end" "$@" +} + +# yield first line of $1 typedef definition (simple typedefs only) +# this probably won't handle typedef struct { \n int foo;\n}; +function find-typedef-decl() { + test $# -ge 2 + local what end + what="/^typedef .* $1"';$/' + end=1 + shift + find-decl "$what" "$end" "$@" +} + +# gen() - DSL-like function to wrap around all the other +# +# syntax: +# gen DEFINE if (KIND [METHOD of]) NAME [(matches|lacks) PATTERN|absent] in + +# where: +# DEFINE is HAVE_ or NEED_ #define to print; +# `if` is there to just read it easier and made syntax easier to check; +# +# NAME is the name for what we are looking for; +# +# KIND specifies what kind of declaration/definition we are looking for, +# could be: fun, enum, struct, method, macro, typedef, +# 'implementation of macro' +# for KIND=method, we are looking for function ptr named METHOD in struct +# named NAME (two optional args are then necessary (METHOD & of)); +# +# for KIND='implementation of macro' we are looking for the full +# implementation of the macro, not just its first line. This is usually +# combined with "matches" or "lacks". +# +# next [optional] args could be used: +# matches PATTERN - use to grep for the PATTERN within definition +# (eg, for ext_ack param) +# lacks - use to add #define only if there is no match of the PATTERN, +# *but* the NAME is *found* +# absent - the NAME that we grep for must be not found +# (ie: function not exisiting) +# +# without this optional params, behavior is the same as with +# `matches .` - use to grep just for existence of NAME; +# +# `in` is there to ease syntax, similar to `if` before. +# +# is just space-separate list of files to look in, +# single (-) for stdin. +# +# PATTERN is awk pattern, will be wrapped by two slashes (/) +function gen() { + test $# -ge 6 || die 20 "too few arguments, $# given, at least 6 needed" + local define if_kw kind name in_kw # mandatory + local of_kw method_name operator pattern # optional + local src_line="${BASH_SOURCE[0]}:${BASH_LINENO[0]}" + define="$1" + if_kw="$2" + kind="$3" + local orig_args_cnt=$# + shift 3 + [ "$if_kw" != if ] && die 21 "$src_line: 'if' keyword expected, '$if_kw' given" + case "$kind" in + fun|enum|struct|macro|typedef) + name="$1" + shift + ;; + method) + test $# -ge 5 || die 22 "$src_line: too few arguments, $orig_args_cnt given, at least 8 needed" + method_name="$1" + of_kw="$2" + name="$3" + shift 3 + [ "$of_kw" != of ] && die 23 "$src_line: 'of' keyword expected, '$of_kw' given" + ;; + implementation) + test $# -ge 5 || die 28 "$src_line: too few arguments, $orig_args_cnt given, at least 8 needed" + of_kw="$1" + kind="$2" + name="$3" + shift 3 + [ "$of_kw" != of ] && die 29 "$src_line: 'of' keyword expected, '$of_kw' given" + [ "$kind" != macro ] && die 30 "$src_line: implementation only supports 'macro', '$kind' given" + kind=macro-implementation + ;; + *) die 24 "$src_line: unknown KIND ($kind) to look for" ;; + esac + operator="$1" + case "$operator" in + absent) + pattern='.' + in_kw="$2" + shift 2 + ;; + matches|lacks) + pattern="$2" + in_kw="$3" + shift 3 + ;; + in) + operator=matches + pattern='.' + in_kw=in + shift + ;; + *) die 25 "$src_line: unknown OPERATOR ($operator) to look for" ;; + esac + [ "$in_kw" != in ] && die 26 "$src_line: 'in' keyword expected, '$in_kw' given" + test $# -ge 1 || die 27 "$src_line: too few arguments, at least one filename expected" + + local first_decl= + if [ "$kind" = method ]; then + first_decl="$(find-struct-decl "$name" "$@")" || exit 28 + # prepare params for next lookup phase + set -- - # overwrite $@ to be single dash (-) + name="$method_name" + kind=fun + elif [[ $# = 1 && "$1" = '-' ]]; then + # avoid losing stdin provided to gen() due to redirection (<<<) + first_decl="$(cat -)" + fi + + # lookup the NAME + local body + body="$(find-$kind-decl "$name" "$@" <<< "$first_decl")" || exit 29 + awk -v define="$define" -v pattern="$pattern" -v "$operator"=1 ' + /./ { not_empty = 1 } + $0 ~ pattern { found = 1 } + END { + if (lacks && !found && not_empty || matches && found || absent && !found) + print "#define", define + } + ' <<< "$body" +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/linux_kcompat.h b/drivers/intel/irdma-1.14.33/src/irdma/linux_kcompat.h new file mode 100644 index 000000000..f04c10f69 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/linux_kcompat.h @@ -0,0 +1,413 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2020 - 2022 Intel Corporation */ +#ifndef LINUX_KCOMPAT_H +#define LINUX_KCOMPAT_H + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 19, 0) +#define IB_DEV_CAPS_VER_2 +#endif + +/* IB_IW_PKEY */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0) +#define IB_IW_PKEY +#endif + +/* KMAP_LOCAL_PAGE */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0) +#define USE_KMAP +#endif + +/* CREATE_AH */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 8, 0) +#define CREATE_AH_VER_5 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) +#define CREATE_AH_VER_2 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0) +#define CREATE_AH_VER_3 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(4, 12, 0) +#define CREATE_AH_VER_1_2 +#define ETHER_COPY_VER_2 +#else +#define CREATE_AH_VER_1_1 +#define ETHER_COPY_VER_1 +#endif + +/* DESTROY_AH */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) +#define DESTROY_AH_VER_4 +#else +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) +#define DESTROY_AH_VER_3 +#else +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0) +#define DESTROY_AH_VER_2 +#else +#define DESTROY_AH_VER_1 +#endif +#endif +#endif + +/* CREAT_QP */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 15, 0) +#define CREATE_QP_VER_2 +#define GLOBAL_QP_MEM +#else +#define CREATE_QP_VER_1 +#endif + +/* DESTROY_QP */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) +#define DESTROY_QP_VER_1 +#define kc_irdma_destroy_qp(ibqp, udata) irdma_destroy_qp(ibqp) +#else +#define DESTROY_QP_VER_2 +#define kc_irdma_destroy_qp(ibqp, udata) irdma_destroy_qp(ibqp, udata) +#endif + +/* CREATE_CQ */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0) +#define CREATE_CQ_VER_3 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) +#define CREATE_CQ_VER_2 +#else +#define CREATE_CQ_VER_1 +#endif + +/* ALLOC_UCONTEXT/ DEALLOC_UCONTEXT */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) +#define ALLOC_UCONTEXT_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#else +#define ALLOC_UCONTEXT_VER_2 +#define DEALLOC_UCONTEXT_VER_2 +#endif + +/* ALLOC_PD , DEALLOC_PD */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) +#define DEALLOC_PD_VER_4 +#define ALLOC_PD_VER_3 +#else +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) +#define ALLOC_PD_VER_3 +#define DEALLOC_PD_VER_3 +#else +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0) +#define ALLOC_PD_VER_2 +#define DEALLOC_PD_VER_2 +#else +#define ALLOC_PD_VER_1 +#define DEALLOC_PD_VER_1 +#endif +#endif +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 16, 0) +#define ALLOC_HW_STATS_STRUCT_V2 +#else +#define ALLOC_HW_STATS_STRUCT_V1 +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 14, 0) +#define ALLOC_HW_STATS_V3 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0) +#define ALLOC_HW_STATS_V2 +#else +#define ALLOC_HW_STATS_V1 +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 13, 0) +#define QUERY_GID_ROCE_V2 +#define MODIFY_PORT_V2 +#define QUERY_PKEY_V2 +#define ROCE_PORT_IMMUTABLE_V2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define IW_PORT_IMMUTABLE_V2 +#define QUERY_GID_V2 +#define QUERY_PORT_V2 +#else +#define QUERY_GID_ROCE_V1 +#define MODIFY_PORT_V1 +#define QUERY_PKEY_V1 +#define ROCE_PORT_IMMUTABLE_V1 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IW_PORT_IMMUTABLE_V1 +#define QUERY_GID_V1 +#define QUERY_PORT_V1 +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) +#define VMA_DATA +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0) +/* https://lore.kernel.org/linux-rdma/20191217210406.GC17227@ziepe.ca/ + * This series adds mmap DB support and also extends rdma_user_mmap_io API + * with an extra param + */ +#define RDMA_MMAP_DB_SUPPORT +#endif + +/* IRDMA_ALLOC_MW */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) +#define IRDMA_ALLOC_MW_VER_2 +#else +#define IRDMA_ALLOC_MW_VER_1 +#endif + +/* IRDMA_ALLOC_MR */ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 9, 0) && LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0)) +#define IRDMA_ALLOC_MR_VER_1 +#else +#define IRDMA_ALLOC_MR_VER_0 +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 16, 0) +#define IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION IB_CQ_FLAGS_TIMESTAMP_COMPLETION +#endif + +/* IRDMA_DESTROY_CQ */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 9, 3) +#define IRDMA_DESTROY_CQ_VER_4 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0) +#define IRDMA_DESTROY_CQ_VER_3 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) +#define IRDMA_DESTROY_CQ_VER_2 +#else +#define IRDMA_DESTROY_CQ_VER_1 +#endif /* LINUX_VERSION_CODE */ + +/* IRDMA_DESTROY_SRQ */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) +#define IRDMA_DESTROY_SRQ_VER_3 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) +#define IRDMA_DESTROY_SRQ_VER_2 +#else +#define IRDMA_DESTROY_SRQ_VER_1 +#endif /* LINUX_VERSION_CODE */ + +/* max_sge, ip_gid, gid_attr_network_type, deref_sgid_attr */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0) +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) +#define IB_GET_CACHED_GID +#else +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 19, 0) +#define kc_typeq_ib_wr const +#else +#define kc_typeq_ib_wr +#endif + +/* ib_register_device */ +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 20, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0)) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, NULL) +#elif (LINUX_VERSION_CODE >= KERNEL_VERSION(5, 1, 0)) && (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#else +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 0, 0) +#define HAS_IB_SET_DEVICE_OP +#endif /* >= 5.0.0 */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0) +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define kc_set_ibdev_add_del_gid(ibdev) do { \ + ibdev->add_gid = irdma_add_gid; \ + ibdev->del_gid = irdma_del_gid; \ +} while (0) +#else +#define kc_set_ibdev_add_del_gid(ibdev) +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) +#else +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* < 4.20.0 */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 17, 0) && \ + LINUX_VERSION_CODE < KERNEL_VERSION(5, 3, 0)) +#define IRDMA_SET_DRIVER_ID +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0)) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define SET_BEST_PAGE_SZ_V1 +#else +#define SET_BEST_PAGE_SZ_V2 +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 11, 0)) +#define UVERBS_CMD_MASK +#else +#define USE_QP_ATTRS_STANDARD +#endif + +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 10, 0)) +#define SET_PCIDEV_PARENT +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) +#define ib_device_put(dev) +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) +#else +#define NETDEV_TO_IBDEV_SUPPORT +#define IB_DEALLOC_DRIVER_SUPPORT +#endif /* < 5.1.0 */ + +/******PORT_PHYS_STATE enums***************************************************/ +#if (LINUX_VERSION_CODE < KERNEL_VERSION(5, 4, 0)) +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; +#endif +/*********************************************************/ + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#else +#define kc_get_ucontext(udata) to_ucontext(context) +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0) +#define IN_IFADDR +#else +#define FOR_IFA +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 1, 0) +struct ib_ucontext *irdma_alloc_ucontext(struct ib_device *ibdev, struct ib_udata *udata); +int irdma_dealloc_ucontext(struct ib_ucontext *context); +struct ib_pd *irdma_alloc_pd(struct ib_device *ibdev, struct ib_ucontext *context, struct ib_udata *udata); +int irdma_dealloc_pd(struct ib_pd *ibpd); +#else +int irdma_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata); +void irdma_dealloc_ucontext(struct ib_ucontext *context); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) +int irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata); +int irdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); +#else +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) +int irdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); +void irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata); +#else +int irdma_alloc_pd(struct ib_pd *pd, struct ib_ucontext *context, struct ib_udata *udata); +void irdma_dealloc_pd(struct ib_pd *ibpd); +#endif +#endif +#endif + +/*****SETUP DMA_DEVICE***************************************************/ +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 11, 0) +#define set_ibdev_dma_device(ibdev, dev) \ + ibdev.dma_device = dev +#else +#define set_ibdev_dma_device(ibdev, dev) +#endif /* < 4.11.0 */ +/*********************************************************/ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 12, 0) +#define rdma_ah_attr ib_ah_attr +#define ah_attr_to_dmac(attr) ((attr).dmac) +#else +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#endif /* < 4.12.0 */ + +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 10, 0)) && \ +(LINUX_VERSION_CODE < KERNEL_VERSION(4, 15, 0)) +#define IB_RESOLVE_ETH_DMAC +#endif /* >= 4.10.0 */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 13, 0) +#define wait_queue_entry __wait_queue +#endif /* < 4.13.0 */ + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 17, 0) +#define IRDMA_ADD_DEL_GID +#endif + +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 19, 0) +#define SET_ROCE_CM_INFO_VER_1 +#define IB_IW_MANDATORY_AH_OP +#elif LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) +#define SET_ROCE_CM_INFO_VER_2 +#else +#define SET_ROCE_CM_INFO_VER_3 +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 6, 0) +#define IB_UMEM_GET_V3 +#elif LINUX_VERSION_CODE >= KERNEL_VERSION(5, 5, 0) +#define IB_UMEM_GET_V2 +#else +#define IB_UMEM_GET_V1 +#endif + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) +#define DEREG_MR_VER_2 +#else +#define DEREG_MR_VER_1 +#endif + +/* REREG MR */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0) +#define REREG_MR_VER_2 +#else +#define REREG_MR_VER_1 +#endif +/* DMABUF */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(6, 0, 0) +#define SET_DMABUF +#endif +/* IRDMA_IRQ_UPDATE_AFFINITY */ +#if (LINUX_VERSION_CODE >= KERNEL_VERSION(4, 14, 0)) && \ +(LINUX_VERSION_CODE < KERNEL_VERSION(5, 17, 0)) +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#endif +#endif /* LINUX_KCOMPAT_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/main.c b/drivers/intel/irdma-1.14.33/src/irdma/main.c new file mode 100644 index 000000000..0c26b5de7 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/main.c @@ -0,0 +1,1016 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "main.h" +/* TODO: Adding this here is not ideal. Can we remove this warning now? */ +#include "icrdma_hw.h" +#define DRV_VER_MAJOR 1 +#define DRV_VER_MINOR 14 +#define DRV_VER_BUILD 33 +#define DRV_VER __stringify(DRV_VER_MAJOR) "." \ + __stringify(DRV_VER_MINOR) "." __stringify(DRV_VER_BUILD) + +static u8 resource_profile; +module_param(resource_profile, byte, 0444); +MODULE_PARM_DESC(resource_profile, "Resource Profile: 0=PF only(default), 1=Weighted VF, 2=Even Distribution"); + +static unsigned short max_rdma_vfs = IRDMA_MAX_PE_ENA_VF_COUNT; +module_param(max_rdma_vfs, ushort, 0444); +MODULE_PARM_DESC(max_rdma_vfs, "Maximum VF count: 0-32, default=32"); + +bool irdma_upload_context; +module_param(irdma_upload_context, bool, 0644); +MODULE_PARM_DESC(irdma_upload_context, "Upload QP context, default=false"); + +static unsigned int limits_sel = 3; +module_param(limits_sel, uint, 0444); +MODULE_PARM_DESC(limits_sel, "Resource limits selector, Range: 0-7, default=3"); + +static unsigned int gen1_limits_sel = 1; +module_param(gen1_limits_sel, uint, 0444); +MODULE_PARM_DESC(gen1_limits_sel, "x722 resource limits selector, Range: 0-5, default=1"); + +static unsigned int roce_ena; +module_param(roce_ena, uint, 0444); +MODULE_PARM_DESC(roce_ena, "RoCE enable: 1=enable RoCEv2 on all ports (not supported on x722), 0=iWARP(default)"); + +static ulong roce_port_cfg; +module_param(roce_port_cfg, ulong, 0444); +MODULE_PARM_DESC(roce_port_cfg, "RoCEv2 per port enable: 1=port0 RoCEv2 all others iWARP, 2=port1 RoCEv2 etc. not supported on X722"); + +static bool en_rem_endpoint_trk; +module_param(en_rem_endpoint_trk, bool, 0444); +MODULE_PARM_DESC(en_rem_endpoint_trk, "Remote Endpoint Tracking: 1=enabled (not supported on x722), 0=disabled(default)"); + +static u8 fragment_count_limit = 6; +module_param(fragment_count_limit, byte, 0444); +MODULE_PARM_DESC(fragment_count_limit, "adjust maximum values for queue depth and inline data size, default=6, Range: 2-13"); + +/******************Advanced RoCEv2 congestion knobs***********************************************/ +static bool dcqcn_enable; +module_param(dcqcn_enable, bool, 0444); +MODULE_PARM_DESC(dcqcn_enable, "enables DCQCN algorithm for RoCEv2 on all ports, default=false "); + +static bool dcqcn_cc_cfg_valid; +module_param(dcqcn_cc_cfg_valid, bool, 0444); +MODULE_PARM_DESC(dcqcn_cc_cfg_valid, "set DCQCN parameters to be valid, default=false"); + +static u8 dcqcn_min_dec_factor = 1; +module_param(dcqcn_min_dec_factor, byte, 0444); +MODULE_PARM_DESC(dcqcn_min_dec_factor, "set minimum percentage factor by which tx rate can be changed for CNP, Range: 1-100, default=1"); + +static u8 dcqcn_min_rate_MBps; +module_param(dcqcn_min_rate_MBps, byte, 0444); +MODULE_PARM_DESC(dcqcn_min_rate_MBps, "set minimum rate limit value, in MBits per second, default=0"); + +static u8 dcqcn_F = 5; +module_param(dcqcn_F, byte, 0444); +MODULE_PARM_DESC(dcqcn_F, "set number of times to stay in each stage of bandwidth recovery, default=5"); + +static unsigned short dcqcn_T = 0x37; +module_param(dcqcn_T, ushort, 0444); +MODULE_PARM_DESC(dcqcn_T, "set number of usecs that should elapse before increasing the CWND in DCQCN mode, default=0x37"); + +static unsigned int dcqcn_B = 0x249f0; +module_param(dcqcn_B, uint, 0444); +MODULE_PARM_DESC(dcqcn_B, "The number of bytes to transmit before updating CWND in DCQCN mode. default=0x249f0"); + +static unsigned short dcqcn_rai_factor = 1; +module_param(dcqcn_rai_factor, ushort, 0444); +MODULE_PARM_DESC(dcqcn_rai_factor, "set number of MSS to add to the congestion window in additive increase mode, default=1"); + +static unsigned short dcqcn_hai_factor = 5; +module_param(dcqcn_hai_factor, ushort, 0444); +MODULE_PARM_DESC(dcqcn_hai_factor, "set number of MSS to add to the congestion window in hyperactive increase mode, default=5"); + +static unsigned int dcqcn_rreduce_mperiod = 50; +module_param(dcqcn_rreduce_mperiod, uint, 0444); +MODULE_PARM_DESC(dcqcn_rreduce_mperiod, "set minimum time between 2 consecutive rate reductions for a single flow, default=50"); + +/**************************************************************************************************/ + +MODULE_ALIAS("i40iw"); +MODULE_AUTHOR("Intel Corporation, "); +MODULE_DESCRIPTION("Intel(R) Ethernet Protocol Driver for RDMA"); +MODULE_LICENSE("Dual BSD/GPL"); +MODULE_VERSION(DRV_VER); + +/** + * set_protocol_used - set protocol_used against HW generation and roce_ena flag + * @rf: RDMA PCI function + * @roce_ena: RoCE enabled bit flag + */ +static inline void set_protocol_used(struct irdma_pci_f *rf, uint roce_ena) +{ + switch (rf->rdma_ver) { + case IRDMA_GEN_3: + case IRDMA_GEN_4: + rf->protocol_used = IRDMA_ROCE_PROTOCOL_ONLY; + break; + case IRDMA_GEN_2: + rf->protocol_used = roce_ena & BIT(PCI_FUNC(rf->pcidev->devfn)) ? + IRDMA_ROCE_PROTOCOL_ONLY : IRDMA_IWARP_PROTOCOL_ONLY; + + break; + case IRDMA_GEN_1: + rf->protocol_used = IRDMA_IWARP_PROTOCOL_ONLY; + break; + } +} + +/** + * irdma_set_rf_user_cfg_params - Setup RF configurations from module parameters + * @rf: RDMA PCI function + */ +void irdma_set_rf_user_cfg_params(struct irdma_pci_f *rf) +{ + if (limits_sel > 7) + limits_sel = 7; + + if (gen1_limits_sel > 5) + gen1_limits_sel = 5; + + rf->limits_sel = (rf->rdma_ver == IRDMA_GEN_1) ? gen1_limits_sel : + limits_sel; + if (roce_ena) + pr_warn_once("irdma: Because roce_ena is ENABLED, roce_port_cfg will be ignored."); + set_protocol_used(rf, roce_ena ? 0xFFFFFFFF : roce_port_cfg); + rf->rsrc_profile = (resource_profile < IRDMA_HMC_PROFILE_EQUAL) ? + (u8)resource_profile + IRDMA_HMC_PROFILE_DEFAULT : + IRDMA_HMC_PROFILE_DEFAULT; + if (max_rdma_vfs > IRDMA_MAX_PE_ENA_VF_COUNT) { + pr_warn_once("irdma: Requested VF count [%d] is above max supported. Setting to %d.", + max_rdma_vfs, IRDMA_MAX_PE_ENA_VF_COUNT); + max_rdma_vfs = IRDMA_MAX_PE_ENA_VF_COUNT; + } + rf->max_rdma_vfs = (rf->rsrc_profile != IRDMA_HMC_PROFILE_DEFAULT) ? + max_rdma_vfs : 0; + rf->en_rem_endpoint_trk = en_rem_endpoint_trk; + rf->fragcnt_limit = fragment_count_limit; + if (rf->fragcnt_limit > 13 || rf->fragcnt_limit < 2) { + rf->fragcnt_limit = 6; + pr_warn_once("irdma: Requested [%d] fragment count limit out of range (2-13), setting to default=6.", + fragment_count_limit); + } + rf->dcqcn_ena = dcqcn_enable; + + /* Skip over all checking if no dcqcn */ + if (!dcqcn_enable) + return; + + rf->dcqcn_params.cc_cfg_valid = dcqcn_cc_cfg_valid; + rf->dcqcn_params.dcqcn_b = dcqcn_B; + +#define DCQCN_B_MAX GENMASK(25, 0) + if (rf->dcqcn_params.dcqcn_b > DCQCN_B_MAX) { + rf->dcqcn_params.dcqcn_b = DCQCN_B_MAX; + pr_warn_once("irdma: Requested [%d] dcqcn_b value too high, setting to %d.", + dcqcn_B, rf->dcqcn_params.dcqcn_b); + } + +#define DCQCN_F_MAX 8 + rf->dcqcn_params.dcqcn_f = dcqcn_F; + if (dcqcn_F > DCQCN_F_MAX) { + rf->dcqcn_params.dcqcn_f = DCQCN_F_MAX; + pr_warn_once("irdma: Requested [%d] dcqcn_f value too high, setting to %d.", + dcqcn_F, DCQCN_F_MAX); + } + + rf->dcqcn_params.dcqcn_t = dcqcn_T; + rf->dcqcn_params.hai_factor = dcqcn_hai_factor; + rf->dcqcn_params.min_dec_factor = dcqcn_min_dec_factor; + if (dcqcn_min_dec_factor < 1 || dcqcn_min_dec_factor > 100) { + rf->dcqcn_params.dcqcn_b = 1; + pr_warn_once("irdma: Requested [%d] dcqcn_min_dec_factor out of range (1-100) , setting to default=1", + dcqcn_min_dec_factor); + } + + rf->dcqcn_params.min_rate = dcqcn_min_rate_MBps; + rf->dcqcn_params.rai_factor = dcqcn_rai_factor; + rf->dcqcn_params.rreduce_mperiod = dcqcn_rreduce_mperiod; +} + +static int irdma_init_dbg_and_configfs(void) +{ +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + int ret; + +#endif /* CONFIGFS_SUPPORT */ +#ifdef CONFIG_DEBUG_FS + irdma_dbg_init(); +#endif +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + ret = irdma_configfs_init(); + if (ret) { + pr_err("Failed to register irdma to configfs subsystem\n"); +#ifdef CONFIG_DEBUG_FS + irdma_dbg_exit(); +#endif + return ret; + } +#endif /* CONFIG_CONFIGFS_FS */ + return 0; +} + +static inline void irdma_deinit_dbg_and_configfs(void) +{ +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + irdma_configfs_exit(); +#endif +#ifdef CONFIG_DEBUG_FS + irdma_dbg_exit(); +#endif +} + +static int irdma_vchnl_receive(struct iidc_core_dev_info *cdev_info, u32 vf_id, + u8 *msg, u16 len) +{ + struct irdma_device *iwdev = dev_get_drvdata(&cdev_info->adev->dev); + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + + if (WARN_ON(!len || !msg)) + return -EINVAL; + + return dev->vchnl_if->vchnl_recv(dev, (u16)vf_id, msg, len); +} + +int irdma_vchnl_send_pf(struct irdma_sc_dev *dev, u16 vf_id, u8 *msg, u16 len) +{ + struct iidc_core_dev_info *cdev_info = dev_to_rf(dev)->cdev; + + cdev_info->ops->vc_send(cdev_info, vf_id, msg, len); + + return 0; +} + +int irdma_vchnl_send_sync(struct irdma_sc_dev *dev, u8 *msg, u16 len, + u8 *recv_msg, u16 *recv_len) +{ + struct iidc_core_dev_info *cdev_info = dev_to_rf(dev)->cdev; + int ret; + + ret = cdev_info->ops->vc_send_sync(cdev_info, msg, len, recv_msg, + recv_len); + if (ret == -ETIMEDOUT) { + ibdev_err(&(dev_to_rf(dev)->iwdev->ibdev), + "Virtual channel Req <-> Resp completion timeout = 0x%x\n", ret); + dev->vchnl_up = false; + } + + return ret; +} + +static struct irdma_vchnl_if irdma_vchnl_if_pf = { + .vchnl_recv = irdma_vchnl_recv_pf, +}; + +static struct irdma_vchnl_if irdma_vchnl_if_req = { + .vchnl_recv = irdma_vchnl_req_recv, +}; + +static void irdma_prep_tc_change(struct irdma_device *iwdev) +{ + iwdev->vsi.tc_change_pending = true; + irdma_sc_suspend_resume_qps(&iwdev->vsi, IRDMA_OP_SUSPEND); + + /* Wait for all qp's to suspend */ + wait_event_timeout(iwdev->suspend_wq, + !atomic_read(&iwdev->vsi.qp_suspend_reqs), + msecs_to_jiffies(IRDMA_EVENT_TIMEOUT_MS)); + + if (iwdev->rf->rdma_ver == IRDMA_GEN_2) + irdma_ws_reset(&iwdev->vsi); +} + +static void irdma_log_invalid_mtu(u16 mtu, struct irdma_sc_dev *dev) +{ + if (mtu < IRDMA_MIN_MTU_IPV4) + ibdev_warn(to_ibdev(dev), + "MTU setting [%d] too low for RDMA traffic. Minimum MTU is 576 for IPv4\n", + mtu); + else if (mtu < IRDMA_MIN_MTU_IPV6) + ibdev_warn(to_ibdev(dev), + "MTU setting [%d] too low for RDMA traffic. Minimum MTU is 1280 for IPv6\\n", + mtu); +} + +static void irdma_fill_qos_info(struct irdma_l2params *l2params, + struct iidc_qos_params *qos_info) +{ + int i; + + l2params->num_tc = qos_info->num_tc; + l2params->vsi_prio_type = qos_info->vport_priority_type; + l2params->vsi_rel_bw = qos_info->vport_relative_bw; + for (i = 0; i < l2params->num_tc; i++) { + l2params->tc_info[i].egress_virt_up = + qos_info->tc_info[i].egress_virt_up; + l2params->tc_info[i].ingress_virt_up = + qos_info->tc_info[i].ingress_virt_up; + l2params->tc_info[i].prio_type = qos_info->tc_info[i].prio_type; + l2params->tc_info[i].rel_bw = qos_info->tc_info[i].rel_bw; + l2params->tc_info[i].tc_ctx = qos_info->tc_info[i].tc_ctx; + } + for (i = 0; i < IIDC_MAX_USER_PRIORITY; i++) + l2params->up2tc[i] = qos_info->up2tc[i]; + + if (qos_info->pfc_mode == IIDC_DSCP_PFC_MODE) { + l2params->dscp_mode = true; + memcpy(l2params->dscp_map, qos_info->dscp_map, + sizeof(l2params->dscp_map)); + } +} + +static void irdma_free_one_vf(struct irdma_vchnl_dev *vc_dev) +{ + struct irdma_sc_dev *dev = vc_dev->pf_dev; + + irdma_ws_reset(vc_dev->vf_vsi); + irdma_del_hmc_objects(dev, &vc_dev->hmc_info, true, false, + dev->hw_attrs.uk_attrs.hw_rev); + irdma_pf_put_vf_hmc_fcn(dev, vc_dev); + irdma_put_vfdev(dev, vc_dev); +} + +static void irdma_free_all_vf_rsrc(struct irdma_sc_dev *dev) +{ + u16 vf_idx; + + for (vf_idx = 0; vf_idx < dev->num_vfs; vf_idx++) { + if (dev->vc_dev[vf_idx]) + irdma_free_one_vf(dev->vc_dev[vf_idx]); + } +} + +/** + * irdma_failover_start - Handle failover start + * @iwdev: rdma device + * @failing_port: Port number failing + **/ +static void irdma_failover_start(struct irdma_device *iwdev, u8 failing_port) +{ + iwdev->vsi.failover_pending = true; + irdma_ws_failover_cmd(&iwdev->vsi, IRDMA_OP_WS_FAILOVER_START, failing_port, 0); +} + +/** + * irdma_failover_complete - Handle fail over complete + * @iwdev: rdma device structure + * @failing_port: Port number failing + * @active_port: fail_over_port number + **/ +static void irdma_failover_complete(struct irdma_device *iwdev, u8 failing_port, u8 active_port) +{ + if (iwdev->vsi.lag_aa) + irdma_ws_move_cmd(&iwdev->vsi); + else + irdma_ws_failover_cmd(&iwdev->vsi, + IRDMA_OP_WS_FAILOVER_COMPLETE, + failing_port, active_port); + iwdev->vsi.failover_pending = false; +} + +static void irdma_iidc_event_handler(struct iidc_core_dev_info *cdev_info, struct iidc_event *event) +{ + struct irdma_device *iwdev = dev_get_drvdata(&cdev_info->adev->dev); + struct irdma_l2params l2params = {}; + + if (!iwdev || iwdev->rf->reset) + return; + + if (*event->type & BIT(IIDC_EVENT_AFTER_MTU_CHANGE)) { + ibdev_dbg(&iwdev->ibdev, "CLNT: new MTU = %d\n", iwdev->netdev->mtu); + if (iwdev->vsi.mtu != iwdev->netdev->mtu) { + l2params.mtu = iwdev->netdev->mtu; + l2params.mtu_changed = true; + irdma_log_invalid_mtu(l2params.mtu, &iwdev->rf->sc_dev); + if (iwdev->vsi.tc_change_pending) { + iwdev->vsi.mtu_change_pending = true; + iwdev->vsi.mtu = iwdev->netdev->mtu; + return; + } + irdma_change_l2params(&iwdev->vsi, &l2params); + } + } else if (*event->type & BIT(IIDC_EVENT_VF_RESET)) { + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_vchnl_dev *vc_dev = + irdma_find_vc_dev(dev, event->info.vf_id); + + if (vc_dev) + irdma_free_one_vf(vc_dev); + } else if (*event->type & BIT(IIDC_EVENT_BEFORE_TC_CHANGE)) { + if (iwdev->vsi.tc_change_pending) + return; + + irdma_prep_tc_change(iwdev); + } else if (*event->type & BIT(IIDC_EVENT_AFTER_TC_CHANGE)) { + + if (!iwdev->vsi.tc_change_pending) + return; + + if (iwdev->vsi.mtu_change_pending) { + iwdev->vsi.mtu_change_pending = false; + l2params.mtu = iwdev->vsi.mtu; + l2params.mtu_changed = true; + } + + l2params.tc_changed = true; + ibdev_dbg(&iwdev->ibdev, "CLNT: TC Change\n"); + + irdma_fill_qos_info(&l2params, &cdev_info->qos_info); + if (iwdev->rf->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY) + iwdev->dcb_vlan_mode = l2params.num_tc > 1 && !l2params.dscp_mode; + if (iwdev->rf->sc_dev.privileged) + irdma_check_fc_for_tc_update(&iwdev->vsi, &l2params); + irdma_change_l2params(&iwdev->vsi, &l2params); + } else if (*event->type & BIT(IIDC_EVENT_FAILOVER_START) && iwdev->lag_mode) { + ibdev_dbg(&iwdev->ibdev, "CLNT: IIDC_EVENT_FAILOVER_START: rdma_port = [%d, %d], bitmap = 0x%x, failing_port=%d\n", + cdev_info->rdma_ports[0], cdev_info->rdma_ports[1], + cdev_info->rdma_port_bitmap, + cdev_info->rdma_active_port); + irdma_failover_start(iwdev, cdev_info->rdma_active_port); + } else if (*event->type & BIT(IIDC_EVENT_FAILOVER_FINISH)) { + if (iwdev->lag_mode == IRDMA_LAG_ACTIVE_ACTIVE) { + ibdev_dbg(&iwdev->ibdev, "CLNT: IIDC_EVENT_FAILOVER_FINISH ports[1][2] = %d %d, bitmap = 0x%x\n", + cdev_info->rdma_ports[0], + cdev_info->rdma_ports[1], + cdev_info->rdma_port_bitmap); + iwdev->vsi.lag_ports[0] = cdev_info->rdma_ports[0]; + iwdev->vsi.lag_ports[1] = cdev_info->rdma_ports[1]; + iwdev->vsi.lag_port_bitmap = cdev_info->rdma_port_bitmap; + } + irdma_failover_complete(iwdev, 0, cdev_info->rdma_active_port); + } else if (*event->type & BIT(IIDC_EVENT_CRIT_ERR)) { + ibdev_warn(&iwdev->ibdev, "ICE OICR event notification: oicr = 0x%08x\n", + event->info.reg); + if (event->info.reg & IRDMAPFINT_OICR_PE_CRITERR_M) { + u32 pe_criterr; + + pe_criterr = readl(iwdev->rf->sc_dev.hw_regs[IRDMA_GLPE_CRITERR]); +#define IRDMA_Q1_RESOURCE_ERR 0x0001024d + if (pe_criterr != IRDMA_Q1_RESOURCE_ERR) { + ibdev_err(&iwdev->ibdev, "critical PE Error, GLPE_CRITERR=0x%08x\n", + pe_criterr); + iwdev->rf->reset = true; + } else { + ibdev_warn(&iwdev->ibdev, "Q1 Resource Check\n"); + } + } + if (event->info.reg & IRDMAPFINT_OICR_HMC_ERR_M) { + ibdev_err(&iwdev->ibdev, "HMC Error\n"); + iwdev->rf->reset = true; + } + if (event->info.reg & IRDMAPFINT_OICR_PE_PUSH_M) { + ibdev_err(&iwdev->ibdev, "PE Push Error\n"); + iwdev->rf->reset = true; + } + if (iwdev->rf->reset) + iwdev->rf->gen_ops.request_reset(iwdev->rf); + } else if (*event->type & BIT(IIDC_EVENT_WARN_RESET)) { + iwdev->rf->reset = true; + } +} + +/** + * irdma_request_reset - Request a reset + * @rf: RDMA PCI function + */ +static void irdma_request_reset(struct irdma_pci_f *rf) +{ + struct iidc_core_dev_info *cdev_info = rf->cdev; + + ibdev_warn(&rf->iwdev->ibdev, "Requesting a reset\n"); + rf->sc_dev.vchnl_up = false; + cdev_info->ops->request_reset(rf->cdev, IIDC_CORER); +} + +/* + * irdma_vchnl_req_aeq_vec_map_gen2 - Virt channel AEQ configuration + * @dev: device + * @idx: function relative MSI-X vector + * + * Call the IDC to send a AEQ configuration request. + * Return 0 if successful, otherwise return error + */ +int irdma_vchnl_req_aeq_vec_map_gen2(struct irdma_sc_dev *dev, u32 idx) +{ + struct iidc_core_dev_info *cdev_info = dev_to_rf(dev)->cdev; + struct iidc_qvlist_info qvl_info = {}; + struct iidc_qv_info *qvinfo = &qvl_info.qv_info[0]; + + qvl_info.num_vectors = 1; + qvinfo->ceq_idx = IRDMA_Q_INVALID_IDX; + qvinfo->v_idx = idx; + qvinfo->itr_idx = IRDMA_IDX_ITR0; + + return cdev_info->ops->vc_queue_vec_map_unmap(cdev_info, &qvl_info, + true); +} + +/* + * irdma_vchnl_req_ceq_vec_map_gen2 - Virt channel CEQ configuration + * @dev: shared code device + * @ceq_id: function relative CEQ id + * @idx: function relative MSI-X vector + * + * Call the IDC to send a CEQ configuration request. + * Return 0 if successful, otherwise return error + */ +int irdma_vchnl_req_ceq_vec_map_gen2(struct irdma_sc_dev *dev, u16 ceq_id, u32 idx) +{ + struct iidc_core_dev_info *cdev_info = dev_to_rf(dev)->cdev; + struct iidc_qvlist_info qvl_info = {}; + struct iidc_qv_info *qvinfo = &qvl_info.qv_info[0]; + + qvl_info.num_vectors = 1; + qvinfo->aeq_idx = IRDMA_Q_INVALID_IDX; + qvinfo->ceq_idx = ceq_id; + qvinfo->v_idx = idx; + qvinfo->itr_idx = IRDMA_IDX_ITR0; + + return cdev_info->ops->vc_queue_vec_map_unmap(cdev_info, &qvl_info, + true); +} + +/* + * irdma_lan_register_qset - Register qsets with LAN driver + * @vsi: vsi structure + * @tc_node1: List of Traffic class node ponters + * @tc_node2: List of Traffic class node ponters + */ +static int irdma_lan_register_qset(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node1, + struct irdma_ws_node *tc_node2) +{ + struct irdma_device *iwdev = vsi->back_vsi; + struct iidc_core_dev_info *cdev_info = iwdev->rf->cdev; + int ret; + + if (tc_node2) { + struct iidc_rdma_multi_qset_params mqset = { }; + + mqset.qs_handle[0] = tc_node1->qs_handle; + mqset.qs_handle[1] = tc_node2->qs_handle; + mqset.tc = tc_node2->traffic_class; + mqset.vport_id = vsi->vsi_idx; + mqset.num = 2; + ret = cdev_info->ops->alloc_multi_res(cdev_info, &mqset); + if (ret) { + ibdev_warn(&iwdev->ibdev, "WS: LAN alloc_multi_res for rdma qset failed.\n"); + /* return ret; Ignore return code since RDMA still works when it fails, until ICE is debugged */ + } + tc_node1->l2_sched_node_id = mqset.teid[0]; + tc_node2->l2_sched_node_id = mqset.teid[1]; + vsi->qos[tc_node1->user_pri].l2_sched_node_id[0] = mqset.teid[0]; + vsi->qos[tc_node1->user_pri].l2_sched_node_id[1] = mqset.teid[1]; + } else { + struct iidc_rdma_qset_params qset = { }; + + qset.qs_handle = tc_node1->qs_handle; + qset.tc = tc_node1->traffic_class; + qset.vport_id = vsi->vsi_idx; + ret = cdev_info->ops->alloc_res(cdev_info, &qset); + if (ret) { + ibdev_warn(&iwdev->ibdev, "WS: LAN alloc_res for rdma qset failed.\n"); + //return ret; + } + + tc_node1->l2_sched_node_id = qset.teid; + vsi->qos[tc_node1->user_pri].l2_sched_node_id[0] = qset.teid; + } + return 0; +} + +/** + * irdma_lan_unregister_qset - Unregister qsets with LAN driver + * @vsi: vsi structure + * @tc_node1: Traffic class node + * @tc_node2: Traffic class node + */ +static void irdma_lan_unregister_qset(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node1, + struct irdma_ws_node *tc_node2) +{ + struct irdma_device *iwdev = vsi->back_vsi; + struct iidc_core_dev_info *cdev_info = iwdev->rf->cdev; + + if (vsi->lag_aa) { + struct iidc_rdma_multi_qset_params mqset = { }; + + mqset.qs_handle[0] = tc_node1->qs_handle; + mqset.qs_handle[1] = tc_node2->qs_handle; + mqset.tc = tc_node1->traffic_class; /* TC is the same for both nodes */ + mqset.vport_id = vsi->vsi_idx; + mqset.num = 2; + mqset.teid[0] = tc_node1->l2_sched_node_id; + mqset.teid[1] = tc_node2->l2_sched_node_id; + if (cdev_info->ops->free_multi_res(cdev_info, &mqset)) + ibdev_warn(&iwdev->ibdev, "WS: LAN free_res for rdma qset failed.\n"); + + } else { + struct iidc_rdma_qset_params qset = { }; + struct irdma_ws_node *tc_node = tc_node1 ? tc_node1 : tc_node2; + + qset.qs_handle = tc_node->qs_handle; + qset.tc = tc_node->traffic_class; + qset.vport_id = vsi->vsi_idx; + qset.teid = tc_node->l2_sched_node_id; + + if (cdev_info->ops->free_res(cdev_info, &qset)) + ibdev_warn(&iwdev->ibdev, "WS: LAN free_res for rdma qset failed.\n"); + } +} + +void irdma_cleanup_dead_qps(struct irdma_sc_vsi *vsi) +{ + struct irdma_sc_qp *qp = NULL; + struct irdma_qp *iwqp; + struct irdma_pci_f *rf; + u8 i; + + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); + while (qp) { + if (qp->qp_uk.qp_type == IRDMA_QP_TYPE_UDA) { + qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); + continue; + } + iwqp = qp->qp_uk.back_qp; + rf = iwqp->iwdev->rf; + dma_free_coherent(rf->hw.device, + iwqp->q2_ctx_mem.size, + iwqp->q2_ctx_mem.va, + iwqp->q2_ctx_mem.pa); + dma_free_coherent(rf->hw.device, + iwqp->kqp.dma_mem.size, + iwqp->kqp.dma_mem.va, + iwqp->kqp.dma_mem.pa); + kfree(iwqp->kqp.sq_wrid_mem); + kfree(iwqp->kqp.rq_wrid_mem); + qp = irdma_get_qp_from_list(&vsi->qos[i].qplist, qp); + kfree(iwqp); + } + } +} + +#ifdef HAVE_AUXILIARY_DRIVER_INT_REMOVE +static int irdma_remove(struct auxiliary_device *aux_dev) +#else /* HAVE_AUXILIARY_DRIVER_INT_REMOVE */ +static void irdma_remove(struct auxiliary_device *aux_dev) +#endif /* HAVE_AUXILIARY_DRIVER_INT_REMOVE */ +{ + struct iidc_auxiliary_dev *iidc_adev = container_of(aux_dev, + struct iidc_auxiliary_dev, + adev); + struct iidc_core_dev_info *cdev_info = iidc_adev->cdev_info; + struct irdma_device *iwdev = auxiliary_get_drvdata(aux_dev); + u8 rdma_ver = iwdev->rf->rdma_ver; + + if (rdma_ver == IRDMA_GEN_2 && !iwdev->rf->reset) { + if (iwdev->rf->sc_dev.privileged) + irdma_free_all_vf_rsrc(&iwdev->rf->sc_dev); +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + if (rdma_ver <= IRDMA_GEN_2 && iwdev->up_map_en) { + struct irdma_up_info up_map_info = {}; + + *((u64 *)up_map_info.map) = IRDMA_DEFAULT_UP_UP_MAP; + up_map_info.use_cnp_up_override = false; + up_map_info.cnp_up_override = 0; + up_map_info.hmc_fcn_idx = iwdev->rf->sc_dev.hmc_fn_id; + irdma_cqp_up_map_cmd(&iwdev->rf->sc_dev, + IRDMA_OP_SET_UP_MAP, + &up_map_info); + } +#endif /* CONFIG_CONFIGFS_FS */ + if (iwdev->vsi.tc_change_pending) { + iwdev->vsi.tc_change_pending = false; + irdma_sc_suspend_resume_qps(&iwdev->vsi, + IRDMA_OP_RESUME); + } + + } + + if (rdma_ver == IRDMA_GEN_2) { + if (iwdev->rf->sc_dev.privileged) + cdev_info->ops->update_vport_filter( + cdev_info, iwdev->vsi_num, false); + } + + irdma_ib_unregister_device(iwdev); + irdma_unregister_notifiers(iwdev); + irdma_deinit_device(iwdev); + ib_dealloc_device(&iwdev->ibdev); + pr_debug("INIT: Gen[%d] func[%d] device remove success\n", + rdma_ver, PCI_FUNC(cdev_info->pdev->devfn)); +#ifdef HAVE_AUXILIARY_DRIVER_INT_REMOVE + return 0; +#endif /* HAVE_AUXILIARY_DRIVER_INT_REMOVE */ +} + +static int irdma_vchnl_init(struct irdma_device *iwdev, + struct iidc_core_dev_info *cdev_info, u8 *rdma_ver) +{ + struct irdma_vchnl_init_info virt_info; + struct irdma_pci_f *rf = iwdev->rf; + u8 gen = cdev_info->rdma_caps.gen; + int ret; + + rf->vchnl_wq = alloc_ordered_workqueue("irdma-virtchnl-wq", 0); + if (!rf->vchnl_wq) + return -ENOMEM; + + mutex_init(&rf->sc_dev.vchnl_mutex); + + virt_info.hw_rev = !gen ? IRDMA_GEN_2 : gen; + virt_info.is_pf = !cdev_info->ftype; + + if (cdev_info->ftype) { + virt_info.privileged = false; + } else { + if (cdev_info->ver.major >= 10 && cdev_info->ver.minor >= 2) + virt_info.privileged = cdev_info->rdma_caps.gen == IRDMA_GEN_2; + else + virt_info.privileged = true; + } + virt_info.vchnl_if = virt_info.privileged ? &irdma_vchnl_if_pf : + &irdma_vchnl_if_req; + virt_info.vchnl_wq = rf->vchnl_wq; + ret = irdma_sc_vchnl_init(&rf->sc_dev, &virt_info); + if (ret) { + destroy_workqueue(rf->vchnl_wq); + return ret; + } + + *rdma_ver = rf->sc_dev.hw_attrs.uk_attrs.hw_rev; + return 0; +} + +static int irdma_fill_device_info(struct irdma_device *iwdev, struct iidc_core_dev_info *cdev_info) +{ + struct irdma_pci_f *rf = iwdev->rf; + int err; + + rf->sc_dev.hw = &rf->hw; + rf->iwdev = iwdev; + rf->cdev = cdev_info; + rf->hw.hw_addr = cdev_info->hw_addr; + rf->pcidev = cdev_info->pdev; + rf->hw.device = &rf->pcidev->dev; + rf->ftype = cdev_info->ftype; + rf->msix_count = cdev_info->msix_count; + rf->msix_entries = cdev_info->msix_entries; + + err = irdma_vchnl_init(iwdev, cdev_info, &rf->rdma_ver); + if (err) + return err; + + if (!cdev_info->ftype && cdev_info->ver.major == 10 && + cdev_info->ver.minor == 0 && rf->rdma_ver == IRDMA_GEN_2) { + u32 val; +#define PF_FUNC_RID 0x0009E880 +#define PF_FUNC_RID_FUNCTION_NUMBER GENMASK(2, 0) + rf->hw.hw_addr = cdev_info->hw_addr; + val = rd32(&rf->hw, PF_FUNC_RID); + rf->pf_id = (u8)FIELD_GET(PF_FUNC_RID_FUNCTION_NUMBER, val); + } else { + rf->pf_id = cdev_info->pf_id; + } + + if (!cdev_info->ftype && rf->rdma_ver == IRDMA_GEN_2) { + rf->gen_ops.register_qset = irdma_lan_register_qset; + rf->gen_ops.unregister_qset = irdma_lan_unregister_qset; + } + + rf->default_vsi.vsi_idx = cdev_info->vport_id; + rf->protocol_used = cdev_info->rdma_protocol == IIDC_RDMA_PROTOCOL_ROCEV2 ? + IRDMA_ROCE_PROTOCOL_ONLY : IRDMA_IWARP_PROTOCOL_ONLY; + rf->rsrc_profile = IRDMA_HMC_PROFILE_DEFAULT; + if (rf->rdma_ver == IRDMA_GEN_2) + rf->check_fc = irdma_check_fc_for_qp; + rf->gen_ops.request_reset = irdma_request_reset; + /* Can override limits_sel, protocol_used */ + irdma_set_rf_user_cfg_params(rf); + + mutex_init(&iwdev->ah_tbl_lock); + + rcu_read_lock(); + iwdev->netdev = netdev_master_upper_dev_get_rcu(cdev_info->netdev); + rcu_read_unlock(); + if (!iwdev->netdev || cdev_info->rdma_active_port == + IIDC_RDMA_INVALID_PORT) { + iwdev->netdev = cdev_info->netdev; + } else { + if (rf->protocol_used != IRDMA_ROCE_PROTOCOL_ONLY) { + dev_err(rf->hw.device, "LAG is only supported in RoCEv2 mode.\n"); + return -EINVAL; + } + + if (cdev_info->ver.major >= 10 && cdev_info->ver.minor >= 3) + iwdev->lag_mode = cdev_info->bond_aa ? + IRDMA_LAG_ACTIVE_ACTIVE : + IRDMA_LAG_ACTIVE_PASSIVE; + else + iwdev->lag_mode = IRDMA_LAG_ACTIVE_PASSIVE; + } + iwdev->vsi_num = cdev_info->vport_id; + iwdev->init_state = INITIAL_STATE; + iwdev->roce_cwnd = IRDMA_ROCE_CWND_DEFAULT; + iwdev->roce_ackcreds = IRDMA_ROCE_ACKCREDS_DEFAULT; + iwdev->rcv_wnd = IRDMA_CM_DEFAULT_RCV_WND_SCALED; + iwdev->rcv_wscale = IRDMA_CM_DEFAULT_RCV_WND_SCALE; + iwdev->push_mode = iwdev->rf->rdma_ver <= IRDMA_GEN_2 ? false : true; +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + iwdev->iwarp_ecn_en = iwdev->rf->rdma_ver == IRDMA_GEN_2 ? true : false; + iwdev->iwarp_rtomin = 5; + iwdev->up_up_map = IRDMA_DEFAULT_UP_UP_MAP; +#endif + if (iwdev->rf->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY) { + iwdev->roce_rtomin = 5; + iwdev->roce_dcqcn_en = iwdev->rf->dcqcn_ena; + iwdev->roce_mode = true; + } + dev_info(rf->hw.device, "%s: iwdev->lag_mode = %d\n", __func__, + iwdev->lag_mode); + return 0; +} + +static int irdma_probe(struct auxiliary_device *aux_dev, const struct auxiliary_device_id *id) +{ + struct iidc_auxiliary_dev *iidc_adev = container_of(aux_dev, + struct iidc_auxiliary_dev, + adev); + struct iidc_core_dev_info *cdev_info = iidc_adev->cdev_info; + struct irdma_device *iwdev; + struct irdma_pci_f *rf; + struct irdma_l2params l2params = {}; + int err; + struct irdma_handler *hdl; + + if (cdev_info->ver.major != IIDC_MAJOR_VER) { + pr_err("version mismatch:\n"); + pr_err("expected major ver %d, caller specified major ver %d\n", + IIDC_MAJOR_VER, cdev_info->ver.major); + pr_err("expected minor ver %d, caller specified minor ver %d\n", + IIDC_MINOR_VER, cdev_info->ver.minor); + return -EINVAL; + } + if (cdev_info->ver.minor != IIDC_MINOR_VER) + pr_info("probe: minor version mismatch: expected %0d.%0d caller specified %0d.%0d\n", + IIDC_MAJOR_VER, IIDC_MINOR_VER, + cdev_info->ver.major, cdev_info->ver.minor); + pr_info("probe: cdev_info=%p, cdev_info->dev.aux_dev.bus->number=%d, cdev_info->rdma_active_port=0x%x netdev=%s\n", + cdev_info, cdev_info->pdev->bus->number, cdev_info->rdma_active_port, + netdev_name(cdev_info->netdev)); + iwdev = ib_alloc_device(irdma_device, ibdev); + if (!iwdev) + return -ENOMEM; + iwdev->rf = kzalloc(sizeof(*rf), GFP_KERNEL); + if (!iwdev->rf) { + ib_dealloc_device(&iwdev->ibdev); + return -ENOMEM; + } + + err = irdma_fill_device_info(iwdev, cdev_info); + if (err) + goto err_fill_devinfo; + rf = iwdev->rf; + iwdev->aux_dev = aux_dev; + + hdl = kzalloc(sizeof(*hdl), GFP_KERNEL); + if (!hdl) + goto err_hdl; + + hdl->iwdev = iwdev; + iwdev->hdl = hdl; + err = irdma_ctrl_init_hw(rf); + if (err) + goto err_ctrl_init; + + if (rf->rdma_ver == IRDMA_GEN_2) { + if (irdma_set_attr_from_fragcnt(&rf->sc_dev, rf->fragcnt_limit)) + dev_warn(rf->hw.device, + "device limit update failed for fragment count %d\n", + rf->fragcnt_limit); + } + l2params.mtu = iwdev->netdev->mtu; + irdma_fill_qos_info(&l2params, &cdev_info->qos_info); + if (rf->protocol_used != IRDMA_IWARP_PROTOCOL_ONLY) + iwdev->dcb_vlan_mode = l2params.num_tc > 1 && !l2params.dscp_mode; + err = irdma_rt_init_hw(iwdev, &l2params); + if (err) + goto err_rt_init; + + if (iwdev->lag_mode == IRDMA_LAG_ACTIVE_ACTIVE) { + dev_info(rf->hw.device, + "%s: cdev_info->rdma_ports[] = %d %d, rdma_port_bitmap = 0x%x\n", + __func__, cdev_info->rdma_ports[0], + cdev_info->rdma_ports[1], cdev_info->rdma_port_bitmap); + iwdev->vsi.lag_ports[0] = cdev_info->rdma_ports[0]; + iwdev->vsi.lag_ports[1] = cdev_info->rdma_ports[1]; + iwdev->vsi.lag_port_bitmap = cdev_info->rdma_port_bitmap; + } + err = irdma_register_notifiers(iwdev); + if (err) + goto err_notifier_reg; + irdma_add_handler(hdl); +#ifdef CONFIG_DEBUG_FS + irdma_dbg_pf_init(hdl); +#endif + + err = irdma_ib_register_device(iwdev); + if (err) + goto err_ibreg; + + if (rf->rdma_ver == IRDMA_GEN_2) { + if (rf->sc_dev.privileged) + cdev_info->ops->update_vport_filter( + cdev_info, iwdev->vsi_num, true); + } + + ibdev_dbg(&iwdev->ibdev, "INIT: Gen[%d] PF[%d] device probe success\n", + rf->rdma_ver, PCI_FUNC(rf->pcidev->devfn)); + + auxiliary_set_drvdata(aux_dev, iwdev); + + return 0; + +err_ibreg: +#ifdef CONFIG_DEBUG_FS + irdma_dbg_pf_exit(iwdev->hdl); +#endif + irdma_del_handler(iwdev->hdl); + irdma_unregister_notifiers(iwdev); +err_notifier_reg: + irdma_rt_deinit_hw(iwdev); +err_rt_init: + irdma_ctrl_deinit_hw(rf); +err_ctrl_init: + kfree(hdl); +err_hdl: + destroy_workqueue(rf->vchnl_wq); +err_fill_devinfo: + kfree(iwdev->rf); + ib_dealloc_device(&iwdev->ibdev); + + return err; +} + +static const struct auxiliary_device_id irdma_auxiliary_id_table[] = { + {.name = "ice.iwarp", }, + {.name = "ice.roce", }, + {.name = "idpf.roce", }, + {.name = "iavf.iwarp", }, + {.name = "iavf.roce", }, + {}, +}; + +MODULE_DEVICE_TABLE(auxiliary, irdma_auxiliary_id_table); + +static struct iidc_auxiliary_drv irdma_auxiliary_drv = { + .adrv = { + .id_table = irdma_auxiliary_id_table, + .probe = irdma_probe, + .remove = irdma_remove, + }, + .event_handler = irdma_iidc_event_handler, + .vc_receive = irdma_vchnl_receive, +}; + +static int __init irdma_init_module(void) +{ + int ret; + + pr_info("irdma driver version: %d.%d.%d\n", DRV_VER_MAJOR, + DRV_VER_MINOR, DRV_VER_BUILD); + ret = irdma_init_dbg_and_configfs(); + if (ret) + return ret; + + ret = auxiliary_driver_register(&i40iw_auxiliary_drv); + if (ret) { + pr_err("Failed i40iw(gen_1) auxiliary_driver_register() ret=%d\n", + ret); + irdma_deinit_dbg_and_configfs(); + return ret; + } + + ret = auxiliary_driver_register(&irdma_auxiliary_drv.adrv); + if (ret) { + auxiliary_driver_unregister(&i40iw_auxiliary_drv); + pr_err("Failed irdma auxiliary_driver_register() ret=%d\n", + ret); + irdma_deinit_dbg_and_configfs(); + return ret; + } + + return 0; +} + +static void __exit irdma_exit_module(void) +{ + auxiliary_driver_unregister(&irdma_auxiliary_drv.adrv); + auxiliary_driver_unregister(&i40iw_auxiliary_drv); + irdma_deinit_dbg_and_configfs(); +} + +module_init(irdma_init_module); +module_exit(irdma_exit_module); diff --git a/drivers/intel/irdma-1.14.33/src/irdma/main.h b/drivers/intel/irdma-1.14.33/src/irdma/main.h new file mode 100644 index 000000000..f172b281a --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/main.h @@ -0,0 +1,717 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2024 Intel Corporation */ +#ifndef IRDMA_MAIN_H +#define IRDMA_MAIN_H + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#ifndef CONFIG_64BIT +#include +#endif +#include +#ifndef RDMA_MMAP_DB_SUPPORT +#include +#endif +#include +#ifdef __OFED_4_8__ +#include +#endif /* __OFED_4_8__ */ +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "osdep.h" +#include "defs.h" +#include "hmc.h" +#include "type.h" +#include "ws.h" +#include "protos.h" +#include "pble.h" +#include "cm.h" +#include "iidc.h" +#include "irdma_kcompat.h" +#include "irdma-abi.h" +#include "verbs.h" +#include "user.h" +#include "puda.h" + +extern struct list_head irdma_handlers; +extern spinlock_t irdma_handler_lock; +extern bool irdma_upload_context; +extern struct auxiliary_driver i40iw_auxiliary_drv; + +#define IRDMA_FW_VER_DEFAULT 2 +#define IRDMA_HW_VER 2 + +#define IRDMA_ARP_ADD_UPDATE 1 +#define IRDMA_ARP_ADD IRDMA_ARP_ADD_UPDATE +#define IRDMA_ARP_DELETE 2 +#define IRDMA_ARP_RESOLVE 3 + +#define IRDMA_MACIP_ADD 1 +#define IRDMA_MACIP_DELETE 2 + +#define IW_CCQ_SIZE (IRDMA_CQP_SW_SQSIZE_2048 + 1) +#define IW_CEQ_SIZE 2048 +#define IW_AEQ_SIZE 2048 + +#define RX_BUF_SIZE (1536 + 8) +#define IW_REG0_SIZE (4 * 1024) +#define IW_TX_TIMEOUT (6 * HZ) +#define IW_FIRST_QPN 1 + +#define IW_SW_CONTEXT_ALIGN 1024 + +#define MAX_DPC_ITERATIONS 128 + +#define IRDMA_EVENT_TIMEOUT_MS 5000 +#define IRDMA_VCHNL_EVENT_TIMEOUT_MS 10000 +#define IRDMA_RST_TIMEOUT_HZ 4 + +#define IRDMA_NO_QSET 0xffff + +#define IW_CFG_FPM_QP_COUNT 32768 +#define IRDMA_MAX_PAGES_PER_FMR 262144 +#define IRDMA_MIN_PAGES_PER_FMR 1 +#define IRDMA_CQP_COMPL_RQ_WQE_FLUSHED 2 +#define IRDMA_CQP_COMPL_SQ_WQE_FLUSHED 3 + +#define IRDMA_Q_TYPE_PE_AEQ 0x80 +#define IRDMA_REM_ENDPOINT_TRK_QPID 3 + +#define IRDMA_DRV_OPT_ENA_MPA_VER_0 0x00000001 +#define IRDMA_DRV_OPT_DISABLE_MPA_CRC 0x00000002 +#define IRDMA_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004 +#define IRDMA_DRV_OPT_DISABLE_INTF 0x00000008 +#define IRDMA_DRV_OPT_ENA_MSI 0x00000010 +#define IRDMA_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020 +#define IRDMA_DRV_OPT_NO_INLINE_DATA 0x00000080 +#define IRDMA_DRV_OPT_DISABLE_INT_MOD 0x00000100 +#define IRDMA_DRV_OPT_DISABLE_VIRT_WQ 0x00000200 +#define IRDMA_DRV_OPT_ENA_PAU 0x00000400 +#define IRDMA_DRV_OPT_MCAST_LOGPORT_MAP 0x00000800 + +#define IW_HMC_OBJ_TYPE_NUM ARRAY_SIZE(iw_hmc_obj_types) +#define IRDMA_ROCE_CWND_DEFAULT 0x400 +#define IRDMA_ROCE_ACKCREDS_DEFAULT 0x1E +#if IS_ENABLED(CONFIG_CONFIGFS_FS) +#define IRDMA_DEFAULT_UP_UP_MAP 0x0706050403020100l +#endif /* IS_ENABLED(CONFIG_CONFIGFS_FS) */ + +#define IRDMA_FLUSH_SQ BIT(0) +#define IRDMA_FLUSH_RQ BIT(1) +#define IRDMA_REFLUSH BIT(2) +#define IRDMA_FLUSH_WAIT BIT(3) + +#define IRDMA_IRQ_NAME_STR_LEN 64 + +enum init_completion_state { + INVALID_STATE = 0, + INITIAL_STATE, + CQP_CREATED, + HMC_OBJS_CREATED, + HW_RSRC_INITIALIZED, + CCQ_CREATED, + CEQ0_CREATED, /* Last state of probe */ + ILQ_CREATED, + IEQ_CREATED, + REM_ENDPOINT_TRK_CREATED, + CEQS_CREATED, + PBLE_CHUNK_MEM, + AEQ_CREATED, + IP_ADDR_REGISTERED, /* Last state of open */ +}; + +struct ae_desc { + u16 id; + const char *desc; +}; + +struct irdma_rsrc_limits { + u32 qplimit; + u32 mrlimit; + u32 cqlimit; +}; + +struct irdma_cqp_err_info { + u16 maj; + u16 min; + const char *desc; +}; + +struct irdma_cqp_compl_info { + u32 op_ret_val; + u16 maj_err_code; + u16 min_err_code; + bool error; + u8 op_code; +}; + +struct irdma_cqp_request { + struct cqp_cmds_info info; + wait_queue_head_t waitq; + struct list_head list; + refcount_t refcnt; + void (*callback_fcn)(struct irdma_cqp_request *cqp_request); + void *param; + struct irdma_cqp_compl_info compl_info; + u8 request_done; /* READ/WRITE_ONCE macros operate on it */ + bool waiting:1; + bool dynamic:1; + bool pending:1; +}; + +struct irdma_cqp { + struct irdma_sc_cqp sc_cqp; + spinlock_t req_lock; /* protect CQP request list */ + spinlock_t compl_lock; /* protect CQP completion processing */ + wait_queue_head_t waitq; + wait_queue_head_t remove_wq; + struct irdma_dma_mem sq; + struct irdma_dma_mem host_ctx; + u64 *scratch_array; + struct irdma_cqp_request *cqp_requests; + struct irdma_ooo_cqp_op *ooo_op_array; + struct list_head cqp_avail_reqs; + struct list_head cqp_pending_reqs; +}; + +struct irdma_ccq { + struct irdma_sc_cq sc_cq; + struct irdma_dma_mem mem_cq; + struct irdma_dma_mem shadow_area; +}; + +struct irdma_ceq { + struct irdma_sc_ceq sc_ceq; + struct irdma_dma_mem mem; + u32 irq; + u32 msix_idx; + struct irdma_pci_f *rf; + struct tasklet_struct dpc_tasklet; + spinlock_t ce_lock; /* sync cq destroy with cq completion event notification */ +}; + +struct irdma_aeq { + struct irdma_sc_aeq sc_aeq; + struct irdma_dma_mem mem; + struct irdma_pble_alloc palloc; + bool virtual_map; +}; + +struct irdma_arp_entry { + u32 ip_addr[4]; + u8 mac_addr[ETH_ALEN]; + refcount_t refcnt; + bool delete_pending:1; +}; + +struct irdma_msix_vector { + u32 idx; + u32 irq; + u32 cpu_affinity; + u16 ceq_id; + cpumask_t mask; + char name[IRDMA_IRQ_NAME_STR_LEN]; +}; + +struct irdma_mc_table_info { + u32 mgn; + u32 dest_ip[4]; + bool lan_fwd:1; + bool ipv4_valid:1; +}; + +struct mc_table_list { + struct list_head list; + struct irdma_mc_table_info mc_info; + struct irdma_mcast_grp_info mc_grp_ctx; +}; + +struct irdma_qv_info { + u32 v_idx; /* msix_vector */ + u16 ceq_idx; + u16 aeq_idx; + u8 itr_idx; +}; + +struct irdma_qvlist_info { + u32 num_vectors; + struct irdma_qv_info qv_info[1]; +}; + +struct irdma_gen_ops { + void (*request_reset)(struct irdma_pci_f *rf); + int (*register_qset)(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node1, + struct irdma_ws_node *tc_node2); + void (*unregister_qset)(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node1, + struct irdma_ws_node *tc_node2); +}; + +struct irdma_pci_f { + bool reset:1; + bool rsrc_created:1; + bool msix_shared:1; + bool ftype:1; + u8 rsrc_profile; + u16 max_rdma_vfs; + u8 *hmc_info_mem; + u8 *mem_rsrc; + u8 rdma_ver; + u8 rst_to; + /* Not used in SRIOV VF mode */ + u8 pf_id; + u8 fragcnt_limit; + enum irdma_protocol_used protocol_used; + bool en_rem_endpoint_trk:1; + bool dcqcn_ena:1; + u32 sd_type; +#ifdef CONFIG_DEBUG_FS +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) + u32 hugepgcnt; +#endif +#endif + u32 msix_count; + u32 max_mr; + u32 max_qp; + u32 max_cq; + u32 max_srq; + u32 next_srq; + u32 max_ah; + u32 next_ah; + u32 max_mcg; + u32 next_mcg; + u32 max_pd; + u32 next_cq; + u32 next_pd; + u32 max_mr_size; + u32 max_cqe; + u32 mr_stagmask; + u32 used_pds; + u32 used_cqs; + u32 used_srqs; + u32 used_mrs; + u32 used_qps; + u32 arp_table_size; + u32 next_arp_index; + u32 ceqs_count; + u32 next_ws_node_id; + u32 max_ws_node_id; + u32 limits_sel; + unsigned long *allocated_ws_nodes; + unsigned long *allocated_qps; + unsigned long *allocated_cqs; + unsigned long *allocated_srqs; + unsigned long *allocated_mrs; + unsigned long *allocated_pds; + unsigned long *allocated_mcgs; + unsigned long *allocated_ahs; + unsigned long *allocated_arps; + enum init_completion_state init_state; + struct irdma_sc_dev sc_dev; + struct irdma_handler *hdl; + struct pci_dev *pcidev; + void *cdev; + struct irdma_hw hw; + struct irdma_cqp cqp; + struct irdma_ccq ccq; + struct irdma_aeq aeq; + struct irdma_ceq *ceqlist; + struct irdma_hmc_pble_rsrc *pble_rsrc; + struct irdma_arp_entry *arp_table; + spinlock_t arp_lock; /*protect ARP table access*/ + spinlock_t rsrc_lock; /* protect HW resource array access */ + spinlock_t qptable_lock; /*protect QP table access*/ + spinlock_t cqtable_lock; /*protect CQ table access*/ + spinlock_t srqtable_lock; /*protect SRQ table access*/ + struct irdma_qp **qp_table; + struct irdma_cq **cq_table; + struct irdma_srq **srq_table; + spinlock_t qh_list_lock; /* protect mc_qht_list */ + struct mc_table_list mc_qht_list; + struct irdma_msix_vector *iw_msixtbl; + struct irdma_qvlist_info *iw_qvlist; + struct tasklet_struct dpc_tasklet; + struct msix_entry *msix_entries; + struct irdma_dma_mem obj_mem; + struct irdma_dma_mem obj_next; + atomic64_t push_cnt; + struct workqueue_struct *cqp_cmpl_wq; + struct work_struct cqp_cmpl_work; + struct workqueue_struct *vchnl_wq; + struct irdma_sc_vsi default_vsi; + void *back_fcn; + struct irdma_gen_ops gen_ops; + void (*check_fc)(struct irdma_sc_vsi *vsi, struct irdma_sc_qp *sc_qp); + struct irdma_dcqcn_cc_params dcqcn_params; + struct irdma_device *iwdev; + u8 vlan_parse_en; +}; + +enum irdma_lag_type { + IRDMA_LAG_NONE, + IRDMA_LAG_ACTIVE_PASSIVE, + IRDMA_LAG_ACTIVE_ACTIVE +}; + +struct irdma_device { + struct ib_device ibdev; + struct irdma_pci_f *rf; + struct net_device *netdev; + struct notifier_block nb_netdevice_event; + struct notifier_block nb_net_event; + struct notifier_block nb_inet6addr_event; + struct notifier_block nb_inetaddr_event; + struct auxiliary_device *aux_dev; + struct irdma_handler *hdl; + struct workqueue_struct *cleanup_wq; + struct irdma_sc_vsi vsi; + struct irdma_cm_core cm_core; + DECLARE_HASHTABLE(ah_hash_tbl, 8); + struct mutex ah_tbl_lock; +#ifdef CONFIG_DEBUG_FS + u64 ah_reused; +#endif + u32 ah_list_cnt; + u32 ah_list_hwm; + u32 roce_cwnd; + u32 roce_ackcreds; + u32 vendor_id; + u32 vendor_part_id; + u32 rcv_wnd; + u16 mac_ip_table_idx; + u16 vsi_num; + u8 rcv_wscale; + u8 iw_status; + u8 roce_rtomin; + u8 rd_fence_rate; + bool override_rcv_wnd:1; + bool override_cwnd:1; + bool override_ackcreds:1; + bool override_ooo:1; + bool override_rd_fence_rate:1; + bool override_rtomin:1; +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + u64 up_up_map; + u8 cnp_up_override; + u8 iwarp_rtomin; + u32 ceq_intrl; /* Interrupt rate limit per second: 0-disabled, 4237 - 250,000 */ + bool up_map_en:1; + bool iwarp_dctcp_en:1; + bool iwarp_timely_en:1; + bool iwarp_bolt_en:1; + bool iwarp_ecn_en:1; + bool roce_ecn_en:1; + bool roce_timely_en:1; + bool roce_no_icrc_en:1; + bool roce_dctcp_en:1; +#endif /* CONFIG_CONFIGFS_FS */ + bool push_mode:1; + bool roce_mode:1; + bool roce_dcqcn_en:1; + bool dcb_vlan_mode:1; + bool iw_ooo:1; + enum init_completion_state init_state; + enum irdma_lag_type lag_mode; +#ifdef CONFIG_DEBUG_FS +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) + u32 hugepgcnt; +#endif +#endif + wait_queue_head_t suspend_wq; +#ifdef ENABLE_DUP_CM_NAME_WA + int name_id; +#endif + char ib_devname[IB_DEVICE_NAME_MAX]; +}; + +struct irdma_handler { + struct list_head list; + struct irdma_device *iwdev; +#ifdef CONFIG_DEBUG_FS + struct dentry *irdma_dbg_dentry; + struct list_head ucontext_list; + spinlock_t uctx_list_lock; /*sync access to ucontext list*/ +#endif /* DEBUG_SUPPORT */ + bool shared_res_created; +}; + +static inline struct irdma_device *to_iwdev(struct ib_device *ibdev) +{ + return container_of(ibdev, struct irdma_device, ibdev); +} + +static inline struct irdma_ucontext *to_ucontext(struct ib_ucontext *ibucontext) +{ + return container_of(ibucontext, struct irdma_ucontext, ibucontext); +} + +#ifdef RDMA_MMAP_DB_SUPPORT +static inline struct irdma_user_mmap_entry * +to_irdma_mmap_entry(struct rdma_user_mmap_entry *rdma_entry) +{ + return container_of(rdma_entry, struct irdma_user_mmap_entry, + rdma_entry); +} + +#endif +static inline struct irdma_pd *to_iwpd(struct ib_pd *ibpd) +{ + return container_of(ibpd, struct irdma_pd, ibpd); +} + +static inline struct irdma_ah *to_iwah(struct ib_ah *ibah) +{ + return container_of(ibah, struct irdma_ah, ibah); +} + +static inline struct irdma_mr *to_iwmr(struct ib_mr *ibmr) +{ + return container_of(ibmr, struct irdma_mr, ibmr); +} + +static inline struct irdma_mr *to_iwmw(struct ib_mw *ibmw) +{ + return container_of(ibmw, struct irdma_mr, ibmw); +} + +static inline struct irdma_cq *to_iwcq(struct ib_cq *ibcq) +{ + return container_of(ibcq, struct irdma_cq, ibcq); +} + +static inline struct irdma_qp *to_iwqp(struct ib_qp *ibqp) +{ + return container_of(ibqp, struct irdma_qp, ibqp); +} + +static inline struct irdma_pci_f *dev_to_rf(struct irdma_sc_dev *dev) +{ + return container_of(dev, struct irdma_pci_f, sc_dev); +} + +static inline struct irdma_srq *to_iwsrq(struct ib_srq *ibsrq) +{ + return container_of(ibsrq, struct irdma_srq, ibsrq); +} + +/** + * irdma_alloc_resource - allocate a resource + * @iwdev: device pointer + * @resource_array: resource bit array: + * @max_resources: maximum resource number + * @req_resources_num: Allocated resource number + * @next: next free id + **/ +static inline int irdma_alloc_rsrc(struct irdma_pci_f *rf, + unsigned long *rsrc_array, u32 max_rsrc, + u32 *req_rsrc_num, u32 *next) +{ + u32 rsrc_num; + unsigned long flags; + + spin_lock_irqsave(&rf->rsrc_lock, flags); + rsrc_num = find_next_zero_bit(rsrc_array, max_rsrc, *next); + if (rsrc_num >= max_rsrc) { + rsrc_num = find_first_zero_bit(rsrc_array, max_rsrc); + if (rsrc_num >= max_rsrc) { + spin_unlock_irqrestore(&rf->rsrc_lock, flags); + ibdev_dbg(&rf->iwdev->ibdev, + "ERR: resource [%d] allocation failed\n", + rsrc_num); + return -EOVERFLOW; + } + } + __set_bit(rsrc_num, rsrc_array); + *next = rsrc_num + 1; + if (*next == max_rsrc) + *next = 0; + *req_rsrc_num = rsrc_num; + spin_unlock_irqrestore(&rf->rsrc_lock, flags); + + return 0; +} + +/** + * irdma_free_resource - free a resource + * @iwdev: device pointer + * @resource_array: resource array for the resource_num + * @resource_num: resource number to free + **/ +static inline void irdma_free_rsrc(struct irdma_pci_f *rf, + unsigned long *rsrc_array, u32 rsrc_num) +{ + unsigned long flags; + + spin_lock_irqsave(&rf->rsrc_lock, flags); + __clear_bit(rsrc_num, rsrc_array); + spin_unlock_irqrestore(&rf->rsrc_lock, flags); +} + +int irdma_ctrl_init_hw(struct irdma_pci_f *rf); +void irdma_ctrl_deinit_hw(struct irdma_pci_f *rf); +int irdma_rt_init_hw(struct irdma_device *iwdev, + struct irdma_l2params *l2params); +void irdma_rt_deinit_hw(struct irdma_device *iwdev); +void irdma_qp_add_ref(struct ib_qp *ibqp); +void irdma_qp_rem_ref(struct ib_qp *ibqp); +void irdma_free_lsmm_rsrc(struct irdma_qp *iwqp); +struct ib_qp *irdma_get_qp(struct ib_device *ibdev, int qpn); +void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask); +void irdma_arp_cqp_op(struct irdma_pci_f *rf, u16 arp_index, + const unsigned char *mac_addr, u32 action); +void irdma_manage_arp_cache(struct irdma_pci_f *rf, const unsigned char *mac_addr, + u32 *ip_addr, u32 action); +struct irdma_apbvt_entry *irdma_add_apbvt(struct irdma_device *iwdev, u16 port); +void irdma_del_apbvt(struct irdma_device *iwdev, + struct irdma_apbvt_entry *entry); +struct irdma_cqp_request *irdma_alloc_and_get_cqp_request(struct irdma_cqp *cqp, + bool wait); +void irdma_free_cqp_request(struct irdma_cqp *cqp, + struct irdma_cqp_request *cqp_request); +void irdma_put_cqp_request(struct irdma_cqp *cqp, + struct irdma_cqp_request *cqp_request); +int irdma_alloc_local_mac_entry(struct irdma_pci_f *rf, u16 *mac_tbl_idx); +int irdma_add_local_mac_entry(struct irdma_pci_f *rf, const u8 *mac_addr, u16 idx); +void irdma_del_local_mac_entry(struct irdma_pci_f *rf, u16 idx); +const char *irdma_get_ae_desc(u16 ae_id); + +u32 irdma_initialize_hw_rsrc(struct irdma_pci_f *rf); +void irdma_port_ibevent(struct irdma_device *iwdev); +void irdma_cm_disconn(struct irdma_qp *qp); + +bool irdma_cqp_crit_err(struct irdma_sc_dev *dev, u8 cqp_cmd, + u16 maj_err_code, u16 min_err_code); +int irdma_handle_cqp_op(struct irdma_pci_f *rf, + struct irdma_cqp_request *cqp_request); + +int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, + struct ib_udata *udata); +int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr, + int attr_mask, struct ib_udata *udata); +void irdma_cq_add_ref(struct ib_cq *ibcq); +void irdma_cq_rem_ref(struct ib_cq *ibcq); +void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq); +void irdma_srq_add_ref(struct ib_srq *ibsrq); +void irdma_srq_rem_ref(struct ib_srq *ibsrq); +void irdma_srq_event(struct irdma_sc_srq *srq); +void irdma_srq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_srq *srq); + +void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf); +int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp, + struct irdma_modify_qp_info *info, bool wait); +int irdma_qp_suspend_resume(struct irdma_sc_qp *qp, bool suspend); +int irdma_manage_qhash(struct irdma_device *iwdev, struct irdma_cm_info *cminfo, + enum irdma_quad_entry_type etype, + enum irdma_quad_hash_manage_type mtype, void *cmnode, + bool wait); +void irdma_receive_ilq(struct irdma_sc_vsi *vsi, struct irdma_puda_buf *rbuf); +void irdma_free_sqbuf(struct irdma_sc_vsi *vsi, void *bufp); +void irdma_free_qp_rsrc(struct irdma_qp *iwqp); +int irdma_setup_cm_core(struct irdma_device *iwdev, u8 ver); +void irdma_cleanup_cm_core(struct irdma_cm_core *cm_core); +void irdma_next_iw_state(struct irdma_qp *iwqp, u8 state, u8 del_hash, u8 term, + u8 term_len); +int irdma_send_syn(struct irdma_cm_node *cm_node, u32 sendack); +int irdma_send_reset(struct irdma_cm_node *cm_node); +struct irdma_cm_node *irdma_find_node(struct irdma_cm_core *cm_core, + u16 rem_port, u32 *rem_addr, u16 loc_port, + u32 *loc_addr, u16 vlan_id); +int irdma_hw_flush_wqes(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, + struct irdma_qp_flush_info *info, bool wait); +void irdma_gen_ae(struct irdma_pci_f *rf, struct irdma_sc_qp *qp, + struct irdma_gen_ae_info *info, bool wait); +void irdma_copy_ip_ntohl(u32 *dst, __be32 *src); +void irdma_copy_ip_htonl(__be32 *dst, u32 *src); +u16 irdma_get_vlan_ipv4(u32 *addr); +void irdma_get_vlan_mac_ipv6(u32 *addr, u16 *vlan_id, u8 *mac); +struct ib_mr *irdma_reg_phys_mr(struct ib_pd *ib_pd, u64 addr, u64 size, + int acc, u64 *iova_start); +int irdma_upload_qp_context(struct irdma_qp *iwqp, bool freeze, bool raw); +void irdma_del_hmc_objects(struct irdma_sc_dev *dev, + struct irdma_hmc_info *hmc_info, bool privileged, + bool reset, enum irdma_vers vers); +int irdma_obj_aligned_mem(struct irdma_pci_f *rf, struct irdma_dma_mem *memptr, + u32 size, u32 mask); +void irdma_cqp_ce_handler(struct irdma_pci_f *rf, struct irdma_sc_cq *cq); +int irdma_ah_cqp_op(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd, + bool wait, + void (*callback_fcn)(struct irdma_cqp_request *cqp_request), + void *cb_param); +bool irdma_cq_empty(struct irdma_cq *iwcq); +#if IS_ENABLED(CONFIG_CONFIGFS_FS) +struct irdma_device *irdma_get_device_by_name(const char *name); +#endif +#ifdef CONFIG_DEBUG_FS +struct irdma_handler; +void irdma_dbg_pf_init(struct irdma_handler *hdl); +void irdma_dbg_pf_exit(struct irdma_handler *hdl); +void irdma_dbg_init(void); +void irdma_dbg_exit(void); +void irdma_dbg_save_ucontext(struct irdma_device *iwdev, + struct irdma_ucontext *ucontext); +void irdma_dbg_free_ucontext(struct irdma_ucontext *ucontext); +#endif /* DEBUG_SUPPORT */ +#if IS_ENABLED(CONFIG_CONFIGFS_FS) +int irdma_configfs_init(void); +void irdma_configfs_exit(void); +#endif +int irdma_inetaddr_event(struct notifier_block *notifier, unsigned long event, + void *ptr); +int irdma_inet6addr_event(struct notifier_block *notifier, unsigned long event, + void *ptr); +int irdma_net_event(struct notifier_block *notifier, unsigned long event, + void *ptr); +int irdma_netdevice_event(struct notifier_block *notifier, unsigned long event, + void *ptr); +void irdma_unregister_notifiers(struct irdma_device *iwdev); +int irdma_register_notifiers(struct irdma_device *iwdev); +void irdma_set_rf_user_cfg_params(struct irdma_pci_f *rf); +void irdma_add_ip(struct irdma_device *iwdev); +void irdma_add_handler(struct irdma_handler *hdl); +void irdma_del_handler(struct irdma_handler *hdl); +void cqp_compl_worker(struct work_struct *work); +void irdma_cleanup_dead_qps(struct irdma_sc_vsi *vsi); +static inline void irdma_deinit_device(struct irdma_device *iwdev) +{ + if (iwdev->rf->rdma_ver == IRDMA_GEN_2) + irdma_cleanup_dead_qps(&iwdev->vsi); +#ifdef CONFIG_DEBUG_FS + irdma_dbg_pf_exit(iwdev->hdl); +#endif + irdma_rt_deinit_hw(iwdev); + irdma_ctrl_deinit_hw(iwdev->rf); + irdma_del_handler(iwdev->hdl); + kfree(iwdev->hdl); + if (iwdev->rf->vchnl_wq) + destroy_workqueue(iwdev->rf->vchnl_wq); + kfree(iwdev->rf); +} +int irdma_vchnl_req_aeq_vec_map_gen2(struct irdma_sc_dev *dev, u32 idx); +int irdma_vchnl_req_ceq_vec_map_gen2(struct irdma_sc_dev *dev, u16 ceq_id, u32 idx); +#endif /* IRDMA_MAIN_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ofed_kcompat.h b/drivers/intel/irdma-1.14.33/src/irdma/ofed_kcompat.h new file mode 100644 index 000000000..df3253452 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ofed_kcompat.h @@ -0,0 +1,366 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2020 - 2023 Intel Corporation */ +#ifndef OFED_KCOMPAT_H +#define OFED_KCOMPAT_H + +#include +#if defined(RHEL_7_2) +#include +#include +#include +#include +#include +#include + +#define kstrtobool strtobool + +#define refcount_inc atomic_inc +#define refcount_read atomic_read +#define refcount_set atomic_set +#define refcount_dec atomic_dec +#define refcount_dec_and_test atomic_dec_and_test +#define refcount_sub_and_test atomic_sub_and_test +#define refcount_add atomic_add +#define refcount_inc_not_zero atomic_inc_not_zero +#define rdma_ah_attr ib_ah_attr +#define ah_attr_to_dmac(attr) ((attr).dmac) +#define ib_device_put(dev) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define set_ibdev_dma_device(ibdev, dev) \ + ibdev.dma_device = dev + +struct irdma_cm_node; +struct irdma_device; +struct irdma_pci_f; +struct irdma_qp; + +enum ib_mtu ib_mtu_int_to_enum(int mtu); + +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define kc_get_ucontext(udata) to_ucontext(context) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) +#define kc_typeq_ib_wr +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_set_ibdev_add_del_gid(ibdev) do { \ + ibdev->add_gid = irdma_add_gid; \ + ibdev->del_gid = irdma_del_gid; \ +} while (0) +#define wait_queue_entry __wait_queue + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define COPY_USER_PGADDR_VER_1 +#define CREATE_AH_VER_0 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_1 +#define FOR_IFA +#define IB_GET_ETH_SPEED +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_GET_CACHED_GID +#define IB_IW_MANDATORY_AH_OP +#define IB_IW_PKEY +#define IB_MTU_CONVERSIONS +#define IB_UMEM_GET_V0 +#define IB_USER_VERBS_EX_CMD_MODIFY_QP IB_USER_VERBS_CMD_MODIFY_QP +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +enum ib_uverbs_ex_create_cq_flags { + IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION = 1 << 0, + IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN = 1 << 1, +}; + +enum rdma_create_ah_flags { + /* In a sleepable context */ + RDMA_CREATE_AH_SLEEPABLE = BIT(0), +}; + +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) + +#define sizeof_field(TYPE, MEMBER) sizeof((((TYPE *)0)->MEMBER)) +#define offsetofend(TYPE, MEMBER) \ + (offsetof(TYPE, MEMBER) + sizeof_field(TYPE, MEMBER)) + +#endif /* RHEL_7_2 */ + +#if defined(RHEL_7_2) || defined(RHEL_7_4) +#ifdef MODULE +#undef MODULE_DEVICE_TABLE +#define MODULE_DEVICE_TABLE(type, name) \ +extern typeof(name) __mod_##type##__##name##_device_table \ + __attribute__ ((unused, alias(__stringify(name)))) +#endif /* MODULE */ +#endif /* RHEL_7_2 or RHEL_7_4 */ + +#if defined(RHEL_7_4) || defined(RHEL_7_5) || defined(RHEL_7_6) +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define COPY_USER_PGADDR_VER_1 +#define CREATE_AH_VER_1_2 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_2 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_GET_CACHED_GID +#define IB_IW_MANDATORY_AH_OP +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_SET_DRIVER_ID +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +#define wait_queue_entry __wait_queue +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_typeq_ib_wr +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) + +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) + +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) + +#define kc_set_ibdev_add_del_gid(ibdev) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) + +#endif /* RHEL_7_5 */ + +#if defined(RHEL_7_2) || defined(RHEL_7_4) || defined(SLES_12_SP_3) +static inline void addrconf_addr_eui48(u8 *deui, const char *const addr) +{ + memcpy(deui, addr, 3); + deui[3] = 0xFF; + deui[4] = 0xFE; + memcpy(deui + 5, addr + 3, 3); + deui[0] ^= 2; +} + +#define ETHER_ADDR_TO_U64 + +#endif /* defined(RHEL_7_2) || defined(RHEL_7_4) || defined(SLES_12_SP_3) */ +#if defined(SLES_15) || defined(SLES_12_SP_4) || defined(SLES_12_SP_3) +#ifdef SLES_12_SP_3 +#define wait_queue_entry __wait_queue +#endif + +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define COPY_USER_PGADDR_VER_1 +#define CREATE_AH_VER_1_2 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_2 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_GET_CACHED_GID +#define IB_IW_MANDATORY_AH_OP +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_SET_DRIVER_ID +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_typeq_ib_wr +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define set_ibdev_dma_device(ibdev, dev) + +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) + +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) + +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) + +#define kc_set_ibdev_add_del_gid(ibdev) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) +#endif /* SLES_15 */ + +#endif /* OFED_KCOMPAT_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/oracle_kcompat.h b/drivers/intel/irdma-1.14.33/src/irdma/oracle_kcompat.h new file mode 100644 index 000000000..163640687 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/oracle_kcompat.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2020 - 2022 Intel Corporation */ +#ifndef ORACLE_KCOMPAT_H +#define ORACLE_KCOMPAT_H + +/* IB_IW_PKEY */ +#define IB_IW_PKEY + +/* KMAP_LOCAL_PAGE */ +#define USE_KMAP + +/* CREATE_AH */ +#define CREATE_AH_VER_5 + +/* DESTROY_AH */ +#define DESTROY_AH_VER_3 + +/* CREAT_QP */ +#define CREATE_QP_VER_1 + +/* DESTROY_QP */ +#define DESTROY_QP_VER_2 +#define kc_irdma_destroy_qp(ibqp, udata) irdma_destroy_qp(ibqp, udata) + +/* CREATE_CQ */ +#define CREATE_CQ_VER_3 + +/* ALLOC_UCONTEXT/ DEALLOC_UCONTEXT */ +#define ALLOC_UCONTEXT_VER_2 +#define DEALLOC_UCONTEXT_VER_2 + +/* ALLOC_PD , DEALLOC_PD */ +#define ALLOC_PD_VER_3 +#define DEALLOC_PD_VER_3 + +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_HW_STATS_V2 + +#define QUERY_GID_ROCE_V2 +#define MODIFY_PORT_V2 +#define QUERY_PKEY_V2 +#define ROCE_PORT_IMMUTABLE_V2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define IW_PORT_IMMUTABLE_V2 +#define QUERY_GID_V2 +#define QUERY_PORT_V2 + + +/* IRDMA_ALLOC_MW */ +#define IRDMA_ALLOC_MW_VER_1 + +/* IRDMA_ALLOC_MR */ +#define IRDMA_ALLOC_MR_VER_1 + +/* IRDMA_DESTROY_CQ */ +#define IRDMA_DESTROY_CQ_VER_3 + +/* max_sge, ip_gid, gid_attr_network_type, deref_sgid_attr */ +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ +} while (0) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) + +#define kc_typeq_ib_wr const + +/* ib_register_device */ +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) + +#define HAS_IB_SET_DEVICE_OP + +#define kc_set_ibdev_add_del_gid(ibdev) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) + +#define SET_BEST_PAGE_SZ_V2 +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) + +#define UVERBS_CMD_MASK + +#define NETDEV_TO_IBDEV_SUPPORT +#define IB_DEALLOC_DRIVER_SUPPORT + +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) + +#define IN_IFADDR + +int irdma_alloc_ucontext(struct ib_ucontext *uctx, struct ib_udata *udata); +void irdma_dealloc_ucontext(struct ib_ucontext *context); +int irdma_alloc_pd(struct ib_pd *pd, struct ib_udata *udata); +void irdma_dealloc_pd(struct ib_pd *ibpd, struct ib_udata *udata); + +/*****SETUP DMA_DEVICE***************************************************/ +#define set_ibdev_dma_device(ibdev, dev) +/*********************************************************/ + +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) + +#define SET_ROCE_CM_INFO_VER_3 + +#define IB_UMEM_GET_V1 + +#define DEREG_MR_VER_2 + +/* REREG MR */ +#define REREG_MR_VER_1 + +#endif /* ORACLE_KCOMPAT_H */ + diff --git a/drivers/intel/irdma-1.14.33/src/irdma/osdep.h b/drivers/intel/irdma-1.14.33/src/irdma/osdep.h new file mode 100644 index 000000000..2cdf44874 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/osdep.h @@ -0,0 +1,157 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2022 Intel Corporation */ +#ifndef IRDMA_OSDEP_H +#define IRDMA_OSDEP_H + +#include +#include +#include +#ifdef FIELD_PREP +#include +#endif +#include +#include +#include +#if defined(__OFED_4_8__) +#define refcount_t atomic_t +#define refcount_inc atomic_inc +#define refcount_dec_and_test atomic_dec_and_test +#define refcount_set atomic_set +#else +#include +#endif /* OFED_4_8 */ + +#include "distro_ver.h" +#ifdef RHEL_RELEASE_CODE +#if (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(9, 3)) && defined(CONFIG_X86_64) +#undef mb +#define mb __mb +#undef wmb +#define wmb __wmb +#undef rmb +#define rmb __rmb +#endif /* (RHEL_RELEASE_CODE == RHEL_RELEASE_VERSION(9, 3)) && defined(CONFIG_X86_64) */ +#endif /* RHEL_RELEASE_CODE */ + +#define STATS_TIMER_DELAY 60000 + +/* + * See include/linux/compiler_attributes.h in kernel >=5.4 for fallthrough. + * This code really should be in irdma_kcompat.h but to cover shared code + * it had to be here. + * The two #if checks implements fallthrough definition for kernels < 5.4 + * The first check is for new compiler, GCC >= 5.0. If code in compiler_attributes.h + * is not invoked and compiler supports __has_attribute. + * If fallthrough is not defined after the first check, the second check against fallthrough + * will define the macro for the older compiler. + */ +#if !defined(fallthrough) && !defined(__GCC4_has_attribute___noclone__) && defined(__has_attribute) +# define fallthrough __attribute__((__fallthrough__)) +#endif +#ifndef fallthrough +# define fallthrough do {} while (0) +#endif +#ifndef ibdev_dbg +#define ibdev_dbg(ibdev, fmt, ...) dev_dbg(&((ibdev)->dev), fmt, ##__VA_ARGS__) +#define ibdev_err(ibdev, fmt, ...) dev_err(&((ibdev)->dev), fmt, ##__VA_ARGS__) +#define ibdev_warn(ibdev, fmt, ...) dev_warn(&((ibdev)->dev), fmt, ##__VA_ARGS__) +#define ibdev_info(ibdev, fmt, ...) dev_info(&((ibdev)->dev), fmt, ##__VA_ARGS__) +#else +#define irdma_dbg(idev, fmt, ...) \ +do { \ + struct ib_device *ibdev = irdma_get_ibdev(idev); \ + if (ibdev) \ + ibdev_dbg(ibdev, fmt, ##__VA_ARGS__); \ + else \ + dev_dbg(idev_to_dev(idev), fmt, ##__VA_ARGS__); \ +} while (0) +#endif +#ifndef struct_size +#define struct_size(ptr, member, count) \ + (sizeof(*(ptr)) + sizeof(*(ptr)->member) * (count)) +#endif + +struct irdma_dma_info { + dma_addr_t *dmaaddrs; +}; + +struct irdma_dma_mem { + void *va; + dma_addr_t pa; + u32 size; +} __packed; + +struct irdma_virt_mem { + void *va; + u32 size; +} __packed; + +struct irdma_sc_vsi; +struct irdma_sc_dev; +struct irdma_sc_qp; +struct irdma_puda_buf; +struct irdma_puda_cmpl_info; +struct irdma_update_sds_info; +struct irdma_hmc_fcn_info; +struct irdma_hw; +struct irdma_pci_f; +struct irdma_vchnl_req; +struct irdma_vchnl_manage_pble_info; + +#ifndef FIELD_PREP + +#if defined(__OFED_4_8__) +/* Special handling for 7.2/OFED. The GENMASK macros need to be updated */ +#undef GENMASK +#define GENMASK(h, l) \ + (((~0UL) - (1UL << (l)) + 1) & (~0UL >> (BITS_PER_LONG - 1 - (h)))) +#undef GENMASK_ULL +#define GENMASK_ULL(h, l) \ + (((~0ULL) << (l)) & (~0ULL >> (BITS_PER_LONG_LONG - 1 - (h)))) +#endif +/* Compat for rdma-core-27.0 and OFED 4.8/RHEL 7.2. Not for UPSTREAM */ +#define __bf_shf(x) (__builtin_ffsll(x) - 1) +#define FIELD_PREP(_mask, _val) \ + ({ \ + ((typeof(_mask))(_val) << __bf_shf(_mask)) & (_mask); \ + }) + +#define FIELD_GET(_mask, _reg) \ + ({ \ + (typeof(_mask))(((_reg) & (_mask)) >> __bf_shf(_mask)); \ + }) +#endif /* FIELD_PREP */ +struct ib_device *to_ibdev(struct irdma_sc_dev *dev); +void irdma_ieq_mpa_crc_ae(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp); +int irdma_ieq_check_mpacrc(struct shash_desc *desc, void *addr, u32 len, + u32 val); +struct irdma_sc_qp *irdma_ieq_get_qp(struct irdma_sc_dev *dev, + struct irdma_puda_buf *buf); +void irdma_send_ieq_ack(struct irdma_sc_qp *qp); +void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len, + u32 seqnum); +void irdma_free_hash_desc(struct shash_desc *hash_desc); +int irdma_init_hash_desc(struct shash_desc **hash_desc); +int irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info, + struct irdma_puda_buf *buf); +int irdma_cqp_sds_cmd(struct irdma_sc_dev *dev, + struct irdma_update_sds_info *info); +int irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev, + struct irdma_hmc_fcn_info *hmcfcninfo, + u16 *pmf_idx); +void *irdma_remove_cqp_head(struct irdma_sc_dev *dev); +void irdma_term_modify_qp(struct irdma_sc_qp *qp, u8 next_state, u8 term, + u8 term_len); +void irdma_terminate_done(struct irdma_sc_qp *qp, int timeout_occurred); +void irdma_terminate_start_timer(struct irdma_sc_qp *qp); +void irdma_terminate_del_timer(struct irdma_sc_qp *qp); +void irdma_hw_stats_start_timer(struct irdma_sc_vsi *vsi); +void irdma_hw_stats_stop_timer(struct irdma_sc_vsi *vsi); +void wr32(struct irdma_hw *hw, u32 reg, u32 val); +u32 rd32(struct irdma_hw *hw, u32 reg); +u64 rd64(struct irdma_hw *hw, u32 reg); +int irdma_map_vm_page_list(struct irdma_hw *hw, void *va, dma_addr_t *pg_dma, + u32 pg_cnt); +void irdma_unmap_vm_page_list(struct irdma_hw *hw, dma_addr_t *pg_dma, u32 pg_cnt); +#define bitmap_free(bitmap) kfree(bitmap) +#endif /* IRDMA_OSDEP_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/pble.c b/drivers/intel/irdma-1.14.33/src/irdma/pble.c new file mode 100644 index 000000000..0a8294e39 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/pble.c @@ -0,0 +1,542 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "osdep.h" +#include "hmc.h" +#include "defs.h" +#include "type.h" +#include "protos.h" +#include "virtchnl.h" +#include "pble.h" + +static int add_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc); + +/** + * irdma_destroy_pble_prm - destroy prm during module unload + * @pble_rsrc: pble resources + */ +void irdma_destroy_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc) +{ + struct irdma_chunk *chunk; + struct irdma_pble_prm *pinfo = &pble_rsrc->pinfo; + + while (!list_empty(&pinfo->clist)) { + chunk = (struct irdma_chunk *) pinfo->clist.next; + list_del(&chunk->list); + if (chunk->type == PBLE_SD_PAGED) + irdma_pble_free_paged_mem(chunk); + bitmap_free(chunk->bitmapbuf); + kfree(chunk->chunkmem.va); + } +} + +/** + * irdma_hmc_init_pble - Initialize pble resources during module load + * @dev: irdma_sc_dev struct + * @pble_rsrc: pble resources + */ +int irdma_hmc_init_pble(struct irdma_sc_dev *dev, + struct irdma_hmc_pble_rsrc *pble_rsrc) +{ + struct irdma_hmc_info *hmc_info; + u32 fpm_idx = 0; + int status = 0; + + hmc_info = dev->hmc_info; + pble_rsrc->dev = dev; + pble_rsrc->fpm_base_addr = hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].base; + /* Start pble' on 4k boundary */ + if (pble_rsrc->fpm_base_addr & 0xfff) + fpm_idx = (4096 - (pble_rsrc->fpm_base_addr & 0xfff)) >> 3; + pble_rsrc->unallocated_pble = + hmc_info->hmc_obj[IRDMA_HMC_IW_PBLE].cnt - fpm_idx; + pble_rsrc->next_fpm_addr = pble_rsrc->fpm_base_addr + (fpm_idx << 3); + pble_rsrc->pinfo.pble_shift = PBLE_SHIFT; + + mutex_init(&pble_rsrc->pble_mutex_lock); + + spin_lock_init(&pble_rsrc->pinfo.prm_lock); + INIT_LIST_HEAD(&pble_rsrc->pinfo.clist); + if (add_pble_prm(pble_rsrc)) { + irdma_destroy_pble_prm(pble_rsrc); + status = -ENOMEM; + } + + return status; +} + +/** + * get_sd_pd_idx - Returns sd index, pd index and rel_pd_idx from fpm address + * @pble_rsrc: structure containing fpm address + * @idx: where to return indexes + */ +static void get_sd_pd_idx(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct sd_pd_idx *idx) +{ + idx->sd_idx = (u32)pble_rsrc->next_fpm_addr / IRDMA_HMC_DIRECT_BP_SIZE; + idx->pd_idx = (u32)(pble_rsrc->next_fpm_addr / IRDMA_HMC_PAGED_BP_SIZE); + idx->rel_pd_idx = (idx->pd_idx % IRDMA_HMC_PD_CNT_IN_SD); +} + +/** + * add_sd_direct - add sd direct for pble + * @pble_rsrc: pble resource ptr + * @info: page info for sd + */ +static int add_sd_direct(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_add_page_info *info) +{ + struct irdma_sc_dev *dev = pble_rsrc->dev; + int ret_code = 0; + struct sd_pd_idx *idx = &info->idx; + struct irdma_chunk *chunk = info->chunk; + struct irdma_hmc_info *hmc_info = info->hmc_info; + struct irdma_hmc_sd_entry *sd_entry = info->sd_entry; + u32 offset = 0; + + if (!sd_entry->valid) { + ret_code = irdma_add_sd_table_entry(dev->hw, hmc_info, + info->idx.sd_idx, + IRDMA_SD_TYPE_DIRECT, + IRDMA_HMC_DIRECT_BP_SIZE); + if (ret_code) + return ret_code; + + chunk->type = PBLE_SD_CONTIGOUS; + } + + offset = idx->rel_pd_idx << HMC_PAGED_BP_SHIFT; + chunk->size = info->pages << HMC_PAGED_BP_SHIFT; + chunk->vaddr = sd_entry->u.bp.addr.va + offset; + chunk->fpm_addr = pble_rsrc->next_fpm_addr; + ibdev_dbg(to_ibdev(dev), + "PBLE: chunk_size[%lld] = 0x%llx vaddr=0x%pK fpm_addr = %llx\n", + chunk->size, chunk->size, chunk->vaddr, chunk->fpm_addr); + + return 0; +} + +/** + * fpm_to_idx - given fpm address, get pble index + * @pble_rsrc: pble resource management + * @addr: fpm address for index + */ +static u32 fpm_to_idx(struct irdma_hmc_pble_rsrc *pble_rsrc, u64 addr) +{ + u64 idx; + + idx = (addr - (pble_rsrc->fpm_base_addr)) >> 3; + + return (u32)idx; +} + +/** + * add_bp_pages - add backing pages for sd + * @pble_rsrc: pble resource management + * @info: page info for sd + */ +static int add_bp_pages(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_add_page_info *info) +{ + struct irdma_sc_dev *dev = pble_rsrc->dev; + u8 *addr; + struct irdma_dma_mem mem; + struct irdma_hmc_pd_entry *pd_entry; + struct irdma_hmc_sd_entry *sd_entry = info->sd_entry; + struct irdma_hmc_info *hmc_info = info->hmc_info; + struct irdma_chunk *chunk = info->chunk; + struct irdma_manage_pble_info pble_info; + int status = 0; + u32 rel_pd_idx = info->idx.rel_pd_idx; + u32 pd_idx = info->idx.pd_idx; + u32 i; + + if (irdma_pble_get_paged_mem(chunk, info->pages)) + return -ENOMEM; + + status = irdma_add_sd_table_entry(dev->hw, hmc_info, info->idx.sd_idx, + IRDMA_SD_TYPE_PAGED, + IRDMA_HMC_DIRECT_BP_SIZE); + if (status) + goto error; + + if (dev->hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_3 && !dev->privileged) { + status = irdma_vchnl_req_add_hmc_objs( + dev, IRDMA_HMC_IW_PBLE, + fpm_to_idx(pble_rsrc, pble_rsrc->next_fpm_addr), + (info->pages << PBLE_512_SHIFT)); + if (status) + goto error; + } + + addr = chunk->vaddr; + for (i = 0; i < info->pages; i++) { + mem.pa = (u64)chunk->dmainfo.dmaaddrs[i]; + mem.size = 4096; + mem.va = addr; + pd_entry = &sd_entry->u.pd_table.pd_entry[rel_pd_idx++]; + if (!pd_entry->valid) { + status = irdma_add_pd_table_entry(dev, hmc_info, + pd_idx++, &mem); + if (status) + goto error; + + addr += 4096; + } + } + + if (dev->hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_3 && !dev->privileged) { + pble_info.first_pd_index = (u16)info->idx.rel_pd_idx; + pble_info.inv_pd_ent = false; + pble_info.pd_entry_cnt = PBLE_PER_PAGE; + pble_info.pd_pl_pba = sd_entry->u.pd_table.pd_page_addr.pa; + pble_info.sd_index = info->idx.sd_idx; + + status = irdma_manage_pble_bp(dev, &pble_info); + if (status) + goto error; + } + chunk->fpm_addr = pble_rsrc->next_fpm_addr; + return 0; + +error: + irdma_pble_free_paged_mem(chunk); + + return status; +} + +/** + * irdma_get_type - add a sd entry type for sd + * @dev: irdma_sc_dev struct + * @idx: index of sd + * @pages: pages in the sd + */ +static enum irdma_sd_entry_type irdma_get_type(struct irdma_sc_dev *dev, + struct sd_pd_idx *idx, u32 pages) +{ + enum irdma_sd_entry_type sd_entry_type; + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) + sd_entry_type = (!idx->rel_pd_idx && + pages == IRDMA_HMC_PD_CNT_IN_SD) ? + IRDMA_SD_TYPE_DIRECT : IRDMA_SD_TYPE_PAGED; + else + sd_entry_type = (!idx->rel_pd_idx && + pages == IRDMA_HMC_PD_CNT_IN_SD && + dev->privileged) ? + IRDMA_SD_TYPE_DIRECT : IRDMA_SD_TYPE_PAGED; + return sd_entry_type; +} + +/** + * add_pble_prm - add a sd entry for pble resoure + * @pble_rsrc: pble resource management + */ +static int add_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc) +{ + struct irdma_sc_dev *dev = pble_rsrc->dev; + struct irdma_hmc_sd_entry *sd_entry; + struct irdma_hmc_info *hmc_info; + struct irdma_chunk *chunk; + struct irdma_add_page_info info; + struct sd_pd_idx *idx = &info.idx; + int ret_code = 0; + enum irdma_sd_entry_type sd_entry_type; + u64 sd_reg_val = 0; + struct irdma_virt_mem chunkmem; + u32 pages; + + if (pble_rsrc->unallocated_pble < PBLE_PER_PAGE) + return -ENOMEM; + + if (pble_rsrc->next_fpm_addr & 0xfff) + return -EINVAL; + + chunkmem.size = sizeof(*chunk); + chunkmem.va = kzalloc(chunkmem.size, GFP_KERNEL); + if (!chunkmem.va) + return -ENOMEM; + + chunk = chunkmem.va; + chunk->chunkmem = chunkmem; + hmc_info = dev->hmc_info; + chunk->dev = dev; + chunk->fpm_addr = pble_rsrc->next_fpm_addr; + get_sd_pd_idx(pble_rsrc, idx); + sd_entry = &hmc_info->sd_table.sd_entry[idx->sd_idx]; + pages = (idx->rel_pd_idx) ? (IRDMA_HMC_PD_CNT_IN_SD - idx->rel_pd_idx) : + IRDMA_HMC_PD_CNT_IN_SD; + pages = min(pages, pble_rsrc->unallocated_pble >> PBLE_512_SHIFT); + info.chunk = chunk; + info.hmc_info = hmc_info; + info.pages = pages; + info.sd_entry = sd_entry; + if (!sd_entry->valid) + sd_entry_type = irdma_get_type(dev, idx, pages); + else + sd_entry_type = sd_entry->entry_type; + + ibdev_dbg(to_ibdev(dev), + "PBLE: pages = %d, unallocated_pble[%d] current_fpm_addr = %llx\n", + pages, pble_rsrc->unallocated_pble, + pble_rsrc->next_fpm_addr); + ibdev_dbg(to_ibdev(dev), "PBLE: sd_entry_type = %d\n", sd_entry_type); + if (sd_entry_type == IRDMA_SD_TYPE_DIRECT) + ret_code = add_sd_direct(pble_rsrc, &info); + + if (ret_code) + sd_entry_type = IRDMA_SD_TYPE_PAGED; + else + pble_rsrc->stats_direct_sds++; + + if (sd_entry_type == IRDMA_SD_TYPE_PAGED) { + ret_code = add_bp_pages(pble_rsrc, &info); + if (ret_code) + goto err_bp_pages; + else + pble_rsrc->stats_paged_sds++; + } + + ret_code = irdma_prm_add_pble_mem(&pble_rsrc->pinfo, chunk); + if (ret_code) + goto err_bp_pages; + + pble_rsrc->next_fpm_addr += chunk->size; + ibdev_dbg(to_ibdev(dev), + "PBLE: next_fpm_addr = %llx chunk_size[%llu] = 0x%llx\n", + pble_rsrc->next_fpm_addr, chunk->size, chunk->size); + pble_rsrc->unallocated_pble -= (u32)(chunk->size >> 3); + sd_reg_val = (sd_entry_type == IRDMA_SD_TYPE_PAGED) ? + sd_entry->u.pd_table.pd_page_addr.pa : + sd_entry->u.bp.addr.pa; + if ((dev->privileged && !sd_entry->valid) || + dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + ret_code = irdma_hmc_sd_one(dev, hmc_info->hmc_fn_id, + sd_reg_val, idx->sd_idx, + sd_entry->entry_type, true); + if (ret_code) + goto error; + } + + sd_entry->valid = true; + list_add(&chunk->list, &pble_rsrc->pinfo.clist); + return 0; + +error: + bitmap_free(chunk->bitmapbuf); +err_bp_pages: + kfree(chunk->chunkmem.va); + + return ret_code; +} + +/** + * free_lvl2 - fee level 2 pble + * @pble_rsrc: pble resource management + * @palloc: level 2 pble allocation + */ +static void free_lvl2(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_pble_alloc *palloc) +{ + u32 i; + struct irdma_pble_level2 *lvl2 = &palloc->level2; + struct irdma_pble_info *root = &lvl2->root; + struct irdma_pble_info *leaf = lvl2->leaf; + + for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) { + if (leaf->addr) + irdma_prm_return_pbles(&pble_rsrc->pinfo, + &leaf->chunkinfo); + else + break; + } + + if (root->addr) + irdma_prm_return_pbles(&pble_rsrc->pinfo, &root->chunkinfo); + + kfree(lvl2->leafmem.va); + lvl2->leaf = NULL; +} + +/** + * get_lvl2_pble - get level 2 pble resource + * @pble_rsrc: pble resource management + * @palloc: level 2 pble allocation + */ +static int get_lvl2_pble(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_pble_alloc *palloc) +{ + u32 lf4k, lflast, total, i; + u32 pblcnt = PBLE_PER_PAGE; + u64 *addr; + struct irdma_pble_level2 *lvl2 = &palloc->level2; + struct irdma_pble_info *root = &lvl2->root; + struct irdma_pble_info *leaf; + int ret_code; + u64 fpm_addr; + + /* number of full 512 (4K) leafs) */ + lf4k = palloc->total_cnt >> 9; + lflast = palloc->total_cnt % PBLE_PER_PAGE; + total = (lflast == 0) ? lf4k : lf4k + 1; + lvl2->leaf_cnt = total; + + lvl2->leafmem.size = (sizeof(*leaf) * total); + lvl2->leafmem.va = kzalloc(lvl2->leafmem.size, GFP_KERNEL); + if (!lvl2->leafmem.va) + return -ENOMEM; + + lvl2->leaf = lvl2->leafmem.va; + leaf = lvl2->leaf; + ret_code = irdma_prm_get_pbles(&pble_rsrc->pinfo, &root->chunkinfo, + total << 3, &root->addr, &fpm_addr); + if (ret_code) { + kfree(lvl2->leafmem.va); + lvl2->leaf = NULL; + return -ENOMEM; + } + + root->idx = fpm_to_idx(pble_rsrc, fpm_addr); + root->cnt = total; + addr = root->addr; + for (i = 0; i < total; i++, leaf++) { + pblcnt = (lflast && ((i + 1) == total)) ? + lflast : PBLE_PER_PAGE; + ret_code = irdma_prm_get_pbles(&pble_rsrc->pinfo, + &leaf->chunkinfo, pblcnt << 3, + &leaf->addr, &fpm_addr); + if (ret_code) + goto error; + + leaf->idx = fpm_to_idx(pble_rsrc, fpm_addr); + + leaf->cnt = pblcnt; + *addr = (u64)leaf->idx; + addr++; + } + + palloc->level = PBLE_LEVEL_2; + pble_rsrc->stats_lvl2++; + return 0; + +error: + free_lvl2(pble_rsrc, palloc); + + return -ENOMEM; +} + +/** + * get_lvl1_pble - get level 1 pble resource + * @pble_rsrc: pble resource management + * @palloc: level 1 pble allocation + */ +static int get_lvl1_pble(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_pble_alloc *palloc) +{ + int ret_code; + u64 fpm_addr; + struct irdma_pble_info *lvl1 = &palloc->level1; + + ret_code = irdma_prm_get_pbles(&pble_rsrc->pinfo, &lvl1->chunkinfo, + palloc->total_cnt << 3, &lvl1->addr, + &fpm_addr); + if (ret_code) + return -ENOMEM; + + palloc->level = PBLE_LEVEL_1; + lvl1->idx = fpm_to_idx(pble_rsrc, fpm_addr); + lvl1->cnt = palloc->total_cnt; + pble_rsrc->stats_lvl1++; + + return 0; +} + +/** + * get_lvl1_lvl2_pble - calls get_lvl1 and get_lvl2 pble routine + * @pble_rsrc: pble resources + * @palloc: contains all inforamtion regarding pble (idx + pble addr) + * @lvl: Bitmask for requested pble level + */ +static int get_lvl1_lvl2_pble(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_pble_alloc *palloc, u8 lvl) +{ + int status = 0; + + status = get_lvl1_pble(pble_rsrc, palloc); + if (!status || lvl == PBLE_LEVEL_1 || palloc->total_cnt <= PBLE_PER_PAGE) + return status; + + status = get_lvl2_pble(pble_rsrc, palloc); + + return status; +} + +/** + * irdma_get_pble - allocate pbles from the prm + * @pble_rsrc: pble resources + * @palloc: contains all inforamtion regarding pble (idx + pble addr) + * @pble_cnt: #of pbles requested + * @lvl: requested pble level mask + */ +int irdma_get_pble(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_pble_alloc *palloc, u32 pble_cnt, + u8 lvl) +{ + int status = 0; + int max_sds = 0; + int i; + + palloc->total_cnt = pble_cnt; + palloc->level = PBLE_LEVEL_0; + + mutex_lock(&pble_rsrc->pble_mutex_lock); + + /*check first to see if we can get pble's without acquiring + * additional sd's + */ + status = get_lvl1_lvl2_pble(pble_rsrc, palloc, lvl); + if (!status) + goto exit; + + max_sds = (palloc->total_cnt >> 18) + 1; + for (i = 0; i < max_sds; i++) { + status = add_pble_prm(pble_rsrc); + if (status) + break; + + status = get_lvl1_lvl2_pble(pble_rsrc, palloc, lvl); + /* if level1_only, only go through it once */ + if (!status || lvl == PBLE_LEVEL_1) + break; + } + +exit: + if (!status) { + pble_rsrc->allocdpbles += pble_cnt; + pble_rsrc->stats_alloc_ok++; + } else { + pble_rsrc->stats_alloc_fail++; + } + mutex_unlock(&pble_rsrc->pble_mutex_lock); + + return status; +} + +/** + * irdma_free_pble - put pbles back into prm + * @pble_rsrc: pble resources + * @palloc: contains all information regarding pble resource being freed + */ +void irdma_free_pble(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_pble_alloc *palloc) +{ + if (palloc->level == PBLE_LEVEL_2) + free_lvl2(pble_rsrc, palloc); + else + irdma_prm_return_pbles(&pble_rsrc->pinfo, + &palloc->level1.chunkinfo); + + mutex_lock(&pble_rsrc->pble_mutex_lock); + pble_rsrc->freedpbles += palloc->total_cnt; + pble_rsrc->stats_alloc_freed++; + mutex_unlock(&pble_rsrc->pble_mutex_lock); +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/pble.h b/drivers/intel/irdma-1.14.33/src/irdma/pble.h new file mode 100644 index 000000000..9a7ad1cd6 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/pble.h @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef IRDMA_PBLE_H +#define IRDMA_PBLE_H + +#define PBLE_SHIFT 6 +#define PBLE_PER_PAGE 512 +#define HMC_PAGED_BP_SHIFT 12 +#define PBLE_512_SHIFT 9 +#define PBLE_INVALID_IDX 0xffffffff + +enum irdma_pble_level { + PBLE_LEVEL_0 = 0, + PBLE_LEVEL_1 = 1, + PBLE_LEVEL_2 = 2, +}; + +enum irdma_alloc_type { + PBLE_NO_ALLOC = 0, + PBLE_SD_CONTIGOUS = 1, + PBLE_SD_PAGED = 2, +}; + +struct irdma_chunk; + +struct irdma_pble_chunkinfo { + struct irdma_chunk *pchunk; + u64 bit_idx; + u64 bits_used; +}; + +struct irdma_pble_info { + u64 *addr; + u32 idx; + u32 cnt; + struct irdma_pble_chunkinfo chunkinfo; +}; + +struct irdma_pble_level2 { + struct irdma_pble_info root; + struct irdma_pble_info *leaf; + struct irdma_virt_mem leafmem; + u32 leaf_cnt; +}; + +struct irdma_pble_alloc { + u32 total_cnt; + enum irdma_pble_level level; + union { + struct irdma_pble_info level1; + struct irdma_pble_level2 level2; + }; +}; + +struct sd_pd_idx { + u32 sd_idx; + u32 pd_idx; + u32 rel_pd_idx; +}; + +struct irdma_add_page_info { + struct irdma_chunk *chunk; + struct irdma_hmc_sd_entry *sd_entry; + struct irdma_hmc_info *hmc_info; + struct sd_pd_idx idx; + u32 pages; +}; + +struct irdma_manage_pble_info { + u32 sd_index; + u16 first_pd_index; + u16 pd_entry_cnt; + u8 inv_pd_ent; + u64 pd_pl_pba; +}; + +struct irdma_chunk { + struct list_head list; + struct irdma_dma_info dmainfo; + unsigned long *bitmapbuf; + + u32 sizeofbitmap; + u64 size; + void *vaddr; + u64 fpm_addr; + u32 pg_cnt; + enum irdma_alloc_type type; + struct irdma_sc_dev *dev; + struct irdma_virt_mem chunkmem; +}; + +struct irdma_pble_prm { + struct list_head clist; + spinlock_t prm_lock; /* protect prm bitmap */ + u64 total_pble_alloc; + u64 free_pble_cnt; + u8 pble_shift; +}; + +struct irdma_hmc_pble_rsrc { + u32 unallocated_pble; + struct mutex pble_mutex_lock; /* protect PBLE resource */ + struct irdma_sc_dev *dev; + u64 fpm_base_addr; + u64 next_fpm_addr; + struct irdma_pble_prm pinfo; + u64 allocdpbles; + u64 freedpbles; + u32 stats_direct_sds; + u32 stats_paged_sds; + u64 stats_alloc_ok; + u64 stats_alloc_fail; + u64 stats_alloc_freed; + u64 stats_lvl1; + u64 stats_lvl2; +}; + +void irdma_destroy_pble_prm(struct irdma_hmc_pble_rsrc *pble_rsrc); +int irdma_hmc_init_pble(struct irdma_sc_dev *dev, + struct irdma_hmc_pble_rsrc *pble_rsrc); +void irdma_free_pble(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_pble_alloc *palloc); +int irdma_get_pble(struct irdma_hmc_pble_rsrc *pble_rsrc, + struct irdma_pble_alloc *palloc, u32 pble_cnt, + u8 lvl); +int irdma_prm_add_pble_mem(struct irdma_pble_prm *pprm, + struct irdma_chunk *pchunk); +int irdma_prm_get_pbles(struct irdma_pble_prm *pprm, + struct irdma_pble_chunkinfo *chunkinfo, u64 mem_size, + u64 **vaddr, u64 *fpm_addr); +void irdma_prm_return_pbles(struct irdma_pble_prm *pprm, + struct irdma_pble_chunkinfo *chunkinfo); +void irdma_pble_acquire_lock(struct irdma_hmc_pble_rsrc *pble_rsrc, + unsigned long *flags); +void irdma_pble_release_lock(struct irdma_hmc_pble_rsrc *pble_rsrc, + unsigned long *flags); +void irdma_pble_free_paged_mem(struct irdma_chunk *chunk); +int irdma_pble_get_paged_mem(struct irdma_chunk *chunk, u32 pg_cnt); +int irdma_manage_pble_bp(struct irdma_sc_dev *dev, + struct irdma_manage_pble_info *info); +#endif /* IRDMA_PBLE_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/protos.h b/drivers/intel/irdma-1.14.33/src/irdma/protos.h new file mode 100644 index 000000000..51d285969 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/protos.h @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2016 - 2023 Intel Corporation */ +#ifndef IRDMA_PROTOS_H +#define IRDMA_PROTOS_H + +#define PAUSE_TIMER_VAL 0xffff +#define REFRESH_THRESHOLD 0x7fff +#define HIGH_THRESHOLD 0x800 +#define LOW_THRESHOLD 0x200 +#define ALL_TC2PFC 0xff +#define CQP_COMPL_WAIT_TIME_MS 10 +#define CQP_TIMEOUT_THRESHOLD 500 +#define CQP_DEF_CMPL_TIMEOUT_THRESHOLD 2500 + +/* init operations */ +int irdma_sc_dev_init(struct irdma_sc_dev *dev, struct irdma_device_init_info *info); +void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp); +__le64 *irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp *cqp, u64 scratch); +int irdma_sc_mr_fast_register(struct irdma_sc_qp *qp, + struct irdma_fast_reg_stag_info *info, + bool post_sq); +void irdma_init_config_check(struct irdma_config_check *cc, + u8 traffic_class, + u16 qs_handle); +/* HMC/FPM functions */ +int irdma_sc_init_iw_hmc(struct irdma_sc_dev *dev, u16 hmc_fn_id); +int irdma_pf_init_vfhmc(struct irdma_sc_dev *dev, u8 vf_hmc_fn_id); +/* stats misc */ +int irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev, + struct irdma_vsi_pestat *pestat, bool wait); +void irdma_cqp_gather_stats_gen1(struct irdma_sc_dev *dev, + struct irdma_vsi_pestat *pestat); +void irdma_hw_stats_read_all(struct irdma_vsi_pestat *stats, + const u64 *hw_stats_regs); +int irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd, + struct irdma_ws_node_info *node_info); +int irdma_cqp_ws_move_cmd(struct irdma_sc_dev *dev, + struct irdma_ws_move_node_info *node_move_info); +#if IS_ENABLED(CONFIG_CONFIGFS_FS) +int irdma_cqp_up_map_cmd(struct irdma_sc_dev *dev, u8 cmd, + struct irdma_up_info *map_info); +#endif /* CONFIG_CONFIGFS_FS */ +int irdma_cqp_ceq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_ceq *sc_ceq, + u8 op); +int irdma_cqp_aeq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_aeq *sc_aeq, + u8 op); +int irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd, + struct irdma_stats_inst_info *stats_info); +void irdma_update_stats(struct irdma_dev_hw_stats *hw_stats, + struct irdma_gather_stats *gather_stats, + struct irdma_gather_stats *last_gather_stats, + const struct irdma_hw_stat_map *map, + u16 max_stat_idx); +/* vsi functions */ +int irdma_vsi_stats_init(struct irdma_sc_vsi *vsi, + struct irdma_vsi_stats_info *info); +void irdma_vsi_stats_free(struct irdma_sc_vsi *vsi); +void irdma_sc_vsi_init(struct irdma_sc_vsi *vsi, + struct irdma_vsi_init_info *info); +int irdma_sc_add_cq_ctx(struct irdma_sc_ceq *ceq, struct irdma_sc_cq *cq); +void irdma_sc_remove_cq_ctx(struct irdma_sc_ceq *ceq, struct irdma_sc_cq *cq); +/* misc L2 param change functions */ +void irdma_change_l2params(struct irdma_sc_vsi *vsi, + struct irdma_l2params *l2params); +void irdma_sc_suspend_resume_qps(struct irdma_sc_vsi *vsi, u8 suspend); +int irdma_cqp_qp_suspend_resume(struct irdma_sc_qp *qp, u8 cmd); +void irdma_qp_add_qos(struct irdma_sc_qp *qp); +void irdma_qp_rem_qos(struct irdma_sc_qp *qp); +struct irdma_sc_qp *irdma_get_qp_from_list(struct list_head *head, + struct irdma_sc_qp *qp); +void irdma_reinitialize_ieq(struct irdma_sc_vsi *vsi); +u16 irdma_alloc_ws_node_id(struct irdma_sc_dev *dev); +void irdma_free_ws_node_id(struct irdma_sc_dev *dev, u16 node_id); +struct irdma_sc_vsi *irdma_update_vsi_ctx(struct irdma_sc_dev *dev, + struct irdma_vchnl_dev *vc_dev, + bool enable); +void irdma_update_vf_vlan_cfg(struct irdma_sc_dev *dev, + struct irdma_vchnl_dev *vc_dev); +/* terminate functions*/ +void irdma_terminate_send_fin(struct irdma_sc_qp *qp); + +void irdma_terminate_connection(struct irdma_sc_qp *qp, + struct irdma_aeqe_info *info); + +void irdma_terminate_received(struct irdma_sc_qp *qp, + struct irdma_aeqe_info *info); +/* dynamic memory allocation */ +/* misc */ +u8 irdma_get_encoded_wqe_size(u32 wqsize, enum irdma_queue_type queue_type); +void irdma_modify_qp_to_err(struct irdma_sc_qp *sc_qp); +int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch, + u16 hmc_fn_id, bool post_sq, + bool poll_registers); +int irdma_cfg_fpm_val(struct irdma_sc_dev *dev, u32 qp_count); +int irdma_get_rdma_features(struct irdma_sc_dev *dev); +void free_sd_mem(struct irdma_sc_dev *dev); +int irdma_process_cqp_cmd(struct irdma_sc_dev *dev, + struct cqp_cmds_info *pcmdinfo); +int irdma_process_bh(struct irdma_sc_dev *dev); +extern void dump_ctx(struct irdma_sc_dev *dev, u32 pf_num, u32 qp_num); +void dumpCSR(struct irdma_sc_dev *dev); +void dumpCSRx(struct irdma_sc_dev *dev); +void dumpcls(struct irdma_sc_dev *dev); +int irdma_cqp_sds_cmd(struct irdma_sc_dev *dev, + struct irdma_update_sds_info *info); +int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev, + struct irdma_dma_mem *val_mem, u16 hmc_fn_id); +int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev, + struct irdma_dma_mem *val_mem, u16 hmc_fn_id); +int irdma_alloc_query_fpm_buf(struct irdma_sc_dev *dev, + struct irdma_dma_mem *mem); +int irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev, + struct irdma_hmc_fcn_info *hmcfcninfo, + u16 *pmf_idx); +int irdma_set_attr_from_fragcnt(struct irdma_sc_dev *dev, u8 max_fragcnt); +void *irdma_remove_cqp_head(struct irdma_sc_dev *dev); +u64 ether_addr_to_u64(const u8 *eth_add); +#endif /* IRDMA_PROTOS_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/puda.c b/drivers/intel/irdma-1.14.33/src/irdma/puda.c new file mode 100644 index 000000000..ab4c70e31 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/puda.c @@ -0,0 +1,1728 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "osdep.h" +#include "hmc.h" +#include "defs.h" +#include "type.h" +#include "protos.h" +#include "puda.h" +#include "ws.h" + +static void irdma_ieq_receive(struct irdma_sc_vsi *vsi, + struct irdma_puda_buf *buf); +static void irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid); +static void irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, + struct irdma_puda_buf *buf, u32 wqe_idx); +/** + * irdma_puda_get_listbuf - get buffer from puda list + * @list: list to use for buffers (ILQ or IEQ) + */ +static struct irdma_puda_buf *irdma_puda_get_listbuf(struct list_head *list) +{ + struct irdma_puda_buf *buf = NULL; + + if (!list_empty(list)) { + buf = (struct irdma_puda_buf *)list->next; + list_del((struct list_head *)&buf->list); + } + + return buf; +} + +/** + * irdma_puda_get_bufpool - return buffer from resource + * @rsrc: resource to use for buffer + */ +struct irdma_puda_buf *irdma_puda_get_bufpool(struct irdma_puda_rsrc *rsrc) +{ + struct irdma_puda_buf *buf = NULL; + struct list_head *list = &rsrc->bufpool; + unsigned long flags; + + spin_lock_irqsave(&rsrc->bufpool_lock, flags); + buf = irdma_puda_get_listbuf(list); + if (buf) { + rsrc->avail_buf_count--; + buf->vsi = rsrc->vsi; + } else { + rsrc->stats_buf_alloc_fail++; + } + spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); + + return buf; +} + +/** + * irdma_puda_ret_bufpool - return buffer to rsrc list + * @rsrc: resource to use for buffer + * @buf: buffer to return to resource + */ +void irdma_puda_ret_bufpool(struct irdma_puda_rsrc *rsrc, + struct irdma_puda_buf *buf) +{ + unsigned long flags; + + buf->do_lpb = false; + spin_lock_irqsave(&rsrc->bufpool_lock, flags); + list_add(&buf->list, &rsrc->bufpool); + spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); + rsrc->avail_buf_count++; +} + +/** + * irdma_puda_post_recvbuf - set wqe for rcv buffer + * @rsrc: resource ptr + * @wqe_idx: wqe index to use + * @buf: puda buffer for rcv q + * @initial: flag if during init time + */ +static void irdma_puda_post_recvbuf(struct irdma_puda_rsrc *rsrc, u32 wqe_idx, + struct irdma_puda_buf *buf, bool initial) +{ + __le64 *wqe; + struct irdma_sc_qp *qp = &rsrc->qp; + u64 offset24 = 0; + + /* Synch buffer for use by device */ + dma_sync_single_for_device(rsrc->dev->hw->device, buf->mem.pa, + buf->mem.size, DMA_BIDIRECTIONAL); + qp->qp_uk.rq_wrid_array[wqe_idx] = (uintptr_t)buf; + wqe = qp->qp_uk.rq_base[wqe_idx].elem; + if (!initial) + get_64bit_val(wqe, 24, &offset24); + + offset24 = (offset24) ? 0 : FIELD_PREP(IRDMAQPSQ_VALID, 1); + + set_64bit_val(wqe, 16, 0); + set_64bit_val(wqe, 0, buf->mem.pa); + if (qp->qp_uk.uk_attrs->hw_rev == IRDMA_GEN_1) { + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, buf->mem.size)); + } else { + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_FRAG_LEN, buf->mem.size) | + offset24); + } + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, offset24); +} + +/** + * irdma_puda_replenish_rq - post rcv buffers + * @rsrc: resource to use for buffer + * @initial: flag if during init time + */ +static int irdma_puda_replenish_rq(struct irdma_puda_rsrc *rsrc, bool initial) +{ + u32 i; + u32 invalid_cnt = rsrc->rxq_invalid_cnt; + struct irdma_puda_buf *buf = NULL; + + for (i = 0; i < invalid_cnt; i++) { + buf = irdma_puda_get_bufpool(rsrc); + if (!buf) + return -ENOBUFS; + irdma_puda_post_recvbuf(rsrc, rsrc->rx_wqe_idx, buf, initial); + rsrc->rx_wqe_idx = ((rsrc->rx_wqe_idx + 1) % rsrc->rq_size); + rsrc->rxq_invalid_cnt--; + } + + return 0; +} + +/** + * irdma_puda_alloc_buf - allocate mem for buffer + * @dev: iwarp device + * @len: length of buffer + */ +static struct irdma_puda_buf *irdma_puda_alloc_buf(struct irdma_sc_dev *dev, + u32 len) +{ + struct irdma_puda_buf *buf; + struct irdma_virt_mem buf_mem; + + buf_mem.size = sizeof(*buf); + buf_mem.va = kzalloc(buf_mem.size, GFP_KERNEL); + if (!buf_mem.va) + return NULL; + + buf = buf_mem.va; + buf->mem.size = len; + buf->mem.va = kzalloc(buf->mem.size, GFP_KERNEL); + if (!buf->mem.va) + goto free_virt; + buf->mem.pa = dma_map_single(dev->hw->device, buf->mem.va, + buf->mem.size, DMA_BIDIRECTIONAL); + if (dma_mapping_error(dev->hw->device, buf->mem.pa)) { + kfree(buf->mem.va); + goto free_virt; + } + + buf->buf_mem.va = buf_mem.va; + buf->buf_mem.size = buf_mem.size; + + return buf; + +free_virt: + kfree(buf_mem.va); + return NULL; +} + +/** + * irdma_puda_dele_buf - delete buffer back to system + * @dev: iwarp device + * @buf: buffer to free + */ +static void irdma_puda_dele_buf(struct irdma_sc_dev *dev, + struct irdma_puda_buf *buf) +{ + dma_unmap_single(dev->hw->device, buf->mem.pa, buf->mem.size, + DMA_BIDIRECTIONAL); + kfree(buf->mem.va); + kfree(buf->buf_mem.va); +} + +/** + * irdma_puda_get_next_send_wqe - return next wqe for processing + * @qp: puda qp for wqe + * @wqe_idx: wqe index for caller + */ +static __le64 *irdma_puda_get_next_send_wqe(struct irdma_qp_uk *qp, + u32 *wqe_idx) +{ + int ret_code = 0; + + *wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); + if (!*wqe_idx) + qp->swqe_polarity = !qp->swqe_polarity; + IRDMA_RING_MOVE_HEAD(qp->sq_ring, ret_code); + if (ret_code) + return NULL; + + return qp->sq_base[*wqe_idx].elem; +} + +/** + * irdma_puda_poll_info - poll cq for completion + * @cq: cq for poll + * @info: info return for successful completion + */ +static int irdma_puda_poll_info(struct irdma_sc_cq *cq, + struct irdma_puda_cmpl_info *info) +{ + struct irdma_cq_uk *cq_uk = &cq->cq_uk; + u64 qword0, qword2, qword3, qword6; + __le64 *cqe; + __le64 *ext_cqe = NULL; + u64 qword7 = 0; + u64 comp_ctx; + bool valid_bit; + bool ext_valid = 0; + u32 major_err, minor_err; + u32 peek_head; + bool error; + u8 polarity; + + cqe = IRDMA_GET_CURRENT_CQ_ELEM(&cq->cq_uk); + get_64bit_val(cqe, 24, &qword3); + valid_bit = (bool)FIELD_GET(IRDMA_CQ_VALID, qword3); + if (valid_bit != cq_uk->polarity) + return -ENOENT; + + /* Ensure CQE contents are read after valid bit is checked */ + dma_rmb(); + + if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) + ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); + + if (ext_valid) { + peek_head = (cq_uk->cq_ring.head + 1) % cq_uk->cq_ring.size; + ext_cqe = cq_uk->cq_base[peek_head].buf; + get_64bit_val(ext_cqe, 24, &qword7); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); + if (!peek_head) + polarity ^= 1; + if (polarity != cq_uk->polarity) + return -ENOENT; + + /* Ensure ext CQE contents are read after ext valid bit is checked */ + dma_rmb(); + + IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); + if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) + cq_uk->polarity = !cq_uk->polarity; + /* update cq tail in cq shadow memory also */ + IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); + } + + print_hex_dump_debug("PUDA: PUDA CQE", DUMP_PREFIX_OFFSET, 16, 8, cqe, + 32, false); + if (ext_valid) + print_hex_dump_debug("PUDA: PUDA EXT-CQE", DUMP_PREFIX_OFFSET, + 16, 8, ext_cqe, 32, false); + + error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); + if (error) { + ibdev_dbg(to_ibdev(cq->dev), "PUDA: receive error\n"); + major_err = (u32)(FIELD_GET(IRDMA_CQ_MAJERR, qword3)); + minor_err = (u32)(FIELD_GET(IRDMA_CQ_MINERR, qword3)); + info->compl_error = major_err << 16 | minor_err; + return -EIO; + } + + get_64bit_val(cqe, 0, &qword0); + get_64bit_val(cqe, 16, &qword2); + + info->q_type = (u8)FIELD_GET(IRDMA_CQ_SQ, qword3); + info->qp_id = (u32)FIELD_GET(IRDMACQ_QPID, qword2); + if (cq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) + info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); + + get_64bit_val(cqe, 8, &comp_ctx); + info->qp = (struct irdma_qp_uk *)(unsigned long)comp_ctx; + info->wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); + + if (info->q_type == IRDMA_CQE_QTYPE_RQ) { + if (ext_valid) { + info->vlan_valid = (bool)FIELD_GET(IRDMA_CQ_UDVLANVALID, qword7); + if (info->vlan_valid) { + get_64bit_val(ext_cqe, 16, &qword6); + info->vlan = (u16)FIELD_GET(IRDMA_CQ_UDVLAN, qword6); + } + info->smac_valid = (bool)FIELD_GET(IRDMA_CQ_UDSMACVALID, qword7); + if (info->smac_valid) { + get_64bit_val(ext_cqe, 16, &qword6); + info->smac[0] = (u8)((qword6 >> 40) & 0xFF); + info->smac[1] = (u8)((qword6 >> 32) & 0xFF); + info->smac[2] = (u8)((qword6 >> 24) & 0xFF); + info->smac[3] = (u8)((qword6 >> 16) & 0xFF); + info->smac[4] = (u8)((qword6 >> 8) & 0xFF); + info->smac[5] = (u8)(qword6 & 0xFF); + } + } + + if (cq->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) { + info->vlan_valid = (bool)FIELD_GET(IRDMA_VLAN_TAG_VALID, qword3); + info->l4proto = (u8)FIELD_GET(IRDMA_UDA_L4PROTO, qword2); + info->l3proto = (u8)FIELD_GET(IRDMA_UDA_L3PROTO, qword2); + } + + info->payload_len = (u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); + } + + return 0; +} + +/** + * irdma_puda_poll_cmpl - processes completion for cq + * @dev: iwarp device + * @cq: cq getting interrupt + * @compl_err: return any completion err + */ +int irdma_puda_poll_cmpl(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq, + u32 *compl_err) +{ + struct irdma_qp_uk *qp; + struct irdma_cq_uk *cq_uk = &cq->cq_uk; + struct irdma_puda_cmpl_info info = {}; + int ret = 0; + struct irdma_puda_buf *buf; + struct irdma_puda_rsrc *rsrc; + u8 cq_type = cq->cq_type; + unsigned long flags; + + if (cq_type == IRDMA_CQ_TYPE_ILQ || cq_type == IRDMA_CQ_TYPE_IEQ) { + rsrc = (cq_type == IRDMA_CQ_TYPE_ILQ) ? cq->vsi->ilq : + cq->vsi->ieq; + } else { + ibdev_dbg(to_ibdev(dev), "PUDA: qp_type error\n"); + return -EFAULT; + } + + ret = irdma_puda_poll_info(cq, &info); + *compl_err = info.compl_error; + if (ret == -ENOENT) + return ret; + if (ret) + goto done; + + qp = info.qp; + if (!qp || !rsrc) { + ret = -EFAULT; + goto done; + } + + if (qp->qp_id != rsrc->qp_id) { + ret = -EFAULT; + goto done; + } + + if (info.q_type == IRDMA_CQE_QTYPE_RQ) { + buf = (struct irdma_puda_buf *)(uintptr_t) + qp->rq_wrid_array[info.wqe_idx]; + + /* reusing so synch the buffer for CPU use */ + dma_sync_single_for_cpu(dev->hw->device, buf->mem.pa, + buf->mem.size, DMA_BIDIRECTIONAL); + /* Get all the tcpip information in the buf header */ + ret = irdma_puda_get_tcpip_info(&info, buf); + if (ret) { + rsrc->stats_rcvd_pkt_err++; + if (cq_type == IRDMA_CQ_TYPE_ILQ) { + irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, + info.wqe_idx); + } else { + irdma_puda_ret_bufpool(rsrc, buf); + irdma_puda_replenish_rq(rsrc, false); + } + goto done; + } + + rsrc->stats_pkt_rcvd++; + rsrc->compl_rxwqe_idx = info.wqe_idx; + ibdev_dbg(to_ibdev(dev), "PUDA: RQ completion\n"); + rsrc->receive(rsrc->vsi, buf); + if (cq_type == IRDMA_CQ_TYPE_ILQ) + irdma_ilq_putback_rcvbuf(&rsrc->qp, buf, info.wqe_idx); + else + irdma_puda_replenish_rq(rsrc, false); + + } else { + ibdev_dbg(to_ibdev(dev), "PUDA: SQ completion\n"); + buf = (struct irdma_puda_buf *)(uintptr_t) + qp->sq_wrtrk_array[info.wqe_idx].wrid; + + /* reusing so synch the buffer for CPU use */ + dma_sync_single_for_cpu(dev->hw->device, buf->mem.pa, + buf->mem.size, DMA_BIDIRECTIONAL); + IRDMA_RING_SET_TAIL(qp->sq_ring, info.wqe_idx); + rsrc->xmit_complete(rsrc->vsi, buf); + spin_lock_irqsave(&rsrc->bufpool_lock, flags); + rsrc->tx_wqe_avail_cnt++; + spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); + if (!list_empty(&rsrc->txpend)) + irdma_puda_send_buf(rsrc, NULL); + } + +done: + IRDMA_RING_MOVE_HEAD_NOCHECK(cq_uk->cq_ring); + if (!IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)) + cq_uk->polarity = !cq_uk->polarity; + /* update cq tail in cq shadow memory also */ + IRDMA_RING_MOVE_TAIL(cq_uk->cq_ring); + set_64bit_val(cq_uk->shadow_area, 0, + IRDMA_RING_CURRENT_HEAD(cq_uk->cq_ring)); + + return ret; +} + +/** + * irdma_puda_send - complete send wqe for transmit + * @qp: puda qp for send + * @info: buffer information for transmit + */ +int irdma_puda_send(struct irdma_sc_qp *qp, struct irdma_puda_send_info *info) +{ + __le64 *wqe; + u32 iplen, l4len; + u64 hdr[2]; + u32 wqe_idx; + u8 iipt; + + /* number of 32 bits DWORDS in header */ + l4len = info->tcplen >> 2; + if (info->ipv4) { + iipt = 3; + iplen = 5; + } else { + iipt = 1; + iplen = 10; + } + + wqe = irdma_puda_get_next_send_wqe(&qp->qp_uk, &wqe_idx); + if (!wqe) + return -ENOMEM; + + qp->qp_uk.sq_wrtrk_array[wqe_idx].wrid = (uintptr_t)info->scratch; + /* Third line of WQE descriptor */ + /* maclen is in words */ + + if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + hdr[0] = 0; /* Dest_QPN and Dest_QKey only for UD */ + hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | + FIELD_PREP(IRDMA_UDA_QPSQ_L4LEN, l4len) | + FIELD_PREP(IRDMAQPSQ_AHID, info->ah_id) | + FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | + FIELD_PREP(IRDMA_UDA_QPSQ_VALID, + qp->qp_uk.swqe_polarity); + + /* Forth line of WQE descriptor */ + + set_64bit_val(wqe, 0, info->paddr); + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_FRAG_LEN, info->len) | + FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity)); + } else { + hdr[0] = FIELD_PREP(IRDMA_UDA_QPSQ_MACLEN, info->maclen >> 1) | + FIELD_PREP(IRDMA_UDA_QPSQ_IPLEN, iplen) | + FIELD_PREP(IRDMA_UDA_QPSQ_L4T, 1) | + FIELD_PREP(IRDMA_UDA_QPSQ_IIPT, iipt) | + FIELD_PREP(IRDMA_GEN1_UDA_QPSQ_L4LEN, l4len); + + hdr[1] = FIELD_PREP(IRDMA_UDA_QPSQ_OPCODE, IRDMA_OP_TYPE_SEND) | + FIELD_PREP(IRDMA_UDA_QPSQ_SIGCOMPL, 1) | + FIELD_PREP(IRDMA_UDA_QPSQ_DOLOOPBACK, info->do_lpb) | + FIELD_PREP(IRDMA_UDA_QPSQ_VALID, qp->qp_uk.swqe_polarity); + + /* Forth line of WQE descriptor */ + + set_64bit_val(wqe, 0, info->paddr); + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, info->len)); + } + + set_64bit_val(wqe, 16, hdr[0]); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr[1]); + + print_hex_dump_debug("PUDA: PUDA SEND WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, 32, false); + irdma_uk_qp_post_wr(&qp->qp_uk); + return 0; +} + +/** + * irdma_puda_send_buf - transmit puda buffer + * @rsrc: resource to use for buffer + * @buf: puda buffer to transmit + */ +void irdma_puda_send_buf(struct irdma_puda_rsrc *rsrc, + struct irdma_puda_buf *buf) +{ + struct irdma_puda_send_info info; + int ret = 0; + unsigned long flags; + + spin_lock_irqsave(&rsrc->bufpool_lock, flags); + /* if no wqe available or not from a completion and we have + * pending buffers, we must queue new buffer + */ + if (!rsrc->tx_wqe_avail_cnt || (buf && !list_empty(&rsrc->txpend))) { + list_add_tail(&buf->list, &rsrc->txpend); + spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); + rsrc->stats_sent_pkt_q++; + if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) + ibdev_dbg(to_ibdev(rsrc->dev), + "PUDA: adding to txpend\n"); + return; + } + rsrc->tx_wqe_avail_cnt--; + /* if we are coming from a completion and have pending buffers + * then Get one from pending list + */ + if (!buf) { + buf = irdma_puda_get_listbuf(&rsrc->txpend); + if (!buf) + goto done; + } + + info.scratch = buf; + info.paddr = buf->mem.pa; + info.len = buf->totallen; + info.tcplen = buf->tcphlen; + info.ipv4 = buf->ipv4; + + if (rsrc->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + info.ah_id = buf->ah_id; + } else { + info.maclen = buf->maclen; + info.do_lpb = buf->do_lpb; + } + + /* Synch buffer for use by device */ + dma_sync_single_for_cpu(rsrc->dev->hw->device, buf->mem.pa, + buf->mem.size, DMA_BIDIRECTIONAL); + ret = irdma_puda_send(&rsrc->qp, &info); + if (ret) { + rsrc->tx_wqe_avail_cnt++; + rsrc->stats_sent_pkt_q++; + list_add(&buf->list, &rsrc->txpend); + if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) + ibdev_dbg(to_ibdev(rsrc->dev), + "PUDA: adding to puda_send\n"); + } else { + rsrc->stats_pkt_sent++; + } +done: + spin_unlock_irqrestore(&rsrc->bufpool_lock, flags); +} + +/** + * irdma_puda_qp_setctx - during init, set qp's context + * @rsrc: qp's resource + */ +static void irdma_puda_qp_setctx(struct irdma_puda_rsrc *rsrc) +{ + struct irdma_sc_qp *qp = &rsrc->qp; + __le64 *qp_ctx = qp->hw_host_ctx; + + set_64bit_val(qp_ctx, 8, qp->sq_pa); + set_64bit_val(qp_ctx, 16, qp->rq_pa); + set_64bit_val(qp_ctx, 24, + FIELD_PREP(IRDMAQPC_RQSIZE, qp->hw_rq_size) | + FIELD_PREP(IRDMAQPC_SQSIZE, qp->hw_sq_size)); + set_64bit_val(qp_ctx, 48, + FIELD_PREP(IRDMAQPC_SNDMSS, rsrc->buf_size)); + set_64bit_val(qp_ctx, 56, 0); + if (qp->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + set_64bit_val(qp_ctx, 64, 1); + set_64bit_val(qp_ctx, 136, + FIELD_PREP(IRDMAQPC_TXCQNUM, rsrc->cq_id) | + FIELD_PREP(IRDMAQPC_RXCQNUM, rsrc->cq_id)); + set_64bit_val(qp_ctx, 144, + FIELD_PREP(IRDMAQPC_STAT_INDEX, rsrc->stats_idx)); + set_64bit_val(qp_ctx, 160, + FIELD_PREP(IRDMAQPC_PRIVEN, 1) | + FIELD_PREP(IRDMAQPC_USESTATSINSTANCE, rsrc->stats_idx_valid)); + set_64bit_val(qp_ctx, 168, + FIELD_PREP(IRDMAQPC_QPCOMPCTX, (uintptr_t)qp)); + set_64bit_val(qp_ctx, 176, + FIELD_PREP(IRDMAQPC_SQTPHVAL, qp->sq_tph_val) | + FIELD_PREP(IRDMAQPC_RQTPHVAL, qp->rq_tph_val) | + FIELD_PREP(IRDMAQPC_QSHANDLE, qp->qs_handle)); + + print_hex_dump_debug("PUDA: PUDA QP CONTEXT", DUMP_PREFIX_OFFSET, 16, + 8, qp_ctx, IRDMA_QP_CTX_SIZE, false); +} + +/** + * irdma_puda_qp_wqe - setup wqe for qp create + * @dev: Device + * @qp: Resource qp + */ +static int irdma_puda_qp_wqe(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp) +{ + struct irdma_sc_cqp *cqp; + __le64 *wqe; + u64 hdr; + struct irdma_ccq_cqe_info compl_info; + int status = 0; + + cqp = dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, qp->hw_host_ctx_pa); + set_64bit_val(wqe, 40, qp->shadow_area_pa); + + hdr = qp->qp_uk.qp_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_QP) | + FIELD_PREP(IRDMA_CQPSQ_QP_QPTYPE, IRDMA_QP_TYPE_UDA) | + FIELD_PREP(IRDMA_CQPSQ_QP_CQNUMVALID, 1) | + FIELD_PREP(IRDMA_CQPSQ_QP_NEXTIWSTATE, 2) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("PUDA: PUDA QP CREATE", DUMP_PREFIX_OFFSET, 16, + 8, wqe, 40, false); + irdma_sc_cqp_post_sq(cqp); + status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_QP, + &compl_info); + + return status; +} + +/** + * irdma_puda_qp_create - create qp for resource + * @rsrc: resource to use for buffer + */ +static int irdma_puda_qp_create(struct irdma_puda_rsrc *rsrc) +{ + struct irdma_sc_qp *qp = &rsrc->qp; + struct irdma_qp_uk *ukqp = &qp->qp_uk; + int ret = 0; + u32 sq_size, rq_size; + struct irdma_dma_mem *mem; + + sq_size = rsrc->sq_size * IRDMA_QP_WQE_MIN_SIZE; + rq_size = rsrc->rq_size * IRDMA_QP_WQE_MIN_SIZE; + rsrc->qpmem.size = ALIGN((sq_size + rq_size + (IRDMA_SHADOW_AREA_SIZE << 3) + IRDMA_QP_CTX_SIZE), + IRDMA_HW_PAGE_SIZE); + rsrc->qpmem.va = dma_alloc_coherent(rsrc->dev->hw->device, + rsrc->qpmem.size, &rsrc->qpmem.pa, + GFP_KERNEL); + if (!rsrc->qpmem.va) + return -ENOMEM; + + mem = &rsrc->qpmem; + memset(mem->va, 0, rsrc->qpmem.size); + qp->hw_sq_size = irdma_get_encoded_wqe_size(rsrc->sq_size, IRDMA_QUEUE_TYPE_SQ_RQ); + qp->hw_rq_size = irdma_get_encoded_wqe_size(rsrc->rq_size, IRDMA_QUEUE_TYPE_SQ_RQ); + qp->pd = &rsrc->sc_pd; + qp->qp_uk.qp_type = IRDMA_QP_TYPE_UDA; + qp->dev = rsrc->dev; + qp->qp_uk.back_qp = rsrc; + qp->sq_pa = mem->pa; + qp->rq_pa = qp->sq_pa + sq_size; + qp->vsi = rsrc->vsi; + ukqp->sq_base = mem->va; + ukqp->rq_base = &ukqp->sq_base[rsrc->sq_size]; + ukqp->shadow_area = ukqp->rq_base[rsrc->rq_size].elem; + ukqp->uk_attrs = &qp->dev->hw_attrs.uk_attrs; + qp->shadow_area_pa = qp->rq_pa + rq_size; + qp->hw_host_ctx = ukqp->shadow_area + IRDMA_SHADOW_AREA_SIZE; + qp->hw_host_ctx_pa = qp->shadow_area_pa + (IRDMA_SHADOW_AREA_SIZE << 3); + qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + ukqp->qp_id = rsrc->qp_id; + ukqp->sq_wrtrk_array = rsrc->sq_wrtrk_array; + ukqp->rq_wrid_array = rsrc->rq_wrid_array; + ukqp->sq_size = rsrc->sq_size; + ukqp->rq_size = rsrc->rq_size; + + IRDMA_RING_INIT(ukqp->sq_ring, ukqp->sq_size); + IRDMA_RING_INIT(ukqp->initial_ring, ukqp->sq_size); + IRDMA_RING_INIT(ukqp->rq_ring, ukqp->rq_size); + ukqp->wqe_alloc_db = qp->pd->dev->wqe_alloc_db; + + ret = rsrc->dev->ws_add(qp->vsi, qp->user_pri); + if (ret) { + dma_free_coherent(rsrc->dev->hw->device, rsrc->qpmem.size, + rsrc->qpmem.va, rsrc->qpmem.pa); + rsrc->qpmem.va = NULL; + return ret; + } + + irdma_qp_add_qos(qp); + irdma_puda_qp_setctx(rsrc); + + if (rsrc->dev->ceq_valid) + ret = irdma_cqp_qp_create_cmd(rsrc->dev, qp); + else + ret = irdma_puda_qp_wqe(rsrc->dev, qp); + if (ret) { + irdma_qp_rem_qos(qp); + rsrc->dev->ws_remove(qp->vsi, qp->user_pri); + dma_free_coherent(rsrc->dev->hw->device, rsrc->qpmem.size, + rsrc->qpmem.va, rsrc->qpmem.pa); + rsrc->qpmem.va = NULL; + } + + return ret; +} + +/** + * irdma_puda_cq_wqe - setup wqe for CQ create + * @dev: Device + * @cq: resource for cq + */ +static int irdma_puda_cq_wqe(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq) +{ + __le64 *wqe; + struct irdma_sc_cqp *cqp; + u64 hdr; + struct irdma_ccq_cqe_info compl_info; + int status = 0; + + cqp = dev->cqp; + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, 0); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, cq->cq_uk.cq_size); + set_64bit_val(wqe, 8, RS_64_1(cq, 1)); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_CQPSQ_CQ_SHADOW_READ_THRESHOLD, cq->shadow_read_threshold)); + set_64bit_val(wqe, 32, cq->cq_pa); + set_64bit_val(wqe, 40, cq->shadow_area_pa); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_CQPSQ_TPHVAL, cq->tph_val) | + FIELD_PREP(IRDMA_CQPSQ_VSIIDX, cq->vsi->vsi_idx)); + + hdr = cq->cq_uk.cq_id | + FIELD_PREP(IRDMA_CQPSQ_OPCODE, IRDMA_CQP_OP_CREATE_CQ) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CHKOVERFLOW, 1) | + FIELD_PREP(IRDMA_CQPSQ_CQ_ENCEQEMASK, 1) | + FIELD_PREP(IRDMA_CQPSQ_CQ_CEQIDVALID, 1) | + FIELD_PREP(IRDMA_CQPSQ_WQEVALID, cqp->polarity); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + print_hex_dump_debug("PUDA: PUDA CREATE CQ", DUMP_PREFIX_OFFSET, 16, + 8, wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_sc_cqp_post_sq(dev->cqp); + status = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_CREATE_CQ, + &compl_info); + return status; +} + +/** + * irdma_puda_cq_create - create cq for resource + * @rsrc: resource for which cq to create + */ +static int irdma_puda_cq_create(struct irdma_puda_rsrc *rsrc) +{ + struct irdma_sc_dev *dev = rsrc->dev; + struct irdma_sc_cq *cq = &rsrc->cq; + int ret = 0; + u32 cqsize; + struct irdma_dma_mem *mem; + struct irdma_cq_init_info info = {}; + struct irdma_cq_uk_init_info *init_info = &info.cq_uk_init_info; + + cq->vsi = rsrc->vsi; + cqsize = rsrc->cq_size * (sizeof(struct irdma_cqe)); + rsrc->cqmem.size = ALIGN(cqsize + sizeof(struct irdma_cq_shadow_area), + IRDMA_CQ0_ALIGNMENT); + rsrc->cqmem.va = dma_alloc_coherent(dev->hw->device, rsrc->cqmem.size, + &rsrc->cqmem.pa, GFP_KERNEL); + if (!rsrc->cqmem.va) + return -ENOMEM; + + mem = &rsrc->cqmem; + info.dev = dev; + info.type = (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) ? + IRDMA_CQ_TYPE_ILQ : IRDMA_CQ_TYPE_IEQ; + info.shadow_read_threshold = rsrc->cq_size >> 2; + info.cq_base_pa = mem->pa; + info.shadow_area_pa = mem->pa + cqsize; + init_info->cq_base = mem->va; + init_info->shadow_area = (__le64 *)((u8 *)mem->va + cqsize); + init_info->cq_size = rsrc->cq_size; + init_info->cq_id = rsrc->cq_id; + info.ceqe_mask = true; + info.ceq_id_valid = true; + info.vsi = rsrc->vsi; + + ret = irdma_sc_cq_init(cq, &info); + if (ret) + goto error; + + if (rsrc->dev->ceq_valid) + ret = irdma_cqp_cq_create_cmd(dev, cq); + else + ret = irdma_puda_cq_wqe(dev, cq); +error: + if (ret) { + dma_free_coherent(dev->hw->device, rsrc->cqmem.size, + rsrc->cqmem.va, rsrc->cqmem.pa); + rsrc->cqmem.va = NULL; + } + + return ret; +} + +/** + * irdma_puda_free_qp - free qp for resource + * @rsrc: resource for which qp to free + */ +static void irdma_puda_free_qp(struct irdma_puda_rsrc *rsrc) +{ + int ret; + struct irdma_ccq_cqe_info compl_info; + struct irdma_sc_dev *dev = rsrc->dev; + + if (rsrc->dev->ceq_valid) { + irdma_cqp_qp_destroy_cmd(dev, &rsrc->qp); + rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); + return; + } + + ret = irdma_sc_qp_destroy(&rsrc->qp, 0, false, true, true); + if (ret) + ibdev_dbg(to_ibdev(dev), + "PUDA: error puda qp destroy wqe, status = %d\n", + ret); + if (!ret) { + ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_QP, + &compl_info); + if (ret) + ibdev_dbg(to_ibdev(dev), + "PUDA: error puda qp destroy failed, status = %d\n", + ret); + } + rsrc->dev->ws_remove(rsrc->qp.vsi, rsrc->qp.user_pri); +} + +/** + * irdma_puda_free_cq - free cq for resource + * @rsrc: resource for which cq to free + */ +static void irdma_puda_free_cq(struct irdma_puda_rsrc *rsrc) +{ + int ret; + struct irdma_ccq_cqe_info compl_info; + struct irdma_sc_dev *dev = rsrc->dev; + + if (rsrc->dev->ceq_valid) { + irdma_cqp_cq_destroy_cmd(dev, &rsrc->cq); + return; + } + + ret = irdma_sc_cq_destroy(&rsrc->cq, 0, true); + if (ret) + ibdev_dbg(to_ibdev(dev), "PUDA: error ieq cq destroy\n"); + if (!ret) { + ret = irdma_sc_poll_for_cqp_op_done(dev->cqp, IRDMA_CQP_OP_DESTROY_CQ, + &compl_info); + if (ret) + ibdev_dbg(to_ibdev(dev), + "PUDA: error ieq qp destroy done\n"); + } +} + +/** + * irdma_puda_dele_rsrc - delete all resources during close + * @vsi: VSI structure of device + * @type: type of resource to dele + * @reset: true if reset chip + */ +void irdma_puda_dele_rsrc(struct irdma_sc_vsi *vsi, enum puda_rsrc_type type, + bool reset) +{ + struct irdma_sc_dev *dev = vsi->dev; + struct irdma_puda_rsrc *rsrc; + struct irdma_puda_buf *buf = NULL; + struct irdma_puda_buf *nextbuf = NULL; + struct irdma_virt_mem *vmem; + + switch (type) { + case IRDMA_PUDA_RSRC_TYPE_ILQ: + rsrc = vsi->ilq; + vmem = &vsi->ilq_mem; + vsi->ilq = NULL; + break; + case IRDMA_PUDA_RSRC_TYPE_IEQ: + rsrc = vsi->ieq; + vmem = &vsi->ieq_mem; + vsi->ieq = NULL; + break; + default: + ibdev_dbg(to_ibdev(dev), "PUDA: error resource type = 0x%x\n", + type); + return; + } + + switch (rsrc->cmpl) { + case PUDA_HASH_CRC_COMPLETE: + irdma_free_hash_desc(rsrc->hash_desc); + fallthrough; + case PUDA_QP_CREATED: + irdma_qp_rem_qos(&rsrc->qp); + + if (!reset) + irdma_puda_free_qp(rsrc); + + dma_free_coherent(dev->hw->device, rsrc->qpmem.size, + rsrc->qpmem.va, rsrc->qpmem.pa); + rsrc->qpmem.va = NULL; + fallthrough; + case PUDA_CQ_CREATED: + if (!reset) + irdma_puda_free_cq(rsrc); + + dma_free_coherent(dev->hw->device, rsrc->cqmem.size, + rsrc->cqmem.va, rsrc->cqmem.pa); + rsrc->cqmem.va = NULL; + break; + default: + ibdev_dbg(to_ibdev(rsrc->dev), "PUDA: error no resources\n"); + break; + } + /* Free all allocated puda buffers for both tx and rx */ + buf = rsrc->alloclist; + while (buf) { + nextbuf = buf->next; + irdma_puda_dele_buf(dev, buf); + buf = nextbuf; + rsrc->alloc_buf_count--; + } + + kfree(vmem->va); +} + +/** + * irdma_puda_allocbufs - allocate buffers for resource + * @rsrc: resource for buffer allocation + * @count: number of buffers to create + */ +static int irdma_puda_allocbufs(struct irdma_puda_rsrc *rsrc, u32 count) +{ + u32 i; + struct irdma_puda_buf *buf; + struct irdma_puda_buf *nextbuf; + + for (i = 0; i < count; i++) { + buf = irdma_puda_alloc_buf(rsrc->dev, rsrc->buf_size); + if (!buf) { + rsrc->stats_buf_alloc_fail++; + return -ENOMEM; + } + irdma_puda_ret_bufpool(rsrc, buf); + rsrc->alloc_buf_count++; + if (!rsrc->alloclist) { + rsrc->alloclist = buf; + } else { + nextbuf = rsrc->alloclist; + rsrc->alloclist = buf; + buf->next = nextbuf; + } + } + + rsrc->avail_buf_count = rsrc->alloc_buf_count; + + return 0; +} + +/** + * irdma_puda_create_rsrc - create resource (ilq or ieq) + * @vsi: sc VSI struct + * @info: resource information + */ +int irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi, + struct irdma_puda_rsrc_info *info) +{ + struct irdma_sc_dev *dev = vsi->dev; + int ret = 0; + struct irdma_puda_rsrc *rsrc; + u32 pudasize; + u32 sqwridsize, rqwridsize; + struct irdma_virt_mem *vmem; + + info->count = 1; + pudasize = sizeof(*rsrc); + sqwridsize = info->sq_size * sizeof(struct irdma_sq_uk_wr_trk_info); + rqwridsize = info->rq_size * 8; + switch (info->type) { + case IRDMA_PUDA_RSRC_TYPE_ILQ: + vmem = &vsi->ilq_mem; + break; + case IRDMA_PUDA_RSRC_TYPE_IEQ: + vmem = &vsi->ieq_mem; + break; + default: + return -EOPNOTSUPP; + } + vmem->size = pudasize + sqwridsize + rqwridsize; + vmem->va = kzalloc(vmem->size, GFP_KERNEL); + if (!vmem->va) + return -ENOMEM; + + rsrc = vmem->va; + spin_lock_init(&rsrc->bufpool_lock); + switch (info->type) { + case IRDMA_PUDA_RSRC_TYPE_ILQ: + vsi->ilq = vmem->va; + vsi->ilq_count = info->count; + rsrc->receive = info->receive; + rsrc->xmit_complete = info->xmit_complete; + break; + case IRDMA_PUDA_RSRC_TYPE_IEQ: + vsi->ieq_count = info->count; + vsi->ieq = vmem->va; + rsrc->receive = irdma_ieq_receive; + rsrc->xmit_complete = irdma_ieq_tx_compl; + break; + default: + return -EOPNOTSUPP; + } + + rsrc->type = info->type; + rsrc->sq_wrtrk_array = (struct irdma_sq_uk_wr_trk_info *) + ((u8 *)vmem->va + pudasize); + rsrc->rq_wrid_array = (u64 *)((u8 *)vmem->va + pudasize + sqwridsize); + /* Initialize all ieq lists */ + INIT_LIST_HEAD(&rsrc->bufpool); + INIT_LIST_HEAD(&rsrc->txpend); + + rsrc->tx_wqe_avail_cnt = info->sq_size - 1; + irdma_sc_pd_init(dev, &rsrc->sc_pd, info->pd_id, info->abi_ver); + rsrc->qp_id = info->qp_id; + rsrc->cq_id = info->cq_id; + rsrc->sq_size = info->sq_size; + rsrc->rq_size = info->rq_size; + rsrc->cq_size = info->rq_size + info->sq_size; + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + if (rsrc->type == IRDMA_PUDA_RSRC_TYPE_ILQ) + rsrc->cq_size += info->rq_size; + } + rsrc->buf_size = info->buf_size; + rsrc->dev = dev; + rsrc->vsi = vsi; + rsrc->stats_idx = info->stats_idx; + rsrc->stats_idx_valid = info->stats_idx_valid; + + ret = irdma_puda_cq_create(rsrc); + if (!ret) { + rsrc->cmpl = PUDA_CQ_CREATED; + ret = irdma_puda_qp_create(rsrc); + } + if (ret) { + ibdev_dbg(to_ibdev(dev), + "PUDA: error qp_create type=%d, status=%d\n", + rsrc->type, ret); + goto error; + } + rsrc->cmpl = PUDA_QP_CREATED; + + ret = irdma_puda_allocbufs(rsrc, info->tx_buf_cnt + info->rq_size); + if (ret) { + ibdev_dbg(to_ibdev(dev), "PUDA: error alloc_buf\n"); + goto error; + } + + rsrc->rxq_invalid_cnt = info->rq_size; + ret = irdma_puda_replenish_rq(rsrc, true); + if (ret) + goto error; + + if (info->type == IRDMA_PUDA_RSRC_TYPE_IEQ) { + if (!irdma_init_hash_desc(&rsrc->hash_desc)) { + rsrc->check_crc = true; + rsrc->cmpl = PUDA_HASH_CRC_COMPLETE; + ret = 0; + } + } + + irdma_sc_ccq_arm(&rsrc->cq); + return ret; + +error: + irdma_puda_dele_rsrc(vsi, info->type, false); + + return ret; +} + +/** + * irdma_ilq_putback_rcvbuf - ilq buffer to put back on rq + * @qp: ilq's qp resource + * @buf: puda buffer for rcv q + * @wqe_idx: wqe index of completed rcvbuf + */ +static void irdma_ilq_putback_rcvbuf(struct irdma_sc_qp *qp, + struct irdma_puda_buf *buf, u32 wqe_idx) +{ + __le64 *wqe; + u64 offset8, offset24; + + /* Synch buffer for use by device */ + dma_sync_single_for_device(qp->dev->hw->device, buf->mem.pa, + buf->mem.size, DMA_BIDIRECTIONAL); + wqe = qp->qp_uk.rq_base[wqe_idx].elem; + get_64bit_val(wqe, 24, &offset24); + if (qp->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + get_64bit_val(wqe, 8, &offset8); + if (offset24) + offset8 &= ~FIELD_PREP(IRDMAQPSQ_VALID, 1); + else + offset8 |= FIELD_PREP(IRDMAQPSQ_VALID, 1); + set_64bit_val(wqe, 8, offset8); + dma_wmb(); /* make sure WQE is written before valid bit is set */ + } + if (offset24) + offset24 = 0; + else + offset24 = FIELD_PREP(IRDMAQPSQ_VALID, 1); + + set_64bit_val(wqe, 24, offset24); +} + +/** + * irdma_ieq_get_fpdu_len - get length of fpdu with or without marker + * @pfpdu: pointer to fpdu + * @datap: pointer to data in the buffer + * @rcv_seq: seqnum of the data buffer + */ +static u16 irdma_ieq_get_fpdu_len(struct irdma_pfpdu *pfpdu, u8 *datap, + u32 rcv_seq) +{ + u32 marker_seq, end_seq, blk_start; + u8 marker_len = pfpdu->marker_len; + u16 total_len = 0; + u16 fpdu_len; + + blk_start = (pfpdu->rcv_start_seq - rcv_seq) & (IRDMA_MRK_BLK_SZ - 1); + if (!blk_start) { + total_len = marker_len; + marker_seq = rcv_seq + IRDMA_MRK_BLK_SZ; + if (marker_len && *(u32 *)datap) + return 0; + } else { + marker_seq = rcv_seq + blk_start; + } + + datap += total_len; + fpdu_len = ntohs(*(__be16 *)datap); + fpdu_len += IRDMA_IEQ_MPA_FRAMING; + fpdu_len = (fpdu_len + 3) & 0xfffc; + + if (fpdu_len > pfpdu->max_fpdu_data) + return 0; + + total_len += fpdu_len; + end_seq = rcv_seq + total_len; + while ((int)(marker_seq - end_seq) < 0) { + total_len += marker_len; + end_seq += marker_len; + marker_seq += IRDMA_MRK_BLK_SZ; + } + + return total_len; +} + +/** + * irdma_ieq_copy_to_txbuf - copydata from rcv buf to tx buf + * @buf: rcv buffer with partial + * @txbuf: tx buffer for sending back + * @buf_offset: rcv buffer offset to copy from + * @txbuf_offset: at offset in tx buf to copy + * @len: length of data to copy + */ +static void irdma_ieq_copy_to_txbuf(struct irdma_puda_buf *buf, + struct irdma_puda_buf *txbuf, + u16 buf_offset, u32 txbuf_offset, u32 len) +{ + void *mem1 = (u8 *)buf->mem.va + buf_offset; + void *mem2 = (u8 *)txbuf->mem.va + txbuf_offset; + + memcpy(mem2, mem1, len); +} + +/** + * irdma_ieq_setup_tx_buf - setup tx buffer for partial handling + * @buf: reeive buffer with partial + * @txbuf: buffer to prepare + */ +static void irdma_ieq_setup_tx_buf(struct irdma_puda_buf *buf, + struct irdma_puda_buf *txbuf) +{ + txbuf->tcphlen = buf->tcphlen; + txbuf->ipv4 = buf->ipv4; + + if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + txbuf->hdrlen = txbuf->tcphlen; + irdma_ieq_copy_to_txbuf(buf, txbuf, IRDMA_TCP_OFFSET, 0, + txbuf->hdrlen); + } else { + txbuf->maclen = buf->maclen; + txbuf->hdrlen = buf->hdrlen; + irdma_ieq_copy_to_txbuf(buf, txbuf, 0, 0, buf->hdrlen); + } +} + +/** + * irdma_ieq_check_first_buf - check if rcv buffer's seq is in range + * @buf: receive exception buffer + * @fps: first partial sequence number + */ +static void irdma_ieq_check_first_buf(struct irdma_puda_buf *buf, u32 fps) +{ + u32 offset; + + if (buf->seqnum < fps) { + offset = fps - buf->seqnum; + if (offset > buf->datalen) + return; + buf->data += offset; + buf->datalen -= (u16)offset; + buf->seqnum = fps; + } +} + +/** + * irdma_ieq_compl_pfpdu - write txbuf with full fpdu + * @ieq: ieq resource + * @rxlist: ieq's received buffer list + * @pbufl: temporary list for buffers for fpddu + * @txbuf: tx buffer for fpdu + * @fpdu_len: total length of fpdu + */ +static void irdma_ieq_compl_pfpdu(struct irdma_puda_rsrc *ieq, + struct list_head *rxlist, + struct list_head *pbufl, + struct irdma_puda_buf *txbuf, u16 fpdu_len) +{ + struct irdma_puda_buf *buf; + u32 nextseqnum; + u16 txoffset, bufoffset; + + buf = irdma_puda_get_listbuf(pbufl); + if (!buf) + return; + + nextseqnum = buf->seqnum + fpdu_len; + irdma_ieq_setup_tx_buf(buf, txbuf); + if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + txoffset = txbuf->hdrlen; + txbuf->totallen = txbuf->hdrlen + fpdu_len; + txbuf->data = (u8 *)txbuf->mem.va + txoffset; + } else { + txoffset = buf->hdrlen; + txbuf->totallen = buf->hdrlen + fpdu_len; + txbuf->data = (u8 *)txbuf->mem.va + buf->hdrlen; + } + bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); + + do { + if (buf->datalen >= fpdu_len) { + /* copied full fpdu */ + irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, + fpdu_len); + buf->datalen -= fpdu_len; + buf->data += fpdu_len; + buf->seqnum = nextseqnum; + break; + } + /* copy partial fpdu */ + irdma_ieq_copy_to_txbuf(buf, txbuf, bufoffset, txoffset, + buf->datalen); + txoffset += buf->datalen; + fpdu_len -= buf->datalen; + irdma_puda_ret_bufpool(ieq, buf); + buf = irdma_puda_get_listbuf(pbufl); + if (!buf) + return; + + bufoffset = (u16)(buf->data - (u8 *)buf->mem.va); + } while (1); + + /* last buffer on the list*/ + if (buf->datalen) + list_add(&buf->list, rxlist); + else + irdma_puda_ret_bufpool(ieq, buf); +} + +/** + * irdma_ieq_create_pbufl - create buffer list for single fpdu + * @pfpdu: pointer to fpdu + * @rxlist: resource list for receive ieq buffes + * @pbufl: temp. list for buffers for fpddu + * @buf: first receive buffer + * @fpdu_len: total length of fpdu + */ +static int irdma_ieq_create_pbufl(struct irdma_pfpdu *pfpdu, + struct list_head *rxlist, + struct list_head *pbufl, + struct irdma_puda_buf *buf, u16 fpdu_len) +{ + int status = 0; + struct irdma_puda_buf *nextbuf; + u32 nextseqnum; + u16 plen = fpdu_len - buf->datalen; + bool done = false; + + nextseqnum = buf->seqnum + buf->datalen; + do { + nextbuf = irdma_puda_get_listbuf(rxlist); + if (!nextbuf) { + status = -ENOBUFS; + break; + } + list_add_tail(&nextbuf->list, pbufl); + if (nextbuf->seqnum != nextseqnum) { + pfpdu->bad_seq_num++; + status = -ERANGE; + break; + } + if (nextbuf->datalen >= plen) { + done = true; + } else { + plen -= nextbuf->datalen; + nextseqnum = nextbuf->seqnum + nextbuf->datalen; + } + + } while (!done); + + return status; +} + +/** + * irdma_ieq_handle_partial - process partial fpdu buffer + * @ieq: ieq resource + * @pfpdu: partial management per user qp + * @buf: receive buffer + * @fpdu_len: fpdu len in the buffer + */ +static int irdma_ieq_handle_partial(struct irdma_puda_rsrc *ieq, + struct irdma_pfpdu *pfpdu, + struct irdma_puda_buf *buf, u16 fpdu_len) +{ + int status = 0; + u8 *crcptr; + u32 mpacrc; + u32 seqnum = buf->seqnum; + struct list_head pbufl; /* partial buffer list */ + struct irdma_puda_buf *txbuf = NULL; + struct list_head *rxlist = &pfpdu->rxlist; + + ieq->partials_handled++; + + INIT_LIST_HEAD(&pbufl); + list_add(&buf->list, &pbufl); + + status = irdma_ieq_create_pbufl(pfpdu, rxlist, &pbufl, buf, fpdu_len); + if (status) + goto error; + + txbuf = irdma_puda_get_bufpool(ieq); + if (!txbuf) { + pfpdu->no_tx_bufs++; + status = -ENOBUFS; + goto error; + } + + irdma_ieq_compl_pfpdu(ieq, rxlist, &pbufl, txbuf, fpdu_len); + irdma_ieq_update_tcpip_info(txbuf, fpdu_len, seqnum); + + crcptr = txbuf->data + fpdu_len - 4; + mpacrc = *(u32 *)crcptr; + if (ieq->check_crc) { + status = irdma_ieq_check_mpacrc(ieq->hash_desc, txbuf->data, + (fpdu_len - 4), mpacrc); + if (status) { + ibdev_dbg(to_ibdev(ieq->dev), "IEQ: error bad crc\n"); + pfpdu->mpa_crc_err = true; + goto error; + } + } + + print_hex_dump_debug("IEQ: IEQ TX BUFFER", DUMP_PREFIX_OFFSET, 16, 8, + txbuf->mem.va, txbuf->totallen, false); + if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) + txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; + txbuf->do_lpb = true; + irdma_puda_send_buf(ieq, txbuf); + pfpdu->rcv_nxt = seqnum + fpdu_len; + return status; + +error: + while (!list_empty(&pbufl)) { + buf = (struct irdma_puda_buf *)(pbufl.prev); + list_move(&buf->list, rxlist); + } + if (txbuf) + irdma_puda_ret_bufpool(ieq, txbuf); + + return status; +} + +/** + * irdma_ieq_process_buf - process buffer rcvd for ieq + * @ieq: ieq resource + * @pfpdu: partial management per user qp + * @buf: receive buffer + */ +static int irdma_ieq_process_buf(struct irdma_puda_rsrc *ieq, + struct irdma_pfpdu *pfpdu, + struct irdma_puda_buf *buf) +{ + u16 fpdu_len = 0; + u16 datalen = buf->datalen; + u8 *datap = buf->data; + u8 *crcptr; + u16 ioffset = 0; + u32 mpacrc; + u32 seqnum = buf->seqnum; + u16 len = 0; + u16 full = 0; + bool partial = false; + struct irdma_puda_buf *txbuf; + struct list_head *rxlist = &pfpdu->rxlist; + int ret = 0; + + ioffset = (u16)(buf->data - (u8 *)buf->mem.va); + while (datalen) { + fpdu_len = irdma_ieq_get_fpdu_len(pfpdu, datap, buf->seqnum); + if (!fpdu_len) { + ibdev_dbg(to_ibdev(ieq->dev), + "IEQ: error bad fpdu len\n"); + list_add(&buf->list, rxlist); + pfpdu->mpa_crc_err = true; + return -EINVAL; + } + + if (datalen < fpdu_len) { + partial = true; + break; + } + crcptr = datap + fpdu_len - 4; + mpacrc = *(u32 *)crcptr; + if (ieq->check_crc) + ret = irdma_ieq_check_mpacrc(ieq->hash_desc, datap, + fpdu_len - 4, mpacrc); + if (ret) { + list_add(&buf->list, rxlist); + ibdev_dbg(to_ibdev(ieq->dev), + "ERR: IRDMA_ERR_MPA_CRC\n"); + pfpdu->mpa_crc_err = true; + return ret; + } + full++; + pfpdu->fpdu_processed++; + ieq->fpdu_processed++; + datap += fpdu_len; + len += fpdu_len; + datalen -= fpdu_len; + } + if (full) { + /* copy full pdu's in the txbuf and send them out */ + txbuf = irdma_puda_get_bufpool(ieq); + if (!txbuf) { + pfpdu->no_tx_bufs++; + list_add(&buf->list, rxlist); + return -ENOBUFS; + } + /* modify txbuf's buffer header */ + irdma_ieq_setup_tx_buf(buf, txbuf); + /* copy full fpdu's to new buffer */ + if (ieq->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, + txbuf->hdrlen, len); + txbuf->totallen = txbuf->hdrlen + len; + txbuf->ah_id = pfpdu->ah->ah_info.ah_idx; + } else { + irdma_ieq_copy_to_txbuf(buf, txbuf, ioffset, + buf->hdrlen, len); + txbuf->totallen = buf->hdrlen + len; + } + irdma_ieq_update_tcpip_info(txbuf, len, buf->seqnum); + print_hex_dump_debug("IEQ: IEQ TX BUFFER", DUMP_PREFIX_OFFSET, + 16, 8, txbuf->mem.va, txbuf->totallen, + false); + txbuf->do_lpb = true; + irdma_puda_send_buf(ieq, txbuf); + + if (!datalen) { + pfpdu->rcv_nxt = buf->seqnum + len; + irdma_puda_ret_bufpool(ieq, buf); + return 0; + } + buf->data = datap; + buf->seqnum = seqnum + len; + buf->datalen = datalen; + pfpdu->rcv_nxt = buf->seqnum; + } + if (partial) + return irdma_ieq_handle_partial(ieq, pfpdu, buf, fpdu_len); + + return 0; +} + +/** + * irdma_ieq_process_fpdus - process fpdu's buffers on its list + * @qp: qp for which partial fpdus + * @ieq: ieq resource + */ +void irdma_ieq_process_fpdus(struct irdma_sc_qp *qp, + struct irdma_puda_rsrc *ieq) +{ + struct irdma_pfpdu *pfpdu = &qp->pfpdu; + struct list_head *rxlist = &pfpdu->rxlist; + struct irdma_puda_buf *buf; + int status; + + do { + if (list_empty(rxlist)) + break; + buf = irdma_puda_get_listbuf(rxlist); + if (!buf) { + ibdev_dbg(to_ibdev(ieq->dev), "IEQ: error no buf\n"); + break; + } + if (buf->seqnum != pfpdu->rcv_nxt) { + /* This could be out of order or missing packet */ + pfpdu->out_of_order++; + list_add(&buf->list, rxlist); + break; + } + /* keep processing buffers from the head of the list */ + status = irdma_ieq_process_buf(ieq, pfpdu, buf); + if (status && pfpdu->mpa_crc_err) { + while (!list_empty(rxlist)) { + buf = irdma_puda_get_listbuf(rxlist); + irdma_puda_ret_bufpool(ieq, buf); + pfpdu->crc_err++; + ieq->crc_err++; + } + /* create CQP for AE */ + irdma_ieq_mpa_crc_ae(ieq->dev, qp); + } + } while (!status); +} + +/** + * irdma_ieq_create_ah - create an address handle for IEQ + * @qp: qp pointer + * @buf: buf received on IEQ used to create AH + */ +static int irdma_ieq_create_ah(struct irdma_sc_qp *qp, struct irdma_puda_buf *buf) +{ + struct irdma_ah_info ah_info = {}; + + qp->pfpdu.ah_buf = buf; + irdma_puda_ieq_get_ah_info(qp, &ah_info); + return irdma_puda_create_ah(qp->vsi->dev, &ah_info, false, + IRDMA_PUDA_RSRC_TYPE_IEQ, qp, + &qp->pfpdu.ah); +} + +/** + * irdma_ieq_handle_exception - handle qp's exception + * @ieq: ieq resource + * @qp: qp receiving excpetion + * @buf: receive buffer + */ +static void irdma_ieq_handle_exception(struct irdma_puda_rsrc *ieq, + struct irdma_sc_qp *qp, + struct irdma_puda_buf *buf) +{ + struct irdma_pfpdu *pfpdu = &qp->pfpdu; + u32 *hw_host_ctx = (u32 *)qp->hw_host_ctx; + u32 rcv_wnd = hw_host_ctx[23]; + /* first partial seq # in q2 */ + u32 fps = *(u32 *)(qp->q2_buf + Q2_FPSN_OFFSET); + struct list_head *rxlist = &pfpdu->rxlist; + unsigned long flags = 0; + u8 hw_rev = qp->dev->hw_attrs.uk_attrs.hw_rev; + + print_hex_dump_debug("IEQ: IEQ RX BUFFER", DUMP_PREFIX_OFFSET, 16, 8, + buf->mem.va, buf->totallen, false); + + spin_lock_irqsave(&pfpdu->lock, flags); + pfpdu->total_ieq_bufs++; + if (pfpdu->mpa_crc_err) { + pfpdu->crc_err++; + goto error; + } + if (pfpdu->mode && fps != pfpdu->fps) { + /* clean up qp as it is new partial sequence */ + irdma_ieq_cleanup_qp(ieq, qp); + ibdev_dbg(to_ibdev(ieq->dev), "IEQ: restarting new partial\n"); + pfpdu->mode = false; + } + + if (!pfpdu->mode) { + print_hex_dump_debug("IEQ: Q2 BUFFER", DUMP_PREFIX_OFFSET, 16, + 8, (u64 *)qp->q2_buf, 128, false); + /* First_Partial_Sequence_Number check */ + pfpdu->rcv_nxt = fps; + pfpdu->fps = fps; + pfpdu->mode = true; + pfpdu->max_fpdu_data = (buf->ipv4) ? + (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV4) : + (ieq->vsi->mtu - IRDMA_MTU_TO_MSS_IPV6); + pfpdu->pmode_count++; + ieq->pmode_count++; + INIT_LIST_HEAD(rxlist); + irdma_ieq_check_first_buf(buf, fps); + } + + if (!(rcv_wnd >= (buf->seqnum - pfpdu->rcv_nxt))) { + pfpdu->bad_seq_num++; + ieq->bad_seq_num++; + goto error; + } + + if (!list_empty(rxlist)) { + if (buf->seqnum != pfpdu->nextseqnum) { + irdma_send_ieq_ack(qp); + /* throw away out-of-order, duplicates*/ + goto error; + } + } + /* Insert buf before head */ + list_add_tail(&buf->list, rxlist); + pfpdu->nextseqnum = buf->seqnum + buf->datalen; + pfpdu->lastrcv_buf = buf; + if (hw_rev >= IRDMA_GEN_2 && !pfpdu->ah) { + irdma_ieq_create_ah(qp, buf); + if (!pfpdu->ah) + goto error; + goto exit; + } + if (hw_rev == IRDMA_GEN_1) + irdma_ieq_process_fpdus(qp, ieq); + else if (pfpdu->ah && pfpdu->ah->ah_info.ah_valid) + irdma_ieq_process_fpdus(qp, ieq); +exit: + spin_unlock_irqrestore(&pfpdu->lock, flags); + + return; + +error: + irdma_puda_ret_bufpool(ieq, buf); + spin_unlock_irqrestore(&pfpdu->lock, flags); +} + +/** + * irdma_ieq_receive - received exception buffer + * @vsi: VSI of device + * @buf: exception buffer received + */ +static void irdma_ieq_receive(struct irdma_sc_vsi *vsi, + struct irdma_puda_buf *buf) +{ + struct irdma_puda_rsrc *ieq = vsi->ieq; + struct irdma_sc_qp *qp = NULL; + u32 wqe_idx = ieq->compl_rxwqe_idx; + + qp = irdma_ieq_get_qp(vsi->dev, buf); + if (!qp) { + ieq->stats_bad_qp_id++; + irdma_puda_ret_bufpool(ieq, buf); + } else { + irdma_ieq_handle_exception(ieq, qp, buf); + } + /* + * ieq->rx_wqe_idx is used by irdma_puda_replenish_rq() + * on which wqe_idx to start replenish rq + */ + if (!ieq->rxq_invalid_cnt) + ieq->rx_wqe_idx = wqe_idx; + ieq->rxq_invalid_cnt++; +} + +/** + * irdma_ieq_tx_compl - put back after sending completed exception buffer + * @vsi: sc VSI struct + * @sqwrid: pointer to puda buffer + */ +static void irdma_ieq_tx_compl(struct irdma_sc_vsi *vsi, void *sqwrid) +{ + struct irdma_puda_rsrc *ieq = vsi->ieq; + struct irdma_puda_buf *buf = sqwrid; + + irdma_puda_ret_bufpool(ieq, buf); +} + +/** + * irdma_ieq_cleanup_qp - qp is being destroyed + * @ieq: ieq resource + * @qp: all pending fpdu buffers + */ +void irdma_ieq_cleanup_qp(struct irdma_puda_rsrc *ieq, struct irdma_sc_qp *qp) +{ + struct irdma_puda_buf *buf; + struct irdma_pfpdu *pfpdu = &qp->pfpdu; + struct list_head *rxlist = &pfpdu->rxlist; + + if (qp->pfpdu.ah) { + irdma_puda_free_ah(ieq->dev, qp->pfpdu.ah); + qp->pfpdu.ah = NULL; + qp->pfpdu.ah_buf = NULL; + } + + if (!pfpdu->mode) + return; + + while (!list_empty(rxlist)) { + buf = irdma_puda_get_listbuf(rxlist); + irdma_puda_ret_bufpool(ieq, buf); + } +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/puda.h b/drivers/intel/irdma-1.14.33/src/irdma/puda.h new file mode 100644 index 000000000..b27e06b85 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/puda.h @@ -0,0 +1,185 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2022 Intel Corporation */ +#ifndef IRDMA_PUDA_H +#define IRDMA_PUDA_H + +#define IRDMA_IEQ_MPA_FRAMING 6 +#define IRDMA_TCP_OFFSET 40 +#define IRDMA_IPV4_PAD 20 +#define IRDMA_MRK_BLK_SZ 512 + +enum puda_rsrc_type { + IRDMA_PUDA_RSRC_TYPE_ILQ = 1, + IRDMA_PUDA_RSRC_TYPE_IEQ, + IRDMA_PUDA_RSRC_TYPE_MAX, /* Must be last entry */ +}; + +enum puda_rsrc_complete { + PUDA_CQ_CREATED = 1, + PUDA_QP_CREATED, + PUDA_TX_COMPLETE, + PUDA_RX_COMPLETE, + PUDA_HASH_CRC_COMPLETE, +}; + +struct irdma_sc_dev; +struct irdma_sc_qp; +struct irdma_sc_cq; + +struct irdma_puda_cmpl_info { + struct irdma_qp_uk *qp; + u8 q_type; + u8 l3proto; + u8 l4proto; + u16 vlan; + u32 payload_len; + u32 compl_error; /* No_err=0, else major and minor err code */ + u32 qp_id; + u32 wqe_idx; + bool ipv4:1; + bool smac_valid:1; + bool vlan_valid:1; + u8 smac[ETH_ALEN]; +}; + +struct irdma_puda_send_info { + u64 paddr; /* Physical address */ + u32 len; + u32 ah_id; + u8 tcplen; + u8 maclen; + bool ipv4:1; + bool do_lpb:1; + void *scratch; +}; + +struct irdma_puda_buf { + struct list_head list; /* MUST be first entry */ + struct irdma_dma_mem mem; /* DMA memory for the buffer */ + struct irdma_puda_buf *next; /* for alloclist in rsrc struct */ + struct irdma_virt_mem buf_mem; /* Buffer memory for this buffer */ + void *scratch; + u8 *iph; + u8 *tcph; + u8 *data; + u16 datalen; + u16 vlan_id; + u8 tcphlen; /* tcp length in bytes */ + u8 maclen; /* mac length in bytes */ + u32 totallen; /* machlen+iphlen+tcphlen+datalen */ + refcount_t refcount; + u8 hdrlen; + bool ipv4:1; + bool vlan_valid:1; + bool do_lpb:1; /* Loopback buffer */ + bool smac_valid:1; + u32 seqnum; + u32 ah_id; + u8 smac[ETH_ALEN]; + struct irdma_sc_vsi *vsi; +}; + +struct irdma_puda_rsrc_info { + void (*receive)(struct irdma_sc_vsi *vsi, struct irdma_puda_buf *buf); + void (*xmit_complete)(struct irdma_sc_vsi *vsi, void *sqwrid); + enum puda_rsrc_type type; /* ILQ or IEQ */ + u32 count; + u32 pd_id; + u32 cq_id; + u32 qp_id; + u32 sq_size; + u32 rq_size; + u32 tx_buf_cnt; /* total bufs allocated will be rq_size + tx_buf_cnt */ + u16 buf_size; + u16 stats_idx; + bool stats_idx_valid:1; + int abi_ver; +}; + +struct irdma_puda_rsrc { + struct irdma_sc_cq cq; + struct irdma_sc_qp qp; + struct irdma_sc_pd sc_pd; + struct irdma_sc_dev *dev; + struct irdma_sc_vsi *vsi; + struct irdma_dma_mem cqmem; + struct irdma_dma_mem qpmem; + struct irdma_virt_mem ilq_mem; + enum puda_rsrc_complete cmpl; + enum puda_rsrc_type type; + u16 buf_size; /*buf must be max datalen + tcpip hdr + mac */ + u32 cq_id; + u32 qp_id; + u32 sq_size; + u32 rq_size; + u32 cq_size; + struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; + u64 *rq_wrid_array; + u32 compl_rxwqe_idx; + u32 rx_wqe_idx; + u32 rxq_invalid_cnt; + u32 tx_wqe_avail_cnt; + struct shash_desc *hash_desc; + struct list_head txpend; + struct list_head bufpool; /* free buffers pool list for recv and xmit */ + u32 alloc_buf_count; + u32 avail_buf_count; /* snapshot of currently available buffers */ + spinlock_t bufpool_lock; + struct irdma_puda_buf *alloclist; + void (*receive)(struct irdma_sc_vsi *vsi, struct irdma_puda_buf *buf); + void (*xmit_complete)(struct irdma_sc_vsi *vsi, void *sqwrid); + /* puda stats */ + u64 stats_buf_alloc_fail; + u64 stats_pkt_rcvd; + u64 stats_pkt_sent; + u64 stats_rcvd_pkt_err; + u64 stats_sent_pkt_q; + u64 stats_bad_qp_id; + /* IEQ stats */ + u64 fpdu_processed; + u64 bad_seq_num; + u64 crc_err; + u64 pmode_count; + u64 partials_handled; + u16 stats_idx; + bool check_crc:1; + bool stats_idx_valid:1; +}; + +struct irdma_puda_buf *irdma_puda_get_bufpool(struct irdma_puda_rsrc *rsrc); +void irdma_puda_ret_bufpool(struct irdma_puda_rsrc *rsrc, + struct irdma_puda_buf *buf); +void irdma_puda_send_buf(struct irdma_puda_rsrc *rsrc, + struct irdma_puda_buf *buf); +int irdma_puda_send(struct irdma_sc_qp *qp, struct irdma_puda_send_info *info); +int irdma_puda_create_rsrc(struct irdma_sc_vsi *vsi, + struct irdma_puda_rsrc_info *info); +void irdma_puda_dele_rsrc(struct irdma_sc_vsi *vsi, enum puda_rsrc_type type, + bool reset); +int irdma_puda_poll_cmpl(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq, + u32 *compl_err); + +struct irdma_sc_qp *irdma_ieq_get_qp(struct irdma_sc_dev *dev, + struct irdma_puda_buf *buf); +int irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info, + struct irdma_puda_buf *buf); +int irdma_ieq_check_mpacrc(struct shash_desc *desc, void *addr, u32 len, u32 val); +int irdma_init_hash_desc(struct shash_desc **desc); +void irdma_ieq_mpa_crc_ae(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp); +void irdma_free_hash_desc(struct shash_desc *desc); +void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len, u32 seqnum); +int irdma_cqp_qp_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp); +int irdma_cqp_cq_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq); +int irdma_cqp_qp_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp); +void irdma_cqp_cq_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq); +void irdma_puda_ieq_get_ah_info(struct irdma_sc_qp *qp, + struct irdma_ah_info *ah_info); +int irdma_puda_create_ah(struct irdma_sc_dev *dev, + struct irdma_ah_info *ah_info, bool wait, + enum puda_rsrc_type type, void *cb_param, + struct irdma_sc_ah **ah); +void irdma_puda_free_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah); +void irdma_ieq_process_fpdus(struct irdma_sc_qp *qp, + struct irdma_puda_rsrc *ieq); +void irdma_ieq_cleanup_qp(struct irdma_puda_rsrc *ieq, struct irdma_sc_qp *qp); +#endif /*IRDMA_PROTOS_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/rhel_kcompat.h b/drivers/intel/irdma-1.14.33/src/irdma/rhel_kcompat.h new file mode 100644 index 000000000..261afa1ac --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/rhel_kcompat.h @@ -0,0 +1,1345 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2020 - 2022 Intel Corporation */ +#ifndef RHEL_KCOMPAT_H +#define RHEL_KCOMPAT_H + +#ifdef RHEL_9_2 +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V2 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_QP_VER_2 +#define GLOBAL_QP_MEM +#define CREATE_CQ_VER_3 +#define DESTROY_AH_VER_4 +#define DEALLOC_PD_VER_4 +#define DESTROY_QP_VER_2 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEV_CAPS_VER_2 +#define IB_DEALLOC_DRIVER_SUPPORT +#define IW_PORT_IMMUTABLE_V2 +#define IB_UMEM_GET_V3 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define SET_DMABUF +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_9_2 */ + +#ifdef RHEL_9_1 +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V2 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_QP_VER_2 +#define GLOBAL_QP_MEM +#define CREATE_CQ_VER_3 +#define DESTROY_AH_VER_4 +#define DEALLOC_PD_VER_4 +#define DESTROY_QP_VER_2 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IW_PORT_IMMUTABLE_V2 +#define IB_UMEM_GET_V3 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define SET_DMABUF +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_9_1 */ + +#ifdef RHEL_9_0 +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_QP_VER_1 +#define CREATE_CQ_VER_3 +#define DESTROY_AH_VER_4 +#define DEALLOC_PD_VER_4 +#define DESTROY_QP_VER_2 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IW_PORT_IMMUTABLE_V2 +#define IB_UMEM_GET_V3 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_9_0 */ + +#ifdef RHEL_8_8 +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V2 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_QP_VER_2 +#define GLOBAL_QP_MEM +#define CREATE_CQ_VER_3 +#define DESTROY_AH_VER_4 +#define DEALLOC_PD_VER_4 +#define DESTROY_QP_VER_2 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IW_PORT_IMMUTABLE_V2 +#define IB_UMEM_GET_V2 +#define IB_DEV_CAPS_VER_2 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define GET_NETDEV_OP_V2 + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_8_8 */ + +#ifdef RHEL_8_7 +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V2 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_QP_VER_2 +#define GLOBAL_QP_MEM +#define CREATE_CQ_VER_3 +#define DESTROY_AH_VER_4 +#define DEALLOC_PD_VER_4 +#define DESTROY_QP_VER_2 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IW_PORT_IMMUTABLE_V2 +#define IB_UMEM_GET_V2 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define GET_NETDEV_OP_V2 + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_8_7 */ + +#ifdef RHEL_8_6 +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_QP_VER_1 +#define CREATE_CQ_VER_3 +#define DESTROY_AH_VER_4 +#define DEALLOC_PD_VER_4 +#define DESTROY_QP_VER_2 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IW_PORT_IMMUTABLE_V2 +#define IB_UMEM_GET_V2 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define GET_NETDEV_OP_V2 + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_8_6 */ + +#ifdef RHEL_8_5 +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_QP_VER_1 +#define CREATE_CQ_VER_3 +#define DESTROY_AH_VER_4 +#define DEALLOC_PD_VER_4 +#define DESTROY_QP_VER_2 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_IW_PKEY +#define IW_PORT_IMMUTABLE_V1 +#define IB_UMEM_GET_V2 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define MODIFY_PORT_V1 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_2 +#define ROCE_PORT_IMMUTABLE_V1 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define USE_KMAP + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_8_5 */ + +#ifdef RHEL_8_4 +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_QP_VER_1 +#define CREATE_CQ_VER_3 +#define DESTROY_AH_VER_3 +#define DEALLOC_PD_VER_3 +#define DESTROY_QP_VER_2 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_IW_PKEY +#define IW_PORT_IMMUTABLE_V1 +#define IB_UMEM_GET_V2 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_3 +#define IRDMA_DESTROY_SRQ_VER_2 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define MODIFY_PORT_V1 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define UVERBS_CMD_MASK +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_8_4 */ + +#ifdef RHEL_8_3 + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_2 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_3 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_3 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define NETDEV_TO_IBDEV_SUPPORT +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_IW_PKEY +#define IB_UMEM_GET_V2 +#define IN_IFADDR +#define IRDMA_ALLOC_MR_VER_1 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_3 +#define IRDMA_DESTROY_SRQ_VER_2 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define UVERBS_CMD_MASK +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_8_3 */ + +#ifdef RHEL_7_9 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_4 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define CREATE_QP_VER_1 +#define DESTROY_QP_VER_1 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_UMEM_GET_V1 +#define IB_IW_PKEY +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_2 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +#define kc_set_ibdev_add_del_gid(ibdev) +#define wait_queue_entry __wait_queue +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, NULL) +#define kc_typeq_ib_wr const +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) + +#endif + +#ifdef RHEL_8_2 +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_2 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_1 +#define DESTROY_AH_VER_3 +#define CREATE_QP_VER_1 +#define DESTROY_QP_VER_2 +#define DEALLOC_PD_VER_3 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define NETDEV_TO_IBDEV_SUPPORT +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IN_IFADDR +#define IRDMA_ALLOC_MR_VER_1 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_3 +#define IRDMA_DESTROY_SRQ_VER_2 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define UVERBS_CMD_MASK +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_typeq_ib_wr const + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* RHEL_8_2 */ + +#ifdef RHEL_8_1 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_3 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DESTROY_AH_VER_2 +#define DEALLOC_UCONTEXT_VER_1 +#define DEALLOC_PD_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_QP_VER_1 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define IB_GET_NETDEV_OP_NOT_DEPRECATED +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_SET_DRIVER_ID +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_2 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define kc_irdma_destroy_qp(ibqp, udata) irdma_destroy_qp(ibqp) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, NULL) +#define kc_typeq_ib_wr const +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_set_ibdev_add_del_gid(ibdev) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) +#endif /* RHEL_8_1 */ + +#ifdef RHEL_7_8 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_4 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_2 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +#define kc_set_ibdev_add_del_gid(ibdev) +#define wait_queue_entry __wait_queue +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, NULL) +#define kc_typeq_ib_wr const +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) +#endif /* RHEL_7_8 */ + +#ifdef RHEL_7_7 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_4 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_2 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +#define kc_set_ibdev_add_del_gid(ibdev) +#define wait_queue_entry __wait_queue +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, NULL) +#define kc_typeq_ib_wr const +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) +#endif /* RHEL_7_7 */ + +#ifdef RHEL_8_0 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_1_2 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEALLOC_PD_VER_1 +#define DEREG_MR_VER_1 +#define ETHER_COPY_VER_2 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_UMEM_GET_V1 +#define IB_GET_CACHED_GID +#define IB_IW_MANDATORY_AH_OP +#define IB_IW_PKEY +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_SET_DRIVER_ID +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_typeq_ib_wr +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_set_ibdev_add_del_gid(ibdev) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) +#endif /* RHEL_8_0 */ + +#ifdef RHEL_7_6 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_1_2 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_2 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_GET_CACHED_GID +#define IB_IW_MANDATORY_AH_OP +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IW_PORT_IMMUTABLE_V1 +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +#define wait_queue_entry __wait_queue +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_typeq_ib_wr +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) + +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) + +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) + +#define kc_set_ibdev_add_del_gid(ibdev) do { \ + ibdev->add_gid = irdma_add_gid; \ + ibdev->del_gid = irdma_del_gid; \ +} while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) +#endif /* RHEL_7_6 */ + +#ifdef RHEL_7_5 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_1_2 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_2 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_IW_MANDATORY_AH_OP +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +#define wait_queue_entry __wait_queue +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_typeq_ib_wr +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define set_ibdev_dma_device(ibdev, dev) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) + +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) + +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) + +#define kc_set_ibdev_add_del_gid(ibdev) do { \ + ibdev->add_gid = irdma_add_gid; \ + ibdev->del_gid = irdma_del_gid; \ +} while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) +#endif /* RHEL_7_5 */ + +#ifdef RHEL_7_4 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_1_1 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEALLOC_PD_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_1 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_IW_PKEY +#define IB_IW_MANDATORY_AH_OP +#define IB_GET_CACHED_GID +#define IB_UMEM_GET_V1 +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +#define wait_queue_entry __wait_queue +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_typeq_ib_wr +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define rdma_ah_attr ib_ah_attr +#define ah_attr_to_dmac(attr) ((attr).dmac) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) + +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) + +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) + +#define kc_set_ibdev_add_del_gid(ibdev) do { \ + ibdev->add_gid = irdma_add_gid; \ + ibdev->del_gid = irdma_del_gid; \ +} while (0) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) + +#define set_ibdev_dma_device(ibdev, dev) \ + ibdev.dma_device = dev + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) +#endif /* RHEL_7_4 */ +#endif /* RHEL_KCOMPAT_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/suse_kcompat.h b/drivers/intel/irdma-1.14.33/src/irdma/suse_kcompat.h new file mode 100644 index 000000000..9f27bcf4c --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/suse_kcompat.h @@ -0,0 +1,766 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2020 - 2024 Intel Corporation */ +#ifndef SUSE_KCOMPAT_H +#define SUSE_KCOMPAT_H + +#ifdef SLES_15_SP_6 +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V2 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define COPY_USER_PGADDR_VER_4 +#define CREATE_AH_VER_5 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_2 +#define GLOBAL_QP_MEM +#define DEALLOC_PD_VER_4 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_4 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define IB_DEV_CAPS_VER_2 +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_UMEM_GET_V3 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#define IW_PORT_IMMUTABLE_V2 +#define HAS_IB_SET_DEVICE_OP +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define SET_DMABUF +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 + +#define kc_typeq_ib_wr const +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* SLES_15_SP6 */ + +#ifdef SLES_15_SP_5 +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V2 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_2 +#define GLOBAL_QP_MEM +#define DEALLOC_PD_VER_4 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_4 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_UMEM_GET_V3 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#define IW_PORT_IMMUTABLE_V2 +#define HAS_IB_SET_DEVICE_OP +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define SET_DMABUF +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 + +#define kc_typeq_ib_wr const +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* SLES_15_SP5 */ + +#ifdef SLES_15_SP_4 +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V2 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_2 +#define GLOBAL_QP_MEM +#define DEALLOC_PD_VER_4 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_4 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_UMEM_GET_V3 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_ALLOC_MR_VER_0 +#if (SLE_LOCALVERSION_CODE < KERNEL_VERSION(150400ULL, 24, 49)) +#define IRDMA_IRQ_UPDATE_AFFINITY +#endif +#define IW_PORT_IMMUTABLE_V2 +#define HAS_IB_SET_DEVICE_OP +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define SET_DMABUF +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 + +#define kc_typeq_ib_wr const +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* SLES_15_SP4 */ + +#ifdef SLES_15_SP_3 +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_3 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_3 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_IW_PKEY +#define IB_UMEM_GET_V3 +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_3 +#define IRDMA_DESTROY_SRQ_VER_2 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define HAS_IB_SET_DEVICE_OP +#define MODIFY_PORT_V1 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define UVERBS_CMD_MASK +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define kc_typeq_ib_wr const +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* SLES_15_SP23 */ + +#ifdef SLES_15_SP_2 +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_2 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_3 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_3 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_UMEM_GET_V1 +#define IB_IW_PKEY +#define IN_IFADDR +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_3 +#define IRDMA_DESTROY_SRQ_VER_2 +#define IRDMA_ALLOC_MR_VER_1 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define UVERBS_CMD_MASK +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define kc_typeq_ib_wr const +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#endif /* SLES_15_SP2 */ + +#ifdef SLES_15_SP_1 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_4 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_ADD_DEL_GID +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_SET_DRIVER_ID +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_2 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define kc_typeq_ib_wr const +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, NULL) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) + +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + rdma_gid_attr_network_type(sgid_attr) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) +#endif /* SLES_15_SP_1 */ + +#ifdef SLES_15 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_1_2 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEALLOC_PD_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_2 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_GET_CACHED_GID +#define IB_IW_PKEY +#define IB_IW_MANDATORY_AH_OP +#define IB_UMEM_GET_V1 +#define IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION IB_CQ_FLAGS_TIMESTAMP_COMPLETION +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define kc_typeq_ib_wr +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr).ndev) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) + +#define kc_set_ibdev_add_del_gid(ibdev) do { \ + ibdev->add_gid = irdma_add_gid; \ + ibdev->del_gid = irdma_del_gid; \ +} while (0) + +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) + +#define ibdev_dbg(ibdev, ...) \ + dev_dbg(&((ibdev)->dev), __VA_ARGS__) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) +#endif /* SLES_15 */ + +#ifdef SLES_12_SP_4 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_1_2 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_2 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_GET_CACHED_GID +#define IB_IW_MANDATORY_AH_OP +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION IB_CQ_FLAGS_TIMESTAMP_COMPLETION +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define SET_PCIDEV_PARENT +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE + +#define kc_typeq_ib_wr +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr).ndev) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) + +#define kc_set_ibdev_add_del_gid(ibdev) do { \ + ibdev->add_gid = irdma_add_gid; \ + ibdev->del_gid = irdma_del_gid; \ +} while (0) + +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) + +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) +#endif /* SLES_12_SP_4 */ + +#ifdef SLES_12_SP_5 +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_1_2 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_2 +#define FOR_IFA +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_GET_CACHED_GID +#define IB_IW_MANDATORY_AH_OP +#define IB_IW_PKEY +#define IB_UMEM_GET_V1 +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_2 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define kc_typeq_ib_wr +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define ib_device_put(dev) +#define kc_get_ucontext(udata) to_ucontext(context) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) + +#define kc_set_ibdev_add_del_gid(ibdev) do { \ + ibdev->add_gid = irdma_add_gid; \ + ibdev->del_gid = irdma_del_gid; \ +} while (0) + +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) + +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) + +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) + +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) + +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) + +#define ib_umem_get(udata, addr, size, access, dmasync) \ + ib_umem_get(pd->uobject->context, addr, size, access, dmasync) +#endif /* SLES_12_SP_5 */ + +#endif /* SUSE_KCOMPAT_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/trace.c b/drivers/intel/irdma-1.14.33/src/irdma/trace.c new file mode 100644 index 000000000..b5133f413 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/trace.c @@ -0,0 +1,112 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2019 Intel Corporation */ +#define CREATE_TRACE_POINTS +#include "trace.h" + +const char *print_ip_addr(struct trace_seq *p, u32 *addr, u16 port, bool ipv4) +{ + const char *ret = trace_seq_buffer_ptr(p); + + if (ipv4) { + __be32 myaddr = htonl(*addr); + + trace_seq_printf(p, "%pI4:%d", &myaddr, htons(port)); + } else { + trace_seq_printf(p, "%pI6:%d", addr, htons(port)); + } + trace_seq_putc(p, 0); + + return ret; +} + +const char *parse_iw_event_type(enum iw_cm_event_type iw_type) +{ + switch (iw_type) { + case IW_CM_EVENT_CONNECT_REQUEST: + return "IwRequest"; + case IW_CM_EVENT_CONNECT_REPLY: + return "IwReply"; + case IW_CM_EVENT_ESTABLISHED: + return "IwEstablished"; + case IW_CM_EVENT_DISCONNECT: + return "IwDisconnect"; + case IW_CM_EVENT_CLOSE: + return "IwClose"; + } + + return "Unknown"; +} + +const char *parse_cm_event_type(enum irdma_cm_event_type cm_type) +{ + switch (cm_type) { + case IRDMA_CM_EVENT_ESTABLISHED: + return "CmEstablished"; + case IRDMA_CM_EVENT_MPA_REQ: + return "CmMPA_REQ"; + case IRDMA_CM_EVENT_MPA_CONNECT: + return "CmMPA_CONNECT"; + case IRDMA_CM_EVENT_MPA_ACCEPT: + return "CmMPA_ACCEPT"; + case IRDMA_CM_EVENT_MPA_REJECT: + return "CmMPA_REJECT"; + case IRDMA_CM_EVENT_MPA_ESTABLISHED: + return "CmMPA_ESTABLISHED"; + case IRDMA_CM_EVENT_CONNECTED: + return "CmConnected"; + case IRDMA_CM_EVENT_RESET: + return "CmReset"; + case IRDMA_CM_EVENT_ABORTED: + return "CmAborted"; + case IRDMA_CM_EVENT_UNKNOWN: + return "none"; + } + return "Unknown"; +} + +const char *parse_cm_state(enum irdma_cm_node_state state) +{ + switch (state) { + case IRDMA_CM_STATE_UNKNOWN: + return "UNKNOWN"; + case IRDMA_CM_STATE_INITED: + return "INITED"; + case IRDMA_CM_STATE_LISTENING: + return "LISTENING"; + case IRDMA_CM_STATE_SYN_RCVD: + return "SYN_RCVD"; + case IRDMA_CM_STATE_SYN_SENT: + return "SYN_SENT"; + case IRDMA_CM_STATE_ONE_SIDE_ESTABLISHED: + return "ONE_SIDE_ESTABLISHED"; + case IRDMA_CM_STATE_ESTABLISHED: + return "ESTABLISHED"; + case IRDMA_CM_STATE_ACCEPTING: + return "ACCEPTING"; + case IRDMA_CM_STATE_MPAREQ_SENT: + return "MPAREQ_SENT"; + case IRDMA_CM_STATE_MPAREQ_RCVD: + return "MPAREQ_RCVD"; + case IRDMA_CM_STATE_MPAREJ_RCVD: + return "MPAREJ_RECVD"; + case IRDMA_CM_STATE_OFFLOADED: + return "OFFLOADED"; + case IRDMA_CM_STATE_FIN_WAIT1: + return "FIN_WAIT1"; + case IRDMA_CM_STATE_FIN_WAIT2: + return "FIN_WAIT2"; + case IRDMA_CM_STATE_CLOSE_WAIT: + return "CLOSE_WAIT"; + case IRDMA_CM_STATE_TIME_WAIT: + return "TIME_WAIT"; + case IRDMA_CM_STATE_LAST_ACK: + return "LAST_ACK"; + case IRDMA_CM_STATE_CLOSING: + return "CLOSING"; + case IRDMA_CM_STATE_LISTENER_DESTROYED: + return "LISTENER_DESTROYED"; + case IRDMA_CM_STATE_CLOSED: + return "CLOSED"; + } + return ("Bad state"); +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/trace.h b/drivers/intel/irdma-1.14.33/src/irdma/trace.h new file mode 100644 index 000000000..702e4efb0 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/trace.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2019 Intel Corporation */ +#include "trace_cm.h" diff --git a/drivers/intel/irdma-1.14.33/src/irdma/trace_cm.h b/drivers/intel/irdma-1.14.33/src/irdma/trace_cm.h new file mode 100644 index 000000000..40dd8e848 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/trace_cm.h @@ -0,0 +1,460 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2019 - 2022 Intel Corporation */ +#if !defined(__TRACE_CM_H) || defined(TRACE_HEADER_MULTI_READ) +#define __TRACE_CM_H + +#include +#include + +#include "main.h" + +const char *print_ip_addr(struct trace_seq *p, u32 *addr, u16 port, bool ivp4); +const char *parse_iw_event_type(enum iw_cm_event_type iw_type); +const char *parse_cm_event_type(enum irdma_cm_event_type cm_type); +const char *parse_cm_state(enum irdma_cm_node_state); +#define __print_ip_addr(addr, port, ipv4) print_ip_addr(p, addr, port, ipv4) + +#undef TRACE_SYSTEM +#define TRACE_SYSTEM irdma_cm + +TRACE_EVENT(irdma_create_listen, + TP_PROTO(struct irdma_device *iwdev, struct irdma_cm_info *cm_info), + TP_ARGS(iwdev, cm_info), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __dynamic_array(u32, laddr, 4) + __field(u16, lport) + __field(bool, ipv4) + ), + TP_fast_assign(__entry->iwdev = iwdev; + __entry->lport = cm_info->loc_port; + __entry->ipv4 = cm_info->ipv4; + memcpy(__get_dynamic_array(laddr), + cm_info->loc_addr, 4); + ), + TP_printk("iwdev=%p loc: %s", + __entry->iwdev, + __print_ip_addr(__get_dynamic_array(laddr), + __entry->lport, __entry->ipv4) + ) +); + +TRACE_EVENT(irdma_dec_refcnt_listen, + TP_PROTO(struct irdma_cm_listener *listener, void *caller), + TP_ARGS(listener, caller), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __field(u32, refcnt) + __dynamic_array(u32, laddr, 4) + __field(u16, lport) + __field(bool, ipv4) + __field(void *, caller) + ), + TP_fast_assign(__entry->iwdev = listener->iwdev; + __entry->lport = listener->loc_port; + __entry->ipv4 = listener->ipv4; + memcpy(__get_dynamic_array(laddr), + listener->loc_addr, 4); + ), + TP_printk("iwdev=%p caller=%pS loc: %s", + __entry->iwdev, + __entry->caller, + __print_ip_addr(__get_dynamic_array(laddr), + __entry->lport, __entry->ipv4) + ) +); + +DECLARE_EVENT_CLASS(listener_template, + TP_PROTO(struct irdma_cm_listener *listener), + TP_ARGS(listener), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __field(u16, lport) + __field(u16, vlan_id) + __field(bool, ipv4) + __field(enum irdma_cm_listener_state, + state) + __dynamic_array(u32, laddr, 4) + ), + TP_fast_assign(__entry->iwdev = listener->iwdev; + __entry->lport = listener->loc_port; + __entry->vlan_id = listener->vlan_id; + __entry->ipv4 = listener->ipv4; + __entry->state = listener->listener_state; + memcpy(__get_dynamic_array(laddr), + listener->loc_addr, 4); + ), + TP_printk("iwdev=%p vlan=%d loc: %s", + __entry->iwdev, + __entry->vlan_id, + __print_ip_addr(__get_dynamic_array(laddr), + __entry->lport, __entry->ipv4) + ) +); + +DEFINE_EVENT(listener_template, irdma_find_listener, + TP_PROTO(struct irdma_cm_listener *listener), + TP_ARGS(listener)); + +DEFINE_EVENT(listener_template, irdma_del_multiple_qhash, + TP_PROTO(struct irdma_cm_listener *listener), + TP_ARGS(listener)); + +TRACE_EVENT(irdma_negotiate_mpa_v2, + TP_PROTO(struct irdma_cm_node *cm_node), + TP_ARGS(cm_node), + TP_STRUCT__entry(__field(struct irdma_cm_node *, cm_node) + __field(u16, ord_size) + __field(u16, ird_size) + ), + TP_fast_assign(__entry->cm_node = cm_node; + __entry->ord_size = cm_node->ord_size; + __entry->ird_size = cm_node->ird_size; + ), + TP_printk("MPVA2 Negotiated cm_node=%p ORD:[%d], IRD:[%d]", + __entry->cm_node, + __entry->ord_size, + __entry->ird_size + ) +); + +DECLARE_EVENT_CLASS(tos_template, + TP_PROTO(struct irdma_device *iwdev, u8 tos, u8 user_pri), + TP_ARGS(iwdev, tos, user_pri), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __field(u8, tos) + __field(u8, user_pri) + ), + TP_fast_assign(__entry->iwdev = iwdev; + __entry->tos = tos; + __entry->user_pri = user_pri; + ), + TP_printk("iwdev=%p TOS:[%d] UP:[%d]", + __entry->iwdev, + __entry->tos, + __entry->user_pri + ) +); + +DEFINE_EVENT(tos_template, irdma_listener_tos, + TP_PROTO(struct irdma_device *iwdev, u8 tos, u8 user_pri), + TP_ARGS(iwdev, tos, user_pri)); + +DEFINE_EVENT(tos_template, irdma_dcb_tos, + TP_PROTO(struct irdma_device *iwdev, u8 tos, u8 user_pri), + TP_ARGS(iwdev, tos, user_pri)); + +DECLARE_EVENT_CLASS(qhash_template, + TP_PROTO(struct irdma_device *iwdev, + struct irdma_cm_listener *listener, + const unsigned char *dev_addr), + TP_ARGS(iwdev, listener, dev_addr), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __field(u16, lport) + __field(u16, vlan_id) + __field(bool, ipv4) + __dynamic_array(u32, laddr, 4) + __dynamic_array(u32, mac, ETH_ALEN) + ), + TP_fast_assign(__entry->iwdev = iwdev; + __entry->lport = listener->loc_port; + __entry->vlan_id = listener->vlan_id; + __entry->ipv4 = listener->ipv4; + memcpy(__get_dynamic_array(laddr), + listener->loc_addr, 4); + ether_addr_copy(__get_dynamic_array(mac), + dev_addr); + ), + TP_printk("iwdev=%p vlan=%d MAC=%6phC loc: %s", + __entry->iwdev, + __entry->vlan_id, + __get_dynamic_array(mac), + __print_ip_addr(__get_dynamic_array(laddr), + __entry->lport, __entry->ipv4) + ) +); + +DEFINE_EVENT(qhash_template, irdma_add_mqh_6, + TP_PROTO(struct irdma_device *iwdev, + struct irdma_cm_listener *listener, + const unsigned char *dev_addr), + TP_ARGS(iwdev, listener, dev_addr)); + +DEFINE_EVENT(qhash_template, irdma_add_mqh_4, + TP_PROTO(struct irdma_device *iwdev, + struct irdma_cm_listener *listener, + const unsigned char *dev_addr), + TP_ARGS(iwdev, listener, dev_addr)); + +TRACE_EVENT(irdma_addr_resolve, + TP_PROTO(struct irdma_device *iwdev, char *dev_addr), + TP_ARGS(iwdev, dev_addr), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __dynamic_array(u8, mac, ETH_ALEN) + ), + TP_fast_assign(__entry->iwdev = iwdev; + ether_addr_copy(__get_dynamic_array(mac), dev_addr); + ), + TP_printk("iwdev=%p MAC=%6phC", __entry->iwdev, + __get_dynamic_array(mac) + ) +); + +TRACE_EVENT(irdma_send_cm_event, + TP_PROTO(struct irdma_cm_node *cm_node, struct iw_cm_id *cm_id, + enum iw_cm_event_type type, int status, void *caller), + TP_ARGS(cm_node, cm_id, type, status, caller), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __field(struct irdma_cm_node *, cm_node) + __field(struct iw_cm_id *, cm_id) + __field(u32, refcount) + __field(u16, lport) + __field(u16, rport) + __field(enum irdma_cm_node_state, state) + __field(bool, ipv4) + __field(u16, vlan_id) + __field(int, accel) + __field(enum iw_cm_event_type, type) + __field(int, status) + __field(void *, caller) + __dynamic_array(u32, laddr, 4) + __dynamic_array(u32, raddr, 4) + ), + TP_fast_assign(__entry->iwdev = cm_node->iwdev; + __entry->cm_node = cm_node; + __entry->cm_id = cm_id; + __entry->refcount = refcount_read(&cm_node->refcnt); + __entry->state = cm_node->state; + __entry->lport = cm_node->loc_port; + __entry->rport = cm_node->rem_port; + __entry->ipv4 = cm_node->ipv4; + __entry->vlan_id = cm_node->vlan_id; + __entry->accel = cm_node->accelerated; + __entry->type = type; + __entry->status = status; + __entry->caller = caller; + memcpy(__get_dynamic_array(laddr), + cm_node->loc_addr, 4); + memcpy(__get_dynamic_array(raddr), + cm_node->rem_addr, 4); + ), + TP_printk("iwdev=%p caller=%pS cm_id=%p node=%p refcnt=%d vlan_id=%d accel=%d state=%s event_type=%s status=%d loc: %s rem: %s", + __entry->iwdev, + __entry->caller, + __entry->cm_id, + __entry->cm_node, + __entry->refcount, + __entry->vlan_id, + __entry->accel, + parse_cm_state(__entry->state), + parse_iw_event_type(__entry->type), + __entry->status, + __print_ip_addr(__get_dynamic_array(laddr), + __entry->lport, __entry->ipv4), + __print_ip_addr(__get_dynamic_array(raddr), + __entry->rport, __entry->ipv4) + ) +); + +TRACE_EVENT(irdma_send_cm_event_no_node, + TP_PROTO(struct iw_cm_id *cm_id, enum iw_cm_event_type type, + int status, void *caller), + TP_ARGS(cm_id, type, status, caller), + TP_STRUCT__entry(__field(struct iw_cm_id *, cm_id) + __field(enum iw_cm_event_type, type) + __field(int, status) + __field(void *, caller) + ), + TP_fast_assign(__entry->cm_id = cm_id; + __entry->type = type; + __entry->status = status; + __entry->caller = caller; + ), + TP_printk("cm_id=%p caller=%pS event_type=%s status=%d", + __entry->cm_id, + __entry->caller, + parse_iw_event_type(__entry->type), + __entry->status + ) +); + +DECLARE_EVENT_CLASS(cm_node_template, + TP_PROTO(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type, void *caller), + TP_ARGS(cm_node, type, caller), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __field(struct irdma_cm_node *, cm_node) + __field(u32, refcount) + __field(u16, lport) + __field(u16, rport) + __field(enum irdma_cm_node_state, state) + __field(bool, ipv4) + __field(u16, vlan_id) + __field(int, accel) + __field(enum irdma_cm_event_type, type) + __field(void *, caller) + __dynamic_array(u32, laddr, 4) + __dynamic_array(u32, raddr, 4) + ), + TP_fast_assign(__entry->iwdev = cm_node->iwdev; + __entry->cm_node = cm_node; + __entry->refcount = refcount_read(&cm_node->refcnt); + __entry->state = cm_node->state; + __entry->lport = cm_node->loc_port; + __entry->rport = cm_node->rem_port; + __entry->ipv4 = cm_node->ipv4; + __entry->vlan_id = cm_node->vlan_id; + __entry->accel = cm_node->accelerated; + __entry->type = type; + __entry->caller = caller; + memcpy(__get_dynamic_array(laddr), + cm_node->loc_addr, 4); + memcpy(__get_dynamic_array(raddr), + cm_node->rem_addr, 4); + ), + TP_printk("iwdev=%p caller=%pS node=%p refcnt=%d vlan_id=%d accel=%d state=%s event_type=%s loc: %s rem: %s", + __entry->iwdev, + __entry->caller, + __entry->cm_node, + __entry->refcount, + __entry->vlan_id, + __entry->accel, + parse_cm_state(__entry->state), + parse_cm_event_type(__entry->type), + __print_ip_addr(__get_dynamic_array(laddr), + __entry->lport, __entry->ipv4), + __print_ip_addr(__get_dynamic_array(raddr), + __entry->rport, __entry->ipv4) + ) +); + +DEFINE_EVENT(cm_node_template, irdma_create_event, + TP_PROTO(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type, void *caller), + TP_ARGS(cm_node, type, caller)); + +DEFINE_EVENT(cm_node_template, irdma_accept, + TP_PROTO(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type, void *caller), + TP_ARGS(cm_node, type, caller)); + +DEFINE_EVENT(cm_node_template, irdma_connect, + TP_PROTO(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type, void *caller), + TP_ARGS(cm_node, type, caller)); + +DEFINE_EVENT(cm_node_template, irdma_reject, + TP_PROTO(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type, void *caller), + TP_ARGS(cm_node, type, caller)); + +DEFINE_EVENT(cm_node_template, irdma_find_node, + TP_PROTO(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type, void *caller), + TP_ARGS(cm_node, type, caller)); + +DEFINE_EVENT(cm_node_template, irdma_send_reset, + TP_PROTO(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type, void *caller), + TP_ARGS(cm_node, type, caller)); + +DEFINE_EVENT(cm_node_template, irdma_rem_ref_cm_node, + TP_PROTO(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type, void *caller), + TP_ARGS(cm_node, type, caller)); + +DEFINE_EVENT(cm_node_template, irdma_cm_event_handler, + TP_PROTO(struct irdma_cm_node *cm_node, + enum irdma_cm_event_type type, void *caller), + TP_ARGS(cm_node, type, caller)); + +TRACE_EVENT(open_err_template, + TP_PROTO(struct irdma_cm_node *cm_node, bool reset, void *caller), + TP_ARGS(cm_node, reset, caller), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __field(struct irdma_cm_node *, cm_node) + __field(enum irdma_cm_node_state, state) + __field(bool, reset) + __field(void *, caller) + ), + TP_fast_assign(__entry->iwdev = cm_node->iwdev; + __entry->cm_node = cm_node; + __entry->state = cm_node->state; + __entry->reset = reset; + __entry->caller = caller; + ), + TP_printk("iwdev=%p caller=%pS node%p reset=%d state=%s", + __entry->iwdev, + __entry->caller, + __entry->cm_node, + __entry->reset, + parse_cm_state(__entry->state) + ) +); + +DEFINE_EVENT(open_err_template, irdma_active_open_err, + TP_PROTO(struct irdma_cm_node *cm_node, bool reset, void *caller), + TP_ARGS(cm_node, reset, caller)); + +DEFINE_EVENT(open_err_template, irdma_passive_open_err, + TP_PROTO(struct irdma_cm_node *cm_node, bool reset, void *caller), + TP_ARGS(cm_node, reset, caller)); + +DECLARE_EVENT_CLASS(cm_node_ah_template, + TP_PROTO(struct irdma_cm_node *cm_node), + TP_ARGS(cm_node), + TP_STRUCT__entry(__field(struct irdma_device *, iwdev) + __field(struct irdma_cm_node *, cm_node) + __field(struct irdma_sc_ah *, ah) + __field(u32, refcount) + __field(u16, lport) + __field(u16, rport) + __field(enum irdma_cm_node_state, state) + __field(bool, ipv4) + __field(u16, vlan_id) + __field(int, accel) + __dynamic_array(u32, laddr, 4) + __dynamic_array(u32, raddr, 4) + ), + TP_fast_assign(__entry->iwdev = cm_node->iwdev; + __entry->cm_node = cm_node; + __entry->ah = cm_node->ah; + __entry->refcount = refcount_read(&cm_node->refcnt); + __entry->lport = cm_node->loc_port; + __entry->rport = cm_node->rem_port; + __entry->state = cm_node->state; + __entry->ipv4 = cm_node->ipv4; + __entry->vlan_id = cm_node->vlan_id; + __entry->accel = cm_node->accelerated; + memcpy(__get_dynamic_array(laddr), + cm_node->loc_addr, 4); + memcpy(__get_dynamic_array(raddr), + cm_node->rem_addr, 4); + ), + TP_printk("iwdev=%p node=%p ah=%p refcnt=%d vlan_id=%d accel=%d state=%s loc: %s rem: %s", + __entry->iwdev, + __entry->cm_node, + __entry->ah, + __entry->refcount, + __entry->vlan_id, + __entry->accel, + parse_cm_state(__entry->state), + __print_ip_addr(__get_dynamic_array(laddr), + __entry->lport, __entry->ipv4), + __print_ip_addr(__get_dynamic_array(raddr), + __entry->rport, __entry->ipv4) + ) +); + +DEFINE_EVENT(cm_node_ah_template, irdma_cm_free_ah, + TP_PROTO(struct irdma_cm_node *cm_node), + TP_ARGS(cm_node)); + +DEFINE_EVENT(cm_node_ah_template, irdma_create_ah, + TP_PROTO(struct irdma_cm_node *cm_node), + TP_ARGS(cm_node)); + +#endif /* __TRACE_CM_H */ + +#undef TRACE_INCLUDE_PATH +#undef TRACE_INCLUDE_FILE +#define TRACE_INCLUDE_PATH . +#define TRACE_INCLUDE_FILE trace_cm +#include diff --git a/drivers/intel/irdma-1.14.33/src/irdma/type.h b/drivers/intel/irdma-1.14.33/src/irdma/type.h new file mode 100644 index 000000000..f63ec8e20 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/type.h @@ -0,0 +1,1807 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef IRDMA_TYPE_H +#define IRDMA_TYPE_H + +#include "osdep.h" + +#include "irdma.h" +#include "user.h" +#include "hmc.h" +#include "uda.h" +#include "ws.h" +#include "virtchnl.h" +#include "pble.h" + +#define IRDMA_DEBUG_ERR "ERR" +#define IRDMA_DEBUG_INIT "INIT" +#define IRDMA_DEBUG_DEV "DEV" +#define IRDMA_DEBUG_CM "CM" +#define IRDMA_DEBUG_VERBS "VERBS" +#define IRDMA_DEBUG_PUDA "PUDA" +#define IRDMA_DEBUG_ILQ "ILQ" +#define IRDMA_DEBUG_IEQ "IEQ" +#define IRDMA_DEBUG_QP "QP" +#define IRDMA_DEBUG_CQ "CQ" +#define IRDMA_DEBUG_MR "MR" +#define IRDMA_DEBUG_PBLE "PBLE" +#define IRDMA_DEBUG_WQE "WQE" +#define IRDMA_DEBUG_AEQ "AEQ" +#define IRDMA_DEBUG_CQP "CQP" +#define IRDMA_DEBUG_HMC "HMC" +#define IRDMA_DEBUG_USER "USER" +#define IRDMA_DEBUG_VIRT "VIRT" +#define IRDMA_DEBUG_DCB "DCB" +#define IRDMA_DEBUG_CQE "CQE" +#define IRDMA_DEBUG_CLNT "CLNT" +#define IRDMA_DEBUG_WS "WS" +#define IRDMA_DEBUG_STATS "STATS" + +#define RSVD_OFFSET 0xFFFFFFFF + +enum irdma_page_size { + IRDMA_PAGE_SIZE_4K = 0, + IRDMA_PAGE_SIZE_2M, + IRDMA_PAGE_SIZE_1G, +}; + +enum irdma_hdrct_flags { + DDP_LEN_FLAG = 0x80, + DDP_HDR_FLAG = 0x40, + RDMA_HDR_FLAG = 0x20, +}; + +enum irdma_term_layers { + LAYER_RDMA = 0, + LAYER_DDP = 1, + LAYER_MPA = 2, +}; + +enum irdma_term_error_types { + RDMAP_REMOTE_PROT = 1, + RDMAP_REMOTE_OP = 2, + DDP_CATASTROPHIC = 0, + DDP_TAGGED_BUF = 1, + DDP_UNTAGGED_BUF = 2, + DDP_LLP = 3, +}; + +enum irdma_term_rdma_errors { + RDMAP_INV_STAG = 0x00, + RDMAP_INV_BOUNDS = 0x01, + RDMAP_ACCESS = 0x02, + RDMAP_UNASSOC_STAG = 0x03, + RDMAP_TO_WRAP = 0x04, + RDMAP_INV_RDMAP_VER = 0x05, + RDMAP_UNEXPECTED_OP = 0x06, + RDMAP_CATASTROPHIC_LOCAL = 0x07, + RDMAP_CATASTROPHIC_GLOBAL = 0x08, + RDMAP_CANT_INV_STAG = 0x09, + RDMAP_UNSPECIFIED = 0xff, +}; + +enum irdma_term_ddp_errors { + DDP_CATASTROPHIC_LOCAL = 0x00, + DDP_TAGGED_INV_STAG = 0x00, + DDP_TAGGED_BOUNDS = 0x01, + DDP_TAGGED_UNASSOC_STAG = 0x02, + DDP_TAGGED_TO_WRAP = 0x03, + DDP_TAGGED_INV_DDP_VER = 0x04, + DDP_UNTAGGED_INV_QN = 0x01, + DDP_UNTAGGED_INV_MSN_NO_BUF = 0x02, + DDP_UNTAGGED_INV_MSN_RANGE = 0x03, + DDP_UNTAGGED_INV_MO = 0x04, + DDP_UNTAGGED_INV_TOO_LONG = 0x05, + DDP_UNTAGGED_INV_DDP_VER = 0x06, +}; + +enum irdma_term_mpa_errors { + MPA_CLOSED = 0x01, + MPA_CRC = 0x02, + MPA_MARKER = 0x03, + MPA_REQ_RSP = 0x04, +}; + +enum irdma_hw_stats_index { + /* gen1 - 32-bit */ + IRDMA_HW_STAT_INDEX_IP4RXDISCARD = 0, + IRDMA_HW_STAT_INDEX_IP4RXTRUNC = 1, + IRDMA_HW_STAT_INDEX_IP4TXNOROUTE = 2, + IRDMA_HW_STAT_INDEX_IP6RXDISCARD = 3, + IRDMA_HW_STAT_INDEX_IP6RXTRUNC = 4, + IRDMA_HW_STAT_INDEX_IP6TXNOROUTE = 5, + IRDMA_HW_STAT_INDEX_TCPRTXSEG = 6, + IRDMA_HW_STAT_INDEX_TCPRXOPTERR = 7, + IRDMA_HW_STAT_INDEX_TCPRXPROTOERR = 8, + IRDMA_HW_STAT_INDEX_RXVLANERR = 9, + /* gen1 - 64-bit */ + IRDMA_HW_STAT_INDEX_IP4RXOCTS = 10, + IRDMA_HW_STAT_INDEX_IP4RXPKTS = 11, + IRDMA_HW_STAT_INDEX_IP4RXFRAGS = 12, + IRDMA_HW_STAT_INDEX_IP4RXMCPKTS = 13, + IRDMA_HW_STAT_INDEX_IP4TXOCTS = 14, + IRDMA_HW_STAT_INDEX_IP4TXPKTS = 15, + IRDMA_HW_STAT_INDEX_IP4TXFRAGS = 16, + IRDMA_HW_STAT_INDEX_IP4TXMCPKTS = 17, + IRDMA_HW_STAT_INDEX_IP6RXOCTS = 18, + IRDMA_HW_STAT_INDEX_IP6RXPKTS = 19, + IRDMA_HW_STAT_INDEX_IP6RXFRAGS = 20, + IRDMA_HW_STAT_INDEX_IP6RXMCPKTS = 21, + IRDMA_HW_STAT_INDEX_IP6TXOCTS = 22, + IRDMA_HW_STAT_INDEX_IP6TXPKTS = 23, + IRDMA_HW_STAT_INDEX_IP6TXFRAGS = 24, + IRDMA_HW_STAT_INDEX_IP6TXMCPKTS = 25, + IRDMA_HW_STAT_INDEX_TCPRXSEGS = 26, + IRDMA_HW_STAT_INDEX_TCPTXSEG = 27, + IRDMA_HW_STAT_INDEX_RDMARXRDS = 28, + IRDMA_HW_STAT_INDEX_RDMARXSNDS = 29, + IRDMA_HW_STAT_INDEX_RDMARXWRS = 30, + IRDMA_HW_STAT_INDEX_RDMATXRDS = 31, + IRDMA_HW_STAT_INDEX_RDMATXSNDS = 32, + IRDMA_HW_STAT_INDEX_RDMATXWRS = 33, + IRDMA_HW_STAT_INDEX_RDMAVBND = 34, + IRDMA_HW_STAT_INDEX_RDMAVINV = 35, + IRDMA_HW_STAT_INDEX_IP4RXMCOCTS = 36, + IRDMA_HW_STAT_INDEX_IP4TXMCOCTS = 37, + IRDMA_HW_STAT_INDEX_IP6RXMCOCTS = 38, + IRDMA_HW_STAT_INDEX_IP6TXMCOCTS = 39, + IRDMA_HW_STAT_INDEX_UDPRXPKTS = 40, + IRDMA_HW_STAT_INDEX_UDPTXPKTS = 41, + IRDMA_HW_STAT_INDEX_MAX_GEN_1 = 42, /* Must be same value as next entry */ + + /* gen2 - 64-bit */ + IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS = 42, + + /* gen2 - 32-bit */ + IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED = 43, + IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED = 44, + IRDMA_HW_STAT_INDEX_TXNPCNPSENT = 45, + IRDMA_HW_STAT_INDEX_MAX_GEN_2 = 46, + + /* gen3 */ + IRDMA_HW_STAT_INDEX_RNR_SENT = 46, + IRDMA_HW_STAT_INDEX_RNR_RCVD = 47, + IRDMA_HW_STAT_INDEX_RDMAORDLMTCNT = 48, + IRDMA_HW_STAT_INDEX_RDMAIRDLMTCNT = 49, + IRDMA_HW_STAT_INDEX_RDMARXATS = 50, + IRDMA_HW_STAT_INDEX_RDMATXATS = 51, + IRDMA_HW_STAT_INDEX_NAKSEQERR = 52, + IRDMA_HW_STAT_INDEX_NAKSEQERR_IMPLIED = 53, + IRDMA_HW_STAT_INDEX_RTO = 54, + IRDMA_HW_STAT_INDEX_RXOOOPKTS = 55, + IRDMA_HW_STAT_INDEX_ICRCERR = 56, + IRDMA_HW_STAT_INDEX_RDMARXFLUSH = 57, + IRDMA_HW_STAT_INDEX_RDMATXFLUSH = 58, + IRDMA_HW_STAT_INDEX_RDMARXATOMICWRITE = 59, + IRDMA_HW_STAT_INDEX_RDMATXATOMICWRITE = 60, + IRDMA_HW_STAT_INDEX_MAX_GEN_3 = 61, +}; + +#define IRDMA_MIN_FEATURES 2 + +enum irdma_feature_type { + IRDMA_FEATURE_FW_INFO = 0, + IRDMA_HW_VERSION_INFO = 1, + IRDMA_QP_MAX_INCR = 2, + IRDMA_CQ_MAX_INCR = 3, + IRDMA_CEQ_MAX_INCR = 4, + IRDMA_SD_MAX_INCR = 5, + IRDMA_QP_SMALL = 6, + IRDMA_QP_MEDIUM = 7, + IRDMA_QP_LARGE = 8, + IRDMA_QP_XLARGE = 9, + IRDMA_CQ_SMALL = 10, + IRDMA_CQ_MEDIUM = 11, + IRDMA_CQ_LARGE = 12, + IRDMA_CQ_XLARGE = 13, + IRDMA_CEQ_SMALL = 14, + IRDMA_CEQ_MEDIUM = 15, + IRDMA_CEQ_LARGE = 16, + IRDMA_CEQ_XLARGE = 17, + IRDMA_SD_SMALL = 18, + IRDMA_SD_MEDIUM = 19, + IRDMA_SD_LARGE = 20, + IRDMA_SD_XLARGE = 21, + IRDMA_OBJ_1 = 22, + IRDMA_OBJ_2 = 23, + IRDMA_ENDPT_TRK = 24, + IRDMA_FTN_INLINE_MAX = 25, + IRDMA_QSETS_MAX = 26, + IRDMA_ASO = 27, + /* this indicates if atomics are allowed */ + IRDMA_FTN_FLAGS = 32, + IRDMA_FTN_NOP = 33, + IRDMA_MAX_FEATURES, /* Must be last entry */ +}; + +enum irdma_sched_prio_type { + IRDMA_PRIO_WEIGHTED_RR = 1, + IRDMA_PRIO_STRICT = 2, + IRDMA_PRIO_WEIGHTED_STRICT = 3, +}; + +enum irdma_vm_vf_type { + IRDMA_VF_TYPE = 0, + IRDMA_VM_TYPE, + IRDMA_PF_TYPE, +}; + +enum irdma_cqp_hmc_profile { + IRDMA_HMC_PROFILE_DEFAULT = 1, + IRDMA_HMC_PROFILE_FAVOR_VF = 2, + IRDMA_HMC_PROFILE_EQUAL = 3, +}; + +enum irdma_quad_entry_type { + IRDMA_QHASH_TYPE_TCP_ESTABLISHED = 1, + IRDMA_QHASH_TYPE_TCP_SYN, + IRDMA_QHASH_TYPE_UDP_UNICAST, + IRDMA_QHASH_TYPE_UDP_MCAST, + IRDMA_QHASH_TYPE_ROCE_MCAST, + IRDMA_QHASH_TYPE_ROCEV2_HW, +}; + +enum irdma_quad_hash_manage_type { + IRDMA_QHASH_MANAGE_TYPE_DELETE = 0, + IRDMA_QHASH_MANAGE_TYPE_ADD, + IRDMA_QHASH_MANAGE_TYPE_MODIFY, +}; + +enum irdma_syn_rst_handling { + IRDMA_SYN_RST_HANDLING_HW_TCP_SECURE = 0, + IRDMA_SYN_RST_HANDLING_HW_TCP, + IRDMA_SYN_RST_HANDLING_FW_TCP_SECURE, + IRDMA_SYN_RST_HANDLING_FW_TCP, +}; + +enum irdma_queue_type { + IRDMA_QUEUE_TYPE_SQ_RQ = 0, + IRDMA_QUEUE_TYPE_CQP, + IRDMA_QUEUE_TYPE_SRQ, +}; + +struct irdma_sc_dev; +struct irdma_vsi_pestat; + +struct irdma_dcqcn_cc_params { + u8 cc_cfg_valid; + u8 min_dec_factor; + u8 min_rate; + u8 dcqcn_f; + u16 rai_factor; + u16 hai_factor; + u16 dcqcn_t; + u32 dcqcn_b; + u32 rreduce_mperiod; +}; + +struct irdma_cqp_init_info { + u64 cqp_compl_ctx; + u64 host_ctx_pa; + u64 sq_pa; + struct irdma_sc_dev *dev; + struct irdma_cqp_quanta *sq; + struct irdma_dcqcn_cc_params dcqcn_params; + __le64 *host_ctx; + u64 *scratch_array; + u32 sq_size; + struct irdma_ooo_cqp_op *ooo_op_array; + u32 pe_en_vf_cnt; + u16 hw_maj_ver; + u16 hw_min_ver; + u8 struct_ver; + u8 hmc_profile; + u8 ena_vf_count; + u8 ceqs_per_vf; + u8 ooisc_blksize; + u8 rrsp_blksize; + u8 q1_blksize; + u8 xmit_blksize; + u8 ts_override; + u8 ts_shift; + u8 en_fine_grained_timers; + u8 blksizes_valid; + bool en_datacenter_tcp:1; + bool disable_packed:1; + bool rocev2_rto_policy:1; + bool en_rem_endpoint_trk:1; + enum irdma_protocol_used protocol_used; +}; + +struct irdma_terminate_hdr { + u8 layer_etype; + u8 error_code; + u8 hdrct; + u8 rsvd; +}; + +struct irdma_cqp_sq_wqe { + __le64 buf[IRDMA_CQP_WQE_SIZE]; +}; + +struct irdma_sc_aeqe { + __le64 buf[IRDMA_AEQE_SIZE]; +}; + +struct irdma_ceqe { + __le64 buf[IRDMA_CEQE_SIZE]; +}; + +struct irdma_cqp_ctx { + __le64 buf[IRDMA_CQP_CTX_SIZE]; +}; + +struct irdma_cq_shadow_area { + __le64 buf[IRDMA_SHADOW_AREA_SIZE]; +}; + +struct irdma_dev_hw_stats_offsets { + u32 stats_offset[IRDMA_HW_STAT_INDEX_MAX_GEN_1]; +}; + +struct irdma_dev_hw_stats { + u64 stats_val[IRDMA_GATHER_STATS_BUF_SIZE / sizeof(u64)]; +}; + +struct irdma_gather_stats { + u64 val[IRDMA_GATHER_STATS_BUF_SIZE / sizeof(u64)]; +}; + +struct irdma_hw_stat_map { + u16 byteoff; + u8 bitoff; + u64 bitmask; +}; + +struct irdma_stats_gather_info { + bool use_hmc_fcn_index:1; + bool use_stats_inst:1; + u16 hmc_fcn_index; + u16 stats_inst_index; + struct irdma_dma_mem stats_buff_mem; + void *gather_stats_va; + void *last_gather_stats_va; +}; + +struct irdma_vsi_pestat { + struct irdma_hw *hw; + struct irdma_dev_hw_stats hw_stats; + struct irdma_stats_gather_info gather_info; + struct timer_list stats_timer; + struct irdma_sc_vsi *vsi; + spinlock_t lock; /* rdma stats lock */ +}; + +struct irdma_hw { + u8 __iomem *hw_addr; + u8 __iomem *priv_hw_addr; + struct device *device; + struct irdma_hmc_info hmc; +}; + +struct irdma_pfpdu { + struct list_head rxlist; + u32 rcv_nxt; + u32 fps; + u32 max_fpdu_data; + u32 nextseqnum; + u32 rcv_start_seq; + bool mode:1; + bool mpa_crc_err:1; + u8 marker_len; + u64 total_ieq_bufs; + u64 fpdu_processed; + u64 bad_seq_num; + u64 crc_err; + u64 no_tx_bufs; + u64 tx_err; + u64 out_of_order; + u64 pmode_count; + struct irdma_sc_ah *ah; + struct irdma_puda_buf *ah_buf; + spinlock_t lock; /* fpdu processing lock */ + struct irdma_puda_buf *lastrcv_buf; +}; + +struct irdma_sc_pd { + struct irdma_sc_dev *dev; + u32 pd_id; + int abi_ver; +}; + +struct irdma_cqp_quanta { + __le64 elem[IRDMA_CQP_WQE_SIZE]; +}; + +struct irdma_ooo_cqp_op { + struct list_head list_entry; + u64 scratch; + u32 def_info; + u32 sw_def_info; + u32 wqe_idx; + bool deferred:1; +}; + +struct irdma_sc_cqp { + spinlock_t ooo_list_lock; /* protects list of pending completions */ + struct list_head ooo_avail; + struct list_head ooo_pnd; + u32 last_def_cmpl_ticket; + u32 sw_def_cmpl_ticket; + u32 size; + u64 sq_pa; + u64 host_ctx_pa; + void *back_cqp; + struct irdma_sc_dev *dev; + int (*process_cqp_sds)(struct irdma_sc_dev *dev, + struct irdma_update_sds_info *info); + struct irdma_dma_mem sdbuf; + struct irdma_ring sq_ring; + struct irdma_cqp_quanta *sq_base; + struct irdma_dcqcn_cc_params dcqcn_params; + __le64 *host_ctx; + u64 *scratch_array; + u64 requested_ops; + atomic64_t completed_ops; + struct irdma_ooo_cqp_op *ooo_op_array; + u32 cqp_id; + u32 sq_size; + u32 pe_en_vf_cnt; + u32 hw_sq_size; + u16 hw_maj_ver; + u16 hw_min_ver; + u8 struct_ver; + u8 polarity; + u8 hmc_profile; + u8 ena_vf_count; + u8 timeout_count; + u8 ceqs_per_vf; + u8 ooisc_blksize; + u8 rrsp_blksize; + u8 q1_blksize; + u8 xmit_blksize; + u8 ts_override; + u8 ts_shift; + u8 en_fine_grained_timers; + u8 blksizes_valid; + bool en_datacenter_tcp:1; + bool disable_packed:1; + bool rocev2_rto_policy:1; + bool en_rem_endpoint_trk:1; + enum irdma_protocol_used protocol_used; +}; + +struct irdma_sc_aeq { + u32 size; + u64 aeq_elem_pa; + struct irdma_sc_dev *dev; + struct irdma_sc_aeqe *aeqe_base; + void *pbl_list; + u32 elem_cnt; + struct irdma_ring aeq_ring; + u8 pbl_chunk_size; + u32 first_pm_pbl_idx; + u32 msix_idx; + u8 polarity; + bool virtual_map:1; + bool pasid_valid:1; + u32 pasid; +}; + +struct irdma_sc_ceq { + u32 size; + u64 ceq_elem_pa; + struct irdma_sc_dev *dev; + struct irdma_ceqe *ceqe_base; + void *pbl_list; + u32 ceq_id; + u32 elem_cnt; + struct irdma_ring ceq_ring; + u8 pbl_chunk_size; + u8 tph_val; + u32 first_pm_pbl_idx; + u8 polarity; + struct irdma_sc_vsi *vsi; + bool virtual_map:1; + bool tph_en:1; + bool itr_no_expire:1; + bool pasid_valid:1; + u32 pasid; +}; + +struct irdma_sc_cq { + struct irdma_cq_uk cq_uk; + u64 cq_pa; + u64 shadow_area_pa; + struct irdma_sc_dev *dev; + struct irdma_sc_vsi *vsi; + void *pbl_list; + void *back_cq; + u32 ceq_id; + u32 shadow_read_threshold; + u8 pbl_chunk_size; + u8 cq_type; + u8 tph_val; + u32 first_pm_pbl_idx; + bool ceqe_mask:1; + bool virtual_map:1; + bool check_overflow:1; + bool ceq_id_valid:1; + bool tph_en:1; + bool pasid_valid:1; + u32 pasid; +}; + +struct irdma_sc_qp { + struct irdma_qp_uk qp_uk; + u64 sq_pa; + u64 rq_pa; + u64 hw_host_ctx_pa; + u64 shadow_area_pa; + u64 q2_pa; + struct irdma_sc_dev *dev; + struct irdma_sc_vsi *vsi; + struct irdma_sc_pd *pd; + __le64 *hw_host_ctx; + void *llp_stream_handle; + struct irdma_pfpdu pfpdu; + u32 ieq_qp; + u8 *q2_buf; + u64 qp_compl_ctx; + u32 push_idx; + u16 qs_handle; + u16 push_offset; + u8 flush_wqes_count; + u8 sq_tph_val; + u8 rq_tph_val; + u8 qp_state; + u8 hw_sq_size; + u8 hw_rq_size; + u8 src_mac_addr_idx; + u8 qs_idx; + bool on_qoslist:1; + bool ieq_pass_thru:1; + bool sq_tph_en:1; + bool rq_tph_en:1; + bool rcv_tph_en:1; + bool xmit_tph_en:1; + bool virtual_map:1; + bool flush_sq:1; + bool flush_rq:1; + bool err_sq_idx_valid:1; + bool pasid_valid:1; + u32 pasid; + u32 pkt_limit; + u32 err_sq_idx; + bool sq_flush_code:1; + bool rq_flush_code:1; + enum irdma_flush_opcode flush_code; + enum irdma_qp_event_type event_type; + u8 term_flags; + u8 user_pri; + struct list_head list; +}; + +struct irdma_stats_inst_info { + u16 hmc_fn_id; + u16 stats_idx; + bool use_hmc_fcn_index:1; +}; + +struct irdma_up_info { + u8 map[8]; + u8 cnp_up_override; + u16 hmc_fcn_idx; + bool use_vlan:1; + bool use_cnp_up_override:1; +}; + +#define IRDMA_MAX_WS_NODES 0x3FF +#define IRDMA_WS_NODE_INVALID 0xFFFF + +struct irdma_ws_move_node_info { + u16 node_id[16]; + u8 num_nodes; + u8 target_port; + bool resume_traffic:1; +}; + +struct irdma_ws_node_info { + u16 id; + u16 vsi; + u16 parent_id; + u16 qs_handle; + bool type_leaf:1; + bool enable:1; + u8 prio_type; + u8 tc; + u8 weight; + u8 failing_port; + u8 active_port; + bool assign_to_active_port:1; + + enum irdma_ws_op_type ws_op_type; + u32 lng_id; + u32 rate; + u8 rate_limit_flags; + u8 port_num; + bool lossless_tc:1; +}; + +struct irdma_hmc_fpm_misc { + u32 max_ceqs; + u32 max_sds; + u32 loc_mem_pages; + u32 xf_block_size; + u32 q1_block_size; + u32 ht_multiplier; + u32 timer_bucket; + u32 rrf_block_size; + u32 ooiscf_block_size; +}; + +struct irdma_vchnl_if { + int (*vchnl_recv)(struct irdma_sc_dev *dev, u16 vf_id, u8 *msg, + u16 len); +}; + +#define IRDMA_VCHNL_MAX_MSG_SIZE 512 +#define IRDMA_LEAF_DEFAULT_REL_BW 64 +#define IRDMA_PARENT_DEFAULT_REL_BW 1 + +struct irdma_qos { + struct list_head qplist; + struct mutex qos_mutex; /* protect QoS attributes per QoS level */ + u32 l2_sched_node_id[2]; + u16 qs_handle[2]; + u8 traffic_class; + u8 rel_bw; + u8 prio_type; + bool valid:1; +}; + +struct irdma_config_check { + bool config_ok:1; + bool lfc_set:1; + bool pfc_set:1; + u8 traffic_class; + u16 qs_handle; +}; + +struct irdma_vchnl_dev { + struct irdma_sc_dev *pf_dev; + struct irdma_sc_vsi *vf_vsi; + u8 *hmc_info_mem; + u8 vchnl_msg_buf[IRDMA_VCHNL_MAX_MSG_SIZE]; + struct irdma_hmc_info hmc_info; + struct irdma_hmc_fpm_misc hmc_fpm_misc; + u64 fpm_query_buf_pa; + u64 *fpm_query_buf; + refcount_t refcnt; + u16 pmf_index; + u16 vf_id; + u16 iw_vf_idx; + u8 protocol_used; + bool stats_initialized:1; + bool pf_hmc_initialized:1; + bool reset_en:1; + bool port_vlan_en:1; +}; + +#define IRDMA_INVALID_STATS_IDX 0xff +struct irdma_sc_vsi { + u16 vsi_idx; + struct irdma_sc_dev *dev; + struct irdma_vchnl_dev *vc_dev; + void *back_vsi; + u32 ilq_count; + struct irdma_virt_mem ilq_mem; + struct irdma_puda_rsrc *ilq; + u32 ieq_count; + struct irdma_virt_mem ieq_mem; + struct irdma_puda_rsrc *ieq; + u32 exception_lan_q; + u16 mtu; + u16 vf_id; + enum irdma_vm_vf_type vm_vf_type; + bool stats_inst_alloc:1; + bool tc_change_pending:1; + bool mtu_change_pending:1; + bool failover_pending:1; + bool lag_aa:1; +#define IRDMA_LAG_PRIMARY_IDX 0 +#define IRDMA_LAG_SECONDARY_IDX 1 + u8 lag_ports[2]; /* Ports in LAG AA */ + u8 lag_port_bitmap; /* bitmap of port's link on active-active bond */ + atomic_t port1_qp_cnt; + atomic_t port2_qp_cnt; + u16 primary_port_node_ids[IRDMA_MAX_USER_PRIORITY]; /* node ID's assigned to primary port */ + u16 secondary_port_node_ids[IRDMA_MAX_USER_PRIORITY]; /* node ID's assigned to secondary port */ + bool primary_port_migrated:1; /* true means primary port nodes have been moved to secondary port */ + bool secondary_port_migrated:1; /* true means secondary port nodes have been moved to primary port */ + struct irdma_vsi_pestat *pestat; + atomic_t qp_suspend_reqs; + int (*register_qset)(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node1, + struct irdma_ws_node *tc_node2); + void (*unregister_qset)(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node1, + struct irdma_ws_node *tc_node2); + struct irdma_config_check cfg_check[IRDMA_MAX_USER_PRIORITY]; + bool tc_print_warning[IEEE_8021QAZ_MAX_TCS]; + u8 qos_rel_bw; + u8 qos_prio_type; + u16 stats_idx; + u8 dscp_map[IRDMA_DSCP_NUM_VAL]; + struct irdma_qos qos[IRDMA_MAX_USER_PRIORITY]; + u64 hw_stats_regs[IRDMA_HW_STAT_INDEX_MAX_GEN_1]; + bool dscp_mode:1; +}; + +struct irdma_sc_dev { + struct list_head cqp_cmd_head; /* head of the CQP command list */ + spinlock_t cqp_lock; /* protect CQP list access */ + bool stats_idx_array[IRDMA_MAX_STATS_COUNT_GEN1]; + struct irdma_dma_mem vf_fpm_query_buf[IRDMA_MAX_PE_ENA_VF_COUNT]; + u64 fpm_query_buf_pa; + u64 fpm_commit_buf_pa; + __le64 *fpm_query_buf; + __le64 *fpm_commit_buf; + struct irdma_hw *hw; + u32 __iomem *wqe_alloc_db; + u32 __iomem *cq_arm_db; + u32 __iomem *aeq_alloc_db; + u32 __iomem *cqp_db; + u32 __iomem *cq_ack_db; + u32 __iomem *hw_regs[IRDMA_MAX_REGS]; + u32 ceq_itr; /* Interrupt throttle, usecs between interrupts: 0 disabled. 2 - 8160 */ + u64 hw_masks[IRDMA_MAX_MASKS]; + u8 hw_shifts[IRDMA_MAX_SHIFTS]; + const struct irdma_hw_stat_map *hw_stats_map; + u64 hw_stats_regs[IRDMA_HW_STAT_INDEX_MAX_GEN_1]; + u64 hw_stats_vf_regs[IRDMA_HW_STAT_INDEX_MAX_GEN_1]; + u64 feature_info[IRDMA_MAX_FEATURES]; + u64 cqp_cmd_stats[IRDMA_MAX_CQP_OPS]; + struct irdma_hw_attrs hw_attrs; + struct irdma_hmc_info *hmc_info; + struct irdma_vchnl_if *vchnl_if; + struct irdma_vchnl_rdma_caps vc_caps; + u8 vc_recv_buf[IRDMA_VCHNL_MAX_MSG_SIZE]; + u16 vc_recv_len; + struct irdma_vchnl_dev *vc_dev[IRDMA_MAX_PE_ENA_VF_COUNT]; + spinlock_t vc_dev_lock; /* sync vchnl_dev usage with async events like reset */ + struct workqueue_struct *vchnl_wq; + struct irdma_sc_cqp *cqp; + struct irdma_sc_aeq *aeq; + struct irdma_sc_ceq *ceq[IRDMA_CEQ_MAX_COUNT]; + struct irdma_sc_cq *ccq; + const struct irdma_irq_ops *irq_ops; + struct irdma_qos qos[IRDMA_MAX_USER_PRIORITY]; + struct irdma_hmc_fpm_misc hmc_fpm_misc; + struct irdma_ws_node *ws_tree_root; + struct mutex ws_mutex; /* ws tree mutex */ + u32 vchnl_ver; + u16 num_vfs; + u16 hmc_fn_id; + u8 vf_id; + bool privileged:1; + bool vchnl_up:1; + bool ceq_valid:1; + bool is_pf:1; + bool double_vlan_en:1; + u8 protocol_used; + struct mutex vchnl_mutex; + int (*ws_add)(struct irdma_sc_vsi *vsi, u8 user_pri); + void (*ws_remove)(struct irdma_sc_vsi *vsi, u8 user_pri); + void (*ws_reset)(struct irdma_sc_vsi *vsi); +}; + +struct irdma_modify_cq_info { + u64 cq_pa; + struct irdma_cqe *cq_base; + u32 cq_size; + u32 shadow_read_threshold; + u8 pbl_chunk_size; + u32 first_pm_pbl_idx; + bool virtual_map:1; + bool check_overflow:1; + bool cq_resize:1; +}; + +struct irdma_srq_init_info { + struct irdma_sc_pd *pd; + struct irdma_sc_vsi *vsi; + u64 srq_pa; + u64 shadow_area_pa; + u32 first_pm_pbl_idx; + u32 pasid; + u32 srq_size; + u16 srq_limit; + u8 pasid_valid; + u8 wqe_size; + u8 leaf_pbl_size; + u8 virtual_map; + u8 tph_en; + u8 arm_limit_event; + u8 tph_value; + u8 pbl_chunk_size; + struct irdma_srq_uk_init_info srq_uk_init_info; +}; + +struct irdma_sc_srq { + struct irdma_sc_dev *dev; + struct irdma_sc_vsi *vsi; + struct irdma_sc_pd *pd; + struct irdma_srq_uk srq_uk; + void *back_srq; + u64 srq_pa; + u64 shadow_area_pa; + u32 first_pm_pbl_idx; + u32 pasid; + u32 hw_srq_size; + u16 srq_limit; + u8 pasid_valid; + u8 leaf_pbl_size; + u8 virtual_map; + u8 tph_en; + u8 arm_limit_event; + u8 tph_val; +}; + +struct irdma_modify_srq_info { + u16 srq_limit; + u8 arm_limit_event; +}; + +struct irdma_set_interrupt_info { + u32 hmc_fcn_id; + u32 ceq_agent_interrupt_index; + u32 ceq_id; + u32 aeq_agent_interrupt_index; + u8 use_hmc_fcn_id; + u8 set_ceq_int; + u8 set_aeq_int; + u8 enable_int; +}; + +struct irdma_create_qp_info { + bool ord_valid:1; + bool tcp_ctx_valid:1; + bool cq_num_valid:1; + bool arp_cache_idx_valid:1; + bool mac_valid:1; + bool force_lpb:1; + u8 next_iwarp_state; +}; + +struct irdma_modify_qp_info { + u64 rx_win0; + u64 rx_win1; + u16 new_mss; + u8 next_iwarp_state; + u8 curr_iwarp_state; + u8 termlen; + bool ord_valid:1; + bool tcp_ctx_valid:1; + bool udp_ctx_valid:1; + bool cq_num_valid:1; + bool arp_cache_idx_valid:1; + bool reset_tcp_conn:1; + bool remove_hash_idx:1; + bool dont_send_term:1; + bool dont_send_fin:1; + bool cached_var_valid:1; + bool mss_change:1; + bool force_lpb:1; + bool mac_valid:1; +}; + +struct irdma_ccq_cqe_info { + struct irdma_sc_cqp *cqp; + u64 scratch; + u32 op_ret_val; + u16 maj_err_code; + u16 min_err_code; + u8 op_code; + bool error:1; + bool pending:1; +}; + +struct irdma_qos_tc_info { + u64 tc_ctx; + u8 rel_bw; + u8 prio_type; + u8 egress_virt_up; + u8 ingress_virt_up; +}; + +struct irdma_l2params { + struct irdma_qos_tc_info tc_info[IRDMA_MAX_USER_PRIORITY]; + u32 num_apps; + u16 qs_handle_list[IRDMA_MAX_USER_PRIORITY]; + u16 mtu; + u8 up2tc[IRDMA_MAX_USER_PRIORITY]; + u8 dscp_map[IRDMA_DSCP_NUM_VAL]; + u8 num_tc; + u8 vsi_rel_bw; + u8 vsi_prio_type; + bool mtu_changed:1; + bool tc_changed:1; + bool dscp_mode:1; +}; + +struct irdma_vsi_init_info { + struct irdma_sc_dev *dev; + void *back_vsi; + struct irdma_l2params *params; + u16 exception_lan_q; + u16 pf_data_vsi_num; + enum irdma_vm_vf_type vm_vf_type; + int (*register_qset)(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node1, + struct irdma_ws_node *tc_node2); + void (*unregister_qset)(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node1, + struct irdma_ws_node *tc_node2); + bool lag_aa:1; +}; + +struct irdma_vsi_stats_info { + struct irdma_vsi_pestat *pestat; + u8 fcn_id; + bool alloc_stats_inst:1; +}; + +struct irdma_device_init_info { + u64 fpm_query_buf_pa; + u64 fpm_commit_buf_pa; + __le64 *fpm_query_buf; + __le64 *fpm_commit_buf; + struct irdma_hw *hw; + void __iomem *bar0; + enum irdma_protocol_used protocol_used; + u16 max_vfs; + u16 hmc_fn_id; +}; + +struct irdma_ceq_init_info { + u64 ceqe_pa; + struct irdma_sc_dev *dev; + u64 *ceqe_base; + void *pbl_list; + u32 elem_cnt; + u32 ceq_id; + bool virtual_map:1; + bool tph_en:1; + bool itr_no_expire:1; + u8 pbl_chunk_size; + u8 tph_val; + u32 first_pm_pbl_idx; + struct irdma_sc_vsi *vsi; +}; + +struct irdma_aeq_init_info { + u64 aeq_elem_pa; + struct irdma_sc_dev *dev; + u32 *aeqe_base; + void *pbl_list; + u32 elem_cnt; + bool virtual_map:1; + u8 pbl_chunk_size; + u32 first_pm_pbl_idx; + u32 msix_idx; +}; + +struct irdma_ccq_init_info { + u64 cq_pa; + u64 shadow_area_pa; + struct irdma_sc_dev *dev; + struct irdma_cqe *cq_base; + __le64 *shadow_area; + void *pbl_list; + u32 num_elem; + u32 ceq_id; + u32 shadow_read_threshold; + bool ceqe_mask:1; + bool ceq_id_valid:1; + bool avoid_mem_cflct:1; + bool virtual_map:1; + bool tph_en:1; + u8 tph_val; + u8 pbl_chunk_size; + u32 first_pm_pbl_idx; + struct irdma_sc_vsi *vsi; +}; + +struct irdma_udp_offload_info { + bool ipv4:1; + bool insert_vlan_tag:1; + u8 ttl; + u8 tos; + u16 src_port; + u16 dst_port; + u32 dest_ip_addr[4]; + u32 snd_mss; + u16 vlan_tag; + u16 arp_idx; + u32 flow_label; + u8 udp_state; + u32 psn_nxt; + u32 lsn; + u32 epsn; + u32 psn_max; + u32 psn_una; + u32 local_ipaddr[4]; + u32 cwnd; + u8 rexmit_thresh; + u8 rnr_nak_thresh; + u8 rnr_nak_tmr; + u8 min_rnr_timer; +}; + +struct irdma_roce_offload_info { + u16 p_key; + u32 err_rq_idx; + u32 qkey; + u32 dest_qp; + u8 roce_tver; + u8 ack_credits; + u8 err_rq_idx_valid; + u32 pd_id; + u16 ord_size; + u16 ird_size; + bool is_qp1:1; + bool udprivcq_en:1; + bool dcqcn_en:1; + bool rcv_no_icrc:1; + bool wr_rdresp_en:1; + bool bind_en:1; + bool flush_mr:1; + bool fast_reg_en:1; + bool priv_mode_en:1; + bool rd_en:1; + bool timely_en:1; + bool dctcp_en:1; + bool fw_cc_enable:1; + bool use_stats_inst:1; + u8 local_ack_timeout; + u16 t_high; + u16 t_low; + u8 last_byte_sent; + u8 mac_addr[ETH_ALEN]; + u8 rtomin; +}; + +struct irdma_iwarp_offload_info { + u16 rcv_mark_offset; + u16 snd_mark_offset; + u8 ddp_ver; + u8 rdmap_ver; + u8 iwarp_mode; + u32 err_rq_idx; + u32 pd_id; + u16 ord_size; + u16 ird_size; + bool ib_rd_en:1; + bool align_hdrs:1; + bool rcv_no_mpa_crc:1; + bool err_rq_idx_valid:1; + bool snd_mark_en:1; + bool rcv_mark_en:1; + bool wr_rdresp_en:1; + bool fast_reg_en:1; + bool priv_mode_en:1; + bool rd_en:1; + bool timely_en:1; + bool use_stats_inst:1; + bool ecn_en:1; + bool dctcp_en:1; + u16 t_high; + u16 t_low; + u8 last_byte_sent; + u8 mac_addr[ETH_ALEN]; + u8 rtomin; +}; + +struct irdma_tcp_offload_info { + bool ipv4:1; + bool no_nagle:1; + bool insert_vlan_tag:1; + bool time_stamp:1; + bool drop_ooo_seg:1; + bool avoid_stretch_ack:1; + bool wscale:1; + bool ignore_tcp_opt:1; + bool ignore_tcp_uns_opt:1; + u8 cwnd_inc_limit; + u8 dup_ack_thresh; + u8 ttl; + u8 src_mac_addr_idx; + u8 tos; + u16 src_port; + u16 dst_port; + u32 dest_ip_addr[4]; + //u32 dest_ip_addr0; + //u32 dest_ip_addr1; + //u32 dest_ip_addr2; + //u32 dest_ip_addr3; + u32 snd_mss; + u16 syn_rst_handling; + u16 vlan_tag; + u16 arp_idx; + u32 flow_label; + u8 tcp_state; + u8 snd_wscale; + u8 rcv_wscale; + u32 time_stamp_recent; + u32 time_stamp_age; + u32 snd_nxt; + u32 snd_wnd; + u32 rcv_nxt; + u32 rcv_wnd; + u32 snd_max; + u32 snd_una; + u32 srtt; + u32 rtt_var; + u32 ss_thresh; + u32 cwnd; + u32 snd_wl1; + u32 snd_wl2; + u32 max_snd_window; + u8 rexmit_thresh; + u32 local_ipaddr[4]; +}; + +struct irdma_qp_host_ctx_info { + u64 qp_compl_ctx; + union { + struct irdma_tcp_offload_info *tcp_info; + struct irdma_udp_offload_info *udp_info; + }; + union { + struct irdma_iwarp_offload_info *iwarp_info; + struct irdma_roce_offload_info *roce_info; + }; + u32 send_cq_num; + u32 rcv_cq_num; + u32 srq_id; + u32 rem_endpoint_idx; + u16 stats_idx; + bool remote_atomics_en:1; + bool srq_valid:1; + bool tcp_info_valid:1; + bool iwarp_info_valid:1; + bool stats_idx_valid:1; + u8 user_pri; +}; + +struct irdma_aeqe_info { + u64 compl_ctx; + u32 qp_cq_id; + u32 wqe_idx; + u32 def_info; /* only valid for DEF_CMPL */ + u16 ae_id; + u8 tcp_state; + u8 iwarp_state; + bool qp:1; + bool cq:1; + bool sq:1; + bool rq:1; + bool srq:1; + bool in_rdrsp_wr:1; + bool out_rdrsp:1; + bool aeqe_overflow:1; + /* This flag is used to determine if we should pass the rq tail + * in the QP context for FW/HW. It is set when ae_src is rq for GEN1/GEN2 + * And additionally set for inbound atomic, read and write for GEN3 + */ + bool err_rq_idx_valid:1; + u8 q2_data_written; + u8 ae_src; +}; + +struct irdma_allocate_stag_info { + u64 total_len; + u64 first_pm_pbl_idx; + u32 chunk_size; + u32 stag_idx; + u32 page_size; + u32 pd_id; + u16 access_rights; + bool remote_access:1; + bool use_hmc_fcn_index:1; + bool use_pf_rid:1; + bool all_memory:1; + bool remote_atomics_en:1; + bool pasid_valid:1; + u32 pasid; + bool use_aso:1; + u8 aso_host_id; + u8 aso_vm_vf_type; + u8 aso_vm_vf_num; + u8 aso_pf_num; + bool non_cached:1; + u8 placement_type; + u16 hmc_fcn_index; +}; + +struct irdma_mw_alloc_info { + u32 mw_stag_index; + u32 page_size; + u32 pd_id; + bool remote_access:1; + bool mw_wide:1; + bool mw1_bind_dont_vldt_key:1; + u8 remote_atomics_en; +}; + +struct irdma_reg_ns_stag_info { + u64 reg_addr_pa; + u64 va; + u64 total_len; + u32 page_size; + u32 chunk_size; + u32 first_pm_pbl_index; + enum irdma_addressing_type addr_type; + irdma_stag_index stag_idx; + u16 access_rights; + u32 pd_id; + irdma_stag_key stag_key; + bool use_hmc_fcn_index:1; + u16 hmc_fcn_index; + bool use_pf_rid:1; + bool all_memory:1; + bool pasid_valid:1; + u8 remote_atomics_en; + u32 pasid; + bool non_cached:1; + u8 placement_type; +}; + +struct irdma_fast_reg_stag_info { + u64 wr_id; + u64 reg_addr_pa; + u64 fbo; + void *va; + u64 total_len; + u32 page_size; + u32 chunk_size; + u32 first_pm_pbl_index; + enum irdma_addressing_type addr_type; + irdma_stag_index stag_idx; + u16 access_rights; + u32 pd_id; + irdma_stag_key stag_key; + bool local_fence:1; + bool read_fence:1; + bool signaled:1; + bool push_wqe:1; + bool use_hmc_fcn_index:1; + u16 hmc_fcn_index; + bool use_pf_rid:1; + bool defer_flag:1; + bool remote_atomics_en:1; +}; + +struct irdma_dealloc_stag_info { + u32 stag_idx; + u32 pd_id; + bool mr:1; + bool dealloc_pbl:1; +}; + +struct irdma_register_shared_stag { + u64 va; + enum irdma_addressing_type addr_type; + irdma_stag_index new_stag_idx; + irdma_stag_index parent_stag_idx; + u32 access_rights; + u32 pd_id; + u32 page_size; + irdma_stag_key new_stag_key; + u8 remote_atomics_en; +}; + +struct irdma_qp_init_info { + struct irdma_qp_uk_init_info qp_uk_init_info; + struct irdma_sc_pd *pd; + struct irdma_sc_vsi *vsi; + __le64 *host_ctx; + u8 *q2; + u64 sq_pa; + u64 rq_pa; + u64 host_ctx_pa; + u64 q2_pa; + u64 shadow_area_pa; + u8 sq_tph_val; + u8 rq_tph_val; + bool sq_tph_en:1; + bool rq_tph_en:1; + bool rcv_tph_en:1; + bool xmit_tph_en:1; + bool virtual_map:1; +}; + +struct irdma_cq_init_info { + struct irdma_sc_dev *dev; + u64 cq_base_pa; + u64 shadow_area_pa; + u32 ceq_id; + u32 shadow_read_threshold; + u8 pbl_chunk_size; + u32 first_pm_pbl_idx; + bool virtual_map:1; + bool ceqe_mask:1; + bool ceq_id_valid:1; + bool tph_en:1; + bool pasid_valid:1; + u32 pasid; + u8 tph_val; + u8 type; + struct irdma_cq_uk_init_info cq_uk_init_info; + struct irdma_sc_vsi *vsi; +}; + +struct irdma_upload_context_info { + u64 buf_pa; + u32 qp_id; + u16 hmc_fcn_id; + u8 qp_type; + bool freeze_qp:1; + bool raw_format:1; + bool use_hmc_fcn_id:1; +}; + +struct irdma_local_mac_entry_info { + u8 mac_addr[6]; + u16 entry_idx; +}; + +struct irdma_add_arp_cache_entry_info { + u8 mac_addr[ETH_ALEN]; + u32 reach_max; + u16 arp_index; + bool permanent:1; +}; + +struct irdma_apbvt_info { + u16 port; + bool add:1; +}; + +struct irdma_qhash_table_info { + struct irdma_sc_vsi *vsi; + enum irdma_quad_hash_manage_type manage; + enum irdma_quad_entry_type entry_type; + bool vlan_valid:1; + bool ipv4_valid:1; + u8 mac_addr[ETH_ALEN]; + u16 vlan_id; + u8 user_pri; + u32 qp_num; + u32 dest_ip[4]; + u32 src_ip[4]; + u16 dest_port; + u16 src_port; +}; + +struct irdma_cqp_manage_push_page_info { + u32 push_idx; + u16 qs_handle; + u16 hmc_fn_id; + u8 free_page; + u8 push_page_type; + u8 page_type; + u8 use_hmc_fn_id; +}; + +struct irdma_qp_flush_info { + u32 err_sq_idx; + u16 sq_minor_code; + u16 sq_major_code; + u16 rq_minor_code; + u16 rq_major_code; + u16 ae_code; + u8 ae_src; + bool sq:1; + bool rq:1; + bool userflushcode:1; + bool generate_ae:1; + bool err_sq_idx_valid:1; +}; + +struct irdma_gen_ae_info { + u16 ae_code; + u8 ae_src; +}; + +struct irdma_cqp_timeout { + u64 compl_cqp_cmds; + u32 count; +}; + +struct irdma_irq_ops { + void (*irdma_cfg_aeq)(struct irdma_sc_dev *dev, u32 idx, bool enable); + void (*irdma_cfg_ceq)(struct irdma_sc_dev *dev, u32 ceq_id, u32 idx, + bool enable); + void (*irdma_dis_irq)(struct irdma_sc_dev *dev, u32 idx); + void (*irdma_en_irq)(struct irdma_sc_dev *dev, u32 idx); +}; + +void irdma_sc_ccq_arm(struct irdma_sc_cq *ccq); +int irdma_sc_ccq_create(struct irdma_sc_cq *ccq, u64 scratch, + bool check_overflow, bool post_sq); +int irdma_sc_ccq_destroy(struct irdma_sc_cq *ccq, u64 scratch, bool post_sq); +int irdma_sc_ccq_get_cqe_info(struct irdma_sc_cq *ccq, + struct irdma_ccq_cqe_info *info); +int irdma_sc_ccq_init(struct irdma_sc_cq *ccq, + struct irdma_ccq_init_info *info); + +int irdma_sc_cceq_create(struct irdma_sc_ceq *ceq); +int irdma_sc_cceq_destroy_done(struct irdma_sc_ceq *ceq); + +int irdma_sc_ceq_destroy(struct irdma_sc_ceq *ceq, u64 scratch, bool post_sq); +int irdma_sc_ceq_init(struct irdma_sc_ceq *ceq, + struct irdma_ceq_init_info *info); +void irdma_sc_cleanup_ceqes(struct irdma_sc_cq *cq, struct irdma_sc_ceq *ceq); +void *irdma_sc_process_ceq(struct irdma_sc_dev *dev, struct irdma_sc_ceq *ceq); + +int irdma_sc_aeq_init(struct irdma_sc_aeq *aeq, + struct irdma_aeq_init_info *info); +int irdma_sc_get_next_aeqe(struct irdma_sc_aeq *aeq, + struct irdma_aeqe_info *info); +void irdma_sc_repost_aeq_entries(struct irdma_sc_dev *dev, u32 count); + +void irdma_sc_pd_init(struct irdma_sc_dev *dev, struct irdma_sc_pd *pd, u32 pd_id, + int abi_ver); +void irdma_cfg_aeq(struct irdma_sc_dev *dev, u32 idx, bool enable); +#if IS_ENABLED(CONFIG_CONFIGFS_FS) +void irdma_set_irq_rate_limit(struct irdma_sc_dev *dev, u32 idx, u32 interval); +#endif +void irdma_check_cqp_progress(struct irdma_cqp_timeout *cqp_timeout, + struct irdma_sc_dev *dev); +void irdma_sc_cqp_def_cmpl_ae_handler(struct irdma_sc_dev *dev, + struct irdma_aeqe_info *info, + bool first, u64 *scratch, + u32 *sw_def_info); +u64 irdma_sc_cqp_cleanup_handler(struct irdma_sc_dev *dev); +int irdma_sc_cqp_create(struct irdma_sc_cqp *cqp, u16 *maj_err, u16 *min_err); +int irdma_sc_cqp_destroy(struct irdma_sc_cqp *cqp, bool free_hwcqp); +int irdma_sc_cqp_init(struct irdma_sc_cqp *cqp, + struct irdma_cqp_init_info *info); +void irdma_sc_cqp_post_sq(struct irdma_sc_cqp *cqp); +int irdma_sc_poll_for_cqp_op_done(struct irdma_sc_cqp *cqp, u8 opcode, + struct irdma_ccq_cqe_info *cmpl_info); +int irdma_sc_qp_create(struct irdma_sc_qp *qp, + struct irdma_create_qp_info *info, u64 scratch, + bool post_sq); +int irdma_sc_qp_destroy(struct irdma_sc_qp *qp, u64 scratch, + bool remove_hash_idx, bool ignore_mw_bnd, bool post_sq); +int irdma_sc_qp_flush_wqes(struct irdma_sc_qp *qp, + struct irdma_qp_flush_info *info, u64 scratch, + bool post_sq); +int irdma_sc_qp_init(struct irdma_sc_qp *qp, struct irdma_qp_init_info *info); +int irdma_sc_qp_modify(struct irdma_sc_qp *qp, + struct irdma_modify_qp_info *info, u64 scratch, + bool post_sq); +void irdma_sc_send_lsmm(struct irdma_sc_qp *qp, void *lsmm_buf, u32 size, + irdma_stag stag); +void irdma_sc_send_rtt(struct irdma_sc_qp *qp, bool read); +void irdma_sc_qp_setctx(struct irdma_sc_qp *qp, __le64 *qp_ctx, + struct irdma_qp_host_ctx_info *info); +void irdma_sc_qp_setctx_roce(struct irdma_sc_qp *qp, __le64 *qp_ctx, + struct irdma_qp_host_ctx_info *info); +int irdma_sc_cq_destroy(struct irdma_sc_cq *cq, u64 scratch, bool post_sq); +int irdma_sc_cq_init(struct irdma_sc_cq *cq, struct irdma_cq_init_info *info); +void irdma_sc_cq_resize(struct irdma_sc_cq *cq, struct irdma_modify_cq_info *info); +int irdma_sc_aeq_destroy(struct irdma_sc_aeq *aeq, u64 scratch, bool post_sq); +int irdma_sc_static_hmc_pages_allocated(struct irdma_sc_cqp *cqp, u64 scratch, + u16 hmc_fn_id, bool post_sq, + bool poll_registers); +int irdma_sc_srq_init(struct irdma_sc_srq *srq, + struct irdma_srq_init_info *info); + +void sc_vsi_update_stats(struct irdma_sc_vsi *vsi); +struct cqp_info { + union { + struct { + struct irdma_sc_qp *qp; + struct irdma_create_qp_info info; + u64 scratch; + } qp_create; + + struct { + struct irdma_sc_qp *qp; + struct irdma_modify_qp_info info; + u64 scratch; + } qp_modify; + + struct { + struct irdma_sc_qp *qp; + u64 scratch; + bool remove_hash_idx; + bool ignore_mw_bnd; + } qp_destroy; + + struct { + struct irdma_sc_cq *cq; + u64 scratch; + bool check_overflow; + } cq_create; + + struct { + struct irdma_sc_cq *cq; + struct irdma_modify_cq_info info; + u64 scratch; + } cq_modify; + + struct { + struct irdma_sc_cq *cq; + u64 scratch; + } cq_destroy; + + struct { + struct irdma_sc_dev *dev; + struct irdma_allocate_stag_info info; + u64 scratch; + } alloc_stag; + + struct { + struct irdma_sc_dev *dev; + struct irdma_mw_alloc_info info; + u64 scratch; + } mw_alloc; + + struct { + struct irdma_sc_dev *dev; + struct irdma_reg_ns_stag_info info; + u64 scratch; + } mr_reg_non_shared; + + struct { + struct irdma_sc_dev *dev; + struct irdma_dealloc_stag_info info; + u64 scratch; + } dealloc_stag; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_add_arp_cache_entry_info info; + u64 scratch; + } add_arp_cache_entry; + + struct { + struct irdma_sc_cqp *cqp; + u64 scratch; + u16 arp_index; + } del_arp_cache_entry; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_local_mac_entry_info info; + u64 scratch; + } add_local_mac_entry; + + struct { + struct irdma_sc_cqp *cqp; + u64 scratch; + u8 entry_idx; + u8 ignore_ref_count; + } del_local_mac_entry; + + struct { + struct irdma_sc_cqp *cqp; + u64 scratch; + } alloc_local_mac_entry; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_manage_pble_info info; + u64 scratch; + } manage_pble_bp; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_cqp_manage_push_page_info info; + u64 scratch; + } manage_push_page; + + struct { + struct irdma_sc_dev *dev; + struct irdma_upload_context_info info; + u64 scratch; + } qp_upload_context; + + struct { + struct irdma_sc_dev *dev; + struct irdma_hmc_fcn_info info; + u64 scratch; + } manage_hmc_pm; + + struct { + struct irdma_sc_ceq *ceq; + u64 scratch; + } ceq_create; + + struct { + struct irdma_sc_ceq *ceq; + u64 scratch; + } ceq_destroy; + + struct { + struct irdma_sc_aeq *aeq; + u64 scratch; + } aeq_create; + + struct { + struct irdma_sc_aeq *aeq; + u64 scratch; + } aeq_destroy; + + struct { + struct irdma_sc_qp *qp; + struct irdma_qp_flush_info info; + u64 scratch; + } qp_flush_wqes; + + struct { + struct irdma_sc_qp *qp; + struct irdma_gen_ae_info info; + u64 scratch; + } gen_ae; + + struct { + struct irdma_sc_cqp *cqp; + void *fpm_val_va; + u64 fpm_val_pa; + u16 hmc_fn_id; + u64 scratch; + } query_fpm_val; + + struct { + struct irdma_sc_cqp *cqp; + void *fpm_val_va; + u64 fpm_val_pa; + u16 hmc_fn_id; + u64 scratch; + } commit_fpm_val; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_apbvt_info info; + u64 scratch; + } manage_apbvt_entry; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_qhash_table_info info; + u64 scratch; + } manage_qhash_table_entry; + + struct { + struct irdma_sc_dev *dev; + struct irdma_update_sds_info info; + u64 scratch; + } update_pe_sds; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_sc_qp *qp; + u64 scratch; + } suspend_resume; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_ah_info info; + u64 scratch; + } ah_create; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_ah_info info; + u64 scratch; + } ah_destroy; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_mcast_grp_info info; + u64 scratch; + } mc_create; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_mcast_grp_info info; + u64 scratch; + } mc_destroy; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_mcast_grp_info info; + u64 scratch; + } mc_modify; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_stats_inst_info info; + u64 scratch; + } stats_manage; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_stats_gather_info info; + u64 scratch; + } stats_gather; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_ws_node_info info; + u64 scratch; + } ws_node; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_ws_move_node_info info; + u64 scratch; + } ws_move_node; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_up_info info; + u64 scratch; + } up_map; + + struct { + struct irdma_sc_cqp *cqp; + struct irdma_dma_mem query_buff_mem; + u64 scratch; + } query_rdma; + + struct { + struct irdma_sc_srq *srq; + u64 scratch; + } srq_create; + + struct { + struct irdma_sc_srq *srq; + struct irdma_modify_srq_info info; + u64 scratch; + } srq_modify; + + struct { + struct irdma_sc_srq *srq; + u64 scratch; + } srq_destroy; + + } u; +}; + +struct cqp_cmds_info { + struct list_head cqp_cmd_entry; + u8 cqp_cmd; + u8 post_sq; + struct cqp_info in; +}; + +struct irdma_vchnl_work { + struct work_struct work; + u8 vf_msg_buf[IRDMA_VCHNL_MAX_MSG_SIZE]; + struct irdma_sc_dev *dev; + u16 vf_id; + u16 len; +}; + +__le64 *irdma_sc_cqp_get_next_send_wqe_idx(struct irdma_sc_cqp *cqp, u64 scratch, + u32 *wqe_idx); + +/** + * irdma_sc_cqp_get_next_send_wqe - get next wqe on cqp sq + * @cqp: struct for cqp hw + * @scratch: private data for CQP WQE + */ +static inline __le64 *irdma_sc_cqp_get_next_send_wqe(struct irdma_sc_cqp *cqp, u64 scratch) +{ + u32 wqe_idx; + + return irdma_sc_cqp_get_next_send_wqe_idx(cqp, scratch, &wqe_idx); +} +#endif /* IRDMA_TYPE_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ubuntu_kcompat.h b/drivers/intel/irdma-1.14.33/src/irdma/ubuntu_kcompat.h new file mode 100644 index 000000000..b99bf1491 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ubuntu_kcompat.h @@ -0,0 +1,505 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2020 - 2024 Intel Corporation */ +#ifndef UBUNTU_KCOMPAT_H +#define UBUNTU_KCOMPAT_H + +#ifdef UBUNTU_2404 +/* Ubuntu 24.04 - Linux 6.8.0 */ +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V2 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define COPY_USER_PGADDR_VER_4 +#define CREATE_AH_VER_5 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_2 +#define DEALLOC_PD_VER_4 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_4 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define GLOBAL_QP_MEM +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_DEV_CAPS_VER_2 +#define IB_UMEM_GET_V3 +#define IN_IFADDR +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IW_PORT_IMMUTABLE_V2 +#define MODIFY_PORT_V2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define REREG_MR_VER_2 +#define ROCE_PORT_IMMUTABLE_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_BEST_PAGE_SZ_V2 +#define SET_ROCE_CM_INFO_VER_3 +#define SET_DMABUF + +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) rdma_gid_attr_network_type(sgid_attr) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_typeq_ib_wr const +#endif /* UBUNTU_2204 */ + +#ifdef UBUNTU_2204 +/* Ubuntu 22.04 */ +#define ALLOC_HW_STATS_V3 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_2 +#define DEALLOC_PD_VER_4 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_4 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V2 +#define GET_LINK_LAYER_V2 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_UMEM_GET_V3 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IN_IFADDR +#define IW_PORT_IMMUTABLE_V2 +#define MODIFY_PORT_V2 +#define REREG_MR_VER_2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V2 +#define QUERY_GID_ROCE_V2 +#define QUERY_PKEY_V2 +#define QUERY_PORT_V2 +#define ROCE_PORT_IMMUTABLE_V2 +#define SET_BEST_PAGE_SZ_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_ROCE_CM_INFO_VER_3 +#define GLOBAL_QP_MEM + +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) rdma_gid_attr_network_type(sgid_attr) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_typeq_ib_wr const +#endif /* UBUNTU_2204 */ + +#ifdef UBUNTU_200405 +/* Ubuntu 20.04.05 */ +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_2 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_3 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_3 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_UMEM_GET_V3 +#define IRDMA_ALLOC_MR_VER_1 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_3 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IN_IFADDR +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define REREG_MR_VER_1 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_ROCE_CM_INFO_VER_3 +#define USE_KMAP +#define UVERBS_CMD_MASK +#define IB_IW_PKEY +#define SET_PCIDEV_PARENT + +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) rdma_gid_attr_network_type(sgid_attr) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_typeq_ib_wr const +#endif /* UBUNTU_200405 */ + +#ifdef UBUNTU_200404 +/* Ubuntu 20.04.4 */ +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_2 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_3 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_3 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_UMEM_GET_V3 +#define IRDMA_ALLOC_MR_VER_1 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_3 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IN_IFADDR +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define REREG_MR_VER_1 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_ROCE_CM_INFO_VER_3 +#define USE_KMAP +#define UVERBS_CMD_MASK +#define IB_IW_PKEY +#define SET_PCIDEV_PARENT + +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) rdma_gid_attr_network_type(sgid_attr) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_typeq_ib_wr const +#endif /* UBUNTU_200404 */ + +#ifdef UBUNTU_200403 +/* Ubuntu 20.04.3 */ +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_4 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_4 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_IW_PKEY +#define IB_UMEM_GET_V3 +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_2 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IN_IFADDR +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define REREG_MR_VER_2 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_ROCE_CM_INFO_VER_3 + +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name, dev) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) rdma_gid_attr_network_type(sgid_attr) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_typeq_ib_wr const +#endif /* UBUNTU_200403 */ + +#ifdef UBUNTU_200402 +/* Ubuntu 20.04.2 */ +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_5 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_3 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_3 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_IW_PKEY +#define IB_UMEM_GET_V3 +#define IRDMA_ALLOC_MR_VER_1 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_4 +#define IRDMA_DESTROY_SRQ_VER_3 +#define IN_IFADDR +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_ROCE_CM_INFO_VER_3 +#define UVERBS_CMD_MASK +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) rdma_gid_attr_network_type(sgid_attr) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_typeq_ib_wr const +#endif /* UBUNTU_200402 */ + +#ifdef UBUNTU_2004 +/* Ubuntu 20.04 backport from > 5.4 kernel */ +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_3 +#define ALLOC_UCONTEXT_VER_2 +#define CREATE_AH_VER_2 +#define CREATE_CQ_VER_3 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_3 +#define DEALLOC_UCONTEXT_VER_2 +#define DEREG_MR_VER_2 +#define DESTROY_AH_VER_3 +#define DESTROY_QP_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define HAS_IB_SET_DEVICE_OP +#define IB_DEALLOC_DRIVER_SUPPORT +#define IB_IW_PKEY +#define IB_UMEM_GET_V2 +#define IRDMA_ALLOC_MR_VER_1 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_3 +#define IRDMA_DESTROY_SRQ_VER_2 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IN_IFADDR +#define IW_PORT_IMMUTABLE_V1 +#define MODIFY_PORT_V1 +#define NETDEV_TO_IBDEV_SUPPORT +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V2 +#define RDMA_MMAP_DB_SUPPORT +#define SET_ROCE_CM_INFO_VER_3 +#define UVERBS_CMD_MASK +#define USE_KMAP +#define SET_PCIDEV_PARENT + +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) +#define set_max_sge(props, rf) do { \ + ((props)->max_send_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + ((props)->max_recv_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags); \ + } while (0) +#define kc_deref_sgid_attr(sgid_attr) ((sgid_attr)->ndev) +#define kc_get_ucontext(udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) ib_modify_qp_is_ok(cur_state, next_state, type, mask) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, name) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) rdma_gid_attr_network_type(sgid_attr) +#define kc_rdma_udata_to_drv_context(ibpd, udata) rdma_udata_to_drv_context(udata, struct irdma_ucontext, ibucontext) +#define kc_set_ibdev_add_del_gid(ibdev) +#define kc_set_props_ip_gid_caps(props) ((props)->ip_gids = true) +#define kc_typeq_ib_wr const +#endif /* UBUNTU_2004 */ + +#ifdef UBUNTU_1804 +#define ALLOC_HW_STATS_V1 +#define ALLOC_HW_STATS_STRUCT_V1 +#define ALLOC_PD_VER_1 +#define ALLOC_UCONTEXT_VER_1 +#define CREATE_AH_VER_1_2 +#define CREATE_CQ_VER_1 +#define CREATE_QP_VER_1 +#define DEALLOC_PD_VER_1 +#define DEALLOC_UCONTEXT_VER_1 +#define DEREG_MR_VER_1 +#define DESTROY_AH_VER_1 +#define DESTROY_QP_VER_1 +#define ETHER_COPY_VER_2 +#define GET_HW_STATS_V1 +#define GET_LINK_LAYER_V1 +#define IB_GET_CACHED_GID +#define IB_IW_MANDATORY_AH_OP +#define IB_IW_PKEY +#define IB_UMEM_GET_V0 +#define IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION IB_CQ_FLAGS_TIMESTAMP_COMPLETION +#define IRDMA_ADD_DEL_GID +#define IRDMA_ALLOC_MR_VER_0 +#define IRDMA_ALLOC_MW_VER_1 +#define IRDMA_DESTROY_CQ_VER_1 +#define IRDMA_DESTROY_SRQ_VER_1 +#define IRDMA_IRQ_UPDATE_AFFINITY +#define IRDMA_AUX_GET_SET_DRV_DATA +#define IW_PORT_IMMUTABLE_V1 +#define FOR_IFA +#define MODIFY_PORT_V1 +#define QUERY_GID_V1 +#define QUERY_GID_ROCE_V1 +#define QUERY_PKEY_V1 +#define QUERY_PORT_V1 +#define REREG_MR_VER_1 +#define ROCE_PORT_IMMUTABLE_V1 +#define SET_BEST_PAGE_SZ_V1 +#define SET_ROCE_CM_INFO_VER_1 +#define UVERBS_CMD_MASK +#define VMA_DATA +#define USE_KMAP +#define NEED_IDA_ALLOC_MIN_MAX_RANGE_FREE +#define SET_PCIDEV_PARENT + +enum ib_port_phys_state { + IB_PORT_PHYS_STATE_SLEEP = 1, + IB_PORT_PHYS_STATE_POLLING = 2, + IB_PORT_PHYS_STATE_DISABLED = 3, + IB_PORT_PHYS_STATE_PORT_CONFIGURATION_TRAINING = 4, + IB_PORT_PHYS_STATE_LINK_UP = 5, + IB_PORT_PHYS_STATE_LINK_ERROR_RECOVERY = 6, + IB_PORT_PHYS_STATE_PHY_TEST = 7, +}; + +int irdma_add_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + const union ib_gid *gid, + const struct ib_gid_attr *attr, + void **context); +int irdma_del_gid(struct ib_device *device, + u8 port_num, + unsigned int index, + void **context); + +#define kc_set_ibdev_add_del_gid(ibdev) do { \ + ibdev->add_gid = irdma_add_gid; \ + ibdev->del_gid = irdma_del_gid; \ +} while (0) +#define ah_attr_to_dmac(attr) ((attr).roce.dmac) +#define set_ibdev_dma_device(ibdev, dev) +#define set_max_sge(props, rf) \ + ((props)->max_sge = (rf)->sc_dev.hw_attrs.uk_attrs.max_hw_wq_frags) +#define kc_set_props_ip_gid_caps(props) \ + ((props)->port_cap_flags |= IB_PORT_IP_BASED_GIDS) +#define kc_rdma_gid_attr_network_type(sgid_attr, gid_type, gid) \ + ib_gid_to_network_type(gid_type, gid) +#define kc_deref_sgid_attr(sgid_attr) (sgid_attr.ndev) +#define rdma_query_gid(ibdev, port, index, gid) \ + ib_get_cached_gid(ibdev, port, index, gid, NULL) + +#define kc_get_ucontext(udata) to_ucontext(context) +#define kc_ib_register_device(device, name, dev) ib_register_device(device, NULL) +#define kc_ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) \ + ib_modify_qp_is_ok(cur_state, next_state, type, mask, ll) +#define kc_rdma_udata_to_drv_context(ibpd, udata) to_ucontext((ibpd)->uobject->context) +#define kc_typeq_ib_wr +#define ib_device_put(dev) +#define ib_alloc_device(irdma_device, ibdev) \ + ((struct irdma_device *)ib_alloc_device(sizeof(struct irdma_device))) +#endif /* UBUNTU_1804 */ + +#endif /* UBUNTU_KCOMPAT_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/uda.c b/drivers/intel/irdma-1.14.33/src/irdma/uda.c new file mode 100644 index 000000000..c1d5169d1 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/uda.c @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2016 - 2023 Intel Corporation */ +#include "osdep.h" +#include "hmc.h" +#include "defs.h" +#include "type.h" +#include "protos.h" +#include "uda.h" +#include "uda_d.h" + +/** + * irdma_sc_access_ah() - Create, modify or delete AH + * @cqp: struct for cqp hw + * @info: ah information + * @op: Operation + * @scratch: u64 saved to be used during cqp completion + */ +int irdma_sc_access_ah(struct irdma_sc_cqp *cqp, struct irdma_ah_info *info, + u32 op, u64 scratch) +{ + __le64 *wqe; + u64 qw1, qw2; + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, + FIELD_PREP(IRDMAQPC_MACADDRESS, ether_addr_to_u64(info->mac_addr))); + + qw1 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXLO, info->pd_idx) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_TC, info->tc_tos) | + FIELD_PREP(IRDMA_UDAQPC_VLANTAG, info->vlan_tag); + + qw2 = FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ARPINDEX, info->dst_arpindex) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_FLOWLABEL, info->flow_label) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_HOPLIMIT, info->hop_ttl) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_PDINDEXHI, info->pd_idx >> 16); + + if (!info->ipv4_valid) { + set_64bit_val(wqe, 40, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1])); + set_64bit_val(wqe, 32, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->dest_ip_addr[2]) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[3])); + + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->src_ip_addr[0]) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->src_ip_addr[1])); + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->src_ip_addr[2]) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->src_ip_addr[3])); + } else { + set_64bit_val(wqe, 32, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[0])); + + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->src_ip_addr[0])); + } + + set_64bit_val(wqe, 8, qw1); + set_64bit_val(wqe, 16, qw2); + + dma_wmb(); /* need write block before writing WQE header */ + + set_64bit_val( + wqe, 24, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_OPCODE, op) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK, info->do_lpbk) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_IPV4VALID, info->ipv4_valid) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_AVIDX, info->ah_idx) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG, info->insert_vlan_tag)); + + print_hex_dump_debug("WQE: MANAGE_AH WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_create_mg_ctx() - create a mcg context + * @info: multicast group context info + */ +static void irdma_create_mg_ctx(struct irdma_mcast_grp_info *info) +{ + struct irdma_mcast_grp_ctx_entry_info *entry_info = NULL; + u8 idx = 0; /* index in the array */ + u8 ctx_idx = 0; /* index in the MG context */ + + memset(info->dma_mem_mc.va, 0, IRDMA_MAX_MGS_PER_CTX * sizeof(u64)); + + for (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) { + entry_info = &info->mg_ctx_info[idx]; + if (entry_info->valid_entry) { + set_64bit_val((__le64 *)info->dma_mem_mc.va, + ctx_idx * sizeof(u64), + FIELD_PREP(IRDMA_UDA_MGCTX_DESTPORT, entry_info->dest_port) | + FIELD_PREP(IRDMA_UDA_MGCTX_VALIDENT, entry_info->valid_entry) | + FIELD_PREP(IRDMA_UDA_MGCTX_QPID, entry_info->qp_id)); + ctx_idx++; + } + } +} + +/** + * irdma_access_mcast_grp() - Access mcast group based on op + * @cqp: Control QP + * @info: multicast group context info + * @op: operation to perform + * @scratch: u64 saved to be used during cqp completion + */ +int irdma_access_mcast_grp(struct irdma_sc_cqp *cqp, + struct irdma_mcast_grp_info *info, u32 op, + u64 scratch) +{ + __le64 *wqe; + + if (info->mg_id >= IRDMA_UDA_MAX_FSI_MGS) { + ibdev_dbg(to_ibdev(cqp->dev), "WQE: mg_id out of range\n"); + return -EINVAL; + } + + wqe = irdma_sc_cqp_get_next_send_wqe(cqp, scratch); + if (!wqe) { + ibdev_dbg(to_ibdev(cqp->dev), "WQE: ring full\n"); + return -ENOMEM; + } + + irdma_create_mg_ctx(info); + + set_64bit_val(wqe, 32, info->dma_mem_mc.pa); + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMA_UDA_CQPSQ_MG_VLANID, info->vlan_id) | + FIELD_PREP(IRDMA_UDA_CQPSQ_QS_HANDLE, info->qs_handle)); + set_64bit_val(wqe, 0, ether_addr_to_u64(info->dest_mac_addr)); + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID, info->hmc_fcn_id)); + + if (!info->ipv4_valid) { + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR0, info->dest_ip_addr[0]) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR1, info->dest_ip_addr[1])); + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR2, info->dest_ip_addr[2]) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[3])); + } else { + set_64bit_val(wqe, 48, + FIELD_PREP(IRDMA_UDA_CQPSQ_MAV_ADDR3, info->dest_ip_addr[0])); + } + + dma_wmb(); /* need write memory block before writing the WQE header. */ + + set_64bit_val(wqe, 24, + FIELD_PREP(IRDMA_UDA_CQPSQ_MG_WQEVALID, cqp->polarity) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MG_OPCODE, op) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MG_MGIDX, info->mg_id) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MG_VLANVALID, info->vlan_valid) | + FIELD_PREP(IRDMA_UDA_CQPSQ_MG_IPV4VALID, info->ipv4_valid)); + + print_hex_dump_debug("WQE: MANAGE_MCG WQE", DUMP_PREFIX_OFFSET, 16, 8, + wqe, IRDMA_CQP_WQE_SIZE * 8, false); + print_hex_dump_debug("WQE: MCG_HOST CTX WQE", DUMP_PREFIX_OFFSET, 16, + 8, info->dma_mem_mc.va, + IRDMA_MAX_MGS_PER_CTX * 8, false); + irdma_sc_cqp_post_sq(cqp); + + return 0; +} + +/** + * irdma_compare_mgs - Compares two multicast group structures + * @entry1: Multcast group info + * @entry2: Multcast group info in context + */ +static bool irdma_compare_mgs(struct irdma_mcast_grp_ctx_entry_info *entry1, + struct irdma_mcast_grp_ctx_entry_info *entry2) +{ + if (entry1->dest_port == entry2->dest_port && + entry1->qp_id == entry2->qp_id) + return true; + + return false; +} + +/** + * irdma_sc_add_mcast_grp - Allocates mcast group entry in ctx + * @ctx: Multcast group context + * @mg: Multcast group info + */ +int irdma_sc_add_mcast_grp(struct irdma_mcast_grp_info *ctx, + struct irdma_mcast_grp_ctx_entry_info *mg) +{ + u32 idx; + bool free_entry_found = false; + u32 free_entry_idx = 0; + + /* find either an identical or a free entry for a multicast group */ + for (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) { + if (ctx->mg_ctx_info[idx].valid_entry) { + if (irdma_compare_mgs(&ctx->mg_ctx_info[idx], mg)) { + ctx->mg_ctx_info[idx].use_cnt++; + return 0; + } + continue; + } + if (!free_entry_found) { + free_entry_found = true; + free_entry_idx = idx; + } + } + + if (free_entry_found) { + ctx->mg_ctx_info[free_entry_idx] = *mg; + ctx->mg_ctx_info[free_entry_idx].valid_entry = true; + ctx->mg_ctx_info[free_entry_idx].use_cnt = 1; + ctx->no_of_mgs++; + return 0; + } + + return -ENOMEM; +} + +/** + * irdma_sc_del_mcast_grp - Delete mcast group + * @ctx: Multcast group context + * @mg: Multcast group info + * + * Finds and removes a specific mulicast group from context, all + * parameters must match to remove a multicast group. + */ +int irdma_sc_del_mcast_grp(struct irdma_mcast_grp_info *ctx, + struct irdma_mcast_grp_ctx_entry_info *mg) +{ + u32 idx; + + /* find an entry in multicast group context */ + for (idx = 0; idx < IRDMA_MAX_MGS_PER_CTX; idx++) { + if (!ctx->mg_ctx_info[idx].valid_entry) + continue; + + if (irdma_compare_mgs(mg, &ctx->mg_ctx_info[idx])) { + ctx->mg_ctx_info[idx].use_cnt--; + + if (!ctx->mg_ctx_info[idx].use_cnt) { + ctx->mg_ctx_info[idx].valid_entry = false; + ctx->no_of_mgs--; + /* Remove gap if element was not the last */ + if (idx != ctx->no_of_mgs && + ctx->no_of_mgs > 0) { + memcpy(&ctx->mg_ctx_info[idx], + &ctx->mg_ctx_info[ctx->no_of_mgs - 1], + sizeof(ctx->mg_ctx_info[idx])); + ctx->mg_ctx_info[ctx->no_of_mgs - 1].valid_entry = false; + } + } + + return 0; + } + } + + return -EINVAL; +} + diff --git a/drivers/intel/irdma-1.14.33/src/irdma/uda.h b/drivers/intel/irdma-1.14.33/src/irdma/uda.h new file mode 100644 index 000000000..ed7154489 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/uda.h @@ -0,0 +1,88 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2016 - 2023 Intel Corporation */ +#ifndef IRDMA_UDA_H +#define IRDMA_UDA_H + +#define IRDMA_UDA_MAX_FSI_MGS 4096 +#define IRDMA_UDA_MAX_PFS 16 +#define IRDMA_UDA_MAX_VFS 128 + +struct irdma_sc_cqp; + +struct irdma_ah_info { + struct irdma_sc_vsi *vsi; + struct irdma_cqp_request *cqp_request; + u32 pd_idx; + u32 dst_arpindex; + u32 dest_ip_addr[4]; + u32 src_ip_addr[4]; + u32 flow_label; + u32 ah_idx; + u16 vlan_tag; + u8 insert_vlan_tag; + u8 tc_tos; + u8 hop_ttl; + u8 mac_addr[ETH_ALEN]; + bool ah_valid:1; + bool ipv4_valid:1; + bool do_lpbk:1; +}; + +struct irdma_sc_ah { + struct irdma_sc_dev *dev; + struct irdma_ah_info ah_info; +}; + +int irdma_sc_add_mcast_grp(struct irdma_mcast_grp_info *ctx, + struct irdma_mcast_grp_ctx_entry_info *mg); +int irdma_sc_del_mcast_grp(struct irdma_mcast_grp_info *ctx, + struct irdma_mcast_grp_ctx_entry_info *mg); +int irdma_sc_access_ah(struct irdma_sc_cqp *cqp, struct irdma_ah_info *info, + u32 op, u64 scratch); +int irdma_access_mcast_grp(struct irdma_sc_cqp *cqp, + struct irdma_mcast_grp_info *info, u32 op, + u64 scratch); + +static inline void irdma_sc_init_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah) +{ + ah->dev = dev; +} + +static inline int irdma_sc_create_ah(struct irdma_sc_cqp *cqp, + struct irdma_ah_info *info, u64 scratch) +{ + return irdma_sc_access_ah(cqp, info, IRDMA_CQP_OP_CREATE_ADDR_HANDLE, + scratch); +} + +static inline int irdma_sc_destroy_ah(struct irdma_sc_cqp *cqp, + struct irdma_ah_info *info, u64 scratch) +{ + return irdma_sc_access_ah(cqp, info, IRDMA_CQP_OP_DESTROY_ADDR_HANDLE, + scratch); +} + +static inline int irdma_sc_create_mcast_grp(struct irdma_sc_cqp *cqp, + struct irdma_mcast_grp_info *info, + u64 scratch) +{ + return irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_CREATE_MCAST_GRP, + scratch); +} + +static inline int irdma_sc_modify_mcast_grp(struct irdma_sc_cqp *cqp, + struct irdma_mcast_grp_info *info, + u64 scratch) +{ + return irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_MODIFY_MCAST_GRP, + scratch); +} + +static inline int irdma_sc_destroy_mcast_grp(struct irdma_sc_cqp *cqp, + struct irdma_mcast_grp_info *info, + u64 scratch) +{ + return irdma_access_mcast_grp(cqp, info, IRDMA_CQP_OP_DESTROY_MCAST_GRP, + scratch); +} +#endif /* IRDMA_UDA_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/uda_d.h b/drivers/intel/irdma-1.14.33/src/irdma/uda_d.h new file mode 100644 index 000000000..46260dfcf --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/uda_d.h @@ -0,0 +1,221 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2016 - 2021 Intel Corporation */ +#ifndef IRDMA_UDA_D_H +#define IRDMA_UDA_D_H +/* L4 packet type */ +#define IRDMA_E_UDA_SQ_L4T_UNKNOWN 0 +#define IRDMA_E_UDA_SQ_L4T_TCP 1 +#define IRDMA_E_UDA_SQ_L4T_SCTP 2 +#define IRDMA_E_UDA_SQ_L4T_UDP 3 +/* Inner IP header type */ +#define IRDMA_E_UDA_SQ_IIPT_UNKNOWN 0 +#define IRDMA_E_UDA_SQ_IIPT_IPV6 1 +#define IRDMA_E_UDA_SQ_IIPT_IPV4_NO_CSUM 2 +#define IRDMA_E_UDA_SQ_IIPT_IPV4_CSUM 3 +#define IRDMA_UDA_QPSQ_PUSHWQE_S 56 +#define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56) +#define IRDMA_UDA_QPSQ_INLINEDATAFLAG_S 57 +#define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57) +#define IRDMA_UDA_QPSQ_INLINEDATALEN_S 48 +#define IRDMA_UDA_QPSQ_INLINEDATALEN GENMASK_ULL(55, 48) +#define IRDMA_UDA_QPSQ_ADDFRAGCNT_S 38 +#define IRDMA_UDA_QPSQ_ADDFRAGCNT GENMASK_ULL(41, 38) +#define IRDMA_UDA_QPSQ_IPFRAGFLAGS_S 42 +#define IRDMA_UDA_QPSQ_IPFRAGFLAGS GENMASK_ULL(43, 42) +#define IRDMA_UDA_QPSQ_NOCHECKSUM_S 45 +#define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45) +#define IRDMA_UDA_QPSQ_AHIDXVALID_S 46 +#define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46) +#define IRDMA_UDA_QPSQ_LOCAL_FENCE_S 61 +#define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61) +#define IRDMA_UDA_QPSQ_AHIDX_S 0 +#define IRDMA_UDA_QPSQ_AHIDX GENMASK_ULL(16, 0) +#define IRDMA_UDA_QPSQ_PROTOCOL_S 16 +#define IRDMA_UDA_QPSQ_PROTOCOL GENMASK_ULL(23, 16) +#define IRDMA_UDA_QPSQ_EXTHDRLEN_S 32 +#define IRDMA_UDA_QPSQ_EXTHDRLEN GENMASK_ULL(40, 32) +#define IRDMA_UDA_QPSQ_MULTICAST_S 63 +#define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63) +#define IRDMA_UDA_QPSQ_MACLEN_S 56 +#define IRDMA_UDA_QPSQ_MACLEN GENMASK_ULL(62, 56) +#define IRDMA_UDA_QPSQ_MACLEN_LINE 2 +#define IRDMA_UDA_QPSQ_IPLEN_S 48 +#define IRDMA_UDA_QPSQ_IPLEN GENMASK_ULL(54, 48) +#define IRDMA_UDA_QPSQ_IPLEN_LINE 2 +#define IRDMA_UDA_QPSQ_L4T_S 30 +#define IRDMA_UDA_QPSQ_L4T GENMASK_ULL(31, 30) +#define IRDMA_UDA_QPSQ_L4T_LINE 2 +#define IRDMA_UDA_QPSQ_IIPT_S 28 +#define IRDMA_UDA_QPSQ_IIPT GENMASK_ULL(29, 28) +#define IRDMA_UDA_QPSQ_IIPT_LINE 2 +#define IRDMA_UDA_QPSQ_DO_LPB_LINE 3 +#define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_S 45 +#define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45) +#define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM_LINE 3 +#define IRDMA_UDA_QPSQ_IMMDATA_S 0 +#define IRDMA_UDA_QPSQ_IMMDATA GENMASK_ULL(63, 0) +/* Byte Offset 0 */ +#define IRDMA_UDAQPC_IPV4_S 3 +#define IRDMA_UDAQPC_IPV4 BIT_ULL(3) +#define IRDMA_UDAQPC_INSERTVLANTAG_S 5 +#define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5) +#define IRDMA_UDAQPC_ISQP1_S 6 +#define IRDMA_UDAQPC_ISQP1 BIT_ULL(6) +#define IRDMA_UDAQPC_RQWQESIZE_S IRDMAQPC_RQWQESIZE_S +#define IRDMA_UDAQPC_RQWQESIZE IRDMAQPC_RQWQESIZE +#define IRDMA_UDAQPC_ECNENABLE_S 14 +#define IRDMA_UDAQPC_ECNENABLE BIT_ULL(14) +#define IRDMA_UDAQPC_PDINDEXHI_S 20 +#define IRDMA_UDAQPC_PDINDEXHI GENMASK_ULL(21, 20) +#define IRDMA_UDAQPC_DCTCPENABLE_S 25 +#define IRDMA_UDAQPC_DCTCPENABLE BIT_ULL(25) +#define IRDMA_UDAQPC_RCVTPHEN_S IRDMAQPC_RCVTPHEN_S +#define IRDMA_UDAQPC_RCVTPHEN IRDMAQPC_RCVTPHEN +#define IRDMA_UDAQPC_XMITTPHEN_S IRDMAQPC_XMITTPHEN_S +#define IRDMA_UDAQPC_XMITTPHEN IRDMAQPC_XMITTPHEN +#define IRDMA_UDAQPC_RQTPHEN_S IRDMAQPC_RQTPHEN_S +#define IRDMA_UDAQPC_RQTPHEN IRDMAQPC_RQTPHEN +#define IRDMA_UDAQPC_SQTPHEN_S IRDMAQPC_SQTPHEN_S +#define IRDMA_UDAQPC_SQTPHEN IRDMAQPC_SQTPHEN +#define IRDMA_UDAQPC_PPIDX_S IRDMAQPC_PPIDX_S +#define IRDMA_UDAQPC_PPIDX IRDMAQPC_PPIDX +#define IRDMA_UDAQPC_PMENA_S IRDMAQPC_PMENA_S +#define IRDMA_UDAQPC_PMENA IRDMAQPC_PMENA +#define IRDMA_UDAQPC_INSERTTAG2_S 11 +#define IRDMA_UDAQPC_INSERTTAG2 BIT_ULL(11) +#define IRDMA_UDAQPC_INSERTTAG3_S 14 +#define IRDMA_UDAQPC_INSERTTAG3 BIT_ULL(14) +#define IRDMA_UDAQPC_RQSIZE_S IRDMAQPC_RQSIZE_S +#define IRDMA_UDAQPC_RQSIZE IRDMAQPC_RQSIZE +#define IRDMA_UDAQPC_SQSIZE_S IRDMAQPC_SQSIZE_S +#define IRDMA_UDAQPC_SQSIZE IRDMAQPC_SQSIZE +#define IRDMA_UDAQPC_TXCQNUM_S IRDMAQPC_TXCQNUM_S +#define IRDMA_UDAQPC_TXCQNUM IRDMAQPC_TXCQNUM +#define IRDMA_UDAQPC_RXCQNUM_S IRDMAQPC_RXCQNUM_S +#define IRDMA_UDAQPC_RXCQNUM IRDMAQPC_RXCQNUM +#define IRDMA_UDAQPC_QPCOMPCTX_S IRDMAQPC_QPCOMPCTX_S +#define IRDMA_UDAQPC_QPCOMPCTX IRDMAQPC_QPCOMPCTX +#define IRDMA_UDAQPC_SQTPHVAL_S IRDMAQPC_SQTPHVAL_S +#define IRDMA_UDAQPC_SQTPHVAL IRDMAQPC_SQTPHVAL +#define IRDMA_UDAQPC_RQTPHVAL_S IRDMAQPC_RQTPHVAL_S +#define IRDMA_UDAQPC_RQTPHVAL IRDMAQPC_RQTPHVAL +#define IRDMA_UDAQPC_QSHANDLE_S IRDMAQPC_QSHANDLE_S +#define IRDMA_UDAQPC_QSHANDLE IRDMAQPC_QSHANDLE +#define IRDMA_UDAQPC_RQHDRRINGBUFSIZE_S 48 +#define IRDMA_UDAQPC_RQHDRRINGBUFSIZE GENMASK_ULL(49, 48) +#define IRDMA_UDAQPC_SQHDRRINGBUFSIZE_S 32 +#define IRDMA_UDAQPC_SQHDRRINGBUFSIZE GENMASK_ULL(33, 32) +#define IRDMA_UDAQPC_PRIVILEGEENABLE_S 25 +#define IRDMA_UDAQPC_PRIVILEGEENABLE BIT_ULL(25) +#define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE_S 26 +#define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE BIT_ULL(26) +#define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX_S 0 +#define IRDMA_UDAQPC_STATISTICS_INSTANCE_INDEX GENMASK_ULL(6, 0) +#define IRDMA_UDAQPC_PRIVHDRGENENABLE_S 0 +#define IRDMA_UDAQPC_PRIVHDRGENENABLE BIT_ULL(0) +#define IRDMA_UDAQPC_RQHDRSPLITENABLE_S 3 +#define IRDMA_UDAQPC_RQHDRSPLITENABLE BIT_ULL(3) +#define IRDMA_UDAQPC_RQHDRRINGBUFENABLE_S 2 +#define IRDMA_UDAQPC_RQHDRRINGBUFENABLE BIT_ULL(2) +#define IRDMA_UDAQPC_SQHDRRINGBUFENABLE_S 1 +#define IRDMA_UDAQPC_SQHDRRINGBUFENABLE BIT_ULL(1) +#define IRDMA_UDAQPC_IPID_S 32 +#define IRDMA_UDAQPC_IPID GENMASK_ULL(47, 32) +#define IRDMA_UDAQPC_SNDMSS_S 16 +#define IRDMA_UDAQPC_SNDMSS GENMASK_ULL(29, 16) +#define IRDMA_UDAQPC_VLANTAG_S 0 +#define IRDMA_UDAQPC_VLANTAG GENMASK_ULL(15, 0) +#define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI_S 20 +#define IRDMA_UDA_CQPSQ_MAV_PDINDEXHI GENMASK_ULL(27, 20) +#define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO_S 48 +#define IRDMA_UDA_CQPSQ_MAV_PDINDEXLO GENMASK_ULL(63, 48) +#define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX_S 24 +#define IRDMA_UDA_CQPSQ_MAV_SRCMACADDRINDEX GENMASK_ULL(29, 24) +#define IRDMA_UDA_CQPSQ_MAV_ARPINDEX_S 48 +#define IRDMA_UDA_CQPSQ_MAV_ARPINDEX GENMASK_ULL(63, 48) +#define IRDMA_UDA_CQPSQ_MAV_TC_S 32 +#define IRDMA_UDA_CQPSQ_MAV_TC GENMASK_ULL(39, 32) +#define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT_S 32 +#define IRDMA_UDA_CQPSQ_MAV_HOPLIMIT GENMASK_ULL(39, 32) +#define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL_S 0 +#define IRDMA_UDA_CQPSQ_MAV_FLOWLABEL GENMASK_ULL(19, 0) +#define IRDMA_UDA_CQPSQ_MAV_ADDR0_S 32 +#define IRDMA_UDA_CQPSQ_MAV_ADDR0 GENMASK_ULL(63, 32) +#define IRDMA_UDA_CQPSQ_MAV_ADDR1_S 0 +#define IRDMA_UDA_CQPSQ_MAV_ADDR1 GENMASK_ULL(31, 0) +#define IRDMA_UDA_CQPSQ_MAV_ADDR2_S 32 +#define IRDMA_UDA_CQPSQ_MAV_ADDR2 GENMASK_ULL(63, 32) +#define IRDMA_UDA_CQPSQ_MAV_ADDR3_S 0 +#define IRDMA_UDA_CQPSQ_MAV_ADDR3 GENMASK_ULL(31, 0) +#define IRDMA_UDA_CQPSQ_MAV_WQEVALID_S 63 +#define IRDMA_UDA_CQPSQ_MAV_WQEVALID BIT_ULL(63) +#define IRDMA_UDA_CQPSQ_MAV_OPCODE_S 32 +#define IRDMA_UDA_CQPSQ_MAV_OPCODE GENMASK_ULL(37, 32) +#define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK_S 62 +#define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK BIT_ULL(62) +#define IRDMA_UDA_CQPSQ_MAV_IPV4VALID_S 59 +#define IRDMA_UDA_CQPSQ_MAV_IPV4VALID BIT_ULL(59) + +#define IRDMA_UDA_CQPSQ_MAV_AVIDX_S 0 +#define IRDMA_UDA_CQPSQ_MAV_AVIDX GENMASK_ULL(23, 0) +#define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG_S 60 +#define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG BIT_ULL(60) +#define IRDMA_UDA_MGCTX_VFFLAG_S 29 +#define IRDMA_UDA_MGCTX_VFFLAG BIT_ULL(29) +#define IRDMA_UDA_MGCTX_DESTPORT_S 32 +#define IRDMA_UDA_MGCTX_DESTPORT GENMASK_ULL(47, 32) +#define IRDMA_UDA_MGCTX_VFID_S 22 +#define IRDMA_UDA_MGCTX_VFID GENMASK_ULL(28, 22) +#define IRDMA_UDA_MGCTX_VALIDENT_S 31 +#define IRDMA_UDA_MGCTX_VALIDENT BIT_ULL(31) +#define IRDMA_UDA_MGCTX_PFID_S 18 +#define IRDMA_UDA_MGCTX_PFID GENMASK_ULL(21, 18) +#define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT_S 30 +#define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT BIT_ULL(30) +#define IRDMA_UDA_MGCTX_QPID_S 0 +#define IRDMA_UDA_MGCTX_QPID GENMASK_ULL(17, 0) +#define IRDMA_UDA_CQPSQ_MG_WQEVALID_S 63 +#define IRDMA_UDA_CQPSQ_MG_WQEVALID BIT_ULL(63) +#define IRDMA_UDA_CQPSQ_MG_OPCODE_S 32 +#define IRDMA_UDA_CQPSQ_MG_OPCODE GENMASK_ULL(37, 32) +#define IRDMA_UDA_CQPSQ_MG_MGIDX_S 0 +#define IRDMA_UDA_CQPSQ_MG_MGIDX GENMASK_ULL(12, 0) +#define IRDMA_UDA_CQPSQ_MG_IPV4VALID_S 60 +#define IRDMA_UDA_CQPSQ_MG_IPV4VALID BIT_ULL(60) +#define IRDMA_UDA_CQPSQ_MG_VLANVALID_S 59 +#define IRDMA_UDA_CQPSQ_MG_VLANVALID BIT_ULL(59) +#define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID_S 0 +#define IRDMA_UDA_CQPSQ_MG_HMC_FCN_ID GENMASK_ULL(5, 0) +#define IRDMA_UDA_CQPSQ_MG_VLANID_S 32 +#define IRDMA_UDA_CQPSQ_MG_VLANID GENMASK_ULL(43, 32) +#define IRDMA_UDA_CQPSQ_QS_HANDLE_S 0 +#define IRDMA_UDA_CQPSQ_QS_HANDLE GENMASK_ULL(9, 0) +#define IRDMA_UDA_CQPSQ_QHASH_QPN_S 32 +#define IRDMA_UDA_CQPSQ_QHASH_QPN GENMASK_ULL(49, 32) +#define IRDMA_UDA_CQPSQ_QHASH__S 0 +#define IRDMA_UDA_CQPSQ_QHASH_ BIT_ULL(0) +#define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT_S 16 +#define IRDMA_UDA_CQPSQ_QHASH_SRC_PORT GENMASK_ULL(31, 16) +#define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT_S 0 +#define IRDMA_UDA_CQPSQ_QHASH_DEST_PORT GENMASK_ULL(15, 0) +#define IRDMA_UDA_CQPSQ_QHASH_ADDR0_S 32 +#define IRDMA_UDA_CQPSQ_QHASH_ADDR0 GENMASK_ULL(63, 32) +#define IRDMA_UDA_CQPSQ_QHASH_ADDR1_S 0 +#define IRDMA_UDA_CQPSQ_QHASH_ADDR1 GENMASK_ULL(31, 0) +#define IRDMA_UDA_CQPSQ_QHASH_ADDR2_S 32 +#define IRDMA_UDA_CQPSQ_QHASH_ADDR2 GENMASK_ULL(63, 32) +#define IRDMA_UDA_CQPSQ_QHASH_ADDR3_S 0 +#define IRDMA_UDA_CQPSQ_QHASH_ADDR3 GENMASK_ULL(31, 0) +#define IRDMA_UDA_CQPSQ_QHASH_WQEVALID_S 63 +#define IRDMA_UDA_CQPSQ_QHASH_WQEVALID BIT_ULL(63) +#define IRDMA_UDA_CQPSQ_QHASH_OPCODE_S 32 +#define IRDMA_UDA_CQPSQ_QHASH_OPCODE GENMASK_ULL(37, 32) +#define IRDMA_UDA_CQPSQ_QHASH_MANAGE_S 61 +#define IRDMA_UDA_CQPSQ_QHASH_MANAGE GENMASK_ULL(62, 61) +#define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID_S 60 +#define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60) +#define IRDMA_UDA_CQPSQ_QHASH_LANFWD_S 59 +#define IRDMA_UDA_CQPSQ_QHASH_LANFWD BIT_ULL(59) +#define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE_S 42 +#define IRDMA_UDA_CQPSQ_QHASH_ENTRYTYPE GENMASK_ULL(44, 42) +#endif /* IRDMA_UDA_D_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/uk.c b/drivers/intel/irdma-1.14.33/src/irdma/uk.c new file mode 100644 index 000000000..735e11b7d --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/uk.c @@ -0,0 +1,2244 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "osdep.h" +#include "defs.h" +#include "user.h" +#include "irdma.h" + +/** + * irdma_set_fragment - set fragment in wqe + * @wqe: wqe for setting fragment + * @offset: offset value + * @sge: sge length and stag + * @valid: The wqe valid + */ +static void irdma_set_fragment(__le64 *wqe, u32 offset, struct ib_sge *sge, + u8 valid) +{ + if (sge) { + set_64bit_val(wqe, offset, + FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); + set_64bit_val(wqe, offset + 8, + FIELD_PREP(IRDMAQPSQ_VALID, valid) | + FIELD_PREP(IRDMAQPSQ_FRAG_LEN, sge->length) | + FIELD_PREP(IRDMAQPSQ_FRAG_STAG, sge->lkey)); + } else { + set_64bit_val(wqe, offset, 0); + set_64bit_val(wqe, offset + 8, + FIELD_PREP(IRDMAQPSQ_VALID, valid)); + } +} + +/** + * irdma_set_fragment_gen_1 - set fragment in wqe + * @wqe: wqe for setting fragment + * @offset: offset value + * @sge: sge length and stag + * @valid: wqe valid flag + */ +static void irdma_set_fragment_gen_1(__le64 *wqe, u32 offset, + struct ib_sge *sge, u8 valid) +{ + if (sge) { + set_64bit_val(wqe, offset, + FIELD_PREP(IRDMAQPSQ_FRAG_TO, sge->addr)); + set_64bit_val(wqe, offset + 8, + FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_LEN, sge->length) | + FIELD_PREP(IRDMAQPSQ_GEN1_FRAG_STAG, sge->lkey)); + } else { + set_64bit_val(wqe, offset, 0); + set_64bit_val(wqe, offset + 8, 0); + } +} + +/** + * irdma_nop_hdr - Format header section of noop WQE + * @qp: hw qp ptr + */ +static inline u64 irdma_nop_hdr(struct irdma_qp_uk *qp) +{ + return FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_NOP) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, false) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); +} + +/** + * irdma_nop_1 - insert a NOP wqe + * @qp: hw qp ptr + */ +static int irdma_nop_1(struct irdma_qp_uk *qp) +{ + __le64 *wqe; + u32 wqe_idx; + + if (!qp->sq_ring.head) + return -EINVAL; + + wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); + wqe = qp->sq_base[wqe_idx].elem; + + qp->sq_wrtrk_array[wqe_idx].quanta = IRDMA_QP_WQE_MIN_QUANTA; + + set_64bit_val(wqe, 0, 0); + set_64bit_val(wqe, 8, 0); + set_64bit_val(wqe, 16, 0); + + /* make sure WQE is written before valid bit is set */ + dma_wmb(); + + set_64bit_val(wqe, 24, irdma_nop_hdr(qp)); + + return 0; +} + +/** + * irdma_clr_wqes - clear next 128 sq entries + * @qp: hw qp ptr + * @qp_wqe_idx: wqe_idx + */ +void irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx) +{ + struct irdma_qp_quanta *sq; + u32 wqe_idx; + + if (!(qp_wqe_idx & 0x7F)) { + wqe_idx = (qp_wqe_idx + 128) % qp->sq_ring.size; + sq = qp->sq_base + wqe_idx; + if (wqe_idx) + memset(sq, qp->swqe_polarity ? 0 : 0xFF, + 128 * sizeof(*sq)); + else + memset(sq, qp->swqe_polarity ? 0xFF : 0, + 128 * sizeof(*sq)); + } +} + +/** + * irdma_uk_qp_post_wr - ring doorbell + * @qp: hw qp ptr + */ +void irdma_uk_qp_post_wr(struct irdma_qp_uk *qp) +{ + u64 temp; + u32 hw_sq_tail; + u32 sw_sq_head; + + /* valid bit is written before reading shadow */ + mb(); + + /* read the doorbell shadow area */ + get_64bit_val(qp->shadow_area, 0, &temp); + + hw_sq_tail = (u32)FIELD_GET(IRDMA_QP_DBSA_HW_SQ_TAIL, temp); + sw_sq_head = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); + if (qp->push_dropped) { + writel(qp->qp_id, qp->wqe_alloc_db); + qp->push_dropped = false; + } else if (sw_sq_head != hw_sq_tail) { + if (sw_sq_head > qp->initial_ring.head) { + if (hw_sq_tail >= qp->initial_ring.head && + hw_sq_tail < sw_sq_head) + writel(qp->qp_id, qp->wqe_alloc_db); + } else { + writel(qp->qp_id, qp->wqe_alloc_db); + } + } + + qp->initial_ring.head = qp->sq_ring.head; +} + +/** + * irdma_qp_ring_push_db - ring qp doorbell + * @qp: hw qp ptr + * @wqe_idx: wqe index + */ +static void irdma_qp_ring_push_db(struct irdma_qp_uk *qp, u32 wqe_idx) +{ + set_32bit_val(qp->push_db, 0, + FIELD_PREP(IRDMA_WQEALLOC_WQE_DESC_INDEX, wqe_idx >> 3) | qp->qp_id); + qp->initial_ring.head = qp->sq_ring.head; + qp->push_mode = true; + qp->push_dropped = false; +} + +void irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 *wqe, u16 quanta, + u32 wqe_idx, bool post_sq) +{ + __le64 *push; + + if (IRDMA_RING_CURRENT_HEAD(qp->initial_ring) != + IRDMA_RING_CURRENT_TAIL(qp->sq_ring) && + !qp->push_mode) { + irdma_uk_qp_post_wr(qp); + } else { + push = (__le64 *)((uintptr_t)qp->push_wqe + + (wqe_idx & 0x7) * 0x20); + memcpy(push, wqe, quanta * IRDMA_QP_WQE_MIN_SIZE); + irdma_qp_ring_push_db(qp, wqe_idx); + } +} + +/** + * irdma_qp_get_next_send_wqe - pad with NOP if needed, return where next WR should go + * @qp: hw qp ptr + * @wqe_idx: return wqe index + * @quanta: (in/out) ptr to size of WR in quanta. Modified in case pad is needed + * @total_size: size of WR in bytes + * @info: info on WR + */ +__le64 *irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx, + u16 *quanta, u32 total_size, + struct irdma_post_sq_info *info) +{ + __le64 *wqe; + __le64 *wqe_0 = NULL; + u32 nop_wqe_idx; + u16 wqe_quanta = *quanta; + bool push_wqe_pad = false; + u16 avail_quanta; + u16 i; + + if (info->push_wqe && (*quanta & 0x1)) { + *quanta = *quanta + 1; + push_wqe_pad = true; + } + avail_quanta = qp->uk_attrs->max_hw_sq_chunk - + (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) % + qp->uk_attrs->max_hw_sq_chunk); + + if (*quanta <= avail_quanta) { + /* WR fits in current chunk */ + if (*quanta > IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring)) + return NULL; + } else { + /* Need to pad with NOP */ + if (*quanta + avail_quanta > + IRDMA_SQ_RING_FREE_QUANTA(qp->sq_ring)) + return NULL; + + nop_wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); + for (i = 0; i < avail_quanta; i++) { + irdma_nop_1(qp); + IRDMA_RING_MOVE_HEAD_NOCHECK(qp->sq_ring); + } + if (qp->push_db && info->push_wqe) + irdma_qp_push_wqe(qp, qp->sq_base[nop_wqe_idx].elem, + avail_quanta, nop_wqe_idx, true); + } + + *wqe_idx = IRDMA_RING_CURRENT_HEAD(qp->sq_ring); + if (!*wqe_idx) + qp->swqe_polarity = !qp->swqe_polarity; + + IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, *quanta); + + irdma_clr_wqes(qp, *wqe_idx); + + wqe = qp->sq_base[*wqe_idx].elem; + if (qp->uk_attrs->hw_rev == IRDMA_GEN_1 && wqe_quanta == 1 && + (IRDMA_RING_CURRENT_HEAD(qp->sq_ring) & 1)) { + wqe_0 = qp->sq_base[IRDMA_RING_CURRENT_HEAD(qp->sq_ring)].elem; + wqe_0[3] = cpu_to_le64(FIELD_PREP(IRDMAQPSQ_VALID, + qp->swqe_polarity ? 0 : 1)); + } + qp->sq_wrtrk_array[*wqe_idx].wrid = info->wr_id; + qp->sq_wrtrk_array[*wqe_idx].wr_len = total_size; + qp->sq_wrtrk_array[*wqe_idx].quanta = wqe_quanta; + + /* Push mode to WC memory requires multiples of 64-byte block writes. */ + if (push_wqe_pad) { + __le64 *push_wqe; + + nop_wqe_idx = *wqe_idx + wqe_quanta; + push_wqe = qp->sq_base[nop_wqe_idx].elem; + qp->sq_wrtrk_array[nop_wqe_idx].quanta = IRDMA_QP_WQE_MIN_QUANTA; + + set_64bit_val(push_wqe, 0, 0); + set_64bit_val(push_wqe, 8, 0); + set_64bit_val(push_wqe, 16, 0); + set_64bit_val(push_wqe, 24, irdma_nop_hdr(qp)); + } + + return wqe; +} + +__le64 *irdma_srq_get_next_recv_wqe(struct irdma_srq_uk *srq, u32 *wqe_idx) +{ + int ret_code; + __le64 *wqe; + + if (IRDMA_RING_FULL_ERR(srq->srq_ring)) + return NULL; + + IRDMA_ATOMIC_RING_MOVE_HEAD(srq->srq_ring, *wqe_idx, ret_code); + if (ret_code) + return NULL; + + if (!*wqe_idx) + srq->srwqe_polarity = !srq->srwqe_polarity; + wqe = srq->srq_base[*wqe_idx * srq->wqe_size_multiplier].elem; + + return wqe; +} + +/** + * irdma_qp_get_next_recv_wqe - get next qp's rcv wqe + * @qp: hw qp ptr + * @wqe_idx: return wqe index + */ +__le64 *irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx) +{ + __le64 *wqe; + int ret_code; + + if (IRDMA_RING_FULL_ERR(qp->rq_ring)) + return NULL; + + IRDMA_ATOMIC_RING_MOVE_HEAD(qp->rq_ring, *wqe_idx, ret_code); + if (ret_code) + return NULL; + + if (!*wqe_idx) + qp->rwqe_polarity = !qp->rwqe_polarity; + /* rq_wqe_size_multiplier is no of 32 byte quanta in one rq wqe */ + wqe = qp->rq_base[*wqe_idx * qp->rq_wqe_size_multiplier].elem; + + return wqe; +} + +/** + * irdma_uk_rdma_write - rdma write operation + * @qp: hw qp ptr + * @info: post sq information + * @post_sq: flag to post sq + */ +int irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, + bool post_sq) +{ + u64 hdr; + __le64 *wqe; + struct irdma_rdma_write *op_info; + u32 i, wqe_idx; + u32 total_size = 0, byte_off; + int ret_code; + u32 frag_cnt, addl_frag_cnt; + bool read_fence = false; + u16 quanta; + + info->push_wqe = qp->push_db ? true : false; + + op_info = &info->op.rdma_write; + if (op_info->num_lo_sges > qp->max_sq_frag_cnt) + return -EINVAL; + + for (i = 0; i < op_info->num_lo_sges; i++) + total_size += op_info->lo_sg_list[i].length; + + read_fence |= info->read_fence; + + if (info->imm_data_valid) + frag_cnt = op_info->num_lo_sges + 1; + else + frag_cnt = op_info->num_lo_sges; + addl_frag_cnt = frag_cnt > 1 ? (frag_cnt - 1) : 0; + ret_code = irdma_fragcnt_to_quanta_sq(frag_cnt, &quanta); + if (ret_code) + return ret_code; + + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.addr)); + + if (info->imm_data_valid) { + set_64bit_val(wqe, 0, + FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); + i = 0; + } else { + qp->wqe_ops.iw_set_fragment(wqe, 0, + op_info->lo_sg_list, + qp->swqe_polarity); + i = 1; + } + + for (byte_off = 32; i < op_info->num_lo_sges; i++) { + qp->wqe_ops.iw_set_fragment(wqe, byte_off, + &op_info->lo_sg_list[i], + qp->swqe_polarity); + byte_off += 16; + } + + /* if not an odd number set valid bit in next fragment */ + if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(frag_cnt & 0x01) && + frag_cnt) { + qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, + qp->swqe_polarity); + if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) + ++addl_frag_cnt; + } + + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.lkey) | + FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | + FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, info->imm_data_valid) | + FIELD_PREP(IRDMAQPSQ_REPORTRTT, info->report_rtt) | + FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +int irdma_uk_atomic_write(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq) +{ + struct irdma_atomic_write *op_info; + u32 total_size = 0; + u32 wqe_idx; + u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; + __le64 *wqe; + u64 hdr; + + info->push_wqe = qp->push_db ? true : false; + + op_info = &info->op.atomic_write; + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, op_info->tagged_offset); + if (op_info->is_inline_data) + set_64bit_val(wqe, 8, op_info->inline_data); + else { + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_LOCSTAG, op_info->stag) | + FIELD_PREP(IRDMAQPSQ_FRAG_LEN, IRDMAQP_ATOMIC_WRITE_FRAG_LEN) | + FIELD_PREP(IRDMAQPSQ_FRAG_VALID, qp->swqe_polarity)); + } + set_64bit_val(wqe, 16, op_info->remote_tagged_offset); + + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->remote_stag) | + FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, op_info->is_inline_data) | + FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_ATOMIC_WRITE) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +int irdma_uk_flush_mem_region(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq) +{ + struct irdma_flush_mem_region *op_info; + u32 total_size = 0; + u32 wqe_idx; + u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; + __le64 *wqe; + u64 hdr; + + info->push_wqe = qp->push_db ? true : false; + + op_info = &info->op.flush_mem_region; + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_FLUSH_MEM_LEN, op_info->length)); + set_64bit_val(wqe, 16, op_info->remote_tagged_offset); + + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->remote_stag) | + FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_FLUSH_MEM_REGION) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_PLACEMENT_TYPE, op_info->placement_type) | + FIELD_PREP(IRDMAQPSQ_SELECTIVITY, op_info->selectivity) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +/** + * irdma_uk_atomic_fetch_add - atomic fetch and add operation + * @qp: hw qp ptr + * @info: post sq information + * @post_sq: flag to post sq + */ +int irdma_uk_atomic_fetch_add(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq) +{ + struct irdma_atomic_fetch_add *op_info; + u32 total_size = 0; + u16 quanta = 2; + u32 wqe_idx; + __le64 *wqe; + u64 hdr; + + info->push_wqe = qp->push_db ? true : false; + + op_info = &info->op.atomic_fetch_add; + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, op_info->tagged_offset); + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_LOCSTAG, op_info->stag)); + set_64bit_val(wqe, 16, op_info->remote_tagged_offset); + + hdr = FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, 1) | + FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->remote_stag) | + FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_ATOMIC_FETCH_ADD) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + set_64bit_val(wqe, 32, op_info->fetch_add_data_bytes); + set_64bit_val(wqe, 40, 0); + set_64bit_val(wqe, 48, 0); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity)); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +/** + * irdma_uk_atomic_compare_swap - atomic compare and swap operation + * @qp: hw qp ptr + * @info: post sq information + * @post_sq: flag to post sq + */ +int irdma_uk_atomic_compare_swap(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq) +{ + struct irdma_atomic_compare_swap *op_info; + u32 total_size = 0; + u16 quanta = 2; + u32 wqe_idx; + __le64 *wqe; + u64 hdr; + + info->push_wqe = qp->push_db ? true : false; + + op_info = &info->op.atomic_compare_swap; + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 0, op_info->tagged_offset); + set_64bit_val(wqe, 8, + FIELD_PREP(IRDMAQPSQ_LOCSTAG, op_info->stag)); + set_64bit_val(wqe, 16, op_info->remote_tagged_offset); + + hdr = FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, 1) | + FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->remote_stag) | + FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMAQP_OP_ATOMIC_COMPARE_SWAP_ADD) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + set_64bit_val(wqe, 32, op_info->swap_data_bytes); + set_64bit_val(wqe, 40, op_info->compare_data_bytes); + set_64bit_val(wqe, 48, 0); + set_64bit_val(wqe, 56, + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity)); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +/** + * irdma_uk_srq_post_receive - post a receive wqe to a shared rq + * @srq: shared rq ptr + * @info: post rq information + */ +int irdma_uk_srq_post_receive(struct irdma_srq_uk *srq, + struct irdma_post_rq_info *info) +{ + u32 wqe_idx, i, byte_off; + u32 addl_frag_cnt; + __le64 *wqe; + u64 hdr; + + if (srq->max_srq_frag_cnt < info->num_sges) + return -EINVAL; + + wqe = irdma_srq_get_next_recv_wqe(srq, &wqe_idx); + if (!wqe) + return -ENOMEM; + + addl_frag_cnt = info->num_sges > 1 ? info->num_sges - 1 : 0; + srq->wqe_ops.iw_set_fragment(wqe, 0, info->sg_list, + srq->srwqe_polarity); + + for (i = 1, byte_off = 32; i < info->num_sges; i++) { + srq->wqe_ops.iw_set_fragment(wqe, byte_off, &info->sg_list[i], + srq->srwqe_polarity); + byte_off += 16; + } + + /* if not an odd number set valid bit in next fragment */ + if (srq->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(info->num_sges & 0x01) && + info->num_sges) { + srq->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, + srq->srwqe_polarity); + if (srq->uk_attrs->hw_rev == IRDMA_GEN_2) + ++addl_frag_cnt; + } + + set_64bit_val(wqe, 16, (u64)info->wr_id); + hdr = FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | + FIELD_PREP(IRDMAQPSQ_VALID, srq->srwqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + set_64bit_val(srq->shadow_area, 0, (wqe_idx + 1) % srq->srq_ring.size); + + return 0; +} +/** + * irdma_uk_rdma_read - rdma read command + * @qp: hw qp ptr + * @info: post sq information + * @inv_stag: flag for inv_stag + * @post_sq: flag to post sq + */ +int irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, + bool inv_stag, bool post_sq) +{ + struct irdma_rdma_read *op_info; + int ret_code; + u32 i, byte_off, total_size = 0; + bool local_fence = false; + bool ord_fence = false; + u32 addl_frag_cnt; + __le64 *wqe; + u32 wqe_idx; + u16 quanta; + u64 hdr; + + info->push_wqe = qp->push_db ? true : false; + + op_info = &info->op.rdma_read; + if (qp->max_sq_frag_cnt < op_info->num_lo_sges) + return -EINVAL; + + for (i = 0; i < op_info->num_lo_sges; i++) + total_size += op_info->lo_sg_list[i].length; + + ret_code = irdma_fragcnt_to_quanta_sq(op_info->num_lo_sges, &quanta); + if (ret_code) + return ret_code; + + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return -ENOMEM; + + if (qp->rd_fence_rate && (qp->ord_cnt++ == qp->rd_fence_rate)) { + ord_fence = true; + qp->ord_cnt = 0; + } + + addl_frag_cnt = op_info->num_lo_sges > 1 ? + (op_info->num_lo_sges - 1) : 0; + local_fence |= info->local_fence; + + qp->wqe_ops.iw_set_fragment(wqe, 0, op_info->lo_sg_list, + qp->swqe_polarity); + for (i = 1, byte_off = 32; i < op_info->num_lo_sges; ++i) { + qp->wqe_ops.iw_set_fragment(wqe, byte_off, + &op_info->lo_sg_list[i], + qp->swqe_polarity); + byte_off += 16; + } + + /* if not an odd number set valid bit in next fragment */ + if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && + !(op_info->num_lo_sges & 0x01) && op_info->num_lo_sges) { + qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, + qp->swqe_polarity); + if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) + ++addl_frag_cnt; + } + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.addr)); + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.lkey) | + FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | + FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | + FIELD_PREP(IRDMAQPSQ_OPCODE, + (inv_stag ? IRDMAQP_OP_RDMA_READ_LOC_INV : IRDMAQP_OP_RDMA_READ)) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, + info->read_fence || ord_fence ? 1 : 0) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +/** + * irdma_uk_send - rdma send command + * @qp: hw qp ptr + * @info: post sq information + * @post_sq: flag to post sq + */ +int irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, + bool post_sq) +{ + __le64 *wqe; + struct irdma_post_send *op_info; + u64 hdr; + u32 i, wqe_idx, total_size = 0, byte_off; + int ret_code; + u32 frag_cnt, addl_frag_cnt; + bool read_fence = false; + u16 quanta; + + info->push_wqe = qp->push_db ? true : false; + + op_info = &info->op.send; + if (qp->max_sq_frag_cnt < op_info->num_sges) + return -EINVAL; + + for (i = 0; i < op_info->num_sges; i++) + total_size += op_info->sg_list[i].length; + + if (info->imm_data_valid) + frag_cnt = op_info->num_sges + 1; + else + frag_cnt = op_info->num_sges; + ret_code = irdma_fragcnt_to_quanta_sq(frag_cnt, &quanta); + if (ret_code) + return ret_code; + + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return -ENOMEM; + + read_fence |= info->read_fence; + addl_frag_cnt = frag_cnt > 1 ? (frag_cnt - 1) : 0; + if (info->imm_data_valid) { + set_64bit_val(wqe, 0, + FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); + i = 0; + } else { + qp->wqe_ops.iw_set_fragment(wqe, 0, + frag_cnt ? op_info->sg_list : NULL, + qp->swqe_polarity); + i = 1; + } + + for (byte_off = 32; i < op_info->num_sges; i++) { + qp->wqe_ops.iw_set_fragment(wqe, byte_off, &op_info->sg_list[i], + qp->swqe_polarity); + byte_off += 16; + } + + /* if not an odd number set valid bit in next fragment */ + if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(frag_cnt & 0x01) && + frag_cnt) { + qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, + qp->swqe_polarity); + if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) + ++addl_frag_cnt; + } + + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_DESTQKEY, op_info->qkey) | + FIELD_PREP(IRDMAQPSQ_DESTQPN, op_info->dest_qp)); + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, info->stag_to_inv) | + FIELD_PREP(IRDMAQPSQ_AHID, op_info->ah_id) | + FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, + (info->imm_data_valid ? 1 : 0)) | + FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | + FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | + FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_UDPHEADER, info->udp_hdr) | + FIELD_PREP(IRDMAQPSQ_L4LEN, info->l4len) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +/** + * irdma_copy_inline_data_gen_1 - Copy inline data to wqe + * @wqe: pointer to wqe + * @sge_list: table of pointers to inline data + * @num_sges: Total inline data length + * @polarity: compatibility parameter + */ +static void irdma_copy_inline_data_gen_1(u8 *wqe, struct ib_sge *sge_list, + u32 num_sges, u8 polarity) +{ + u32 quanta_bytes_remaining = 16; + u32 i; + + for (i = 0; i < num_sges; i++) { + u8 *cur_sge = (u8 *)(uintptr_t)sge_list[i].addr; + u32 sge_len = sge_list[i].length; + + while (sge_len) { + u32 bytes_copied; + + bytes_copied = min(sge_len, quanta_bytes_remaining); + memcpy(wqe, cur_sge, bytes_copied); + wqe += bytes_copied; + cur_sge += bytes_copied; + quanta_bytes_remaining -= bytes_copied; + sge_len -= bytes_copied; + + if (!quanta_bytes_remaining) { + /* Remaining inline bytes reside after hdr */ + wqe += 16; + quanta_bytes_remaining = 32; + } + } + } +} + +/** + * irdma_inline_data_size_to_quanta_gen_1 - based on inline data, quanta + * @data_size: data size for inline + * + * Gets the quanta based on inline and immediate data. + */ +static inline u16 irdma_inline_data_size_to_quanta_gen_1(u32 data_size) +{ + return data_size <= 16 ? IRDMA_QP_WQE_MIN_QUANTA : 2; +} + +/** + * irdma_copy_inline_data - Copy inline data to wqe + * @wqe: pointer to wqe + * @sge_list: table of pointers to inline data + * @num_sges: number of SGE's + * @polarity: polarity of wqe valid bit + */ +static void irdma_copy_inline_data(u8 *wqe, struct ib_sge *sge_list, + u32 num_sges, u8 polarity) +{ + u8 inline_valid = polarity << IRDMA_INLINE_VALID_S; + u32 quanta_bytes_remaining = 8; + u32 i; + bool first_quanta = true; + + wqe += 8; + + for (i = 0; i < num_sges; i++) { + u8 *cur_sge = (u8 *)(uintptr_t)sge_list[i].addr; + u32 sge_len = sge_list[i].length; + + while (sge_len) { + u32 bytes_copied; + + bytes_copied = min(sge_len, quanta_bytes_remaining); + memcpy(wqe, cur_sge, bytes_copied); + wqe += bytes_copied; + cur_sge += bytes_copied; + quanta_bytes_remaining -= bytes_copied; + sge_len -= bytes_copied; + + if (!quanta_bytes_remaining) { + quanta_bytes_remaining = 31; + + /* Remaining inline bytes reside after hdr */ + if (first_quanta) { + first_quanta = false; + wqe += 16; + } else { + *wqe = inline_valid; + wqe++; + } + } + } + } + if (!first_quanta && quanta_bytes_remaining < 31) + *(wqe + quanta_bytes_remaining) = inline_valid; +} + +/** + * irdma_inline_data_size_to_quanta - based on inline data, quanta + * @data_size: data size for inline + * + * Gets the quanta based on inline and immediate data. + */ +static u16 irdma_inline_data_size_to_quanta(u32 data_size) +{ + if (data_size <= 8) + return IRDMA_QP_WQE_MIN_QUANTA; + else if (data_size <= 39) + return 2; + else if (data_size <= 70) + return 3; + else if (data_size <= 101) + return 4; + else if (data_size <= 132) + return 5; + else if (data_size <= 163) + return 6; + else if (data_size <= 194) + return 7; + else + return 8; +} + +/** + * irdma_uk_inline_rdma_write - inline rdma write operation + * @qp: hw qp ptr + * @info: post sq information + * @post_sq: flag to post sq + */ +int irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq) +{ + __le64 *wqe; + struct irdma_rdma_write *op_info; + u64 hdr = 0; + u32 wqe_idx; + bool read_fence = false; + u16 quanta; + u32 i, total_size = 0; + + info->push_wqe = qp->push_db ? true : false; + op_info = &info->op.rdma_write; + + if (unlikely(qp->max_sq_frag_cnt < op_info->num_lo_sges)) + return -EINVAL; + + for (i = 0; i < op_info->num_lo_sges; i++) + total_size += op_info->lo_sg_list[i].length; + + if (unlikely(total_size > qp->max_inline_data)) + return -EINVAL; + + quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(total_size); + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return -ENOMEM; + + read_fence |= info->read_fence; + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_FRAG_TO, op_info->rem_addr.addr)); + + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, op_info->rem_addr.lkey) | + FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | + FIELD_PREP(IRDMAQPSQ_INLINEDATALEN, total_size) | + FIELD_PREP(IRDMAQPSQ_REPORTRTT, info->report_rtt ? 1 : 0) | + FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, 1) | + FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, info->imm_data_valid ? 1 : 0) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe ? 1 : 0) | + FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + if (info->imm_data_valid) + set_64bit_val(wqe, 0, + FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); + + qp->wqe_ops.iw_copy_inline_data((u8 *)wqe, op_info->lo_sg_list, + op_info->num_lo_sges, qp->swqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +/** + * irdma_uk_inline_send - inline send operation + * @qp: hw qp ptr + * @info: post sq information + * @post_sq: flag to post sq + */ +int irdma_uk_inline_send(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq) +{ + __le64 *wqe; + struct irdma_post_send *op_info; + u64 hdr; + u32 wqe_idx; + bool read_fence = false; + u16 quanta; + u32 i, total_size = 0; + + info->push_wqe = qp->push_db ? true : false; + op_info = &info->op.send; + + if (unlikely(qp->max_sq_frag_cnt < op_info->num_sges)) + return -EINVAL; + + for (i = 0; i < op_info->num_sges; i++) + total_size += op_info->sg_list[i].length; + + if (unlikely(total_size > qp->max_inline_data)) + return -EINVAL; + + quanta = qp->wqe_ops.iw_inline_data_size_to_quanta(total_size); + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, total_size, info); + if (!wqe) + return -ENOMEM; + + set_64bit_val(wqe, 16, + FIELD_PREP(IRDMAQPSQ_DESTQKEY, op_info->qkey) | + FIELD_PREP(IRDMAQPSQ_DESTQPN, op_info->dest_qp)); + + read_fence |= info->read_fence; + hdr = FIELD_PREP(IRDMAQPSQ_REMSTAG, info->stag_to_inv) | + FIELD_PREP(IRDMAQPSQ_AHID, op_info->ah_id) | + FIELD_PREP(IRDMAQPSQ_OPCODE, info->op_type) | + FIELD_PREP(IRDMAQPSQ_INLINEDATALEN, total_size) | + FIELD_PREP(IRDMAQPSQ_IMMDATAFLAG, + (info->imm_data_valid ? 1 : 0)) | + FIELD_PREP(IRDMAQPSQ_REPORTRTT, (info->report_rtt ? 1 : 0)) | + FIELD_PREP(IRDMAQPSQ_INLINEDATAFLAG, 1) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, info->local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_UDPHEADER, info->udp_hdr) | + FIELD_PREP(IRDMAQPSQ_L4LEN, info->l4len) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + if (info->imm_data_valid) + set_64bit_val(wqe, 0, + FIELD_PREP(IRDMAQPSQ_IMMDATA, info->imm_data)); + qp->wqe_ops.iw_copy_inline_data((u8 *)wqe, op_info->sg_list, + op_info->num_sges, qp->swqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +/** + * irdma_uk_stag_local_invalidate - stag invalidate operation + * @qp: hw qp ptr + * @info: post sq information + * @post_sq: flag to post sq + */ +int irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, + bool post_sq) +{ + __le64 *wqe; + struct irdma_inv_local_stag *op_info; + u64 hdr; + u32 wqe_idx; + bool local_fence = false; + struct ib_sge sge = {}; + u16 quanta = IRDMA_QP_WQE_MIN_QUANTA; + + info->push_wqe = qp->push_db ? true : false; + op_info = &info->op.inv_local_stag; + local_fence = info->local_fence; + + wqe = irdma_qp_get_next_send_wqe(qp, &wqe_idx, &quanta, 0, info); + if (!wqe) + return -ENOMEM; + + sge.lkey = op_info->target_stag; + qp->wqe_ops.iw_set_fragment(wqe, 0, &sge, 0); + + set_64bit_val(wqe, 16, 0); + + hdr = FIELD_PREP(IRDMAQPSQ_OPCODE, IRDMA_OP_TYPE_INV_STAG) | + FIELD_PREP(IRDMAQPSQ_PUSHWQE, info->push_wqe) | + FIELD_PREP(IRDMAQPSQ_READFENCE, info->read_fence) | + FIELD_PREP(IRDMAQPSQ_LOCALFENCE, local_fence) | + FIELD_PREP(IRDMAQPSQ_SIGCOMPL, info->signaled) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->swqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + if (info->push_wqe) + irdma_qp_push_wqe(qp, wqe, quanta, wqe_idx, post_sq); + else if (post_sq) + irdma_uk_qp_post_wr(qp); + + return 0; +} + +/** + * irdma_uk_post_receive - post receive wqe + * @qp: hw qp ptr + * @info: post rq information + */ +int irdma_uk_post_receive(struct irdma_qp_uk *qp, + struct irdma_post_rq_info *info) +{ + u32 wqe_idx, i, byte_off; + u32 addl_frag_cnt; + __le64 *wqe; + u64 hdr; + + if (qp->max_rq_frag_cnt < info->num_sges) + return -EINVAL; + + wqe = irdma_qp_get_next_recv_wqe(qp, &wqe_idx); + if (!wqe) + return -ENOMEM; + + qp->rq_wrid_array[wqe_idx] = info->wr_id; + addl_frag_cnt = info->num_sges > 1 ? (info->num_sges - 1) : 0; + qp->wqe_ops.iw_set_fragment(wqe, 0, info->sg_list, + qp->rwqe_polarity); + + for (i = 1, byte_off = 32; i < info->num_sges; i++) { + qp->wqe_ops.iw_set_fragment(wqe, byte_off, &info->sg_list[i], + qp->rwqe_polarity); + byte_off += 16; + } + + /* if not an odd number set valid bit in next fragment */ + if (qp->uk_attrs->hw_rev >= IRDMA_GEN_2 && !(info->num_sges & 0x01) && + info->num_sges) { + qp->wqe_ops.iw_set_fragment(wqe, byte_off, NULL, + qp->rwqe_polarity); + if (qp->uk_attrs->hw_rev == IRDMA_GEN_2) + ++addl_frag_cnt; + } + + set_64bit_val(wqe, 16, 0); + hdr = FIELD_PREP(IRDMAQPSQ_ADDFRAGCNT, addl_frag_cnt) | + FIELD_PREP(IRDMAQPSQ_VALID, qp->rwqe_polarity); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + set_64bit_val(wqe, 24, hdr); + + return 0; +} + +/** + * irdma_uk_cq_resize - reset the cq buffer info + * @cq: cq to resize + * @cq_base: new cq buffer addr + * @cq_size: number of cqes + */ +void irdma_uk_cq_resize(struct irdma_cq_uk *cq, void *cq_base, int cq_size) +{ + cq->cq_base = cq_base; + cq->cq_size = cq_size; + IRDMA_RING_INIT(cq->cq_ring, cq->cq_size); + cq->polarity = 1; +} + +/** + * irdma_uk_cq_set_resized_cnt - record the count of the resized buffers + * @cq: cq to resize + * @cq_cnt: the count of the resized cq buffers + */ +void irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *cq, u16 cq_cnt) +{ + u64 temp_val; + u16 sw_cq_sel; + u8 arm_next_se; + u8 arm_next; + u8 arm_seq_num; + + get_64bit_val(cq->shadow_area, 32, &temp_val); + + sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); + sw_cq_sel += cq_cnt; + + arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); + arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); + arm_next = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT, temp_val); + + temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | + FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | + FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | + FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, arm_next); + + set_64bit_val(cq->shadow_area, 32, temp_val); +} + +/** + * irdma_uk_cq_request_notification - cq notification request (door bell) + * @cq: hw cq + * @cq_notify: notification type + */ +void irdma_uk_cq_request_notification(struct irdma_cq_uk *cq, + enum irdma_cmpl_notify cq_notify) +{ + u64 temp_val; + u16 sw_cq_sel; + u8 arm_next_se = 0; + u8 arm_next = 0; + u8 arm_seq_num; + + get_64bit_val(cq->shadow_area, 32, &temp_val); + arm_seq_num = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_SEQ_NUM, temp_val); + arm_seq_num++; + sw_cq_sel = (u16)FIELD_GET(IRDMA_CQ_DBSA_SW_CQ_SELECT, temp_val); + arm_next_se = (u8)FIELD_GET(IRDMA_CQ_DBSA_ARM_NEXT_SE, temp_val); + arm_next_se |= 1; + if (cq_notify == IRDMA_CQ_COMPL_EVENT) + arm_next = 1; + temp_val = FIELD_PREP(IRDMA_CQ_DBSA_ARM_SEQ_NUM, arm_seq_num) | + FIELD_PREP(IRDMA_CQ_DBSA_SW_CQ_SELECT, sw_cq_sel) | + FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT_SE, arm_next_se) | + FIELD_PREP(IRDMA_CQ_DBSA_ARM_NEXT, arm_next); + + set_64bit_val(cq->shadow_area, 32, temp_val); + + dma_wmb(); /* make sure WQE is populated before valid bit is set */ + + writel(cq->cq_id, cq->cqe_alloc_db); +} + +/** + * irdma_uk_cq_poll_cmpl - get cq completion info + * @cq: hw cq + * @info: cq poll information returned + */ +int irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq, + struct irdma_cq_poll_info *info) +{ + u64 comp_ctx, qword0, qword2, qword3; + __le64 *cqe; + struct irdma_qp_uk *qp; + struct irdma_srq_uk *srq; + struct qp_err_code qp_err; + u8 is_srq; + struct irdma_ring *pring = NULL; + u32 wqe_idx; + int ret_code; + bool move_cq_head = true; + u8 polarity; + bool ext_valid; + __le64 *ext_cqe; + + if (cq->avoid_mem_cflct) + cqe = IRDMA_GET_CURRENT_EXTENDED_CQ_ELEM(cq); + else + cqe = IRDMA_GET_CURRENT_CQ_ELEM(cq); + + get_64bit_val(cqe, 24, &qword3); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); + if (polarity != cq->polarity) + return -ENOENT; + + /* Ensure CQE contents are read after valid bit is checked */ + dma_rmb(); + + ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); + if (ext_valid) { + u64 qword6, qword7; + u32 peek_head; + + if (cq->avoid_mem_cflct) { + ext_cqe = (__le64 *)((u8 *)cqe + 32); + get_64bit_val(ext_cqe, 24, &qword7); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); + } else { + peek_head = (cq->cq_ring.head + 1) % cq->cq_ring.size; + ext_cqe = cq->cq_base[peek_head].buf; + get_64bit_val(ext_cqe, 24, &qword7); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); + if (!peek_head) + polarity ^= 1; + } + if (polarity != cq->polarity) + return -ENOENT; + + /* Ensure ext CQE contents are read after ext valid bit is checked */ + dma_rmb(); + + info->imm_valid = (bool)FIELD_GET(IRDMA_CQ_IMMVALID, qword7); + if (info->imm_valid) { + u64 qword4; + + get_64bit_val(ext_cqe, 0, &qword4); + info->imm_data = (u32)FIELD_GET(IRDMA_CQ_IMMDATALOW32, qword4); + } + info->ud_smac_valid = (bool)FIELD_GET(IRDMA_CQ_UDSMACVALID, qword7); + info->ud_vlan_valid = (bool)FIELD_GET(IRDMA_CQ_UDVLANVALID, qword7); + if (info->ud_smac_valid || info->ud_vlan_valid) { + get_64bit_val(ext_cqe, 16, &qword6); + if (info->ud_vlan_valid) + info->ud_vlan = (u16)FIELD_GET(IRDMA_CQ_UDVLAN, qword6); + if (info->ud_smac_valid) { + info->ud_smac[5] = qword6 & 0xFF; + info->ud_smac[4] = (qword6 >> 8) & 0xFF; + info->ud_smac[3] = (qword6 >> 16) & 0xFF; + info->ud_smac[2] = (qword6 >> 24) & 0xFF; + info->ud_smac[1] = (qword6 >> 32) & 0xFF; + info->ud_smac[0] = (qword6 >> 40) & 0xFF; + } + } + } else { + info->imm_valid = false; + info->ud_smac_valid = false; + info->ud_vlan_valid = false; + } + + info->q_type = (u8)FIELD_GET(IRDMA_CQ_SQ, qword3); + is_srq = (u8)FIELD_GET(IRDMA_CQ_SRQ, qword3); + info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); + info->push_dropped = (bool)FIELD_GET(IRDMACQ_PSHDROP, qword3); + info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); + get_64bit_val(cqe, 8, &comp_ctx); + if (is_srq) + get_64bit_val(cqe, 40, (u64 *)&qp); + else + qp = (struct irdma_qp_uk *)(unsigned long)comp_ctx; + if (!qp || qp->destroy_pending) { + ret_code = -EFAULT; + goto exit; + } + if (info->error) { + info->major_err = FIELD_GET(IRDMA_CQ_MAJERR, qword3); + info->minor_err = FIELD_GET(IRDMA_CQ_MINERR, qword3); + switch (info->major_err) { + case IRDMA_SRQFLUSH_RSVD_MAJOR_ERR: + qp_err = irdma_ae_to_qp_err_code(info->minor_err); + info->minor_err = qp_err.flush_code; + fallthrough; + case IRDMA_FLUSH_MAJOR_ERR: + /* Set the min error to standard flush error code for remaining cqes */ + if (info->minor_err != FLUSH_GENERAL_ERR) { + qword3 &= ~IRDMA_CQ_MINERR; + qword3 |= FIELD_PREP(IRDMA_CQ_MINERR, FLUSH_GENERAL_ERR); + set_64bit_val(cqe, 24, qword3); + } + info->comp_status = IRDMA_COMPL_STATUS_FLUSHED; + break; + default: + info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; + break; + } + } else { + info->comp_status = IRDMA_COMPL_STATUS_SUCCESS; + } + + get_64bit_val(cqe, 0, &qword0); + get_64bit_val(cqe, 16, &qword2); + + info->qp_id = (u32)FIELD_GET(IRDMACQ_QPID, qword2); + info->ud_src_qpn = (u32)FIELD_GET(IRDMACQ_UDSRCQPN, qword2); + + info->solicited_event = (bool)FIELD_GET(IRDMACQ_SOEVENT, qword3); + wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); + info->qp_handle = (irdma_qp_handle)(unsigned long)qp; + info->op_type = (u8)FIELD_GET(IRDMACQ_OP, qword3); + + if (info->q_type == IRDMA_CQE_QTYPE_RQ && is_srq) { + srq = qp->srq_uk; + + get_64bit_val(cqe, 8, &info->wr_id); + info->bytes_xfered = (u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); + + if (qword3 & IRDMACQ_STAG) { + info->stag_invalid_set = true; + info->inv_stag = (u32)FIELD_GET(IRDMACQ_INVSTAG, qword2); + } else { + info->stag_invalid_set = false; + } + IRDMA_RING_MOVE_TAIL(srq->srq_ring); + pring = &srq->srq_ring; + } else if (info->q_type == IRDMA_CQE_QTYPE_RQ && !is_srq) { + u32 array_idx; + + array_idx = wqe_idx / qp->rq_wqe_size_multiplier; + + if (info->comp_status == IRDMA_COMPL_STATUS_FLUSHED || + info->comp_status == IRDMA_COMPL_STATUS_UNKNOWN) { + if (!IRDMA_RING_MORE_WORK(qp->rq_ring)) { + ret_code = -ENOENT; + goto exit; + } + + info->wr_id = qp->rq_wrid_array[qp->rq_ring.tail]; + array_idx = qp->rq_ring.tail; + } else { + info->wr_id = qp->rq_wrid_array[array_idx]; + } + + info->bytes_xfered = (u32)FIELD_GET(IRDMACQ_PAYLDLEN, qword0); + + if (qword3 & IRDMACQ_STAG) { + info->stag_invalid_set = true; + info->inv_stag = (u32)FIELD_GET(IRDMACQ_INVSTAG, qword2); + } else { + info->stag_invalid_set = false; + } + IRDMA_RING_SET_TAIL(qp->rq_ring, array_idx + 1); + if (info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) { + qp->rq_flush_seen = true; + if (!IRDMA_RING_MORE_WORK(qp->rq_ring)) + qp->rq_flush_complete = true; + else + move_cq_head = false; + } + pring = &qp->rq_ring; + } else { /* q_type is IRDMA_CQE_QTYPE_SQ */ + if (qp->first_sq_wq) { + if (wqe_idx + 1 >= qp->conn_wqes) + qp->first_sq_wq = false; + + if (wqe_idx < qp->conn_wqes && qp->sq_ring.head == qp->sq_ring.tail) { + IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); + IRDMA_RING_MOVE_TAIL(cq->cq_ring); + set_64bit_val(cq->shadow_area, 0, + IRDMA_RING_CURRENT_HEAD(cq->cq_ring)); + memset(info, 0, sizeof(*info)); + return irdma_uk_cq_poll_cmpl(cq, info); + } + } + /*cease posting push mode on push drop*/ + if (info->push_dropped) { + qp->push_mode = false; + qp->push_dropped = true; + } + if (info->comp_status != IRDMA_COMPL_STATUS_FLUSHED) { + info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid; + if (!info->comp_status) + info->bytes_xfered = qp->sq_wrtrk_array[wqe_idx].wr_len; + info->op_type = (u8)FIELD_GET(IRDMACQ_OP, qword3); + IRDMA_RING_SET_TAIL(qp->sq_ring, + wqe_idx + qp->sq_wrtrk_array[wqe_idx].quanta); + } else { + unsigned long flags; + + spin_lock_irqsave(qp->lock, flags); + if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) { + spin_unlock_irqrestore(qp->lock, flags); + ret_code = -ENOENT; + goto exit; + } + + do { + __le64 *sw_wqe; + u64 wqe_qword; + u32 tail; + + tail = qp->sq_ring.tail; + sw_wqe = qp->sq_base[tail].elem; + get_64bit_val(sw_wqe, 24, + &wqe_qword); + info->op_type = (u8)FIELD_GET(IRDMAQPSQ_OPCODE, + wqe_qword); + IRDMA_RING_SET_TAIL(qp->sq_ring, + tail + qp->sq_wrtrk_array[tail].quanta); + if (info->op_type != IRDMAQP_OP_NOP) { + info->wr_id = qp->sq_wrtrk_array[tail].wrid; + info->bytes_xfered = qp->sq_wrtrk_array[tail].wr_len; + break; + } + } while (1); + + if (info->op_type == IRDMA_OP_TYPE_BIND_MW && + info->minor_err == FLUSH_PROT_ERR) + info->minor_err = FLUSH_MW_BIND_ERR; + qp->sq_flush_seen = true; + if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) + qp->sq_flush_complete = true; + spin_unlock_irqrestore(qp->lock, flags); + } + pring = &qp->sq_ring; + } + + ret_code = 0; + +exit: + if (!ret_code && info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) { + if (pring && IRDMA_RING_MORE_WORK(*pring)) + move_cq_head = false; + } + /* Park CQ head during a flush to generate additional CQEs from SW + * for all unprocessed WQEs. + * For GEN3 and beyond FW will generate/flush these CQEs so move + * to the next CQE. + */ + if (move_cq_head || qp->uk_attrs->hw_rev >= IRDMA_GEN_3) { + IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); + if (!IRDMA_RING_CURRENT_HEAD(cq->cq_ring)) + cq->polarity ^= 1; + + if (ext_valid && !cq->avoid_mem_cflct) { + IRDMA_RING_MOVE_HEAD_NOCHECK(cq->cq_ring); + if (!IRDMA_RING_CURRENT_HEAD(cq->cq_ring)) + cq->polarity ^= 1; + } + + IRDMA_RING_MOVE_TAIL(cq->cq_ring); + if (!cq->avoid_mem_cflct && ext_valid) + IRDMA_RING_MOVE_TAIL(cq->cq_ring); + set_64bit_val(cq->shadow_area, 0, + IRDMA_RING_CURRENT_HEAD(cq->cq_ring)); + } else { + qword3 &= ~IRDMA_CQ_WQEIDX; + qword3 |= FIELD_PREP(IRDMA_CQ_WQEIDX, pring->tail); + set_64bit_val(cqe, 24, qword3); + } + + return ret_code; +} + +#ifdef PRINT_CQES +/** + * irdma_print_cqes - print cq completion info + * @cq: hw cq + */ +void irdma_print_cqes(struct irdma_cq_uk *cq) +{ + u8 cq_polarity = cq->polarity; + int i = 0; + + pr_info("%s[%d]: CQ (cq_id=%u, polarity=%d, head=%u, size=%u)\n", + __func__, __LINE__, cq->cq_id, cq_polarity, cq->cq_ring.head, + cq->cq_ring.size); + + while (true) { + u64 comp_ctx, qword0, qword2, qword3; + struct irdma_cq_poll_info cqe_info; + struct irdma_cq_poll_info *info = &cqe_info; + struct irdma_qp_uk *qp; + __le64 *ext_cqe = NULL; + bool ext_valid; + u8 polarity; + u32 wqe_idx; + __le64 *cqe; + + IRDMA_GET_CQ_ELEM_AT_OFFSET(cq, i, cqe); + get_64bit_val(cqe, 24, &qword3); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); + + if (polarity != cq_polarity) { + pr_info("%s[%d]: CQ (cq_id=%u) is empty\n", __func__, + __LINE__, cq->cq_id); + return; + } + + /* Ensure CQE contents are read after valid bit is checked */ + dma_rmb(); + + ext_valid = (bool)FIELD_GET(IRDMA_CQ_EXTCQE, qword3); + if (ext_valid) { + u64 qword7; + u32 peek_head; + + if (cq->avoid_mem_cflct) { + ext_cqe = (__le64 *)((u8 *)cqe + 32); + get_64bit_val(ext_cqe, 24, &qword7); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); + } else { + peek_head = IRDMA_GET_RING_OFFSET(cq->cq_ring, i + 1); + ext_cqe = cq->cq_base[peek_head].buf; + get_64bit_val(ext_cqe, 24, &qword7); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword7); + if (!peek_head) + polarity ^= 1; + } + if (polarity != cq_polarity) { + pr_info("%s[%d]: Extended CQ (cq_id=%u) is empty\n", + __func__, __LINE__, cq->cq_id); + return; + } + + /* Ensure ext CQE contents are read after ext valid bit is checked */ + dma_rmb(); + + memset(info, 0, sizeof(*info)); + info->imm_valid = (bool)FIELD_GET(IRDMA_CQ_IMMVALID, qword7); + if (info->imm_valid) { + u64 qword4; + + get_64bit_val(ext_cqe, 0, &qword4); + info->imm_data = (u32)FIELD_GET(IRDMA_CQ_IMMDATALOW32, qword4); + } + } else { + info->imm_valid = false; + } + + info->q_type = (u8)FIELD_GET(IRDMA_CQ_SQ, qword3); + info->error = (bool)FIELD_GET(IRDMA_CQ_ERROR, qword3); + info->push_dropped = (bool)FIELD_GET(IRDMACQ_PSHDROP, qword3); + info->ipv4 = (bool)FIELD_GET(IRDMACQ_IPV4, qword3); + if (info->error) { + info->major_err = FIELD_GET(IRDMA_CQ_MAJERR, qword3); + info->minor_err = FIELD_GET(IRDMA_CQ_MINERR, qword3); + if (info->major_err == IRDMA_FLUSH_MAJOR_ERR) + info->comp_status = IRDMA_COMPL_STATUS_FLUSHED; + else + info->comp_status = IRDMA_COMPL_STATUS_UNKNOWN; + } else { + info->comp_status = IRDMA_COMPL_STATUS_SUCCESS; + info->major_err = 0; + info->minor_err = 0; + } + + get_64bit_val(cqe, 0, &qword0); + get_64bit_val(cqe, 16, &qword2); + + info->qp_id = (u32)FIELD_GET(IRDMACQ_QPID, qword2); + get_64bit_val(cqe, 8, &comp_ctx); + info->solicited_event = (bool)FIELD_GET(IRDMACQ_SOEVENT, qword3); + + pr_info("%s[%d]: Found CQE (cq_id=%u major_err=%u minor_err=%u q_type=%u " + "push_dropped=%s ipv4=%s solicited_event=%s imm_data=%u qp_id=%u)\n", + __func__, __LINE__, cq->cq_id, info->major_err, + info->minor_err, info->q_type, + info->push_dropped ? "true" : "false", + info->ipv4 ? "true" : "false", + info->solicited_event ? "true" : "false", + info->imm_valid ? info->imm_data : 0, info->qp_id); + + qp = (struct irdma_qp_uk *)(uintptr_t)comp_ctx; + if (!qp || qp->destroy_pending) { + pr_info("%s[%d]: Found CQE for (cq_id=%u qp_id=%u): QP destroyed\n", + __func__, __LINE__, cq->cq_id, info->qp_id); + goto loop_end; + } + wqe_idx = (u32)FIELD_GET(IRDMA_CQ_WQEIDX, qword3); + info->qp_handle = (irdma_qp_handle)(uintptr_t)qp; + info->op_type = (u8)FIELD_GET(IRDMACQ_OP, qword3); + + if (info->q_type == IRDMA_CQE_QTYPE_RQ) { + u32 array_idx; + + array_idx = wqe_idx / qp->rq_wqe_size_multiplier; + info->wr_id = qp->rq_wrid_array[array_idx]; + + if (qword3 & IRDMACQ_STAG) { + info->stag_invalid_set = true; + info->inv_stag = (u32)FIELD_GET(IRDMACQ_INVSTAG, qword2); + } else { + info->stag_invalid_set = false; + } + + pr_info("%s[%d]: Found CQE for RQ qp_id=%u rq_ring (head=%u tail=%u size=%u) " + "wr_id=%llu wqe_idx=%u, stag_invalid_set=%s op_type=%u\n", + __func__, __LINE__, info->qp_id, + qp->rq_ring.head, qp->rq_ring.tail, + qp->rq_ring.size, info->wr_id, wqe_idx, + info->stag_invalid_set ? "true" : "false", + info->op_type); + + } else { /* q_type is IRDMA_CQE_QTYPE_SQ */ + + if (qp->first_sq_wq) { + pr_info("%s[%d]: Found CQE for SQ first_sq_wq (qp_id=%u, wqe_idx=%u, conn_wqes=%d)\n", + __func__, __LINE__, info->qp_id, + wqe_idx, qp->conn_wqes); + + if (wqe_idx < qp->conn_wqes && qp->sq_ring.head == qp->sq_ring.tail) + goto loop_end; + } + + info->wr_id = qp->sq_wrtrk_array[wqe_idx].wrid; + info->op_type = (u8)FIELD_GET(IRDMACQ_OP, qword3); + + pr_info("%s[%d]: Found CQE for SQ qp_id=%u, sq_ring (head=%u tail=%u size=%u) " + "wr_id=%llu wqe_idx=%u op_type=%u\n", + __func__, __LINE__, info->qp_id, + qp->sq_ring.head, qp->sq_ring.tail, + qp->sq_ring.size, info->wr_id, wqe_idx, + info->op_type); + } +loop_end: + i++; + if (!IRDMA_GET_RING_OFFSET(cq->cq_ring, i)) + cq_polarity ^= 1; + + if (ext_valid && !cq->avoid_mem_cflct) { + i++; + if (!IRDMA_GET_RING_OFFSET(cq->cq_ring, i)) + cq_polarity ^= 1; + } + } +} + +/** + * irdma_print_sq_wqes - print sqp wqes + * @qp: hw qp + */ +void irdma_print_sq_wqes(struct irdma_qp_uk *qp) +{ + u32 wqe_idx = IRDMA_RING_CURRENT_TAIL(qp->sq_ring); + u8 sq_polarity = qp->swqe_polarity; + + pr_info("%s[%d]: SQ (qp_id=%u sq_polarity=%d head=%u tail=%u size=%u)\n", + __func__, __LINE__, qp->qp_id, sq_polarity, qp->sq_ring.head, + qp->sq_ring.tail, qp->sq_ring.size); + + if (!IRDMA_RING_MORE_WORK(qp->sq_ring)) { + pr_info("%s[%d]: SQ is empty (qp_id=%u)\n", __func__, + __LINE__, qp->qp_id); + return; + } + + while (true) { + u8 wqe_polarity; + __le64 *wqe; + u64 val; + int i; + + wqe = qp->sq_base[wqe_idx].elem; + get_64bit_val(wqe, 24, &val); + wqe_polarity = FIELD_GET(IRDMAQPSQ_VALID, val); + + if (wqe_polarity != sq_polarity) + break; + + pr_info("%s[%d]: Found WQE in SQ qp_id=%u wr_id=%llu wqe_idx=%u " + "wr_len=%u quanta=%u hdr=0x%0llX\n", __func__, + __LINE__, qp->qp_id, qp->sq_wrtrk_array[wqe_idx].wrid, + wqe_idx, qp->sq_wrtrk_array[wqe_idx].wr_len, + qp->sq_wrtrk_array[wqe_idx].quanta, val); + + for (i = 0; i < (qp->sq_wrtrk_array[wqe_idx].quanta * IRDMA_QP_WQE_MIN_SIZE / 8); i++) + pr_debug("index %03d val: %016llx\n", i, *(wqe + i)); + wqe_idx += qp->sq_wrtrk_array[wqe_idx].quanta; + + if (!wqe_idx) + sq_polarity = !qp->swqe_polarity; + } +} +#endif /* defined(CONFIG_DEBUG_FS) || (!defined(__KERNEL__) && !defined(UPSTREAM_RELEASE)) */ + +/** + * irdma_round_up_wq - return round up qp wq depth + * @wqdepth: wq depth in quanta to round up + */ +static int irdma_round_up_wq(u32 wqdepth) +{ + int scount = 1; + + for (wqdepth--; scount <= 16; scount *= 2) + wqdepth |= wqdepth >> scount; + + return ++wqdepth; +} + +/** + * irdma_get_wqe_shift - get shift count for maximum wqe size + * @uk_attrs: qp HW attributes + * @sge: Maximum Scatter Gather Elements wqe + * @inline_data: Maximum inline data size + * @shift: Returns the shift needed based on sge + * + * Shift can be used to left shift the wqe size based on number of SGEs and inlind data size. + * For 1 SGE or inline data <= 8, shift = 0 (wqe size of 32 + * bytes). For 2 or 3 SGEs or inline data <= 39, shift = 1 (wqe + * size of 64 bytes). + * For 4-7 SGE's and inline <= 101 Shift of 2 otherwise (wqe + * size of 256 bytes). + */ +void irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge, + u32 inline_data, u8 *shift) +{ + *shift = 0; + if (uk_attrs->hw_rev >= IRDMA_GEN_2) { + if (sge > 1 || inline_data > 8) { + if (sge < 4 && inline_data <= 39) + *shift = 1; + else if (sge < 8 && inline_data <= 101) + *shift = 2; + else + *shift = 3; + } + } else if (sge > 1 || inline_data > 16) { + *shift = (sge < 4 && inline_data <= 48) ? 1 : 2; + } +} + +/* + * irdma_get_sqdepth - get SQ depth (quanta) + * @uk_attrs: qp HW attributes + * @sq_size: SQ size + * @shift: shift which determines size of WQE + * @sqdepth: depth of SQ + */ +int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, u32 sq_size, u8 shift, u32 *sqdepth) +{ + u32 min_size = (u32)uk_attrs->min_hw_wq_size << shift; + + *sqdepth = irdma_round_up_wq((sq_size << shift) + IRDMA_SQ_RSVD); + + if (*sqdepth < min_size) + *sqdepth = min_size; + else if (*sqdepth > uk_attrs->max_hw_wq_quanta) + return -EINVAL; + + return 0; +} + +/* + * irdma_get_rqdepth - get RQ depth (quanta) + * @uk_attrs: qp HW attributes + * @rq_size: SRQ size + * @shift: shift which determines size of WQE + * @rqdepth: depth of RQ/SRQ + */ +int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, u32 rq_size, u8 shift, u32 *rqdepth) +{ + u32 min_size = (u32)uk_attrs->min_hw_wq_size << shift; + + *rqdepth = irdma_round_up_wq((rq_size << shift) + IRDMA_RQ_RSVD); + + if (*rqdepth < min_size) + *rqdepth = min_size; + else if (*rqdepth > uk_attrs->max_hw_rq_quanta) + return -EINVAL; + + return 0; +} + +/* + * irdma_get_srqdepth - get SRQ depth (quanta) + * @uk_attrs: qp HW attributes + * @srq_size: SRQ size + * @shift: shift which determines size of WQE + * @srqdepth: depth of SRQ + */ +int irdma_get_srqdepth(struct irdma_uk_attrs *uk_attrs, u32 srq_size, u8 shift, u32 *srqdepth) +{ + *srqdepth = irdma_round_up_wq((srq_size << shift) + IRDMA_RQ_RSVD); + + if (*srqdepth < ((u32)uk_attrs->min_hw_wq_size << shift)) + *srqdepth = uk_attrs->min_hw_wq_size << shift; + else if (*srqdepth > uk_attrs->max_hw_srq_quanta) + return -EINVAL; + + return 0; +} + +static const struct irdma_wqe_uk_ops iw_wqe_uk_ops = { + .iw_copy_inline_data = irdma_copy_inline_data, + .iw_inline_data_size_to_quanta = irdma_inline_data_size_to_quanta, + .iw_set_fragment = irdma_set_fragment, +}; + +static const struct irdma_wqe_uk_ops iw_wqe_uk_ops_gen_1 = { + .iw_copy_inline_data = irdma_copy_inline_data_gen_1, + .iw_inline_data_size_to_quanta = irdma_inline_data_size_to_quanta_gen_1, + .iw_set_fragment = irdma_set_fragment_gen_1, +}; + +/** + * irdma_setup_connection_wqes - setup WQEs necessary to complete + * connection. + * @qp: hw qp (user and kernel) + * @info: qp initialization info + */ +static void irdma_setup_connection_wqes(struct irdma_qp_uk *qp, + struct irdma_qp_uk_init_info *info) +{ + u16 move_cnt = 1; + + if (info->start_wqe_idx) + move_cnt = info->start_wqe_idx; + else if (!info->legacy_mode && + (qp->uk_attrs->feature_flags & IRDMA_FEATURE_RTS_AE)) + move_cnt = 3; + qp->conn_wqes = move_cnt; + IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->sq_ring, move_cnt); + IRDMA_RING_MOVE_TAIL_BY_COUNT(qp->sq_ring, move_cnt); + IRDMA_RING_MOVE_HEAD_BY_COUNT_NOCHECK(qp->initial_ring, move_cnt); +} + +/** + * irdma_uk_srq_init - initialize shared qp + * @srq: hw srq (user and kernel) + * @info: srq initialization info + * + * initializes the vars used in both user and kernel mode. + * size of the wqe depends on numbers of max. fragements + * allowed. Then size of wqe * the number of wqes should be the + * amount of memory allocated for srq. + */ +int irdma_uk_srq_init(struct irdma_srq_uk *srq, + struct irdma_srq_uk_init_info *info) +{ + u8 rqshift; + + srq->uk_attrs = info->uk_attrs; + if (info->max_srq_frag_cnt > srq->uk_attrs->max_hw_wq_frags) + return -EINVAL; + + irdma_get_wqe_shift(srq->uk_attrs, info->max_srq_frag_cnt, 0, &rqshift); + srq->srq_caps = info->srq_caps; + srq->srq_base = info->srq; + srq->shadow_area = info->shadow_area; + srq->srq_id = info->srq_id; + srq->srwqe_polarity = 0; + srq->srq_size = info->srq_size; + srq->wqe_size = rqshift; + srq->max_srq_frag_cnt = min(srq->uk_attrs->max_hw_wq_frags, + ((u32)2 << rqshift) - 1); + IRDMA_RING_INIT(srq->srq_ring, srq->srq_size); + srq->wqe_size_multiplier = 1 << rqshift; + srq->wqe_ops = iw_wqe_uk_ops; + + return 0; +} + +/** + * irdma_uk_calc_shift_wq - calculate WQE shift for both SQ and RQ + * @ukinfo: qp initialization info + * @sq_shift: Returns shift of SQ + * @rq_shift: Returns shift of RQ + */ +void irdma_uk_calc_shift_wq(struct irdma_qp_uk_init_info *ukinfo, u8 *sq_shift, + u8 *rq_shift) +{ + bool imm_support = ukinfo->uk_attrs->hw_rev >= IRDMA_GEN_2 ? true : false; + + irdma_get_wqe_shift(ukinfo->uk_attrs, + imm_support ? ukinfo->max_sq_frag_cnt + 1 : + ukinfo->max_sq_frag_cnt, + ukinfo->max_inline_data, sq_shift); + + irdma_get_wqe_shift(ukinfo->uk_attrs, ukinfo->max_rq_frag_cnt, 0, + rq_shift); + + if (ukinfo->uk_attrs->hw_rev == IRDMA_GEN_1) { + if (ukinfo->abi_ver > 4) + *rq_shift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1; + } +} + +/** + * irdma_uk_calc_depth_shift_sq - calculate depth and shift for SQ size. + * @ukinfo: qp initialization info + * @sq_depth: Returns depth of SQ + * @sq_shift: Returns shift of SQ + */ +int irdma_uk_calc_depth_shift_sq(struct irdma_qp_uk_init_info *ukinfo, + u32 *sq_depth, u8 *sq_shift) +{ + bool imm_support = ukinfo->uk_attrs->hw_rev >= IRDMA_GEN_2 ? true : false; + int status; + irdma_get_wqe_shift(ukinfo->uk_attrs, + imm_support ? ukinfo->max_sq_frag_cnt + 1 : + ukinfo->max_sq_frag_cnt, + ukinfo->max_inline_data, sq_shift); + status = irdma_get_sqdepth(ukinfo->uk_attrs, ukinfo->sq_size, + *sq_shift, sq_depth); + + return status; +} + +/** + * irdma_uk_calc_depth_shift_rq - calculate depth and shift for RQ size. + * @ukinfo: qp initialization info + * @rq_depth: Returns depth of RQ + * @rq_shift: Returns shift of RQ + */ +int irdma_uk_calc_depth_shift_rq(struct irdma_qp_uk_init_info *ukinfo, + u32 *rq_depth, u8 *rq_shift) +{ + int status; + + irdma_get_wqe_shift(ukinfo->uk_attrs, ukinfo->max_rq_frag_cnt, 0, + rq_shift); + + if (ukinfo->uk_attrs->hw_rev == IRDMA_GEN_1) { + if (ukinfo->abi_ver > 4) + *rq_shift = IRDMA_MAX_RQ_WQE_SHIFT_GEN1; + } + + status = irdma_get_rqdepth(ukinfo->uk_attrs, ukinfo->rq_size, + *rq_shift, rq_depth); + + return status; +} + +/** + * irdma_uk_qp_init - initialize shared qp + * @qp: hw qp (user and kernel) + * @info: qp initialization info + * + * initializes the vars used in both user and kernel mode. + * size of the wqe depends on numbers of max. fragements + * allowed. Then size of wqe * the number of wqes should be the + * amount of memory allocated for sq and rq. + */ +int irdma_uk_qp_init(struct irdma_qp_uk *qp, struct irdma_qp_uk_init_info *info) +{ + int ret_code = 0; + u32 sq_ring_size; + + qp->uk_attrs = info->uk_attrs; + if (info->max_sq_frag_cnt > qp->uk_attrs->max_hw_wq_frags || + info->max_rq_frag_cnt > qp->uk_attrs->max_hw_wq_frags) + return -EINVAL; + + qp->qp_caps = info->qp_caps; + qp->sq_base = info->sq; + qp->rq_base = info->rq; + qp->qp_type = info->type ? info->type : IRDMA_QP_TYPE_IWARP; + qp->shadow_area = info->shadow_area; + qp->sq_wrtrk_array = info->sq_wrtrk_array; + + qp->rq_wrid_array = info->rq_wrid_array; + qp->wqe_alloc_db = info->wqe_alloc_db; + qp->rd_fence_rate = info->rd_fence_rate; + qp->qp_id = info->qp_id; + qp->sq_size = info->sq_size; + qp->push_mode = false; + qp->max_sq_frag_cnt = info->max_sq_frag_cnt; + sq_ring_size = qp->sq_size << info->sq_shift; + IRDMA_RING_INIT(qp->sq_ring, sq_ring_size); + IRDMA_RING_INIT(qp->initial_ring, sq_ring_size); + if (info->first_sq_wq) { + irdma_setup_connection_wqes(qp, info); + qp->swqe_polarity = 1; + qp->first_sq_wq = true; + } else { + qp->swqe_polarity = 0; + } + qp->swqe_polarity_deferred = 1; + qp->rwqe_polarity = 0; + qp->rq_size = info->rq_size; + qp->max_rq_frag_cnt = info->max_rq_frag_cnt; + qp->max_inline_data = info->max_inline_data; + qp->rq_wqe_size = info->rq_shift; + IRDMA_RING_INIT(qp->rq_ring, qp->rq_size); + qp->rq_wqe_size_multiplier = 1 << info->rq_shift; + if (qp->uk_attrs->hw_rev == IRDMA_GEN_1) + qp->wqe_ops = iw_wqe_uk_ops_gen_1; + else + qp->wqe_ops = iw_wqe_uk_ops; + qp->srq_uk = info->srq_uk; + qp->start_wqe_idx = info->start_wqe_idx; + + return ret_code; +} + +/** + * irdma_uk_cq_init - initialize shared cq (user and kernel) + * @cq: hw cq + * @info: hw cq initialization info + */ +int irdma_uk_cq_init(struct irdma_cq_uk *cq, struct irdma_cq_uk_init_info *info) +{ + cq->cq_base = info->cq_base; + cq->cq_id = info->cq_id; + cq->cq_size = info->cq_size; + cq->cqe_alloc_db = info->cqe_alloc_db; + cq->cq_ack_db = info->cq_ack_db; + cq->shadow_area = info->shadow_area; + cq->avoid_mem_cflct = info->avoid_mem_cflct; + IRDMA_RING_INIT(cq->cq_ring, cq->cq_size); + cq->polarity = 1; + + return 0; +} + +/** + * irdma_uk_clean_cq - clean cq entries + * @q: completion context + * @cq: cq to clean + */ +void irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq) +{ + __le64 *cqe; + u64 qword3, comp_ctx; + u32 cq_head; + u8 polarity, temp; + + cq_head = cq->cq_ring.head; + temp = cq->polarity; + do { + if (cq->avoid_mem_cflct) + cqe = ((struct irdma_extended_cqe *)(cq->cq_base))[cq_head].buf; + else + cqe = cq->cq_base[cq_head].buf; + get_64bit_val(cqe, 24, &qword3); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); + + if (polarity != temp) + break; + + /* Ensure CQE contents are read after valid bit is checked */ + dma_rmb(); + + get_64bit_val(cqe, 8, &comp_ctx); + if ((void *)(unsigned long)comp_ctx == q) + set_64bit_val(cqe, 8, 0); + + cq_head = (cq_head + 1) % cq->cq_ring.size; + if (!cq_head) + temp ^= 1; + } while (true); +} + +/** + * irdma_fragcnt_to_quanta_sq - calculate quanta based on fragment count for SQ + * @frag_cnt: number of fragments + * @quanta: quanta for frag_cnt + */ +int irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta) +{ + switch (frag_cnt) { + case 0: + case 1: + *quanta = IRDMA_QP_WQE_MIN_QUANTA; + break; + case 2: + case 3: + *quanta = 2; + break; + case 4: + case 5: + *quanta = 3; + break; + case 6: + case 7: + *quanta = 4; + break; + case 8: + case 9: + *quanta = 5; + break; + case 10: + case 11: + *quanta = 6; + break; + case 12: + case 13: + *quanta = 7; + break; + case 14: + case 15: /* when immediate data is present */ + *quanta = 8; + break; + default: + return -EINVAL; + } + + return 0; +} + +/** + * irdma_fragcnt_to_wqesize_rq - calculate wqe size based on fragment count for RQ + * @frag_cnt: number of fragments + * @wqe_size: size in bytes given frag_cnt + */ +int irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size) +{ + switch (frag_cnt) { + case 0: + case 1: + *wqe_size = 32; + break; + case 2: + case 3: + *wqe_size = 64; + break; + case 4: + case 5: + case 6: + case 7: + *wqe_size = 128; + break; + case 8: + case 9: + case 10: + case 11: + case 12: + case 13: + case 14: + *wqe_size = 256; + break; + default: + return -EINVAL; + } + + return 0; +} + diff --git a/drivers/intel/irdma-1.14.33/src/irdma/user.h b/drivers/intel/irdma-1.14.33/src/irdma/user.h new file mode 100644 index 000000000..9a0b4340e --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/user.h @@ -0,0 +1,743 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef IRDMA_USER_H +#define IRDMA_USER_H + +#ifdef CONFIG_DEBUG_FS +#define PRINT_CQES +#endif + +#define irdma_handle void * +#define irdma_adapter_handle irdma_handle +#define irdma_qp_handle irdma_handle +#define irdma_cq_handle irdma_handle +#define irdma_pd_id irdma_handle +#define irdma_stag_handle irdma_handle +#define irdma_stag_index u32 +#define irdma_stag u32 +#define irdma_stag_key u8 +#define irdma_tagged_offset u64 +#define irdma_access_privileges u32 +#define irdma_physical_fragment u64 +#define irdma_address_list u64 * + +#define IRDMA_MAX_MR_SIZE 0x200000000000ULL + +#define IRDMA_ACCESS_FLAGS_LOCALREAD 0x01 +#define IRDMA_ACCESS_FLAGS_LOCALWRITE 0x02 +#define IRDMA_ACCESS_FLAGS_REMOTEREAD_ONLY 0x04 +#define IRDMA_ACCESS_FLAGS_REMOTEREAD 0x05 +#define IRDMA_ACCESS_FLAGS_REMOTEWRITE_ONLY 0x08 +#define IRDMA_ACCESS_FLAGS_REMOTEWRITE 0x0a +#define IRDMA_ACCESS_FLAGS_BIND_WINDOW 0x10 +#define IRDMA_ACCESS_FLAGS_ZERO_BASED 0x20 +#define IRDMA_ACCESS_FLAGS_ALL 0x3f + +#define IRDMA_FLUSH_MEM_REGION_PLACE_TYPE_GLOBAL_VIS BIT(0) +#define IRDMA_FLUSH_MEM_REGION_PLACE_TYPE_PERSISTENCE BIT(1) +#define IRDMA_FLUSH_MEM_REGION_SELECTIVITY_TYPE_WRITES_IN_RANGE 0x0 +#define IRDMA_FLUSH_MEM_REGION_SELECTIVITY_TYPE_ALL_WRITES 0x1 + +#define IRDMA_OP_TYPE_RDMA_WRITE 0x00 +#define IRDMA_OP_TYPE_RDMA_READ 0x01 +#define IRDMA_OP_TYPE_SEND 0x03 +#define IRDMA_OP_TYPE_SEND_INV 0x04 +#define IRDMA_OP_TYPE_SEND_SOL 0x05 +#define IRDMA_OP_TYPE_SEND_SOL_INV 0x06 +#define IRDMA_OP_TYPE_RDMA_WRITE_SOL 0x0d +#define IRDMA_OP_TYPE_BIND_MW 0x08 +#define IRDMA_OP_TYPE_FAST_REG_NSMR 0x09 +#define IRDMA_OP_TYPE_INV_STAG 0x0a +#define IRDMA_OP_TYPE_RDMA_READ_INV_STAG 0x0b +#define IRDMA_OP_TYPE_NOP 0x0c +#define IRDMA_OP_TYPE_ATOMIC_FETCH_AND_ADD 0x0f +#define IRDMA_OP_TYPE_ATOMIC_COMPARE_AND_SWAP 0x11 +#define IRDMA_OP_TYPE_ATOMIC_WRITE 0x12 +#define IRDMA_OP_TYPE_FLUSH_MEMORY_REGION 0x13 +#define IRDMA_OP_TYPE_REC 0x3e +#define IRDMA_OP_TYPE_REC_IMM 0x3f + +#define IRDMA_FLUSH_MAJOR_ERR 1 +#define IRDMA_SRQFLUSH_RSVD_MAJOR_ERR 0xfffe +/* Async Events codes */ +#define IRDMA_AE_AMP_UNALLOCATED_STAG 0x0102 +#define IRDMA_AE_AMP_INVALID_STAG 0x0103 +#define IRDMA_AE_AMP_BAD_QP 0x0104 +#define IRDMA_AE_AMP_BAD_PD 0x0105 +#define IRDMA_AE_AMP_BAD_STAG_KEY 0x0106 +#define IRDMA_AE_AMP_BAD_STAG_INDEX 0x0107 +#define IRDMA_AE_AMP_BOUNDS_VIOLATION 0x0108 +#define IRDMA_AE_AMP_RIGHTS_VIOLATION 0x0109 +#define IRDMA_AE_AMP_TO_WRAP 0x010a +#define IRDMA_AE_AMP_FASTREG_VALID_STAG 0x010c +#define IRDMA_AE_AMP_FASTREG_MW_STAG 0x010d +#define IRDMA_AE_AMP_FASTREG_INVALID_RIGHTS 0x010e +#define IRDMA_AE_AMP_FASTREG_INVALID_LENGTH 0x0110 +#define IRDMA_AE_AMP_INVALIDATE_SHARED 0x0111 +#define IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS 0x0112 +#define IRDMA_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS 0x0113 +#define IRDMA_AE_AMP_MWBIND_VALID_STAG 0x0114 +#define IRDMA_AE_AMP_MWBIND_OF_MR_STAG 0x0115 +#define IRDMA_AE_AMP_MWBIND_TO_ZERO_BASED_STAG 0x0116 +#define IRDMA_AE_AMP_MWBIND_TO_MW_STAG 0x0117 +#define IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS 0x0118 +#define IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS 0x0119 +#define IRDMA_AE_AMP_MWBIND_TO_INVALID_PARENT 0x011a +#define IRDMA_AE_AMP_MWBIND_BIND_DISABLED 0x011b +#define IRDMA_AE_PRIV_OPERATION_DENIED 0x011c +#define IRDMA_AE_AMP_INVALIDATE_TYPE1_MW 0x011d +#define IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW 0x011e +#define IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG 0x011f +#define IRDMA_AE_AMP_MWBIND_WRONG_TYPE 0x0120 +#define IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH 0x0121 +#define IRDMA_AE_AMP_MEM_FLUSH_OVER_REACH 0x0125 +#define IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG 0x0132 +#define IRDMA_AE_UDA_XMIT_BAD_PD 0x0133 +#define IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT 0x0134 +#define IRDMA_AE_UDA_L4LEN_INVALID 0x0135 +#define IRDMA_AE_BAD_CLOSE 0x0201 +#define IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE 0x0202 +#define IRDMA_AE_CQ_OPERATION_ERROR 0x0203 +#define IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO 0x0205 +#define IRDMA_AE_STAG_ZERO_INVALID 0x0206 +#define IRDMA_AE_IB_RREQ_AND_Q1_FULL 0x0207 +#define IRDMA_AE_IB_INVALID_REQUEST 0x0208 +#define IRDMA_AE_SRQ_LIMIT 0x0209 +#define IRDMA_AE_WQE_UNEXPECTED_OPCODE 0x020a +#define IRDMA_AE_WQE_INVALID_PARAMETER 0x020b +#define IRDMA_AE_WQE_INVALID_FRAG_DATA 0x020c +#define IRDMA_AE_IB_REMOTE_ACCESS_ERROR 0x020d +#define IRDMA_AE_IB_REMOTE_OP_ERROR 0x020e +#define IRDMA_AE_SRQ_CATASTROPHIC_ERROR 0x020f +#define IRDMA_AE_WQE_LSMM_TOO_LONG 0x0220 +#define IRDMA_AE_ATOMIC_ALIGNMENT 0x0221 +#define IRDMA_AE_ATOMIC_MASK 0x0222 +#define IRDMA_AE_INVALID_REQUEST 0x0223 +#define IRDMA_AE_PCIE_ATOMIC_DISABLE 0x0224 +#define IRDMA_AE_MEM_FLUSH_DISABLE 0x0230 +#define IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN 0x0301 +#define IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER 0x0303 +#define IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION 0x0304 +#define IRDMA_AE_DDP_UBE_INVALID_MO 0x0305 +#define IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE 0x0306 +#define IRDMA_AE_DDP_UBE_INVALID_QN 0x0307 +#define IRDMA_AE_DDP_NO_L_BIT 0x0308 +#define IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION 0x0311 +#define IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE 0x0312 +#define IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST 0x0313 +#define IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP 0x0314 +#define IRDMA_AE_ROCE_RSP_LENGTH_ERROR 0x0316 +#define IRDMA_AE_ROCE_REQ_LENGTH_ERROR 0x0318 +#define IRDMA_AE_ROCE_EMPTY_MCG 0x0380 +#define IRDMA_AE_ROCE_BAD_MC_IP_ADDR 0x0381 +#define IRDMA_AE_ROCE_BAD_MC_QPID 0x0382 +#define IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH 0x0383 +#define IRDMA_AE_INVALID_ARP_ENTRY 0x0401 +#define IRDMA_AE_INVALID_TCP_OPTION_RCVD 0x0402 +#define IRDMA_AE_STALE_ARP_ENTRY 0x0403 +#define IRDMA_AE_INVALID_AH_ENTRY 0x0406 +#define IRDMA_AE_LLP_CLOSE_COMPLETE 0x0501 +#define IRDMA_AE_LLP_CONNECTION_RESET 0x0502 +#define IRDMA_AE_LLP_FIN_RECEIVED 0x0503 +#define IRDMA_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH 0x0504 +#define IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR 0x0505 +#define IRDMA_AE_LLP_SEGMENT_TOO_SMALL 0x0507 +#define IRDMA_AE_LLP_SYN_RECEIVED 0x0508 +#define IRDMA_AE_LLP_TERMINATE_RECEIVED 0x0509 +#define IRDMA_AE_LLP_TOO_MANY_RETRIES 0x050a +#define IRDMA_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES 0x050b +#define IRDMA_AE_LLP_DOUBT_REACHABILITY 0x050c +#define IRDMA_AE_LLP_CONNECTION_ESTABLISHED 0x050e +#define IRDMA_AE_LLP_TOO_MANY_RNRS 0x050f +#define IRDMA_AE_RESOURCE_EXHAUSTION 0x0520 +#define IRDMA_AE_RESET_SENT 0x0601 +#define IRDMA_AE_TERMINATE_SENT 0x0602 +#define IRDMA_AE_RESET_NOT_SENT 0x0603 +#define IRDMA_AE_LCE_QP_CATASTROPHIC 0x0700 +#define IRDMA_AE_LCE_FUNCTION_CATASTROPHIC 0x0701 +#define IRDMA_AE_LCE_CQ_CATASTROPHIC 0x0702 +#define IRDMA_AE_REMOTE_QP_CATASTROPHIC 0x0703 +#define IRDMA_AE_LOCAL_QP_CATASTROPHIC 0x0704 +#define IRDMA_AE_RCE_QP_CATASTROPHIC 0x0705 +#define IRDMA_AE_QP_SUSPEND_COMPLETE 0x0900 +#define IRDMA_AE_CQP_DEFERRED_COMPLETE 0x0901 +#define IRDMA_AE_ADAPTER_CATASTROPHIC 0x0B0B + +enum irdma_device_caps_const { + IRDMA_WQE_SIZE = 4, + IRDMA_CQP_WQE_SIZE = 8, + IRDMA_CQE_SIZE = 4, + IRDMA_EXTENDED_CQE_SIZE = 8, + IRDMA_AEQE_SIZE = 2, + IRDMA_CEQE_SIZE = 1, + IRDMA_CQP_CTX_SIZE = 8, + IRDMA_SHADOW_AREA_SIZE = 8, + IRDMA_GATHER_STATS_BUF_SIZE = 1024, + IRDMA_MIN_IW_QP_ID = 0, + IRDMA_MIN_IW_SRQ_ID = 0, + IRDMA_QUERY_FPM_BUF_SIZE = 184, + IRDMA_COMMIT_FPM_BUF_SIZE = 192, + IRDMA_MIN_CEQID = 0, + IRDMA_MAX_CEQID = 1023, + IRDMA_CEQ_MAX_COUNT = IRDMA_MAX_CEQID + 1, + IRDMA_MIN_CQID = 0, + IRDMA_MIN_AEQ_ENTRIES = 1, + IRDMA_MAX_AEQ_ENTRIES = 524287, + IRDMA_MAX_AEQ_ENTRIES_GEN_3 = 262144, + IRDMA_MIN_CEQ_ENTRIES = 1, + IRDMA_MAX_CEQ_ENTRIES = 262143, + IRDMA_MIN_CQ_SIZE = 1, + IRDMA_MAX_CQ_SIZE = 1048575, + IRDMA_DB_ID_ZERO = 0, + IRDMA_MAX_OUTBOUND_MSG_SIZE = 2147483647, + IRDMA_MAX_INBOUND_MSG_SIZE = 2147483647, + IRDMA_MAX_PE_ENA_VF_COUNT = 32, + IRDMA_MAX_VF_FPM_ID = 47, + IRDMA_MAX_SQ_PAYLOAD_SIZE = 2145386496, + IRDMA_MAX_INLINE_DATA_SIZE = 101, + IRDMA_MAX_WQ_ENTRIES = 32768, + IRDMA_Q2_BUF_SIZE = 256, + IRDMA_QP_CTX_SIZE = 256, + IRDMA_MAX_PDS = 262144, +}; + +enum irdma_addressing_type { + IRDMA_ADDR_TYPE_ZERO_BASED = 0, + IRDMA_ADDR_TYPE_VA_BASED = 1, +}; + +enum irdma_flush_opcode { + FLUSH_INVALID = 0, + FLUSH_GENERAL_ERR, + FLUSH_PROT_ERR, + FLUSH_REM_ACCESS_ERR, + FLUSH_LOC_QP_OP_ERR, + FLUSH_REM_OP_ERR, + FLUSH_LOC_LEN_ERR, + FLUSH_FATAL_ERR, + FLUSH_RETRY_EXC_ERR, + FLUSH_MW_BIND_ERR, + FLUSH_REM_INV_REQ_ERR, + FLUSH_RNR_RETRY_EXC_ERR, +}; + +enum irdma_qp_event_type { + IRDMA_QP_EVENT_CATASTROPHIC, + IRDMA_QP_EVENT_ACCESS_ERR, + IRDMA_QP_EVENT_REQ_ERR, +}; + +enum irdma_cmpl_status { + IRDMA_COMPL_STATUS_SUCCESS = 0, + IRDMA_COMPL_STATUS_FLUSHED, + IRDMA_COMPL_STATUS_INVALID_WQE, + IRDMA_COMPL_STATUS_QP_CATASTROPHIC, + IRDMA_COMPL_STATUS_REMOTE_TERMINATION, + IRDMA_COMPL_STATUS_INVALID_STAG, + IRDMA_COMPL_STATUS_BASE_BOUND_VIOLATION, + IRDMA_COMPL_STATUS_ACCESS_VIOLATION, + IRDMA_COMPL_STATUS_INVALID_PD_ID, + IRDMA_COMPL_STATUS_WRAP_ERROR, + IRDMA_COMPL_STATUS_STAG_INVALID_PDID, + IRDMA_COMPL_STATUS_RDMA_READ_ZERO_ORD, + IRDMA_COMPL_STATUS_QP_NOT_PRIVLEDGED, + IRDMA_COMPL_STATUS_STAG_NOT_INVALID, + IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_SIZE, + IRDMA_COMPL_STATUS_INVALID_PHYS_BUF_ENTRY, + IRDMA_COMPL_STATUS_INVALID_FBO, + IRDMA_COMPL_STATUS_INVALID_LEN, + IRDMA_COMPL_STATUS_INVALID_ACCESS, + IRDMA_COMPL_STATUS_PHYS_BUF_LIST_TOO_LONG, + IRDMA_COMPL_STATUS_INVALID_VIRT_ADDRESS, + IRDMA_COMPL_STATUS_INVALID_REGION, + IRDMA_COMPL_STATUS_INVALID_WINDOW, + IRDMA_COMPL_STATUS_INVALID_TOTAL_LEN, + IRDMA_COMPL_STATUS_UNKNOWN, +}; + +enum irdma_cmpl_notify { + IRDMA_CQ_COMPL_EVENT = 0, + IRDMA_CQ_COMPL_SOLICITED = 1, +}; + +enum irdma_qp_caps { + IRDMA_WRITE_WITH_IMM = 1, + IRDMA_SEND_WITH_IMM = 2, + IRDMA_ROCE = 4, + IRDMA_PUSH_MODE = 8, +}; + +struct irdma_srq_uk; +struct irdma_srq_uk_init_info; +struct irdma_qp_uk; +struct irdma_cq_uk; +struct irdma_qp_uk_init_info; +struct irdma_cq_uk_init_info; + +struct irdma_ring { + u32 head; + u32 tail; /* effective tail */ + u32 true_tail; + u32 size; +}; + +struct irdma_cqe { + __le64 buf[IRDMA_CQE_SIZE]; +}; + +struct irdma_extended_cqe { + __le64 buf[IRDMA_EXTENDED_CQE_SIZE]; +}; + +struct irdma_post_send_combined_inline_sge { + struct ib_sge * sg_list; + void *data; + u32 num_sges; + u32 len; + u32 ah_id; + u32 qkey; + u32 dest_qp; +}; + +struct irdma_post_send { + struct ib_sge * sg_list; + u32 num_sges; + u32 qkey; + u32 dest_qp; + u32 ah_id; +}; + +struct irdma_post_rq_info { + u64 wr_id; + struct ib_sge * sg_list; + u32 num_sges; +}; + +struct irdma_rdma_write_combined_inline_sge { + struct ib_sge * lo_sg_list; + void *data; + u32 num_lo_sges; + u32 len; + struct ib_sge rem_addr; +}; + +struct irdma_rdma_write { + struct ib_sge * lo_sg_list; + u32 num_lo_sges; + struct ib_sge rem_addr; +}; + +struct irdma_rdma_read { + struct ib_sge * lo_sg_list; + u32 num_lo_sges; + struct ib_sge rem_addr; +}; + +struct irdma_bind_window { + irdma_stag mr_stag; + u64 bind_len; + void *va; + enum irdma_addressing_type addressing_type; + bool ena_reads:1; + bool ena_writes:1; + irdma_stag mw_stag; + bool mem_window_type_1:1; + bool remote_atomics_en:1; +}; + +struct irdma_atomic_fetch_add { + u64 tagged_offset; + u64 remote_tagged_offset; + u64 fetch_add_data_bytes; + u32 stag; + u32 remote_stag; +}; + +struct irdma_atomic_compare_swap { + u64 tagged_offset; + u64 remote_tagged_offset; + u64 swap_data_bytes; + u64 compare_data_bytes; + u32 stag; + u32 remote_stag; +}; + +struct irdma_atomic_write { + u64 tagged_offset; + u64 remote_tagged_offset; + u64 write_data_bytes; + u64 inline_data; + u32 remote_stag; + u32 stag; + bool is_inline_data:1; +}; + +struct irdma_flush_mem_region { + u64 remote_tagged_offset; + u32 remote_stag; + u32 length; + u8 selectivity; + u8 placement_type; +}; +struct irdma_inv_local_stag { + irdma_stag target_stag; +}; + +struct irdma_post_sq_info { + u64 wr_id; + u8 op_type; + u8 l4len; + bool signaled:1; + bool read_fence:1; + bool local_fence:1; + bool inline_data:1; + bool imm_data_valid:1; + bool push_wqe:1; + bool report_rtt:1; + bool udp_hdr:1; + bool defer_flag:1; + bool remote_atomic_en:1; + u32 imm_data; + u32 stag_to_inv; + union { + struct irdma_post_send send; + struct irdma_rdma_write rdma_write; + struct irdma_rdma_read rdma_read; + struct irdma_bind_window bind_window; + struct irdma_inv_local_stag inv_local_stag; + struct irdma_atomic_fetch_add atomic_fetch_add; + struct irdma_atomic_compare_swap atomic_compare_swap; + struct irdma_rdma_write_combined_inline_sge rdma_write_combined_sge_inline; + struct irdma_post_send_combined_inline_sge send_combined_sge_inline; + struct irdma_atomic_write atomic_write; + struct irdma_flush_mem_region flush_mem_region; + } op; +}; + +struct irdma_cq_poll_info { + u64 wr_id; + irdma_qp_handle qp_handle; + u32 bytes_xfered; + u32 qp_id; + u32 ud_src_qpn; + u32 imm_data; + irdma_stag inv_stag; /* or L_R_Key */ + enum irdma_cmpl_status comp_status; + u16 major_err; + u16 minor_err; + u16 ud_vlan; + u8 ud_smac[6]; + u8 op_type; + u8 q_type; + bool stag_invalid_set:1; /* or L_R_Key set */ + bool push_dropped:1; + bool error:1; + bool solicited_event:1; + bool ipv4:1; + bool ud_vlan_valid:1; + bool ud_smac_valid:1; + bool imm_valid:1; +}; + +struct qp_err_code { + enum irdma_flush_opcode flush_code; + enum irdma_qp_event_type event_type; +}; + +int irdma_uk_flush_mem_region(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq); +int irdma_uk_atomic_write(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq); + +int irdma_uk_atomic_compare_swap(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq); +int irdma_uk_atomic_fetch_add(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq); +int irdma_uk_inline_rdma_write(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq); +int irdma_uk_inline_send(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, bool post_sq); +int irdma_uk_post_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, + bool post_sq); +int irdma_uk_post_receive(struct irdma_qp_uk *qp, + struct irdma_post_rq_info *info); +void irdma_uk_qp_post_wr(struct irdma_qp_uk *qp); +int irdma_uk_rdma_read(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, + bool inv_stag, bool post_sq); +int irdma_uk_rdma_write(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, + bool post_sq); +int irdma_uk_send(struct irdma_qp_uk *qp, struct irdma_post_sq_info *info, + bool post_sq); +int irdma_uk_stag_local_invalidate(struct irdma_qp_uk *qp, + struct irdma_post_sq_info *info, + bool post_sq); + +struct irdma_wqe_uk_ops { + void (*iw_copy_inline_data)(u8 *dest, struct ib_sge *sge_list, u32 num_sges, u8 polarity); + u16 (*iw_inline_data_size_to_quanta)(u32 data_size); + void (*iw_set_fragment)(__le64 *wqe, u32 offset, struct ib_sge *sge, + u8 valid); + void (*iw_set_mw_bind_wqe)(__le64 *wqe, + struct irdma_bind_window *op_info); +}; + +int irdma_uk_cq_poll_cmpl(struct irdma_cq_uk *cq, + struct irdma_cq_poll_info *info); +void irdma_uk_cq_request_notification(struct irdma_cq_uk *cq, + enum irdma_cmpl_notify cq_notify); +void irdma_uk_cq_resize(struct irdma_cq_uk *cq, void *cq_base, int size); +void irdma_uk_cq_set_resized_cnt(struct irdma_cq_uk *qp, u16 cnt); +int irdma_uk_cq_init(struct irdma_cq_uk *cq, + struct irdma_cq_uk_init_info *info); +int irdma_uk_qp_init(struct irdma_qp_uk *qp, + struct irdma_qp_uk_init_info *info); +void irdma_uk_calc_shift_wq(struct irdma_qp_uk_init_info *ukinfo, u8 *sq_shift, + u8 *rq_shift); +int irdma_uk_calc_depth_shift_sq(struct irdma_qp_uk_init_info *ukinfo, + u32 *sq_depth, u8 *sq_shift); +int irdma_uk_calc_depth_shift_rq(struct irdma_qp_uk_init_info *ukinfo, + u32 *rq_depth, u8 *rq_shift); +int irdma_uk_srq_init(struct irdma_srq_uk *srq, + struct irdma_srq_uk_init_info *info); +int irdma_uk_srq_post_receive(struct irdma_srq_uk *srq, + struct irdma_post_rq_info *info); + +struct irdma_srq_uk { + u32 srq_caps; + struct irdma_qp_quanta *srq_base; + struct irdma_uk_attrs *uk_attrs; + __le64 *shadow_area; + struct irdma_ring srq_ring; + struct irdma_ring initial_ring; + u32 srq_id; + u32 srq_size; + u32 max_srq_frag_cnt; + struct irdma_wqe_uk_ops wqe_ops; + u8 srwqe_polarity; + u8 wqe_size; + u8 wqe_size_multiplier; + u8 deferred_flag; +}; + +struct irdma_srq_uk_init_info { + struct irdma_qp_quanta *srq; + struct irdma_uk_attrs *uk_attrs; + __le64 *shadow_area; + u64 *srq_wrid_array; + u32 srq_id; + u32 srq_caps; + u32 srq_size; + u32 max_srq_frag_cnt; +}; + +struct irdma_sq_uk_wr_trk_info { + u64 wrid; + u32 wr_len; + u16 quanta; + u8 reserved[2]; +}; + +struct irdma_qp_quanta { + __le64 elem[IRDMA_WQE_SIZE]; +}; + +struct irdma_qp_uk { + struct irdma_qp_quanta *sq_base; + struct irdma_qp_quanta *rq_base; + struct irdma_srq_uk *srq_uk; + struct irdma_uk_attrs *uk_attrs; + u32 __iomem *wqe_alloc_db; + struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; + u64 *rq_wrid_array; + __le64 *shadow_area; + __le32 *push_db; + __le64 *push_wqe; + void *push_db_map; + void *push_wqe_map; + struct irdma_ring sq_ring; + struct irdma_ring rq_ring; + struct irdma_ring initial_ring; + u32 qp_id; + u32 qp_caps; + u32 sq_size; + u32 rq_size; + u32 max_sq_frag_cnt; + u32 max_rq_frag_cnt; + u32 max_inline_data; + struct irdma_wqe_uk_ops wqe_ops; + u16 conn_wqes; + u8 qp_type; + u8 swqe_polarity; + u8 swqe_polarity_deferred; + u8 rwqe_polarity; + u8 rq_wqe_size; + u8 rq_wqe_size_multiplier; + u8 start_wqe_idx; + bool deferred_flag:1; + bool push_mode:1; /* whether the last post wqe was pushed */ + bool push_dropped:1; + bool first_sq_wq:1; + bool sq_flush_complete:1; /* Indicates flush was seen and SQ was empty after the flush */ + bool rq_flush_complete:1; /* Indicates flush was seen and RQ was empty after the flush */ + bool destroy_pending:1; /* Indicates the QP is being destroyed */ + void *back_qp; + spinlock_t *lock; + u8 dbg_rq_flushed; + u16 ord_cnt; + u8 sq_flush_seen; + u8 rq_flush_seen; + u8 rd_fence_rate; +}; + +struct irdma_cq_uk { + struct irdma_cqe *cq_base; + u32 __iomem *cqe_alloc_db; + u32 __iomem *cq_ack_db; + __le64 *shadow_area; + u32 cq_id; + u32 cq_size; + struct irdma_ring cq_ring; + u8 polarity; + bool avoid_mem_cflct:1; +}; + +struct irdma_qp_uk_init_info { + struct irdma_qp_quanta *sq; + struct irdma_qp_quanta *rq; + struct irdma_srq_uk *srq_uk; + struct irdma_uk_attrs *uk_attrs; + u32 __iomem *wqe_alloc_db; + __le64 *shadow_area; + struct irdma_sq_uk_wr_trk_info *sq_wrtrk_array; + u64 *rq_wrid_array; + u32 qp_id; + u32 qp_caps; + u32 sq_size; + u32 rq_size; + u32 max_sq_frag_cnt; + u32 max_rq_frag_cnt; + u32 max_inline_data; + u32 sq_depth; + u32 rq_depth; + u8 first_sq_wq; + u8 start_wqe_idx; + u8 type; + u8 sq_shift; + u8 rq_shift; + u8 rd_fence_rate; + int abi_ver; + bool legacy_mode; +}; + +struct irdma_cq_uk_init_info { + u32 __iomem *cqe_alloc_db; + u32 __iomem *cq_ack_db; + struct irdma_cqe *cq_base; + __le64 *shadow_area; + u32 cq_size; + u32 cq_id; + bool avoid_mem_cflct; +}; + +void irdma_print_cqes(struct irdma_cq_uk *cq); +void irdma_print_sq_wqes(struct irdma_qp_uk *qp); +__le64 *irdma_qp_get_next_send_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx, + u16 *quanta, u32 total_size, + struct irdma_post_sq_info *info); +__le64 *irdma_srq_get_next_recv_wqe(struct irdma_srq_uk *srq, u32 *wqe_idx); +__le64 *irdma_qp_get_next_recv_wqe(struct irdma_qp_uk *qp, u32 *wqe_idx); +void irdma_uk_clean_cq(void *q, struct irdma_cq_uk *cq); +int irdma_nop(struct irdma_qp_uk *qp, u64 wr_id, bool signaled, bool post_sq); +int irdma_fragcnt_to_quanta_sq(u32 frag_cnt, u16 *quanta); +int irdma_fragcnt_to_wqesize_rq(u32 frag_cnt, u16 *wqe_size); +void irdma_get_wqe_shift(struct irdma_uk_attrs *uk_attrs, u32 sge, + u32 inline_data, u8 *shift); +int irdma_get_sqdepth(struct irdma_uk_attrs *uk_attrs, u32 sq_size, + u8 shift, u32 *sqdepth); +int irdma_get_rqdepth(struct irdma_uk_attrs *uk_attrs, u32 rq_size, + u8 shift, u32 *rqdepth); +int irdma_get_srqdepth(struct irdma_uk_attrs *uk_attrs, u32 srq_size, + u8 shift, u32 *srqdepth); +void irdma_qp_push_wqe(struct irdma_qp_uk *qp, __le64 *wqe, u16 quanta, + u32 wqe_idx, bool post_sq); +void irdma_clr_wqes(struct irdma_qp_uk *qp, u32 qp_wqe_idx); + +static inline struct qp_err_code irdma_ae_to_qp_err_code(u16 ae_id) +{ + struct qp_err_code qp_err = {}; + + switch (ae_id) { + case IRDMA_AE_AMP_BOUNDS_VIOLATION: + case IRDMA_AE_AMP_INVALID_STAG: + case IRDMA_AE_AMP_RIGHTS_VIOLATION: + case IRDMA_AE_AMP_UNALLOCATED_STAG: + case IRDMA_AE_AMP_BAD_PD: + case IRDMA_AE_AMP_BAD_QP: + case IRDMA_AE_AMP_BAD_STAG_KEY: + case IRDMA_AE_AMP_BAD_STAG_INDEX: + case IRDMA_AE_AMP_TO_WRAP: + case IRDMA_AE_PRIV_OPERATION_DENIED: + qp_err.flush_code = FLUSH_PROT_ERR; + qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; + break; + case IRDMA_AE_UDA_XMIT_BAD_PD: + case IRDMA_AE_WQE_UNEXPECTED_OPCODE: + qp_err.flush_code = FLUSH_LOC_QP_OP_ERR; + qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; + break; + case IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT: + case IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG: + case IRDMA_AE_UDA_L4LEN_INVALID: + case IRDMA_AE_DDP_UBE_INVALID_MO: + case IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER: + qp_err.flush_code = FLUSH_LOC_LEN_ERR; + qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; + break; + case IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS: + case IRDMA_AE_IB_REMOTE_ACCESS_ERROR: + qp_err.flush_code = FLUSH_REM_ACCESS_ERR; + qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; + break; + case IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS: + case IRDMA_AE_AMP_MWBIND_BIND_DISABLED: + case IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS: + case IRDMA_AE_AMP_MWBIND_VALID_STAG: + qp_err.flush_code = FLUSH_MW_BIND_ERR; + qp_err.event_type = IRDMA_QP_EVENT_ACCESS_ERR; + break; + case IRDMA_AE_LLP_TOO_MANY_RETRIES: + qp_err.flush_code = FLUSH_RETRY_EXC_ERR; + qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; + break; + case IRDMA_AE_IB_INVALID_REQUEST: + qp_err.flush_code = FLUSH_REM_INV_REQ_ERR; + qp_err.event_type = IRDMA_QP_EVENT_REQ_ERR; + break; + case IRDMA_AE_LLP_SEGMENT_TOO_SMALL: + case IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR: + case IRDMA_AE_ROCE_RSP_LENGTH_ERROR: + case IRDMA_AE_ROCE_REQ_LENGTH_ERROR: + case IRDMA_AE_IB_REMOTE_OP_ERROR: + qp_err.flush_code = FLUSH_REM_OP_ERR; + qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; + break; + case IRDMA_AE_LLP_TOO_MANY_RNRS: + qp_err.flush_code = FLUSH_RNR_RETRY_EXC_ERR; + qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; + break; + case IRDMA_AE_LCE_QP_CATASTROPHIC: + case IRDMA_AE_REMOTE_QP_CATASTROPHIC: + case IRDMA_AE_LOCAL_QP_CATASTROPHIC: + case IRDMA_AE_RCE_QP_CATASTROPHIC: + qp_err.flush_code = FLUSH_FATAL_ERR; + qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; + break; + default: + qp_err.flush_code = FLUSH_GENERAL_ERR; + qp_err.event_type = IRDMA_QP_EVENT_CATASTROPHIC; + break; + } + + return qp_err; +} +#endif /* IRDMA_USER_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/utils.c b/drivers/intel/irdma-1.14.33/src/irdma/utils.c new file mode 100644 index 000000000..f37296aad --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/utils.c @@ -0,0 +1,3321 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "main.h" + +LIST_HEAD(irdma_handlers); +DEFINE_SPINLOCK(irdma_handler_lock); + +static const struct ae_desc ae_desc_list[] = { + {IRDMA_AE_AMP_UNALLOCATED_STAG, "Unallocated memory key (L-Key/R-Key)"}, + {IRDMA_AE_AMP_INVALID_STAG, "Invalid memory key (L-Key/R-Key)"}, + {IRDMA_AE_AMP_BAD_QP, + "Memory protection error: Accessing Memory Window (MW) which belongs to a different QP"}, + {IRDMA_AE_AMP_BAD_PD, + "Memory protection error: Accessing Memory Window (MW)/Memory Region (MR) which belongs to a different PD"}, + {IRDMA_AE_AMP_BAD_STAG_KEY, "Bad memory key (L-Key/R-Key)"}, + {IRDMA_AE_AMP_BAD_STAG_INDEX, "Bad memory key (L-Key/R-Key): Too large memory key index"}, + {IRDMA_AE_AMP_BOUNDS_VIOLATION, "Memory Window (MW)/Memory Region (MR) bounds violation"}, + {IRDMA_AE_AMP_RIGHTS_VIOLATION, "Memory Window (MW)/Memory Region (MR) rights violation"}, + {IRDMA_AE_AMP_TO_WRAP, + "Memory protection error: The address within Memory Window (MW)/Memory Region (MR) wraps"}, + {IRDMA_AE_AMP_FASTREG_VALID_STAG, + "Fastreg error: Registration to a valid MR"}, + {IRDMA_AE_AMP_FASTREG_MW_STAG, + "Fastreg error: Registration to a valid Memory Window (MW)"}, + {IRDMA_AE_AMP_FASTREG_INVALID_RIGHTS, "Fastreg error: Invalid rights"}, + {IRDMA_AE_AMP_FASTREG_INVALID_LENGTH, "Fastreg error: Invalid length"}, + {IRDMA_AE_AMP_INVALIDATE_SHARED, "Attempt to invalidate a shared MR"}, + {IRDMA_AE_AMP_INVALIDATE_NO_REMOTE_ACCESS_RIGHTS, + "Attempt to remotely invalidate Memory Window (MW)/Memory Region (MR) without rights"}, + {IRDMA_AE_AMP_INVALIDATE_MR_WITH_BOUND_WINDOWS, + "Attempt to invalidate MR with a bound Memory Window (MW)"}, + {IRDMA_AE_AMP_MWBIND_VALID_STAG, + "Attempt to bind an Memory Window (MW) with a valid MW memory key (L-Key/R-Key)"}, + {IRDMA_AE_AMP_MWBIND_OF_MR_STAG, + "Attempt to bind an Memory Window (MW) with an MR memory key (L-Key/R-Key)"}, + {IRDMA_AE_AMP_MWBIND_TO_ZERO_BASED_STAG, + "Attempt to bind an Memory Window (MW) to a zero based MR"}, + {IRDMA_AE_AMP_MWBIND_TO_MW_STAG, + "Attempt to bind an Memory Window (MW) using MW memory key (L-Key/R-Key) instead of MR memory key (L-Key/R-Key)"}, + {IRDMA_AE_AMP_MWBIND_INVALID_RIGHTS, "Memory Window (MW) bind error: Invalid rights"}, + {IRDMA_AE_AMP_MWBIND_INVALID_BOUNDS, "Memory Window (MW) bind error: Invalid bounds"}, + {IRDMA_AE_AMP_MWBIND_TO_INVALID_PARENT, + "Memory Window (MW) bind error: Invalid parent MR"}, + {IRDMA_AE_AMP_MWBIND_BIND_DISABLED, + "Memory Window (MW) bind error: Disabled bind support"}, + {IRDMA_AE_PRIV_OPERATION_DENIED, + "Denying a privileged operation on a non-privileged QP"}, + {IRDMA_AE_AMP_INVALIDATE_TYPE1_MW, "Memory Window (MW) error: Invalidate type 1 MW"}, + {IRDMA_AE_AMP_MWBIND_ZERO_BASED_TYPE1_MW, + "Memory Window (MW) bind error: Zero-based addressing for type 1 MW"}, + {IRDMA_AE_AMP_FASTREG_INVALID_PBL_HPS_CFG, + "Fastreg error: Invalid host page size config"}, + {IRDMA_AE_AMP_MWBIND_WRONG_TYPE, "MB bind error: Wrong Memory Window (MW) type"}, + {IRDMA_AE_AMP_FASTREG_PBLE_MISMATCH, + "Fastreg error: Invalid request to change physical MR to virtual or vice versa"}, + {IRDMA_AE_UDA_XMIT_DGRAM_TOO_LONG, + "Userspace Direct Access (UDA) QP xmit error: Packet length exceeds the QP MTU"}, + {IRDMA_AE_UDA_XMIT_BAD_PD, + "Userspace Direct Access (UDA) QP xmit error: Attempt to access a different PD"}, + {IRDMA_AE_UDA_XMIT_DGRAM_TOO_SHORT, + "Userspace Direct Access (UDA) QP xmit error: Too short packet length"}, + {IRDMA_AE_UDA_L4LEN_INVALID, + "Userspace Direct Access (UDA) error: Invalid packet length field"}, + {IRDMA_AE_BAD_CLOSE, + "iWARP error: Data is received when QP state is closing"}, + {IRDMA_AE_RDMAP_ROE_BAD_LLP_CLOSE, + "iWARP error: FIN is received when xmit data is pending"}, + {IRDMA_AE_CQ_OPERATION_ERROR, "CQ overflow"}, + {IRDMA_AE_RDMA_READ_WHILE_ORD_ZERO, + "QP error: Attempted RDMA Read when the outbound RDMA Read queue depth is zero"}, + {IRDMA_AE_STAG_ZERO_INVALID, + "Zero invalid memory key (L-Key/R-Key) on inbound RDMA R/W"}, + {IRDMA_AE_IB_RREQ_AND_Q1_FULL, + "QP error: Received RDMA Read request when the inbound RDMA Read queue is full"}, + {IRDMA_AE_IB_INVALID_REQUEST, + "QP error: Invalid operation detected by the remote peer"}, + {IRDMA_AE_SRQ_LIMIT, + "Shared RQ event: Reached receive WQE limit"}, + {IRDMA_AE_WQE_UNEXPECTED_OPCODE, + "QP error: Invalid opcode in SQ WQE"}, + {IRDMA_AE_WQE_INVALID_PARAMETER, + "QP error: Invalid parameter in a WQE"}, + {IRDMA_AE_WQE_INVALID_FRAG_DATA, + "QP error: Invalid fragment in a WQE"}, + {IRDMA_AE_IB_REMOTE_ACCESS_ERROR, + "RoCEv2 error: Remote access error"}, + {IRDMA_AE_IB_REMOTE_OP_ERROR, + "RoCEv2 error: Remote operation error"}, + {IRDMA_AE_SRQ_CATASTROPHIC_ERROR, "Shared RQ catastrophicerror"}, + {IRDMA_AE_WQE_LSMM_TOO_LONG, "iWARP error: Connection error"}, + {IRDMA_AE_ATOMIC_ALIGNMENT, + "Atomic error: Memory address isn't 64-bit aligned"}, + {IRDMA_AE_ATOMIC_MASK, "Atomic error: Mask field isn't set"}, + {IRDMA_AE_INVALID_REQUEST, + "Atomic error: QP isn't enabled for remote atomic support"}, + {IRDMA_AE_PCIE_ATOMIC_DISABLE, + "Atomic error: PCIe interface isn't enabled for atomic operations"}, + {IRDMA_AE_DDP_INVALID_MSN_GAP_IN_MSN, + "iWARP error: Invalid message sequence number"}, + {IRDMA_AE_DDP_UBE_DDP_MESSAGE_TOO_LONG_FOR_AVAILABLE_BUFFER, + "iWARP error: Inbound message is too long for the available buffer"}, + {IRDMA_AE_DDP_UBE_INVALID_DDP_VERSION, "iWARP error: Invalid DDP protocol version"}, + {IRDMA_AE_DDP_UBE_INVALID_MO, "Received message with too large offset"}, + {IRDMA_AE_DDP_UBE_INVALID_MSN_NO_BUFFER_AVAILABLE, + "iWARP error: Inbound Send message when no receive buffer is available"}, + {IRDMA_AE_DDP_UBE_INVALID_QN, "iWARP error: Invalid QP number in inbound packet"}, + {IRDMA_AE_DDP_NO_L_BIT, + "iWARP error: Last bit not set in an inbound packet which completes RDMA Read"}, + {IRDMA_AE_RDMAP_ROE_INVALID_RDMAP_VERSION, "iWARP error: Invalid RDMAP protocol version"}, + {IRDMA_AE_RDMAP_ROE_UNEXPECTED_OPCODE, "QP error: Invalid opcode"}, + {IRDMA_AE_ROE_INVALID_RDMA_READ_REQUEST, "Inbound Read request when QP isn't enabled for RDMA Read"}, + {IRDMA_AE_ROE_INVALID_RDMA_WRITE_OR_READ_RESP, + "Inbound RDMA Read response or RDMA Write when QP isn't enabled for RDMA R/W"}, + {IRDMA_AE_ROCE_RSP_LENGTH_ERROR, "RoCEv2 error: Received packet with incorrect length field"}, + {IRDMA_AE_ROCE_EMPTY_MCG, "RoCEv2 error: Multicast group has no valid members"}, + {IRDMA_AE_ROCE_BAD_MC_IP_ADDR, "RoCEv2 error: Multicast IP address doesn't match"}, + {IRDMA_AE_ROCE_BAD_MC_QPID, "RoCEv2 error: Multicast packet QP number isn't 0xffffff"}, + {IRDMA_AE_MCG_QP_PROTOCOL_MISMATCH, "RoCEv2 error: Multicast packet protocol mismatch"}, + {IRDMA_AE_INVALID_ARP_ENTRY, "Invalid ARP entry"}, + {IRDMA_AE_INVALID_TCP_OPTION_RCVD, "iWARP error: Invalid TCP option"}, + {IRDMA_AE_STALE_ARP_ENTRY, "Stale ARP entry"}, + {IRDMA_AE_INVALID_AH_ENTRY, "Invalid AH entry"}, + {IRDMA_AE_LLP_CLOSE_COMPLETE, + "iWARP event: Graceful close complete"}, + {IRDMA_AE_LLP_CONNECTION_RESET, + "iWARP event: Received a TCP packet with a RST bit set"}, + {IRDMA_AE_LLP_FIN_RECEIVED, + "iWARP event: Received a TCP packet with a FIN bit set"}, + {IRDMA_AE_LLP_RECEIVED_MARKER_AND_LENGTH_FIELDS_DONT_MATCH, + "iWARP error: Unable to close a gap in the TCP sequence"}, + {IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR, "Received an ICRC error"}, + {IRDMA_AE_LLP_SEGMENT_TOO_SMALL, + "iWARP error: Received a packet with insufficient space for protocol headers"}, + {IRDMA_AE_LLP_SYN_RECEIVED, + "iWARP event: Received a TCP packet with a SYN bit set"}, + {IRDMA_AE_LLP_TERMINATE_RECEIVED, + "iWARP error: Received a terminate message"}, + {IRDMA_AE_LLP_TOO_MANY_RETRIES, "Connection error: The max number of retries has been reached"}, + {IRDMA_AE_LLP_TOO_MANY_KEEPALIVE_RETRIES, + "Connection error: The max number of keepalive retries has been reached"}, + {IRDMA_AE_LLP_DOUBT_REACHABILITY, + "Connection error: Doubt reachability (usually occurs after the max number of retries has been reached)"}, + {IRDMA_AE_LLP_CONNECTION_ESTABLISHED, + "iWARP event: Connection established"}, + {IRDMA_AE_LLP_TOO_MANY_RNRS, "RoCEv2: Too many RNR NACKs"}, + {IRDMA_AE_RESOURCE_EXHAUSTION, + "QP error: Resource exhaustion"}, + {IRDMA_AE_RESET_SENT, + "Reset sent (as requested via Modify QP)"}, + {IRDMA_AE_TERMINATE_SENT, + "Terminate sent (as requested via Modify QP)"}, + {IRDMA_AE_RESET_NOT_SENT, + "Reset not sent (but requested via Modify QP)"}, + {IRDMA_AE_LCE_QP_CATASTROPHIC, + "QP error: HW transaction resulted in catastrophic error"}, + {IRDMA_AE_LCE_FUNCTION_CATASTROPHIC, + "PCIe function error: HW transaction resulted in catastrophic error"}, + {IRDMA_AE_LCE_CQ_CATASTROPHIC, + "CQ error: HW transaction resulted in catastrophic error"}, + {IRDMA_AE_REMOTE_QP_CATASTROPHIC, + "Remote QP error: HW transaction resulted in catastrophic error"}, + {IRDMA_AE_LOCAL_QP_CATASTROPHIC, + "Local QP error: HW transaction resulted in catastrophic error"}, + {IRDMA_AE_RCE_QP_CATASTROPHIC, + "Remote CQ error: HW transaction resulted in catastrophic error"}, + {IRDMA_AE_QP_SUSPEND_COMPLETE, "QP event: Suspend complete"}, + {IRDMA_AE_CQP_DEFERRED_COMPLETE, + "One or more deferred completions have finished"}, + {IRDMA_AE_ADAPTER_CATASTROPHIC, + "Adapter error: HW transaction resulted in catastrophic error"} +}; + +/** + * irdma_get_ae_desc - returns AE description + * @ae_id: the AE number + */ +const char *irdma_get_ae_desc(u16 ae_id) +{ + const char *desc = ""; + int i; + + for (i = 0; i < ARRAY_SIZE(ae_desc_list); i++) { + if (ae_desc_list[i].id == ae_id) { + desc = ae_desc_list[i].desc; + break; + } + } + return desc; +} + +/** + * irdma_arp_table -manage arp table + * @rf: RDMA PCI function + * @ip_addr: ip address for device + * @mac_addr: mac address ptr + * @action: modify, delete or add/update + */ +int irdma_arp_table(struct irdma_pci_f *rf, u32 *ip_addr, const u8 *mac_addr, + u32 action) +{ + unsigned long flags; + int arp_index; + u32 ip[4] = {}; + + memcpy(ip, ip_addr, sizeof(ip)); + + spin_lock_irqsave(&rf->arp_lock, flags); + for (arp_index = 0; (u32)arp_index < rf->arp_table_size; arp_index++) { + if (!memcmp(rf->arp_table[arp_index].ip_addr, ip, sizeof(ip)) && + !rf->arp_table[arp_index].delete_pending) + break; + } + + switch (action) { + case IRDMA_ARP_ADD_UPDATE: /* ARP Add or Update */ + if (arp_index == rf->arp_table_size) { + if (irdma_alloc_rsrc(rf, rf->allocated_arps, + rf->arp_table_size, + (u32 *)&arp_index, + &rf->next_arp_index)) { + arp_index = -1; + break; + } + refcount_set(&rf->arp_table[arp_index].refcnt, 0); + } + + memcpy(rf->arp_table[arp_index].ip_addr, ip, + sizeof(rf->arp_table[arp_index].ip_addr)); + ether_addr_copy(rf->arp_table[arp_index].mac_addr, mac_addr); + break; + case IRDMA_ARP_RESOLVE: + if (arp_index == rf->arp_table_size) + arp_index = -1; + break; + case IRDMA_ARP_DELETE: + if (arp_index == rf->arp_table_size) { + arp_index = -1; + break; + } + + if (!refcount_read(&rf->arp_table[arp_index].refcnt)) { + memset(rf->arp_table[arp_index].ip_addr, 0, + sizeof(rf->arp_table[arp_index].ip_addr)); + eth_zero_addr(rf->arp_table[arp_index].mac_addr); + irdma_free_rsrc(rf, rf->allocated_arps, arp_index); + rf->arp_table[arp_index].delete_pending = false; + } else { + rf->arp_table[arp_index].delete_pending = true; + arp_index = -1; /* prevent immediate CQP ARP index deletion */ + } + break; + default: + arp_index = -1; + break; + } + + spin_unlock_irqrestore(&rf->arp_lock, flags); + return arp_index; +} + +static int irdma_get_arp(struct irdma_pci_f *rf, u16 arp_index) +{ + unsigned long flags; + u32 ip_zero[4] = {}; + + if (arp_index >= rf->arp_table_size) + return -EINVAL; + + spin_lock_irqsave(&rf->arp_lock, flags); + if (!memcmp(rf->arp_table[arp_index].ip_addr, ip_zero, sizeof(ip_zero))) { + spin_unlock_irqrestore(&rf->arp_lock, flags); + return -EINVAL; + } + if (!refcount_read(&rf->arp_table[arp_index].refcnt)) + refcount_set(&rf->arp_table[arp_index].refcnt, 1); + else + refcount_inc(&rf->arp_table[arp_index].refcnt); + spin_unlock_irqrestore(&rf->arp_lock, flags); + + return 0; +} + +static void irdma_put_arp(struct irdma_pci_f *rf, u16 arp_index) +{ + unsigned long flags; + + if (arp_index >= rf->arp_table_size) + return; + spin_lock_irqsave(&rf->arp_lock, flags); + if (!refcount_dec_and_test(&rf->arp_table[arp_index].refcnt)) { + spin_unlock_irqrestore(&rf->arp_lock, flags); + return; + } + + if (rf->arp_table[arp_index].delete_pending) { + u32 ip_addr[4]; + + memcpy(ip_addr, rf->arp_table[arp_index].ip_addr, + sizeof(ip_addr)); + memset(rf->arp_table[arp_index].ip_addr, 0, + sizeof(rf->arp_table[arp_index].ip_addr)); + eth_zero_addr(rf->arp_table[arp_index].mac_addr); + spin_unlock_irqrestore(&rf->arp_lock, flags); + irdma_arp_cqp_op(rf, arp_index, NULL, IRDMA_ARP_DELETE); + rf->arp_table[arp_index].delete_pending = false; + irdma_free_rsrc(rf, rf->allocated_arps, arp_index); + } else { + spin_unlock_irqrestore(&rf->arp_lock, flags); + } +} + +/** + * irdma_add_arp - add a new arp entry if needed and resolve it + * @rf: RDMA function + * @ip: IP address + * @mac: MAC address + */ +int irdma_add_arp(struct irdma_pci_f *rf, u32 *ip, const u8 *mac) +{ + irdma_manage_arp_cache(rf, mac, ip, IRDMA_ARP_ADD_UPDATE); + + return irdma_arp_table(rf, ip, NULL, IRDMA_ARP_RESOLVE); +} + +/** + * wr32 - write 32 bits to hw register + * @hw: hardware information including registers + * @reg: register offset + * @val: value to write to register + */ +inline void wr32(struct irdma_hw *hw, u32 reg, u32 val) +{ + writel(val, hw->hw_addr + reg); +} + +/** + * rd32 - read a 32 bit hw register + * @hw: hardware information including registers + * @reg: register offset + * + * Return value of register content + */ +inline u32 rd32(struct irdma_hw *hw, u32 reg) +{ + return readl(hw->hw_addr + reg); +} + +/** + * rd64 - read a 64 bit hw register + * @hw: hardware information including registers + * @reg: register offset + * + * Return value of register content + */ +inline u64 rd64(struct irdma_hw *hw, u32 reg) +{ + return readq(hw->hw_addr + reg); +} + +static void irdma_gid_change_event(struct ib_device *ibdev) +{ + struct ib_event ib_event; + + ib_event.event = IB_EVENT_GID_CHANGE; + ib_event.device = ibdev; + ib_event.element.port_num = 1; + ib_dispatch_event(&ib_event); +} + +static void irdma_if_notify_sched(struct irdma_device *iwdev, + struct net_device *netdev, + u32 *ipaddr, bool ipv4, bool ifup) +{ + struct if_notify_work *work; + + work = kzalloc(sizeof(*work), GFP_ATOMIC); + if (!work) + return; + work->iwdev = iwdev; + work->vlan_id = rdma_vlan_dev_vlan_id(netdev); + work->ipv4 = ipv4; + work->ifup = ifup; + memcpy(work->ipaddr, ipaddr, ipv4 ? 4 : 16); + + INIT_WORK(&work->work, irdma_if_notify_worker); + queue_work(iwdev->cleanup_wq, &work->work); +} +/** + * irdma_inetaddr_event - system notifier for ipv4 addr events + * @notifier: not used + * @event: event for notifier + * @ptr: if address + */ +int irdma_inetaddr_event(struct notifier_block *notifier, unsigned long event, + void *ptr) +{ + struct in_ifaddr *ifa = ptr; + struct net_device *real_dev, *netdev = ifa->ifa_dev->dev; + struct irdma_device *iwdev; + u32 local_ipaddr[4] = {}; + + real_dev = rdma_vlan_dev_real_dev(netdev); + if (!real_dev) + real_dev = netdev; + + iwdev = container_of(notifier, struct irdma_device, nb_inetaddr_event); + if (iwdev->netdev != real_dev) + return NOTIFY_DONE; + + local_ipaddr[0] = ntohl(ifa->ifa_address); + ibdev_dbg(&iwdev->ibdev, + "DEV: netdev %s event %lu local_ip=%pI4 MAC=%pM\n", + netdev_name(netdev), + event, &local_ipaddr, netdev->dev_addr); + switch (event) { + case NETDEV_DOWN: + irdma_manage_arp_cache(iwdev->rf, netdev->dev_addr, + local_ipaddr, IRDMA_ARP_DELETE); + irdma_if_notify_sched(iwdev, netdev, local_ipaddr, true, false); + irdma_gid_change_event(&iwdev->ibdev); + break; + case NETDEV_UP: + case NETDEV_CHANGEADDR: + irdma_manage_arp_cache(iwdev->rf, netdev->dev_addr, + local_ipaddr, IRDMA_ARP_ADD_UPDATE); + irdma_if_notify_sched(iwdev, netdev, local_ipaddr, true, true); + irdma_gid_change_event(&iwdev->ibdev); + break; + default: + break; + } + + return NOTIFY_DONE; +} + +/** + * irdma_inet6addr_event - system notifier for ipv6 addr events + * @notifier: not used + * @event: event for notifier + * @ptr: if address + */ +int irdma_inet6addr_event(struct notifier_block *notifier, unsigned long event, + void *ptr) +{ + struct inet6_ifaddr *ifa = ptr; + struct net_device *real_dev, *netdev = ifa->idev->dev; + struct irdma_device *iwdev; + u32 local_ipaddr6[4]; + + real_dev = rdma_vlan_dev_real_dev(netdev); + if (!real_dev) + real_dev = netdev; + + iwdev = container_of(notifier, struct irdma_device, nb_inet6addr_event); + if (iwdev->netdev != real_dev) + return NOTIFY_DONE; + + irdma_copy_ip_ntohl(local_ipaddr6, ifa->addr.in6_u.u6_addr32); + ibdev_dbg(&iwdev->ibdev, + "DEV: netdev %s event %lu local_ip=%pI6 MAC=%pM\n", + netdev_name(netdev), event, local_ipaddr6, netdev->dev_addr); + + switch (event) { + case NETDEV_DOWN: + irdma_manage_arp_cache(iwdev->rf, netdev->dev_addr, + local_ipaddr6, IRDMA_ARP_DELETE); + irdma_if_notify_sched(iwdev, netdev, local_ipaddr6, false, false); + irdma_gid_change_event(&iwdev->ibdev); + break; + case NETDEV_UP: + case NETDEV_CHANGEADDR: + irdma_manage_arp_cache(iwdev->rf, netdev->dev_addr, + local_ipaddr6, IRDMA_ARP_ADD_UPDATE); + irdma_if_notify_sched(iwdev, netdev, local_ipaddr6, + false, true); + irdma_gid_change_event(&iwdev->ibdev); + break; + default: + break; + } + + return NOTIFY_DONE; +} + +/** + * irdma_net_event - system notifier for net events + * @notifier: not used + * @event: event for notifier + * @ptr: neighbor + */ +int irdma_net_event(struct notifier_block *notifier, unsigned long event, + void *ptr) +{ + struct neighbour *neigh = ptr; + struct net_device *real_dev, *netdev = (struct net_device *)neigh->dev; + struct irdma_device *iwdev; + __be32 *p; + u32 local_ipaddr[4] = {}; + + switch (event) { + case NETEVENT_NEIGH_UPDATE: + + real_dev = rdma_vlan_dev_real_dev(netdev); + if (!real_dev) + real_dev = netdev; + + iwdev = container_of(notifier, struct irdma_device, nb_net_event); + if (iwdev->netdev != real_dev) + return NOTIFY_DONE; + + p = (__be32 *)neigh->primary_key; + if (neigh->tbl->family == AF_INET6) + irdma_copy_ip_ntohl(local_ipaddr, p); + else + local_ipaddr[0] = ntohl(*p); + ibdev_dbg(&iwdev->ibdev, + "DEV: netdev %s state %d local_ip=%pI4 MAC=%pM\n", + netdev_name(iwdev->netdev), neigh->nud_state, + local_ipaddr, neigh->ha); + + if (neigh->nud_state & NUD_VALID) + irdma_manage_arp_cache(iwdev->rf, neigh->ha, + local_ipaddr, + IRDMA_ARP_ADD_UPDATE); + else + irdma_manage_arp_cache(iwdev->rf, neigh->ha, + local_ipaddr, IRDMA_ARP_DELETE); + break; + default: + break; + } + + return NOTIFY_DONE; +} + +/** + * irdma_netdevice_event - system notifier for netdev events + * @notifier: not used + * @event: event for notifier + * @ptr: netdev + */ +int irdma_netdevice_event(struct notifier_block *notifier, unsigned long event, + void *ptr) +{ + struct irdma_device *iwdev; + struct net_device *netdev = netdev_notifier_info_to_dev(ptr); + + iwdev = container_of(notifier, struct irdma_device, nb_netdevice_event); + if (iwdev->netdev != netdev) + return NOTIFY_DONE; + + iwdev->iw_status = 1; + switch (event) { + case NETDEV_DOWN: + iwdev->iw_status = 0; + fallthrough; + case NETDEV_UP: + irdma_port_ibevent(iwdev); + break; + default: + break; + } + + return NOTIFY_DONE; +} + +void irdma_unregister_notifiers(struct irdma_device *iwdev) +{ + unregister_netdevice_notifier(&iwdev->nb_netdevice_event); + unregister_netevent_notifier(&iwdev->nb_net_event); + unregister_inet6addr_notifier(&iwdev->nb_inet6addr_event); + unregister_inetaddr_notifier(&iwdev->nb_inetaddr_event); +} + +int irdma_register_notifiers(struct irdma_device *iwdev) +{ + int ret; + + iwdev->nb_netdevice_event.notifier_call = irdma_netdevice_event; + ret = register_netdevice_notifier(&iwdev->nb_netdevice_event); + if (ret) { + ibdev_err(&iwdev->ibdev, "register_netdevice_notifier failed\n"); + return ret; + } + + iwdev->nb_net_event.notifier_call = irdma_net_event; + ret = register_netevent_notifier(&iwdev->nb_net_event); + if (ret) { + ibdev_err(&iwdev->ibdev, "register_netevent_notifier failed\n"); + goto netevent_error; + } + + iwdev->nb_inet6addr_event.notifier_call = irdma_inet6addr_event; + ret = register_inet6addr_notifier(&iwdev->nb_inet6addr_event); + if (ret) { + ibdev_err(&iwdev->ibdev, "register_inet6addr_notifier failed\n"); + goto inet6addr_error; + } + + iwdev->nb_inetaddr_event.notifier_call = irdma_inetaddr_event; + ret = register_inetaddr_notifier(&iwdev->nb_inetaddr_event); + if (ret) { + ibdev_err(&iwdev->ibdev, "register_inetaddr_notifier failed\n"); + goto inetaddr_error; + } + + return 0; + +inetaddr_error: + unregister_inet6addr_notifier(&iwdev->nb_inet6addr_event); +inet6addr_error: + unregister_netevent_notifier(&iwdev->nb_net_event); +netevent_error: + unregister_netdevice_notifier(&iwdev->nb_netdevice_event); + return ret; +} +/** + * irdma_add_handler - add a handler to the list + * @hdl: handler to be added to the handler list + */ +void irdma_add_handler(struct irdma_handler *hdl) +{ + unsigned long flags; + + spin_lock_irqsave(&irdma_handler_lock, flags); + list_add(&hdl->list, &irdma_handlers); + spin_unlock_irqrestore(&irdma_handler_lock, flags); +} + +/** + * irdma_del_handler - delete a handler from the list + * @hdl: handler to be deleted from the handler list + */ +void irdma_del_handler(struct irdma_handler *hdl) +{ + unsigned long flags; + + spin_lock_irqsave(&irdma_handler_lock, flags); + list_del(&hdl->list); + spin_unlock_irqrestore(&irdma_handler_lock, flags); +} + +/** + * irdma_add_ipv6_addr - add ipv6 address to the hw arp table + * @iwdev: irdma device + */ +static void irdma_add_ipv6_addr(struct irdma_device *iwdev) +{ + struct net_device *ip_dev; + struct inet6_dev *idev; + struct inet6_ifaddr *ifp, *tmp; + u32 local_ipaddr6[4]; + + rcu_read_lock(); + for_each_netdev_rcu(&init_net, ip_dev) { + if (((rdma_vlan_dev_vlan_id(ip_dev) < 0xFFFF && + rdma_vlan_dev_real_dev(ip_dev) == iwdev->netdev) || + ip_dev == iwdev->netdev) && + (READ_ONCE(ip_dev->flags) & IFF_UP)) { + idev = __in6_dev_get(ip_dev); + if (!idev) { + ibdev_err(&iwdev->ibdev, "ipv6 inet device not found for netdev=%s\n", + netdev_name(ip_dev)); + break; + } + list_for_each_entry_safe(ifp, tmp, &idev->addr_list, + if_list) { + ibdev_dbg(&iwdev->ibdev, + "INIT: netdev = %s, IP=%pI6, vlan_id=%d, MAC=%pM\n", + netdev_name(ip_dev), &ifp->addr, + rdma_vlan_dev_vlan_id(ip_dev), + ip_dev->dev_addr); + irdma_copy_ip_ntohl(local_ipaddr6, + ifp->addr.in6_u.u6_addr32); + irdma_manage_arp_cache(iwdev->rf, + ip_dev->dev_addr, + local_ipaddr6, + IRDMA_ARP_ADD_UPDATE); + } + } + } + rcu_read_unlock(); +} + +/** + * irdma_add_ipv4_addr - add ipv4 address to the hw arp table + * @iwdev: irdma device + */ +static void irdma_add_ipv4_addr(struct irdma_device *iwdev) +{ + struct net_device *dev; + struct in_device *idev; + u32 local_ipaddr4[4] = {}; + + rcu_read_lock(); + for_each_netdev_rcu(&init_net, dev) { + if (((rdma_vlan_dev_vlan_id(dev) < 0xFFFF && + rdma_vlan_dev_real_dev(dev) == iwdev->netdev) || + dev == iwdev->netdev) && (READ_ONCE(dev->flags) & IFF_UP)) { +#ifdef IN_IFADDR + const struct in_ifaddr *ifa; + +#endif + idev = __in_dev_get_rcu(dev); + if (!idev) + continue; + +#ifdef IN_IFADDR + in_dev_for_each_ifa_rcu(ifa, idev) { +#elif defined(FOR_IFA) + for_ifa(idev) { +#endif + ibdev_dbg(&iwdev->ibdev, "CM: netdev = %s, IP=%pI4, vlan_id=%d, MAC=%pM\n", + netdev_name(dev), &ifa->ifa_address, rdma_vlan_dev_vlan_id(dev), + dev->dev_addr); + local_ipaddr4[0] = ntohl(ifa->ifa_address); + irdma_manage_arp_cache(iwdev->rf, dev->dev_addr, + local_ipaddr4, + IRDMA_ARP_ADD_UPDATE); + } +#ifdef FOR_IFA + endfor_ifa(idev); +#endif + } + } + rcu_read_unlock(); +} + +/** + * irdma_add_ip - add ip addresses + * @iwdev: irdma device + * + * Add ipv4/ipv6 addresses to the arp cache + */ +void irdma_add_ip(struct irdma_device *iwdev) +{ + irdma_add_ipv4_addr(iwdev); + irdma_add_ipv6_addr(iwdev); +} + +/** + * irdma_alloc_and_get_cqp_request - get cqp struct + * @cqp: device cqp ptr + * @wait: cqp to be used in wait mode + */ +struct irdma_cqp_request *irdma_alloc_and_get_cqp_request(struct irdma_cqp *cqp, + bool wait) +{ + struct irdma_cqp_request *cqp_request = NULL; + unsigned long flags; + + spin_lock_irqsave(&cqp->req_lock, flags); + if (!list_empty(&cqp->cqp_avail_reqs)) { + cqp_request = list_entry(cqp->cqp_avail_reqs.next, + struct irdma_cqp_request, list); + list_del_init(&cqp_request->list); + } + spin_unlock_irqrestore(&cqp->req_lock, flags); + if (!cqp_request) { + cqp_request = kzalloc(sizeof(*cqp_request), GFP_ATOMIC); + if (cqp_request) { + cqp_request->dynamic = true; + if (wait) + init_waitqueue_head(&cqp_request->waitq); + } + } + if (!cqp_request) { + ibdev_dbg(to_ibdev(cqp->sc_cqp.dev), "ERR: CQP Request Fail: No Memory"); + return NULL; + } + + cqp_request->waiting = wait; + refcount_set(&cqp_request->refcnt, 1); + memset(&cqp_request->compl_info, 0, sizeof(cqp_request->compl_info)); + + return cqp_request; +} + +/** + * irdma_get_cqp_request - increase refcount for cqp_request + * @cqp_request: pointer to cqp_request instance + */ +static inline void irdma_get_cqp_request(struct irdma_cqp_request *cqp_request) +{ + refcount_inc(&cqp_request->refcnt); +} + +/** + * irdma_free_cqp_request - free cqp request + * @cqp: cqp ptr + * @cqp_request: to be put back in cqp list + */ +void irdma_free_cqp_request(struct irdma_cqp *cqp, + struct irdma_cqp_request *cqp_request) +{ + unsigned long flags; + + if (cqp_request->dynamic) { + kfree(cqp_request); + } else { + WRITE_ONCE(cqp_request->request_done, false); + cqp_request->callback_fcn = NULL; + cqp_request->waiting = false; + cqp_request->pending = false; + + spin_lock_irqsave(&cqp->req_lock, flags); + list_add_tail(&cqp_request->list, &cqp->cqp_avail_reqs); + spin_unlock_irqrestore(&cqp->req_lock, flags); + } + wake_up(&cqp->remove_wq); +} + +/** + * irdma_put_cqp_request - dec ref count and free if 0 + * @cqp: cqp ptr + * @cqp_request: to be put back in cqp list + */ +void irdma_put_cqp_request(struct irdma_cqp *cqp, + struct irdma_cqp_request *cqp_request) +{ + if (refcount_dec_and_test(&cqp_request->refcnt)) + irdma_free_cqp_request(cqp, cqp_request); +} + +/** + * irdma_free_pending_cqp_request -free pending cqp request objs + * @cqp: cqp ptr + * @cqp_request: to be put back in cqp list + */ +static void +irdma_free_pending_cqp_request(struct irdma_cqp *cqp, + struct irdma_cqp_request *cqp_request) +{ + cqp_request->compl_info.error = true; + WRITE_ONCE(cqp_request->request_done, true); + + if (cqp_request->waiting) + wake_up(&cqp_request->waitq); + wait_event_timeout(cqp->remove_wq, + refcount_read(&cqp_request->refcnt) == 1, 1000); + irdma_put_cqp_request(cqp, cqp_request); +} + +/** + * irdma_cleanup_deferred_cqp_ops - clean-up cqp with no completions + * @dev: sc_dev + * @cqp: cqp + */ +static void irdma_cleanup_deferred_cqp_ops(struct irdma_sc_dev *dev, + struct irdma_cqp *cqp) +{ + u64 scratch; + + /* process all CQP requests with deferred/pending completions */ + while ((scratch = irdma_sc_cqp_cleanup_handler(dev))) + irdma_free_pending_cqp_request(cqp, (struct irdma_cqp_request *) + (uintptr_t)scratch); +} + +/** + * irdma_cleanup_pending_cqp_op - clean-up cqp with no + * completions + * @rf: RDMA PCI function + */ +void irdma_cleanup_pending_cqp_op(struct irdma_pci_f *rf) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + struct irdma_cqp *cqp = &rf->cqp; + struct irdma_cqp_request *cqp_request = NULL; + struct cqp_cmds_info *pcmdinfo = NULL; + u32 i, pending_work, wqe_idx; + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) + irdma_cleanup_deferred_cqp_ops(dev, cqp); + pending_work = IRDMA_RING_USED_QUANTA(cqp->sc_cqp.sq_ring); + wqe_idx = IRDMA_RING_CURRENT_TAIL(cqp->sc_cqp.sq_ring); + for (i = 0; i < pending_work; i++) { + cqp_request = (struct irdma_cqp_request *)(uintptr_t) + cqp->scratch_array[wqe_idx]; + if (cqp_request) + irdma_free_pending_cqp_request(cqp, cqp_request); + wqe_idx = (wqe_idx + 1) % IRDMA_RING_SIZE(cqp->sc_cqp.sq_ring); + } + + while (!list_empty(&dev->cqp_cmd_head)) { + pcmdinfo = irdma_remove_cqp_head(dev); + cqp_request = + container_of(pcmdinfo, struct irdma_cqp_request, info); + if (cqp_request) + irdma_free_pending_cqp_request(cqp, cqp_request); + } +} + +static int irdma_get_timeout_threshold(struct irdma_sc_dev *dev) +{ + u16 time_s = dev->vc_caps.cqp_timeout_s; + + if (!time_s) + return CQP_TIMEOUT_THRESHOLD; + + return time_s * 1000 / dev->hw_attrs.max_cqp_compl_wait_time_ms; +} + +static int irdma_get_def_timeout_threshold(struct irdma_sc_dev *dev) +{ + u16 time_s = dev->vc_caps.cqp_def_timeout_s; + + if (!time_s) + return CQP_DEF_CMPL_TIMEOUT_THRESHOLD; + + return time_s * 1000 / dev->hw_attrs.max_cqp_compl_wait_time_ms; +} + +/** + * irdma_wait_event - wait for completion + * @rf: RDMA PCI function + * @cqp_request: cqp request to wait + */ +static int irdma_wait_event(struct irdma_pci_f *rf, + struct irdma_cqp_request *cqp_request) +{ + struct irdma_cqp_timeout cqp_timeout = {}; + int timeout_threshold = irdma_get_timeout_threshold(&rf->sc_dev); + bool cqp_error = false; + int err_code = 0; + + cqp_timeout.compl_cqp_cmds = atomic64_read(&rf->sc_dev.cqp->completed_ops); + do { + int wait_time_ms = rf->sc_dev.hw_attrs.max_cqp_compl_wait_time_ms; + + irdma_cqp_ce_handler(rf, &rf->ccq.sc_cq); + if (wait_event_timeout(cqp_request->waitq, + READ_ONCE(cqp_request->request_done), + msecs_to_jiffies(wait_time_ms))) + break; + + if (cqp_request->pending) + /* There was a deferred or pending completion + * received for this CQP request, so we need + * to wait longer than usual. + */ + timeout_threshold = irdma_get_def_timeout_threshold(&rf->sc_dev); + + irdma_check_cqp_progress(&cqp_timeout, &rf->sc_dev); + + if (cqp_timeout.count < timeout_threshold) + continue; + + if (!rf->reset) { + rf->reset = true; + rf->gen_ops.request_reset(rf); + } + return -ETIMEDOUT; + } while (1); + + cqp_error = cqp_request->compl_info.error; + if (cqp_error) { + err_code = -EIO; + if (cqp_request->compl_info.maj_err_code == 0xFFFF) { + if (cqp_request->compl_info.min_err_code == 0x8002) { + err_code = -EBUSY; + } else if (cqp_request->compl_info.min_err_code == 0x8029) { + if (!rf->reset) { + rf->reset = true; + rf->gen_ops.request_reset(rf); + } + } + } + } + + return err_code; +} + +static const char *const irdma_cqp_cmd_names[IRDMA_MAX_CQP_OPS] = { + [IRDMA_OP_CEQ_DESTROY] = "Destroy CEQ Cmd", + [IRDMA_OP_AEQ_DESTROY] = "Destroy AEQ Cmd", + [IRDMA_OP_DELETE_ARP_CACHE_ENTRY] = "Delete ARP Cache Cmd", + [IRDMA_OP_MANAGE_APBVT_ENTRY] = "Manage APBV Table Entry Cmd", + [IRDMA_OP_CEQ_CREATE] = "CEQ Create Cmd", + [IRDMA_OP_AEQ_CREATE] = "AEQ Destroy Cmd", + [IRDMA_OP_MANAGE_QHASH_TABLE_ENTRY] = "Manage Quad Hash Table Entry Cmd", + [IRDMA_OP_QP_MODIFY] = "Modify QP Cmd", + [IRDMA_OP_QP_UPLOAD_CONTEXT] = "Upload Context Cmd", + [IRDMA_OP_CQ_CREATE] = "Create CQ Cmd", + [IRDMA_OP_CQ_DESTROY] = "Destroy CQ Cmd", + [IRDMA_OP_QP_CREATE] = "Create QP Cmd", + [IRDMA_OP_QP_DESTROY] = "Destroy QP Cmd", + [IRDMA_OP_ALLOC_STAG] = "Allocate STag Cmd", + [IRDMA_OP_MR_REG_NON_SHARED] = "Register Non-Shared MR Cmd", + [IRDMA_OP_DEALLOC_STAG] = "Deallocate STag Cmd", + [IRDMA_OP_MW_ALLOC] = "Allocate Memory Window Cmd", + [IRDMA_OP_QP_FLUSH_WQES] = "Flush QP Cmd", + [IRDMA_OP_ADD_ARP_CACHE_ENTRY] = "Add ARP Cache Cmd", + [IRDMA_OP_MANAGE_PUSH_PAGE] = "Manage Push Page Cmd", + [IRDMA_OP_UPDATE_PE_SDS] = "Update PE SDs Cmd", + [IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE] = "Manage HMC PM Function Table Cmd", + [IRDMA_OP_SUSPEND] = "Suspend QP Cmd", + [IRDMA_OP_RESUME] = "Resume QP Cmd", + [IRDMA_OP_MANAGE_PBLE_BP] = + "Manage Function PBLE Backing Pages Cmd", + [IRDMA_OP_QUERY_FPM_VAL] = "Query FPM Values Cmd", + [IRDMA_OP_COMMIT_FPM_VAL] = "Commit FPM Values Cmd", + [IRDMA_OP_AH_CREATE] = "Create Address Handle Cmd", + [IRDMA_OP_AH_MODIFY] = "Modify Address Handle Cmd", + [IRDMA_OP_AH_DESTROY] = "Destroy Address Handle Cmd", + [IRDMA_OP_MC_CREATE] = "Create Multicast Group Cmd", + [IRDMA_OP_MC_DESTROY] = "Destroy Multicast Group Cmd", + [IRDMA_OP_MC_MODIFY] = "Modify Multicast Group Cmd", + [IRDMA_OP_STATS_ALLOCATE] = "Add Statistics Instance Cmd", + [IRDMA_OP_STATS_FREE] = "Free Statistics Instance Cmd", + [IRDMA_OP_STATS_GATHER] = "Gather Statistics Cmd", + [IRDMA_OP_WS_ADD_NODE] = "Add Work Scheduler Node Cmd", + [IRDMA_OP_WS_MODIFY_NODE] = "Modify Work Scheduler Node Cmd", + [IRDMA_OP_WS_DELETE_NODE] = "Delete Work Scheduler Node Cmd", + [IRDMA_OP_WS_FAILOVER_START] = "Failover Start Cmd", + [IRDMA_OP_WS_FAILOVER_COMPLETE] = "Failover Complete Cmd", + [IRDMA_OP_SET_UP_MAP] = "Set UP-UP Mapping Cmd", + [IRDMA_OP_GEN_AE] = "Generate AE Cmd", + [IRDMA_OP_QUERY_RDMA_FEATURES] = "RDMA Get Features Cmd", + [IRDMA_OP_ALLOC_LOCAL_MAC_ENTRY] = "Allocate Local MAC Entry Cmd", + [IRDMA_OP_ADD_LOCAL_MAC_ENTRY] = "Add Local MAC Entry Cmd", + [IRDMA_OP_DELETE_LOCAL_MAC_ENTRY] = "Delete Local MAC Entry Cmd", + [IRDMA_OP_CQ_MODIFY] = "CQ Modify Cmd", + [IRDMA_OP_SRQ_CREATE] = "Create SRQ Cmd", + [IRDMA_OP_SRQ_MODIFY] = "Modify SRQ Cmd", + [IRDMA_OP_SRQ_DESTROY] = "Destroy SRQ Cmd", +}; + +static const struct irdma_cqp_err_info irdma_noncrit_err_list[] = { + {0xffff, 0x8002, "Invalid State"}, + {0xffff, 0x8006, "Flush No Wqe Pending"}, + {0xffff, 0x8007, "Modify QP Bad Close"}, + {0xffff, 0x8009, "LLP Closed"}, + {0xffff, 0x800a, "Reset Not Sent"}, + {0xffff, 0x0200, "Failover Pending"}, +}; + +/** + * irdma_cqp_crit_err - check if CQP error is critical + * @dev: pointer to dev structure + * @cqp_cmd: code for last CQP operation + * @maj_err_code: major error code + * @min_err_code: minot error code + */ +bool irdma_cqp_crit_err(struct irdma_sc_dev *dev, u8 cqp_cmd, + u16 maj_err_code, u16 min_err_code) +{ + int i; + + for (i = 0; i < ARRAY_SIZE(irdma_noncrit_err_list); ++i) { + if (maj_err_code == irdma_noncrit_err_list[i].maj && + min_err_code == irdma_noncrit_err_list[i].min) { + ibdev_dbg(to_ibdev(dev), + "CQP: [%s Error][%s] maj=0x%x min=0x%x\n", + irdma_noncrit_err_list[i].desc, + irdma_cqp_cmd_names[cqp_cmd], maj_err_code, + min_err_code); + return false; + } + } + return true; +} + +/** + * irdma_handle_cqp_op - process cqp command + * @rf: RDMA PCI function + * @cqp_request: cqp request to process + */ +int irdma_handle_cqp_op(struct irdma_pci_f *rf, + struct irdma_cqp_request *cqp_request) +{ + struct irdma_sc_dev *dev = &rf->sc_dev; + struct cqp_cmds_info *info = &cqp_request->info; + int status; + bool put_cqp_request = true; + + if (rf->reset) + return 0; + + irdma_get_cqp_request(cqp_request); + status = irdma_process_cqp_cmd(dev, info); + if (status) + goto err; + + if (cqp_request->waiting) { + put_cqp_request = false; + status = irdma_wait_event(rf, cqp_request); + if (status) + goto err; + } + + return 0; + +err: + if (irdma_cqp_crit_err(dev, info->cqp_cmd, + cqp_request->compl_info.maj_err_code, + cqp_request->compl_info.min_err_code)) + ibdev_err(&rf->iwdev->ibdev, + "[%s Error][op_code=%d] status=%d waiting=%d completion_err=%d maj=0x%x min=0x%x\n", + irdma_cqp_cmd_names[info->cqp_cmd], info->cqp_cmd, status, + cqp_request->waiting, cqp_request->compl_info.error, + cqp_request->compl_info.maj_err_code, + cqp_request->compl_info.min_err_code); + + if (put_cqp_request) + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +void irdma_qp_add_ref(struct ib_qp *ibqp) +{ + struct irdma_qp *iwqp = to_iwqp(ibqp); + + refcount_inc(&iwqp->refcnt); +} + +void irdma_qp_rem_ref(struct ib_qp *ibqp) +{ + struct irdma_qp *iwqp = to_iwqp(ibqp); + struct irdma_device *iwdev = iwqp->iwdev; + unsigned long flags; + + spin_lock_irqsave(&iwdev->rf->qptable_lock, flags); + if (!refcount_dec_and_test(&iwqp->refcnt)) { + spin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags); + return; + } + + iwdev->rf->qp_table[iwqp->ibqp.qp_num] = NULL; + spin_unlock_irqrestore(&iwdev->rf->qptable_lock, flags); + complete(&iwqp->free_qp); +} + +void irdma_cq_add_ref(struct ib_cq *ibcq) +{ + struct irdma_cq *iwcq = to_iwcq(ibcq); + + refcount_inc(&iwcq->refcnt); +} + +void irdma_cq_rem_ref(struct ib_cq *ibcq) +{ + struct irdma_cq *iwcq = to_iwcq(ibcq); + struct irdma_pci_f *rf = container_of(iwcq->sc_cq.dev, struct irdma_pci_f, sc_dev); + unsigned long flags; + + spin_lock_irqsave(&rf->cqtable_lock, flags); + if (!refcount_dec_and_test(&iwcq->refcnt)) { + spin_unlock_irqrestore(&rf->cqtable_lock, flags); + return; + } + + rf->cq_table[iwcq->cq_num] = NULL; + spin_unlock_irqrestore(&rf->cqtable_lock, flags); + complete(&iwcq->free_cq); +} + +void irdma_srq_add_ref(struct ib_srq *ibsrq) +{ + struct irdma_srq *iwsrq = to_iwsrq(ibsrq); + + refcount_inc(&iwsrq->refcnt); +} + +void irdma_srq_rem_ref(struct ib_srq *ibsrq) +{ + struct irdma_srq *iwsrq = to_iwsrq(ibsrq); + struct irdma_pci_f *rf = dev_to_rf(iwsrq->sc_srq.dev); + unsigned long flags; + + spin_lock_irqsave(&rf->srqtable_lock, flags); + if (!refcount_dec_and_test(&iwsrq->refcnt)) { + spin_unlock_irqrestore(&rf->srqtable_lock, flags); + return; + } + + rf->srq_table[iwsrq->srq_num] = NULL; + spin_unlock_irqrestore(&rf->srqtable_lock, flags); + complete(&iwsrq->free_srq); +} + +#ifndef ibdev_dbg +struct ib_device *irdma_get_ibdev(struct irdma_sc_dev *dev) +{ + return &(container_of(dev, struct irdma_pci_f, sc_dev))->iwdev->ibdev; +} +#else +struct ib_device *to_ibdev(struct irdma_sc_dev *dev) +{ + return &(container_of(dev, struct irdma_pci_f, sc_dev))->iwdev->ibdev; +} +#endif/* ibdev_dbg */ + +/** + * irdma_get_qp - get qp address + * @device: iwarp device + * @qpn: qp number + */ +struct ib_qp *irdma_get_qp(struct ib_device *device, int qpn) +{ + struct irdma_device *iwdev = to_iwdev(device); + + if (qpn < IW_FIRST_QPN || qpn >= iwdev->rf->max_qp) + return NULL; + + return &iwdev->rf->qp_table[qpn]->ibqp; +} + +/** + * irdma_remove_cqp_head - return head entry and remove + * @dev: device + */ +void *irdma_remove_cqp_head(struct irdma_sc_dev *dev) +{ + struct list_head *entry; + struct list_head *list = &dev->cqp_cmd_head; + + if (list_empty(list)) + return NULL; + + entry = list->next; + list_del(entry); + + return entry; +} + +/** + * irdma_cqp_sds_cmd - create cqp command for sd + * @dev: hardware control device structure + * @sdinfo: information for sd cqp + * + */ +int irdma_cqp_sds_cmd(struct irdma_sc_dev *dev, + struct irdma_update_sds_info *sdinfo) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_pci_f *rf = dev_to_rf(dev); + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + memcpy(&cqp_info->in.u.update_pe_sds.info, sdinfo, + sizeof(cqp_info->in.u.update_pe_sds.info)); + cqp_info->cqp_cmd = IRDMA_OP_UPDATE_PE_SDS; + cqp_info->post_sq = 1; + cqp_info->in.u.update_pe_sds.dev = dev; + cqp_info->in.u.update_pe_sds.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_qp_suspend_resume - cqp command for suspend/resume + * @qp: hardware control qp + * @op: suspend or resume + */ +int irdma_cqp_qp_suspend_resume(struct irdma_sc_qp *qp, u8 op) +{ + struct irdma_sc_dev *dev = qp->dev; + struct irdma_cqp_request *cqp_request; + struct irdma_sc_cqp *cqp = dev->cqp; + struct cqp_cmds_info *cqp_info; + struct irdma_pci_f *rf = dev_to_rf(dev); + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = op; + cqp_info->in.u.suspend_resume.cqp = cqp; + cqp_info->in.u.suspend_resume.qp = qp; + cqp_info->in.u.suspend_resume.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_term_modify_qp - modify qp for term message + * @qp: hardware control qp + * @next_state: qp's next state + * @term: terminate code + * @term_len: length + */ +void irdma_term_modify_qp(struct irdma_sc_qp *qp, u8 next_state, u8 term, + u8 term_len) +{ + struct irdma_qp *iwqp; + + iwqp = qp->qp_uk.back_qp; + irdma_next_iw_state(iwqp, next_state, 0, term, term_len); +}; + +/** + * irdma_terminate_done - after terminate is completed + * @qp: hardware control qp + * @timeout_occurred: indicates if terminate timer expired + */ +void irdma_terminate_done(struct irdma_sc_qp *qp, int timeout_occurred) +{ + struct irdma_qp *iwqp; + u8 hte = 0; + bool first_time; + unsigned long flags; + + iwqp = qp->qp_uk.back_qp; + spin_lock_irqsave(&iwqp->lock, flags); + if (iwqp->hte_added) { + iwqp->hte_added = 0; + hte = 1; + } + first_time = !(qp->term_flags & IRDMA_TERM_DONE); + qp->term_flags |= IRDMA_TERM_DONE; + spin_unlock_irqrestore(&iwqp->lock, flags); + if (first_time) { + if (!timeout_occurred) + irdma_terminate_del_timer(qp); + + irdma_next_iw_state(iwqp, IRDMA_QP_STATE_ERROR, hte, 0, 0); + irdma_cm_disconn(iwqp); + } +} + +static void irdma_terminate_timeout(struct timer_list *t) +{ + struct irdma_qp *iwqp = from_timer(iwqp, t, terminate_timer); + struct irdma_sc_qp *qp = &iwqp->sc_qp; + + irdma_terminate_done(qp, 1); + irdma_qp_rem_ref(&iwqp->ibqp); +} + +/** + * irdma_terminate_start_timer - start terminate timeout + * @qp: hardware control qp + */ +void irdma_terminate_start_timer(struct irdma_sc_qp *qp) +{ + struct irdma_qp *iwqp; + + iwqp = qp->qp_uk.back_qp; + irdma_qp_add_ref(&iwqp->ibqp); + timer_setup(&iwqp->terminate_timer, irdma_terminate_timeout, 0); + iwqp->terminate_timer.expires = jiffies + HZ; + + add_timer(&iwqp->terminate_timer); +} + +/** + * irdma_terminate_del_timer - delete terminate timeout + * @qp: hardware control qp + */ +void irdma_terminate_del_timer(struct irdma_sc_qp *qp) +{ + struct irdma_qp *iwqp; + int ret; + + iwqp = qp->qp_uk.back_qp; + ret = del_timer(&iwqp->terminate_timer); + if (ret) + irdma_qp_rem_ref(&iwqp->ibqp); +} + +/** + * irdma_cqp_manage_hmc_fcn_cmd - issue cqp command to manage hmc + * @dev: hardware control device structure + * @hmcfcninfo: info for hmc + * @pmf_idx: pmf or hmc function index for the vc_dev + */ +int irdma_cqp_manage_hmc_fcn_cmd(struct irdma_sc_dev *dev, + struct irdma_hmc_fcn_info *hmcfcninfo, + u16 *pmf_idx) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_pci_f *rf = dev_to_rf(dev); + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + memcpy(&cqp_info->in.u.manage_hmc_pm.info, hmcfcninfo, + sizeof(cqp_info->in.u.manage_hmc_pm.info)); + cqp_info->in.u.manage_hmc_pm.dev = dev; + cqp_info->cqp_cmd = IRDMA_OP_MANAGE_HMC_PM_FUNC_TABLE; + cqp_info->post_sq = 1; + cqp_info->in.u.manage_hmc_pm.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + *pmf_idx = cqp_request->compl_info.op_ret_val; + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_query_fpm_val_cmd - send cqp command for fpm + * @dev: function device struct + * @val_mem: buffer for fpm + * @hmc_fn_id: function id for fpm + */ +int irdma_cqp_query_fpm_val_cmd(struct irdma_sc_dev *dev, + struct irdma_dma_mem *val_mem, u16 hmc_fn_id) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_pci_f *rf = dev_to_rf(dev); + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + cqp_request->param = NULL; + cqp_info->in.u.query_fpm_val.cqp = dev->cqp; + cqp_info->in.u.query_fpm_val.fpm_val_pa = val_mem->pa; + cqp_info->in.u.query_fpm_val.fpm_val_va = val_mem->va; + cqp_info->in.u.query_fpm_val.hmc_fn_id = hmc_fn_id; + cqp_info->cqp_cmd = IRDMA_OP_QUERY_FPM_VAL; + cqp_info->post_sq = 1; + cqp_info->in.u.query_fpm_val.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_commit_fpm_val_cmd - commit fpm values in hw + * @dev: hardware control device structure + * @val_mem: buffer with fpm values + * @hmc_fn_id: function id for fpm + */ +int irdma_cqp_commit_fpm_val_cmd(struct irdma_sc_dev *dev, + struct irdma_dma_mem *val_mem, u16 hmc_fn_id) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_pci_f *rf = dev_to_rf(dev); + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + cqp_request->param = NULL; + cqp_info->in.u.commit_fpm_val.cqp = dev->cqp; + cqp_info->in.u.commit_fpm_val.fpm_val_pa = val_mem->pa; + cqp_info->in.u.commit_fpm_val.fpm_val_va = val_mem->va; + cqp_info->in.u.commit_fpm_val.hmc_fn_id = hmc_fn_id; + cqp_info->cqp_cmd = IRDMA_OP_COMMIT_FPM_VAL; + cqp_info->post_sq = 1; + cqp_info->in.u.commit_fpm_val.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_cq_create_cmd - create a cq for the cqp + * @dev: device pointer + * @cq: pointer to created cq + */ +int irdma_cqp_cq_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq) +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = IRDMA_OP_CQ_CREATE; + cqp_info->post_sq = 1; + cqp_info->in.u.cq_create.cq = cq; + cqp_info->in.u.cq_create.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(iwcqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_qp_create_cmd - create a qp for the cqp + * @dev: device pointer + * @qp: pointer to created qp + */ +int irdma_cqp_qp_create_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp) +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_create_qp_info *qp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + qp_info = &cqp_request->info.in.u.qp_create.info; + memset(qp_info, 0, sizeof(*qp_info)); + qp_info->cq_num_valid = true; + qp_info->next_iwarp_state = IRDMA_QP_STATE_RTS; + cqp_info->cqp_cmd = IRDMA_OP_QP_CREATE; + cqp_info->post_sq = 1; + cqp_info->in.u.qp_create.qp = qp; + cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(iwcqp, cqp_request); + + return status; +} + +/** + * irdma_dealloc_push_page - free a push page for qp + * @rf: RDMA PCI function + * @iwqp: QP pointer + */ +void irdma_dealloc_push_page(struct irdma_pci_f *rf, + struct irdma_qp *iwqp) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + struct irdma_sc_qp *qp = &iwqp->sc_qp; + struct irdma_pd *pd = iwqp->iwpd; + u32 push_pos; + bool is_empty; + + if (qp->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) + return; + + mutex_lock(&pd->push_alloc_mutex); + + push_pos = qp->push_offset / IRDMA_PUSH_WIN_SIZE; + __clear_bit(push_pos, pd->push_offset_bmap); + is_empty = bitmap_empty(pd->push_offset_bmap, IRDMA_QPS_PER_PUSH_PAGE); + if (!is_empty) { + qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + goto exit; + } + + if (!rf->sc_dev.privileged) { + u32 pg_idx = qp->push_idx; + + status = irdma_vchnl_req_manage_push_pg(&rf->sc_dev, false, + qp->qs_handle, &pg_idx); + if (!status) { + qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + pd->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + atomic64_sub(2, &rf->push_cnt); + } else { + __set_bit(push_pos, pd->push_offset_bmap); + } + goto exit; + } + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, false); + if (!cqp_request) { + __set_bit(push_pos, pd->push_offset_bmap); + goto exit; + } + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE; + cqp_info->post_sq = 1; + cqp_info->in.u.manage_push_page.info.push_idx = qp->push_idx; + cqp_info->in.u.manage_push_page.info.qs_handle = qp->qs_handle; + cqp_info->in.u.manage_push_page.info.free_page = 1; + cqp_info->in.u.manage_push_page.info.push_page_type = 0; + cqp_info->in.u.manage_push_page.cqp = &rf->cqp.sc_cqp; + cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(rf, cqp_request); + if (!status) { + qp->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + atomic64_sub(2, &rf->push_cnt); + pd->push_idx = IRDMA_INVALID_PUSH_PAGE_INDEX; + } else { + __set_bit(push_pos, pd->push_offset_bmap); + } + irdma_put_cqp_request(&rf->cqp, cqp_request); +exit: + mutex_unlock(&pd->push_alloc_mutex); +} + +/** + * irdma_srq_wq_destroy - send srq destroy cqp + * @rf: RDMA PCI function + * @srq: hardware control srq + */ +void irdma_srq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_srq *srq) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return; + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = IRDMA_OP_SRQ_DESTROY; + cqp_info->post_sq = 1; + cqp_info->in.u.srq_destroy.srq = srq; + cqp_info->in.u.srq_destroy.scratch = (uintptr_t)cqp_request; + + irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); +} + +/** + * irdma_cq_wq_destroy - send cq destroy cqp + * @rf: RDMA PCI function + * @cq: hardware control cq + */ +void irdma_cq_wq_destroy(struct irdma_pci_f *rf, struct irdma_sc_cq *cq) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return; + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = IRDMA_OP_CQ_DESTROY; + cqp_info->post_sq = 1; + cqp_info->in.u.cq_destroy.cq = cq; + cqp_info->in.u.cq_destroy.scratch = (uintptr_t)cqp_request; + + irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); +} + +/** + * irdma_hw_modify_qp_callback - handle state for modifyQPs that don't wait + * @cqp_request: modify QP completion + */ +static void irdma_hw_modify_qp_callback(struct irdma_cqp_request *cqp_request) +{ + struct cqp_cmds_info *cqp_info; + struct irdma_qp *iwqp; + + cqp_info = &cqp_request->info; + iwqp = cqp_info->in.u.qp_modify.qp->qp_uk.back_qp; + atomic_dec(&iwqp->hw_mod_qp_pend); + wake_up(&iwqp->mod_qp_waitq); +} + +/** + * irdma_hw_modify_qp - setup cqp for modify qp + * @iwdev: RDMA device + * @iwqp: qp ptr (user or kernel) + * @info: info for modify qp + * @wait: flag to wait or not for modify qp completion + */ +int irdma_hw_modify_qp(struct irdma_device *iwdev, struct irdma_qp *iwqp, + struct irdma_modify_qp_info *info, bool wait) +{ + int status; + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_modify_qp_info *m_info; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); + if (!cqp_request) + return -ENOMEM; + + if (!wait) { + cqp_request->callback_fcn = irdma_hw_modify_qp_callback; + atomic_inc(&iwqp->hw_mod_qp_pend); + } + cqp_info = &cqp_request->info; + m_info = &cqp_info->in.u.qp_modify.info; + memcpy(m_info, info, sizeof(*m_info)); + cqp_info->cqp_cmd = IRDMA_OP_QP_MODIFY; + cqp_info->post_sq = 1; + cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp; + cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + if (status) { + if (rdma_protocol_roce(&iwdev->ibdev, 1)) + return status; + + switch (m_info->next_iwarp_state) { + struct irdma_gen_ae_info ae_info; + + case IRDMA_QP_STATE_RTS: + case IRDMA_QP_STATE_IDLE: + case IRDMA_QP_STATE_TERMINATE: + case IRDMA_QP_STATE_CLOSING: + if (info->curr_iwarp_state == IRDMA_QP_STATE_IDLE) + irdma_send_reset(iwqp->cm_node); + else + iwqp->sc_qp.term_flags = IRDMA_TERM_DONE; + if (!wait) { + ae_info.ae_code = IRDMA_AE_BAD_CLOSE; + ae_info.ae_src = 0; + irdma_gen_ae(rf, &iwqp->sc_qp, &ae_info, false); + } else { + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, + wait); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + m_info = &cqp_info->in.u.qp_modify.info; + memcpy(m_info, info, sizeof(*m_info)); + cqp_info->cqp_cmd = IRDMA_OP_QP_MODIFY; + cqp_info->post_sq = 1; + cqp_info->in.u.qp_modify.qp = &iwqp->sc_qp; + cqp_info->in.u.qp_modify.scratch = (uintptr_t)cqp_request; + m_info->next_iwarp_state = IRDMA_QP_STATE_ERROR; + m_info->reset_tcp_conn = true; + irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + } + break; + case IRDMA_QP_STATE_ERROR: + default: + break; + } + } + + return status; +} + +/** + * irdma_cqp_cq_destroy_cmd - destroy the cqp cq + * @dev: device pointer + * @cq: pointer to cq + */ +void irdma_cqp_cq_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_cq *cq) +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + + irdma_cq_wq_destroy(rf, cq); +} + +/** + * irdma_cqp_qp_destroy_cmd - destroy the cqp + * @dev: device pointer + * @qp: pointer to qp + */ +int irdma_cqp_qp_destroy_cmd(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp) +{ +#define IRDMA_CQP_MIN_ERR_FAILOVER_PENDING 0x200 + struct irdma_pci_f *rf = dev_to_rf(dev); + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int retry_cnt = 3; + int status; + +retry: + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + memset(cqp_info, 0, sizeof(*cqp_info)); + cqp_info->cqp_cmd = IRDMA_OP_QP_DESTROY; + cqp_info->post_sq = 1; + cqp_info->in.u.qp_destroy.qp = qp; + cqp_info->in.u.qp_destroy.scratch = (uintptr_t)cqp_request; + cqp_info->in.u.qp_destroy.remove_hash_idx = true; + + status = irdma_handle_cqp_op(rf, cqp_request); + if (status && cqp_request->compl_info.maj_err_code == 0xffff && + cqp_request->compl_info.min_err_code == IRDMA_CQP_MIN_ERR_FAILOVER_PENDING) { + if (retry_cnt--) { + irdma_put_cqp_request(&rf->cqp, cqp_request); + msleep(20); + goto retry; + } + } + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_ieq_mpa_crc_ae - generate AE for crc error + * @dev: hardware control device structure + * @qp: hardware control qp + */ +void irdma_ieq_mpa_crc_ae(struct irdma_sc_dev *dev, struct irdma_sc_qp *qp) +{ + struct irdma_gen_ae_info info = {}; + struct irdma_pci_f *rf = dev_to_rf(dev); + + ibdev_dbg(&rf->iwdev->ibdev, "AEQ: Generate MPA CRC AE\n"); + info.ae_code = IRDMA_AE_LLP_RECEIVED_MPA_CRC_ERROR; + info.ae_src = IRDMA_AE_SOURCE_RQ; + irdma_gen_ae(rf, qp, &info, false); +} + +/** + * irdma_init_hash_desc - initialize hash for crc calculation + * @desc: cryption type + */ +int irdma_init_hash_desc(struct shash_desc **desc) +{ + struct crypto_shash *tfm; + struct shash_desc *tdesc; + + tfm = crypto_alloc_shash("crc32c", 0, 0); + if (IS_ERR(tfm)) + return PTR_ERR(tfm); + + tdesc = kzalloc(sizeof(*tdesc) + crypto_shash_descsize(tfm), + GFP_KERNEL); + if (!tdesc) { + crypto_free_shash(tfm); + return -ENOMEM; + } + + tdesc->tfm = tfm; + *desc = tdesc; + + return 0; +} + +/** + * irdma_free_hash_desc - free hash desc + * @desc: to be freed + */ +void irdma_free_hash_desc(struct shash_desc *desc) +{ + if (desc) { + crypto_free_shash(desc->tfm); + kfree(desc); + } +} + +/** + * irdma_ieq_check_mpacrc - check if mpa crc is OK + * @desc: desc for hash + * @addr: address of buffer for crc + * @len: length of buffer + * @val: value to be compared + */ +int irdma_ieq_check_mpacrc(struct shash_desc *desc, void *addr, u32 len, + u32 val) +{ + u32 crc = 0; + int ret; + + crypto_shash_init(desc); + ret = crypto_shash_update(desc, addr, len); + if (ret) + return ret; + + crypto_shash_final(desc, (u8 *)&crc); + if (crc != val) + return -EINVAL; + + return ret; +} + +/** + * irdma_alloc_query_fpm_buf - allocate buffer for fpm + * @dev: hardware control device structure + * @mem: buffer ptr for fpm to be allocated + * @return: memory allocation status + */ +int irdma_alloc_query_fpm_buf(struct irdma_sc_dev *dev, + struct irdma_dma_mem *mem) +{ + return irdma_obj_aligned_mem(dev_to_rf(dev), mem, + IRDMA_QUERY_FPM_BUF_SIZE, + IRDMA_FPM_QUERY_BUF_ALIGNMENT_M); +} + +/** + * irdma_ieq_get_qp - get qp based on quad in puda buffer + * @dev: hardware control device structure + * @buf: receive puda buffer on exception q + */ +struct irdma_sc_qp *irdma_ieq_get_qp(struct irdma_sc_dev *dev, + struct irdma_puda_buf *buf) +{ + struct irdma_qp *iwqp; + struct irdma_cm_node *cm_node; + struct irdma_device *iwdev = buf->vsi->back_vsi; + u32 loc_addr[4] = {}; + u32 rem_addr[4] = {}; + u16 loc_port, rem_port; + struct ipv6hdr *ip6h; + struct iphdr *iph = (struct iphdr *)buf->iph; + struct tcphdr *tcph = (struct tcphdr *)buf->tcph; + + if (iph->version == 4) { + loc_addr[0] = ntohl(iph->daddr); + rem_addr[0] = ntohl(iph->saddr); + } else { + ip6h = (struct ipv6hdr *)buf->iph; + irdma_copy_ip_ntohl(loc_addr, ip6h->daddr.in6_u.u6_addr32); + irdma_copy_ip_ntohl(rem_addr, ip6h->saddr.in6_u.u6_addr32); + } + loc_port = ntohs(tcph->dest); + rem_port = ntohs(tcph->source); + cm_node = irdma_find_node(&iwdev->cm_core, rem_port, rem_addr, loc_port, + loc_addr, buf->vlan_valid ? buf->vlan_id : 0xFFFF); + if (!cm_node) + return NULL; + + iwqp = cm_node->iwqp; + irdma_rem_ref_cm_node(cm_node); + + return &iwqp->sc_qp; +} + +/** + * irdma_send_ieq_ack - ACKs for duplicate or OOO partials FPDUs + * @qp: qp ptr + */ +void irdma_send_ieq_ack(struct irdma_sc_qp *qp) +{ + struct irdma_cm_node *cm_node = ((struct irdma_qp *)qp->qp_uk.back_qp)->cm_node; + struct irdma_puda_buf *buf = qp->pfpdu.lastrcv_buf; + struct tcphdr *tcph = (struct tcphdr *)buf->tcph; + + cm_node->tcp_cntxt.rcv_nxt = qp->pfpdu.nextseqnum; + cm_node->tcp_cntxt.loc_seq_num = ntohl(tcph->ack_seq); + + irdma_send_ack(cm_node); +} + +/** + * irdma_puda_ieq_get_ah_info - get AH info from IEQ buffer + * @qp: qp pointer + * @ah_info: AH info pointer + */ +void irdma_puda_ieq_get_ah_info(struct irdma_sc_qp *qp, + struct irdma_ah_info *ah_info) +{ + struct irdma_puda_buf *buf = qp->pfpdu.ah_buf; + struct iphdr *iph; + struct ipv6hdr *ip6h; + + memset(ah_info, 0, sizeof(*ah_info)); + ah_info->do_lpbk = true; + ah_info->vlan_tag = buf->vlan_id; + ah_info->insert_vlan_tag = buf->vlan_valid; + ah_info->ipv4_valid = buf->ipv4; + ah_info->vsi = qp->vsi; + + if (buf->smac_valid) + ether_addr_copy(ah_info->mac_addr, buf->smac); + + if (buf->ipv4) { + ah_info->ipv4_valid = true; + iph = (struct iphdr *)buf->iph; + ah_info->hop_ttl = iph->ttl; + ah_info->tc_tos = iph->tos; + ah_info->dest_ip_addr[0] = ntohl(iph->daddr); + ah_info->src_ip_addr[0] = ntohl(iph->saddr); + } else { + ip6h = (struct ipv6hdr *)buf->iph; + ah_info->hop_ttl = ip6h->hop_limit; + ah_info->tc_tos = ip6h->priority; + irdma_copy_ip_ntohl(ah_info->dest_ip_addr, + ip6h->daddr.in6_u.u6_addr32); + irdma_copy_ip_ntohl(ah_info->src_ip_addr, + ip6h->saddr.in6_u.u6_addr32); + } + + ah_info->dst_arpindex = irdma_arp_table(dev_to_rf(qp->dev), + ah_info->dest_ip_addr, + NULL, IRDMA_ARP_RESOLVE); +} + +/** + * irdma_gen1_ieq_update_tcpip_info - update tcpip in the buffer + * @buf: puda to update + * @len: length of buffer + * @seqnum: seq number for tcp + */ +static void irdma_gen1_ieq_update_tcpip_info(struct irdma_puda_buf *buf, + u16 len, u32 seqnum) +{ + struct tcphdr *tcph; + struct iphdr *iph; + u16 iphlen; + u16 pktsize; + u8 *addr = buf->mem.va; + + iphlen = (buf->ipv4) ? 20 : 40; + iph = (struct iphdr *)(addr + buf->maclen); + tcph = (struct tcphdr *)(addr + buf->maclen + iphlen); + pktsize = len + buf->tcphlen + iphlen; + iph->tot_len = htons(pktsize); + tcph->seq = htonl(seqnum); +} + +/** + * irdma_ieq_update_tcpip_info - update tcpip in the buffer + * @buf: puda to update + * @len: length of buffer + * @seqnum: seq number for tcp + */ +void irdma_ieq_update_tcpip_info(struct irdma_puda_buf *buf, u16 len, + u32 seqnum) +{ + struct tcphdr *tcph; + u8 *addr; + + if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + return irdma_gen1_ieq_update_tcpip_info(buf, len, seqnum); + + addr = buf->mem.va; + tcph = (struct tcphdr *)addr; + tcph->seq = htonl(seqnum); +} + +/** + * irdma_gen1_puda_get_tcpip_info - get tcpip info from puda + * buffer + * @info: to get information + * @buf: puda buffer + */ +static int irdma_gen1_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info, + struct irdma_puda_buf *buf) +{ + struct iphdr *iph; + struct ipv6hdr *ip6h; + struct tcphdr *tcph; + u16 iphlen; + u16 pkt_len; + u8 *mem = buf->mem.va; + struct ethhdr *ethh = buf->mem.va; + + if (ethh->h_proto == htons(0x8100)) { + info->vlan_valid = true; + buf->vlan_id = ntohs(((struct vlan_ethhdr *)ethh)->h_vlan_TCI) & + VLAN_VID_MASK; + } + + buf->maclen = (info->vlan_valid) ? 18 : 14; + iphlen = (info->l3proto) ? 40 : 20; + buf->ipv4 = (info->l3proto) ? false : true; + buf->iph = mem + buf->maclen; + iph = (struct iphdr *)buf->iph; + buf->tcph = buf->iph + iphlen; + tcph = (struct tcphdr *)buf->tcph; + + if (buf->ipv4) { + pkt_len = ntohs(iph->tot_len); + } else { + ip6h = (struct ipv6hdr *)buf->iph; + pkt_len = ntohs(ip6h->payload_len) + iphlen; + } + + buf->totallen = pkt_len + buf->maclen; + + if (info->payload_len < buf->totallen) { + ibdev_dbg(to_ibdev(buf->vsi->dev), + "ERR: payload_len = 0x%x totallen expected0x%x\n", + info->payload_len, buf->totallen); + return -EINVAL; + } + + buf->tcphlen = tcph->doff << 2; + buf->datalen = pkt_len - iphlen - buf->tcphlen; + buf->data = buf->datalen ? buf->tcph + buf->tcphlen : NULL; + buf->hdrlen = buf->maclen + iphlen + buf->tcphlen; + buf->seqnum = ntohl(tcph->seq); + + return 0; +} + +/** + * irdma_puda_get_tcpip_info - get tcpip info from puda buffer + * @info: to get information + * @buf: puda buffer + */ +int irdma_puda_get_tcpip_info(struct irdma_puda_cmpl_info *info, + struct irdma_puda_buf *buf) +{ + struct tcphdr *tcph; + u32 pkt_len; + u8 *mem; + + if (buf->vsi->dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_1) + return irdma_gen1_puda_get_tcpip_info(info, buf); + + mem = buf->mem.va; + buf->vlan_valid = info->vlan_valid; + if (info->vlan_valid) + buf->vlan_id = info->vlan; + + buf->ipv4 = info->ipv4; + if (buf->ipv4) + buf->iph = mem + IRDMA_IPV4_PAD; + else + buf->iph = mem; + + buf->tcph = mem + IRDMA_TCP_OFFSET; + tcph = (struct tcphdr *)buf->tcph; + pkt_len = info->payload_len; + buf->totallen = pkt_len; + buf->tcphlen = tcph->doff << 2; + buf->datalen = pkt_len - IRDMA_TCP_OFFSET - buf->tcphlen; + buf->data = buf->datalen ? buf->tcph + buf->tcphlen : NULL; + buf->hdrlen = IRDMA_TCP_OFFSET + buf->tcphlen; + buf->seqnum = ntohl(tcph->seq); + + if (info->smac_valid) { + ether_addr_copy(buf->smac, info->smac); + buf->smac_valid = true; + } + + return 0; +} + +/** + * irdma_hw_stats_timeout - Stats timer-handler which updates all HW stats + * @t: timer_list pointer + */ +static void irdma_hw_stats_timeout(struct timer_list *t) +{ + struct irdma_vsi_pestat *pf_devstat = + from_timer(pf_devstat, t, stats_timer); + struct irdma_sc_vsi *sc_vsi = pf_devstat->vsi; + + if (sc_vsi->dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) + irdma_cqp_gather_stats_cmd(sc_vsi->dev, sc_vsi->pestat, false); + else + irdma_cqp_gather_stats_gen1(sc_vsi->dev, sc_vsi->pestat); + + mod_timer(&pf_devstat->stats_timer, + jiffies + msecs_to_jiffies(STATS_TIMER_DELAY)); +} + +/** + * irdma_hw_stats_start_timer - Start periodic stats timer + * @vsi: vsi structure pointer + */ +void irdma_hw_stats_start_timer(struct irdma_sc_vsi *vsi) +{ + struct irdma_vsi_pestat *devstat = vsi->pestat; + + timer_setup(&devstat->stats_timer, irdma_hw_stats_timeout, 0); + mod_timer(&devstat->stats_timer, + jiffies + msecs_to_jiffies(STATS_TIMER_DELAY)); +} + +/** + * irdma_hw_stats_stop_timer - Delete periodic stats timer + * @vsi: pointer to vsi structure + */ +void irdma_hw_stats_stop_timer(struct irdma_sc_vsi *vsi) +{ + struct irdma_vsi_pestat *devstat = vsi->pestat; + + del_timer_sync(&devstat->stats_timer); +} + +/** + * irdma_cqp_gather_stats_gen1 - Gather stats + * @dev: pointer to device structure + * @pestat: statistics structure + */ +void irdma_cqp_gather_stats_gen1(struct irdma_sc_dev *dev, + struct irdma_vsi_pestat *pestat) +{ + struct irdma_gather_stats *gather_stats = + pestat->gather_info.gather_stats_va; + const struct irdma_hw_stat_map *map = dev->hw_stats_map; + u16 max_stats_idx = dev->hw_attrs.max_stat_idx; + u32 stats_inst_offset_32; + u32 stats_inst_offset_64; + u64 new_val; + u16 i; + + stats_inst_offset_32 = (pestat->gather_info.use_stats_inst) ? + pestat->gather_info.stats_inst_index : + pestat->hw->hmc.hmc_fn_id; + stats_inst_offset_32 *= 4; + stats_inst_offset_64 = stats_inst_offset_32 * 2; + + for (i = 0; i < max_stats_idx; i++) { + if (map[i].bitmask <= IRDMA_MAX_STATS_32) { + new_val = rd32(dev->hw, + dev->hw_stats_regs[i] + stats_inst_offset_32); + } else { + new_val = rd64(dev->hw, + dev->hw_stats_regs[i] + stats_inst_offset_64); + } + gather_stats->val[map[i].byteoff / sizeof(u64)] = new_val; + } + + sc_vsi_update_stats(pestat->vsi); +} + +/** + * irdma_process_cqp_stats - Checking for wrap and update stats + * @cqp_request: cqp_request structure pointer + */ +static void irdma_process_cqp_stats(struct irdma_cqp_request *cqp_request) +{ + struct irdma_vsi_pestat *pestat = cqp_request->param; + + sc_vsi_update_stats(pestat->vsi); +} + +/** + * irdma_cqp_gather_stats_cmd - Gather stats + * @dev: pointer to device structure + * @pestat: pointer to stats info + * @wait: flag to wait or not wait for stats + */ +int irdma_cqp_gather_stats_cmd(struct irdma_sc_dev *dev, + struct irdma_vsi_pestat *pestat, bool wait) + +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + memset(cqp_info, 0, sizeof(*cqp_info)); + cqp_info->cqp_cmd = IRDMA_OP_STATS_GATHER; + cqp_info->post_sq = 1; + cqp_info->in.u.stats_gather.info = pestat->gather_info; + cqp_info->in.u.stats_gather.scratch = (uintptr_t)cqp_request; + cqp_info->in.u.stats_gather.cqp = &rf->cqp.sc_cqp; + cqp_request->param = pestat; + if (!wait) + cqp_request->callback_fcn = irdma_process_cqp_stats; + status = irdma_handle_cqp_op(rf, cqp_request); + if (wait) + sc_vsi_update_stats(pestat->vsi); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_stats_inst_cmd - Allocate/free stats instance + * @vsi: pointer to vsi structure + * @cmd: command to allocate or free + * @stats_info: pointer to allocate stats info + */ +int irdma_cqp_stats_inst_cmd(struct irdma_sc_vsi *vsi, u8 cmd, + struct irdma_stats_inst_info *stats_info) +{ + struct irdma_pci_f *rf = dev_to_rf(vsi->dev); + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + bool wait = false; + + if (cmd == IRDMA_OP_STATS_ALLOCATE) + wait = true; + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, wait); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + memset(cqp_info, 0, sizeof(*cqp_info)); + cqp_info->cqp_cmd = cmd; + cqp_info->post_sq = 1; + cqp_info->in.u.stats_manage.info = *stats_info; + cqp_info->in.u.stats_manage.scratch = (uintptr_t)cqp_request; + cqp_info->in.u.stats_manage.cqp = &rf->cqp.sc_cqp; + status = irdma_handle_cqp_op(rf, cqp_request); + if (wait) + stats_info->stats_idx = cqp_request->compl_info.op_ret_val; + irdma_put_cqp_request(iwcqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_ceq_cmd - Create/Destroy CEQ's after CEQ 0 + * @dev: pointer to device info + * @sc_ceq: pointer to ceq structure + * @op: Create or Destroy + */ +int irdma_cqp_ceq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_ceq *sc_ceq, + u8 op) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_pci_f *rf = dev_to_rf(dev); + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + cqp_info->post_sq = 1; + cqp_info->cqp_cmd = op; + cqp_info->in.u.ceq_create.ceq = sc_ceq; + cqp_info->in.u.ceq_create.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_aeq_cmd - Create/Destroy AEQ + * @dev: pointer to device info + * @sc_aeq: pointer to aeq structure + * @op: Create or Destroy + */ +int irdma_cqp_aeq_cmd(struct irdma_sc_dev *dev, struct irdma_sc_aeq *sc_aeq, + u8 op) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_pci_f *rf = dev_to_rf(dev); + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + cqp_info->post_sq = 1; + cqp_info->cqp_cmd = op; + cqp_info->in.u.aeq_create.aeq = sc_aeq; + cqp_info->in.u.aeq_create.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_ws_move_cmd - Move WS nodes + * @dev: pointer to device structure + * @node_move_info: pointer to ws node info + */ +int irdma_cqp_ws_move_cmd(struct irdma_sc_dev *dev, + struct irdma_ws_move_node_info *node_move_info) +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_sc_cqp *cqp = &iwcqp->sc_cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); + if (!cqp_request) + return -ENOMEM; + cqp_info = &cqp_request->info; + memset(cqp_info, 0, sizeof(*cqp_info)); + cqp_info->cqp_cmd = IRDMA_OP_WS_MOVE; + cqp_info->post_sq = 1; + cqp_info->in.u.ws_move_node.info = *node_move_info; + cqp_info->in.u.ws_move_node.cqp = cqp; + cqp_info->in.u.ws_move_node.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_cqp_ws_node_cmd - Add/modify/delete ws node + * @dev: pointer to device structure + * @cmd: Add, modify or delete + * @node_info: pointer to ws node info + */ +int irdma_cqp_ws_node_cmd(struct irdma_sc_dev *dev, u8 cmd, + struct irdma_ws_node_info *node_info) +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_sc_cqp *cqp = &iwcqp->sc_cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + bool poll; + + if (!rf->sc_dev.ceq_valid) + poll = true; + else + poll = false; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, !poll); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + memset(cqp_info, 0, sizeof(*cqp_info)); + cqp_info->cqp_cmd = cmd; + cqp_info->post_sq = 1; + cqp_info->in.u.ws_node.info = *node_info; + cqp_info->in.u.ws_node.cqp = cqp; + cqp_info->in.u.ws_node.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(rf, cqp_request); + if (status) + goto exit; + + if (poll) { + struct irdma_ccq_cqe_info compl_info; + + status = irdma_sc_poll_for_cqp_op_done(cqp, IRDMA_CQP_OP_WORK_SCHED_NODE, + &compl_info); + node_info->qs_handle = compl_info.op_ret_val; + ibdev_dbg(&rf->iwdev->ibdev, "DCB: opcode=%d, compl_info.retval=%d\n", + compl_info.op_code, compl_info.op_ret_val); + } else { + node_info->qs_handle = cqp_request->compl_info.op_ret_val; + } + +exit: + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +#if IS_ENABLED(CONFIG_CONFIGFS_FS) +/** + * irdma_cqp_up_map_cmd - Set the up-up mapping + * @dev: pointer to device structure + * @cmd: map command + * @map_info: pointer to up map info + */ +int irdma_cqp_up_map_cmd(struct irdma_sc_dev *dev, u8 cmd, + struct irdma_up_info *map_info) +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + struct irdma_cqp *iwcqp = &rf->cqp; + struct irdma_sc_cqp *cqp = &iwcqp->sc_cqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, false); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + memset(cqp_info, 0, sizeof(*cqp_info)); + cqp_info->cqp_cmd = cmd; + cqp_info->post_sq = 1; + cqp_info->in.u.up_map.info = *map_info; + cqp_info->in.u.up_map.cqp = cqp; + cqp_info->in.u.up_map.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +#endif /* CONFIG_CONFIGFS_FS */ +/** + * irdma_ah_do_cqp - perform an AH cqp operation + * @rf: RDMA PCI function + * @sc_ah: address handle + * @cmd: AH operation + * @wait: wait if true + * @callback_fcn: Callback function on CQP op completion + * @cb_param: parameter for callback function + * + * returns errno + */ +static int irdma_ah_do_cqp(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd, + bool wait, + void (*callback_fcn)(struct irdma_cqp_request *), + void *cb_param) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + if (cmd != IRDMA_OP_AH_CREATE && cmd != IRDMA_OP_AH_DESTROY) + return -EINVAL; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, wait); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = cmd; + cqp_info->post_sq = 1; + if (cmd == IRDMA_OP_AH_CREATE) { + if (!wait) + irdma_get_cqp_request(cqp_request); + sc_ah->ah_info.cqp_request = cqp_request; + + cqp_info->in.u.ah_create.info = sc_ah->ah_info; + cqp_info->in.u.ah_create.scratch = (uintptr_t)cqp_request; + cqp_info->in.u.ah_create.cqp = &rf->cqp.sc_cqp; + } else if (cmd == IRDMA_OP_AH_DESTROY) { + cqp_info->in.u.ah_destroy.info = sc_ah->ah_info; + cqp_info->in.u.ah_destroy.scratch = (uintptr_t)cqp_request; + cqp_info->in.u.ah_destroy.cqp = &rf->cqp.sc_cqp; + } + + if (!wait) { + cqp_request->callback_fcn = callback_fcn; + cqp_request->param = cb_param; + } + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + if (status) + return -ENOMEM; + + if (wait) + sc_ah->ah_info.ah_valid = (cmd != IRDMA_OP_AH_DESTROY); + + return 0; +} + +int irdma_ah_cqp_op(struct irdma_pci_f *rf, struct irdma_sc_ah *sc_ah, u8 cmd, + bool wait, + void (*callback_fcn)(struct irdma_cqp_request *), + void *cb_param) +{ + int status; + + if (cmd == IRDMA_OP_AH_CREATE) { + status = irdma_get_arp(rf, sc_ah->ah_info.dst_arpindex); + if (status) { + ibdev_err(&rf->iwdev->ibdev, "%s get_arp failed for index = %d\n", + __func__, sc_ah->ah_info.dst_arpindex); + + return -EINVAL; + } + status = irdma_ah_do_cqp(rf, sc_ah, cmd, wait, callback_fcn, + cb_param); + if (status) + irdma_put_arp(rf, sc_ah->ah_info.dst_arpindex); + } else { + status = irdma_ah_do_cqp(rf, sc_ah, cmd, wait, callback_fcn, + cb_param); + if (cmd == IRDMA_OP_AH_DESTROY) + irdma_put_arp(rf, sc_ah->ah_info.dst_arpindex); + } + + return status; +} + +/** + * irdma_ieq_ah_cb - callback after creation of AH for IEQ + * @cqp_request: pointer to cqp_request of create AH + */ +static void irdma_ieq_ah_cb(struct irdma_cqp_request *cqp_request) +{ + struct irdma_sc_qp *qp = cqp_request->param; + struct irdma_sc_ah *sc_ah = qp->pfpdu.ah; + unsigned long flags; + + spin_lock_irqsave(&qp->pfpdu.lock, flags); + if (!cqp_request->compl_info.op_ret_val) { + sc_ah->ah_info.ah_valid = true; + irdma_ieq_process_fpdus(qp, qp->vsi->ieq); + } else { + sc_ah->ah_info.ah_valid = false; + irdma_ieq_cleanup_qp(qp->vsi->ieq, qp); + } + spin_unlock_irqrestore(&qp->pfpdu.lock, flags); +} + +/** + * irdma_ilq_ah_cb - callback after creation of AH for ILQ + * @cqp_request: pointer to cqp_request of create AH + */ +static void irdma_ilq_ah_cb(struct irdma_cqp_request *cqp_request) +{ + struct irdma_cm_node *cm_node = cqp_request->param; + struct irdma_sc_ah *sc_ah = cm_node->ah; + + sc_ah->ah_info.ah_valid = !cqp_request->compl_info.op_ret_val; + irdma_add_conn_est_qh(cm_node); +} + +/** + * irdma_puda_create_ah - create AH for ILQ/IEQ qp's + * @dev: device pointer + * @ah_info: Address handle info + * @wait: When true will wait for operation to complete + * @type: ILQ/IEQ + * @cb_param: Callback param when not waiting + * @ah_ret: Returned pointer to address handle if created + * + */ +int irdma_puda_create_ah(struct irdma_sc_dev *dev, + struct irdma_ah_info *ah_info, bool wait, + enum puda_rsrc_type type, void *cb_param, + struct irdma_sc_ah **ah_ret) +{ + struct irdma_sc_ah *ah; + struct irdma_pci_f *rf = dev_to_rf(dev); + int err; + + ah = kzalloc(sizeof(*ah), GFP_ATOMIC); + *ah_ret = ah; + if (!ah) + return -ENOMEM; + + err = irdma_alloc_rsrc(rf, rf->allocated_ahs, rf->max_ah, + &ah_info->ah_idx, &rf->next_ah); + if (err) + goto err_free; + + ah->dev = dev; + ah->ah_info = *ah_info; + + if (type == IRDMA_PUDA_RSRC_TYPE_ILQ) + err = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait, + irdma_ilq_ah_cb, cb_param); + else + err = irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_CREATE, wait, + irdma_ieq_ah_cb, cb_param); + + if (err) + goto error; + return 0; + +error: + irdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx); +err_free: + kfree(ah); + *ah_ret = NULL; + return -ENOMEM; +} + +/** + * irdma_puda_free_ah - free a puda address handle + * @dev: device pointer + * @ah: The address handle to free + */ +void irdma_puda_free_ah(struct irdma_sc_dev *dev, struct irdma_sc_ah *ah) +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + + if (!ah) + return; + + if (ah->ah_info.ah_valid) { + irdma_ah_cqp_op(rf, ah, IRDMA_OP_AH_DESTROY, false, NULL, NULL); + irdma_free_rsrc(rf, rf->allocated_ahs, ah->ah_info.ah_idx); + } + + kfree(ah); +} + +/** + * irdma_prm_add_pble_mem - add moemory to pble resources + * @pprm: pble resource manager + * @pchunk: chunk of memory to add + */ +int irdma_prm_add_pble_mem(struct irdma_pble_prm *pprm, + struct irdma_chunk *pchunk) +{ + u64 sizeofbitmap; + + if (pchunk->size & 0xfff) + return -EINVAL; + + sizeofbitmap = (u64)pchunk->size >> pprm->pble_shift; + + pchunk->bitmapbuf = bitmap_zalloc(sizeofbitmap, GFP_KERNEL); + if (!pchunk->bitmapbuf) + return -ENOMEM; + + pchunk->sizeofbitmap = sizeofbitmap; + /* each pble is 8 bytes hence shift by 3 */ + pprm->total_pble_alloc += pchunk->size >> 3; + pprm->free_pble_cnt += pchunk->size >> 3; + + return 0; +} + +/** + * irdma_prm_get_pbles - get pble's from prm + * @pprm: pble resource manager + * @chunkinfo: nformation about chunk where pble's were acquired + * @mem_size: size of pble memory needed + * @vaddr: returns virtual address of pble memory + * @fpm_addr: returns fpm address of pble memory + */ +int irdma_prm_get_pbles(struct irdma_pble_prm *pprm, + struct irdma_pble_chunkinfo *chunkinfo, u64 mem_size, + u64 **vaddr, u64 *fpm_addr) +{ + u64 bits_needed; + u64 bit_idx = PBLE_INVALID_IDX; + struct irdma_chunk *pchunk = NULL; + struct list_head *chunk_entry = pprm->clist.next; + u32 offset; + unsigned long flags; + *vaddr = NULL; + *fpm_addr = 0; + + bits_needed = DIV_ROUND_UP_ULL(mem_size, BIT_ULL(pprm->pble_shift)); + + spin_lock_irqsave(&pprm->prm_lock, flags); + while (chunk_entry != &pprm->clist) { + pchunk = (struct irdma_chunk *)chunk_entry; + bit_idx = bitmap_find_next_zero_area(pchunk->bitmapbuf, + pchunk->sizeofbitmap, 0, + bits_needed, 0); + if (bit_idx < pchunk->sizeofbitmap) + break; + + /* list.next used macro */ + chunk_entry = pchunk->list.next; + } + + if (!pchunk || bit_idx >= pchunk->sizeofbitmap) { + spin_unlock_irqrestore(&pprm->prm_lock, flags); + return -ENOMEM; + } + + bitmap_set(pchunk->bitmapbuf, bit_idx, bits_needed); + offset = bit_idx << pprm->pble_shift; + *vaddr = pchunk->vaddr + offset; + *fpm_addr = pchunk->fpm_addr + offset; + + chunkinfo->pchunk = pchunk; + chunkinfo->bit_idx = bit_idx; + chunkinfo->bits_used = bits_needed; + /* 3 is sizeof pble divide */ + pprm->free_pble_cnt -= chunkinfo->bits_used << (pprm->pble_shift - 3); + spin_unlock_irqrestore(&pprm->prm_lock, flags); + + return 0; +} + +/** + * irdma_prm_return_pbles - return pbles back to prm + * @pprm: pble resource manager + * @chunkinfo: chunk where pble's were acquired and to be freed + */ +void irdma_prm_return_pbles(struct irdma_pble_prm *pprm, + struct irdma_pble_chunkinfo *chunkinfo) +{ + unsigned long flags; + + spin_lock_irqsave(&pprm->prm_lock, flags); + pprm->free_pble_cnt += chunkinfo->bits_used << (pprm->pble_shift - 3); + bitmap_clear(chunkinfo->pchunk->bitmapbuf, chunkinfo->bit_idx, + chunkinfo->bits_used); + spin_unlock_irqrestore(&pprm->prm_lock, flags); +} + +int irdma_map_vm_page_list(struct irdma_hw *hw, void *va, dma_addr_t *pg_dma, + u32 pg_cnt) +{ + struct page *vm_page; + int i; + u8 *addr; + + addr = (u8 *)(uintptr_t)va; + for (i = 0; i < pg_cnt; i++) { + vm_page = vmalloc_to_page(addr); + if (!vm_page) + goto err; + + pg_dma[i] = dma_map_page(hw->device, vm_page, 0, PAGE_SIZE, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(hw->device, pg_dma[i])) + goto err; + + addr += PAGE_SIZE; + } + + return 0; + +err: + irdma_unmap_vm_page_list(hw, pg_dma, i); + return -ENOMEM; +} + +void irdma_unmap_vm_page_list(struct irdma_hw *hw, dma_addr_t *pg_dma, u32 pg_cnt) +{ + int i; + + for (i = 0; i < pg_cnt; i++) + dma_unmap_page(hw->device, pg_dma[i], PAGE_SIZE, + DMA_BIDIRECTIONAL); +} + +/** + * irdma_pble_free_paged_mem - free virtual paged memory + * @chunk: chunk to free with paged memory + */ +void irdma_pble_free_paged_mem(struct irdma_chunk *chunk) +{ + if (!chunk->pg_cnt) + goto done; + + irdma_unmap_vm_page_list(chunk->dev->hw, chunk->dmainfo.dmaaddrs, + chunk->pg_cnt); + +done: + kfree(chunk->dmainfo.dmaaddrs); + chunk->dmainfo.dmaaddrs = NULL; + vfree(chunk->vaddr); + chunk->vaddr = NULL; + chunk->type = 0; +} + +/** + * irdma_pble_get_paged_mem -allocate paged memory for pbles + * @chunk: chunk to add for paged memory + * @pg_cnt: number of pages needed + */ +int irdma_pble_get_paged_mem(struct irdma_chunk *chunk, u32 pg_cnt) +{ + u32 size; + void *va; + + chunk->dmainfo.dmaaddrs = kzalloc(pg_cnt << 3, GFP_KERNEL); + if (!chunk->dmainfo.dmaaddrs) + return -ENOMEM; + + size = PAGE_SIZE * pg_cnt; + va = vmalloc(size); + if (!va) + goto err; + + if (irdma_map_vm_page_list(chunk->dev->hw, va, chunk->dmainfo.dmaaddrs, + pg_cnt)) { + vfree(va); + goto err; + } + chunk->vaddr = va; + chunk->size = size; + chunk->pg_cnt = pg_cnt; + chunk->type = PBLE_SD_PAGED; + + return 0; +err: + kfree(chunk->dmainfo.dmaaddrs); + chunk->dmainfo.dmaaddrs = NULL; + + return -ENOMEM; +} + +void irdma_update_vf_vlan_cfg(struct irdma_sc_dev *dev, + struct irdma_vchnl_dev *vc_dev) +{ + struct iidc_core_dev_info *cdev_info = dev_to_rf(dev)->cdev; + struct iidc_vf_port_info port_info = {}; + + if (cdev_info->ops->get_vf_info(cdev_info, vc_dev->vf_id, &port_info)) + return; + + vc_dev->port_vlan_en = port_info.port_vlan_id ? true : false; +} + +struct irdma_sc_vsi *irdma_update_vsi_ctx(struct irdma_sc_dev *dev, + struct irdma_vchnl_dev *vc_dev, + bool enable) +{ + struct irdma_vsi_init_info vsi_info = {}; + struct irdma_l2params l2params = {}; + struct irdma_pci_f *rf = dev_to_rf(dev); + struct irdma_sc_vsi *vf_vsi; + struct iidc_core_dev_info *cdev_info = dev_to_rf(dev)->cdev; + + vf_vsi = vc_dev->vf_vsi; + if (!vf_vsi && enable) { + struct iidc_vf_port_info port_info = {}; + struct irdma_device *iwdev = rf->iwdev; + + if (cdev_info->ops->get_vf_info(cdev_info, vc_dev->vf_id, + &port_info)) + return NULL; + + vf_vsi = kzalloc(sizeof(*vf_vsi), GFP_KERNEL); + if (!vf_vsi) + return NULL; + + vc_dev->port_vlan_en = port_info.port_vlan_id ? true : false; + l2params.up2tc[0] = iwdev->vsi.qos[0].traffic_class; + l2params.mtu = iwdev->vsi.mtu; + l2params.num_tc = 1; + l2params.vsi_rel_bw = iwdev->vsi.qos[0].rel_bw; + l2params.vsi_prio_type = iwdev->vsi.qos[0].prio_type; + + vsi_info.vm_vf_type = IRDMA_PF_TYPE; + vsi_info.dev = dev; + vsi_info.back_vsi = iwdev; + vsi_info.params = &l2params; + vsi_info.pf_data_vsi_num = port_info.vport_id; + vsi_info.register_qset = rf->gen_ops.register_qset; + vsi_info.unregister_qset = rf->gen_ops.unregister_qset; + irdma_sc_vsi_init(vf_vsi, &vsi_info); + } + if (!vf_vsi) + return NULL; + if (!enable) { + cdev_info->ops->update_vport_filter(cdev_info, vf_vsi->vsi_idx, + false); + kfree(vf_vsi); + vf_vsi = NULL; + vc_dev->vf_vsi = NULL; + } else { + cdev_info->ops->update_vport_filter(cdev_info, vf_vsi->vsi_idx, + true); + } + + return vf_vsi; +} + +/** + * irdma_alloc_ws_node_id - Allocate a tx scheduler node ID + * @dev: device pointer + */ +u16 irdma_alloc_ws_node_id(struct irdma_sc_dev *dev) +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + u32 next = 1; + u32 node_id; + + if (irdma_alloc_rsrc(rf, rf->allocated_ws_nodes, rf->max_ws_node_id, + &node_id, &next)) + return IRDMA_WS_NODE_INVALID; + + return (u16)node_id; +} + +/** + * irdma_free_ws_node_id - Free a tx scheduler node ID + * @dev: device pointer + * @node_id: Work scheduler node ID + */ +void irdma_free_ws_node_id(struct irdma_sc_dev *dev, u16 node_id) +{ + struct irdma_pci_f *rf = dev_to_rf(dev); + + irdma_free_rsrc(rf, rf->allocated_ws_nodes, (u32)node_id); +} + +/** + * irdma_modify_qp_to_err - Modify a QP to error + * @sc_qp: qp structure + */ +void irdma_modify_qp_to_err(struct irdma_sc_qp *sc_qp) +{ + struct irdma_qp *qp = sc_qp->qp_uk.back_qp; + struct ib_qp_attr attr; + + if (qp->iwdev->rf->reset) + return; + attr.qp_state = IB_QPS_ERR; + + if (rdma_protocol_roce(qp->ibqp.device, 1)) + irdma_modify_qp_roce(&qp->ibqp, &attr, IB_QP_STATE, NULL); + else + irdma_modify_qp(&qp->ibqp, &attr, IB_QP_STATE, NULL); +} + +void irdma_ib_qp_event(struct irdma_qp *iwqp, enum irdma_qp_event_type event) +{ + struct ib_event ibevent; + + if (!iwqp->ibqp.event_handler) + return; + + switch (event) { + case IRDMA_QP_EVENT_CATASTROPHIC: + ibevent.event = IB_EVENT_QP_FATAL; + break; + case IRDMA_QP_EVENT_ACCESS_ERR: + ibevent.event = IB_EVENT_QP_ACCESS_ERR; + break; + case IRDMA_QP_EVENT_REQ_ERR: + ibevent.event = IB_EVENT_QP_REQ_ERR; + break; + } + ibevent.device = iwqp->ibqp.device; + ibevent.element.qp = &iwqp->ibqp; + iwqp->ibqp.event_handler(&ibevent, iwqp->ibqp.qp_context); +} +static void clear_qp_ctx_addr(__le64 *ctx) +{ + u64 tmp; + + get_64bit_val(ctx, 272, &tmp); + tmp &= GENMASK_ULL(63, 58); + set_64bit_val(ctx, 272, tmp); + + get_64bit_val(ctx, 296, &tmp); + tmp &= GENMASK_ULL(7, 0); + set_64bit_val(ctx, 296, tmp); + + get_64bit_val(ctx, 312, &tmp); + tmp &= GENMASK_ULL(7, 0); + set_64bit_val(ctx, 312, tmp); + + set_64bit_val(ctx, 368, 0); +} + +/** + * irdma_upload_qp_context - upload raw QP context + * @iwqp: QP pointer + * @freeze: freeze QP + * @raw: raw context flag + */ +int irdma_upload_qp_context(struct irdma_qp *iwqp, bool freeze, bool raw) +{ + struct irdma_dma_mem dma_mem; + struct irdma_sc_dev *dev; + struct irdma_sc_qp *qp; + struct irdma_cqp *iwcqp; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_upload_context_info *info; + struct irdma_pci_f *rf; + int ret; + u32 *ctx; + + rf = iwqp->iwdev->rf; + if (!rf) + return -EINVAL; + + qp = &iwqp->sc_qp; + dev = &rf->sc_dev; + iwcqp = &rf->cqp; + + cqp_request = irdma_alloc_and_get_cqp_request(iwcqp, true); + if (!cqp_request) + return -EINVAL; + + cqp_info = &cqp_request->info; + info = &cqp_info->in.u.qp_upload_context.info; + memset(info, 0, sizeof(struct irdma_upload_context_info)); + cqp_info->cqp_cmd = IRDMA_OP_QP_UPLOAD_CONTEXT; + cqp_info->post_sq = 1; + cqp_info->in.u.qp_upload_context.dev = dev; + cqp_info->in.u.qp_upload_context.scratch = (uintptr_t)cqp_request; + + dma_mem.size = ALIGN(PAGE_SIZE, PAGE_SIZE); + dma_mem.va = dma_alloc_coherent(dev->hw->device, dma_mem.size, + &dma_mem.pa, GFP_KERNEL); + if (!dma_mem.va) { + irdma_put_cqp_request(&rf->cqp, cqp_request); + return -ENOMEM; + } + + ctx = dma_mem.va; + info->buf_pa = dma_mem.pa; + info->raw_format = raw; + info->freeze_qp = freeze; + info->qp_type = qp->qp_uk.qp_type; /* 1 is iWARP and 2 UDA */ + info->qp_id = qp->qp_uk.qp_id; + ret = irdma_handle_cqp_op(rf, cqp_request); + if (ret) + goto error; + ibdev_dbg(to_ibdev(dev), "QP: PRINT CONTXT QP [%u]\n", info->qp_id); + { + u32 i, j; + + clear_qp_ctx_addr(dma_mem.va); + for (i = 0, j = 0; i < 32; i++, j += 4) + ibdev_dbg(to_ibdev(dev), + "QP: [%u] %u:\t [%08X %08x %08X %08X]\n", + info->qp_id, (j * 4), ctx[j], ctx[j + 1], ctx[j + 2], + ctx[j + 3]); + } +error: + irdma_put_cqp_request(iwcqp, cqp_request); + dma_free_coherent(dev->hw->device, dma_mem.size, dma_mem.va, + dma_mem.pa); + dma_mem.va = NULL; + + return ret; +} + +bool irdma_cq_empty(struct irdma_cq *iwcq) +{ + struct irdma_cq_uk *ukcq; + u64 qword3; + __le64 *cqe; + u8 polarity; + + ukcq = &iwcq->sc_cq.cq_uk; + cqe = IRDMA_GET_CURRENT_CQ_ELEM(ukcq); + get_64bit_val(cqe, 24, &qword3); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); + + return polarity != ukcq->polarity; +} + +static bool qp_has_unpolled_cqes(struct irdma_qp *iwqp, struct irdma_cq *iwcq) +{ + struct irdma_cq_uk *cq = &iwcq->sc_cq.cq_uk; + struct irdma_qp_uk *qp = &iwqp->sc_qp.qp_uk; + u32 cq_head = IRDMA_RING_CURRENT_HEAD(cq->cq_ring); + u64 qword3, comp_ctx; + __le64 *cqe; + u8 polarity, cq_polarity; + + cq_polarity = cq->polarity; + do { + if (cq->avoid_mem_cflct) + cqe = ((struct irdma_extended_cqe *)(cq->cq_base))[cq_head].buf; + else + cqe = cq->cq_base[cq_head].buf; + get_64bit_val(cqe, 24, &qword3); + polarity = (u8)FIELD_GET(IRDMA_CQ_VALID, qword3); + + if (polarity != cq_polarity) + break; + + /* Ensure CQE contents are read after valid bit is checked */ + dma_rmb(); + + get_64bit_val(cqe, 8, &comp_ctx); + if ((struct irdma_qp_uk *)(unsigned long)comp_ctx == qp) + return true; + + cq_head = (cq_head + 1) % cq->cq_ring.size; + if (!cq_head) + cq_polarity ^= 1; + } while (true); + + return false; +} + +void irdma_remove_cmpls_list(struct irdma_cq *iwcq) +{ + struct irdma_cmpl_gen *cmpl_node; + struct list_head *tmp_node, *list_node; + + list_for_each_safe(list_node, tmp_node, &iwcq->cmpl_generated) { + cmpl_node = list_entry(list_node, struct irdma_cmpl_gen, list); + list_del(&cmpl_node->list); + kfree(cmpl_node); + } +} + +int irdma_generated_cmpls(struct irdma_cq *iwcq, struct irdma_cq_poll_info *cq_poll_info) +{ + struct irdma_cmpl_gen *cmpl; + + if (list_empty(&iwcq->cmpl_generated)) + return -ENOENT; + cmpl = list_first_entry_or_null(&iwcq->cmpl_generated, struct irdma_cmpl_gen, list); + list_del(&cmpl->list); + memcpy(cq_poll_info, &cmpl->cpi, sizeof(*cq_poll_info)); + kfree(cmpl); + + ibdev_dbg(to_ibdev(iwcq->sc_cq.dev), + "VERBS: %s: Poll artificially generated completion for QP 0x%X, op %u, wr_id=0x%llx\n", + __func__, cq_poll_info->qp_id, cq_poll_info->op_type, + cq_poll_info->wr_id); + + return 0; +} + +/** + * irdma_set_cpi_common_values - fill in values for polling info struct + * @cpi: resulting structure of cq_poll_info type + * @qp: QPair + * @qp_num: id of the QP + */ +static void irdma_set_cpi_common_values(struct irdma_cq_poll_info *cpi, + struct irdma_qp_uk *qp, u32 qp_num) +{ + cpi->comp_status = IRDMA_COMPL_STATUS_FLUSHED; + cpi->error = 1; + cpi->major_err = IRDMA_FLUSH_MAJOR_ERR; + cpi->minor_err = FLUSH_GENERAL_ERR; + cpi->qp_handle = (irdma_qp_handle)(uintptr_t)qp; + cpi->qp_id = qp_num; +} + +static inline void irdma_comp_handler(struct irdma_cq *cq) +{ + if (!cq->ibcq.comp_handler) + return; + + if (atomic_read(&cq->armed)) + cq->ibcq.comp_handler(&cq->ibcq, cq->ibcq.cq_context); +} + +/** + * irdma_generate_flush_completions - generate completion from WRs + * @iwqp: pointer to QP + */ +void irdma_generate_flush_completions(struct irdma_qp *iwqp) +{ + struct irdma_qp_uk *qp = &iwqp->sc_qp.qp_uk; + struct irdma_ring *sq_ring = &qp->sq_ring; + struct irdma_ring *rq_ring = &qp->rq_ring; + struct irdma_cmpl_gen *cmpl; + __le64 *sw_wqe; + u64 wqe_qword; + u32 wqe_idx; + bool compl_generated = false; + unsigned long flags1; + + spin_lock_irqsave(&iwqp->iwscq->lock, flags1); + if (!qp_has_unpolled_cqes(iwqp, iwqp->iwscq)) { + unsigned long flags2; + + spin_lock_irqsave(&iwqp->lock, flags2); + while (IRDMA_RING_MORE_WORK(*sq_ring)) { + cmpl = kzalloc(sizeof(*cmpl), GFP_ATOMIC); + if (!cmpl) { + spin_unlock_irqrestore(&iwqp->lock, flags2); + spin_unlock_irqrestore(&iwqp->iwscq->lock, flags1); + return; + } + + wqe_idx = sq_ring->tail; + irdma_set_cpi_common_values(&cmpl->cpi, qp, qp->qp_id); + + cmpl->cpi.wr_id = qp->sq_wrtrk_array[wqe_idx].wrid; + sw_wqe = qp->sq_base[wqe_idx].elem; + get_64bit_val(sw_wqe, 24, &wqe_qword); + cmpl->cpi.op_type = (u8)FIELD_GET(IRDMAQPSQ_OPCODE, wqe_qword); + cmpl->cpi.q_type = IRDMA_CQE_QTYPE_SQ; + /* remove the SQ WR by moving SQ tail*/ + IRDMA_RING_SET_TAIL(*sq_ring, + sq_ring->tail + qp->sq_wrtrk_array[sq_ring->tail].quanta); + + if (cmpl->cpi.op_type == IRDMAQP_OP_NOP) { + kfree(cmpl); + continue; + } + ibdev_dbg(to_ibdev(iwqp->sc_qp.dev), + "DEV: %s: adding wr_id = 0x%llx SQ Completion to list qp_id=%d\n", + __func__, cmpl->cpi.wr_id, qp->qp_id); + list_add_tail(&cmpl->list, &iwqp->iwscq->cmpl_generated); + compl_generated = true; + } + spin_unlock_irqrestore(&iwqp->lock, flags2); + spin_unlock_irqrestore(&iwqp->iwscq->lock, flags1); + if (compl_generated) { + irdma_comp_handler(iwqp->iwscq); + compl_generated = false; + } + } else { + spin_unlock_irqrestore(&iwqp->iwscq->lock, flags1); + irdma_sched_qp_flush_work(iwqp); + } + + spin_lock_irqsave(&iwqp->iwrcq->lock, flags1); + if (!qp_has_unpolled_cqes(iwqp, iwqp->iwrcq)) { + unsigned long flags2; + + spin_lock_irqsave(&iwqp->lock, flags2); + while (IRDMA_RING_MORE_WORK(*rq_ring)) { + cmpl = kzalloc(sizeof(*cmpl), GFP_ATOMIC); + if (!cmpl) { + spin_unlock_irqrestore(&iwqp->lock, flags2); + spin_unlock_irqrestore(&iwqp->iwrcq->lock, flags1); + return; + } + + wqe_idx = rq_ring->tail; + irdma_set_cpi_common_values(&cmpl->cpi, qp, qp->qp_id); + + cmpl->cpi.wr_id = qp->rq_wrid_array[wqe_idx]; + cmpl->cpi.op_type = IRDMA_OP_TYPE_REC; + cmpl->cpi.q_type = IRDMA_CQE_QTYPE_RQ; + /* remove the RQ WR by moving RQ tail */ + IRDMA_RING_SET_TAIL(*rq_ring, rq_ring->tail + 1); + ibdev_dbg(to_ibdev(iwqp->sc_qp.dev), + "DEV: %s: adding wr_id = 0x%llx RQ Completion to list qp_id=%d, wqe_idx=%d\n", + __func__, cmpl->cpi.wr_id, qp->qp_id, + wqe_idx); + + list_add_tail(&cmpl->list, &iwqp->iwrcq->cmpl_generated); + + compl_generated = true; + } + spin_unlock_irqrestore(&iwqp->lock, flags2); + spin_unlock_irqrestore(&iwqp->iwrcq->lock, flags1); + if (compl_generated) + irdma_comp_handler(iwqp->iwrcq); + } else { + spin_unlock_irqrestore(&iwqp->iwrcq->lock, flags1); + irdma_sched_qp_flush_work(iwqp); + } +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/verbs.c b/drivers/intel/irdma-1.14.33/src/irdma/verbs.c new file mode 100644 index 000000000..b572ae79d --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/verbs.c @@ -0,0 +1,4781 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "main.h" + +/** + * irdma_query_device - get device attributes + * @ibdev: device pointer from stack + * @props: returning device attributes + * @udata: user data + */ +static int irdma_query_device(struct ib_device *ibdev, + struct ib_device_attr *props, + struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ibdev); + struct irdma_pci_f *rf = iwdev->rf; + struct pci_dev *pcidev = iwdev->rf->pcidev; + struct irdma_hw_attrs *hw_attrs = &rf->sc_dev.hw_attrs; + + if (udata->inlen || udata->outlen) + return -EINVAL; + + memset(props, 0, sizeof(*props)); + addrconf_addr_eui48((u8 *)&props->sys_image_guid, + iwdev->netdev->dev_addr); + props->fw_ver = (u64)irdma_fw_major_ver(&rf->sc_dev) << 32 | + irdma_fw_minor_ver(&rf->sc_dev); + props->device_cap_flags = IB_DEVICE_MEM_WINDOW | + IB_DEVICE_MEM_MGT_EXTENSIONS; +#ifdef IB_DEV_CAPS_VER_2 + props->kernel_cap_flags = IBK_LOCAL_DMA_LKEY; +#else + props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY; +#endif + props->vendor_id = pcidev->vendor; + props->vendor_part_id = pcidev->device; + props->hw_ver = pcidev->revision; + props->page_size_cap = hw_attrs->page_size_cap; + props->max_mr_size = hw_attrs->max_mr_size; + props->max_qp = rf->max_qp - rf->used_qps; + props->max_qp_wr = hw_attrs->max_qp_wr; + set_max_sge(props, rf); + props->max_cq = rf->max_cq - rf->used_cqs; + props->max_cqe = rf->max_cqe - 1; + props->max_mr = rf->max_mr - rf->used_mrs; + if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_3) + props->max_mw = props->max_mr; + props->max_pd = rf->max_pd - rf->used_pds; + props->max_sge_rd = hw_attrs->uk_attrs.max_hw_read_sges; + props->max_qp_rd_atom = hw_attrs->max_hw_ird; + props->max_qp_init_rd_atom = hw_attrs->max_hw_ord; + if (rdma_protocol_roce(ibdev, 1)) { + props->device_cap_flags |= IB_DEVICE_RC_RNR_NAK_GEN; + props->max_pkeys = IRDMA_PKEY_TBL_SZ; + props->max_ah = rf->max_ah; + if (hw_attrs->uk_attrs.hw_rev == IRDMA_GEN_2) { + props->max_mcast_grp = rf->max_mcg; + props->max_mcast_qp_attach = IRDMA_MAX_MGS_PER_CTX; + props->max_total_mcast_qp_attach = rf->max_qp * IRDMA_MAX_MGS_PER_CTX; + } + } + props->max_fast_reg_page_list_len = IRDMA_MAX_PAGES_PER_FMR; + props->max_srq = rf->max_srq - rf->used_srqs; + props->max_srq_wr = IRDMA_MAX_SRQ_WRS; + props->max_srq_sge = hw_attrs->uk_attrs.max_hw_wq_frags; + if (hw_attrs->uk_attrs.feature_flags & IRDMA_FEATURE_ATOMIC_OPS) + props->atomic_cap = IB_ATOMIC_HCA; + else + props->atomic_cap = IB_ATOMIC_NONE; + props->masked_atomic_cap = props->atomic_cap; + if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_3) { +#define HCA_CORE_CLOCK_KHZ 1000000UL + props->timestamp_mask = GENMASK(31, 0); + props->hca_core_clock = HCA_CORE_CLOCK_KHZ; + } + if (hw_attrs->uk_attrs.hw_rev >= IRDMA_GEN_2) + props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B; + + return 0; +} + +static int irdma_mmap_legacy(struct irdma_ucontext *ucontext, + struct vm_area_struct *vma) +{ + u64 pfn; + + if (vma->vm_pgoff || vma->vm_end - vma->vm_start != PAGE_SIZE) + return -EINVAL; + + vma->vm_private_data = ucontext; + pfn = ((uintptr_t)ucontext->iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET] + + pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT; + +#ifdef RDMA_MMAP_DB_SUPPORT + return rdma_user_mmap_io(&ucontext->ibucontext, vma, pfn, PAGE_SIZE, + pgprot_noncached(vma->vm_page_prot), NULL); +#else + return rdma_user_mmap_io(&ucontext->ibucontext, vma, pfn, PAGE_SIZE, + pgprot_noncached(vma->vm_page_prot)); +#endif +} + +#ifdef RDMA_MMAP_DB_SUPPORT +static void irdma_mmap_free(struct rdma_user_mmap_entry *rdma_entry) +{ + struct irdma_user_mmap_entry *entry = to_irdma_mmap_entry(rdma_entry); + + kfree(entry); +} + +struct rdma_user_mmap_entry* +irdma_user_mmap_entry_insert(struct irdma_ucontext *ucontext, u64 bar_offset, + enum irdma_mmap_flag mmap_flag, u64 *mmap_offset) +{ + struct irdma_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL); + int ret; + + if (!entry) + return NULL; + + entry->bar_offset = bar_offset; + entry->mmap_flag = mmap_flag; + + ret = rdma_user_mmap_entry_insert(&ucontext->ibucontext, + &entry->rdma_entry, PAGE_SIZE); + if (ret) { + kfree(entry); + return NULL; + } + *mmap_offset = rdma_user_mmap_get_offset(&entry->rdma_entry); + + return &entry->rdma_entry; +} + +#else /* RDMA_MMAP_DB_SUPPORT */ +static inline bool find_key_in_mmap_tbl(struct irdma_ucontext *ucontext, u64 key) +{ + struct irdma_user_mmap_entry *entry; + + hash_for_each_possible(ucontext->mmap_hash_tbl, entry, hlist, key) { + if (entry->pgoff_key == key) + return true; + } + + return false; +} + +struct irdma_user_mmap_entry * +irdma_user_mmap_entry_add_hash(struct irdma_ucontext *ucontext, u64 bar_offset, + enum irdma_mmap_flag mmap_flag, u64 *mmap_offset) +{ + struct irdma_user_mmap_entry *entry = kzalloc(sizeof(*entry), GFP_KERNEL); + unsigned long flags; + int retry_cnt = 0; + + if (!entry) + return NULL; + + entry->bar_offset = bar_offset; + entry->mmap_flag = mmap_flag; + entry->ucontext = ucontext; + do { + get_random_bytes(&entry->pgoff_key, sizeof(entry->pgoff_key)); + + /* The key is a page offset */ + entry->pgoff_key >>= PAGE_SHIFT; + + /*In the event of a collision in the hash table, retry a new key */ + spin_lock_irqsave(&ucontext->mmap_tbl_lock, flags); + if (!find_key_in_mmap_tbl(ucontext, entry->pgoff_key)) { + hash_add(ucontext->mmap_hash_tbl, &entry->hlist, entry->pgoff_key); + spin_unlock_irqrestore(&ucontext->mmap_tbl_lock, flags); + goto hash_add_done; + } + spin_unlock_irqrestore(&ucontext->mmap_tbl_lock, flags); + } while (retry_cnt++ < 10); + + ibdev_dbg(&ucontext->iwdev->ibdev, + "VERBS: mmap table add failed: Cannot find a unique key\n"); + kfree(entry); + return NULL; + +hash_add_done: + /*libc mmap uses a byte offset */ + *mmap_offset = entry->pgoff_key << PAGE_SHIFT; + + return entry; +} + +static struct irdma_user_mmap_entry *irdma_find_user_mmap_entry(struct irdma_ucontext *ucontext, + struct vm_area_struct *vma) +{ + struct irdma_user_mmap_entry *entry; + unsigned long flags; + + if (vma->vm_end - vma->vm_start != PAGE_SIZE) + return NULL; + + spin_lock_irqsave(&ucontext->mmap_tbl_lock, flags); + hash_for_each_possible(ucontext->mmap_hash_tbl, entry, hlist, vma->vm_pgoff) { + if (entry->pgoff_key == vma->vm_pgoff) { + spin_unlock_irqrestore(&ucontext->mmap_tbl_lock, flags); + return entry; + } + } + + spin_unlock_irqrestore(&ucontext->mmap_tbl_lock, flags); + + return NULL; +} + +void irdma_user_mmap_entry_del_hash(struct irdma_user_mmap_entry *entry) +{ + struct irdma_ucontext *ucontext; + unsigned long flags; + + if (!entry) + return; + + ucontext = entry->ucontext; + + spin_lock_irqsave(&ucontext->mmap_tbl_lock, flags); + hash_del(&entry->hlist); + spin_unlock_irqrestore(&ucontext->mmap_tbl_lock, flags); + + kfree(entry); +} + +#endif /* RDMA_MMAP_DB_SUPPORT */ +/** + * irdma_mmap - user memory map + * @context: context created during alloc + * @vma: kernel info for user memory map + */ +static int irdma_mmap(struct ib_ucontext *context, struct vm_area_struct *vma) +{ +#ifdef RDMA_MMAP_DB_SUPPORT + struct rdma_user_mmap_entry *rdma_entry; +#endif + struct irdma_user_mmap_entry *entry; + struct irdma_ucontext *ucontext; + u64 pfn; + int ret; + + ucontext = to_ucontext(context); + + /* Legacy support for libi40iw with hard-coded mmap key */ + if (ucontext->legacy_mode) + return irdma_mmap_legacy(ucontext, vma); + +#ifdef RDMA_MMAP_DB_SUPPORT + rdma_entry = rdma_user_mmap_entry_get(&ucontext->ibucontext, vma); + if (!rdma_entry) { + ibdev_dbg(&ucontext->iwdev->ibdev, + "VERBS: pgoff[0x%lx] does not have valid entry\n", + vma->vm_pgoff); + return -EINVAL; + } + + entry = to_irdma_mmap_entry(rdma_entry); +#else + entry = irdma_find_user_mmap_entry(ucontext, vma); + if (!entry) { + ibdev_dbg(&ucontext->iwdev->ibdev, + "VERBS: pgoff[0x%lx] does not have valid entry\n", + vma->vm_pgoff); + return -EINVAL; + } +#endif + ibdev_dbg(&ucontext->iwdev->ibdev, + "VERBS: bar_offset [0x%llx] mmap_flag [%d]\n", + entry->bar_offset, entry->mmap_flag); + + pfn = (entry->bar_offset + + pci_resource_start(ucontext->iwdev->rf->pcidev, 0)) >> PAGE_SHIFT; + + switch (entry->mmap_flag) { + case IRDMA_MMAP_IO_NC: +#ifdef RDMA_MMAP_DB_SUPPORT + ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE, + pgprot_noncached(vma->vm_page_prot), + rdma_entry); +#else + ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE, + pgprot_noncached(vma->vm_page_prot)); +#endif + break; + case IRDMA_MMAP_IO_WC: +#ifdef RDMA_MMAP_DB_SUPPORT + ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE, + pgprot_writecombine(vma->vm_page_prot), + rdma_entry); +#else + ret = rdma_user_mmap_io(context, vma, pfn, PAGE_SIZE, + pgprot_writecombine(vma->vm_page_prot)); +#endif + break; + default: + ret = -EINVAL; + } + + if (ret) + ibdev_dbg(&ucontext->iwdev->ibdev, + "VERBS: bar_offset [0x%llx] mmap_flag[%d] err[%d]\n", + entry->bar_offset, entry->mmap_flag, ret); +#ifdef RDMA_MMAP_DB_SUPPORT + rdma_user_mmap_entry_put(rdma_entry); +#endif + + return ret; +} + +/** + * irdma_alloc_push_page - allocate a push page for qp + * @iwqp: qp pointer + */ +static void irdma_alloc_push_page(struct irdma_qp *iwqp) +{ + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_device *iwdev = iwqp->iwdev; + struct irdma_sc_qp *qp = &iwqp->sc_qp; + struct irdma_pd *pd = iwqp->iwpd; + u32 push_pos = 0; + int status; + + mutex_lock(&pd->push_alloc_mutex); + /* Upstream push mode is only enabled for GEN_3 and + * skipping push reuse isn't necessary + */ + if (iwqp->iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_3) + goto skip_push_reuse; + if (pd->push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { + bitmap_zero(pd->push_offset_bmap, IRDMA_QPS_PER_PUSH_PAGE); + } else { + if (pd->qs_handle == qp->qs_handle) { + push_pos = find_first_zero_bit(pd->push_offset_bmap, + IRDMA_QPS_PER_PUSH_PAGE); + if (push_pos < IRDMA_QPS_PER_PUSH_PAGE) { + qp->push_idx = pd->push_idx; + qp->push_offset = push_pos * IRDMA_PUSH_WIN_SIZE; + __set_bit(push_pos, pd->push_offset_bmap); + } + } + goto exit; + } + +skip_push_reuse: + if (atomic64_read(&iwdev->rf->push_cnt) + 2 > + iwdev->rf->sc_dev.hw_attrs.max_hw_device_pages) + goto exit; + + if (!iwdev->rf->sc_dev.privileged) { + u32 pg_idx; + + status = irdma_vchnl_req_manage_push_pg(&iwdev->rf->sc_dev, true, + qp->qs_handle, &pg_idx); + if (!status && pg_idx != IRDMA_INVALID_PUSH_PAGE_INDEX) { + qp->push_idx = pg_idx; + qp->push_offset = push_pos * IRDMA_PUSH_WIN_SIZE; + atomic64_add(2, &iwdev->rf->push_cnt); + __set_bit(push_pos, pd->push_offset_bmap); + pd->push_idx = pg_idx; + pd->qs_handle = qp->qs_handle; + } + goto exit; + } + + cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); + if (!cqp_request) + goto exit; + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = IRDMA_OP_MANAGE_PUSH_PAGE; + cqp_info->post_sq = 1; + cqp_info->in.u.manage_push_page.info.push_idx = 0; + cqp_info->in.u.manage_push_page.info.qs_handle = + qp->vsi->qos[qp->user_pri].qs_handle[qp->qs_idx]; + cqp_info->in.u.manage_push_page.info.free_page = 0; + cqp_info->in.u.manage_push_page.info.push_page_type = 0; + cqp_info->in.u.manage_push_page.cqp = &iwdev->rf->cqp.sc_cqp; + cqp_info->in.u.manage_push_page.scratch = (uintptr_t)cqp_request; + + status = irdma_handle_cqp_op(iwdev->rf, cqp_request); + if (!status && cqp_request->compl_info.op_ret_val < + iwdev->rf->sc_dev.hw_attrs.max_hw_device_pages) { + qp->push_idx = cqp_request->compl_info.op_ret_val; + atomic64_add(2, &iwdev->rf->push_cnt); + qp->push_offset = push_pos * IRDMA_PUSH_WIN_SIZE; + __set_bit(push_pos, pd->push_offset_bmap); + pd->push_idx = cqp_request->compl_info.op_ret_val; + pd->qs_handle = qp->qs_handle; + } + + irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); +exit: + mutex_unlock(&pd->push_alloc_mutex); +} + +/** + * irdma_get_pbl - Retrieve pbl from a list given a virtual + * address + * @va: user virtual address + * @pbl_list: pbl list to search in (QP's or CQ's) + */ +struct irdma_pbl *irdma_get_pbl(unsigned long va, + struct list_head *pbl_list) +{ + struct irdma_pbl *iwpbl; + + list_for_each_entry(iwpbl, pbl_list, list) { + if (iwpbl->user_base == va) { + list_del(&iwpbl->list); + iwpbl->on_list = false; + return iwpbl; + } + } + + return NULL; +} + +/** + * irdma_clean_cqes - clean cq entries for qp + * @iwqp: qp ptr (user or kernel) + * @iwcq: cq ptr + */ +void irdma_clean_cqes(struct irdma_qp *iwqp, struct irdma_cq *iwcq) +{ + struct irdma_cq_uk *ukcq = &iwcq->sc_cq.cq_uk; + unsigned long flags; + struct irdma_cmpl_gen *cmpl_node; + struct list_head *tmp_node, *list_node; + + spin_lock_irqsave(&iwcq->lock, flags); + irdma_uk_clean_cq(&iwqp->sc_qp.qp_uk, ukcq); + + list_for_each_safe(list_node, tmp_node, &iwcq->cmpl_generated) { + cmpl_node = list_entry(list_node, struct irdma_cmpl_gen, list); + if (cmpl_node->cpi.qp_id == iwqp->ibqp.qp_num) { + list_del(&cmpl_node->list); + kfree(cmpl_node); + } + } + + spin_unlock_irqrestore(&iwcq->lock, flags); +} + +static u64 irdma_compute_push_wqe_offset(struct irdma_device *iwdev, u32 page_idx) +{ + u64 bar_off = (uintptr_t)iwdev->rf->sc_dev.hw_regs[IRDMA_DB_ADDR_OFFSET]; + + if (iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2) { + /* skip over db page */ + bar_off += IRDMA_HW_PAGE_SIZE; + /* skip over reserved space */ + bar_off += iwdev->rf->ftype ? IRDMA_VF_BAR_RSVD : + IRDMA_PF_BAR_RSVD; + } + + /* push wqe page */ + bar_off += (u64)page_idx * IRDMA_HW_PAGE_SIZE; + + return bar_off; +} + +void irdma_remove_push_mmap_entries(struct irdma_qp *iwqp) +{ + if (iwqp->push_db_mmap_entry) { +#ifdef RDMA_MMAP_DB_SUPPORT + rdma_user_mmap_entry_remove(iwqp->push_db_mmap_entry); +#else + irdma_user_mmap_entry_del_hash(iwqp->push_db_mmap_entry); +#endif + iwqp->push_db_mmap_entry = NULL; + } + if (iwqp->push_wqe_mmap_entry) { +#ifdef RDMA_MMAP_DB_SUPPORT + rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry); +#else + irdma_user_mmap_entry_del_hash(iwqp->push_wqe_mmap_entry); +#endif + iwqp->push_wqe_mmap_entry = NULL; + } +} + +static int irdma_setup_push_mmap_entries(struct irdma_ucontext *ucontext, + struct irdma_qp *iwqp, + u64 *push_wqe_mmap_key, + u64 *push_db_mmap_key) +{ + struct irdma_device *iwdev = ucontext->iwdev; + u64 bar_off; + + WARN_ON_ONCE(iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev < IRDMA_GEN_2); + + bar_off = irdma_compute_push_wqe_offset(iwdev, iwqp->sc_qp.push_idx); + +#ifdef RDMA_MMAP_DB_SUPPORT + iwqp->push_wqe_mmap_entry = irdma_user_mmap_entry_insert(ucontext, + bar_off, IRDMA_MMAP_IO_WC, + push_wqe_mmap_key); +#else + iwqp->push_wqe_mmap_entry = irdma_user_mmap_entry_add_hash(ucontext, bar_off, + IRDMA_MMAP_IO_WC, + push_wqe_mmap_key); +#endif + if (!iwqp->push_wqe_mmap_entry) + return -ENOMEM; + + /* push doorbell page */ + bar_off += IRDMA_HW_PAGE_SIZE; +#ifdef RDMA_MMAP_DB_SUPPORT + iwqp->push_db_mmap_entry = irdma_user_mmap_entry_insert(ucontext, + bar_off, IRDMA_MMAP_IO_NC, + push_db_mmap_key); +#else + + iwqp->push_db_mmap_entry = irdma_user_mmap_entry_add_hash(ucontext, bar_off, + IRDMA_MMAP_IO_NC, + push_db_mmap_key); +#endif + if (!iwqp->push_db_mmap_entry) { +#ifdef RDMA_MMAP_DB_SUPPORT + rdma_user_mmap_entry_remove(iwqp->push_wqe_mmap_entry); +#else + irdma_user_mmap_entry_del_hash(iwqp->push_wqe_mmap_entry); +#endif + return -ENOMEM; + } + + return 0; +} + +/** + * irdma_setup_virt_qp - setup for allocation of virtual qp + * @iwdev: irdma device + * @iwqp: qp ptr + * @init_info: initialize info to return + */ +void irdma_setup_virt_qp(struct irdma_device *iwdev, + struct irdma_qp *iwqp, + struct irdma_qp_init_info *init_info) +{ + struct irdma_pbl *iwpbl = iwqp->iwpbl; + struct irdma_qp_mr *qpmr = &iwpbl->qp_mr; + + iwqp->page = qpmr->sq_page; + init_info->shadow_area_pa = qpmr->shadow; + if (iwpbl->pbl_allocated) { + init_info->virtual_map = true; + init_info->sq_pa = qpmr->sq_pbl.idx; + /* Need to use contiguous buffer for RQ of QP in case it is associated with SRQ */ + init_info->rq_pa = init_info->qp_uk_init_info.srq_uk ? qpmr->rq_pa : + qpmr->rq_pbl.idx; + } else { + init_info->sq_pa = qpmr->sq_pbl.addr; + init_info->rq_pa = qpmr->rq_pbl.addr; + } +} + +/** + * irdma_setup_umode_qp - setup sq and rq size in user mode qp + * @udata: user data + * @iwdev: iwarp device + * @iwqp: qp ptr (user or kernel) + * @info: initialize info to return + * @init_attr: Initial QP create attributes + */ +int irdma_setup_umode_qp(struct ib_udata *udata, + struct irdma_device *iwdev, + struct irdma_qp *iwqp, + struct irdma_qp_init_info *info, + struct ib_qp_init_attr *init_attr) +{ + struct irdma_ucontext *ucontext = kc_rdma_udata_to_drv_context(&iwqp->iwpd->ibpd, udata); + struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info; + struct irdma_create_qp_req req = {}; + unsigned long flags; + int ret; + + ret = ib_copy_from_udata(&req, udata, + min(sizeof(req), udata->inlen)); + if (ret) { + ibdev_dbg(&iwdev->ibdev, "VERBS: ib_copy_from_data fail\n"); + return ret; + } + + iwqp->ctx_info.qp_compl_ctx = req.user_compl_ctx; + iwqp->user_mode = 1; + if (req.user_wqe_bufs) { + info->qp_uk_init_info.legacy_mode = ucontext->legacy_mode; + spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags); + iwqp->iwpbl = irdma_get_pbl((unsigned long)req.user_wqe_bufs, + &ucontext->qp_reg_mem_list); + spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); + + if (!iwqp->iwpbl) { + ret = -ENODATA; + ibdev_dbg(&iwdev->ibdev, "VERBS: no pbl info\n"); + return ret; + } + } + + if (!ucontext->use_raw_attrs) { + /** + * Maintain backward compat with older ABI which passes sq and + * rq depth in quanta in cap.max_send_wr and cap.max_recv_wr. + * There is no way to compute the correct value of + * iwqp->max_send_wr/max_recv_wr in the kernel. + */ + iwqp->max_send_wr = init_attr->cap.max_send_wr; + iwqp->max_recv_wr = init_attr->cap.max_recv_wr; + ukinfo->sq_size = init_attr->cap.max_send_wr; + ukinfo->rq_size = init_attr->cap.max_recv_wr; + irdma_uk_calc_shift_wq(ukinfo, &ukinfo->sq_shift, &ukinfo->rq_shift); + } else { + ret = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth, + &ukinfo->sq_shift); + if (ret) + return ret; + + ret = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth, + &ukinfo->rq_shift); + if (ret) + return ret; + + iwqp->max_send_wr = (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift; + iwqp->max_recv_wr = (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift; + ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift; + ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift; + } + if (req.comp_mask & IRDMA_CREATE_QP_USE_START_WQE_IDX && + iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_RTS_AE) + ukinfo->start_wqe_idx = 4; + irdma_setup_virt_qp(iwdev, iwqp, info); + + return 0; +} + +/** + * irdma_setup_kmode_qp - setup initialization for kernel mode qp + * @iwdev: iwarp device + * @iwqp: qp ptr (user or kernel) + * @info: initialize info to return + * @init_attr: Initial QP create attributes + */ +int irdma_setup_kmode_qp(struct irdma_device *iwdev, + struct irdma_qp *iwqp, + struct irdma_qp_init_info *info, + struct ib_qp_init_attr *init_attr) +{ + struct irdma_dma_mem *mem = &iwqp->kqp.dma_mem; + u32 size; + int status; + struct irdma_qp_uk_init_info *ukinfo = &info->qp_uk_init_info; + + status = irdma_uk_calc_depth_shift_sq(ukinfo, &ukinfo->sq_depth, + &ukinfo->sq_shift); + if (status) + return status; + + status = irdma_uk_calc_depth_shift_rq(ukinfo, &ukinfo->rq_depth, + &ukinfo->rq_shift); + if (status) + return status; + + iwqp->kqp.sq_wrid_mem = + kcalloc(ukinfo->sq_depth, sizeof(*iwqp->kqp.sq_wrid_mem), GFP_KERNEL); + if (!iwqp->kqp.sq_wrid_mem) + return -ENOMEM; + + iwqp->kqp.rq_wrid_mem = + kcalloc(ukinfo->rq_depth, sizeof(*iwqp->kqp.rq_wrid_mem), GFP_KERNEL); + if (!iwqp->kqp.rq_wrid_mem) { + kfree(iwqp->kqp.sq_wrid_mem); + iwqp->kqp.sq_wrid_mem = NULL; + return -ENOMEM; + } + + ukinfo->sq_wrtrk_array = iwqp->kqp.sq_wrid_mem; + ukinfo->rq_wrid_array = iwqp->kqp.rq_wrid_mem; + + size = (ukinfo->sq_depth + ukinfo->rq_depth) * IRDMA_QP_WQE_MIN_SIZE; + size += (IRDMA_SHADOW_AREA_SIZE << 3); + + mem->size = ALIGN(size, 256); + mem->va = dma_alloc_coherent(iwdev->rf->hw.device, mem->size, + &mem->pa, GFP_KERNEL); + if (!mem->va) { + kfree(iwqp->kqp.sq_wrid_mem); + iwqp->kqp.sq_wrid_mem = NULL; + kfree(iwqp->kqp.rq_wrid_mem); + iwqp->kqp.rq_wrid_mem = NULL; + return -ENOMEM; + } + + ukinfo->sq = mem->va; + info->sq_pa = mem->pa; + ukinfo->rq = &ukinfo->sq[ukinfo->sq_depth]; + info->rq_pa = info->sq_pa + (ukinfo->sq_depth * IRDMA_QP_WQE_MIN_SIZE); + ukinfo->shadow_area = ukinfo->rq[ukinfo->rq_depth].elem; + info->shadow_area_pa = info->rq_pa + (ukinfo->rq_depth * IRDMA_QP_WQE_MIN_SIZE); + ukinfo->sq_size = ukinfo->sq_depth >> ukinfo->sq_shift; + ukinfo->rq_size = ukinfo->rq_depth >> ukinfo->rq_shift; + + iwqp->max_send_wr = (ukinfo->sq_depth - IRDMA_SQ_RSVD) >> ukinfo->sq_shift; + iwqp->max_recv_wr = (ukinfo->rq_depth - IRDMA_RQ_RSVD) >> ukinfo->rq_shift; + init_attr->cap.max_send_wr = iwqp->max_send_wr; + init_attr->cap.max_recv_wr = iwqp->max_recv_wr; + + return 0; +} + +int irdma_cqp_create_qp_cmd(struct irdma_qp *iwqp) +{ + struct irdma_pci_f *rf = iwqp->iwdev->rf; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_create_qp_info *qp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + qp_info = &cqp_request->info.in.u.qp_create.info; + memset(qp_info, 0, sizeof(*qp_info)); + qp_info->mac_valid = true; + qp_info->cq_num_valid = true; + qp_info->next_iwarp_state = IRDMA_QP_STATE_IDLE; + + cqp_info->cqp_cmd = IRDMA_OP_QP_CREATE; + cqp_info->post_sq = 1; + cqp_info->in.u.qp_create.qp = &iwqp->sc_qp; + cqp_info->in.u.qp_create.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + + return status; +} + +void irdma_roce_fill_and_set_qpctx_info(struct irdma_qp *iwqp, + struct irdma_qp_host_ctx_info *ctx_info) +{ + struct irdma_device *iwdev = iwqp->iwdev; + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_roce_offload_info *roce_info; + struct irdma_udp_offload_info *udp_info; + + udp_info = &iwqp->udp_info; + udp_info->snd_mss = ib_mtu_enum_to_int(ib_mtu_int_to_enum(iwdev->vsi.mtu)); + udp_info->cwnd = iwdev->roce_cwnd; + udp_info->rexmit_thresh = 2; + udp_info->rnr_nak_thresh = 2; + udp_info->src_port = 0xc000; + udp_info->dst_port = ROCE_V2_UDP_DPORT; + roce_info = &iwqp->roce_info; + ether_addr_copy(roce_info->mac_addr, iwdev->netdev->dev_addr); + + roce_info->rd_en = true; + roce_info->wr_rdresp_en = true; + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) + roce_info->bind_en = true; + roce_info->dcqcn_en = false; + roce_info->rtomin = iwdev->roce_rtomin; + +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + roce_info->dcqcn_en = iwdev->roce_dcqcn_en; + roce_info->timely_en = iwdev->roce_timely_en; + roce_info->dctcp_en = iwdev->roce_dctcp_en; + roce_info->rtomin = iwdev->roce_rtomin; + roce_info->rcv_no_icrc = iwdev->roce_no_icrc_en; +#endif /* IS_ENABLED(CONFIG_CONFIGFS_FS) */ + roce_info->ack_credits = iwdev->roce_ackcreds; + roce_info->ird_size = dev->hw_attrs.max_hw_ird; + roce_info->ord_size = dev->hw_attrs.max_hw_ord; + + if (!iwqp->user_mode) { + roce_info->priv_mode_en = true; + roce_info->fast_reg_en = true; + roce_info->udprivcq_en = true; + } + roce_info->roce_tver = 0; + + ctx_info->roce_info = &iwqp->roce_info; + ctx_info->udp_info = &iwqp->udp_info; + irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info); +} + +void irdma_iw_fill_and_set_qpctx_info(struct irdma_qp *iwqp, + struct irdma_qp_host_ctx_info *ctx_info) +{ + struct irdma_device *iwdev = iwqp->iwdev; + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_iwarp_offload_info *iwarp_info; + + iwarp_info = &iwqp->iwarp_info; + ether_addr_copy(iwarp_info->mac_addr, iwdev->netdev->dev_addr); + iwarp_info->rd_en = true; + iwarp_info->wr_rdresp_en = true; + iwarp_info->ecn_en = true; + iwarp_info->rtomin = 5; +#if IS_ENABLED(CONFIG_CONFIGFS_FS) + iwarp_info->dctcp_en = iwdev->iwarp_dctcp_en; + iwarp_info->timely_en = iwdev->iwarp_timely_en; + iwarp_info->ecn_en = iwdev->iwarp_ecn_en; + iwarp_info->rtomin = iwdev->iwarp_rtomin; + + if (iwarp_info->dctcp_en) + iwarp_info->ecn_en = false; +#endif + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) + iwarp_info->ib_rd_en = true; + if (!iwqp->user_mode) { + iwarp_info->priv_mode_en = true; + iwarp_info->fast_reg_en = true; + } + iwarp_info->ddp_ver = 1; + iwarp_info->rdmap_ver = 1; + + ctx_info->iwarp_info = &iwqp->iwarp_info; + ctx_info->iwarp_info_valid = true; + irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info); + ctx_info->iwarp_info_valid = false; +} + +int irdma_validate_qp_attrs(struct ib_qp_init_attr *init_attr, + struct irdma_device *iwdev) +{ + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_uk_attrs *uk_attrs = &dev->hw_attrs.uk_attrs; + + if (init_attr->create_flags) + return -EOPNOTSUPP; + + if (init_attr->cap.max_inline_data > uk_attrs->max_hw_inline || + init_attr->cap.max_send_sge > uk_attrs->max_hw_wq_frags || + init_attr->cap.max_send_wr > uk_attrs->max_hw_wq_quanta || + init_attr->cap.max_recv_wr > uk_attrs->max_hw_rq_quanta || + init_attr->cap.max_recv_sge > uk_attrs->max_hw_wq_frags) + return -EINVAL; + + if (rdma_protocol_roce(&iwdev->ibdev, 1)) { + if (init_attr->qp_type != IB_QPT_RC && + init_attr->qp_type != IB_QPT_UD && + init_attr->qp_type != IB_QPT_GSI) + return -EOPNOTSUPP; + } else { + if (init_attr->qp_type != IB_QPT_RC) + return -EOPNOTSUPP; + } + + return 0; +} + +void irdma_sched_qp_flush_work(struct irdma_qp *iwqp) +{ + if (iwqp->sc_qp.qp_uk.destroy_pending) + return; + irdma_qp_add_ref(&iwqp->ibqp); + if (mod_delayed_work(iwqp->iwdev->cleanup_wq, &iwqp->dwork_flush, + msecs_to_jiffies(IRDMA_FLUSH_DELAY_MS))) + irdma_qp_rem_ref(&iwqp->ibqp); +} + +void irdma_flush_worker(struct work_struct *work) +{ + struct delayed_work *dwork = to_delayed_work(work); + struct irdma_qp *iwqp = container_of(dwork, struct irdma_qp, dwork_flush); + + irdma_generate_flush_completions(iwqp); + /* For the add in irdma_sched_qp_flush_work */ + irdma_qp_rem_ref(&iwqp->ibqp); +} + +static int irdma_get_ib_acc_flags(struct irdma_qp *iwqp) +{ + int acc_flags = 0; + + if (rdma_protocol_roce(iwqp->ibqp.device, 1)) { + if (iwqp->roce_info.wr_rdresp_en) { + acc_flags |= IB_ACCESS_LOCAL_WRITE; + acc_flags |= IB_ACCESS_REMOTE_WRITE; + } + if (iwqp->roce_info.rd_en) + acc_flags |= IB_ACCESS_REMOTE_READ; + if (iwqp->roce_info.bind_en) + acc_flags |= IB_ACCESS_MW_BIND; + if (iwqp->ctx_info.remote_atomics_en) + acc_flags |= IB_ACCESS_REMOTE_ATOMIC; + } else { + if (iwqp->iwarp_info.wr_rdresp_en) { + acc_flags |= IB_ACCESS_LOCAL_WRITE; + acc_flags |= IB_ACCESS_REMOTE_WRITE; + } + if (iwqp->iwarp_info.rd_en) + acc_flags |= IB_ACCESS_REMOTE_READ; + if (iwqp->ctx_info.remote_atomics_en) + acc_flags |= IB_ACCESS_REMOTE_ATOMIC; + } + return acc_flags; +} + +/** + * irdma_query_qp - query qp attributes + * @ibqp: qp pointer + * @attr: attributes pointer + * @attr_mask: Not used + * @init_attr: qp attributes to return + */ +static int irdma_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, + int attr_mask, struct ib_qp_init_attr *init_attr) +{ + struct irdma_qp *iwqp = to_iwqp(ibqp); + struct irdma_sc_qp *qp = &iwqp->sc_qp; + + memset(attr, 0, sizeof(*attr)); + memset(init_attr, 0, sizeof(*init_attr)); + + attr->qp_state = iwqp->ibqp_state; + attr->cur_qp_state = iwqp->ibqp_state; + attr->cap.max_send_wr = iwqp->max_send_wr; + attr->cap.max_recv_wr = iwqp->max_recv_wr; + attr->cap.max_inline_data = qp->qp_uk.max_inline_data; + attr->cap.max_send_sge = qp->qp_uk.max_sq_frag_cnt; + attr->cap.max_recv_sge = qp->qp_uk.max_rq_frag_cnt; + attr->qp_access_flags = irdma_get_ib_acc_flags(iwqp); + attr->port_num = 1; + if (rdma_protocol_roce(ibqp->device, 1)) { + attr->path_mtu = ib_mtu_int_to_enum(iwqp->udp_info.snd_mss); + attr->qkey = iwqp->roce_info.qkey; + attr->rq_psn = iwqp->udp_info.epsn; + attr->sq_psn = iwqp->udp_info.psn_nxt; + attr->dest_qp_num = iwqp->roce_info.dest_qp; + attr->pkey_index = iwqp->roce_info.p_key; + attr->retry_cnt = iwqp->udp_info.rexmit_thresh; + attr->rnr_retry = iwqp->udp_info.rnr_nak_thresh; + attr->min_rnr_timer = iwqp->udp_info.min_rnr_timer; + attr->max_rd_atomic = iwqp->roce_info.ord_size; + attr->max_dest_rd_atomic = iwqp->roce_info.ird_size; + } + + init_attr->event_handler = iwqp->ibqp.event_handler; + init_attr->qp_context = iwqp->ibqp.qp_context; + init_attr->send_cq = iwqp->ibqp.send_cq; + init_attr->recv_cq = iwqp->ibqp.recv_cq; + init_attr->srq = iwqp->ibqp.srq; + init_attr->cap = attr->cap; + + return 0; +} + +static int irdma_wait_for_suspend(struct irdma_qp *iwqp) +{ + if (!wait_event_timeout(iwqp->iwdev->suspend_wq, + !iwqp->suspend_pending, + msecs_to_jiffies(IRDMA_EVENT_TIMEOUT_MS))) { + iwqp->suspend_pending = false; + ibdev_warn(&iwqp->iwdev->ibdev, + "modify_qp timed out waiting for suspend. qp_id = %d, last_ae = 0x%x\n", + iwqp->ibqp.qp_num, iwqp->last_aeq); + return -EBUSY; + } + + return 0; +} + +/** + * irdma_modify_qp_roce - modify qp request + * @ibqp: qp's pointer for modify + * @attr: access attributes + * @attr_mask: state mask + * @udata: user data + */ +int irdma_modify_qp_roce(struct ib_qp *ibqp, struct ib_qp_attr *attr, + int attr_mask, struct ib_udata *udata) +{ +#define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush) +#define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid) + struct irdma_pd *iwpd = to_iwpd(ibqp->pd); + struct irdma_qp *iwqp = to_iwqp(ibqp); + struct irdma_device *iwdev = iwqp->iwdev; + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_qp_host_ctx_info *ctx_info; + struct irdma_roce_offload_info *roce_info; + struct irdma_udp_offload_info *udp_info; + struct irdma_modify_qp_info info = {}; + struct irdma_modify_qp_resp uresp = {}; + struct irdma_modify_qp_req ureq; + unsigned long flags; + u8 issue_modify_qp = 0; + int ret = 0; + + ctx_info = &iwqp->ctx_info; + roce_info = &iwqp->roce_info; + udp_info = &iwqp->udp_info; + + if (udata) { + if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) || + (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN)) + return -EINVAL; + } + + if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) + return -EOPNOTSUPP; + + if (attr_mask & IB_QP_DEST_QPN) + roce_info->dest_qp = attr->dest_qp_num; + + if (attr_mask & IB_QP_PKEY_INDEX) { + ret = irdma_query_pkey(ibqp->device, 0, attr->pkey_index, + &roce_info->p_key); + if (ret) + return ret; + } + + if (attr_mask & IB_QP_QKEY) + roce_info->qkey = attr->qkey; + + if (attr_mask & IB_QP_PATH_MTU) + udp_info->snd_mss = ib_mtu_enum_to_int(attr->path_mtu); + + if (attr_mask & IB_QP_SQ_PSN) { + udp_info->psn_nxt = attr->sq_psn; + udp_info->lsn = 0xffff; + udp_info->psn_una = attr->sq_psn; + udp_info->psn_max = attr->sq_psn; + } + + if (attr_mask & IB_QP_RQ_PSN) + udp_info->epsn = attr->rq_psn; + + if (attr_mask & IB_QP_RNR_RETRY) + udp_info->rnr_nak_thresh = attr->rnr_retry; + + if (attr_mask & IB_QP_MIN_RNR_TIMER && + dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) + udp_info->min_rnr_timer = attr->min_rnr_timer; + + if (attr_mask & IB_QP_RETRY_CNT) + udp_info->rexmit_thresh = attr->retry_cnt; + + ctx_info->roce_info->pd_id = iwpd->sc_pd.pd_id; + + if (attr_mask & IB_QP_AV) { + struct irdma_av *av = &iwqp->roce_ah.av; + u16 vlan_id = VLAN_N_VID; + u32 local_ip[4] = {}; + + memset(&iwqp->roce_ah, 0, sizeof(iwqp->roce_ah)); + if (attr->ah_attr.ah_flags & IB_AH_GRH) { + udp_info->ttl = attr->ah_attr.grh.hop_limit; + udp_info->flow_label = attr->ah_attr.grh.flow_label; + udp_info->tos = attr->ah_attr.grh.traffic_class; + + udp_info->src_port = kc_rdma_get_udp_sport(udp_info->flow_label, + ibqp->qp_num, + roce_info->dest_qp); + + irdma_qp_rem_qos(&iwqp->sc_qp); + dev->ws_remove(iwqp->sc_qp.vsi, ctx_info->user_pri); + if (iwqp->sc_qp.vsi->dscp_mode) + ctx_info->user_pri = + iwqp->sc_qp.vsi->dscp_map[irdma_tos2dscp(udp_info->tos)]; + else + ctx_info->user_pri = rt_tos2priority(udp_info->tos); + } + ret = kc_irdma_set_roce_cm_info(iwqp, attr, &vlan_id); + if (ret) + return ret; + if (dev->ws_add(iwqp->sc_qp.vsi, ctx_info->user_pri)) + return -ENOMEM; + iwqp->sc_qp.user_pri = ctx_info->user_pri; + irdma_qp_add_qos(&iwqp->sc_qp); + + if (vlan_id >= VLAN_N_VID && iwdev->dcb_vlan_mode) + vlan_id = 0; + if (vlan_id < VLAN_N_VID) { + udp_info->insert_vlan_tag = true; + udp_info->vlan_tag = vlan_id | + ctx_info->user_pri << VLAN_PRIO_SHIFT; + } else { + udp_info->insert_vlan_tag = false; + } + + av->attrs = attr->ah_attr; + rdma_gid2ip((struct sockaddr *)&av->dgid_addr, &attr->ah_attr.grh.dgid); + if (av->net_type == RDMA_NETWORK_IPV6) { + __be32 *daddr = + av->dgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32; + __be32 *saddr = + av->sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32; + + irdma_copy_ip_ntohl(&udp_info->dest_ip_addr[0], daddr); + irdma_copy_ip_ntohl(&udp_info->local_ipaddr[0], saddr); + + udp_info->ipv4 = false; + irdma_copy_ip_ntohl(local_ip, daddr); + } else if (av->net_type == RDMA_NETWORK_IPV4) { + __be32 saddr = av->sgid_addr.saddr_in.sin_addr.s_addr; + __be32 daddr = av->dgid_addr.saddr_in.sin_addr.s_addr; + + local_ip[0] = ntohl(daddr); + + udp_info->ipv4 = true; + udp_info->dest_ip_addr[0] = 0; + udp_info->dest_ip_addr[1] = 0; + udp_info->dest_ip_addr[2] = 0; + udp_info->dest_ip_addr[3] = local_ip[0]; + + udp_info->local_ipaddr[0] = 0; + udp_info->local_ipaddr[1] = 0; + udp_info->local_ipaddr[2] = 0; + udp_info->local_ipaddr[3] = ntohl(saddr); + } else { + return -EINVAL; + } + udp_info->arp_idx = + irdma_add_arp(iwdev->rf, local_ip, + ah_attr_to_dmac(attr->ah_attr)); + } + + if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) { + if (attr->max_rd_atomic > dev->hw_attrs.max_hw_ord) { + ibdev_err(&iwdev->ibdev, + "rd_atomic = %d, above max_hw_ord=%d\n", + attr->max_rd_atomic, + dev->hw_attrs.max_hw_ord); + return -EINVAL; + } + if (attr->max_rd_atomic) + roce_info->ord_size = attr->max_rd_atomic; + info.ord_valid = true; + } + + if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) { + if (attr->max_dest_rd_atomic > dev->hw_attrs.max_hw_ird) { + ibdev_err(&iwdev->ibdev, + "rd_atomic = %d, above max_hw_ird=%d\n", + attr->max_rd_atomic, + dev->hw_attrs.max_hw_ird); + return -EINVAL; + } + if (attr->max_dest_rd_atomic) + roce_info->ird_size = attr->max_dest_rd_atomic; + } + + if (attr_mask & IB_QP_ACCESS_FLAGS) { + if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE) + roce_info->wr_rdresp_en = true; + if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) + roce_info->wr_rdresp_en = true; + if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) + roce_info->rd_en = true; + if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) + ctx_info->remote_atomics_en = true; + } + + wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend)); + + ibdev_dbg(&iwdev->ibdev, + "VERBS: caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d attr_mask=0x%x\n", + __builtin_return_address(0), ibqp->qp_num, attr->qp_state, + iwqp->ibqp_state, iwqp->iwarp_state, attr_mask); + + spin_lock_irqsave(&iwqp->lock, flags); + if (attr_mask & IB_QP_STATE) { + if (!kc_ib_modify_qp_is_ok(iwqp->ibqp_state, attr->qp_state, + iwqp->ibqp.qp_type, attr_mask, + IB_LINK_LAYER_ETHERNET)) { + ibdev_warn(&iwdev->ibdev, "modify_qp invalid for qp_id=%d, old_state=0x%x, new_state=0x%x\n", + iwqp->ibqp.qp_num, iwqp->ibqp_state, + attr->qp_state); + ret = -EINVAL; + goto exit; + } + info.curr_iwarp_state = iwqp->iwarp_state; + + switch (attr->qp_state) { + case IB_QPS_INIT: + if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) { + ret = -EINVAL; + goto exit; + } + + if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) { + info.next_iwarp_state = IRDMA_QP_STATE_IDLE; + issue_modify_qp = 1; + } + break; + case IB_QPS_RTR: + if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) { + ret = -EINVAL; + goto exit; + } + info.arp_cache_idx_valid = true; + info.cq_num_valid = true; + info.next_iwarp_state = IRDMA_QP_STATE_RTR; + issue_modify_qp = 1; + break; + case IB_QPS_RTS: + if (iwqp->ibqp_state < IB_QPS_RTR || + iwqp->ibqp_state == IB_QPS_ERR) { + ret = -EINVAL; + goto exit; + } + + info.arp_cache_idx_valid = true; + info.cq_num_valid = true; + info.ord_valid = true; + info.next_iwarp_state = IRDMA_QP_STATE_RTS; + issue_modify_qp = 1; + if (dev->hw_attrs.uk_attrs.hw_rev == IRDMA_GEN_2 && + dev->privileged) + iwdev->rf->check_fc(&iwdev->vsi, &iwqp->sc_qp); + udp_info->cwnd = iwdev->roce_cwnd; + roce_info->ack_credits = iwdev->roce_ackcreds; + if (iwdev->push_mode && udata && + iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { + spin_unlock_irqrestore(&iwqp->lock, flags); + irdma_alloc_push_page(iwqp); + spin_lock_irqsave(&iwqp->lock, flags); + } + break; + case IB_QPS_SQD: + if (iwqp->iwarp_state == IRDMA_QP_STATE_SQD) + goto exit; + + if (iwqp->iwarp_state != IRDMA_QP_STATE_RTS) { + ret = -EINVAL; + goto exit; + } + + info.next_iwarp_state = IRDMA_QP_STATE_SQD; + issue_modify_qp = 1; + iwqp->suspend_pending = true; + break; + case IB_QPS_SQE: + case IB_QPS_ERR: + case IB_QPS_RESET: + if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) { + spin_unlock_irqrestore(&iwqp->lock, flags); + if (udata && udata->inlen) { + if (ib_copy_from_udata(&ureq, udata, + min(sizeof(ureq), udata->inlen))) + return -EINVAL; + + irdma_flush_wqes(iwqp, + (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) | + (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) | + IRDMA_REFLUSH); + } + return 0; + } + + info.next_iwarp_state = IRDMA_QP_STATE_ERROR; + issue_modify_qp = 1; + break; + default: + ret = -EINVAL; + goto exit; + } + + iwqp->ibqp_state = attr->qp_state; + } + + ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id; + ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id; + irdma_sc_qp_setctx_roce(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info); + spin_unlock_irqrestore(&iwqp->lock, flags); + + if (attr_mask & IB_QP_STATE) { + if (issue_modify_qp) { + ctx_info->rem_endpoint_idx = udp_info->arp_idx; + if (irdma_hw_modify_qp(iwdev, iwqp, &info, true)) + return -EINVAL; + if (info.next_iwarp_state == IRDMA_QP_STATE_SQD) { + ret = irdma_wait_for_suspend(iwqp); + if (ret) + return ret; + } + spin_lock_irqsave(&iwqp->lock, flags); + if (iwqp->iwarp_state == info.curr_iwarp_state) { + iwqp->iwarp_state = info.next_iwarp_state; + iwqp->ibqp_state = attr->qp_state; + } + if (iwqp->ibqp_state > IB_QPS_RTS && + !iwqp->flush_issued) { + spin_unlock_irqrestore(&iwqp->lock, flags); + irdma_flush_wqes(iwqp, IRDMA_FLUSH_SQ | + IRDMA_FLUSH_RQ | + IRDMA_FLUSH_WAIT); + iwqp->flush_issued = 1; + + } else { + spin_unlock_irqrestore(&iwqp->lock, flags); + } + } else { + iwqp->ibqp_state = attr->qp_state; + } + if (udata && udata->outlen && dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + struct irdma_ucontext *ucontext; + + ucontext = kc_rdma_udata_to_drv_context(ibqp, udata); + if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX && + !iwqp->push_wqe_mmap_entry && + !irdma_setup_push_mmap_entries(ucontext, iwqp, + &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) { + uresp.push_valid = 1; + uresp.push_offset = iwqp->sc_qp.push_offset; + } + uresp.rd_fence_rate = iwdev->rd_fence_rate; + ret = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), + udata->outlen)); + if (ret) { + irdma_remove_push_mmap_entries(iwqp); + ibdev_dbg(&iwdev->ibdev, + "VERBS: copy_to_udata failed\n"); + return ret; + } + } + } + + return 0; +exit: + spin_unlock_irqrestore(&iwqp->lock, flags); + + return ret; +} + +/** + * irdma_modify_qp - modify qp request + * @ibqp: qp's pointer for modify + * @attr: access attributes + * @attr_mask: state mask + * @udata: user data + */ +int irdma_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr, int attr_mask, + struct ib_udata *udata) +{ +#define IRDMA_MODIFY_QP_MIN_REQ_LEN offsetofend(struct irdma_modify_qp_req, rq_flush) +#define IRDMA_MODIFY_QP_MIN_RESP_LEN offsetofend(struct irdma_modify_qp_resp, push_valid) + struct irdma_qp *iwqp = to_iwqp(ibqp); + struct irdma_device *iwdev = iwqp->iwdev; + struct irdma_sc_dev *dev = &iwdev->rf->sc_dev; + struct irdma_qp_host_ctx_info *ctx_info; + struct irdma_tcp_offload_info *tcp_info; + struct irdma_iwarp_offload_info *offload_info; + struct irdma_modify_qp_info info = {}; + struct irdma_modify_qp_resp uresp = {}; + struct irdma_modify_qp_req ureq = {}; + u8 issue_modify_qp = 0; + u8 dont_wait = 0; + int err; + unsigned long flags; + + if (udata) { + if ((udata->inlen && udata->inlen < IRDMA_MODIFY_QP_MIN_REQ_LEN) || + (udata->outlen && udata->outlen < IRDMA_MODIFY_QP_MIN_RESP_LEN)) + return -EINVAL; + } + + if (attr_mask & ~IB_QP_ATTR_STANDARD_BITS) + return -EOPNOTSUPP; + + ctx_info = &iwqp->ctx_info; + offload_info = &iwqp->iwarp_info; + tcp_info = &iwqp->tcp_info; + wait_event(iwqp->mod_qp_waitq, !atomic_read(&iwqp->hw_mod_qp_pend)); + ibdev_dbg(&iwdev->ibdev, + "VERBS: caller: %pS qp_id=%d to_ibqpstate=%d ibqpstate=%d irdma_qpstate=%d last_aeq=%d hw_tcp_state=%d hw_iwarp_state=%d attr_mask=0x%x\n", + __builtin_return_address(0), ibqp->qp_num, attr->qp_state, + iwqp->ibqp_state, iwqp->iwarp_state, iwqp->last_aeq, + iwqp->hw_tcp_state, iwqp->hw_iwarp_state, attr_mask); + + spin_lock_irqsave(&iwqp->lock, flags); + if (attr_mask & IB_QP_STATE) { + info.curr_iwarp_state = iwqp->iwarp_state; + switch (attr->qp_state) { + case IB_QPS_INIT: + case IB_QPS_RTR: + if (iwqp->iwarp_state > IRDMA_QP_STATE_IDLE) { + err = -EINVAL; + goto exit; + } + + if (iwqp->iwarp_state == IRDMA_QP_STATE_INVALID) { + info.next_iwarp_state = IRDMA_QP_STATE_IDLE; + issue_modify_qp = 1; + } + if (iwdev->push_mode && udata && + iwqp->sc_qp.push_idx == IRDMA_INVALID_PUSH_PAGE_INDEX) { + spin_unlock_irqrestore(&iwqp->lock, flags); + irdma_alloc_push_page(iwqp); + spin_lock_irqsave(&iwqp->lock, flags); + } + break; + case IB_QPS_RTS: + if (iwqp->iwarp_state > IRDMA_QP_STATE_RTS || + !iwqp->cm_id) { + err = -EINVAL; + goto exit; + } + + issue_modify_qp = 1; + iwqp->hw_tcp_state = IRDMA_TCP_STATE_ESTABLISHED; + iwqp->hte_added = 1; + info.next_iwarp_state = IRDMA_QP_STATE_RTS; + info.tcp_ctx_valid = true; + info.ord_valid = true; + info.arp_cache_idx_valid = true; + info.cq_num_valid = true; + break; + case IB_QPS_SQD: + if (iwqp->hw_iwarp_state > IRDMA_QP_STATE_RTS) { + err = 0; + goto exit; + } + + if (iwqp->iwarp_state == IRDMA_QP_STATE_CLOSING || + iwqp->iwarp_state < IRDMA_QP_STATE_RTS) { + err = 0; + goto exit; + } + + if (iwqp->iwarp_state > IRDMA_QP_STATE_CLOSING) { + err = -EINVAL; + goto exit; + } + + info.next_iwarp_state = IRDMA_QP_STATE_CLOSING; + issue_modify_qp = 1; + break; + case IB_QPS_SQE: + if (iwqp->iwarp_state >= IRDMA_QP_STATE_TERMINATE) { + err = -EINVAL; + goto exit; + } + + info.next_iwarp_state = IRDMA_QP_STATE_TERMINATE; + issue_modify_qp = 1; + break; + case IB_QPS_ERR: + case IB_QPS_RESET: + if (iwqp->iwarp_state == IRDMA_QP_STATE_ERROR) { + spin_unlock_irqrestore(&iwqp->lock, flags); + if (udata && udata->inlen) { + if (ib_copy_from_udata(&ureq, udata, + min(sizeof(ureq), udata->inlen))) + return -EINVAL; + + irdma_flush_wqes(iwqp, + (ureq.sq_flush ? IRDMA_FLUSH_SQ : 0) | + (ureq.rq_flush ? IRDMA_FLUSH_RQ : 0) | + IRDMA_REFLUSH); + } + return 0; + } + + if (iwqp->sc_qp.term_flags) { + spin_unlock_irqrestore(&iwqp->lock, flags); + irdma_terminate_del_timer(&iwqp->sc_qp); + spin_lock_irqsave(&iwqp->lock, flags); + } + info.next_iwarp_state = IRDMA_QP_STATE_ERROR; + if (iwqp->hw_tcp_state > IRDMA_TCP_STATE_CLOSED && + iwdev->iw_status && + iwqp->hw_tcp_state != IRDMA_TCP_STATE_TIME_WAIT) + info.reset_tcp_conn = true; + else + dont_wait = 1; + + issue_modify_qp = 1; + info.next_iwarp_state = IRDMA_QP_STATE_ERROR; + break; + default: + err = -EINVAL; + goto exit; + } + + iwqp->ibqp_state = attr->qp_state; + } + if (attr_mask & IB_QP_ACCESS_FLAGS) { + ctx_info->iwarp_info_valid = true; + if (attr->qp_access_flags & IB_ACCESS_LOCAL_WRITE) + offload_info->wr_rdresp_en = true; + if (attr->qp_access_flags & IB_ACCESS_REMOTE_WRITE) + offload_info->wr_rdresp_en = true; + if (attr->qp_access_flags & IB_ACCESS_REMOTE_READ) + offload_info->rd_en = true; + if (attr->qp_access_flags & IB_ACCESS_REMOTE_ATOMIC) + ctx_info->remote_atomics_en = true; + } + + if (ctx_info->iwarp_info_valid) { + ctx_info->send_cq_num = iwqp->iwscq->sc_cq.cq_uk.cq_id; + ctx_info->rcv_cq_num = iwqp->iwrcq->sc_cq.cq_uk.cq_id; + irdma_sc_qp_setctx(&iwqp->sc_qp, iwqp->host_ctx.va, ctx_info); + } + spin_unlock_irqrestore(&iwqp->lock, flags); + + if (attr_mask & IB_QP_STATE) { + if (issue_modify_qp) { + ctx_info->rem_endpoint_idx = tcp_info->arp_idx; + if (irdma_hw_modify_qp(iwdev, iwqp, &info, true)) + return -EINVAL; + } + + spin_lock_irqsave(&iwqp->lock, flags); + if (iwqp->iwarp_state == info.curr_iwarp_state) { + iwqp->iwarp_state = info.next_iwarp_state; + iwqp->ibqp_state = attr->qp_state; + } + spin_unlock_irqrestore(&iwqp->lock, flags); + } + + if (issue_modify_qp && iwqp->ibqp_state > IB_QPS_RTS) { + if (dont_wait) { + if (iwqp->hw_tcp_state) { + spin_lock_irqsave(&iwqp->lock, flags); + iwqp->hw_tcp_state = IRDMA_TCP_STATE_CLOSED; + iwqp->last_aeq = IRDMA_AE_RESET_SENT; + spin_unlock_irqrestore(&iwqp->lock, flags); + } + irdma_cm_disconn(iwqp); + } else { + int close_timer_started; + + spin_lock_irqsave(&iwdev->cm_core.ht_lock, flags); + + if (iwqp->cm_node) { + refcount_inc(&iwqp->cm_node->refcnt); + spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags); + close_timer_started = atomic_inc_return(&iwqp->close_timer_started); + if (iwqp->cm_id && close_timer_started == 1) + irdma_schedule_cm_timer(iwqp->cm_node, + (struct irdma_puda_buf *)iwqp, + IRDMA_TIMER_TYPE_CLOSE, 1, 0); + + irdma_rem_ref_cm_node(iwqp->cm_node); + } else { + spin_unlock_irqrestore(&iwdev->cm_core.ht_lock, flags); + } + } + } + if (attr_mask & IB_QP_STATE && udata && udata->outlen && + dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) { + struct irdma_ucontext *ucontext; + + ucontext = kc_rdma_udata_to_drv_context(ibqp, udata); + if (iwqp->sc_qp.push_idx != IRDMA_INVALID_PUSH_PAGE_INDEX && + !iwqp->push_wqe_mmap_entry && + !irdma_setup_push_mmap_entries(ucontext, iwqp, + &uresp.push_wqe_mmap_key, &uresp.push_db_mmap_key)) { + uresp.push_valid = 1; + uresp.push_offset = iwqp->sc_qp.push_offset; + } + uresp.rd_fence_rate = iwdev->rd_fence_rate; + + err = ib_copy_to_udata(udata, &uresp, min(sizeof(uresp), + udata->outlen)); + if (err) { + irdma_remove_push_mmap_entries(iwqp); + ibdev_dbg(&iwdev->ibdev, + "VERBS: copy_to_udata failed\n"); + return err; + } + } + + return 0; +exit: + spin_unlock_irqrestore(&iwqp->lock, flags); + + return err; +} + +/** + * irdma_srq_free_rsrc - free up resources for srq + * @rf: RDMA PCI function + * @iwsrq: srq ptr + */ +void irdma_srq_free_rsrc(struct irdma_pci_f *rf, struct irdma_srq *iwsrq) +{ + struct irdma_sc_srq *srq = &iwsrq->sc_srq; + + if (!iwsrq->user_mode) { + dma_free_coherent(rf->sc_dev.hw->device, iwsrq->kmem.size, + iwsrq->kmem.va, iwsrq->kmem.pa); + iwsrq->kmem.va = NULL; + } + + irdma_free_rsrc(rf, rf->allocated_srqs, srq->srq_uk.srq_id); +} + +/** + * irdma_cq_free_rsrc - free up resources for cq + * @rf: RDMA PCI function + * @iwcq: cq ptr + */ +void irdma_cq_free_rsrc(struct irdma_pci_f *rf, struct irdma_cq *iwcq) +{ + struct irdma_sc_cq *cq = &iwcq->sc_cq; + + if (!iwcq->user_mode) { + dma_free_coherent(rf->sc_dev.hw->device, iwcq->kmem.size, + iwcq->kmem.va, iwcq->kmem.pa); + iwcq->kmem.va = NULL; + dma_free_coherent(rf->sc_dev.hw->device, + iwcq->kmem_shadow.size, + iwcq->kmem_shadow.va, iwcq->kmem_shadow.pa); + iwcq->kmem_shadow.va = NULL; + } + + irdma_free_rsrc(rf, rf->allocated_cqs, cq->cq_uk.cq_id); +} + +/** + * irdma_free_cqbuf - worker to free a cq buffer + * @work: provides access to the cq buffer to free + */ +static void irdma_free_cqbuf(struct work_struct *work) +{ + struct irdma_cq_buf *cq_buf = container_of(work, struct irdma_cq_buf, work); + + dma_free_coherent(cq_buf->hw->device, cq_buf->kmem_buf.size, + cq_buf->kmem_buf.va, cq_buf->kmem_buf.pa); + cq_buf->kmem_buf.va = NULL; + kfree(cq_buf); +} + +/** + * irdma_process_resize_list - remove resized cq buffers from the resize_list + * @iwcq: cq which owns the resize_list + * @iwdev: irdma device + * @lcqe_buf: the buffer where the last cqe is received + */ +int irdma_process_resize_list(struct irdma_cq *iwcq, + struct irdma_device *iwdev, + struct irdma_cq_buf *lcqe_buf) +{ + struct list_head *tmp_node, *list_node; + struct irdma_cq_buf *cq_buf; + int cnt = 0; + + list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) { + cq_buf = list_entry(list_node, struct irdma_cq_buf, list); + if (cq_buf == lcqe_buf) + return cnt; + + list_del(&cq_buf->list); + queue_work(iwdev->cleanup_wq, &cq_buf->work); + cnt++; + } + + return cnt; +} + +/** + * irdma_resize_cq - resize cq + * @ibcq: cq to be resized + * @entries: desired cq size + * @udata: user data + */ +static int irdma_resize_cq(struct ib_cq *ibcq, int entries, + struct ib_udata *udata) +{ +#define IRDMA_RESIZE_CQ_MIN_REQ_LEN offsetofend(struct irdma_resize_cq_req, user_cq_buffer) + struct irdma_cq *iwcq = to_iwcq(ibcq); + struct irdma_sc_dev *dev = iwcq->sc_cq.dev; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_modify_cq_info *m_info; + struct irdma_modify_cq_info info = {}; + struct irdma_dma_mem kmem_buf; + struct irdma_cq_mr *cqmr_buf; + struct irdma_pbl *iwpbl_buf; + struct irdma_device *iwdev; + struct irdma_pci_f *rf; + struct irdma_cq_buf *cq_buf = NULL; + unsigned long flags; + int ret; + + iwdev = to_iwdev(ibcq->device); + rf = iwdev->rf; + + if (!(rf->sc_dev.hw_attrs.uk_attrs.feature_flags & + IRDMA_FEATURE_CQ_RESIZE)) + return -EOPNOTSUPP; + + if (udata && udata->inlen < IRDMA_RESIZE_CQ_MIN_REQ_LEN) + return -EINVAL; + + if (entries > rf->max_cqe) + return -EINVAL; + + if (!iwcq->user_mode) { + entries++; + if (rf->sc_dev.hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_2) + entries *= 2; + } + + info.cq_size = max(entries, 4); + + if (info.cq_size == iwcq->sc_cq.cq_uk.cq_size - 1) + return 0; + + if (udata) { + struct irdma_resize_cq_req req = {}; + struct irdma_ucontext *ucontext = + kc_rdma_udata_to_drv_context(ibcq, udata); + + /* CQ resize not supported with legacy GEN_1 libi40iw */ + if (ucontext->legacy_mode) + return -EOPNOTSUPP; + + if (ib_copy_from_udata(&req, udata, + min(sizeof(req), udata->inlen))) + return -EINVAL; + + spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); + iwpbl_buf = irdma_get_pbl((unsigned long)req.user_cq_buffer, + &ucontext->cq_reg_mem_list); + spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); + + if (!iwpbl_buf) + return -ENOMEM; + + cqmr_buf = &iwpbl_buf->cq_mr; + if (iwpbl_buf->pbl_allocated) { + info.virtual_map = true; + info.pbl_chunk_size = 1; + info.first_pm_pbl_idx = cqmr_buf->cq_pbl.idx; + } else { + info.cq_pa = cqmr_buf->cq_pbl.addr; + } + } else { + /* Kmode CQ resize */ + int rsize; + + rsize = info.cq_size * sizeof(struct irdma_cqe); + kmem_buf.size = ALIGN(round_up(rsize, 256), 256); + kmem_buf.va = dma_alloc_coherent(dev->hw->device, + kmem_buf.size, &kmem_buf.pa, + GFP_KERNEL); + if (!kmem_buf.va) + return -ENOMEM; + + info.cq_base = kmem_buf.va; + info.cq_pa = kmem_buf.pa; + cq_buf = kzalloc(sizeof(*cq_buf), GFP_KERNEL); + if (!cq_buf) { + ret = -ENOMEM; + goto error; + } + } + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) { + ret = -ENOMEM; + goto error; + } + + info.shadow_read_threshold = iwcq->sc_cq.shadow_read_threshold; + info.cq_resize = true; + + cqp_info = &cqp_request->info; + m_info = &cqp_info->in.u.cq_modify.info; + memcpy(m_info, &info, sizeof(*m_info)); + + cqp_info->cqp_cmd = IRDMA_OP_CQ_MODIFY; + cqp_info->in.u.cq_modify.cq = &iwcq->sc_cq; + cqp_info->in.u.cq_modify.scratch = (uintptr_t)cqp_request; + cqp_info->post_sq = 1; + ret = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + if (ret) + goto error; + + spin_lock_irqsave(&iwcq->lock, flags); + if (cq_buf) { + cq_buf->kmem_buf = iwcq->kmem; + cq_buf->hw = dev->hw; + memcpy(&cq_buf->cq_uk, &iwcq->sc_cq.cq_uk, sizeof(cq_buf->cq_uk)); + INIT_WORK(&cq_buf->work, irdma_free_cqbuf); + list_add_tail(&cq_buf->list, &iwcq->resize_list); + iwcq->kmem = kmem_buf; + } + + irdma_sc_cq_resize(&iwcq->sc_cq, &info); + ibcq->cqe = info.cq_size - 1; + spin_unlock_irqrestore(&iwcq->lock, flags); + + return 0; +error: + if (!udata) { + dma_free_coherent(dev->hw->device, kmem_buf.size, kmem_buf.va, + kmem_buf.pa); + kmem_buf.va = NULL; + } + kfree(cq_buf); + + return ret; +} + +/** + * irdma_srq_event - event notification for srq limit + * @srq: shared srq struct + */ +void irdma_srq_event(struct irdma_sc_srq *srq) +{ + struct irdma_srq *iwsrq = container_of(srq, struct irdma_srq, sc_srq); + struct ib_srq *ibsrq = &iwsrq->ibsrq; + struct ib_event event; + + srq->srq_limit = 0; + + if (!ibsrq->event_handler) + return; + + event.device = ibsrq->device; + event.element.port_num = 1; + event.element.srq = ibsrq; + event.event = IB_EVENT_SRQ_LIMIT_REACHED; + ibsrq->event_handler(&event, ibsrq->srq_context); +} + +/** + * irdma_modify_srq - modify srq request + * @ibsrq: srq's pointer for modify + * @attr: access attributes + * @attr_mask: state mask + * @udata: user data + */ +static int irdma_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr, + enum ib_srq_attr_mask attr_mask, + struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ibsrq->device); + struct irdma_srq *iwsrq = to_iwsrq(ibsrq); + struct irdma_cqp_request *cqp_request; + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_modify_srq_info *info; + struct cqp_cmds_info *cqp_info; + int status; + + if (attr_mask & IB_SRQ_MAX_WR) + return -EINVAL; + + if (!(attr_mask & IB_SRQ_LIMIT)) + return 0; + + if (attr->srq_limit > iwsrq->sc_srq.srq_uk.srq_size) + return -EINVAL; + + /* Execute this cqp op synchronously, so we can update srq_limit + * upon successful completion. + */ + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + info = &cqp_info->in.u.srq_modify.info; + info->srq_limit = attr->srq_limit; + if (info->srq_limit > 0xFFF) + info->srq_limit = 0xFFF; + info->arm_limit_event = 1; + + cqp_info->cqp_cmd = IRDMA_OP_SRQ_MODIFY; + cqp_info->post_sq = 1; + cqp_info->in.u.srq_modify.srq = &iwsrq->sc_srq; + cqp_info->in.u.srq_modify.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + if (status) + return status; + + iwsrq->sc_srq.srq_limit = info->srq_limit; + + return 0; +} + +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) || defined(RHEL_8_2) || defined(RHEL_8_3) || defined(RHEL_8_4) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) +static int irdma_setup_umode_srq(struct irdma_device *iwdev, + struct irdma_srq *iwsrq, + struct irdma_srq_init_info *info, + struct ib_udata *udata) +#else +static int irdma_setup_umode_srq(struct irdma_device *iwdev, + struct irdma_srq *iwsrq, + struct irdma_srq_init_info *info, + struct ib_pd *pd, + struct ib_udata *udata) +#endif +{ +#define IRDMA_CREATE_SRQ_MIN_REQ_LEN offsetofend(struct irdma_create_srq_req, user_shadow_area) + struct irdma_create_srq_req req = {}; + struct irdma_ucontext *ucontext; + struct irdma_srq_mr *srqmr; + struct irdma_pbl *iwpbl; + unsigned long flags; +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) && !defined(RHEL_8_2) && !defined(RHEL_8_3) && !defined(RHEL_8_4) && !defined(RHEL_8_5) && !defined(RHEL_8_6) && !defined(RHEL_8_7) && !defined(RHEL_8_8) + struct ib_ucontext *context; +#endif + + iwsrq->user_mode = true; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) || defined(RHEL_8_2) || defined(RHEL_8_3) || defined(RHEL_8_4) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) + ucontext = rdma_udata_to_drv_context(udata, struct irdma_ucontext, + ibucontext); +#else + context = pd->uobject ? pd->uobject->context : NULL; + ucontext = kc_get_ucontext(udata); +#endif + + if (udata->inlen < IRDMA_CREATE_SRQ_MIN_REQ_LEN) + return -EINVAL; + + if (ib_copy_from_udata(&req, udata, + min(sizeof(req), udata->inlen))) + return -EFAULT; + + spin_lock_irqsave(&ucontext->srq_reg_mem_list_lock, flags); + iwpbl = irdma_get_pbl((unsigned long)req.user_srq_buf, + &ucontext->srq_reg_mem_list); + spin_unlock_irqrestore(&ucontext->srq_reg_mem_list_lock, flags); + if (!iwpbl) + return -EPROTO; + + iwsrq->iwpbl = iwpbl; + srqmr = &iwpbl->srq_mr; + + if (iwpbl->pbl_allocated) { + info->virtual_map = true; + info->pbl_chunk_size = 1; + info->first_pm_pbl_idx = srqmr->srq_pbl.idx; + info->leaf_pbl_size = 1; + } else { + info->srq_pa = srqmr->srq_pbl.addr; + } + info->shadow_area_pa = srqmr->shadow; + + return 0; +} + +static int irdma_setup_kmode_srq(struct irdma_device *iwdev, + struct irdma_srq *iwsrq, + struct irdma_srq_init_info *info, u32 depth, + u8 shift) +{ + struct irdma_srq_uk_init_info *ukinfo = &info->srq_uk_init_info; + struct irdma_dma_mem *mem = &iwsrq->kmem; + u32 size, ring_size; + + ring_size = depth * IRDMA_QP_WQE_MIN_SIZE; + size = ring_size + (IRDMA_SHADOW_AREA_SIZE << 3); + + mem->size = ALIGN(size, 256); + mem->va = dma_alloc_coherent(iwdev->rf->hw.device, mem->size, + &mem->pa, GFP_KERNEL); + if (!mem->va) + return -ENOMEM; + + ukinfo->srq = mem->va; + ukinfo->srq_size = depth >> shift; + ukinfo->shadow_area = mem->va + ring_size; + + info->shadow_area_pa = info->srq_pa + ring_size; + info->srq_pa = mem->pa; + + return 0; +} + +/** + * irdma_create_srq - create srq + * @ibsrq: ib's srq pointer + * @initattrs: attributes for srq + * @udata: user data for create srq + */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) || defined(RHEL_8_2) || defined(RHEL_8_3) || defined(RHEL_8_4) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) +static int irdma_create_srq(struct ib_srq *ibsrq, + struct ib_srq_init_attr *initattrs, + struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ibsrq->device); + struct ib_srq_attr *attr = &initattrs->attr; + struct irdma_pd *iwpd = to_iwpd(ibsrq->pd); + struct irdma_srq *iwsrq = to_iwsrq(ibsrq); +#else +static struct ib_srq *irdma_create_srq(struct ib_pd *ibpd, + struct ib_srq_init_attr *initattrs, + struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(ibpd->device); + struct ib_srq_attr *attr = &initattrs->attr; + struct irdma_pd *iwpd = to_iwpd(ibpd); + struct irdma_srq *iwsrq; +#endif + struct irdma_srq_uk_init_info *ukinfo; + struct irdma_cqp_request *cqp_request; + struct irdma_srq_init_info info = {}; + struct irdma_pci_f *rf = iwdev->rf; + struct irdma_uk_attrs *uk_attrs; + struct cqp_cmds_info *cqp_info; + int err_code = 0; + u32 depth; + u8 shift; + + uk_attrs = &rf->sc_dev.hw_attrs.uk_attrs; + ukinfo = &info.srq_uk_init_info; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) && !defined(RHEL_8_2) && !defined(RHEL_8_3) && !defined(RHEL_8_4) && !defined(RHEL_8_5) && !defined(RHEL_8_6) && !defined(RHEL_8_7) && !defined(RHEL_8_8) + if (initattrs->srq_type != IB_SRQT_BASIC) + return ERR_PTR(-EOPNOTSUPP); + + iwsrq = kzalloc(sizeof(*iwsrq), GFP_KERNEL); + if (!iwsrq) + return ERR_PTR(-ENOMEM); +#else + if (initattrs->srq_type != IB_SRQT_BASIC) + return -EOPNOTSUPP; +#endif +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) || defined(RHEL_8_2) || defined(RHEL_8_3) || defined(RHEL_8_4) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) + if (!(uk_attrs->feature_flags & IRDMA_FEATURE_SRQ) || + attr->max_sge > uk_attrs->max_hw_wq_frags) + return -EINVAL; +#else + if (!(uk_attrs->feature_flags & IRDMA_FEATURE_SRQ) || + attr->max_sge > uk_attrs->max_hw_wq_frags) { + err_code = -EINVAL; + goto error; + } +#endif + + iwsrq->sg_list = kcalloc(uk_attrs->max_hw_wq_frags, sizeof(*iwsrq->sg_list), + GFP_KERNEL); + if (!iwsrq->sg_list) { +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) && !defined(RHEL_8_2) && !defined(RHEL_8_3) && !defined(RHEL_8_4) && !defined(RHEL_8_5) && !defined(RHEL_8_6) && !defined(RHEL_8_7) && !defined(RHEL_8_8) + err_code = -ENOMEM; + goto error; +#else + return -ENOMEM; +#endif + } + + refcount_set(&iwsrq->refcnt, 1); + spin_lock_init(&iwsrq->lock); + err_code = irdma_alloc_rsrc(rf, rf->allocated_srqs, rf->max_srq, + &iwsrq->srq_num, &rf->next_srq); + if (err_code) + goto free_sg_list; + + ukinfo->max_srq_frag_cnt = attr->max_sge; + ukinfo->uk_attrs = uk_attrs; + ukinfo->srq_id = iwsrq->srq_num; + + irdma_get_wqe_shift(ukinfo->uk_attrs, ukinfo->max_srq_frag_cnt, 0, + &shift); + + err_code = irdma_get_srqdepth(ukinfo->uk_attrs, attr->max_wr, shift, &depth); + if (err_code) + goto free_sg_list; + + /* Actual SRQ size in WRs for ring and HW */ + ukinfo->srq_size = depth >> shift; + + /* Max postable WRs to SRQ */ + iwsrq->max_wr = (depth - IRDMA_RQ_RSVD) >> shift; + attr->max_wr = iwsrq->max_wr; + + if (udata) +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) && !defined(RHEL_8_2) && !defined(RHEL_8_3) && !defined(RHEL_8_4) && !defined(RHEL_8_5) && !defined(RHEL_8_6) && !defined(RHEL_8_7) && !defined(RHEL_8_8) + err_code = irdma_setup_umode_srq(iwdev, iwsrq, &info, ibpd, udata); +#else + err_code = irdma_setup_umode_srq(iwdev, iwsrq, &info, udata); +#endif + else + err_code = irdma_setup_kmode_srq(iwdev, iwsrq, &info, depth, shift); + + if (err_code) + goto free_rsrc; + + info.vsi = &iwdev->vsi; + info.pd = &iwpd->sc_pd; + + err_code = irdma_sc_srq_init(&iwsrq->sc_srq, &info); + if (err_code) + goto free_dmem; + + cqp_request = irdma_alloc_and_get_cqp_request(&rf->cqp, true); + if (!cqp_request) { + err_code = -ENOMEM; + goto free_dmem; + } + + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = IRDMA_OP_SRQ_CREATE; + cqp_info->post_sq = 1; + cqp_info->in.u.srq_create.srq = &iwsrq->sc_srq; + cqp_info->in.u.srq_create.scratch = (uintptr_t)cqp_request; + err_code = irdma_handle_cqp_op(rf, cqp_request); + irdma_put_cqp_request(&rf->cqp, cqp_request); + if (err_code) + goto free_dmem; + + if (udata) { + struct irdma_create_srq_resp resp = {}; + + resp.srq_id = iwsrq->srq_num; + resp.srq_size = ukinfo->srq_size; + if (ib_copy_to_udata(udata, &resp, + min(sizeof(resp), udata->outlen))) { + err_code = -EPROTO; + goto srq_destroy; + } + } + + rf->srq_table[iwsrq->srq_num] = iwsrq; + init_completion(&iwsrq->free_srq); + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) && !defined(RHEL_8_2) && !defined(RHEL_8_3) && !defined(RHEL_8_4) && !defined(RHEL_8_5) && !defined(RHEL_8_6) && !defined(RHEL_8_7) && !defined(RHEL_8_8) + return &iwsrq->ibsrq; +#else + return 0; +#endif + +srq_destroy: + irdma_srq_wq_destroy(rf, &iwsrq->sc_srq); + +free_dmem: + if (!iwsrq->user_mode) + dma_free_coherent(rf->hw.device, iwsrq->kmem.size, + iwsrq->kmem.va, iwsrq->kmem.pa); +free_rsrc: + irdma_free_rsrc(rf, rf->allocated_srqs, iwsrq->srq_num); +free_sg_list: + kfree(iwsrq->sg_list); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) && !defined(RHEL_8_2) && !defined(RHEL_8_3) && !defined(RHEL_8_4) && !defined(RHEL_8_5) && !defined(RHEL_8_6) && !defined(RHEL_8_7) && !defined(RHEL_8_8) +error: + kfree(iwsrq); + return ERR_PTR(err_code); +#else + return err_code; +#endif +} + +/** + * irdma_query_srq - get SRQ attributes + * @ibsrq: the SRQ to query + * @attr: the attributes of the SRQ + */ +static int irdma_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr) +{ + struct irdma_srq *iwsrq = to_iwsrq(ibsrq); + + attr->max_wr = iwsrq->max_wr; + attr->max_sge = iwsrq->sc_srq.srq_uk.max_srq_frag_cnt; + attr->srq_limit = iwsrq->sc_srq.srq_limit; + + return 0; +} + +/** + * irdma_get_mr_access - get hw MR access permissions from IB access flags + * @access: IB access flags + * @hw_rev: Hardware version + */ +static inline u16 irdma_get_mr_access(int access, u8 hw_rev) +{ + u16 hw_access = 0; + + hw_access |= (access & IB_ACCESS_LOCAL_WRITE) ? + IRDMA_ACCESS_FLAGS_LOCALWRITE : 0; + hw_access |= (access & IB_ACCESS_REMOTE_WRITE) ? + IRDMA_ACCESS_FLAGS_REMOTEWRITE : 0; + hw_access |= (access & IB_ACCESS_REMOTE_READ) ? + IRDMA_ACCESS_FLAGS_REMOTEREAD : 0; + if (hw_rev >= IRDMA_GEN_3) { + hw_access |= (access & IB_ACCESS_MW_BIND) ? + IRDMA_ACCESS_FLAGS_BIND_WINDOW : 0; + } + hw_access |= (access & IB_ZERO_BASED) ? + IRDMA_ACCESS_FLAGS_ZERO_BASED : 0; + hw_access |= IRDMA_ACCESS_FLAGS_LOCALREAD; + + return hw_access; +} + +/** + * irdma_free_stag - free stag resource + * @iwdev: irdma device + * @stag: stag to free + */ +void irdma_free_stag(struct irdma_device *iwdev, u32 stag) +{ + u32 stag_idx; + + stag_idx = (stag & iwdev->rf->mr_stagmask) >> IRDMA_CQPSQ_STAG_IDX_S; + irdma_free_rsrc(iwdev->rf, iwdev->rf->allocated_mrs, stag_idx); +} + +/** + * irdma_create_stag - create random stag + * @iwdev: irdma device + */ +u32 irdma_create_stag(struct irdma_device *iwdev) +{ + u32 stag; + u32 stag_index = 0; + u32 next_stag_index; + u32 driver_key; + u32 random; + u8 consumer_key; + int ret; + + get_random_bytes(&random, sizeof(random)); + consumer_key = (u8)random; + + driver_key = random & ~iwdev->rf->mr_stagmask; + next_stag_index = (random & iwdev->rf->mr_stagmask) >> 8; + next_stag_index %= iwdev->rf->max_mr; + + ret = irdma_alloc_rsrc(iwdev->rf, iwdev->rf->allocated_mrs, + iwdev->rf->max_mr, &stag_index, + &next_stag_index); + if (ret) + return 0; + stag = stag_index << IRDMA_CQPSQ_STAG_IDX_S; + stag |= driver_key; + stag += (u32)consumer_key; + + return stag; +} + +#if !defined(COPY_USER_PGADDR_VER_1) || defined(UPSTREAM_RELEASE) +/** + * irdma_next_pbl_addr - Get next pbl address + * @pbl: pointer to a pble + * @pinfo: info pointer + * @idx: index + */ +static inline u64 *irdma_next_pbl_addr(u64 *pbl, struct irdma_pble_info **pinfo, + u32 *idx) +{ + *idx += 1; + if (!(*pinfo) || *idx != (*pinfo)->cnt) + return ++pbl; + *idx = 0; + (*pinfo)++; + + return (*pinfo)->addr; +} + +/** + * irdma_copy_user_pgaddrs - copy user page address to pble's os locally + * @iwmr: iwmr for IB's user page addresses + * @pbl: ple pointer to save 1 level or 0 level pble + * @level: indicated level 0, 1 or 2 + */ +static void irdma_copy_user_pgaddrs(struct irdma_mr *iwmr, u64 *pbl, + enum irdma_pble_level level) +{ + struct ib_umem *region = iwmr->region; + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; + struct irdma_pble_info *pinfo; + struct ib_block_iter biter; + u32 idx = 0; + u32 pbl_cnt = 0; + + pinfo = (level == PBLE_LEVEL_1) ? NULL : palloc->level2.leaf; + + if (iwmr->type == IRDMA_MEMREG_TYPE_QP) +#ifdef HAVE_IB_UMEM_SG_HEAD + iwpbl->qp_mr.sq_page = sg_page(region->sg_head.sgl); +#else + iwpbl->qp_mr.sq_page = sg_page(region->sgt_append.sgt.sgl); +#endif + + rdma_umem_for_each_dma_block(region, &biter, iwmr->page_size) { + *pbl = rdma_block_iter_dma_address(&biter); + if (++pbl_cnt == palloc->total_cnt) + break; + pbl = irdma_next_pbl_addr(pbl, &pinfo, &idx); + } +} + +#endif +/** + * irdma_check_mem_contiguous - check if pbls stored in arr are contiguous + * @arr: lvl1 pbl array + * @npages: page count + * @pg_size: page size + * + */ +static bool irdma_check_mem_contiguous(u64 *arr, u32 npages, u32 pg_size) +{ + u32 pg_idx; + + for (pg_idx = 0; pg_idx < npages; pg_idx++) { + if ((*arr + (pg_size * pg_idx)) != arr[pg_idx]) + return false; + } + + return true; +} + +/** + * irdma_check_mr_contiguous - check if MR is physically contiguous + * @palloc: pbl allocation struct + * @pg_size: page size + */ +static bool irdma_check_mr_contiguous(struct irdma_pble_alloc *palloc, + u32 pg_size) +{ + struct irdma_pble_level2 *lvl2 = &palloc->level2; + struct irdma_pble_info *leaf = lvl2->leaf; + u64 *arr = NULL; + u64 *start_addr = NULL; + int i; + bool ret; + + if (palloc->level == PBLE_LEVEL_1) { + arr = palloc->level1.addr; + ret = irdma_check_mem_contiguous(arr, palloc->total_cnt, + pg_size); + return ret; + } + + start_addr = leaf->addr; + + for (i = 0; i < lvl2->leaf_cnt; i++, leaf++) { + arr = leaf->addr; + if ((*start_addr + (i * pg_size * PBLE_PER_PAGE)) != *arr) + return false; + ret = irdma_check_mem_contiguous(arr, leaf->cnt, pg_size); + if (!ret) + return false; + } + + return true; +} + +/** + * irdma_setup_pbles - copy user pg address to pble's + * @rf: RDMA PCI function + * @iwmr: mr pointer for this memory registration + * @lvl: requested pble levels + */ +static int irdma_setup_pbles(struct irdma_pci_f *rf, struct irdma_mr *iwmr, + u8 lvl) +{ + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; + struct irdma_pble_info *pinfo; + u64 *pbl; + int status; + enum irdma_pble_level level = PBLE_LEVEL_1; + + if (lvl) { + status = irdma_get_pble(rf->pble_rsrc, palloc, iwmr->page_cnt, + lvl); + if (status) + return status; + + iwpbl->pbl_allocated = true; + level = palloc->level; + pinfo = (level == PBLE_LEVEL_1) ? &palloc->level1 : + palloc->level2.leaf; + pbl = pinfo->addr; + } else { + pbl = iwmr->pgaddrmem; + } + + irdma_copy_user_pgaddrs(iwmr, pbl, level); + + if (lvl) + iwmr->pgaddrmem[0] = *pbl; + + return 0; +} + +/** + * irdma_handle_q_mem - handle memory for qp and cq + * @iwdev: irdma device + * @req: information for q memory management + * @iwpbl: pble struct + * @lvl: pble level mask + */ +static int irdma_handle_q_mem(struct irdma_device *iwdev, + struct irdma_mem_reg_req *req, + struct irdma_pbl *iwpbl, u8 lvl) +{ + struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; + struct irdma_mr *iwmr = iwpbl->iwmr; + struct irdma_qp_mr *qpmr = &iwpbl->qp_mr; + struct irdma_cq_mr *cqmr = &iwpbl->cq_mr; + struct irdma_srq_mr *srqmr = &iwpbl->srq_mr; + struct irdma_hmc_pble *hmc_p; + u64 *arr = iwmr->pgaddrmem; + u32 pg_size, total; + int err = 0; + bool ret = true; + + pg_size = iwmr->page_size; + err = irdma_setup_pbles(iwdev->rf, iwmr, lvl); + if (err) + return err; + + if (lvl) + arr = palloc->level1.addr; + + switch (iwmr->type) { + case IRDMA_MEMREG_TYPE_QP: + total = req->sq_pages + req->rq_pages; + hmc_p = &qpmr->sq_pbl; + qpmr->shadow = (dma_addr_t)arr[total]; + /* Need to use physical address for RQ of QP in case it is associated with SRQ */ + qpmr->rq_pa = (dma_addr_t)arr[req->sq_pages]; + if (lvl) { + ret = irdma_check_mem_contiguous(arr, req->sq_pages, + pg_size); + if (ret) + ret = irdma_check_mem_contiguous(&arr[req->sq_pages], + req->rq_pages, + pg_size); + } + + if (!ret) { + hmc_p->idx = palloc->level1.idx; + hmc_p = &qpmr->rq_pbl; + hmc_p->idx = palloc->level1.idx + req->sq_pages; + } else { + hmc_p->addr = arr[0]; + hmc_p = &qpmr->rq_pbl; + hmc_p->addr = arr[req->sq_pages]; + } + break; + case IRDMA_MEMREG_TYPE_SRQ: + hmc_p = &srqmr->srq_pbl; + srqmr->shadow = (dma_addr_t)arr[req->rq_pages]; + if (lvl) + ret = irdma_check_mem_contiguous(arr, req->rq_pages, + pg_size); + + if (!ret) + hmc_p->idx = palloc->level1.idx; + else + hmc_p->addr = arr[0]; + break; + case IRDMA_MEMREG_TYPE_CQ: + hmc_p = &cqmr->cq_pbl; + + if (!cqmr->split) + cqmr->shadow = (dma_addr_t)arr[req->cq_pages]; + + if (lvl) + ret = irdma_check_mem_contiguous(arr, req->cq_pages, + pg_size); + + if (!ret) + hmc_p->idx = palloc->level1.idx; + else + hmc_p->addr = arr[0]; + break; + default: + ibdev_dbg(&iwdev->ibdev, "VERBS: MR type error\n"); + err = -EINVAL; + } + + if (lvl && ret) { + irdma_free_pble(iwdev->rf->pble_rsrc, palloc); + iwpbl->pbl_allocated = false; + } + + return err; +} + +/** + * irdma_hw_alloc_mw - create the hw memory window + * @iwdev: irdma device + * @iwmr: pointer to memory window info + */ +int irdma_hw_alloc_mw(struct irdma_device *iwdev, struct irdma_mr *iwmr) +{ + struct irdma_mw_alloc_info *info; + struct irdma_pd *iwpd = to_iwpd(iwmr->ibmr.pd); + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + info = &cqp_info->in.u.mw_alloc.info; + memset(info, 0, sizeof(*info)); + if (iwmr->ibmw.type == IB_MW_TYPE_1) + info->mw_wide = true; + + info->page_size = PAGE_SIZE; + info->mw_stag_index = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S; + info->pd_id = iwpd->sc_pd.pd_id; + info->remote_access = true; + cqp_info->cqp_cmd = IRDMA_OP_MW_ALLOC; + cqp_info->post_sq = 1; + cqp_info->in.u.mw_alloc.dev = &iwdev->rf->sc_dev; + cqp_info->in.u.mw_alloc.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(iwdev->rf, cqp_request); + irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_dealloc_mw - Dealloc memory window + * @ibmw: memory window structure. + */ +static int irdma_dealloc_mw(struct ib_mw *ibmw) +{ + struct ib_pd *ibpd = ibmw->pd; + struct irdma_pd *iwpd = to_iwpd(ibpd); + struct irdma_mr *iwmr = to_iwmr((struct ib_mr *)ibmw); + struct irdma_device *iwdev = to_iwdev(ibmw->device); + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + struct irdma_dealloc_stag_info *info; + + cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + info = &cqp_info->in.u.dealloc_stag.info; + memset(info, 0, sizeof(*info)); + info->pd_id = iwpd->sc_pd.pd_id; + info->stag_idx = RS_64_1(ibmw->rkey, IRDMA_CQPSQ_STAG_IDX_S); + info->mr = false; + cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG; + cqp_info->post_sq = 1; + cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev; + cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request; + irdma_handle_cqp_op(iwdev->rf, cqp_request); + irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); + irdma_free_stag(iwdev, iwmr->stag); +#ifdef IRDMA_ALLOC_MW_VER_1 + kfree(iwmr); +#endif /* IRDMA_ALLOC_MW_VER_1 */ + + return 0; +} + +/** + * irdma_hw_alloc_stag - cqp command to allocate stag + * @iwdev: irdma device + * @iwmr: irdma mr pointer + */ +int irdma_hw_alloc_stag(struct irdma_device *iwdev, + struct irdma_mr *iwmr) +{ + struct irdma_allocate_stag_info *info; + struct ib_pd *pd = iwmr->ibmr.pd; + struct irdma_pd *iwpd = to_iwpd(pd); + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + info = &cqp_info->in.u.alloc_stag.info; + memset(info, 0, sizeof(*info)); + info->page_size = PAGE_SIZE; + info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S; + info->pd_id = iwpd->sc_pd.pd_id; + info->total_len = iwmr->len; +#ifndef RHEL_7_2 + info->all_memory = (pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY) ? true : false; +#endif + info->remote_access = true; + cqp_info->cqp_cmd = IRDMA_OP_ALLOC_STAG; + cqp_info->post_sq = 1; + cqp_info->in.u.alloc_stag.dev = &iwdev->rf->sc_dev; + cqp_info->in.u.alloc_stag.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(iwdev->rf, cqp_request); + irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); + if (!status) + iwmr->is_hwreg = 1; + + return status; +} + +/** + * irdma_set_page - populate pbl list for fmr + * @ibmr: ib mem to access iwarp mr pointer + * @addr: page dma address fro pbl list + */ +static int irdma_set_page(struct ib_mr *ibmr, u64 addr) +{ + struct irdma_mr *iwmr = to_iwmr(ibmr); + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; + u64 *pbl; + + if (unlikely(iwmr->npages == iwmr->page_cnt)) + return -ENOMEM; + + if (palloc->level == PBLE_LEVEL_2) { + struct irdma_pble_info *palloc_info = + palloc->level2.leaf + (iwmr->npages >> PBLE_512_SHIFT); + + palloc_info->addr[iwmr->npages & (PBLE_PER_PAGE - 1)] = addr; + } else { + pbl = palloc->level1.addr; + pbl[iwmr->npages] = addr; + } + + iwmr->npages++; + return 0; +} + +/** + * irdma_map_mr_sg - map of sg list for fmr + * @ibmr: ib mem to access iwarp mr pointer + * @sg: scatter gather list + * @sg_nents: number of sg pages + * @sg_offset: scatter gather list for fmr + */ +static int irdma_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, + int sg_nents, unsigned int *sg_offset) +{ + struct irdma_mr *iwmr = to_iwmr(ibmr); + + iwmr->npages = 0; + + return ib_sg_to_pages(ibmr, sg, sg_nents, sg_offset, irdma_set_page); +} + +/** + * irdma_hwreg_mr - send cqp command for memory registration + * @iwdev: irdma device + * @iwmr: irdma mr pointer + * @access: access for MR + */ +int irdma_hwreg_mr(struct irdma_device *iwdev, struct irdma_mr *iwmr, + u16 access) +{ + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + struct irdma_reg_ns_stag_info *stag_info; + struct ib_pd *pd = iwmr->ibmr.pd; + struct irdma_pd *iwpd = to_iwpd(pd); + struct irdma_pble_alloc *palloc = &iwpbl->pble_alloc; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int ret; + + cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + stag_info = &cqp_info->in.u.mr_reg_non_shared.info; + memset(stag_info, 0, sizeof(*stag_info)); + stag_info->va = iwpbl->user_base; + stag_info->stag_idx = iwmr->stag >> IRDMA_CQPSQ_STAG_IDX_S; + stag_info->stag_key = (u8)iwmr->stag; + stag_info->total_len = iwmr->len; +#ifndef RHEL_7_2 + stag_info->all_memory = (pd->flags & IB_PD_UNSAFE_GLOBAL_RKEY) ? true : false; +#endif + stag_info->access_rights = irdma_get_mr_access(access, + iwdev->rf->sc_dev.hw_attrs.uk_attrs.hw_rev); + stag_info->remote_atomics_en = (access & IB_ACCESS_REMOTE_ATOMIC) ? 1 : 0; + stag_info->pd_id = iwpd->sc_pd.pd_id; + if (stag_info->access_rights & IRDMA_ACCESS_FLAGS_ZERO_BASED) + stag_info->addr_type = IRDMA_ADDR_TYPE_ZERO_BASED; + else + stag_info->addr_type = IRDMA_ADDR_TYPE_VA_BASED; + stag_info->page_size = iwmr->page_size; + + if (iwpbl->pbl_allocated) { + if (palloc->level == PBLE_LEVEL_1) { + stag_info->first_pm_pbl_index = palloc->level1.idx; + stag_info->chunk_size = 1; + } else { + stag_info->first_pm_pbl_index = palloc->level2.root.idx; + stag_info->chunk_size = 3; + } + } else { + stag_info->reg_addr_pa = iwmr->pgaddrmem[0]; +#ifdef CONFIG_DEBUG_FS + iwmr->level0_pa = iwmr->pgaddrmem[0]; +#endif + } + + cqp_info->cqp_cmd = IRDMA_OP_MR_REG_NON_SHARED; + cqp_info->post_sq = 1; + cqp_info->in.u.mr_reg_non_shared.dev = &iwdev->rf->sc_dev; + cqp_info->in.u.mr_reg_non_shared.scratch = (uintptr_t)cqp_request; + ret = irdma_handle_cqp_op(iwdev->rf, cqp_request); + irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); + + if (!ret) + iwmr->is_hwreg = 1; + + return ret; +} + +#ifdef SET_BEST_PAGE_SZ_V1 +/** + * irdma_set_best_pagesz - set MR best pg size and mask values. + * @addr: virtual address + * @iwmr: mr pointer for this memory registration + * @page_size_cap: Page sizes supported + */ +static void irdma_set_best_pagesz(u64 addr, struct irdma_mr *iwmr, u64 page_size_cap) +{ + struct vm_area_struct *vma; + struct hstate *h; + + if (!iwmr->region->hugetlb) { + iwmr->page_size = IRDMA_HW_PAGE_SIZE; + iwmr->page_msk = ~(IRDMA_HW_PAGE_SIZE - 1); + return; + } + vma = find_vma(current->mm, addr); + if (vma && is_vm_hugetlb_page(vma)) { + h = hstate_vma(vma); + if ((huge_page_size(h) == SZ_2M && (page_size_cap & SZ_2M)) || + (huge_page_size(h) == SZ_1G && (page_size_cap & SZ_1G))) { + iwmr->page_size = huge_page_size(h); + iwmr->page_msk = huge_page_mask(h); + } + } +} + +#endif +/* + * irdma_alloc_iwmr - Allocate iwmr + * @region - memory region + * @pd - protection domain + * @virt - virtual address + * @reg_type - registration type + */ +#ifndef SET_BEST_PAGE_SZ_V1 +static struct irdma_mr *irdma_alloc_iwmr(struct ib_umem *region, + struct ib_pd *pd, u64 virt, + enum irdma_memreg_type reg_type) +#else +static struct irdma_mr *irdma_alloc_iwmr(struct ib_umem *region, + struct ib_pd *pd, u64 virt, u64 start, + enum irdma_memreg_type reg_type) +#endif /* SET_BEST_PAGE_SZ_V1 */ +{ +#if defined(SET_BEST_PAGE_SZ_V2) || defined(SET_BEST_PAGE_SZ_V1) + struct irdma_device *iwdev = to_iwdev(pd->device); +#endif + struct irdma_pbl *iwpbl; + struct irdma_mr *iwmr; +#ifdef SET_BEST_PAGE_SZ_V2 + unsigned long pgsz_bitmap; +#endif + + iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL); + if (!iwmr) + return ERR_PTR(-ENOMEM); + + iwpbl = &iwmr->iwpbl; + iwpbl->iwmr = iwmr; + iwmr->region = region; + iwmr->ibmr.pd = pd; + iwmr->ibmr.device = pd->device; + iwmr->ibmr.iova = virt; + iwmr->type = reg_type; + + /* Some OOT versions of irdma_copy_user_pg_addr require the pg mask */ + iwmr->page_msk = ~(IRDMA_HW_PAGE_SIZE - 1); +#ifdef SET_BEST_PAGE_SZ_V1 + iwmr->page_size = IRDMA_HW_PAGE_SIZE; + if (reg_type == IRDMA_MEMREG_TYPE_MEM) + irdma_set_best_pagesz(start, iwmr, + iwdev->rf->sc_dev.hw_attrs.page_size_cap); +#endif +#ifdef SET_BEST_PAGE_SZ_V2 + pgsz_bitmap = (reg_type == IRDMA_MEMREG_TYPE_MEM) ? + iwdev->rf->sc_dev.hw_attrs.page_size_cap : SZ_4K; + + iwmr->page_size = ib_umem_find_best_pgsz(region, pgsz_bitmap, virt); + if (unlikely(!iwmr->page_size)) { + kfree(iwmr); + return ERR_PTR(-EOPNOTSUPP); + } + +#endif + iwmr->len = region->length; + iwpbl->user_base = virt; +#ifdef HAVE_IB_UMEM_NUM_DMA_BLOCKS + iwmr->page_cnt = ib_umem_num_dma_blocks(region, iwmr->page_size); +#else + iwmr->page_cnt = irdma_ib_umem_num_dma_blocks(region, iwmr->page_size, virt); +#endif + + return iwmr; +} + +static void irdma_free_iwmr(struct irdma_mr *iwmr) +{ + kfree(iwmr); +} + +/* + * irdma_reg_user_mr_type_mem - Handle memory registration + * @iwmr - irdma mr + * @access - access rights + * @create_stag - flag to create stag or not + */ +static int irdma_reg_user_mr_type_mem(struct irdma_mr *iwmr, int access, + bool create_stag) +{ + struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + u32 stag = 0; + int err; + u8 lvl; + + lvl = iwmr->page_cnt != 1 ? PBLE_LEVEL_1 | PBLE_LEVEL_2 : PBLE_LEVEL_0; + + err = irdma_setup_pbles(iwdev->rf, iwmr, lvl); + if (err) + return err; + + if (lvl) { + err = irdma_check_mr_contiguous(&iwpbl->pble_alloc, + iwmr->page_size); + if (err) { + irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc); + iwpbl->pbl_allocated = false; + } + } + + if (create_stag) { + stag = irdma_create_stag(iwdev); + if (!stag) { + err = -ENOMEM; + goto free_pble; + } + + iwmr->stag = stag; + iwmr->ibmr.rkey = stag; + iwmr->ibmr.lkey = stag; + } + iwmr->access = access; + err = irdma_hwreg_mr(iwdev, iwmr, access); + if (err) + goto err_hwreg; + + return 0; + +err_hwreg: + if (stag) + irdma_free_stag(iwdev, stag); + +free_pble: + if (iwpbl->pble_alloc.level != PBLE_LEVEL_0 && iwpbl->pbl_allocated) + irdma_free_pble(iwdev->rf->pble_rsrc, &iwpbl->pble_alloc); + + return err; +} + +/* + * irdma_reg_user_mr_type_qp - Handle QP memory registration + * @req - memory reg req + * @udata - user info + * @iwmr - irdma mr + */ +static int irdma_reg_user_mr_type_qp(struct irdma_mem_reg_req req, + struct ib_udata *udata, + struct irdma_mr *iwmr) +{ + struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + struct irdma_ucontext *ucontext; + unsigned long flags; + u32 total; + int err; + u8 lvl; + + /* iWarp: Catch page not starting on OS page boundary */ + if (!rdma_protocol_roce(&iwdev->ibdev, 1) && + ib_umem_offset(iwmr->region)) + return -EINVAL; + + total = req.sq_pages + req.rq_pages + IRDMA_SHADOW_PGCNT; + if (total > iwmr->page_cnt) + return -EINVAL; + + total = req.sq_pages + req.rq_pages; + lvl = total > 2 ? PBLE_LEVEL_1 : PBLE_LEVEL_0; + err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl); + if (err) + return err; + + ucontext = kc_rdma_udata_to_drv_context(iwmr->ibmr.pd, udata); + spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags); + list_add_tail(&iwpbl->list, &ucontext->qp_reg_mem_list); + iwpbl->on_list = true; + spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); + + return 0; +} + +/* + * irdma_reg_user_mr_type_srq - Handle SRQ memory registration + * @req - memory reg req + * @udata - user info + * @iwmr - irdma mr + */ +static int irdma_reg_user_mr_type_srq(struct irdma_mem_reg_req req, + struct ib_udata *udata, + struct irdma_mr *iwmr) +{ + struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + struct irdma_ucontext *ucontext; + unsigned long flags; + u32 total; + int err; + u8 lvl; + + total = req.rq_pages + IRDMA_SHADOW_PGCNT; + if (total > iwmr->page_cnt) + return -EINVAL; + + lvl = req.rq_pages > 1 ? PBLE_LEVEL_1 : PBLE_LEVEL_0; + err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl); + if (err) + return err; + + ucontext = kc_rdma_udata_to_drv_context(iwmr->ibmr.pd, udata); + spin_lock_irqsave(&ucontext->srq_reg_mem_list_lock, flags); + list_add_tail(&iwpbl->list, &ucontext->srq_reg_mem_list); + iwpbl->on_list = true; + spin_unlock_irqrestore(&ucontext->srq_reg_mem_list_lock, flags); + + return 0; +} + +/* + * irdma_reg_user_mr_type_cq - Handle CQ memory registration + * @req - memory reg req + * @udata - user info + * @iwmr - irdma mr + */ +static int irdma_reg_user_mr_type_cq(struct irdma_mem_reg_req req, + struct ib_udata *udata, + struct irdma_mr *iwmr) +{ + struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + struct irdma_ucontext *ucontext; + unsigned long flags; + u32 total; + int err; + u8 lvl; + + total = req.cq_pages + + ((iwdev->rf->sc_dev.hw_attrs.uk_attrs.feature_flags & IRDMA_FEATURE_CQ_RESIZE) ? 0 : IRDMA_SHADOW_PGCNT); + if (total > iwmr->page_cnt) + return -EINVAL; + + lvl = req.cq_pages > 1 ? PBLE_LEVEL_1 : PBLE_LEVEL_0; + err = irdma_handle_q_mem(iwdev, &req, iwpbl, lvl); + if (err) + return err; + + ucontext = kc_rdma_udata_to_drv_context(iwmr->ibmr.pd, udata); + spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); + list_add_tail(&iwpbl->list, &ucontext->cq_reg_mem_list); + iwpbl->on_list = true; + spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); + + return 0; +} + +/** + * irdma_reg_user_mr - Register a user memory region + * @pd: ptr of pd + * @start: virtual start address + * @len: length of mr + * @virt: virtual address + * @access: access of mr + * @udata: user data + */ +static struct ib_mr *irdma_reg_user_mr(struct ib_pd *pd, u64 start, u64 len, + u64 virt, int access, + struct ib_udata *udata) +{ +#define IRDMA_MEM_REG_MIN_REQ_LEN offsetofend(struct irdma_mem_reg_req, sq_pages) + struct irdma_device *iwdev = to_iwdev(pd->device); + struct irdma_mem_reg_req req = {}; + struct ib_umem *region; + struct irdma_mr *iwmr; + int err; + + if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size) + return ERR_PTR(-EINVAL); + + if (udata->inlen < IRDMA_MEM_REG_MIN_REQ_LEN) + return ERR_PTR(-EINVAL); + +#ifdef IB_UMEM_GET_V3 + region = ib_umem_get(pd->device, start, len, access); +#endif +#ifdef IB_UMEM_GET_V2 + region = ib_umem_get(udata, start, len, access); +#endif +#ifdef IB_UMEM_GET_V1 + region = ib_umem_get(udata, start, len, access, 0); +#endif +#ifdef IB_UMEM_GET_V0 + region = ib_umem_get(pd->uobject->context, start, len, access, 0); +#endif + + if (IS_ERR(region)) { + ibdev_dbg(&iwdev->ibdev, + "VERBS: Failed to create ib_umem region err=%ld\n", PTR_ERR(region)); + return (struct ib_mr *)region; + } + + if (ib_copy_from_udata(&req, udata, min(sizeof(req), udata->inlen))) { + ib_umem_release(region); + return ERR_PTR(-EFAULT); + } + +#ifndef SET_BEST_PAGE_SZ_V1 + iwmr = irdma_alloc_iwmr(region, pd, virt, req.reg_type); +#else + iwmr = irdma_alloc_iwmr(region, pd, virt, start, req.reg_type); +#endif + if (IS_ERR(iwmr)) { + ib_umem_release(region); + return (struct ib_mr *)iwmr; + } + + switch (req.reg_type) { + case IRDMA_MEMREG_TYPE_QP: + err = irdma_reg_user_mr_type_qp(req, udata, iwmr); + if (err) + goto error; + + break; + case IRDMA_MEMREG_TYPE_SRQ: + err = irdma_reg_user_mr_type_srq(req, udata, iwmr); + if (err) + goto error; + + break; + case IRDMA_MEMREG_TYPE_CQ: + err = irdma_reg_user_mr_type_cq(req, udata, iwmr); + if (err) + goto error; + + break; + case IRDMA_MEMREG_TYPE_MEM: + err = irdma_reg_user_mr_type_mem(iwmr, access, true); + if (err) + goto error; + +#ifdef CONFIG_DEBUG_FS +#ifdef SET_BEST_PAGE_SZ_V1 + if (iwmr->region->hugetlb && (iwmr->page_size == 0x200000 || + iwmr->page_size == 0x40000000)) + iwdev->hugepgcnt += iwmr->page_cnt; +#endif +#endif + break; + default: + err = -EINVAL; + goto error; + } + + + return &iwmr->ibmr; + +error: + ib_umem_release(region); + irdma_free_iwmr(iwmr); + + return ERR_PTR(err); +} + +int irdma_hwdereg_mr(struct ib_mr *ib_mr) +{ + struct irdma_device *iwdev = to_iwdev(ib_mr->device); + struct irdma_mr *iwmr = to_iwmr(ib_mr); + struct irdma_pd *iwpd = to_iwpd(ib_mr->pd); + struct irdma_dealloc_stag_info *info; + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + struct irdma_cqp_request *cqp_request; + struct cqp_cmds_info *cqp_info; + int status; + + /* Skip HW MR de-register when it is already de-registered + * during an MR re-reregister and the re-registration fails + */ + if (!iwmr->is_hwreg) + return 0; + + cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_info = &cqp_request->info; + info = &cqp_info->in.u.dealloc_stag.info; + memset(info, 0, sizeof(*info)); + info->pd_id = iwpd->sc_pd.pd_id; + info->stag_idx = RS_64_1(ib_mr->rkey, IRDMA_CQPSQ_STAG_IDX_S); + info->mr = true; + if (iwpbl->pbl_allocated) + info->dealloc_pbl = true; + + cqp_info->cqp_cmd = IRDMA_OP_DEALLOC_STAG; + cqp_info->post_sq = 1; + cqp_info->in.u.dealloc_stag.dev = &iwdev->rf->sc_dev; + cqp_info->in.u.dealloc_stag.scratch = (uintptr_t)cqp_request; + status = irdma_handle_cqp_op(iwdev->rf, cqp_request); + irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); + + if (!status) + iwmr->is_hwreg = 0; + + return status; +} + +/* + * irdma_rereg_mr_trans - Re-register a user MR for a change translation. + * @iwmr: ptr of iwmr + * @start: virtual start address + * @len: length of mr + * @virt: virtual address + * + * Re-register a user memory region when a change translation is requested. + * Re-register a new region while reusing the stag from the original registration. + */ +struct ib_mr *irdma_rereg_mr_trans(struct irdma_mr *iwmr, u64 start, u64 len, + u64 virt, struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(iwmr->ibmr.device); + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + struct ib_pd *pd = iwmr->ibmr.pd; + struct ib_umem *region; + int err; + +#ifdef IB_UMEM_GET_V3 + region = ib_umem_get(pd->device, start, len, iwmr->access); +#endif +#ifdef IB_UMEM_GET_V2 + region = ib_umem_get(udata, start, len, iwmr->access); +#endif +#ifdef IB_UMEM_GET_V1 + region = ib_umem_get(udata, start, len, iwmr->access, 0); +#endif +#ifdef IB_UMEM_GET_V0 + region = ib_umem_get(pd->uobject->context, start, len, iwmr->access, 0); +#endif + + if (IS_ERR(region)) { + ibdev_dbg(&iwdev->ibdev, + "VERBS: Failed to create ib_umem region err=%ld\n", PTR_ERR(region)); + return (struct ib_mr *)region; + } + + iwmr->region = region; + iwmr->ibmr.iova = virt; + iwmr->ibmr.pd = pd; + iwmr->page_size = PAGE_SIZE; + +#ifdef SET_BEST_PAGE_SZ_V1 + irdma_set_best_pagesz(start, iwmr, + iwdev->rf->sc_dev.hw_attrs.page_size_cap); + +#endif +#ifdef SET_BEST_PAGE_SZ_V2 + iwmr->page_size = ib_umem_find_best_pgsz(region, + iwdev->rf->sc_dev.hw_attrs.page_size_cap, + virt); + if (unlikely(!iwmr->page_size)) { + err = -EOPNOTSUPP; + goto err; + } +#endif + iwmr->len = region->length; + iwpbl->user_base = virt; +#ifdef HAVE_IB_UMEM_NUM_DMA_BLOCKS + iwmr->page_cnt = ib_umem_num_dma_blocks(region, iwmr->page_size); +#else + iwmr->page_cnt = irdma_ib_umem_num_dma_blocks(region, iwmr->page_size, + virt); +#endif + + err = irdma_reg_user_mr_type_mem(iwmr, iwmr->access, false); + if (err) + goto err; + +#ifdef CONFIG_DEBUG_FS +#ifdef SET_BEST_PAGE_SZ_V1 + if (iwmr->region->hugetlb && (iwmr->page_size == 0x200000 || + iwmr->page_size == 0x40000000)) + iwdev->hugepgcnt += iwmr->page_cnt; +#endif +#endif + return &iwmr->ibmr; + +err: + ib_umem_release(region); + return ERR_PTR(err); +} + +#ifdef SET_DMABUF + +static struct ib_mr *irdma_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start, + u64 len, u64 virt, + int fd, int access, + struct ib_udata *udata) +{ + struct irdma_device *iwdev = to_iwdev(pd->device); + struct ib_umem_dmabuf *umem_dmabuf; + struct irdma_mr *iwmr; + int err; + + if (len > iwdev->rf->sc_dev.hw_attrs.max_mr_size) + return ERR_PTR(-EINVAL); + + umem_dmabuf = ib_umem_dmabuf_get_pinned(pd->device, start, len, fd, access); + if (IS_ERR(umem_dmabuf)) { + err = PTR_ERR(umem_dmabuf); + ibdev_dbg(&iwdev->ibdev, "Failed to get dmabuf umem[%d]\n", err); + return ERR_PTR(err); + } + + iwmr = irdma_alloc_iwmr(&umem_dmabuf->umem, pd, virt, IRDMA_MEMREG_TYPE_MEM); + if (IS_ERR(iwmr)) { + err = PTR_ERR(iwmr); + goto err_release; + } + + err = irdma_reg_user_mr_type_mem(iwmr, access, true); + if (err) + goto err_iwmr; + + return &iwmr->ibmr; + +err_iwmr: + irdma_free_iwmr(iwmr); + +err_release: + ib_umem_release(&umem_dmabuf->umem); + + return ERR_PTR(err); +} + +#endif /* SET_DMABUF */ +/** + * irdma_reg_phys_mr - register kernel physical memory + * @pd: ibpd pointer + * @addr: physical address of memory to register + * @size: size of memory to register + * @access: Access rights + * @iova_start: start of virtual address for physical buffers + */ +struct ib_mr *irdma_reg_phys_mr(struct ib_pd *pd, u64 addr, u64 size, int access, + u64 *iova_start) +{ + struct irdma_device *iwdev = to_iwdev(pd->device); + struct irdma_pbl *iwpbl; + struct irdma_mr *iwmr; + u32 stag; + int ret; + + iwmr = kzalloc(sizeof(*iwmr), GFP_KERNEL); + if (!iwmr) + return ERR_PTR(-ENOMEM); + + iwmr->ibmr.pd = pd; + iwmr->ibmr.device = pd->device; + iwpbl = &iwmr->iwpbl; + iwpbl->iwmr = iwmr; + iwmr->type = IRDMA_MEMREG_TYPE_MEM; + iwpbl->user_base = *iova_start; + stag = irdma_create_stag(iwdev); + if (!stag) { + ret = -ENOMEM; + goto err; + } + + iwmr->stag = stag; + iwmr->ibmr.iova = *iova_start; + iwmr->ibmr.rkey = stag; + iwmr->ibmr.lkey = stag; + iwmr->page_cnt = 1; + iwmr->pgaddrmem[0] = addr; + iwmr->len = size; + iwmr->page_size = SZ_4K; + ret = irdma_hwreg_mr(iwdev, iwmr, access); + if (ret) { + irdma_free_stag(iwdev, stag); + goto err; + } + + return &iwmr->ibmr; + +err: + kfree(iwmr); + + return ERR_PTR(ret); +} + +/** + * irdma_get_dma_mr - register physical mem + * @pd: ptr of pd + * @acc: access for memory + */ +static struct ib_mr *irdma_get_dma_mr(struct ib_pd *pd, int acc) +{ + u64 kva = 0; + + return irdma_reg_phys_mr(pd, 0, 0, acc, &kva); +} + +/** + * irdma_del_memlist - Deleting pbl list entries for CQ/QP + * @iwmr: iwmr for IB's user page addresses + * @ucontext: ptr to user context + */ +void irdma_del_memlist(struct irdma_mr *iwmr, + struct irdma_ucontext *ucontext) +{ + struct irdma_pbl *iwpbl = &iwmr->iwpbl; + unsigned long flags; + + switch (iwmr->type) { + case IRDMA_MEMREG_TYPE_CQ: + spin_lock_irqsave(&ucontext->cq_reg_mem_list_lock, flags); + if (iwpbl->on_list) { + iwpbl->on_list = false; + list_del(&iwpbl->list); + } + spin_unlock_irqrestore(&ucontext->cq_reg_mem_list_lock, flags); + break; + case IRDMA_MEMREG_TYPE_QP: + spin_lock_irqsave(&ucontext->qp_reg_mem_list_lock, flags); + if (iwpbl->on_list) { + iwpbl->on_list = false; + list_del(&iwpbl->list); + } + spin_unlock_irqrestore(&ucontext->qp_reg_mem_list_lock, flags); + break; + case IRDMA_MEMREG_TYPE_SRQ: + spin_lock_irqsave(&ucontext->srq_reg_mem_list_lock, flags); + if (iwpbl->on_list) { + iwpbl->on_list = false; + list_del(&iwpbl->list); + } + spin_unlock_irqrestore(&ucontext->srq_reg_mem_list_lock, flags); + break; + default: + break; + } +} + +/** + * irdma_post_send - kernel application wr + * @ibqp: qp ptr for wr + * @ib_wr: work request ptr + * @bad_wr: return of bad wr if err + */ +static int irdma_post_send(struct ib_qp *ibqp, + kc_typeq_ib_wr struct ib_send_wr *ib_wr, + kc_typeq_ib_wr struct ib_send_wr **bad_wr) +{ + struct irdma_qp *iwqp; + struct irdma_qp_uk *ukqp; + struct irdma_sc_dev *dev; + struct irdma_post_sq_info info; + int err = 0; + unsigned long flags; + bool inv_stag; + struct irdma_ah *ah; + + iwqp = to_iwqp(ibqp); + ukqp = &iwqp->sc_qp.qp_uk; + dev = &iwqp->iwdev->rf->sc_dev; + + spin_lock_irqsave(&iwqp->lock, flags); + while (ib_wr) { + memset(&info, 0, sizeof(info)); + inv_stag = false; + info.wr_id = (ib_wr->wr_id); + if ((ib_wr->send_flags & IB_SEND_SIGNALED) || iwqp->sig_all) + info.signaled = true; + if (ib_wr->send_flags & IB_SEND_FENCE) + info.read_fence = true; + switch (ib_wr->opcode) { + case IB_WR_ATOMIC_CMP_AND_SWP: + info.op_type = IRDMA_OP_TYPE_ATOMIC_COMPARE_AND_SWAP; + info.op.atomic_compare_swap.tagged_offset = ib_wr->sg_list[0].addr; + info.op.atomic_compare_swap.remote_tagged_offset = + atomic_wr(ib_wr)->remote_addr; + info.op.atomic_compare_swap.swap_data_bytes = atomic_wr(ib_wr)->swap; + info.op.atomic_compare_swap.compare_data_bytes = + atomic_wr(ib_wr)->compare_add; + info.op.atomic_compare_swap.stag = ib_wr->sg_list[0].lkey; + info.op.atomic_compare_swap.remote_stag = atomic_wr(ib_wr)->rkey; + err = irdma_uk_atomic_compare_swap(ukqp, &info, false); + break; + case IB_WR_ATOMIC_FETCH_AND_ADD: + info.op_type = IRDMA_OP_TYPE_ATOMIC_FETCH_AND_ADD; + info.op.atomic_fetch_add.tagged_offset = ib_wr->sg_list[0].addr; + info.op.atomic_fetch_add.remote_tagged_offset = + atomic_wr(ib_wr)->remote_addr; + info.op.atomic_fetch_add.fetch_add_data_bytes = + atomic_wr(ib_wr)->compare_add; + info.op.atomic_fetch_add.stag = ib_wr->sg_list[0].lkey; + info.op.atomic_fetch_add.remote_stag = atomic_wr(ib_wr)->rkey; + err = irdma_uk_atomic_fetch_add(ukqp, &info, false); + break; + case IB_WR_SEND_WITH_IMM: + if (ukqp->qp_caps & IRDMA_SEND_WITH_IMM) { + info.imm_data_valid = true; + info.imm_data = ntohl(ib_wr->ex.imm_data); + } else { + err = -EINVAL; + break; + } + fallthrough; + case IB_WR_SEND: + case IB_WR_SEND_WITH_INV: + if (ib_wr->opcode == IB_WR_SEND || + ib_wr->opcode == IB_WR_SEND_WITH_IMM) { + if (ib_wr->send_flags & IB_SEND_SOLICITED) + info.op_type = IRDMA_OP_TYPE_SEND_SOL; + else + info.op_type = IRDMA_OP_TYPE_SEND; + } else { + if (ib_wr->send_flags & IB_SEND_SOLICITED) + info.op_type = IRDMA_OP_TYPE_SEND_SOL_INV; + else + info.op_type = IRDMA_OP_TYPE_SEND_INV; + info.stag_to_inv = ib_wr->ex.invalidate_rkey; + } + + info.op.send.num_sges = ib_wr->num_sge; + info.op.send.sg_list = ib_wr->sg_list; + if (iwqp->ibqp.qp_type == IB_QPT_UD || + iwqp->ibqp.qp_type == IB_QPT_GSI) { + ah = to_iwah(ud_wr(ib_wr)->ah); + info.op.send.ah_id = ah->sc_ah.ah_info.ah_idx; + info.op.send.qkey = ud_wr(ib_wr)->remote_qkey; + info.op.send.dest_qp = ud_wr(ib_wr)->remote_qpn; + } + + if (ib_wr->send_flags & IB_SEND_INLINE) + err = irdma_uk_inline_send(ukqp, &info, false); + else + err = irdma_uk_send(ukqp, &info, false); + break; + case IB_WR_RDMA_WRITE_WITH_IMM: + if (ukqp->qp_caps & IRDMA_WRITE_WITH_IMM) { + info.imm_data_valid = true; + info.imm_data = ntohl(ib_wr->ex.imm_data); + } else { + err = -EINVAL; + break; + } + fallthrough; + case IB_WR_RDMA_WRITE: + if (ib_wr->send_flags & IB_SEND_SOLICITED) + info.op_type = IRDMA_OP_TYPE_RDMA_WRITE_SOL; + else + info.op_type = IRDMA_OP_TYPE_RDMA_WRITE; + + info.op.rdma_write.num_lo_sges = ib_wr->num_sge; + info.op.rdma_write.lo_sg_list = (void *)ib_wr->sg_list; + info.op.rdma_write.rem_addr.addr = rdma_wr(ib_wr)->remote_addr; + info.op.rdma_write.rem_addr.lkey = rdma_wr(ib_wr)->rkey; + if (ib_wr->send_flags & IB_SEND_INLINE) + err = irdma_uk_inline_rdma_write(ukqp, &info, false); + else + err = irdma_uk_rdma_write(ukqp, &info, false); + break; + case IB_WR_RDMA_READ_WITH_INV: + inv_stag = true; + fallthrough; + case IB_WR_RDMA_READ: + if (ib_wr->num_sge > + dev->hw_attrs.uk_attrs.max_hw_read_sges) { + err = -EINVAL; + break; + } + info.op_type = IRDMA_OP_TYPE_RDMA_READ; + info.op.rdma_read.rem_addr.addr = rdma_wr(ib_wr)->remote_addr; + info.op.rdma_read.rem_addr.lkey = rdma_wr(ib_wr)->rkey; + info.op.rdma_read.lo_sg_list = (void *)ib_wr->sg_list; + info.op.rdma_read.num_lo_sges = ib_wr->num_sge; + err = irdma_uk_rdma_read(ukqp, &info, inv_stag, false); + break; + case IB_WR_LOCAL_INV: + info.op_type = IRDMA_OP_TYPE_INV_STAG; + info.local_fence = info.read_fence; + info.op.inv_local_stag.target_stag = ib_wr->ex.invalidate_rkey; + err = irdma_uk_stag_local_invalidate(ukqp, &info, true); + break; + case IB_WR_REG_MR: { + struct irdma_mr *iwmr = to_iwmr(reg_wr(ib_wr)->mr); + struct irdma_pble_alloc *palloc = &iwmr->iwpbl.pble_alloc; + struct irdma_fast_reg_stag_info stag_info = {}; + + stag_info.signaled = info.signaled; + stag_info.read_fence = info.read_fence; + stag_info.access_rights = + irdma_get_mr_access(reg_wr(ib_wr)->access, + dev->hw_attrs.uk_attrs.hw_rev); + stag_info.stag_key = reg_wr(ib_wr)->key & 0xff; + stag_info.stag_idx = reg_wr(ib_wr)->key >> 8; + stag_info.page_size = reg_wr(ib_wr)->mr->page_size; + stag_info.wr_id = ib_wr->wr_id; + stag_info.addr_type = IRDMA_ADDR_TYPE_VA_BASED; + stag_info.va = (void *)(uintptr_t)iwmr->ibmr.iova; + stag_info.total_len = iwmr->ibmr.length; + if (palloc->level == PBLE_LEVEL_2) { + stag_info.chunk_size = 3; + stag_info.first_pm_pbl_index = palloc->level2.root.idx; + } else { + stag_info.chunk_size = 1; + stag_info.first_pm_pbl_index = palloc->level1.idx; + } + stag_info.local_fence = ib_wr->send_flags & IB_SEND_FENCE; + err = irdma_sc_mr_fast_register(&iwqp->sc_qp, &stag_info, + true); + break; + } + default: + err = -EINVAL; + ibdev_dbg(&iwqp->iwdev->ibdev, + "VERBS: upost_send bad opcode = 0x%x\n", + ib_wr->opcode); + break; + } + + if (err) + break; + ib_wr = ib_wr->next; + } + + if (ukqp->uk_attrs->hw_rev <= IRDMA_GEN_2) { + if (!iwqp->flush_issued) { + if (iwqp->hw_iwarp_state <= IRDMA_QP_STATE_RTS) + irdma_uk_qp_post_wr(ukqp); + spin_unlock_irqrestore(&iwqp->lock, flags); + } else { + spin_unlock_irqrestore(&iwqp->lock, flags); + irdma_sched_qp_flush_work(iwqp); + } + } else { + irdma_uk_qp_post_wr(ukqp); + spin_unlock_irqrestore(&iwqp->lock, flags); + } + + if (err) + *bad_wr = ib_wr; + + return err; +} + +/** + * irdma_post_srq_recv - post receive wr for kernel application + * @ibsrq: ib srq pointer + * @ib_wr: work request for receive + * @bad_wr: bad wr caused an error + */ +static int irdma_post_srq_recv(struct ib_srq *ibsrq, + kc_typeq_ib_wr struct ib_recv_wr *ib_wr, + kc_typeq_ib_wr struct ib_recv_wr **bad_wr) +{ + struct irdma_srq *iwsrq = to_iwsrq(ibsrq); + struct irdma_srq_uk *uksrq = &iwsrq->sc_srq.srq_uk; + struct irdma_post_rq_info post_recv = {}; + unsigned long flags; + int err = 0; + + spin_lock_irqsave(&iwsrq->lock, flags); + while (ib_wr) { + if (ib_wr->num_sge > uksrq->max_srq_frag_cnt) { + err = -EINVAL; + goto out; + } + post_recv.num_sges = ib_wr->num_sge; + post_recv.wr_id = ib_wr->wr_id; + post_recv.sg_list = ib_wr->sg_list; + err = irdma_uk_srq_post_receive(uksrq, &post_recv); + if (err) + goto out; + + ib_wr = ib_wr->next; + } + +out: + spin_unlock_irqrestore(&iwsrq->lock, flags); + + if (err) + *bad_wr = ib_wr; + + return err; +} + +/** + * irdma_post_recv - post receive wr for kernel application + * @ibqp: ib qp pointer + * @ib_wr: work request for receive + * @bad_wr: bad wr caused an error + */ +static int irdma_post_recv(struct ib_qp *ibqp, + kc_typeq_ib_wr struct ib_recv_wr *ib_wr, + kc_typeq_ib_wr struct ib_recv_wr **bad_wr) +{ + struct irdma_qp *iwqp = to_iwqp(ibqp); + struct irdma_qp_uk *ukqp = &iwqp->sc_qp.qp_uk; + struct irdma_post_rq_info post_recv = {}; + unsigned long flags; + int err = 0; + + if (ukqp->srq_uk) { + *bad_wr = ib_wr; + return -EINVAL; + } + + spin_lock_irqsave(&iwqp->lock, flags); + + while (ib_wr) { + if (ib_wr->num_sge > ukqp->max_rq_frag_cnt) { + err = -EINVAL; + goto out; + } + post_recv.num_sges = ib_wr->num_sge; + post_recv.wr_id = ib_wr->wr_id; + post_recv.sg_list = ib_wr->sg_list; + err = irdma_uk_post_receive(ukqp, &post_recv); + if (err) { + ibdev_dbg(&iwqp->iwdev->ibdev, + "VERBS: post_recv err %d\n", err); + goto out; + } + + ib_wr = ib_wr->next; + } + +out: + spin_unlock_irqrestore(&iwqp->lock, flags); + if (ukqp->uk_attrs->hw_rev <= IRDMA_GEN_2 && iwqp->flush_issued) + irdma_sched_qp_flush_work(iwqp); + + if (err) + *bad_wr = ib_wr; + + return err; +} + +/** + * irdma_flush_err_to_ib_wc_status - return change flush error code to IB status + * @opcode: iwarp flush code + */ +static enum ib_wc_status irdma_flush_err_to_ib_wc_status(enum irdma_flush_opcode opcode) +{ + switch (opcode) { + case FLUSH_PROT_ERR: + return IB_WC_LOC_PROT_ERR; + case FLUSH_REM_ACCESS_ERR: + return IB_WC_REM_ACCESS_ERR; + case FLUSH_LOC_QP_OP_ERR: + return IB_WC_LOC_QP_OP_ERR; + case FLUSH_REM_OP_ERR: + return IB_WC_REM_OP_ERR; + case FLUSH_LOC_LEN_ERR: + return IB_WC_LOC_LEN_ERR; + case FLUSH_GENERAL_ERR: + return IB_WC_WR_FLUSH_ERR; + case FLUSH_MW_BIND_ERR: + return IB_WC_MW_BIND_ERR; + case FLUSH_REM_INV_REQ_ERR: + return IB_WC_REM_INV_REQ_ERR; + case FLUSH_RETRY_EXC_ERR: + return IB_WC_RETRY_EXC_ERR; + case FLUSH_RNR_RETRY_EXC_ERR: + return IB_WC_RNR_RETRY_EXC_ERR; + case FLUSH_FATAL_ERR: + default: + return IB_WC_FATAL_ERR; + } +} + +/** + * irdma_process_cqe - process cqe info + * @entry: processed cqe + * @cq_poll_info: cqe info + */ +static void irdma_process_cqe(struct ib_wc *entry, + struct irdma_cq_poll_info *cq_poll_info) +{ + struct irdma_sc_qp *qp; + + entry->wc_flags = 0; + entry->pkey_index = 0; + entry->wr_id = cq_poll_info->wr_id; + + qp = cq_poll_info->qp_handle; + entry->qp = qp->qp_uk.back_qp; + + if (cq_poll_info->error) { + entry->status = (cq_poll_info->comp_status == IRDMA_COMPL_STATUS_FLUSHED) ? + irdma_flush_err_to_ib_wc_status(cq_poll_info->minor_err) : IB_WC_GENERAL_ERR; + + entry->vendor_err = cq_poll_info->major_err << 16 | + cq_poll_info->minor_err; + } else { + entry->status = IB_WC_SUCCESS; + if (cq_poll_info->imm_valid) { + entry->ex.imm_data = htonl(cq_poll_info->imm_data); + entry->wc_flags |= IB_WC_WITH_IMM; + } + if (cq_poll_info->ud_smac_valid) { + ether_addr_copy(entry->smac, cq_poll_info->ud_smac); + entry->wc_flags |= IB_WC_WITH_SMAC; + } + + if (cq_poll_info->ud_vlan_valid && + dev_to_rf(qp->dev)->vlan_parse_en) { + u16 vlan = cq_poll_info->ud_vlan & VLAN_VID_MASK; + + entry->sl = cq_poll_info->ud_vlan >> VLAN_PRIO_SHIFT; + if (vlan) { + entry->vlan_id = vlan; + entry->wc_flags |= IB_WC_WITH_VLAN; + } + } else { + entry->sl = 0; + } + } + + if (cq_poll_info->q_type == IRDMA_CQE_QTYPE_SQ) { + set_ib_wc_op_sq(cq_poll_info, entry); + } else { + if (qp->dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) + set_ib_wc_op_rq(cq_poll_info, entry, + qp->qp_uk.qp_caps & IRDMA_SEND_WITH_IMM ? + true : false); + else + set_ib_wc_op_rq_gen_3(cq_poll_info, entry); + if (qp->qp_uk.qp_type != IRDMA_QP_TYPE_ROCE_UD && + cq_poll_info->stag_invalid_set) { + entry->ex.invalidate_rkey = cq_poll_info->inv_stag; + entry->wc_flags |= IB_WC_WITH_INVALIDATE; + } + } + + if (qp->qp_uk.qp_type == IRDMA_QP_TYPE_ROCE_UD) { + entry->src_qp = cq_poll_info->ud_src_qpn; + entry->slid = 0; + entry->wc_flags |= + (IB_WC_GRH | IB_WC_WITH_NETWORK_HDR_TYPE); + entry->network_hdr_type = cq_poll_info->ipv4 ? + RDMA_NETWORK_IPV4 : + RDMA_NETWORK_IPV6; + } else { + entry->src_qp = cq_poll_info->qp_id; + } + + entry->byte_len = cq_poll_info->bytes_xfered; +} + +/** + * irdma_poll_one - poll one entry of the CQ + * @ukcq: ukcq to poll + * @cur_cqe: current CQE info to be filled in + * @entry: ibv_wc object to be filled for non-extended CQ or NULL for extended CQ + * + * Returns the internal irdma device error code or 0 on success + */ +static inline int irdma_poll_one(struct irdma_cq_uk *ukcq, + struct irdma_cq_poll_info *cur_cqe, + struct ib_wc *entry) +{ + int ret = irdma_uk_cq_poll_cmpl(ukcq, cur_cqe); + + if (ret) + return ret; + + irdma_process_cqe(entry, cur_cqe); + + return 0; +} + +/** + * __irdma_poll_cq - poll cq for completion (kernel apps) + * @iwcq: cq to poll + * @num_entries: number of entries to poll + * @entry: wr of a completed entry + */ +static int __irdma_poll_cq(struct irdma_cq *iwcq, int num_entries, struct ib_wc *entry) +{ + struct list_head *tmp_node, *list_node; + struct irdma_cq_buf *last_buf = NULL; + struct irdma_cq_poll_info *cur_cqe = &iwcq->cur_cqe; + struct irdma_cq_buf *cq_buf; + int ret; + struct irdma_device *iwdev; + struct irdma_cq_uk *ukcq; + bool cq_new_cqe = false; + int resized_bufs = 0; + int npolled = 0; + + iwdev = to_iwdev(iwcq->ibcq.device); + ukcq = &iwcq->sc_cq.cq_uk; + + /* go through the list of previously resized CQ buffers */ + list_for_each_safe(list_node, tmp_node, &iwcq->resize_list) { + cq_buf = container_of(list_node, struct irdma_cq_buf, list); + while (npolled < num_entries) { + ret = irdma_poll_one(&cq_buf->cq_uk, cur_cqe, entry + npolled); + if (!ret) { + ++npolled; + cq_new_cqe = true; + continue; + } + if (ret == -ENOENT) + break; + /* QP using the CQ is destroyed. Skip reporting this CQE */ + if (ret == -EFAULT) { + cq_new_cqe = true; + continue; + } + goto error; + } + + /* save the resized CQ buffer which received the last cqe */ + if (cq_new_cqe) + last_buf = cq_buf; + cq_new_cqe = false; + } + + /* check the current CQ for new cqes */ + while (npolled < num_entries) { + ret = irdma_poll_one(ukcq, cur_cqe, entry + npolled); + if (ret == -ENOENT) { + ret = irdma_generated_cmpls(iwcq, cur_cqe); + if (!ret) + irdma_process_cqe(entry + npolled, cur_cqe); + } + if (!ret) { + ++npolled; + cq_new_cqe = true; + continue; + } + + if (ret == -ENOENT) + break; + /* QP using the CQ is destroyed. Skip reporting this CQE */ + if (ret == -EFAULT) { + cq_new_cqe = true; + continue; + } + goto error; + } + + if (cq_new_cqe) + /* all previous CQ resizes are complete */ + resized_bufs = irdma_process_resize_list(iwcq, iwdev, NULL); + else if (last_buf) + /* only CQ resizes up to the last_buf are complete */ + resized_bufs = irdma_process_resize_list(iwcq, iwdev, last_buf); + if (resized_bufs) + /* report to the HW the number of complete CQ resizes */ + irdma_uk_cq_set_resized_cnt(ukcq, resized_bufs); + + return npolled; +error: + ibdev_dbg(&iwdev->ibdev, "VERBS: %s: Error polling CQ, irdma_err: %d\n", + __func__, ret); + + return ret; +} + +/** + * irdma_poll_cq - poll cq for completion (kernel apps) + * @ibcq: cq to poll + * @num_entries: number of entries to poll + * @entry: wr of a completed entry + */ +static int irdma_poll_cq(struct ib_cq *ibcq, int num_entries, + struct ib_wc *entry) +{ + struct irdma_cq *iwcq; + unsigned long flags; + int ret; + + iwcq = to_iwcq(ibcq); + + spin_lock_irqsave(&iwcq->lock, flags); + ret = __irdma_poll_cq(iwcq, num_entries, entry); + spin_unlock_irqrestore(&iwcq->lock, flags); + + return ret; +} + +/** + * irdma_req_notify_cq - arm cq kernel application + * @ibcq: cq to arm + * @notify_flags: notofication flags + */ +static int irdma_req_notify_cq(struct ib_cq *ibcq, + enum ib_cq_notify_flags notify_flags) +{ + struct irdma_cq *iwcq; + struct irdma_cq_uk *ukcq; + unsigned long flags; + enum irdma_cmpl_notify cq_notify = IRDMA_CQ_COMPL_EVENT; + bool promo_event = false; + int ret = 0; + + iwcq = to_iwcq(ibcq); + ukcq = &iwcq->sc_cq.cq_uk; + + spin_lock_irqsave(&iwcq->lock, flags); + if (notify_flags == IB_CQ_SOLICITED) { + cq_notify = IRDMA_CQ_COMPL_SOLICITED; + } else { + if (iwcq->last_notify == IRDMA_CQ_COMPL_SOLICITED) + promo_event = true; + } + + if (!atomic_cmpxchg(&iwcq->armed, 0, 1) || promo_event) { + iwcq->last_notify = cq_notify; + irdma_uk_cq_request_notification(ukcq, cq_notify); + } + + if ((notify_flags & IB_CQ_REPORT_MISSED_EVENTS) && + (!irdma_cq_empty(iwcq) || !list_empty(&iwcq->cmpl_generated))) + ret = 1; + spin_unlock_irqrestore(&iwcq->lock, flags); + + return ret; +} + +#ifdef ALLOC_HW_STATS_STRUCT_V2 +const struct rdma_stat_desc irdma_hw_stat_descs[] = { + /* gen1 - 32-bit */ + [IRDMA_HW_STAT_INDEX_IP4RXDISCARD].name = "ip4InDiscards", + [IRDMA_HW_STAT_INDEX_IP4RXTRUNC].name = "ip4InTruncatedPkts", + [IRDMA_HW_STAT_INDEX_IP4TXNOROUTE].name = "ip4OutNoRoutes", + [IRDMA_HW_STAT_INDEX_IP6RXDISCARD].name = "ip6InDiscards", + [IRDMA_HW_STAT_INDEX_IP6RXTRUNC].name = "ip6InTruncatedPkts", + [IRDMA_HW_STAT_INDEX_IP6TXNOROUTE].name = "ip6OutNoRoutes", + [IRDMA_HW_STAT_INDEX_RXVLANERR].name = "rxVlanErrors", + /* gen1 - 64-bit */ + [IRDMA_HW_STAT_INDEX_IP4RXOCTS].name = "ip4InOctets", + [IRDMA_HW_STAT_INDEX_IP4RXPKTS].name = "ip4InPkts", + [IRDMA_HW_STAT_INDEX_IP4RXFRAGS].name = "ip4InReasmRqd", + [IRDMA_HW_STAT_INDEX_IP4RXMCPKTS].name = "ip4InMcastPkts", + [IRDMA_HW_STAT_INDEX_IP4TXOCTS].name = "ip4OutOctets", + [IRDMA_HW_STAT_INDEX_IP4TXPKTS].name = "ip4OutPkts", + [IRDMA_HW_STAT_INDEX_IP4TXFRAGS].name = "ip4OutSegRqd", + [IRDMA_HW_STAT_INDEX_IP4TXMCPKTS].name = "ip4OutMcastPkts", + [IRDMA_HW_STAT_INDEX_IP6RXOCTS].name = "ip6InOctets", + [IRDMA_HW_STAT_INDEX_IP6RXPKTS].name = "ip6InPkts", + [IRDMA_HW_STAT_INDEX_IP6RXFRAGS].name = "ip6InReasmRqd", + [IRDMA_HW_STAT_INDEX_IP6RXMCPKTS].name = "ip6InMcastPkts", + [IRDMA_HW_STAT_INDEX_IP6TXOCTS].name = "ip6OutOctets", + [IRDMA_HW_STAT_INDEX_IP6TXPKTS].name = "ip6OutPkts", + [IRDMA_HW_STAT_INDEX_IP6TXFRAGS].name = "ip6OutSegRqd", + [IRDMA_HW_STAT_INDEX_IP6TXMCPKTS].name = "ip6OutMcastPkts", + [IRDMA_HW_STAT_INDEX_RDMARXRDS].name = "InRdmaReads", + [IRDMA_HW_STAT_INDEX_RDMARXSNDS].name = "InRdmaSends", + [IRDMA_HW_STAT_INDEX_RDMARXWRS].name = "InRdmaWrites", + [IRDMA_HW_STAT_INDEX_RDMATXRDS].name = "OutRdmaReads", + [IRDMA_HW_STAT_INDEX_RDMATXSNDS].name = "OutRdmaSends", + [IRDMA_HW_STAT_INDEX_RDMATXWRS].name = "OutRdmaWrites", + [IRDMA_HW_STAT_INDEX_RDMAVBND].name = "RdmaBnd", + [IRDMA_HW_STAT_INDEX_RDMAVINV].name = "RdmaInv", + + /* gen2 - 32-bit */ + [IRDMA_HW_STAT_INDEX_RXRPCNPHANDLED].name = "cnpHandled", + [IRDMA_HW_STAT_INDEX_RXRPCNPIGNORED].name = "cnpIgnored", + [IRDMA_HW_STAT_INDEX_TXNPCNPSENT].name = "cnpSent", + /* gen2 - 64-bit */ + [IRDMA_HW_STAT_INDEX_IP4RXMCOCTS].name = "ip4InMcastOctets", + [IRDMA_HW_STAT_INDEX_IP4TXMCOCTS].name = "ip4OutMcastOctets", + [IRDMA_HW_STAT_INDEX_IP6RXMCOCTS].name = "ip6InMcastOctets", + [IRDMA_HW_STAT_INDEX_IP6TXMCOCTS].name = "ip6OutMcastOctets", + [IRDMA_HW_STAT_INDEX_UDPRXPKTS].name = "RxUDP", + [IRDMA_HW_STAT_INDEX_UDPTXPKTS].name = "TxUDP", + [IRDMA_HW_STAT_INDEX_RXNPECNMARKEDPKTS].name = "RxECNMrkd", + [IRDMA_HW_STAT_INDEX_TCPRTXSEG].name = "RetransSegs", + [IRDMA_HW_STAT_INDEX_TCPRXOPTERR].name = "InOptErrors", + [IRDMA_HW_STAT_INDEX_TCPRXPROTOERR].name = "InProtoErrors", + [IRDMA_HW_STAT_INDEX_TCPRXSEGS].name = "InSegs", + [IRDMA_HW_STAT_INDEX_TCPTXSEG].name = "OutSegs", + + /* gen3 */ + [IRDMA_HW_STAT_INDEX_RNR_SENT].name = "RNR sent", + [IRDMA_HW_STAT_INDEX_RNR_RCVD].name = "RNR received", + [IRDMA_HW_STAT_INDEX_RDMAORDLMTCNT].name = "ord limit count", + [IRDMA_HW_STAT_INDEX_RDMAIRDLMTCNT].name = "ird limit count", + [IRDMA_HW_STAT_INDEX_RDMARXATS].name = "Rx ATS", + [IRDMA_HW_STAT_INDEX_RDMATXATS].name = "Tx ATS", + [IRDMA_HW_STAT_INDEX_NAKSEQERR].name = "Nak Sequence Error", + [IRDMA_HW_STAT_INDEX_NAKSEQERR_IMPLIED].name = "Nak Sequence Error Implied", + [IRDMA_HW_STAT_INDEX_RTO].name = "RTO", + [IRDMA_HW_STAT_INDEX_RXOOOPKTS].name = "Rcvd Out of order packets", + [IRDMA_HW_STAT_INDEX_ICRCERR].name = "CRC errors", +}; + +#endif /* ALLOC_HW_STATS_STRUCT_V2 */ +/** + * mcast_list_add - Add a new mcast item to list + * @rf: RDMA PCI function + * @new_elem: pointer to element to add + */ +static void mcast_list_add(struct irdma_pci_f *rf, + struct mc_table_list *new_elem) +{ + list_add(&new_elem->list, &rf->mc_qht_list.list); +} + +/** + * mcast_list_del - Remove an mcast item from list + * @mc_qht_elem: pointer to mcast table list element + */ +static void mcast_list_del(struct mc_table_list *mc_qht_elem) +{ + if (mc_qht_elem) + list_del(&mc_qht_elem->list); +} + +/** + * mcast_list_lookup_ip - Search mcast list for address + * @rf: RDMA PCI function + * @ip_mcast: pointer to mcast IP address + */ +static struct mc_table_list *mcast_list_lookup_ip(struct irdma_pci_f *rf, + u32 *ip_mcast) +{ + struct mc_table_list *mc_qht_el; + struct list_head *pos, *q; + + list_for_each_safe (pos, q, &rf->mc_qht_list.list) { + mc_qht_el = list_entry(pos, struct mc_table_list, list); + if (!memcmp(mc_qht_el->mc_info.dest_ip, ip_mcast, + sizeof(mc_qht_el->mc_info.dest_ip))) + return mc_qht_el; + } + + return NULL; +} + +/** + * irdma_mcast_cqp_op - perform a mcast cqp operation + * @iwdev: irdma device + * @mc_grp_ctx: mcast group info + * @op: operation + * + * returns error status + */ +static int irdma_mcast_cqp_op(struct irdma_device *iwdev, + struct irdma_mcast_grp_info *mc_grp_ctx, u8 op) +{ + struct cqp_cmds_info *cqp_info; + struct irdma_cqp_request *cqp_request; + int status; + + cqp_request = irdma_alloc_and_get_cqp_request(&iwdev->rf->cqp, true); + if (!cqp_request) + return -ENOMEM; + + cqp_request->info.in.u.mc_create.info = *mc_grp_ctx; + cqp_info = &cqp_request->info; + cqp_info->cqp_cmd = op; + cqp_info->post_sq = 1; + cqp_info->in.u.mc_create.scratch = (uintptr_t)cqp_request; + cqp_info->in.u.mc_create.cqp = &iwdev->rf->cqp.sc_cqp; + status = irdma_handle_cqp_op(iwdev->rf, cqp_request); + irdma_put_cqp_request(&iwdev->rf->cqp, cqp_request); + + return status; +} + +/** + * irdma_attach_mcast - attach a qp to a multicast group + * @ibqp: ptr to qp + * @ibgid: pointer to global ID + * @lid: local ID + * + * returns error status + */ +static int irdma_attach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid) +{ + struct irdma_qp *iwqp = to_iwqp(ibqp); + struct irdma_device *iwdev = iwqp->iwdev; + struct irdma_pci_f *rf = iwdev->rf; + struct mc_table_list *mc_qht_elem; + struct irdma_mcast_grp_ctx_entry_info mcg_info = {}; + unsigned long flags; + u32 ip_addr[4] = {}; + u32 mgn; + u32 no_mgs; + int ret = 0; + bool ipv4; + u16 vlan_id; + union irdma_sockaddr sgid_addr; + unsigned char dmac[ETH_ALEN]; + + rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid); + + if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid)) { + irdma_copy_ip_ntohl(ip_addr, + sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32); + irdma_get_vlan_mac_ipv6(ip_addr, &vlan_id, NULL); + ipv4 = false; + ibdev_dbg(&iwdev->ibdev, + "VERBS: qp_id=%d, IP6address=%pI6\n", ibqp->qp_num, + ip_addr); + irdma_mcast_mac_v6(ip_addr, dmac); + } else { + ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr); + ipv4 = true; + vlan_id = irdma_get_vlan_ipv4(ip_addr); + irdma_mcast_mac_v4(ip_addr, dmac); + ibdev_dbg(&iwdev->ibdev, + "VERBS: qp_id=%d, IP4address=%pI4, MAC=%pM\n", + ibqp->qp_num, ip_addr, dmac); + } + + spin_lock_irqsave(&rf->qh_list_lock, flags); + mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr); + if (!mc_qht_elem) { + struct irdma_dma_mem *dma_mem_mc; + + spin_unlock_irqrestore(&rf->qh_list_lock, flags); + mc_qht_elem = kzalloc(sizeof(*mc_qht_elem), GFP_KERNEL); + if (!mc_qht_elem) + return -ENOMEM; + + mc_qht_elem->mc_info.ipv4_valid = ipv4; + memcpy(mc_qht_elem->mc_info.dest_ip, ip_addr, + sizeof(mc_qht_elem->mc_info.dest_ip)); + ret = irdma_alloc_rsrc(rf, rf->allocated_mcgs, rf->max_mcg, + &mgn, &rf->next_mcg); + if (ret) { + kfree(mc_qht_elem); + return -ENOMEM; + } + + mc_qht_elem->mc_info.mgn = mgn; + dma_mem_mc = &mc_qht_elem->mc_grp_ctx.dma_mem_mc; + dma_mem_mc->size = ALIGN(sizeof(u64) * IRDMA_MAX_MGS_PER_CTX, + IRDMA_HW_PAGE_SIZE); + dma_mem_mc->va = dma_alloc_coherent(rf->hw.device, + dma_mem_mc->size, + &dma_mem_mc->pa, + GFP_KERNEL); + if (!dma_mem_mc->va) { + irdma_free_rsrc(rf, rf->allocated_mcgs, mgn); + kfree(mc_qht_elem); + return -ENOMEM; + } + + mc_qht_elem->mc_grp_ctx.mg_id = (u16)mgn; + memcpy(mc_qht_elem->mc_grp_ctx.dest_ip_addr, ip_addr, + sizeof(mc_qht_elem->mc_grp_ctx.dest_ip_addr)); + mc_qht_elem->mc_grp_ctx.ipv4_valid = ipv4; + mc_qht_elem->mc_grp_ctx.vlan_id = vlan_id; + if (vlan_id < VLAN_N_VID) + mc_qht_elem->mc_grp_ctx.vlan_valid = true; + mc_qht_elem->mc_grp_ctx.hmc_fcn_id = iwdev->rf->sc_dev.hmc_fn_id; + mc_qht_elem->mc_grp_ctx.qs_handle = + iwqp->sc_qp.vsi->qos[iwqp->sc_qp.user_pri].qs_handle[iwqp->sc_qp.qs_idx]; + ether_addr_copy(mc_qht_elem->mc_grp_ctx.dest_mac_addr, dmac); + + spin_lock_irqsave(&rf->qh_list_lock, flags); + mcast_list_add(rf, mc_qht_elem); + } else { + if (mc_qht_elem->mc_grp_ctx.no_of_mgs == + IRDMA_MAX_MGS_PER_CTX) { + spin_unlock_irqrestore(&rf->qh_list_lock, flags); + return -ENOMEM; + } + } + + mcg_info.qp_id = iwqp->ibqp.qp_num; + no_mgs = mc_qht_elem->mc_grp_ctx.no_of_mgs; + irdma_sc_add_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info); + spin_unlock_irqrestore(&rf->qh_list_lock, flags); + + /* Only if there is a change do we need to modify or create */ + if (!no_mgs) { + ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx, + IRDMA_OP_MC_CREATE); + } else if (no_mgs != mc_qht_elem->mc_grp_ctx.no_of_mgs) { + ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx, + IRDMA_OP_MC_MODIFY); + } else { + return 0; + } + + if (ret) + goto error; + + return 0; + +error: + irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info); + if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) { + mcast_list_del(mc_qht_elem); + dma_free_coherent(rf->hw.device, + mc_qht_elem->mc_grp_ctx.dma_mem_mc.size, + mc_qht_elem->mc_grp_ctx.dma_mem_mc.va, + mc_qht_elem->mc_grp_ctx.dma_mem_mc.pa); + mc_qht_elem->mc_grp_ctx.dma_mem_mc.va = NULL; + irdma_free_rsrc(rf, rf->allocated_mcgs, + mc_qht_elem->mc_grp_ctx.mg_id); + kfree(mc_qht_elem); + } + + return ret; +} + +/** + * irdma_detach_mcast - detach a qp from a multicast group + * @ibqp: ptr to qp + * @ibgid: pointer to global ID + * @lid: local ID + * + * returns error status + */ +static int irdma_detach_mcast(struct ib_qp *ibqp, union ib_gid *ibgid, u16 lid) +{ + struct irdma_qp *iwqp = to_iwqp(ibqp); + struct irdma_device *iwdev = iwqp->iwdev; + struct irdma_pci_f *rf = iwdev->rf; + u32 ip_addr[4] = {}; + struct mc_table_list *mc_qht_elem; + struct irdma_mcast_grp_ctx_entry_info mcg_info = {}; + int ret; + unsigned long flags; + union irdma_sockaddr sgid_addr; + + rdma_gid2ip((struct sockaddr *)&sgid_addr, ibgid); + if (!ipv6_addr_v4mapped((struct in6_addr *)ibgid)) + irdma_copy_ip_ntohl(ip_addr, + sgid_addr.saddr_in6.sin6_addr.in6_u.u6_addr32); + else + ip_addr[0] = ntohl(sgid_addr.saddr_in.sin_addr.s_addr); + + spin_lock_irqsave(&rf->qh_list_lock, flags); + mc_qht_elem = mcast_list_lookup_ip(rf, ip_addr); + if (!mc_qht_elem) { + spin_unlock_irqrestore(&rf->qh_list_lock, flags); + ibdev_dbg(&iwdev->ibdev, + "VERBS: address not found MCG\n"); + return 0; + } + + mcg_info.qp_id = iwqp->ibqp.qp_num; + irdma_sc_del_mcast_grp(&mc_qht_elem->mc_grp_ctx, &mcg_info); + if (!mc_qht_elem->mc_grp_ctx.no_of_mgs) { + mcast_list_del(mc_qht_elem); + spin_unlock_irqrestore(&rf->qh_list_lock, flags); + ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx, + IRDMA_OP_MC_DESTROY); + if (ret) { + ibdev_dbg(&iwdev->ibdev, + "VERBS: failed MC_DESTROY MCG\n"); + spin_lock_irqsave(&rf->qh_list_lock, flags); + mcast_list_add(rf, mc_qht_elem); + spin_unlock_irqrestore(&rf->qh_list_lock, flags); + return -EAGAIN; + } + + dma_free_coherent(rf->hw.device, + mc_qht_elem->mc_grp_ctx.dma_mem_mc.size, + mc_qht_elem->mc_grp_ctx.dma_mem_mc.va, + mc_qht_elem->mc_grp_ctx.dma_mem_mc.pa); + mc_qht_elem->mc_grp_ctx.dma_mem_mc.va = NULL; + irdma_free_rsrc(rf, rf->allocated_mcgs, + mc_qht_elem->mc_grp_ctx.mg_id); + kfree(mc_qht_elem); + } else { + spin_unlock_irqrestore(&rf->qh_list_lock, flags); + ret = irdma_mcast_cqp_op(iwdev, &mc_qht_elem->mc_grp_ctx, + IRDMA_OP_MC_MODIFY); + if (ret) { + ibdev_dbg(&iwdev->ibdev, + "VERBS: failed Modify MCG\n"); + return ret; + } + } + + return 0; +} + +/** + * irdma_query_ah - Query address handle + * @ibah: pointer to address handle + * @ah_attr: address handle attributes + */ +static int irdma_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr) +{ + struct irdma_ah *ah = to_iwah(ibah); + + memset(ah_attr, 0, sizeof(*ah_attr)); + if (ah->av.attrs.ah_flags & IB_AH_GRH) { + ah_attr->ah_flags = IB_AH_GRH; + ah_attr->grh.flow_label = ah->sc_ah.ah_info.flow_label; + ah_attr->grh.traffic_class = ah->sc_ah.ah_info.tc_tos; + ah_attr->grh.hop_limit = ah->sc_ah.ah_info.hop_ttl; + ah_attr->grh.sgid_index = ah->sgid_index; + ah_attr->grh.sgid_index = ah->sgid_index; + memcpy(&ah_attr->grh.dgid, &ah->dgid, + sizeof(ah_attr->grh.dgid)); + } + + return 0; +} + +#ifdef IB_DEALLOC_DRIVER_SUPPORT +/** + * irdma_ib_dealloc_device + * @ibdev: ib device + * + * callback from ibdev dealloc_driver to deallocate resources + * unber irdma device + */ +static inline void irdma_ib_dealloc_device(struct ib_device *ibdev) +{ + irdma_deinit_device(to_iwdev(ibdev)); +} +#endif + +#ifdef IB_GET_NETDEV_OP_NOT_DEPRECATED +#ifdef GET_NETDEV_OP_V2 +static struct net_device *irdma_get_netdev(struct ib_device *ibdev, u32 port_num) +#else +static struct net_device *irdma_get_netdev(struct ib_device *ibdev, u8 port_num) +#endif +{ + struct irdma_device *iwdev = to_iwdev(ibdev); + + if (iwdev->netdev) { + dev_hold(iwdev->netdev); + return iwdev->netdev; + } + + return NULL; +} + +#endif +#ifdef HAS_IB_SET_DEVICE_OP +static struct ib_device_ops irdma_gen3_dev_ops; +#ifdef IB_DEALLOC_DRIVER_SUPPORT +static struct ib_device_ops irdma_gen1_dev_ops; +#endif /* IB_DEALLOC_DRIVER_SUPPORT */ +static struct ib_device_ops irdma_roce_dev_ops; +static struct ib_device_ops irdma_mcast_ops; +static struct ib_device_ops irdma_iw_dev_ops; +static const struct ib_device_ops irdma_dev_ops = { +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0) || defined(RHEL_8_2) || defined(RHEL_8_3) || defined(RHEL_8_4) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) + .owner = THIS_MODULE, + .driver_id = RDMA_DRIVER_I40IW, + .uverbs_abi_ver = IRDMA_ABI_VER, +#endif +#if defined(ALLOC_HW_STATS_V3) + .alloc_hw_port_stats = irdma_alloc_hw_port_stats, +#else + .alloc_hw_stats = irdma_alloc_hw_stats, +#endif + .alloc_mr = irdma_alloc_mr, + .alloc_pd = irdma_alloc_pd, + .alloc_ucontext = irdma_alloc_ucontext, + .create_cq = irdma_create_cq, + .create_qp = irdma_create_qp, + .dealloc_pd = irdma_dealloc_pd, + .dealloc_ucontext = irdma_dealloc_ucontext, + .dereg_mr = irdma_dereg_mr, + .destroy_cq = irdma_destroy_cq, + .destroy_qp = irdma_destroy_qp, + .disassociate_ucontext = irdma_disassociate_ucontext, + .get_dev_fw_str = irdma_get_dev_fw_str, + .get_dma_mr = irdma_get_dma_mr, + .get_hw_stats = irdma_get_hw_stats, +#ifdef IB_GET_NETDEV_OP_NOT_DEPRECATED + .get_netdev = irdma_get_netdev, +#endif + .map_mr_sg = irdma_map_mr_sg, + .mmap = irdma_mmap, +#ifdef RDMA_MMAP_DB_SUPPORT + .mmap_free = irdma_mmap_free, +#endif + .poll_cq = irdma_poll_cq, + .post_recv = irdma_post_recv, + .post_send = irdma_post_send, + .query_device = irdma_query_device, + .query_port = irdma_query_port, + .modify_port = irdma_modify_port, + .query_qp = irdma_query_qp, +#ifdef SET_DMABUF + .reg_user_mr_dmabuf = irdma_reg_user_mr_dmabuf, +#endif + .reg_user_mr = irdma_reg_user_mr, + .rereg_user_mr = irdma_rereg_user_mr, + .req_notify_cq = irdma_req_notify_cq, + .resize_cq = irdma_resize_cq, +#ifdef INIT_RDMA_OBJ_SIZE + INIT_RDMA_OBJ_SIZE(ib_pd, irdma_pd, ibpd), + INIT_RDMA_OBJ_SIZE(ib_ucontext, irdma_ucontext, ibucontext), +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) || defined(RHEL_8_2) || defined(RHEL_8_3) || defined(RHEL_8_4) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) + INIT_RDMA_OBJ_SIZE(ib_ah, irdma_ah, ibah), + INIT_RDMA_OBJ_SIZE(ib_srq, irdma_srq, ibsrq), +#endif /* 5.2.0 */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 3, 0) || defined(RHEL_8_2) || defined(RHEL_8_3) || defined(RHEL_8_4) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) + INIT_RDMA_OBJ_SIZE(ib_cq, irdma_cq, ibcq), +#endif /* 5.3.0 */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) + INIT_RDMA_OBJ_SIZE(ib_mw, irdma_mr, ibmw), +#endif /* 5.10.0 */ +#ifdef GLOBAL_QP_MEM + INIT_RDMA_OBJ_SIZE(ib_qp, irdma_qp, ibqp), +#endif /* GLOBAL_QP_MEM */ +#endif /* INIT_RDMA_OBJ_SIZE */ +}; + +#endif /* HAS_IB_SET_DEVICE_OP */ +static void irdma_set_device_ops(struct ib_device *ibdev) +{ +#ifndef HAS_IB_SET_DEVICE_OP + struct ib_device *dev_ops = ibdev; + +#if defined(RHEL_7_7) || defined(RHEL_7_8) || defined(RHEL_7_9) || defined(RHEL_8_2) || defined(RHEL_8_3) || defined(RHEL_8_4) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) + dev_ops->uverbs_abi_ver = IRDMA_ABI_VER; + dev_ops->driver_id = RDMA_DRIVER_I40IW; + dev_ops->owner = THIS_MODULE; +#endif + dev_ops->alloc_hw_stats = irdma_alloc_hw_stats; + dev_ops->alloc_mr = irdma_alloc_mr; + dev_ops->alloc_pd = irdma_alloc_pd; + dev_ops->alloc_ucontext = irdma_alloc_ucontext; + dev_ops->create_cq = irdma_create_cq; + dev_ops->create_qp = irdma_create_qp; + dev_ops->dealloc_pd = irdma_dealloc_pd; + dev_ops->dealloc_ucontext = irdma_dealloc_ucontext; + dev_ops->dereg_mr = irdma_dereg_mr; + dev_ops->destroy_cq = irdma_destroy_cq; + dev_ops->destroy_qp = irdma_destroy_qp; + dev_ops->disassociate_ucontext = irdma_disassociate_ucontext; + dev_ops->get_dev_fw_str = irdma_get_dev_fw_str; + dev_ops->get_dma_mr = irdma_get_dma_mr; + dev_ops->get_hw_stats = irdma_get_hw_stats; + dev_ops->get_netdev = irdma_get_netdev; + dev_ops->map_mr_sg = irdma_map_mr_sg; + dev_ops->mmap = irdma_mmap; +#ifdef RDMA_MMAP_DB_SUPPORT + dev_ops->mmap_free = irdma_mmap_free; +#endif + dev_ops->poll_cq = irdma_poll_cq; + dev_ops->post_recv = irdma_post_recv; + dev_ops->post_send = irdma_post_send; + dev_ops->query_device = irdma_query_device; + dev_ops->query_port = irdma_query_port; + dev_ops->modify_port = irdma_modify_port; + dev_ops->query_qp = irdma_query_qp; +#ifdef SET_DMABUF + dev_ops->reg_user_mr_dmabuf = irdma_reg_user_mr_dmabuf, +#endif + dev_ops->reg_user_mr = irdma_reg_user_mr; + dev_ops->rereg_user_mr = irdma_rereg_user_mr; + dev_ops->req_notify_cq = irdma_req_notify_cq; + dev_ops->resize_cq = irdma_resize_cq; + dev_ops->create_srq = irdma_create_srq; + dev_ops->destroy_srq = irdma_destroy_srq; + dev_ops->modify_srq = irdma_modify_srq; + dev_ops->query_srq = irdma_query_srq; + dev_ops->post_srq_recv = irdma_post_srq_recv; +#else /* !HAS_IB_SET_DEVICE_OP */ + ib_set_device_ops(ibdev, &irdma_dev_ops); +#endif /* !HAS_IB_SET_DEVICE_OP */ +} + +static void irdma_set_device_mcast_ops(struct ib_device *ibdev) +{ +#ifdef HAS_IB_SET_DEVICE_OP + struct ib_device_ops *dev_ops = &irdma_mcast_ops; +#else + struct ib_device *dev_ops = ibdev; +#endif + dev_ops->attach_mcast = irdma_attach_mcast; + dev_ops->detach_mcast = irdma_detach_mcast; +#ifdef HAS_IB_SET_DEVICE_OP + ib_set_device_ops(ibdev, &irdma_mcast_ops); +#endif +} + +static void irdma_set_device_roce_ops(struct ib_device *ibdev) +{ +#ifdef HAS_IB_SET_DEVICE_OP + struct ib_device_ops *dev_ops = &irdma_roce_dev_ops; +#else + struct ib_device *dev_ops = ibdev; +#endif + dev_ops->create_ah = irdma_create_ah; +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 11, 0) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) + dev_ops->create_user_ah = irdma_create_ah; +#endif + dev_ops->destroy_ah = irdma_destroy_ah; + dev_ops->get_link_layer = irdma_get_link_layer; + dev_ops->get_port_immutable = irdma_roce_port_immutable; + dev_ops->modify_qp = irdma_modify_qp_roce; + dev_ops->query_ah = irdma_query_ah; + dev_ops->query_gid = irdma_query_gid_roce; + dev_ops->query_pkey = irdma_query_pkey; + kc_set_ibdev_add_del_gid(ibdev); +#ifdef HAS_IB_SET_DEVICE_OP + ib_set_device_ops(ibdev, &irdma_roce_dev_ops); +#endif +} + +static void irdma_set_device_iw_ops(struct ib_device *ibdev) +{ +#ifdef HAS_IB_SET_DEVICE_OP + struct ib_device_ops *dev_ops = &irdma_iw_dev_ops; +#else + struct ib_device *dev_ops = ibdev; +#endif + +#ifdef IB_IW_MANDATORY_AH_OP + ibdev->uverbs_cmd_mask |= + (1ull << IB_USER_VERBS_CMD_CREATE_AH) | + (1ull << IB_USER_VERBS_CMD_DESTROY_AH); + + dev_ops->create_ah = irdma_create_ah_stub; + dev_ops->destroy_ah = irdma_destroy_ah_stub; +#endif + dev_ops->get_port_immutable = irdma_iw_port_immutable; + dev_ops->modify_qp = irdma_modify_qp; + dev_ops->query_gid = irdma_query_gid; +#ifdef IB_IW_PKEY + dev_ops->query_pkey = irdma_iw_query_pkey; +#endif +#ifdef HAS_IB_SET_DEVICE_OP + ib_set_device_ops(ibdev, &irdma_iw_dev_ops); +#endif +} + +static inline void irdma_set_device_gen1_ops(struct ib_device *ibdev) +{ +#ifdef IB_DEALLOC_DRIVER_SUPPORT +#ifdef HAS_IB_SET_DEVICE_OP + struct ib_device_ops *dev_ops = &irdma_gen1_dev_ops; +#else + struct ib_device *dev_ops = ibdev; +#endif + dev_ops->dealloc_driver = irdma_ib_dealloc_device, +#ifdef HAS_IB_SET_DEVICE_OP + ib_set_device_ops(ibdev, &irdma_gen1_dev_ops); +#endif +#endif /* IB_DEALLOC_DRIVER_SUPPORT */ +} + +static inline void irdma_set_device_gen3_ops(struct ib_device *ibdev) +{ +#ifdef HAS_IB_SET_DEVICE_OP + struct ib_device_ops *dev_ops = &irdma_gen3_dev_ops; +#else + struct ib_device *dev_ops = ibdev; +#endif + dev_ops->alloc_mw = irdma_alloc_mw, + dev_ops->dealloc_mw = irdma_dealloc_mw, + dev_ops->create_srq = irdma_create_srq; + dev_ops->destroy_srq = irdma_destroy_srq; + dev_ops->modify_srq = irdma_modify_srq; + dev_ops->query_srq = irdma_query_srq; + dev_ops->post_srq_recv = irdma_post_srq_recv; +#ifdef HAS_IB_SET_DEVICE_OP + ib_set_device_ops(ibdev, &irdma_gen3_dev_ops); +#endif +} + +/** + * irdma_init_roce_device - initialization of roce rdma device + * @iwdev: irdma device + */ +static void irdma_init_roce_device(struct irdma_device *iwdev) +{ +#ifdef UVERBS_CMD_MASK + kc_set_roce_uverbs_cmd_mask(iwdev); +#endif + iwdev->ibdev.node_type = RDMA_NODE_IB_CA; + addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid, + iwdev->netdev->dev_addr); + irdma_set_device_roce_ops(&iwdev->ibdev); + if (iwdev->rf->rdma_ver == IRDMA_GEN_2) + irdma_set_device_mcast_ops(&iwdev->ibdev); +} + +/** + * irdma_init_iw_device - initialization of iwarp rdma device + * @iwdev: irdma device + */ +static int irdma_init_iw_device(struct irdma_device *iwdev) +{ + struct net_device *netdev = iwdev->netdev; + + iwdev->ibdev.node_type = RDMA_NODE_RNIC; + addrconf_addr_eui48((u8 *)&iwdev->ibdev.node_guid, + netdev->dev_addr); +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 2, 0) || defined(RHEL_8_2) || defined(RHEL_8_3) || defined(RHEL_8_4) || defined(RHEL_8_5) || defined(RHEL_8_6) || defined(RHEL_8_7) || defined(RHEL_8_8) + iwdev->ibdev.ops.iw_add_ref = irdma_qp_add_ref; + iwdev->ibdev.ops.iw_rem_ref = irdma_qp_rem_ref; + iwdev->ibdev.ops.iw_get_qp = irdma_get_qp; + iwdev->ibdev.ops.iw_connect = irdma_connect; + iwdev->ibdev.ops.iw_accept = irdma_accept; + iwdev->ibdev.ops.iw_reject = irdma_reject; + iwdev->ibdev.ops.iw_create_listen = irdma_create_listen; + iwdev->ibdev.ops.iw_destroy_listen = irdma_destroy_listen; + memcpy(iwdev->ibdev.iw_ifname, netdev->name, + sizeof(iwdev->ibdev.iw_ifname)); +#else + iwdev->ibdev.iwcm = kzalloc(sizeof(*iwdev->ibdev.iwcm), GFP_KERNEL); + if (!iwdev->ibdev.iwcm) + return -ENOMEM; + + iwdev->ibdev.iwcm->add_ref = irdma_qp_add_ref; + iwdev->ibdev.iwcm->rem_ref = irdma_qp_rem_ref; + iwdev->ibdev.iwcm->get_qp = irdma_get_qp; + iwdev->ibdev.iwcm->connect = irdma_connect; + iwdev->ibdev.iwcm->accept = irdma_accept; + iwdev->ibdev.iwcm->reject = irdma_reject; + iwdev->ibdev.iwcm->create_listen = irdma_create_listen; + iwdev->ibdev.iwcm->destroy_listen = irdma_destroy_listen; + memcpy(iwdev->ibdev.iwcm->ifname, netdev->name, + sizeof(iwdev->ibdev.iwcm->ifname)); +#endif + irdma_set_device_iw_ops(&iwdev->ibdev); + + return 0; +} + +/** + * irdma_init_rdma_device - initialization of rdma device + * @iwdev: irdma device + */ +static int irdma_init_rdma_device(struct irdma_device *iwdev) +{ + int ret; + +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 3, 0) && !defined(RHEL_8_2) && !defined(RHEL_8_3) && !defined(RHEL_8_4) && !defined(RHEL_8_5) && !defined(RHEL_8_6) && !defined(RHEL_8_7) && !defined(RHEL_8_8) + iwdev->ibdev.owner = THIS_MODULE; + iwdev->ibdev.uverbs_abi_ver = IRDMA_ABI_VER; +#endif +#ifdef UVERBS_CMD_MASK + kc_set_rdma_uverbs_cmd_mask(iwdev); +#endif + + if (iwdev->roce_mode) { + irdma_init_roce_device(iwdev); + } else { + ret = irdma_init_iw_device(iwdev); + if (ret) + return ret; + } + + iwdev->ibdev.phys_port_cnt = 1; + iwdev->ibdev.num_comp_vectors = iwdev->rf->ceqs_count; + iwdev->ibdev.dev.parent = &iwdev->rf->pcidev->dev; + set_ibdev_dma_device(iwdev->ibdev, &iwdev->rf->pcidev->dev); + irdma_set_device_ops(&iwdev->ibdev); + if (iwdev->rf->rdma_ver == IRDMA_GEN_1) + irdma_set_device_gen1_ops(&iwdev->ibdev); + if (iwdev->rf->rdma_ver >= IRDMA_GEN_3) + irdma_set_device_gen3_ops(&iwdev->ibdev); + + return 0; +} + +/** + * irdma_port_ibevent - indicate port event + * @iwdev: irdma device + */ +void irdma_port_ibevent(struct irdma_device *iwdev) +{ + struct ib_event event; + + event.device = &iwdev->ibdev; + event.element.port_num = 1; + event.event = + iwdev->iw_status ? IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR; + ib_dispatch_event(&event); +} + +/** + * irdma_ib_unregister_device - unregister rdma device from IB + * core + * @iwdev: irdma device + */ +void irdma_ib_unregister_device(struct irdma_device *iwdev) +{ + iwdev->iw_status = 0; + irdma_port_ibevent(iwdev); + ib_unregister_device(&iwdev->ibdev); +#ifndef NETDEV_TO_IBDEV_SUPPORT + dev_put(iwdev->netdev); +#endif + irdma_release_ib_devname(iwdev); +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) && !defined(RHEL_8_2) && !defined(RHEL_8_3) && !defined(RHEL_8_4) && !defined(RHEL_8_5) && !defined(RHEL_8_6) && !defined(RHEL_8_7) && !defined(RHEL_8_8) + kfree(iwdev->ibdev.iwcm); + iwdev->ibdev.iwcm = NULL; +#endif +} + +/** + * irdma_ib_register_device - register irdma device to IB core + * @iwdev: irdma device + */ +int irdma_ib_register_device(struct irdma_device *iwdev) +{ + const char *name = irdma_set_ib_devname(iwdev); + int ret; + + ret = irdma_init_rdma_device(iwdev); + if (ret) + return ret; + + kc_set_driver_id(iwdev->ibdev); +#ifdef NETDEV_TO_IBDEV_SUPPORT + ret = ib_device_set_netdev(&iwdev->ibdev, iwdev->netdev, 1); + if (ret) + goto error; +#else + dev_hold(iwdev->netdev); +#endif +#if LINUX_VERSION_CODE < KERNEL_VERSION(4, 20, 0) +#ifdef CONFIG_SUSE_KERNEL +#if SLE_VERSION_CODE <= SLE_VERSION(15, 0, 0) + strlcpy(iwdev->ibdev.name, name, sizeof(iwdev->ibdev.name)); +#endif /* SLE_VERSION_CODE */ +#else + strlcpy(iwdev->ibdev.name, name, sizeof(iwdev->ibdev.name)); +#endif /* CONFIG_SUSE_KERNEL */ +#endif /* LINUX_VERSION_CODE */ +#if LINUX_VERSION_CODE >= KERNEL_VERSION(5, 10, 0) + dma_set_max_seg_size(iwdev->rf->hw.device, UINT_MAX); +#endif + ret = kc_ib_register_device(&iwdev->ibdev, name, iwdev->rf->hw.device); + if (ret) + goto error; + + iwdev->iw_status = 1; + irdma_port_ibevent(iwdev); + + return 0; + +error: +#if LINUX_VERSION_CODE < KERNEL_VERSION(5, 2, 0) && !defined(RHEL_8_2) && !defined(RHEL_8_3) && !defined(RHEL_8_4) && !defined(RHEL_8_5) && !defined(RHEL_8_6) && !defined(RHEL_8_7) && !defined(RHEL_8_8) + kfree(iwdev->ibdev.iwcm); + iwdev->ibdev.iwcm = NULL; +#endif + ibdev_dbg(&iwdev->ibdev, "VERBS: Register RDMA device fail\n"); + + return ret; +} + diff --git a/drivers/intel/irdma-1.14.33/src/irdma/verbs.h b/drivers/intel/irdma-1.14.33/src/irdma/verbs.h new file mode 100644 index 000000000..79c8fbc36 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/verbs.h @@ -0,0 +1,440 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef IRDMA_VERBS_H +#define IRDMA_VERBS_H + +#define IRDMA_MAX_SAVED_PHY_PGADDR 4 +#define IRDMA_FLUSH_DELAY_MS 20 + +#define IRDMA_PKEY_TBL_SZ 1 +#define IRDMA_DEFAULT_PKEY 0xFFFF + +#define IRDMA_QPS_PER_PUSH_PAGE 16 +#define IRDMA_PUSH_WIN_SIZE 256 + +#define IRDMA_SHADOW_PGCNT 1 + +#define iwdev_to_idev(iwdev) (&(iwdev)->rf->sc_dev) + +struct irdma_ucontext { + struct ib_ucontext ibucontext; + struct irdma_device *iwdev; +#ifdef RDMA_MMAP_DB_SUPPORT + struct rdma_user_mmap_entry *db_mmap_entry; +#else + struct irdma_user_mmap_entry *db_mmap_entry; + DECLARE_HASHTABLE(mmap_hash_tbl, 6); + spinlock_t mmap_tbl_lock; /* protect mmap hash table entries */ +#endif + struct list_head cq_reg_mem_list; + spinlock_t cq_reg_mem_list_lock; /* protect CQ memory list */ + struct list_head qp_reg_mem_list; + spinlock_t qp_reg_mem_list_lock; /* protect QP memory list */ + struct list_head srq_reg_mem_list; + spinlock_t srq_reg_mem_list_lock; /* protect SRQ memory list */ +#ifdef CONFIG_DEBUG_FS + struct list_head uctx_list; +#endif + /* FIXME: Move to kcompat ideally. Used < 4.20.0 for old diassasscoaite flow */ + struct list_head vma_list; + struct mutex vma_list_mutex; /* protect the vma_list */ + int abi_ver; + bool legacy_mode:1; + bool use_raw_attrs:1; +}; + +struct irdma_pd { + struct ib_pd ibpd; + struct irdma_sc_pd sc_pd; + struct mutex push_alloc_mutex; /* protect push page alloc within a PD*/ + DECLARE_BITMAP(push_offset_bmap, IRDMA_QPS_PER_PUSH_PAGE); + u32 push_idx; + u16 qs_handle; +}; + +union irdma_sockaddr { + struct sockaddr_in saddr_in; + struct sockaddr_in6 saddr_in6; +}; + +struct irdma_av { + u8 macaddr[16]; + struct rdma_ah_attr attrs; + union irdma_sockaddr sgid_addr; + union irdma_sockaddr dgid_addr; + u8 net_type; +}; + +struct irdma_ah { + struct ib_ah ibah; + struct irdma_sc_ah sc_ah; + struct irdma_pd *pd; + struct irdma_av av; + u8 sgid_index; + union ib_gid dgid; + struct hlist_node list; + refcount_t refcnt; + struct irdma_ah *parent_ah; /* AH from cached list */ +}; + +struct irdma_hmc_pble { + union { + u32 idx; + dma_addr_t addr; + }; +}; + +struct irdma_cq_mr { + struct irdma_hmc_pble cq_pbl; + dma_addr_t shadow; + bool split; +}; + +struct irdma_srq_mr { + struct irdma_hmc_pble srq_pbl; + dma_addr_t shadow; +}; + +struct irdma_qp_mr { + struct irdma_hmc_pble sq_pbl; + struct irdma_hmc_pble rq_pbl; + dma_addr_t shadow; + dma_addr_t rq_pa; + struct page *sq_page; +}; + +struct irdma_cq_buf { + struct irdma_dma_mem kmem_buf; + struct irdma_cq_uk cq_uk; + struct irdma_hw *hw; + struct list_head list; + struct work_struct work; +}; + +struct irdma_pbl { + struct list_head list; + union { + struct irdma_qp_mr qp_mr; + struct irdma_cq_mr cq_mr; + struct irdma_srq_mr srq_mr; + }; + + bool pbl_allocated:1; + bool on_list:1; + u64 user_base; + struct irdma_pble_alloc pble_alloc; + struct irdma_mr *iwmr; +}; + +struct irdma_mr { + union { + struct ib_mr ibmr; + struct ib_mw ibmw; + }; + struct ib_umem *region; + int access; + u8 is_hwreg; + u16 type; + u32 page_cnt; + u64 page_size; + u64 page_msk; + u32 npages; + u32 stag; + u64 len; + u64 pgaddrmem[IRDMA_MAX_SAVED_PHY_PGADDR]; +#ifdef CONFIG_DEBUG_FS + u64 level0_pa; +#endif + struct irdma_pbl iwpbl; +}; + +struct irdma_srq { + struct ib_srq ibsrq; + struct irdma_sc_srq sc_srq; + struct irdma_dma_mem kmem; + struct completion free_srq; + u64 *srq_wrid_mem; + refcount_t refcnt; + spinlock_t lock; /* for poll srq */ + struct irdma_pbl *iwpbl; + struct ib_sge *sg_list; + u16 srq_head; + u32 srq_num; + u32 max_wr; + bool user_mode:1; +}; + +struct irdma_cq { + struct ib_cq ibcq; + struct irdma_sc_cq sc_cq; + u16 cq_head; + u16 cq_size; + u16 cq_num; + bool user_mode; + atomic_t armed; + enum irdma_cmpl_notify last_notify; + u32 polled_cmpls; + u32 cq_mem_size; + struct irdma_dma_mem kmem; + struct irdma_dma_mem kmem_shadow; + struct completion free_cq; + refcount_t refcnt; + spinlock_t lock; /* for poll cq */ + struct irdma_pbl *iwpbl; + struct irdma_pbl *iwpbl_shadow; + struct list_head resize_list; + struct irdma_cq_poll_info cur_cqe; + struct list_head cmpl_generated; +}; + +struct irdma_cmpl_gen { + struct list_head list; + struct irdma_cq_poll_info cpi; +}; + +struct disconn_work { + struct work_struct work; + struct irdma_qp *iwqp; +}; + +struct if_notify_work { + struct work_struct work; + struct irdma_device *iwdev; + u32 ipaddr[4]; + u16 vlan_id; + bool ipv4:1; + bool ifup:1; +}; + +struct iw_cm_id; + +struct irdma_qp_kmode { + struct irdma_dma_mem dma_mem; + struct irdma_sq_uk_wr_trk_info *sq_wrid_mem; + u64 *rq_wrid_mem; +}; + +struct irdma_qp { + struct ib_qp ibqp; + struct irdma_sc_qp sc_qp; + struct irdma_device *iwdev; + struct irdma_cq *iwscq; + struct irdma_cq *iwrcq; + struct irdma_pd *iwpd; +#ifdef RDMA_MMAP_DB_SUPPORT + struct rdma_user_mmap_entry *push_wqe_mmap_entry; + struct rdma_user_mmap_entry *push_db_mmap_entry; +#else + struct irdma_user_mmap_entry *push_wqe_mmap_entry; + struct irdma_user_mmap_entry *push_db_mmap_entry; +#endif + struct irdma_qp_host_ctx_info ctx_info; + union { + struct irdma_iwarp_offload_info iwarp_info; + struct irdma_roce_offload_info roce_info; + }; + + union { + struct irdma_tcp_offload_info tcp_info; + struct irdma_udp_offload_info udp_info; + }; + + struct irdma_ah roce_ah; + struct list_head teardown_entry; + refcount_t refcnt; + struct iw_cm_id *cm_id; + struct irdma_cm_node *cm_node; + struct delayed_work dwork_flush; + struct ib_mr *lsmm_mr; + atomic_t hw_mod_qp_pend; + enum ib_qp_state ibqp_state; + u32 qp_mem_size; + u32 last_aeq; + int max_send_wr; + int max_recv_wr; + atomic_t close_timer_started; + spinlock_t lock; /* serialize posting WRs to SQ/RQ */ + struct irdma_qp_context *iwqp_context; + void *pbl_vbase; + dma_addr_t pbl_pbase; + struct page *page; + u8 iwarp_state; + u16 term_sq_flush_code; + u16 term_rq_flush_code; + u8 hw_iwarp_state; + u8 hw_tcp_state; + struct irdma_qp_kmode kqp; + struct irdma_dma_mem host_ctx; + struct timer_list terminate_timer; + struct irdma_pbl *iwpbl; + struct ib_sge *sg_list; + struct irdma_dma_mem q2_ctx_mem; + struct irdma_dma_mem ietf_mem; + struct completion free_qp; + wait_queue_head_t waitq; + wait_queue_head_t mod_qp_waitq; + u8 rts_ae_rcvd; + bool active_conn:1; + bool user_mode:1; + bool hte_added:1; + bool flush_issued:1; + bool sig_all:1; + bool pau_mode:1; + bool suspend_pending:1; +}; + +enum irdma_mmap_flag { + IRDMA_MMAP_IO_NC, + IRDMA_MMAP_IO_WC, +}; + +struct irdma_user_mmap_entry { +#ifdef RDMA_MMAP_DB_SUPPORT + struct rdma_user_mmap_entry rdma_entry; +#else + struct irdma_ucontext *ucontext; + struct hlist_node hlist; + u64 pgoff_key; /* Used to compute offset (in bytes) returned to user libc's mmap */ +#endif + u64 bar_offset; + u8 mmap_flag; +}; + +static inline u16 irdma_fw_major_ver(struct irdma_sc_dev *dev) +{ + return (u16)FIELD_GET(IRDMA_FW_VER_MAJOR, dev->feature_info[IRDMA_FEATURE_FW_INFO]); +} + +static inline u16 irdma_fw_minor_ver(struct irdma_sc_dev *dev) +{ + return (u16)FIELD_GET(IRDMA_FW_VER_MINOR, dev->feature_info[IRDMA_FEATURE_FW_INFO]); +} + +static inline void set_ib_wc_op_sq(struct irdma_cq_poll_info *cq_poll_info, + struct ib_wc *entry) +{ + struct irdma_sc_qp *qp; + + switch (cq_poll_info->op_type) { + case IRDMA_OP_TYPE_RDMA_WRITE: + case IRDMA_OP_TYPE_RDMA_WRITE_SOL: + entry->opcode = IB_WC_RDMA_WRITE; + break; + case IRDMA_OP_TYPE_RDMA_READ_INV_STAG: + case IRDMA_OP_TYPE_RDMA_READ: + entry->opcode = IB_WC_RDMA_READ; + break; + case IRDMA_OP_TYPE_SEND_SOL: + case IRDMA_OP_TYPE_SEND_SOL_INV: + case IRDMA_OP_TYPE_SEND_INV: + case IRDMA_OP_TYPE_SEND: + entry->opcode = IB_WC_SEND; + break; + case IRDMA_OP_TYPE_FAST_REG_NSMR: + entry->opcode = IB_WC_REG_MR; + break; + case IRDMA_OP_TYPE_ATOMIC_COMPARE_AND_SWAP: + entry->opcode = IB_WC_COMP_SWAP; + break; + case IRDMA_OP_TYPE_ATOMIC_FETCH_AND_ADD: + entry->opcode = IB_WC_FETCH_ADD; + break; + case IRDMA_OP_TYPE_INV_STAG: + entry->opcode = IB_WC_LOCAL_INV; + break; + default: + qp = cq_poll_info->qp_handle; + ibdev_err(to_ibdev(qp->dev), "Invalid opcode = %d in CQE\n", + cq_poll_info->op_type); + entry->status = IB_WC_GENERAL_ERR; + } +} + +static inline void set_ib_wc_op_rq_gen_3(struct irdma_cq_poll_info *cq_poll_info, + struct ib_wc *entry) +{ + switch (cq_poll_info->op_type) { + case IRDMA_OP_TYPE_RDMA_WRITE: + case IRDMA_OP_TYPE_RDMA_WRITE_SOL: + entry->opcode = IB_WC_RECV_RDMA_WITH_IMM; + break; + default: + entry->opcode = IB_WC_RECV; + } +} + +static inline void set_ib_wc_op_rq(struct irdma_cq_poll_info *cq_poll_info, + struct ib_wc *entry, bool send_imm_support) +{ + /** + * iWARP does not support sendImm, so the presence of Imm data + * must be WriteImm. + */ + if (!send_imm_support) { + entry->opcode = cq_poll_info->imm_valid ? + IB_WC_RECV_RDMA_WITH_IMM : + IB_WC_RECV; + return; + } + switch (cq_poll_info->op_type) { + case IB_OPCODE_RDMA_WRITE_ONLY_WITH_IMMEDIATE: + case IB_OPCODE_RDMA_WRITE_LAST_WITH_IMMEDIATE: + entry->opcode = IB_WC_RECV_RDMA_WITH_IMM; + break; + default: + entry->opcode = IB_WC_RECV; + } +} + +/** + * irdma_mcast_mac_v4 - Get the multicast MAC for an IP address + * @ip_addr: IPv4 address + * @mac: pointer to result MAC address + * + */ +static inline void irdma_mcast_mac_v4(u32 *ip_addr, u8 *mac) +{ + u8 *ip = (u8 *)ip_addr; + unsigned char mac4[ETH_ALEN] = {0x01, 0x00, 0x5E, ip[2] & 0x7F, ip[1], + ip[0]}; + + ether_addr_copy(mac, mac4); +} + +/** + * irdma_mcast_mac_v6 - Get the multicast MAC for an IP address + * @ip_addr: IPv6 address + * @mac: pointer to result MAC address + * + */ +static inline void irdma_mcast_mac_v6(u32 *ip_addr, u8 *mac) +{ + u8 *ip = (u8 *)ip_addr; + unsigned char mac6[ETH_ALEN] = {0x33, 0x33, ip[3], ip[2], ip[1], ip[0]}; + + ether_addr_copy(mac, mac6); +} + +#ifdef ALLOC_HW_STATS_STRUCT_V2 +extern const struct rdma_stat_desc irdma_hw_stat_descs[]; + +#endif /* ALLOC_HW_STATS_STRUCT_V2 */ +#ifdef RDMA_MMAP_DB_SUPPORT +struct rdma_user_mmap_entry* +irdma_user_mmap_entry_insert(struct irdma_ucontext *ucontext, u64 bar_offset, + enum irdma_mmap_flag mmap_flag, u64 *mmap_offset); +#else +struct irdma_user_mmap_entry * +irdma_user_mmap_entry_add_hash(struct irdma_ucontext *ucontext, u64 bar_offset, + enum irdma_mmap_flag mmap_flag, u64 *mmap_offset); +void irdma_user_mmap_entry_del_hash(struct irdma_user_mmap_entry *entry); +#endif /* RDMA_MMAP_DB_SUPPORT */ +int irdma_ib_register_device(struct irdma_device *iwdev); +void irdma_ib_unregister_device(struct irdma_device *iwdev); +void irdma_ib_qp_event(struct irdma_qp *iwqp, enum irdma_qp_event_type event); +void irdma_generate_flush_completions(struct irdma_qp *iwqp); +void irdma_remove_cmpls_list(struct irdma_cq *iwcq); +int irdma_generated_cmpls(struct irdma_cq *iwcq, struct irdma_cq_poll_info *cq_poll_info); +void irdma_sched_qp_flush_work(struct irdma_qp *iwqp); +void irdma_flush_worker(struct work_struct *work); +#endif /* IRDMA_VERBS_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/virtchnl.c b/drivers/intel/irdma-1.14.33/src/irdma/virtchnl.c new file mode 100644 index 000000000..a20466748 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/virtchnl.c @@ -0,0 +1,1479 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#include "osdep.h" +#include "hmc.h" +#include "defs.h" +#include "type.h" +#include "protos.h" +#include "virtchnl.h" +#include "ws.h" +#include "i40iw_hw.h" + +struct vchnl_reg_map_elem { + u16 reg_id; + u16 reg_idx; + bool pg_rel; +}; + +struct vchnl_regfld_map_elem { + u16 regfld_id; + u16 regfld_idx; +}; + +static struct vchnl_reg_map_elem vchnl_reg_map[] = { + {IRDMA_VCHNL_REG_ID_CQPTAIL, IRDMA_CQPTAIL, false}, + {IRDMA_VCHNL_REG_ID_CQPDB, IRDMA_CQPDB, false}, + {IRDMA_VCHNL_REG_ID_CCQPSTATUS, IRDMA_CCQPSTATUS, false}, + {IRDMA_VCHNL_REG_ID_CCQPHIGH, IRDMA_CCQPHIGH, false}, + {IRDMA_VCHNL_REG_ID_CCQPLOW, IRDMA_CCQPLOW, false}, + {IRDMA_VCHNL_REG_ID_CQARM, IRDMA_CQARM, false}, + {IRDMA_VCHNL_REG_ID_CQACK, IRDMA_CQACK, false}, + {IRDMA_VCHNL_REG_ID_AEQALLOC, IRDMA_AEQALLOC, false}, + {IRDMA_VCHNL_REG_ID_CQPERRCODES, IRDMA_CQPERRCODES, false}, + {IRDMA_VCHNL_REG_ID_WQEALLOC, IRDMA_WQEALLOC, false}, + {IRDMA_VCHNL_REG_ID_DB_ADDR_OFFSET, IRDMA_DB_ADDR_OFFSET, false }, + {IRDMA_VCHNL_REG_ID_DYN_CTL, IRDMA_GLINT_DYN_CTL, false }, + {IRDMA_VCHNL_REG_INV_ID, IRDMA_VCHNL_REG_INV_ID, false } +}; + +static struct vchnl_regfld_map_elem vchnl_regfld_map[] = { + {IRDMA_VCHNL_REGFLD_ID_CCQPSTATUS_CQP_OP_ERR, IRDMA_CCQPSTATUS_CCQP_ERR_M}, + {IRDMA_VCHNL_REGFLD_ID_CCQPSTATUS_CCQP_DONE, IRDMA_CCQPSTATUS_CCQP_DONE_M}, + {IRDMA_VCHNL_REGFLD_ID_CQPSQ_STAG_PDID, IRDMA_CQPSQ_STAG_PDID_M}, + {IRDMA_VCHNL_REGFLD_ID_CQPSQ_CQ_CEQID, IRDMA_CQPSQ_CQ_CEQID_M}, + {IRDMA_VCHNL_REGFLD_ID_CQPSQ_CQ_CQID, IRDMA_CQPSQ_CQ_CQID_M}, + {IRDMA_VCHNL_REGFLD_ID_COMMIT_FPM_CQCNT, IRDMA_COMMIT_FPM_CQCNT_M}, + {IRDMA_VCHNL_REGFLD_ID_UPESD_HMCN_ID, IRDMA_CQPSQ_UPESD_HMCFNID_M}, + {IRDMA_VCHNL_REGFLD_INV_ID, IRDMA_VCHNL_REGFLD_INV_ID} +}; + +#define IRDMA_VCHNL_REG_COUNT ARRAY_SIZE(vchnl_reg_map) +#define IRDMA_VCHNL_REGFLD_COUNT ARRAY_SIZE(vchnl_regfld_map) +#define IRDMA_VCHNL_REGFLD_BUF_SIZE \ + (IRDMA_VCHNL_REG_COUNT * sizeof(struct irdma_vchnl_reg_info) + \ + IRDMA_VCHNL_REGFLD_COUNT * sizeof(struct irdma_vchnl_reg_field_info)) +#define IRDMA_REGMAP_RESP_BUF_SIZE (IRDMA_VCHNL_RESP_MIN_SIZE + IRDMA_VCHNL_REGFLD_BUF_SIZE) + +static enum irdma_hmc_rsrc_type hmc_rsrc_types_gen2[] = { + IRDMA_HMC_IW_QP, + IRDMA_HMC_IW_CQ, + IRDMA_HMC_IW_HTE, + IRDMA_HMC_IW_ARP, + IRDMA_HMC_IW_APBVT_ENTRY, + IRDMA_HMC_IW_MR, + IRDMA_HMC_IW_XF, + IRDMA_HMC_IW_XFFL, + IRDMA_HMC_IW_Q1, + IRDMA_HMC_IW_Q1FL, + IRDMA_HMC_IW_TIMER, + IRDMA_HMC_IW_FSIMC, + IRDMA_HMC_IW_FSIAV, + IRDMA_HMC_IW_PBLE, + IRDMA_HMC_IW_RRF, + IRDMA_HMC_IW_RRFFL, + IRDMA_HMC_IW_HDR, + IRDMA_HMC_IW_MD, + IRDMA_HMC_IW_OOISC, + IRDMA_HMC_IW_OOISCFFL, +}; + +static enum irdma_hmc_rsrc_type hmc_rsrc_types_gen3[] = { + IRDMA_HMC_IW_QP, + IRDMA_HMC_IW_CQ, + IRDMA_HMC_IW_SRQ, + IRDMA_HMC_IW_HTE, + IRDMA_HMC_IW_ARP, + IRDMA_HMC_IW_APBVT_ENTRY, + IRDMA_HMC_IW_MR, + IRDMA_HMC_IW_XF, + IRDMA_HMC_IW_XFFL, + IRDMA_HMC_IW_Q1, + IRDMA_HMC_IW_Q1FL, + IRDMA_HMC_IW_TIMER, + IRDMA_HMC_IW_FSIMC, + IRDMA_HMC_IW_FSIAV, + IRDMA_HMC_IW_PBLE, + IRDMA_HMC_IW_RRF, + IRDMA_HMC_IW_RRFFL, + IRDMA_HMC_IW_HDR, + IRDMA_HMC_IW_MD, + IRDMA_HMC_IW_OOISC, + IRDMA_HMC_IW_OOISCFFL, +}; + +/** + * irdma_sc_vchnl_init - Initialize dev virtchannel and get hw_rev + * @dev: dev structure to update + * @info: virtchannel info parameters to fill into the dev structure + */ +int irdma_sc_vchnl_init(struct irdma_sc_dev *dev, + struct irdma_vchnl_init_info *info) +{ + dev->vchnl_if = info->vchnl_if; + dev->vchnl_up = dev->vchnl_if ? true : false; + dev->privileged = info->privileged; + dev->is_pf = info->is_pf; + dev->vchnl_wq = info->vchnl_wq; + dev->hw_attrs.uk_attrs.hw_rev = info->hw_rev; + dev->hw_attrs.uk_attrs.max_hw_push_len = IRDMA_DEFAULT_MAX_PUSH_LEN; + + if (!dev->privileged) { + int ret = irdma_vchnl_req_get_ver(dev, IRDMA_VCHNL_CHNL_VER_MAX, + &dev->vchnl_ver); + /* Attempt to negotiate down to V1 as it does not negotaite. */ + if (ret) { + ret = irdma_vchnl_req_get_ver(dev, IRDMA_VCHNL_CHNL_VER_V1, + &dev->vchnl_ver); + } + + ibdev_dbg(to_ibdev(dev), + "DEV: Get Channel version ret = %d, version is %u\n", + ret, dev->vchnl_ver); + + if (ret) + return ret; + + /* IRDMA_VCHNL_OP_GET_RDMA_CAPS not supported in V1. */ + if (dev->vchnl_ver == IRDMA_VCHNL_OP_GET_VER_V1) { + dev->hw_attrs.uk_attrs.hw_rev = IRDMA_GEN_2; + return 0; + } + ret = irdma_vchnl_req_get_caps(dev); + if (ret) + return ret; + + dev->hw_attrs.uk_attrs.hw_rev = dev->vc_caps.hw_rev; + dev->hw_attrs.uk_attrs.max_hw_push_len = dev->vc_caps.max_hw_push_len; + } + + return 0; +} + +/** + * irdma_find_vc_dev - get vchnl dev pointer + * @dev: shared device pointer + * @vf_id: virtual function id + */ +struct irdma_vchnl_dev *irdma_find_vc_dev(struct irdma_sc_dev *dev, u16 vf_id) +{ + struct irdma_vchnl_dev *vc_dev = NULL; + unsigned long flags; + u16 iw_vf_idx; + + spin_lock_irqsave(&dev->vc_dev_lock, flags); + for (iw_vf_idx = 0; iw_vf_idx < dev->num_vfs; iw_vf_idx++) { + if (dev->vc_dev[iw_vf_idx] && + dev->vc_dev[iw_vf_idx]->vf_id == vf_id) { + vc_dev = dev->vc_dev[iw_vf_idx]; + refcount_inc(&vc_dev->refcnt); + break; + } + } + spin_unlock_irqrestore(&dev->vc_dev_lock, flags); + + return vc_dev; +} + +/** + * irdma_remove_vc_dev - remove vc_dev + * @dev: shared device pointer + * @vc_dev: vf dev to be removed + */ +void irdma_remove_vc_dev(struct irdma_sc_dev *dev, struct irdma_vchnl_dev *vc_dev) +{ + unsigned long flags; + + spin_lock_irqsave(&dev->vc_dev_lock, flags); + dev->vc_dev[vc_dev->iw_vf_idx] = NULL; + spin_unlock_irqrestore(&dev->vc_dev_lock, flags); +} + +/** + * irdma_vchnl_pf_send_resp - Send channel version to VF + * @dev: irdma_vchnl_pf_send_resp device pointer + * @vf_id: Virtual function ID associated with the message + * @vchnl_msg: Virtual channel message buffer pointer + * @param: parameter that is passed back to the VF + * @param_len: length of parameter that's being passed in + * @resp_code: response code sent back to VF + */ +static void irdma_vchnl_pf_send_resp(struct irdma_sc_dev *dev, u16 vf_id, + struct irdma_vchnl_op_buf *vchnl_msg, + void *param, u16 param_len, int resp_code) +{ + u8 resp_buf[IRDMA_VCHNL_MAX_MSG_SIZE] = {}; + struct irdma_vchnl_resp_buf *vchnl_msg_resp; + int ret; + + vchnl_msg_resp = (struct irdma_vchnl_resp_buf *)resp_buf; + vchnl_msg_resp->op_ctx = vchnl_msg->op_ctx; + vchnl_msg_resp->buf_len = IRDMA_VCHNL_RESP_MIN_SIZE + param_len; + vchnl_msg_resp->op_ret = (s16)resp_code; + if (param_len) + memcpy(vchnl_msg_resp->buf, param, param_len); + + ret = irdma_vchnl_send_pf(dev, vf_id, resp_buf, + vchnl_msg_resp->buf_len); + if (ret) + ibdev_dbg(to_ibdev(dev), + "VIRT: virt channel send failed ret = %d\n", ret); +} + +/** + * pf_valid_hmc_rsrc_type - Check obj_type input validation + * @hw_rev: hw version + * @obj_type: type of hmc resource + */ +static bool pf_valid_hmc_rsrc_type(u8 hw_rev, u16 obj_type) +{ + enum irdma_hmc_rsrc_type *valid_rsrcs; + u8 num_rsrcs, i; + + switch (hw_rev) { + case IRDMA_GEN_2: + valid_rsrcs = hmc_rsrc_types_gen2; + num_rsrcs = ARRAY_SIZE(hmc_rsrc_types_gen2); + break; + case IRDMA_GEN_3: + valid_rsrcs = hmc_rsrc_types_gen3; + num_rsrcs = ARRAY_SIZE(hmc_rsrc_types_gen3); + break; + default: + return false; + } + + for (i = 0; i < num_rsrcs; i++) { + if (obj_type == valid_rsrcs[i]) + return true; + } + + return false; +} + +/** + * irdma_pf_add_hmc_obj - Add HMC Object for VF + * @vc_dev: pointer to the vc_dev + * @hmc_obj: hmc_obj to be added + */ +static int irdma_pf_add_hmc_obj(struct irdma_vchnl_dev *vc_dev, + struct irdma_vchnl_hmc_obj_range *hmc_obj) +{ + struct irdma_sc_dev *dev = vc_dev->pf_dev; + struct irdma_hmc_info *hmc_info = &vc_dev->hmc_info; + struct irdma_hmc_create_obj_info info = {}; + int ret; + + if (!vc_dev->pf_hmc_initialized) { + ret = irdma_pf_init_vfhmc(vc_dev->pf_dev, + (u8)vc_dev->pmf_index); + if (ret) + return ret; + vc_dev->pf_hmc_initialized = true; + } + + if (!pf_valid_hmc_rsrc_type(dev->hw_attrs.uk_attrs.hw_rev, + hmc_obj->obj_type)) { + ibdev_dbg(to_ibdev(dev), + "VIRT: invalid hmc_rsrc type detected. vf_id %d obj_type 0x%x\n", + vc_dev->vf_id, hmc_obj->obj_type); + return -EINVAL; + } + + info.hmc_info = hmc_info; + info.privileged = false; + info.rsrc_type = (u32)hmc_obj->obj_type; + info.entry_type = (info.rsrc_type == IRDMA_HMC_IW_PBLE) ? + IRDMA_SD_TYPE_PAGED : + IRDMA_SD_TYPE_DIRECT; + info.start_idx = hmc_obj->start_index; + info.count = hmc_obj->obj_count; + ibdev_dbg(to_ibdev(vc_dev->pf_dev), + "VIRT: IRDMA_VCHNL_OP_ADD_HMC_OBJ_RANGE. Add %u type %u objects\n", + info.count, info.rsrc_type); + + return irdma_sc_create_hmc_obj(vc_dev->pf_dev, &info); +} + +/** + * irdma_pf_del_hmc_obj - Delete HMC Object for VF + * @vc_dev: pointer to the vc_dev + * @hmc_obj: hmc_obj to be deleted + */ +static int irdma_pf_del_hmc_obj(struct irdma_vchnl_dev *vc_dev, + struct irdma_vchnl_hmc_obj_range *hmc_obj) +{ + struct irdma_sc_dev *dev = vc_dev->pf_dev; + struct irdma_hmc_info *hmc_info = &vc_dev->hmc_info; + struct irdma_hmc_del_obj_info info = {}; + + if (!vc_dev->pf_hmc_initialized) + return -EINVAL; + + if (!pf_valid_hmc_rsrc_type(dev->hw_attrs.uk_attrs.hw_rev, + hmc_obj->obj_type)) { + ibdev_dbg(to_ibdev(dev), + "VIRT: invalid hmc_rsrc type detected. vf_id %d obj_type 0x%x\n", + vc_dev->vf_id, hmc_obj->obj_type); + return -EINVAL; + } + + info.hmc_info = hmc_info; + info.privileged = false; + info.rsrc_type = (u32)hmc_obj->obj_type; + info.start_idx = hmc_obj->start_index; + info.count = hmc_obj->obj_count; + ibdev_dbg(to_ibdev(vc_dev->pf_dev), + "VIRT: IRDMA_VCHNL_OP_DEL_HMC_OBJ_RANGE. Delete %u type %u objects\n", + info.count, info.rsrc_type); + + return irdma_sc_del_hmc_obj(vc_dev->pf_dev, &info, false); +} + +/** + * irdma_pf_manage_ws_node - managing ws node for VF + * @vc_dev: pointer to the VF Device + * @ws_node: work scheduler node to be modified + * @qs_handle: returned qs_handle provided by cqp + */ +static int +irdma_pf_manage_ws_node(struct irdma_vchnl_dev *vc_dev, + struct irdma_vchnl_manage_ws_node *ws_node, + u16 *qs_handle) +{ + struct irdma_sc_vsi *vsi = vc_dev->vf_vsi; + int ret = 0; + + if (ws_node->user_pri >= IRDMA_MAX_USER_PRIORITY) + return -EINVAL; + + ibdev_dbg(to_ibdev(vc_dev->pf_dev), + "VIRT: IRDMA_VCHNL_OP_MANAGE_WS_NODE. Add %d vf_id %d\n", + ws_node->add, vc_dev->vf_id); + + if (ws_node->add) { + ret = vsi->dev->ws_add(vsi, ws_node->user_pri); + if (ret) + ibdev_dbg(to_ibdev(vc_dev->pf_dev), + "VIRT: irdma_ws_add failed ret = %d\n", ret); + else + *qs_handle = vsi->qos[ws_node->user_pri].qs_handle[0]; + } else { + vsi->dev->ws_remove(vsi, ws_node->user_pri); + } + + return ret; +} + +/** + * irdma_pf_get_reg_layout - Format reg layout for AxF + * @vc_dev: Virtual function device associated with the message + * @reg_array: register layout array passed back to the AxF + */ +static void irdma_pf_get_reg_layout(struct irdma_vchnl_dev *vc_dev, + struct irdma_vchnl_reg_info *reg_array) +{ + struct irdma_vchnl_reg_field_info *regfld_array; + struct irdma_sc_dev *dev = vc_dev->pf_dev; + uintptr_t reg_addr, base_addr; + u16 regfld_idx, reg_idx; + u64 bitmask; + u32 idx; + + base_addr = (uintptr_t)dev->hw->hw_addr; + + for (idx = 0; idx < IRDMA_VCHNL_REG_COUNT; idx++) { + reg_idx = vchnl_reg_map[idx].reg_idx; + reg_array[idx].reg_id = vchnl_reg_map[idx].reg_id; + if (reg_array[idx].reg_id == IRDMA_VCHNL_REG_INV_ID) + break; + + reg_addr = (uintptr_t)dev->hw_regs[reg_idx]; + if (reg_idx != IRDMA_DB_ADDR_OFFSET) + reg_array[idx].reg_offset = (u32)(reg_addr - base_addr); + else + reg_array[idx].reg_offset = (u32)reg_addr; + if (vchnl_reg_map[idx].pg_rel) + reg_array[idx].reg_id |= IRDMA_VCHNL_REG_PAGE_REL; + } + + regfld_array = + (struct irdma_vchnl_reg_field_info *)®_array[idx + 1]; + for (idx = 0; idx < IRDMA_VCHNL_REGFLD_COUNT; idx++) { + regfld_idx = vchnl_regfld_map[idx].regfld_idx; + regfld_array[idx].fld_id = vchnl_regfld_map[idx].regfld_id; + if (regfld_array[idx].fld_id == IRDMA_VCHNL_REGFLD_INV_ID) + break; + + bitmask = dev->hw_masks[regfld_idx] >> + dev->hw_shifts[regfld_idx]; + while (bitmask != 0) { + regfld_array[idx].fld_bits++; + bitmask >>= 1; + } + regfld_array[idx].fld_shift = dev->hw_shifts[regfld_idx]; + } +} + +/** + * irdma_set_hmc_fcn_info - Populate hmc_fcn_info struct + * @vc_dev: pointer to VF dev structure + * @hmc_fcn_info: pointer to HMC fcn info to be filled up + */ +static +void irdma_set_hmc_fcn_info(struct irdma_vchnl_dev *vc_dev, + struct irdma_hmc_fcn_info *hmc_fcn_info) +{ + memset(hmc_fcn_info, 0, sizeof(*hmc_fcn_info)); + + /* For new HW model vf_id is PCI function */ + hmc_fcn_info->vf_id = vc_dev->vf_id; + hmc_fcn_info->protocol_used = vc_dev->protocol_used; + if (vc_dev->pf_dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + hmc_fcn_info->is_pf = 0; + } +} + +/** + * irdma_get_protocol_used - returns protocol family to use for HMC FCN + * @vchnl_msg: inbound vf vchannel message + * + * Return: protool family to use in get hmc function cqp operation. + */ +static enum irdma_protocol_used irdma_get_protocol_used(struct irdma_vchnl_op_buf *vchnl_msg) +{ + struct irdma_vchnl_req_hmc_info *req_hmc; + + if (vchnl_msg->op_ver >= IRDMA_VCHNL_OP_GET_HMC_FCN_V1) { + req_hmc = (struct irdma_vchnl_req_hmc_info *)vchnl_msg->buf; + return req_hmc->protocol_used; + } + return IRDMA_ROCE_PROTOCOL_ONLY; +} + +/** + * irdma_get_next_vf_idx - return the next vf_idx available + * @dev: pointer to RDMA dev structure + */ +static u16 irdma_get_next_vf_idx(struct irdma_sc_dev *dev) +{ + u16 vf_idx; + + for (vf_idx = 0; vf_idx < dev->num_vfs; vf_idx++) { + if (!dev->vc_dev[vf_idx]) + break; + } + + return vf_idx < dev->num_vfs ? vf_idx : IRDMA_VCHNL_INVALID_VF_IDX; +} + +/** + * irdma_put_vfdev - put vfdev and free memory + * @dev: pointer to RDMA dev structure + * @vc_dev: pointer to RDMA vf dev structure + */ +void irdma_put_vfdev(struct irdma_sc_dev *dev, struct irdma_vchnl_dev *vc_dev) +{ + if (refcount_dec_and_test(&vc_dev->refcnt)) { + struct irdma_virt_mem virt_mem; + + if (vc_dev->hmc_info.sd_table.sd_entry) { + virt_mem.va = vc_dev->hmc_info.sd_table.sd_entry; + virt_mem.size = sizeof(struct irdma_hmc_sd_entry) * + (vc_dev->hmc_info.sd_table.sd_cnt + + vc_dev->hmc_info.first_sd_index); + kfree(virt_mem.va); + } + + virt_mem.va = vc_dev; + virt_mem.size = sizeof(*vc_dev); + kfree(virt_mem.va); + } +} + +static int irdma_negotiate_vchnl_rev(u8 hw_rev, u16 op_ver, u32 *vchnl_ver) +{ + if (op_ver < IRDMA_VCHNL_CHNL_VER_MIN) + return -EOPNOTSUPP; + + switch (hw_rev) { + case IRDMA_GEN_3: + default: + if (op_ver < IRDMA_VCHNL_OP_GET_VER_V2) + return -EOPNOTSUPP; + + fallthrough; + case IRDMA_GEN_2: + *vchnl_ver = min((u16)IRDMA_VCHNL_CHNL_VER_MAX, op_ver); + break; + case IRDMA_GEN_1: + /* GEN_1 does not have VF support */ + return -EOPNOTSUPP; + } + + return 0; +} + +/** + * irdma_pf_get_vf_hmc_fcn - Get hmc fcn from CQP for VF + * @dev: pointer to RDMA dev structure + * @vf_id: vf id of the hmc fcn requester + * @protocol_used: protocol family supported for the VF + */ +static struct irdma_vchnl_dev *irdma_pf_get_vf_hmc_fcn(struct irdma_sc_dev *dev, + u16 vf_id, + enum irdma_protocol_used protocol_used) +{ + struct irdma_hmc_fcn_info hmc_fcn_info; + struct irdma_virt_mem virt_mem; + struct irdma_vchnl_dev *vc_dev; + struct irdma_sc_vsi *vsi; + u16 iw_vf_idx = 0; + u32 size; + + iw_vf_idx = irdma_get_next_vf_idx(dev); + if (iw_vf_idx == IRDMA_VCHNL_INVALID_VF_IDX) + return NULL; + + size = sizeof(*vc_dev) + + sizeof(struct irdma_hmc_obj_info) * IRDMA_HMC_IW_MAX; + virt_mem.size = size; + virt_mem.va = kzalloc(virt_mem.size, GFP_KERNEL); + + if (!virt_mem.va) { + ibdev_dbg(to_ibdev(dev), + "VIRT: VF%u Unable to allocate a VF device structure.\n", + vf_id); + return NULL; + } + + vc_dev = virt_mem.va; + vc_dev->pf_dev = dev; + vc_dev->vf_id = vf_id; + vc_dev->iw_vf_idx = iw_vf_idx; + vc_dev->protocol_used = protocol_used; + vc_dev->pf_hmc_initialized = false; + vc_dev->hmc_info.hmc_obj = (struct irdma_hmc_obj_info *)(&vc_dev[1]); + + ibdev_dbg(to_ibdev(dev), "VIRT: vc_dev %p, hmc_info %p, hmc_obj %p\n", + vc_dev, &vc_dev->hmc_info, vc_dev->hmc_info.hmc_obj); + vsi = irdma_update_vsi_ctx(dev, vc_dev, true); + if (!vsi) { + ibdev_dbg(to_ibdev(dev), + "VIRT: VF%u failed updating vsi ctx .\n", vf_id); + dev->vc_dev[vc_dev->iw_vf_idx] = NULL; + kfree(virt_mem.va); + return NULL; + } + + refcount_set(&vc_dev->refcnt, 1); + dev->vc_dev[iw_vf_idx] = vc_dev; + vc_dev->vf_vsi = vsi; + vsi->vf_id = (u16)vc_dev->vf_id; + vsi->vc_dev = vc_dev; + + irdma_set_hmc_fcn_info(vc_dev, &hmc_fcn_info); + if (irdma_cqp_manage_hmc_fcn_cmd(dev, &hmc_fcn_info, + &vc_dev->pmf_index)) { + irdma_update_vsi_ctx(dev, vc_dev, false); + dev->vc_dev[vc_dev->iw_vf_idx] = NULL; + kfree(virt_mem.va); + ibdev_dbg(to_ibdev(dev), + "VIRT: VF%u error CQP Get HMC Function operation.\n", + vf_id); + return NULL; + } + + ibdev_dbg(to_ibdev(dev), "VIRT: HMC Function allocated = 0x%08x\n", + vc_dev->pmf_index); + + /* Caller references vc_dev */ + refcount_inc(&vc_dev->refcnt); + return vc_dev; +} + +/** + * irdma_pf_put_vf_hmc_fcn - Put hmc fcn from CQP for VF + * @dev: pointer to RDMA dev structure + * @vc_dev: vf dev structure + */ +void irdma_pf_put_vf_hmc_fcn(struct irdma_sc_dev *dev, + struct irdma_vchnl_dev *vc_dev) +{ + struct irdma_hmc_fcn_info hmc_fcn_info; + + irdma_set_hmc_fcn_info(vc_dev, &hmc_fcn_info); + hmc_fcn_info.free_fcn = true; + if (irdma_cqp_manage_hmc_fcn_cmd(dev, &hmc_fcn_info, + &vc_dev->pmf_index)) + ibdev_dbg(to_ibdev(dev), + "VIRT: VF%u error CQP Free HMC Function operation.\n", + vc_dev->vf_id); + + irdma_remove_vc_dev(dev, vc_dev); + + irdma_update_vsi_ctx(dev, vc_dev, false); + irdma_put_vfdev(dev, vc_dev); +} + +/** + * irdma_recv_pf_worker - PF receive worker processes inbound vchnl request + * @work: work element for the vchnl request + */ +static void irdma_recv_pf_worker(struct work_struct *work) +{ + struct irdma_vchnl_work *vchnl_work = + container_of(work, struct irdma_vchnl_work, work); + struct irdma_vchnl_op_buf *vchnl_msg = + (struct irdma_vchnl_op_buf *)&vchnl_work->vf_msg_buf; + u16 vf_id = vchnl_work->vf_id, qs_handle = 0, resp_len = 0; + void *param = vchnl_msg->buf, *resp_param = NULL; + int resp_code = 0; + struct irdma_sc_dev *dev = vchnl_work->dev; + struct irdma_vchnl_rdma_caps caps = {}; + struct irdma_vchnl_dev *vc_dev = NULL; + struct irdma_virt_mem virt_mem; + u8 vlan_parse_en; + u32 vchnl_ver; + + ibdev_dbg(to_ibdev(dev), "VIRT: opcode %u", vchnl_msg->op_code); + vc_dev = irdma_find_vc_dev(dev, vf_id); + if (vc_dev && vc_dev->reset_en) + goto free_work; + + switch (vchnl_msg->op_code) { + case IRDMA_VCHNL_OP_GET_VER: + resp_code = irdma_negotiate_vchnl_rev( + dev->hw_attrs.uk_attrs.hw_rev, vchnl_msg->op_ver, + &vchnl_ver); + + resp_param = &vchnl_ver; + resp_len = sizeof(vchnl_ver); + break; + case IRDMA_VCHNL_OP_GET_HMC_FCN: + if (!vc_dev) { + vc_dev = irdma_pf_get_vf_hmc_fcn( + dev, vf_id, irdma_get_protocol_used(vchnl_msg)); + if (!vc_dev) { + resp_code = -ENODEV; + break; + } + } + resp_param = &vc_dev->pmf_index; + resp_len = sizeof(vc_dev->pmf_index); + break; + case IRDMA_VCHNL_OP_PUT_HMC_FCN: + if (!vc_dev) + goto free_work; + + irdma_pf_put_vf_hmc_fcn(dev, vc_dev); + break; + + case IRDMA_VCHNL_OP_ADD_HMC_OBJ_RANGE: + if (!vc_dev) + goto free_work; + + resp_code = irdma_pf_add_hmc_obj(vc_dev, param); + break; + case IRDMA_VCHNL_OP_DEL_HMC_OBJ_RANGE: + if (!vc_dev) + goto free_work; + + resp_code = irdma_pf_del_hmc_obj(vc_dev, param); + break; + case IRDMA_VCHNL_OP_MANAGE_WS_NODE: + if (!vc_dev) + goto free_work; + + resp_code = irdma_pf_manage_ws_node(vc_dev, param, &qs_handle); + resp_param = &qs_handle; + resp_len = sizeof(qs_handle); + break; + case IRDMA_VCHNL_OP_GET_REG_LAYOUT: + if (!vc_dev) + goto free_work; + + irdma_pf_get_reg_layout(vc_dev, param); + resp_param = param; + resp_len = IRDMA_VCHNL_REGFLD_BUF_SIZE; + break; + case IRDMA_VCHNL_OP_VLAN_PARSING: + if (!vc_dev) + goto free_work; + + if (dev->hw_attrs.uk_attrs.hw_rev <= IRDMA_GEN_2) + irdma_update_vf_vlan_cfg(dev, vc_dev); + /* In Linux port_vlan_id != 0 indicates port vlan is enabled. + * Linux is always in double VLAN mode. + */ + vlan_parse_en = !vc_dev->port_vlan_en; + ibdev_dbg(to_ibdev(dev), "VIRT: vlan_parse_en = 0x%x\n", + vlan_parse_en); + + resp_param = &vlan_parse_en; + resp_len = sizeof(vlan_parse_en); + break; + + case IRDMA_VCHNL_OP_GET_RDMA_CAPS: + caps.hw_rev = dev->hw_attrs.uk_attrs.hw_rev; + + resp_len = sizeof(caps); + resp_param = ∩︀ + break; + default: + ibdev_dbg(to_ibdev(dev), "VIRT: Invalid OpCode 0x%x\n", + vchnl_msg->op_code); + resp_code = -EOPNOTSUPP; + } + + irdma_vchnl_pf_send_resp(dev, vf_id, vchnl_msg, resp_param, resp_len, + resp_code); +free_work: + if (vc_dev) + irdma_put_vfdev(dev, vc_dev); + + virt_mem.va = work; + kfree(virt_mem.va); +} + +/** + * irdma_vchnl_pf_verify_msg - validate vf received vchannel message size + * @vchnl_msg: inbound vf vchannel message + * @len: length of the virtual channels message + */ +static bool irdma_vchnl_pf_verify_msg(struct irdma_vchnl_op_buf *vchnl_msg, + u16 len) +{ + u16 op_code = vchnl_msg->op_code; + u16 op_size; + + if (len > IRDMA_VCHNL_MAX_MSG_SIZE) + return false; + + if (len < sizeof(*vchnl_msg)) + return false; + + switch (op_code) { + case IRDMA_VCHNL_OP_ADD_HMC_OBJ_RANGE: + case IRDMA_VCHNL_OP_DEL_HMC_OBJ_RANGE: + op_size = sizeof(struct irdma_vchnl_hmc_obj_range); + if (len < sizeof(*vchnl_msg) + op_size) + return false; + break; + case IRDMA_VCHNL_OP_MANAGE_WS_NODE: + op_size = sizeof(struct irdma_vchnl_manage_ws_node); + if (len < sizeof(*vchnl_msg) + op_size) + return false; + break; + case IRDMA_VCHNL_OP_GET_HMC_FCN: + if (vchnl_msg->op_ver >= IRDMA_VCHNL_OP_GET_HMC_FCN_V1) { + if (len < sizeof(*vchnl_msg) + + sizeof(struct irdma_vchnl_req_hmc_info)) + return false; + } + break; + case IRDMA_VCHNL_OP_GET_VER: + case IRDMA_VCHNL_OP_PUT_HMC_FCN: + case IRDMA_VCHNL_OP_GET_REG_LAYOUT: + case IRDMA_VCHNL_OP_QUEUE_VECTOR_MAP: + case IRDMA_VCHNL_OP_QUEUE_VECTOR_UNMAP: + case IRDMA_VCHNL_OP_VLAN_PARSING: + case IRDMA_VCHNL_OP_GET_RDMA_CAPS: + if (len < sizeof(*vchnl_msg)) + return false; + break; + + default: + return false; + } + + return true; +} +/** + * irdma_vchnl_recv_pf - Receive PF virtual channel messages + * @dev: RDMA device pointer + * @vf_id: Virtual function ID associated with the message + * @msg: Virtual channel message buffer pointer + * @len: Length of the virtual channels message + */ +int irdma_vchnl_recv_pf(struct irdma_sc_dev *dev, u16 vf_id, u8 *msg, u16 len) +{ + struct irdma_vchnl_work *work; + struct irdma_virt_mem workmem; + + ibdev_dbg(to_ibdev(dev), "VIRT: VF%u: msg %p len %u chnl up %u", + vf_id, msg, len, dev->vchnl_up); + + if (!msg || + !irdma_vchnl_pf_verify_msg((struct irdma_vchnl_op_buf *)msg, len)) + return -EINVAL; + + if (!dev->vchnl_up) + return -EBUSY; + + workmem.size = sizeof(*work); + workmem.va = kzalloc(workmem.size, GFP_KERNEL); + if (!workmem.va) + return -ENOMEM; + + work = workmem.va; + memcpy(&work->vf_msg_buf, msg, len); + work->dev = dev; + work->vf_id = vf_id; + work->len = len; + INIT_WORK(&work->work, irdma_recv_pf_worker); + queue_work(dev->vchnl_wq, &work->work); + + return 0; +} + +/** + * irdma_vchnl_req_verify_resp - Verify requested response size + * @vchnl_req: vchnl message requested + * @resp_len: response length sent from vchnl peer + */ +static int irdma_vchnl_req_verify_resp(struct irdma_vchnl_req *vchnl_req, + u16 resp_len) +{ + switch (vchnl_req->vchnl_msg->op_code) { + case IRDMA_VCHNL_OP_GET_VER: + case IRDMA_VCHNL_OP_GET_HMC_FCN: + case IRDMA_VCHNL_OP_PUT_HMC_FCN: + case IRDMA_VCHNL_OP_ADD_HMC_OBJ_RANGE: + case IRDMA_VCHNL_OP_DEL_HMC_OBJ_RANGE: + case IRDMA_VCHNL_OP_MANAGE_WS_NODE: + case IRDMA_VCHNL_OP_VLAN_PARSING: + if (resp_len != vchnl_req->parm_len) + return -EBADMSG; + break; + case IRDMA_VCHNL_OP_GET_RDMA_CAPS: + if (resp_len < IRDMA_VCHNL_OP_GET_RDMA_CAPS_MIN_SIZE) + return -EBADMSG; + break; + case IRDMA_VCHNL_OP_MANAGE_PUSH_PAGE: + case IRDMA_VCHNL_OP_GET_REG_LAYOUT: + case IRDMA_VCHNL_OP_QUEUE_VECTOR_MAP: + case IRDMA_VCHNL_OP_QUEUE_VECTOR_UNMAP: + break; + default: + return -EBADMSG; + } + + return 0; +} + +static void irdma_free_vchnl_req_msg(struct irdma_vchnl_req *vchnl_req) +{ + kfree(vchnl_req->vchnl_msg); +} + +static int irdma_alloc_vchnl_req_msg(struct irdma_vchnl_req *vchnl_req, + struct irdma_vchnl_req_init_info *info) +{ + struct irdma_vchnl_op_buf *vchnl_msg; + + vchnl_msg = kzalloc(IRDMA_VCHNL_MAX_MSG_SIZE, GFP_KERNEL); + + if (!vchnl_msg) + return -ENOMEM; + + vchnl_msg->op_ctx = (uintptr_t)vchnl_req; + vchnl_msg->buf_len = sizeof(*vchnl_msg) + info->req_parm_len; + if (info->req_parm_len) + memcpy(vchnl_msg->buf, info->req_parm, info->req_parm_len); + vchnl_msg->op_code = info->op_code; + vchnl_msg->op_ver = info->op_ver; + + vchnl_req->vchnl_msg = vchnl_msg; + vchnl_req->parm = info->resp_parm; + vchnl_req->parm_len = info->resp_parm_len; + + return 0; +} + +static int irdma_vchnl_req_send_sync(struct irdma_sc_dev *dev, + struct irdma_vchnl_req_init_info *info) +{ + struct irdma_vchnl_req vchnl_req = {}; + u16 resp_len = sizeof(dev->vc_recv_buf); + u16 msg_len; + u8 *msg; + int ret; + + ret = irdma_alloc_vchnl_req_msg(&vchnl_req, info); + if (ret) + return ret; + + msg_len = vchnl_req.vchnl_msg->buf_len; + msg = (u8 *)vchnl_req.vchnl_msg; + + mutex_lock(&dev->vchnl_mutex); + ret = irdma_vchnl_send_sync(dev, msg, msg_len, dev->vc_recv_buf, + &resp_len); + if (ret) + goto exit; + + ret = irdma_vchnl_req_get_resp(dev, &vchnl_req); +exit: + mutex_unlock(&dev->vchnl_mutex); + ibdev_dbg(to_ibdev(dev), + "VIRT: virtual channel send %s caller: %pS ret=%d op=%u op_ver=%u req_len=%u parm_len=%u resp_len=%u\n", + !ret ? "SUCCEEDS" : "FAILS", __builtin_return_address(0), + ret, vchnl_req.vchnl_msg->op_code, + vchnl_req.vchnl_msg->op_ver, vchnl_req.vchnl_msg->buf_len, + vchnl_req.parm_len, vchnl_req.resp_len); + irdma_free_vchnl_req_msg(&vchnl_req); + + return ret; +} + +/** + * irdma_vchnl_req_manage_push_pg - manage push page + * @dev: rdma device pointer + * @add: Add or remove push page + * @qs_handle: qs_handle of push page for add + * @pg_idx: index of push page that is added or removed + */ +int irdma_vchnl_req_manage_push_pg(struct irdma_sc_dev *dev, bool add, + u32 qs_handle, u32 *pg_idx) +{ + struct irdma_vchnl_manage_push_page add_push_pg = {}; + struct irdma_vchnl_req_init_info info = {}; + + if (!dev->vchnl_up) + return -EBUSY; + + add_push_pg.add = add; + add_push_pg.pg_idx = add ? 0 : *pg_idx; + add_push_pg.qs_handle = qs_handle; + + info.op_code = IRDMA_VCHNL_OP_MANAGE_PUSH_PAGE; + info.op_ver = IRDMA_VCHNL_OP_MANAGE_PUSH_PAGE_V0; + info.req_parm = &add_push_pg; + info.req_parm_len = sizeof(add_push_pg); + info.resp_parm = pg_idx; + info.resp_parm_len = sizeof(*pg_idx); + + ibdev_dbg(to_ibdev(dev), + "VIRT: Sending msg: manage_push_pg add = %d, idx %u, qsh %u\n", + add_push_pg.add, add_push_pg.pg_idx, add_push_pg.qs_handle); + + return irdma_vchnl_req_send_sync(dev, &info); +} + +/** + * irdma_vchnl_req_get_reg_layout - Get Register Layout + * @dev: RDMA device pointer + */ +int irdma_vchnl_req_get_reg_layout(struct irdma_sc_dev *dev) +{ + u16 reg_idx, reg_id, tmp_reg_id, regfld_idx, regfld_id, tmp_regfld_id; + struct irdma_vchnl_reg_field_info *regfld_array = NULL; + u8 resp_buffer[IRDMA_REGMAP_RESP_BUF_SIZE] = {}; + struct vchnl_regfld_map_elem *regfld_map_array; + struct irdma_vchnl_req_init_info info = {}; + struct vchnl_reg_map_elem *reg_map_array; + struct irdma_vchnl_reg_info *reg_array; + u8 num_bits, shift_cnt; + u8 __iomem *hw_addr; + u16 buf_len = 0; + u64 bitmask; + u32 rindex; + int ret; + + if (!dev->vchnl_up) + return -EBUSY; + + info.op_code = IRDMA_VCHNL_OP_GET_REG_LAYOUT; + info.op_ver = IRDMA_VCHNL_OP_GET_REG_LAYOUT_V0; + info.resp_parm = resp_buffer; + info.resp_parm_len = sizeof(resp_buffer); + + ret = irdma_vchnl_req_send_sync(dev, &info); + + if (ret) + return ret; + + /* parse the response buffer and update reg info*/ + /* Parse registers till invalid */ + /* Parse register fields till invalid */ + reg_array = (struct irdma_vchnl_reg_info *)resp_buffer; + for (rindex = 0; rindex < IRDMA_VCHNL_REG_COUNT; rindex++) { + buf_len += sizeof(*reg_array); + if (buf_len >= sizeof(resp_buffer)) + return -ENOMEM; + + regfld_array = + (struct irdma_vchnl_reg_field_info *)®_array[rindex + 1]; + reg_id = reg_array[rindex].reg_id; + if (reg_id == IRDMA_VCHNL_REG_INV_ID) + break; + + reg_id &= ~IRDMA_VCHNL_REG_PAGE_REL; + if (reg_id >= IRDMA_VCHNL_REG_COUNT) + return -EINVAL; + + /* search regmap for register index in hw_regs.*/ + reg_map_array = vchnl_reg_map; + do { + tmp_reg_id = reg_map_array->reg_id; + if (tmp_reg_id == reg_id) + break; + + reg_map_array++; + } while (tmp_reg_id != IRDMA_VCHNL_REG_INV_ID); + if (tmp_reg_id != reg_id) + continue; + + reg_idx = reg_map_array->reg_idx; + hw_addr = dev->hw->hw_addr; + + /* Page relative, DB Offset do not need bar offset */ + if (reg_idx == IRDMA_DB_ADDR_OFFSET || + (reg_array[rindex].reg_id & IRDMA_VCHNL_REG_PAGE_REL)) + hw_addr = NULL; + + /* Update the local HW struct */ + dev->hw_regs[reg_idx] = + (u32 __iomem *)(hw_addr + reg_array[rindex].reg_offset); + } + + if (!regfld_array) + return -ENOMEM; + + /* set up doorbell variables using mapped DB page */ + dev->wqe_alloc_db = dev->hw_regs[IRDMA_WQEALLOC]; + dev->cq_arm_db = dev->hw_regs[IRDMA_CQARM]; + dev->aeq_alloc_db = dev->hw_regs[IRDMA_AEQALLOC]; + dev->cqp_db = dev->hw_regs[IRDMA_CQPDB]; + dev->cq_ack_db = dev->hw_regs[IRDMA_CQACK]; + + for (rindex = 0; rindex < IRDMA_VCHNL_REGFLD_COUNT; rindex++) { + buf_len += sizeof(*regfld_array); + if ((buf_len - 1) > sizeof(resp_buffer)) + break; + + if (regfld_array[rindex].fld_id == IRDMA_VCHNL_REGFLD_INV_ID) + break; + + regfld_id = regfld_array[rindex].fld_id; + regfld_map_array = vchnl_regfld_map; + do { + tmp_regfld_id = regfld_map_array->regfld_id; + if (tmp_regfld_id == regfld_id) + break; + + regfld_map_array++; + } while (tmp_regfld_id != IRDMA_VCHNL_REGFLD_INV_ID); + + if (tmp_regfld_id != regfld_id) + continue; + + regfld_idx = regfld_map_array->regfld_idx; + + num_bits = regfld_array[rindex].fld_bits; + shift_cnt = regfld_array[rindex].fld_shift; + if ((num_bits + shift_cnt > 64) || !num_bits) { + ibdev_dbg(to_ibdev(dev), + "ERR: Invalid field mask id %d bits %d shift %d", + regfld_id, num_bits, shift_cnt); + + continue; + } + + bitmask = (1ULL << num_bits) - 1; + dev->hw_masks[regfld_idx] = bitmask << shift_cnt; + dev->hw_shifts[regfld_idx] = shift_cnt; + } + + return 0; +} + +/** + * irdma_vchnl_req_aeq_vec_map - Map AEQ to vector on this function + * @dev: RDMA device pointer + * @v_idx: vector index + */ +int irdma_vchnl_req_aeq_vec_map(struct irdma_sc_dev *dev, u32 v_idx) +{ + struct irdma_vchnl_req_init_info info = {}; + struct irdma_vchnl_qvlist_info *qvl; + struct irdma_vchnl_qv_info *qv; + u16 qvl_size, num_vectors = 1; + int ret; + + if (!dev->vchnl_up) + return -EBUSY; + + qvl_size = struct_size(qvl, qv_info, num_vectors); + + qvl = kzalloc(qvl_size, GFP_KERNEL); + if (!qvl) + return -ENOMEM; + + qvl->num_vectors = 1; + qv = qvl->qv_info; + + qv->ceq_idx = IRDMA_Q_INVALID_IDX; + qv->v_idx = v_idx; + qv->itr_idx = IRDMA_IDX_ITR0; + + info.op_code = IRDMA_VCHNL_OP_QUEUE_VECTOR_MAP; + info.op_ver = IRDMA_VCHNL_OP_QUEUE_VECTOR_MAP_V0; + info.req_parm = qvl; + info.req_parm_len = qvl_size; + + ret = irdma_vchnl_req_send_sync(dev, &info); + kfree(qvl); + + return ret; +} + +/** + * irdma_vchnl_req_ceq_vec_map - Map CEQ to vector on this function + * @dev: RDMA device pointer + * @ceq_id: CEQ index + * @v_idx: vector index + */ +int irdma_vchnl_req_ceq_vec_map(struct irdma_sc_dev *dev, u16 ceq_id, u32 v_idx) +{ + struct irdma_vchnl_req_init_info info = {}; + struct irdma_vchnl_qvlist_info *qvl; + struct irdma_vchnl_qv_info *qv; + u16 qvl_size, num_vectors = 1; + int ret; + + if (!dev->vchnl_up) + return -EBUSY; + + qvl_size = struct_size(qvl, qv_info, num_vectors); + + qvl = kzalloc(qvl_size, GFP_KERNEL); + if (!qvl) + return -ENOMEM; + + qvl->num_vectors = num_vectors; + qv = qvl->qv_info; + + qv->aeq_idx = IRDMA_Q_INVALID_IDX; + qv->ceq_idx = ceq_id; + qv->v_idx = v_idx; + qv->itr_idx = IRDMA_IDX_ITR0; + + info.op_code = IRDMA_VCHNL_OP_QUEUE_VECTOR_MAP; + info.op_ver = IRDMA_VCHNL_OP_QUEUE_VECTOR_MAP_V0; + info.req_parm = qvl; + info.req_parm_len = qvl_size; + + ret = irdma_vchnl_req_send_sync(dev, &info); + kfree(qvl); + + return ret; +} + +/** + * irdma_vchnl_req_recv - Receive virtual channel messages on requester function + * @dev: RDMA device pointer + * @vf_id: Virtual function ID associated with the message + * @msg: Virtual channel message buffer pointer + * @len: Length of the virtual channels message + */ +int irdma_vchnl_req_recv(struct irdma_sc_dev *dev, u16 vf_id, u8 *msg, u16 len) +{ + if (len < sizeof(struct irdma_vchnl_resp_buf)) + return -EINVAL; + if (len > IRDMA_VCHNL_MAX_MSG_SIZE) + len = IRDMA_VCHNL_MAX_MSG_SIZE; + + memcpy(dev->vc_recv_buf, msg, len); + dev->vc_recv_len = len; + + return 0; +} + +/** + * irdma_vchnl_req_get_ver - Request Channel version + * @dev: RDMA device pointer + * @ver_req: Virtual channel version requested + * @ver_res: Virtual channel version response + */ +int irdma_vchnl_req_get_ver(struct irdma_sc_dev *dev, u16 ver_req, u32 *ver_res) +{ + struct irdma_vchnl_req_init_info info = {}; + int ret; + + if (!dev->vchnl_up) + return -EBUSY; + + info.op_code = IRDMA_VCHNL_OP_GET_VER; + info.op_ver = ver_req; + info.resp_parm = ver_res; + info.resp_parm_len = sizeof(*ver_res); + + ret = irdma_vchnl_req_send_sync(dev, &info); + if (ret) + return ret; + + if (*ver_res < IRDMA_VCHNL_CHNL_VER_MIN) { + ibdev_dbg(to_ibdev(dev), + "VIRT: %s unsupported vchnl version 0x%0x\n", + __func__, *ver_res); + return -EOPNOTSUPP; + } + + return 0; +} + +/** + * irdma_vchnl_req_get_hmc_fcn - Request VF HMC Function + * @dev: RDMA device pointer + */ +int irdma_vchnl_req_get_hmc_fcn(struct irdma_sc_dev *dev) +{ + struct irdma_vchnl_req_hmc_info req_hmc = {}; + struct irdma_vchnl_resp_hmc_info resp_hmc = {}; + struct irdma_vchnl_req_init_info info = {}; + int ret; + + if (!dev->vchnl_up) + return -EBUSY; + + info.op_code = IRDMA_VCHNL_OP_GET_HMC_FCN; + info.op_ver = IRDMA_VCHNL_OP_GET_HMC_FCN_V0; + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + info.op_ver = IRDMA_VCHNL_OP_GET_HMC_FCN_V2; + req_hmc.protocol_used = dev->protocol_used; + info.req_parm_len = sizeof(req_hmc); + info.req_parm = &req_hmc; + info.resp_parm = &resp_hmc; + info.resp_parm_len = sizeof(resp_hmc); + } + + ret = irdma_vchnl_req_send_sync(dev, &info); + + if (ret) + return ret; + + if (dev->hw_attrs.uk_attrs.hw_rev >= IRDMA_GEN_3) { + int i; + + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + dev->qos[i].qs_handle[0] = resp_hmc.qs_handle[i]; + dev->qos[i].valid = true; + } + } + return 0; +} + +/** + * irdma_vchnl_req_put_hmc_fcn - Free VF HMC Function + * @dev: RDMA device pointer + */ +int irdma_vchnl_req_put_hmc_fcn(struct irdma_sc_dev *dev) +{ + struct irdma_vchnl_req_init_info info = {}; + + if (!dev->vchnl_up) + return -EBUSY; + + info.op_code = IRDMA_VCHNL_OP_PUT_HMC_FCN; + info.op_ver = IRDMA_VCHNL_OP_PUT_HMC_FCN_V0; + + return irdma_vchnl_req_send_sync(dev, &info); +} + +/** + * irdma_vchnl_req_manage_ws_node - manage ws node + * @dev: RDMA device pointer + * @add: Add or remove ws node + * @user_pri: user priority of ws node + * @qs_handle: qs_handle updated from the vchnl response + */ +int irdma_vchnl_req_manage_ws_node(struct irdma_sc_dev *dev, bool add, + u8 user_pri, u16 *qs_handle) +{ + struct irdma_vchnl_manage_ws_node ws_node = {}; + struct irdma_vchnl_req_init_info info = {}; + + if (!dev->vchnl_up) + return -EBUSY; + + ws_node.add = add; + ws_node.user_pri = user_pri; + + info.op_code = IRDMA_VCHNL_OP_MANAGE_WS_NODE; + info.op_ver = IRDMA_VCHNL_OP_MANAGE_WS_NODE_V0; + info.req_parm = &ws_node; + info.req_parm_len = sizeof(ws_node); + if (add) { + info.resp_parm = qs_handle; + info.resp_parm_len = sizeof(*qs_handle); + } + + ibdev_dbg(to_ibdev(dev), + "VIRT: Sending message: manage_ws_node add = %d, user_pri = %d\n", + ws_node.add, ws_node.user_pri); + + return irdma_vchnl_req_send_sync(dev, &info); +} + +/** + * irdma_vchnl_req_add_hmc_objs - Add HMC Object + * @dev: RDMA device pointer + * @rsrc_type: HMC Resource type + * @start_index: Starting index of the objects to be added + * @rsrc_count: Number of resources to be added + */ +int irdma_vchnl_req_add_hmc_objs(struct irdma_sc_dev *dev, + enum irdma_hmc_rsrc_type rsrc_type, + u32 start_index, u32 rsrc_count) +{ + struct irdma_vchnl_hmc_obj_range add_hmc_obj = {}; + struct irdma_vchnl_req_init_info info = {}; + + if (!dev->vchnl_up) + return -EBUSY; + + add_hmc_obj.obj_type = (u16)rsrc_type; + add_hmc_obj.start_index = start_index; + add_hmc_obj.obj_count = rsrc_count; + + info.op_code = IRDMA_VCHNL_OP_ADD_HMC_OBJ_RANGE; + info.op_ver = IRDMA_VCHNL_OP_ADD_HMC_OBJ_RANGE_V0; + info.req_parm = &add_hmc_obj; + info.req_parm_len = sizeof(add_hmc_obj); + + ibdev_dbg(to_ibdev(dev), + "VIRT: Sending message: obj_type = %d, start_index = %d, obj_count = %d\n", + add_hmc_obj.obj_type, add_hmc_obj.start_index, + add_hmc_obj.obj_count); + + return irdma_vchnl_req_send_sync(dev, &info); +} + +/** + * irdma_vchnl_req_del_hmc_obj - del HMC obj + * @dev: RDMA device pointer + * @rsrc_type: HMC Resource type + * @start_index: Starting index of the object to delete + * @rsrc_count: Number of resources to be delete + */ +int irdma_vchnl_req_del_hmc_obj(struct irdma_sc_dev *dev, + enum irdma_hmc_rsrc_type rsrc_type, + u32 start_index, u32 rsrc_count) +{ + struct irdma_vchnl_hmc_obj_range hmc_obj = {}; + struct irdma_vchnl_req_init_info info = {}; + + if (!dev->vchnl_up) + return -EBUSY; + + hmc_obj.obj_type = (u16)rsrc_type; + hmc_obj.start_index = start_index; + hmc_obj.obj_count = rsrc_count; + + info.op_code = IRDMA_VCHNL_OP_DEL_HMC_OBJ_RANGE; + info.op_ver = IRDMA_VCHNL_OP_DEL_HMC_OBJ_RANGE_V0; + info.req_parm = &hmc_obj; + info.req_parm_len = sizeof(hmc_obj); + + return irdma_vchnl_req_send_sync(dev, &info); +} + +/** + * irdma_vchnl_req_get_vlan_parsing_cfg - Find if vlan should be processed + * @dev: Dev pointer + * @vlan_parse_en: vlan parsing enabled + */ +int irdma_vchnl_req_get_vlan_parsing_cfg(struct irdma_sc_dev *dev, + u8 *vlan_parse_en) +{ + struct irdma_vchnl_req_init_info info = {}; + + if (!dev->vchnl_up) + return -EBUSY; + + info.op_code = IRDMA_VCHNL_OP_VLAN_PARSING; + info.op_ver = IRDMA_VCHNL_OP_VLAN_PARSING_V0; + info.req_parm = vlan_parse_en; + info.req_parm_len = sizeof(*vlan_parse_en); + info.resp_parm = vlan_parse_en; + info.resp_parm_len = sizeof(*vlan_parse_en); + + return irdma_vchnl_req_send_sync(dev, &info); +} + +/** + * irdma_vchnl_req_get_caps - Request RDMA capabilities + * @dev: RDMA device pointer + */ +int irdma_vchnl_req_get_caps(struct irdma_sc_dev *dev) +{ + struct irdma_vchnl_req_init_info info = {}; + int ret; + + if (!dev->vchnl_up) + return -EBUSY; + + info.op_code = IRDMA_VCHNL_OP_GET_RDMA_CAPS; + info.op_ver = IRDMA_VCHNL_OP_GET_RDMA_CAPS_V0; + info.resp_parm = &dev->vc_caps; + info.resp_parm_len = sizeof(dev->vc_caps); + + ret = irdma_vchnl_req_send_sync(dev, &info); + + if (ret) + return ret; + + if (!dev->vc_caps.max_hw_push_len) + dev->vc_caps.max_hw_push_len = IRDMA_DEFAULT_MAX_PUSH_LEN; + + if (dev->vc_caps.hw_rev > IRDMA_GEN_MAX || + dev->vc_caps.hw_rev < IRDMA_GEN_2) { + ibdev_dbg(to_ibdev(dev), + "ERR: %s unsupported hw_rev version 0x%0x\n", + __func__, dev->vc_caps.hw_rev); + return -EOPNOTSUPP; + } + + return 0; +} + +/** + * irdma_vchnl_req_get_resp - Receive the inbound vchnl response. + * @dev: Dev pointer + * @vchnl_req: Vchannel request + */ +int irdma_vchnl_req_get_resp(struct irdma_sc_dev *dev, + struct irdma_vchnl_req *vchnl_req) +{ + struct irdma_vchnl_resp_buf *vchnl_msg_resp = + (struct irdma_vchnl_resp_buf *)dev->vc_recv_buf; + u16 resp_len; + int ret; + + if ((uintptr_t)vchnl_req != (uintptr_t)vchnl_msg_resp->op_ctx) { + ibdev_dbg(to_ibdev(dev), + "VIRT: error vchnl context value does not match\n"); + return -EBADMSG; + } + + resp_len = dev->vc_recv_len - sizeof(*vchnl_msg_resp); + resp_len = min(resp_len, vchnl_req->parm_len); + + if (irdma_vchnl_req_verify_resp(vchnl_req, resp_len)) + return -EBADMSG; + + ret = (int)vchnl_msg_resp->op_ret; + if (ret) + return ret; + + vchnl_req->resp_len = 0; + if (vchnl_req->parm_len && vchnl_req->parm && resp_len) { + memcpy(vchnl_req->parm, vchnl_msg_resp->buf, resp_len); + vchnl_req->resp_len = resp_len; + ibdev_dbg(to_ibdev(dev), "VIRT: Got response, data size %u\n", + resp_len); + } + + return 0; +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/virtchnl.h b/drivers/intel/irdma-1.14.33/src/irdma/virtchnl.h new file mode 100644 index 000000000..15b1a61e6 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/virtchnl.h @@ -0,0 +1,224 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef IRDMA_VIRTCHNL_H +#define IRDMA_VIRTCHNL_H + +#include "hmc.h" +#include "irdma.h" + +/* IRDMA_VCHNL_CHNL_VER_V0 is for legacy hw, no longer supported. */ +#define IRDMA_VCHNL_CHNL_VER_V1 1 +#define IRDMA_VCHNL_CHNL_VER_V2 2 +#define IRDMA_VCHNL_CHNL_VER_MIN IRDMA_VCHNL_CHNL_VER_V1 +#define IRDMA_VCHNL_CHNL_VER_MAX IRDMA_VCHNL_CHNL_VER_V2 + +#define IRDMA_VCHNL_OP_GET_VER_V0 0 +#define IRDMA_VCHNL_OP_GET_VER_V1 1 +#define IRDMA_VCHNL_OP_GET_VER_V2 2 + +#define IRDMA_VCHNL_OP_GET_HMC_FCN_V0 0 +#define IRDMA_VCHNL_OP_GET_HMC_FCN_V1 1 +#define IRDMA_VCHNL_OP_GET_HMC_FCN_V2 2 +#define IRDMA_VCHNL_OP_PUT_HMC_FCN_V0 0 +#define IRDMA_VCHNL_OP_MANAGE_PUSH_PAGE_V0 0 +#define IRDMA_VCHNL_OP_GET_REG_LAYOUT_V0 0 +#define IRDMA_VCHNL_OP_QUEUE_VECTOR_MAP_V0 0 +#define IRDMA_VCHNL_OP_QUEUE_VECTOR_UNMAP_V0 0 +#define IRDMA_VCHNL_OP_GET_RDMA_CAPS_V0 0 +#define IRDMA_VCHNL_OP_GET_RDMA_CAPS_MIN_SIZE 1 +#define IRDMA_VCHNL_OP_ADD_HMC_OBJ_RANGE_V0 0 +#define IRDMA_VCHNL_OP_DEL_HMC_OBJ_RANGE_V0 0 +#define IRDMA_VCHNL_OP_MANAGE_WS_NODE_V0 0 +#define IRDMA_VCHNL_OP_VLAN_PARSING_V0 0 + +#define IRDMA_VCHNL_INVALID_VF_IDX 0xFFFF + +#define IRDMA_VCHNL_REG_ID_CQPTAIL 0 +#define IRDMA_VCHNL_REG_ID_CQPDB 1 +#define IRDMA_VCHNL_REG_ID_CCQPSTATUS 2 +#define IRDMA_VCHNL_REG_ID_CCQPHIGH 3 +#define IRDMA_VCHNL_REG_ID_CCQPLOW 4 +#define IRDMA_VCHNL_REG_ID_CQARM 5 +#define IRDMA_VCHNL_REG_ID_CQACK 6 +#define IRDMA_VCHNL_REG_ID_AEQALLOC 7 +#define IRDMA_VCHNL_REG_ID_CQPERRCODES 8 +#define IRDMA_VCHNL_REG_ID_WQEALLOC 9 +#define IRDMA_VCHNL_REG_ID_IPCONFIG0 10 +#define IRDMA_VCHNL_REG_ID_DB_ADDR_OFFSET 11 +#define IRDMA_VCHNL_REG_ID_DYN_CTL 12 +#define IRDMA_VCHNL_REG_ID_AEQITRMASK 13 +#define IRDMA_VCHNL_REG_ID_CEQITRMASK 14 +#define IRDMA_VCHNL_REG_INV_ID 0xFFFF +#define IRDMA_VCHNL_REG_PAGE_REL 0x8000 + +#define IRDMA_VCHNL_REGFLD_ID_CCQPSTATUS_CQP_OP_ERR 2 +#define IRDMA_VCHNL_REGFLD_ID_CCQPSTATUS_CCQP_DONE 5 +#define IRDMA_VCHNL_REGFLD_ID_CQPSQ_STAG_PDID 6 +#define IRDMA_VCHNL_REGFLD_ID_CQPSQ_CQ_CEQID 7 +#define IRDMA_VCHNL_REGFLD_ID_CQPSQ_CQ_CQID 8 +#define IRDMA_VCHNL_REGFLD_ID_COMMIT_FPM_CQCNT 9 +#define IRDMA_VCHNL_REGFLD_ID_UPESD_HMCN_ID 10 +#define IRDMA_VCHNL_REGFLD_INV_ID 0xFFFF + +#define IRDMA_VCHNL_RESP_MIN_SIZE (sizeof(struct irdma_vchnl_resp_buf)) + +enum irdma_vchnl_ops { + IRDMA_VCHNL_OP_GET_VER = 0, + IRDMA_VCHNL_OP_GET_HMC_FCN = 1, + IRDMA_VCHNL_OP_PUT_HMC_FCN = 2, + IRDMA_VCHNL_OP_ADD_HMC_OBJ_RANGE = 3, + IRDMA_VCHNL_OP_DEL_HMC_OBJ_RANGE = 4, +/* Unused OPs. Do not delete as OP numbers are ABI */ + IRDMA_VCHNL_OP_MANAGE_STATS_INST = 6, + IRDMA_VCHNL_OP_MCG = 7, + IRDMA_VCHNL_OP_UP_MAP = 8, + IRDMA_VCHNL_OP_MANAGE_WS_NODE = 9, + IRDMA_VCHNL_OP_MANAGE_PUSH_PAGE = 10, + IRDMA_VCHNL_OP_GET_REG_LAYOUT = 11, + IRDMA_VCHNL_OP_VLAN_PARSING = 12, + IRDMA_VCHNL_OP_GET_RDMA_CAPS = 13, + IRDMA_VCHNL_OP_QUEUE_VECTOR_MAP = 14, + IRDMA_VCHNL_OP_QUEUE_VECTOR_UNMAP = 15, +}; + +#pragma pack(push, 1) +struct irdma_vchnl_req_hmc_info { + u8 protocol_used; + u8 disable_qos; +}; + +struct irdma_vchnl_resp_hmc_info { + u16 hmc_func; + u16 qs_handle[IRDMA_MAX_USER_PRIORITY]; +}; + +struct irdma_vchnl_qv_info { + u32 v_idx; + u16 ceq_idx; + u16 aeq_idx; + u8 itr_idx; +}; + +struct irdma_vchnl_qvlist_info { + u32 num_vectors; + struct irdma_vchnl_qv_info qv_info[]; +}; +struct irdma_vchnl_op_buf { + u16 op_code; + u16 op_ver; + u16 buf_len; + u16 rsvd; + u64 op_ctx; + /* Member alignment MUST be maintained above this location */ + u8 buf[]; +}; + +struct irdma_vchnl_resp_buf { + u64 op_ctx; + u16 buf_len; + s16 op_ret; + /* Member alignment MUST be maintained above this location */ + u16 rsvd[2]; + u8 buf[]; +}; + +struct irdma_vchnl_hmc_obj_range { + u16 obj_type; + u16 rsvd; + u32 start_index; + u32 obj_count; +}; + +struct irdma_vchnl_manage_ws_node { + u8 add; + u8 user_pri; +}; + +struct irdma_vchnl_rdma_caps { + u8 hw_rev; + u16 cqp_timeout_s; + u16 cqp_def_timeout_s; + u16 max_hw_push_len; +}; + +struct irdma_vchnl_init_info { + struct workqueue_struct *vchnl_wq; + struct irdma_vchnl_if *vchnl_if; + enum irdma_vers hw_rev; + bool privileged; + bool is_pf; +}; + +struct irdma_vchnl_manage_push_page { + u8 page_type; + u8 add; + u32 pg_idx; + u32 qs_handle; +}; + +struct irdma_vchnl_reg_info { + u32 reg_offset; + u16 field_cnt; + u16 reg_id; /* High bit of reg_id: bar or page relative */ +}; + +struct irdma_vchnl_reg_field_info { + u8 fld_shift; + u8 fld_bits; + u16 fld_id; +}; + +struct irdma_vchnl_req { + struct irdma_vchnl_op_buf *vchnl_msg; + void *parm; + u32 vf_id; + u16 parm_len; + u16 resp_len; +}; + +struct irdma_vchnl_req_init_info { + void *req_parm; + void *resp_parm; + u16 req_parm_len; + u16 resp_parm_len; + u16 op_code; + u16 op_ver; +}; + +#pragma pack(pop) + +int irdma_sc_vchnl_init(struct irdma_sc_dev *dev, + struct irdma_vchnl_init_info *info); +int irdma_vchnl_req_add_hmc_objs(struct irdma_sc_dev *dev, + enum irdma_hmc_rsrc_type rsrc_type, + u32 start_index, u32 rsrc_count); +int irdma_vchnl_req_del_hmc_obj(struct irdma_sc_dev *dev, + enum irdma_hmc_rsrc_type rsrc_type, + u32 start_index, u32 rsrc_count); +int irdma_vchnl_req_manage_ws_node(struct irdma_sc_dev *dev, bool add, + u8 user_pri, u16 *qs_handle); +int irdma_vchnl_req_get_vlan_parsing_cfg(struct irdma_sc_dev *dev, + u8 *vlan_parse_en); +int irdma_vchnl_send_sync(struct irdma_sc_dev *dev, u8 *msg, u16 len, + u8 *recv_msg, u16 *recv_len); +int irdma_vchnl_req_recv(struct irdma_sc_dev *dev, u16 vf_id, u8 *msg, u16 len); +int irdma_vchnl_req_get_ver(struct irdma_sc_dev *dev, u16 ver_req, u32 *ver_res); +int irdma_vchnl_req_get_hmc_fcn(struct irdma_sc_dev *dev); +int irdma_vchnl_req_put_hmc_fcn(struct irdma_sc_dev *dev); +int irdma_vchnl_req_get_caps(struct irdma_sc_dev *dev); +int irdma_vchnl_req_get_resp(struct irdma_sc_dev *dev, + struct irdma_vchnl_req *vc_req); +int irdma_vchnl_req_manage_push_pg(struct irdma_sc_dev *dev, bool add, + u32 qs_handle, u32 *pg_idx); +int irdma_vchnl_req_get_reg_layout(struct irdma_sc_dev *dev); +int irdma_vchnl_req_aeq_vec_map(struct irdma_sc_dev *dev, u32 v_idx); +int irdma_vchnl_req_ceq_vec_map(struct irdma_sc_dev *dev, u16 ceq_id, + u32 v_idx); +int irdma_vchnl_send_pf(struct irdma_sc_dev *dev, u16 vf_id, u8 *msg, u16 len); +int irdma_vchnl_recv_pf(struct irdma_sc_dev *dev, u16 vf_id, u8 *msg, u16 len); +struct irdma_vchnl_dev *irdma_find_vc_dev(struct irdma_sc_dev *dev, u16 vf_id); +void irdma_put_vfdev(struct irdma_sc_dev *dev, struct irdma_vchnl_dev *vc_dev); +void irdma_remove_vc_dev(struct irdma_sc_dev *dev, struct irdma_vchnl_dev *vc_dev); +void irdma_pf_put_vf_hmc_fcn(struct irdma_sc_dev *dev, + struct irdma_vchnl_dev *vc_dev); +#endif /* IRDMA_VIRTCHNL_H */ diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ws.c b/drivers/intel/irdma-1.14.33/src/irdma/ws.c new file mode 100644 index 000000000..2cd150197 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ws.c @@ -0,0 +1,737 @@ +// SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB +/* Copyright (c) 2017 - 2023 Intel Corporation */ +#include "osdep.h" +#include "hmc.h" +#include "defs.h" +#include "type.h" +#include "protos.h" +#include "virtchnl.h" + +#include "ws.h" + +#include "iidc.h" + +/** + * irdma_alloc_node - Allocate a WS node and init + * @vsi: vsi pointer + * @user_pri: user priority + * @node_type: Type of node, leaf or parent + * @parent: parent node pointer + */ +static struct irdma_ws_node *irdma_alloc_node(struct irdma_sc_vsi *vsi, + u8 user_pri, + enum irdma_ws_node_type node_type, + struct irdma_ws_node *parent) +{ + struct irdma_virt_mem ws_mem; + struct irdma_ws_node *node; + u16 node_index = 0; + + ws_mem.size = sizeof(*node); + ws_mem.va = kzalloc(ws_mem.size, GFP_KERNEL); + if (!ws_mem.va) + return NULL; + + if (parent || vsi->vm_vf_type == IRDMA_VF_TYPE) { + node_index = irdma_alloc_ws_node_id(vsi->dev); + if (node_index == IRDMA_WS_NODE_INVALID) { + kfree(ws_mem.va); + return NULL; + } + } + + node = ws_mem.va; + node->index = node_index; + node->vsi_index = vsi->vsi_idx; + INIT_LIST_HEAD(&node->child_list_head); + if (node_type == WS_NODE_TYPE_LEAF) { + node->type_leaf = true; + node->traffic_class = vsi->qos[user_pri].traffic_class; + node->user_pri = user_pri; + node->rel_bw = vsi->qos[user_pri].rel_bw; + if (!node->rel_bw) + node->rel_bw = 1; + + node->prio_type = IRDMA_PRIO_WEIGHTED_RR; + } else { + node->rel_bw = 1; + node->prio_type = IRDMA_PRIO_WEIGHTED_RR; + node->enable = true; + } + + node->parent = parent; + + return node; +} + +/** + * irdma_free_node - Free a WS node + * @vsi: VSI stricture of device + * @node: Pointer to node to free + */ +static void irdma_free_node(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *node) +{ + struct irdma_virt_mem ws_mem; + + if (node->index) + irdma_free_ws_node_id(vsi->dev, node->index); + + ws_mem.va = node; + ws_mem.size = sizeof(*node); + kfree(ws_mem.va); +} + +/** + * irdma_ws_cqp_cmd - Post CQP work scheduler node cmd + * @vsi: vsi pointer + * @node: pointer to node + * @cmd: add, remove or modify + * @qs_handle: Pointer to store the qs_handle for a leaf node + */ +static int irdma_ws_cqp_cmd(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *node, u8 cmd, u16 *qs_handle) +{ + struct irdma_ws_node_info node_info = {}; + + node_info.id = node->index; + node_info.vsi = node->vsi_index; + if (node->parent) + node_info.parent_id = node->parent->index; + else + node_info.parent_id = node_info.id; + + node_info.weight = node->rel_bw; + node_info.tc = node->traffic_class; + node_info.prio_type = node->prio_type; + node_info.type_leaf = node->type_leaf; + node_info.failing_port = node->failing_port; + node_info.active_port = node->active_port; + node_info.assign_to_active_port = node->assign_to_active_port; + node_info.enable = node->enable; + if (irdma_cqp_ws_node_cmd(vsi->dev, cmd, &node_info)) { + ibdev_dbg(to_ibdev(vsi->dev), "WS: CQP WS CMD failed\n"); + return -ENOMEM; + } + + if (node->type_leaf && cmd == IRDMA_OP_WS_ADD_NODE && qs_handle) + *qs_handle = node_info.qs_handle; + + return 0; +} + +/** + * ws_find_node - Find SC WS node based on VSI id or TC + * @parent: parent node of First VSI or TC node + * @match_val: value to match + * @type: match type VSI/TC + */ +static struct irdma_ws_node *ws_find_node(struct irdma_ws_node *parent, + u16 match_val, + enum irdma_ws_match_type type) +{ + struct irdma_ws_node *node; + + switch (type) { + case WS_MATCH_TYPE_VSI: + list_for_each_entry(node, &parent->child_list_head, siblings) { + if (node->vsi_index == match_val) + return node; + } + break; + case WS_MATCH_TYPE_TC: + list_for_each_entry(node, &parent->child_list_head, siblings) { + if (node->traffic_class == match_val) + return node; + } + break; + default: + break; + } + + return NULL; +} + +/** + * irdma_ws_in_use - Checks to see if a leaf node is in use + * @vsi: vsi pointer + * @user_pri: user priority + */ +static bool irdma_ws_in_use(struct irdma_sc_vsi *vsi, u8 user_pri) +{ + int i; + + mutex_lock(&vsi->qos[user_pri].qos_mutex); + if (!list_empty(&vsi->qos[user_pri].qplist)) { + mutex_unlock(&vsi->qos[user_pri].qos_mutex); + return true; + } + + /* Check if the qs handle associated with the given user priority + * is in use by any other user priority. If so, nothing left to do + */ + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + if (vsi->qos[i].qs_handle[0] == vsi->qos[user_pri].qs_handle[0] && + !list_empty(&vsi->qos[i].qplist)) { + mutex_unlock(&vsi->qos[user_pri].qos_mutex); + return true; + } + } + mutex_unlock(&vsi->qos[user_pri].qos_mutex); + + return false; +} + +static void irdma_lag_setup_tc_node(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node, + bool first_node) +{ + tc_node->assign_to_active_port = true; + if (first_node) { + /* Default first TC node to primary port unless only secondary port is up */ + if ((vsi->lag_port_bitmap & IIDC_RDMA_BOTH_PORT) == + IIDC_RDMA_SECONDARY_PORT) { + tc_node->active_port = + vsi->lag_ports[IRDMA_LAG_SECONDARY_IDX]; + if (tc_node->active_port == IIDC_RDMA_INVALID_PORT) + tc_node->active_port = + vsi->lag_ports[IRDMA_LAG_PRIMARY_IDX]; + vsi->primary_port_migrated = true; + } else { + tc_node->active_port = + vsi->lag_ports[IRDMA_LAG_PRIMARY_IDX]; + if (tc_node->active_port == IIDC_RDMA_INVALID_PORT) + tc_node->active_port = + vsi->lag_ports[IRDMA_LAG_SECONDARY_IDX]; + vsi->primary_port_migrated = false; + } + } else { + /* If secondary port is not active default to primary if it's active */ + if ((vsi->lag_port_bitmap & IIDC_RDMA_BOTH_PORT) == + IIDC_RDMA_SECONDARY_PORT) { + tc_node->active_port = + vsi->lag_ports[IRDMA_LAG_PRIMARY_IDX]; + if (tc_node->active_port == IIDC_RDMA_INVALID_PORT) + tc_node->active_port = + vsi->lag_ports[IRDMA_LAG_SECONDARY_IDX]; + vsi->secondary_port_migrated = true; + } else { + tc_node->active_port = + vsi->lag_ports[IRDMA_LAG_SECONDARY_IDX]; + if (tc_node->active_port == IIDC_RDMA_INVALID_PORT) + tc_node->active_port = + vsi->lag_ports[IRDMA_LAG_PRIMARY_IDX]; + vsi->secondary_port_migrated = false; + } + } +} + +static void irdma_add_node_id(u16 *node_ids, u16 idx) +{ + int i; + + /* Save the node ID in an available slot indicated by 0 */ + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + if (!node_ids[i]) { + node_ids[i] = idx; + return; + } + } +} + +static void irdma_remove_node_id(u16 *node_ids, u16 idx) +{ + int i; + + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + if (node_ids[i] == idx) { + node_ids[i] = 0; + return; + } + } +} + +/** + * irdma_remove_leaf - Remove leaf node unconditionally + * @vsi: vsi pointer + * @user_pri: user priority + */ +static void irdma_remove_leaf(struct irdma_sc_vsi *vsi, u8 user_pri) +{ + struct irdma_ws_node *ws_tree_root, *vsi_node, *tc_node; + struct irdma_ws_node *tc_node2 = NULL; + u16 qs_handle; + int i; + + qs_handle = vsi->qos[user_pri].qs_handle[0]; + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + if (vsi->qos[i].qs_handle[0] == qs_handle) + vsi->qos[i].valid = false; + } + + if (!vsi->dev->privileged) { + int ret; + + ret = irdma_vchnl_req_manage_ws_node(vsi->dev, false, user_pri, + NULL); + if (ret) + ibdev_dbg(to_ibdev(vsi->dev), + "VIRT: Send message failed ret = %d \n", + ret); + + return; + } + + ws_tree_root = vsi->dev->ws_tree_root; + if (!ws_tree_root) + return; + + vsi_node = ws_find_node(ws_tree_root, vsi->vsi_idx, + WS_MATCH_TYPE_VSI); + if (!vsi_node) + return; + + tc_node = ws_find_node(vsi_node, + vsi->qos[user_pri].traffic_class, + WS_MATCH_TYPE_TC); + if (!tc_node) + return; + + list_del(&tc_node->siblings); + if (vsi->lag_aa) { + tc_node2 = ws_find_node(vsi_node, + vsi->qos[user_pri].traffic_class, + WS_MATCH_TYPE_TC); + if (!tc_node2) + return; + pr_info("%s: Second TC node found. Removing.\n", __func__); + list_del(&tc_node2->siblings); + irdma_ws_cqp_cmd(vsi, tc_node2, IRDMA_OP_WS_DELETE_NODE, NULL); + + irdma_remove_node_id(vsi->primary_port_node_ids, tc_node->index); + irdma_remove_node_id(vsi->secondary_port_node_ids, tc_node2->index); + } + irdma_ws_cqp_cmd(vsi, tc_node, IRDMA_OP_WS_DELETE_NODE, NULL); + + vsi->unregister_qset(vsi, tc_node2, tc_node); + irdma_free_node(vsi, tc_node); + if (tc_node2) + irdma_free_node(vsi, tc_node2); + /* Check if VSI node can be freed */ + if (list_empty(&vsi_node->child_list_head)) { + irdma_ws_cqp_cmd(vsi, vsi_node, IRDMA_OP_WS_DELETE_NODE, NULL); + list_del(&vsi_node->siblings); + irdma_free_node(vsi, vsi_node); + /* Free head node there are no remaining VSI nodes */ + if (list_empty(&ws_tree_root->child_list_head)) { + irdma_ws_cqp_cmd(vsi, ws_tree_root, + IRDMA_OP_WS_DELETE_NODE, NULL); + irdma_free_node(vsi, ws_tree_root); + vsi->dev->ws_tree_root = NULL; + } + } +} + +static int irdma_enable_leaves(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *tc_node1, + struct irdma_ws_node *tc_node2) +{ + int ret; + + ret = vsi->register_qset(vsi, tc_node1, tc_node2); + if (ret) + return ret; + + tc_node1->enable = true; + ret = irdma_ws_cqp_cmd(vsi, tc_node1, IRDMA_OP_WS_MODIFY_NODE, NULL); + if (ret) + goto enable_err; + if (tc_node2) { + tc_node2->enable = true; + ret = irdma_ws_cqp_cmd(vsi, tc_node2, IRDMA_OP_WS_MODIFY_NODE, NULL); + if (ret) + goto enable_err; + } + return 0; + +enable_err: + vsi->unregister_qset(vsi, tc_node1, tc_node2); + + return ret; +} + +static struct irdma_ws_node *irdma_add_leaf_node(struct irdma_sc_vsi *vsi, + struct irdma_ws_node *vsi_node, + u8 user_pri, u16 traffic_class) +{ + struct irdma_ws_node *tc_node = + irdma_alloc_node(vsi, user_pri, WS_NODE_TYPE_LEAF, vsi_node); + struct irdma_ws_node *tc_node2 = NULL; + int i, ret = 0; + + if (!tc_node) + return NULL; + if (vsi->lag_aa) + irdma_lag_setup_tc_node(vsi, tc_node, true); + ret = irdma_ws_cqp_cmd(vsi, tc_node, IRDMA_OP_WS_ADD_NODE, &tc_node->qs_handle); + if (ret) { + irdma_free_node(vsi, tc_node); + return NULL; + } + vsi->qos[tc_node->user_pri].qs_handle[0] = tc_node->qs_handle; + + list_add(&tc_node->siblings, &vsi_node->child_list_head); + + if (vsi->lag_aa) { + irdma_add_node_id(vsi->primary_port_node_ids, tc_node->index); + pr_info("%s: First TC node ID=%d, using active_port = %d\n", + __func__, tc_node->index, tc_node->active_port); + tc_node2 = irdma_alloc_node(vsi, user_pri, WS_NODE_TYPE_LEAF, + vsi_node); + if (!tc_node2) { + irdma_remove_node_id(vsi->primary_port_node_ids, tc_node->index); + goto reg_err; + } + irdma_lag_setup_tc_node(vsi, tc_node2, false); + ret = irdma_ws_cqp_cmd(vsi, tc_node2, IRDMA_OP_WS_ADD_NODE, + &tc_node2->qs_handle); + if (ret) { + irdma_remove_node_id(vsi->primary_port_node_ids, + tc_node->index); + irdma_free_node(vsi, tc_node2); + tc_node2 = NULL; + goto reg_err; + } + vsi->qos[tc_node2->user_pri].qs_handle[1] = tc_node2->qs_handle; + irdma_add_node_id(vsi->secondary_port_node_ids, tc_node2->index); + pr_info("%s: Second TC node ID=%d, using active_port = %d\n", + __func__, tc_node2->index, tc_node2->active_port); + + list_add(&tc_node2->siblings, &vsi_node->child_list_head); + } + + ret = irdma_enable_leaves(vsi, tc_node, tc_node2); + if (ret) { + irdma_remove_node_id(vsi->primary_port_node_ids, tc_node->index); + if (tc_node2) + irdma_remove_node_id(vsi->secondary_port_node_ids, + tc_node2->index); + goto reg_err; + } + + /* + * Iterate through other UPs and update the QS handle if they have + * a matching traffic class. + */ + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; i++) { + if (vsi->qos[i].traffic_class == traffic_class) { + vsi->qos[i].qs_handle[0] = tc_node->qs_handle; + vsi->qos[i].l2_sched_node_id[0] = + tc_node->l2_sched_node_id; + if (tc_node2) { + vsi->qos[i].qs_handle[1] = tc_node2->qs_handle; + vsi->qos[i].l2_sched_node_id[1] = + tc_node2->l2_sched_node_id; + } + vsi->qos[i].valid = true; + } + } + return tc_node; + +reg_err: + if (tc_node2) { + irdma_ws_cqp_cmd(vsi, tc_node2, IRDMA_OP_WS_DELETE_NODE, NULL); + list_del(&tc_node2->siblings); + irdma_free_node(vsi, tc_node2); + } + irdma_ws_cqp_cmd(vsi, tc_node, IRDMA_OP_WS_DELETE_NODE, NULL); + list_del(&tc_node->siblings); + irdma_free_node(vsi, tc_node); + + return NULL; +} + +/** + * irdma_ws_add - Build work scheduler tree, set RDMA qs_handle + * @vsi: vsi pointer + * @user_pri: user priority + */ +int irdma_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri) +{ + struct irdma_ws_node *ws_tree_root; + struct irdma_ws_node *vsi_node; + struct irdma_ws_node *tc_node; + u16 traffic_class; + int ret = 0; + + mutex_lock(&vsi->dev->ws_mutex); + if (vsi->tc_change_pending) { + ret = -EBUSY; + goto exit; + } + + if (vsi->qos[user_pri].valid) + goto exit; + + if (!vsi->dev->privileged) { + u16 vf_qs_handle; + + ret = irdma_vchnl_req_manage_ws_node(vsi->dev, true, user_pri, + &vf_qs_handle); + if (ret) { + ibdev_dbg(to_ibdev(vsi->dev), + "VIRT: Send message failed ret = %d\n", ret); + goto exit; + } + + vsi->qos[user_pri].qs_handle[0] = vf_qs_handle; + vsi->qos[user_pri].valid = true; + goto exit; + } + + ws_tree_root = vsi->dev->ws_tree_root; + if (!ws_tree_root) { + ws_tree_root = irdma_alloc_node(vsi, user_pri, + WS_NODE_TYPE_PARENT, NULL); + if (!ws_tree_root) { + ret = -ENOMEM; + goto exit; + } + ibdev_dbg(to_ibdev(vsi->dev), "WS: Creating root node = %d\n", + ws_tree_root->index); + + ret = irdma_ws_cqp_cmd(vsi, ws_tree_root, IRDMA_OP_WS_ADD_NODE, + NULL); + if (ret) { + irdma_free_node(vsi, ws_tree_root); + goto exit; + } + + vsi->dev->ws_tree_root = ws_tree_root; + } + + /* Find a second tier node that matches the VSI */ + vsi_node = ws_find_node(ws_tree_root, vsi->vsi_idx, + WS_MATCH_TYPE_VSI); + + /* If VSI node doesn't exist, add one */ + if (!vsi_node) { + ibdev_dbg(to_ibdev(vsi->dev), + "WS: Node not found matching VSI %d\n", + vsi->vsi_idx); + vsi_node = irdma_alloc_node(vsi, user_pri, WS_NODE_TYPE_PARENT, + ws_tree_root); + if (!vsi_node) { + ret = -ENOMEM; + goto vsi_add_err; + } + + ret = irdma_ws_cqp_cmd(vsi, vsi_node, IRDMA_OP_WS_ADD_NODE, + NULL); + if (ret) { + irdma_free_node(vsi, vsi_node); + goto vsi_add_err; + } + + list_add(&vsi_node->siblings, &ws_tree_root->child_list_head); + } + + ibdev_dbg(to_ibdev(vsi->dev), + "WS: Using node %d which represents VSI %d\n", + vsi_node->index, vsi->vsi_idx); + traffic_class = vsi->qos[user_pri].traffic_class; + tc_node = ws_find_node(vsi_node, traffic_class, + WS_MATCH_TYPE_TC); + if (!tc_node) { + /* Add leaf node */ + ibdev_dbg(to_ibdev(vsi->dev), + "WS: Node not found matching VSI %d and TC %d\n", + vsi->vsi_idx, traffic_class); + tc_node = irdma_add_leaf_node(vsi, vsi_node, user_pri, + traffic_class); + if (!tc_node) { + ret = -ENOMEM; + goto leaf_add_err; + } + } + ibdev_dbg(to_ibdev(vsi->dev), + "WS: Using node %d which represents VSI %d TC %d\n", + tc_node->index, vsi->vsi_idx, traffic_class); + goto exit; + +leaf_add_err: + if (list_empty(&vsi_node->child_list_head)) { + if (irdma_ws_cqp_cmd(vsi, vsi_node, IRDMA_OP_WS_DELETE_NODE, + NULL)) + goto exit; + list_del(&vsi_node->siblings); + irdma_free_node(vsi, vsi_node); + } + +vsi_add_err: + /* Free head node there are no remaining VSI nodes */ + if (list_empty(&ws_tree_root->child_list_head)) { + irdma_ws_cqp_cmd(vsi, ws_tree_root, IRDMA_OP_WS_DELETE_NODE, + NULL); + vsi->dev->ws_tree_root = NULL; + irdma_free_node(vsi, ws_tree_root); + } + +exit: + mutex_unlock(&vsi->dev->ws_mutex); + return ret; +} + +/** + * irdma_ws_remove - Free WS scheduler node, update WS tree + * @vsi: vsi pointer + * @user_pri: user priority + */ +void irdma_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri) +{ + mutex_lock(&vsi->dev->ws_mutex); + if (irdma_ws_in_use(vsi, user_pri)) + goto exit; + irdma_remove_leaf(vsi, user_pri); +exit: + mutex_unlock(&vsi->dev->ws_mutex); +} + +/** + * irdma_ws_reset - Reset entire WS tree + * @vsi: vsi pointer + */ +void irdma_ws_reset(struct irdma_sc_vsi *vsi) +{ + u8 i; + + mutex_lock(&vsi->dev->ws_mutex); + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; ++i) + irdma_remove_leaf(vsi, i); + mutex_unlock(&vsi->dev->ws_mutex); +} + +static u8 irdma_move_nodes(u16 *dest_nodes, u16 *src_nodes) +{ + int i; + u8 num_nodes = 0; + + for (i = 0; i < IRDMA_MAX_USER_PRIORITY; ++i) { + if (src_nodes[i]) + dest_nodes[num_nodes++] = src_nodes[i]; + } + return num_nodes; +} + +/** + * irdma_ws_move_cmd - Perform Scheduler Move CQP command + * @vsi: vsi pointer + */ +void irdma_ws_move_cmd(struct irdma_sc_vsi *vsi) +{ + struct irdma_ws_move_node_info move_ws_node = {}; + int i; + + mutex_lock(&vsi->dev->ws_mutex); + if ((vsi->lag_port_bitmap & IIDC_RDMA_BOTH_PORT) == + IIDC_RDMA_BOTH_PORT) { /* if both ports are active */ + if (vsi->primary_port_migrated) { /* if primary port was in failed state */ + vsi->primary_port_migrated = false; + /* move all primary port nodes back to the primary port */ + move_ws_node.target_port = + vsi->lag_ports[IRDMA_LAG_PRIMARY_IDX]; + move_ws_node.num_nodes = + irdma_move_nodes(move_ws_node.node_id, + vsi->primary_port_node_ids); + pr_info("%s: both ports active. move primary port node_ids back to target_port=%d, num_nodes = %d, nodes:\n", + __func__, move_ws_node.target_port, + move_ws_node.num_nodes); + } else if (vsi->secondary_port_migrated) { /* secondary port was in failed state */ + vsi->secondary_port_migrated = false; + /* move all secondary port nodes back to the secondary port */ + move_ws_node.target_port = + vsi->lag_ports[IRDMA_LAG_SECONDARY_IDX]; + move_ws_node.num_nodes = + irdma_move_nodes(move_ws_node.node_id, + vsi->secondary_port_node_ids); + pr_info("%s: both ports active. move secondary port node_ids back to target_port=%d, num_nodes = %d, nodes:\n", + __func__, move_ws_node.target_port, + move_ws_node.num_nodes); + + } + for (i = 0; i < move_ws_node.num_nodes; ++i) + pr_info("%d\n", move_ws_node.node_id[i]); + move_ws_node.resume_traffic = true; + if (irdma_cqp_ws_move_cmd(vsi->dev, &move_ws_node)) + ibdev_dbg(to_ibdev(vsi->dev), + "WS: CQP WS MOVE CMD failed, both ports up case\n"); + } else { /* if only one or none are active */ + if (vsi->lag_port_bitmap == IIDC_RDMA_SECONDARY_PORT) { /* if only secodary port is active */ + move_ws_node.target_port = + vsi->lag_ports[IRDMA_LAG_SECONDARY_IDX]; + vsi->secondary_port_migrated = false; + vsi->primary_port_migrated = true; + /* move all primary port nodes to secondary */ + move_ws_node.num_nodes = + irdma_move_nodes(move_ws_node.node_id, + vsi->primary_port_node_ids); + /* move all secodary port nodes back to secodary port */ + move_ws_node.num_nodes = + irdma_move_nodes(move_ws_node.node_id, + vsi->secondary_port_node_ids); + pr_info("%s: only secondary port is active. move all node_ids to target_port=%d, num_nodes = %d, nodes:\n", + __func__, move_ws_node.target_port, + move_ws_node.num_nodes); + } else { /* only primary port is active or none are active, move everything to primary port */ + move_ws_node.target_port = + vsi->lag_ports[IRDMA_LAG_PRIMARY_IDX]; + vsi->secondary_port_migrated = true; + vsi->primary_port_migrated = false; + /* move all primary port nodes back to primary port */ + move_ws_node.num_nodes = + irdma_move_nodes(move_ws_node.node_id, + vsi->primary_port_node_ids); + /* move all secondary port nodes to primary port */ + move_ws_node.num_nodes = + irdma_move_nodes(move_ws_node.node_id, + vsi->secondary_port_node_ids); + pr_info("%s: only primary port is active. move all node_ids to target_port=%d, num_nodes = %d, nodes:\n", + __func__, move_ws_node.target_port, + move_ws_node.num_nodes); + } + move_ws_node.resume_traffic = true; + for (i = 0; i < move_ws_node.num_nodes; ++i) + pr_info("%d\n", move_ws_node.node_id[i]); + + if (irdma_cqp_ws_move_cmd(vsi->dev, &move_ws_node)) + ibdev_dbg(to_ibdev(vsi->dev), + "WS: CQP WS MOVE CMD failed\n"); + } + + mutex_unlock(&vsi->dev->ws_mutex); +} + +/** + * irdma_ws_failover_cmd - Perform failover CQP command + * @vsi: vsi pointer + * @cmd: Failover Start or Complete cmd + * @failing_port: Port number that is failing + * @active_port: Port number to become active + */ +void irdma_ws_failover_cmd(struct irdma_sc_vsi *vsi, u8 cmd, u8 failing_port, + u8 active_port) +{ + struct irdma_ws_node ws_node; + + mutex_lock(&vsi->dev->ws_mutex); + if (WARN_ON_ONCE(!vsi->dev->ws_tree_root)) { + mutex_unlock(&vsi->dev->ws_mutex); + return; + } + ws_node = *vsi->dev->ws_tree_root; + + ws_node.failing_port = failing_port; + ws_node.active_port = active_port; + irdma_ws_cqp_cmd(vsi, &ws_node, cmd, NULL); + mutex_unlock(&vsi->dev->ws_mutex); +} diff --git a/drivers/intel/irdma-1.14.33/src/irdma/ws.h b/drivers/intel/irdma-1.14.33/src/irdma/ws.h new file mode 100644 index 000000000..d2f353686 --- /dev/null +++ b/drivers/intel/irdma-1.14.33/src/irdma/ws.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 or Linux-OpenIB */ +/* Copyright (c) 2015 - 2023 Intel Corporation */ +#ifndef IRDMA_WS_H +#define IRDMA_WS_H + +#include "osdep.h" + +enum irdma_ws_node_type { + WS_NODE_TYPE_PARENT, + WS_NODE_TYPE_LEAF, +}; + +enum irdma_ws_match_type { + WS_MATCH_TYPE_VSI, + WS_MATCH_TYPE_TC, +}; + +struct irdma_ws_node { + struct list_head siblings; + struct list_head child_list_head; + struct irdma_ws_node *parent; + u32 l2_sched_node_id; + u16 index; + u16 qs_handle; + u16 vsi_index; + u8 traffic_class; + u8 user_pri; + u8 rel_bw; + u8 abstraction_layer; /* used for splitting a TC */ + u8 prio_type; + u8 failing_port; + u8 active_port; + bool assign_to_active_port:1; + bool type_leaf:1; + bool enable:1; +}; + +struct irdma_sc_vsi; +int irdma_ws_add(struct irdma_sc_vsi *vsi, u8 user_pri); +void irdma_ws_remove(struct irdma_sc_vsi *vsi, u8 user_pri); +void irdma_ws_reset(struct irdma_sc_vsi *vsi); +void irdma_ws_failover_cmd(struct irdma_sc_vsi *vsi, u8 cmd, u8 failing_port, u8 active_port); +void irdma_ws_move_cmd(struct irdma_sc_vsi *vsi); + +#endif /* IRDMA_WS_H */