From a387387ef6b634b112ae094f1948b47ee65bdc20 Mon Sep 17 00:00:00 2001 From: Susan Su Date: Fri, 19 Nov 2021 17:39:48 +0800 Subject: [PATCH 1/2] Add device MCIMX6X and MCIMX7D and related i.mx drivers - This files are copied from https://github.com/zephyrproject-rtos/hal_nxp/tree/master/imx and re-organized according to current folder structure. - Device headers and device specific files goes to devices/{device} folder, common drivers are put in the drivers/xx_imx driver folder according to IP. Signed-off-by: Susan Su --- devices/MCIMX6X/MCIMX6X_M4.h | 41139 ++++++++++++++++ devices/MCIMX6X/device_imx.h | 74 + devices/MCIMX6X/drivers/adc_imx6sx.c | 519 + devices/MCIMX6X/drivers/adc_imx6sx.h | 513 + devices/MCIMX6X/drivers/ccm_analog_imx6sx.c | 192 + devices/MCIMX6X/drivers/ccm_analog_imx6sx.h | 340 + devices/MCIMX6X/drivers/ccm_imx6sx.c | 67 + devices/MCIMX6X/drivers/ccm_imx6sx.h | 785 + devices/MCIMX6X/drivers/clock_freq.c | 265 + devices/MCIMX6X/drivers/clock_freq.h | 90 + devices/MCIMX6X/drivers/rdc_defs_imx6sx.h | 210 + devices/MCIMX7D/MCIMX7D_M4.h | 44765 ++++++++++++++++++ devices/MCIMX7D/device_imx.h | 74 + devices/MCIMX7D/drivers/adc_imx7d.c | 803 + devices/MCIMX7D/drivers/adc_imx7d.h | 555 + devices/MCIMX7D/drivers/ccm_analog_imx7d.c | 270 + devices/MCIMX7D/drivers/ccm_analog_imx7d.h | 398 + devices/MCIMX7D/drivers/ccm_imx7d.c | 85 + devices/MCIMX7D/drivers/ccm_imx7d.h | 470 + devices/MCIMX7D/drivers/clock_freq.c | 267 + devices/MCIMX7D/drivers/clock_freq.h | 99 + devices/MCIMX7D/drivers/rdc_defs_imx7d.h | 222 + drivers/ecspi_imx/ecspi.c | 205 + drivers/ecspi_imx/ecspi.h | 493 + drivers/epit_imx/epit.c | 89 + drivers/epit_imx/epit.h | 326 + drivers/flexcan_imx/flexcan.c | 1073 + drivers/flexcan_imx/flexcan.h | 712 + drivers/gpio_imx/gpio_imx.c | 162 + drivers/gpio_imx/gpio_imx.h | 272 + drivers/gpt_imx/gpt.c | 91 + drivers/gpt_imx/gpt.h | 414 + drivers/i2c_imx/i2c_imx.c | 167 + drivers/i2c_imx/i2c_imx.h | 284 + drivers/lmem_imx/lmem.c | 348 + drivers/lmem_imx/lmem.h | 174 + drivers/mu_imx/mu_imx.c | 155 + drivers/mu_imx/mu_imx.h | 569 + drivers/rdc_imx/rdc.c | 89 + drivers/rdc_imx/rdc.h | 270 + drivers/rdc_sema_imx/rdc_semaphore.c | 187 + drivers/rdc_sema_imx/rdc_semaphore.h | 140 + drivers/sema4_imx/sema4.c | 199 + drivers/sema4_imx/sema4.h | 278 + drivers/uart_imx/uart_imx.c | 612 + drivers/uart_imx/uart_imx.h | 779 + drivers/wdog_imx/wdog_imx.c | 81 + drivers/wdog_imx/wdog_imx.h | 193 + 48 files changed, 100564 insertions(+) create mode 100644 devices/MCIMX6X/MCIMX6X_M4.h create mode 100644 devices/MCIMX6X/device_imx.h create mode 100644 devices/MCIMX6X/drivers/adc_imx6sx.c create mode 100644 devices/MCIMX6X/drivers/adc_imx6sx.h create mode 100644 devices/MCIMX6X/drivers/ccm_analog_imx6sx.c create mode 100644 devices/MCIMX6X/drivers/ccm_analog_imx6sx.h create mode 100644 devices/MCIMX6X/drivers/ccm_imx6sx.c create mode 100644 devices/MCIMX6X/drivers/ccm_imx6sx.h create mode 100644 devices/MCIMX6X/drivers/clock_freq.c create mode 100644 devices/MCIMX6X/drivers/clock_freq.h create mode 100644 devices/MCIMX6X/drivers/rdc_defs_imx6sx.h create mode 100644 devices/MCIMX7D/MCIMX7D_M4.h create mode 100644 devices/MCIMX7D/device_imx.h create mode 100644 devices/MCIMX7D/drivers/adc_imx7d.c create mode 100644 devices/MCIMX7D/drivers/adc_imx7d.h create mode 100644 devices/MCIMX7D/drivers/ccm_analog_imx7d.c create mode 100644 devices/MCIMX7D/drivers/ccm_analog_imx7d.h create mode 100644 devices/MCIMX7D/drivers/ccm_imx7d.c create mode 100644 devices/MCIMX7D/drivers/ccm_imx7d.h create mode 100644 devices/MCIMX7D/drivers/clock_freq.c create mode 100644 devices/MCIMX7D/drivers/clock_freq.h create mode 100644 devices/MCIMX7D/drivers/rdc_defs_imx7d.h create mode 100644 drivers/ecspi_imx/ecspi.c create mode 100644 drivers/ecspi_imx/ecspi.h create mode 100644 drivers/epit_imx/epit.c create mode 100644 drivers/epit_imx/epit.h create mode 100644 drivers/flexcan_imx/flexcan.c create mode 100644 drivers/flexcan_imx/flexcan.h create mode 100644 drivers/gpio_imx/gpio_imx.c create mode 100644 drivers/gpio_imx/gpio_imx.h create mode 100644 drivers/gpt_imx/gpt.c create mode 100644 drivers/gpt_imx/gpt.h create mode 100644 drivers/i2c_imx/i2c_imx.c create mode 100644 drivers/i2c_imx/i2c_imx.h create mode 100644 drivers/lmem_imx/lmem.c create mode 100644 drivers/lmem_imx/lmem.h create mode 100644 drivers/mu_imx/mu_imx.c create mode 100644 drivers/mu_imx/mu_imx.h create mode 100644 drivers/rdc_imx/rdc.c create mode 100644 drivers/rdc_imx/rdc.h create mode 100644 drivers/rdc_sema_imx/rdc_semaphore.c create mode 100644 drivers/rdc_sema_imx/rdc_semaphore.h create mode 100644 drivers/sema4_imx/sema4.c create mode 100644 drivers/sema4_imx/sema4.h create mode 100644 drivers/uart_imx/uart_imx.c create mode 100644 drivers/uart_imx/uart_imx.h create mode 100644 drivers/wdog_imx/wdog_imx.c create mode 100644 drivers/wdog_imx/wdog_imx.h diff --git a/devices/MCIMX6X/MCIMX6X_M4.h b/devices/MCIMX6X/MCIMX6X_M4.h new file mode 100644 index 000000000..09d5b8b92 --- /dev/null +++ b/devices/MCIMX6X/MCIMX6X_M4.h @@ -0,0 +1,41139 @@ +/* +** ################################################################### +** Processors: MCIMX6X_M4 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** GNU C Compiler - CodeSourcery Sourcery G++ +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: +** Version: rev. 1.0, 2015-07-17 +** Build: b150707 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCIMX6X_M4 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2015-07-17) +** Initial version . +** +** ################################################################### +*/ + +/*! + * @file MCIMX6X_M4.h + * @version 1.0 + * @date 2015-07-17 + * @brief CMSIS Peripheral Access Layer for MCIMX6X_M4 + * + * CMSIS Peripheral Access Layer for MCIMX6X_M4 + */ + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(MCIMX6X_M4_H_) /* Check if memory map has not been already included */ +#define MCIMX6X_M4_H_ +#define MCU_MCIMX6X_M4 + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error MCIMX6X_M4 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000u + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + Cortex_M4_IRQn = 0, /**< Cache Controller interrupt */ + DAP_IRQn = 1, /**< Debug Access Port interrupt request. */ + SDMA_IRQn = 2, /**< SDMA interrupt request from all channels. */ + Reserved0_IRQn = 3, /**< Reserved */ + SNVS_IRQn = 4, /**< PMIC power off request. */ + LCDIF1_IRQn = 5, /**< LCDIF1 Sync Interrupt */ + LCDIF2_IRQn = 6, /**< LCDIF2 Sync Interrupt */ + CSI1_IRQn = 7, /**< CMOS Sensor Interface interrupt request */ + PXP_IRQn = 8, /**< PXP interrupt */ + Reserved1_IRQn = 9, /**< Reserved */ + GPU_IRQn = 10, /**< GPU general interrupt request */ + WDOG3_IRQn = 11, /**< WDOG3 interrupt request */ + SEMA4_CP1_IRQn = 12, /**< SEMA4 CP1 interrupt request. */ + APBHDMA_IRQn = 13, /**< Logical OR of APBH DMA channels 0-3 completion and error interrupts. */ + EIM_IRQn = 14, /**< EIM interrupt request. */ + BCH_IRQn = 15, /**< BCH operation complete interrupt. */ + GPMI_IRQn = 16, /**< GPMI operation timeout error interrupt. */ + UART6_IRQn = 17, /**< UART6 interrupt request. */ + eCSPI5_IRQn = 18, /**< eCSPI5 interrupt request. */ + SNVS_CONSOLIDATED_IRQn = 19, /**< SNVS consolidated interrupt. */ + SNVS_SECURITY_IRQn = 20, /**< SNVS security interrupt. */ + CSU_IRQn = 21, /**< CSU interrupt request 1. Indicates to the processor that one or more alarm inputs were asserted. */ + USDHC1_IRQn = 22, /**< uSDHC1 (Enhanced SDHC) interrupt request */ + USDHC2_IRQn = 23, /**< uSDHC2 (Enhanced SDHC) interrupt request. */ + USDHC3_IRQn = 24, /**< uSDHC3 (Enhanced SDHC) interrupt request. */ + USDHC4_IRQn = 25, /**< uSDHC4 (Enhanced SDHC) interrupt request. */ + UART1_IRQn = 26, /**< UART1 interrupt request. */ + UART2_IRQn = 27, /**< UART2 interrupt request. */ + UART3_IRQn = 28, /**< UART3 interrupt request. */ + UART4_IRQn = 29, /**< UART4 interrupt request. */ + UART5_IRQn = 30, /**< UART5 interrupt request. */ + eCSPI1_IRQn = 31, /**< eCSPI1 interrupt request. */ + eCSPI2_IRQn = 32, /**< eCSPI2 interrupt request. */ + eCSPI3_IRQn = 33, /**< eCSPI3 interrupt request. */ + eCSPI4_IRQn = 34, /**< eCSPI4 interrupt request. */ + I2C4_IRQn = 35, /**< I2C4 interrupt request */ + I2C1_IRQn = 36, /**< I2C1 interrupt request. */ + I2C2_IRQn = 37, /**< I2C2 interrupt request. */ + I2C3_IRQn = 38, /**< I2C3 interrupt request. */ + RDC_IRQn = 39, /**< RDC interrupt request. */ + USB_IRQn = 40, /**< USB HISC Host interrupt request. */ + CSI2_IRQn = 41, /**< CSI interrupt */ + USB_OTG2_IRQn = 42, /**< USB OTG 2 interrupt request. */ + USB_OTG1_IRQn = 43, /**< USB OTG 1 interrupt request. */ + USB_PHY1_IRQn = 44, /**< UTMI0 interrupt request. */ + USB_PHY2_IRQn = 45, /**< UTMI1 interrupt request. */ + SSI1_IRQn = 46, /**< SSI1 interrupt request. */ + SSI2_IRQn = 47, /**< SSI2 interrupt request. */ + SSI3_IRQn = 48, /**< SSI3 interrupt request. */ + Temperature_Monitor_IRQn = 49, /**< Temperature Sensor (temp. greater than threshold) interrupt request. */ + ASRC_IRQn = 50, /**< ASRC interrupt request. */ + ESAI_IRQn = 51, /**< ESAI interrupt request */ + SPDIF_IRQn = 52, /**< SPDIF Rx/Tx interrupt. */ + MLB_ERROR_IRQn = 53, /**< MLB error interrupt request. */ + PMU1_IRQn = 54, /**< Brown-out event on either the 1.1, 2.5 or 3.0 regulators. */ + GPT_IRQn = 55, /**< Logical OR of GPT rollover interrupt line, input capture 1 & 2 lines, output compare 1, 2 & 3 interrupt lines. */ + EPIT1_IRQn = 56, /**< EPIT1 output compare interrupt. */ + EPIT2_IRQn = 57, /**< EPIT2 output compare interrupt. */ + GPIO1_INT7_IRQn = 58, /**< INT7 interrupt request. */ + GPIO1_INT6_IRQn = 59, /**< INT6 interrupt request. */ + GPIO1_INT5_IRQn = 60, /**< INT5 interrupt request. */ + GPIO1_INT4_IRQn = 61, /**< INT4 interrupt request. */ + GPIO1_INT3_IRQn = 62, /**< INT3 interrupt request. */ + GPIO1_INT2_IRQn = 63, /**< INT2 interrupt request. */ + GPIO1_INT1_IRQn = 64, /**< INT1 interrupt request. */ + GPIO1_INT0_IRQn = 65, /**< INT0 interrupt request. */ + GPIO1_INT15_0_IRQn = 66, /**< Combined interrupt indication for GPIO1 signals 0 - 15. */ + GPIO1_INT31_16_IRQn = 67, /**< Combined interrupt indication for GPIO1 signals 16 - 31. */ + GPIO2_INT15_0_IRQn = 68, /**< Combined interrupt indication for GPIO2 signals 0 - 15. */ + GPIO2_INT31_16_IRQn = 69, /**< Combined interrupt indication for GPIO2 signals 16 - 31. */ + GPIO3_INT15_0_IRQn = 70, /**< Combined interrupt indication for GPIO3 signals 0 - 15. */ + GPIO3_INT31_16_IRQn = 71, /**< Combined interrupt indication for GPIO3 signals 16 - 31. */ + GPIO4_INT15_0_IRQn = 72, /**< Combined interrupt indication for GPIO4 signals 0 - 15. */ + GPIO4_INT31_16_IRQn = 73, /**< Combined interrupt indication for GPIO4 signals 16 - 31. */ + GPIO5_INT15_0_IRQn = 74, /**< Combined interrupt indication for GPIO5 signals 0 - 15. */ + GPIO5_INT31_16_IRQn = 75, /**< Combined interrupt indication for GPIO5 signals 16 - 31. */ + GPIO6_INT15_0_IRQn = 76, /**< Combined interrupt indication for GPIO6 signals 0 - 15. */ + GPIO6_INT31_16_IRQn = 77, /**< Combined interrupt indication for GPIO6 signals 16 - 31. */ + GPIO7_INT15_0_IRQn = 78, /**< Combined interrupt indication for GPIO7 signals 0 - 15. */ + GPIO7_INT31_16_IRQn = 79, /**< Combined interrupt indication for GPIO7 signals 16 - 31. */ + WDOG1_IRQn = 80, /**< WDOG1 timer reset interrupt request. */ + WDOG2_IRQn = 81, /**< WDOG2 timer reset interrupt request. */ + KPP_IRQn = 82, /**< Key Pad interrupt request */ + PWM1_PWM5_IRQn = 83, /**< Cumulative interrupt line for PWM1/PWM5. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ + PWM2_PWM6_IRQn = 84, /**< Cumulative interrupt line for PWM2/PWM6. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ + PWM3_PWM7_IRQn = 85, /**< Cumulative interrupt line for PWM3/PWM7. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ + PWM4_PWM8_IRQn = 86, /**< Cumulative interrupt line for PWM4/PWM8. Logical OR of rollover, compare, and FIFO waterlevel crossing interrupts. */ + CCM1_IRQn = 87, /**< CCM interrupt request 1. */ + CCM2_IRQn = 88, /**< CCM interrupt request 2. */ + GPC_IRQn = 89, /**< GPC interrupt request 1. */ + MU_A9_IRQn = 90, /**< Message unit interrupt to A9 core */ + SRC_IRQn = 91, /**< SRC interrupt request. */ + CPU_L2I_IRQn = 92, /**< L2 interrupt request. */ + CPU_PCEI_IRQn = 93, /**< Parity Check error interrupt request. */ + CPU_PUI_IRQn = 94, /**< Performance Unit interrupt. */ + CPU_CTI_IRQn = 95, /**< CTI trigger outputs interrupt. */ + SRC_CPU_WDOG_IRQn = 96, /**< Combined CPU wdog interrupts (4x) out of SRC. */ + SAI1_IRQn = 97, /**< SAI1 interrupt request. */ + SAI2_IRQn = 98, /**< SAI2 interrupt request. */ + MU_M4_IRQn = 99, /**< Message unit Interrupt to M4 core */ + ADC1_IRQn = 100, /**< ADC1 interrupt request. */ + ADC2_IRQn = 101, /**< ADC2 interrupt request. */ + ENET2_IRQn = 102, /**< ENET2 Interrupt Request. */ + ENET2_TI_IRQn = 103, /**< ENET2 1588 Timer interrupt [synchronous] request. */ + SJC_IRQn = 104, /**< SJC interrupt from General Purpose register. */ + CAAM1_IRQn = 105, /**< CAAM job ring 0 interrupt. */ + CAAM2_IRQn = 106, /**< CAAM job ring 1 interrupt. */ + QSPI1_IRQn = 107, /**< QSPI1 interrupt request. */ + TZASC_IRQn = 108, /**< TZASC (PL380) interrupt request. */ + QSPI2_IRQn = 109, /**< QSPI2 interrupt request. */ + FLEXCAN1_IRQn = 110, /**< FLEXCAN1 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */ + FLEXCAN2_IRQn = 111, /**< FLEXCAN2 combined interrupt. Logical OR of ini_int_busoff, ini_int_error, ipi_int_mbor, ipi_int_rxwarning, ipi_int_txwarning and ipi_int_wakein. */ + Reserved2_IRQn = 112, /**< Reserved */ + Reserved3_IRQn = 113, /**< Reserved */ + Reserved4_IRQn = 114, /**< Reserved */ + Reserved5_IRQn = 115, /**< Reserved */ + SEMA4_CP0_IRQn = 116, /**< SEMA4 CP0 interrupt request */ + MLB_IRCI_IRQn = 117, /**< Interrupt request for channels [31:0]. Interrupt request for channels [63:32] available on IRQ #149 if SMX bit is set in MLB150 AHB control register (ACTL), otherwise interrupt for channels [63:32] interrupt is available on IRQ #158. */ + ENET1_IRQn = 118, /**< ENET1 Interrupt Request. */ + ENET1_TI_IRQn = 119, /**< ENET1 1588 Timer interrupt [synchronous] request. */ + PCIe1_IRQn = 120, /**< PCIe interrupt request 1. */ + PCIe2_IRQn = 121, /**< PCIe interrupt request 2. */ + PCIe3_IRQn = 122, /**< PCIe interrupt request 3. */ + PCIe4_IRQn = 123, /**< PCIe interrupt request 4. */ + DCIC1_IRQn = 124, /**< DCIC1 interrupt request. */ + DCIC2_IRQn = 125, /**< DCIC2 interrupt request. */ + MLB_LOCI_IRQn = 126, /**< Logical OR of channel[63:32] interrupt requests. */ + PMU2_IRQn = 127, /**< Brown out of core, gpu, and chip digital regulators occurred. */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t HC0; /**< Control register for hardware triggers, offset: 0x0 */ + __IO uint32_t HC1; /**< Control register for hardware triggers, offset: 0x4 */ + __I uint32_t HS; /**< Status register for HW triggers, offset: 0x8 */ + __IO uint32_t R0; /**< Data result register for HW triggers, offset: 0xC */ + __IO uint32_t R1; /**< Data result register for HW triggers, offset: 0x10 */ + __IO uint32_t CFG; /**< Configuration register, offset: 0x14 */ + __IO uint32_t GC; /**< General control register, offset: 0x18 */ + __IO uint32_t GS; /**< General status register, offset: 0x1C */ + __IO uint32_t CV; /**< Compare value register, offset: 0x20 */ + __IO uint32_t OFS; /**< Offset correction value register, offset: 0x24 */ + __IO uint32_t CAL; /**< Calibration value register, offset: 0x28 */ +} ADC_Type, *ADC_MemMapPtr; + +/* ---------------------------------------------------------------------------- + -- ADC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros + * @{ + */ + +/* ADC - Register accessors */ +#define ADC_HC0_REG(base) ((base)->HC0) +#define ADC_HC1_REG(base) ((base)->HC1) +#define ADC_HS_REG(base) ((base)->HS) +#define ADC_R0_REG(base) ((base)->R0) +#define ADC_R1_REG(base) ((base)->R1) +#define ADC_CFG_REG(base) ((base)->CFG) +#define ADC_GC_REG(base) ((base)->GC) +#define ADC_GS_REG(base) ((base)->GS) +#define ADC_CV_REG(base) ((base)->CV) +#define ADC_OFS_REG(base) ((base)->OFS) +#define ADC_CAL_REG(base) ((base)->CAL) + +/*! + * @} + */ /* end of group ADC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* HC0 Bit Fields */ +#define ADC_HC0_ADCH_MASK 0x1Fu +#define ADC_HC0_ADCH_SHIFT 0 +#define ADC_HC0_ADCH(x) (((uint32_t)(((uint32_t)(x))<BLOCK_ID) +#define AFE_PDBUF_REG(base) ((base)->PDBUF) +#define AFE_SWRST_REG(base) ((base)->SWRST) +#define AFE_BGREG_REG(base) ((base)->BGREG) +#define AFE_ACCESSAR_ID_REG(base) ((base)->ACCESSAR_ID) +#define AFE_PDADC_REG(base) ((base)->PDADC) +#define AFE_PDSARH_REG(base) ((base)->PDSARH) +#define AFE_PDSARL_REG(base) ((base)->PDSARL) +#define AFE_PDADCRFH_REG(base) ((base)->PDADCRFH) +#define AFE_PDADCRFL_REG(base) ((base)->PDADCRFL) +#define AFE_ADCGN_REG(base) ((base)->ADCGN) +#define AFE_REFTRIML_REG(base) ((base)->REFTRIML) +#define AFE_REFTRIMH_REG(base) ((base)->REFTRIMH) +#define AFE_DACAMP_REG(base) ((base)->DACAMP) +#define AFE_CLMPDAT_REG(base) ((base)->CLMPDAT) +#define AFE_CLMPAMP_REG(base) ((base)->CLMPAMP) +#define AFE_CLAMP_REG(base) ((base)->CLAMP) +#define AFE_INPBUF_REG(base) ((base)->INPBUF) +#define AFE_INPFLT_REG(base) ((base)->INPFLT) +#define AFE_ADCDGN_REG(base) ((base)->ADCDGN) +#define AFE_OFFDRV_REG(base) ((base)->OFFDRV) +#define AFE_INPCONFIG_REG(base) ((base)->INPCONFIG) +#define AFE_PROGDELAY_REG(base) ((base)->PROGDELAY) +#define AFE_ADCOMT_REG(base) ((base)->ADCOMT) +#define AFE_ALGDELAY_REG(base) ((base)->ALGDELAY) +#define AFE_ACC_ID_REG(base) ((base)->ACC_ID) +#define AFE_ACCSTA_REG(base) ((base)->ACCSTA) +#define AFE_ACCNOSLI_REG(base) ((base)->ACCNOSLI) +#define AFE_ACCCALCON_REG(base) ((base)->ACCCALCON) +#define AFE_BWEWRICTRL_REG(base) ((base)->BWEWRICTRL) +#define AFE_SELSLI_REG(base) ((base)->SELSLI) +#define AFE_SELBYT_REG(base) ((base)->SELBYT) +#define AFE_REDVAL_REG(base) ((base)->REDVAL) +#define AFE_WRIBYT_REG(base) ((base)->WRIBYT) + +/*! + * @} + */ /* end of group AFE_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- AFE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AFE_Register_Masks AFE Register Masks + * @{ + */ + +/* BLOCK_ID Bit Fields */ +#define AFE_BLOCK_ID_BLOCK_ID_MASK 0xFFu +#define AFE_BLOCK_ID_BLOCK_ID_SHIFT 0 +#define AFE_BLOCK_ID_BLOCK_ID(x) (((uint32_t)(((uint32_t)(x))<ASRCTR) +#define ASRC_ASRIER_REG(base) ((base)->ASRIER) +#define ASRC_ASRCNCR_REG(base) ((base)->ASRCNCR) +#define ASRC_ASRCFG_REG(base) ((base)->ASRCFG) +#define ASRC_ASRCSR_REG(base) ((base)->ASRCSR) +#define ASRC_ASRCDR1_REG(base) ((base)->ASRCDR1) +#define ASRC_ASRCDR2_REG(base) ((base)->ASRCDR2) +#define ASRC_ASRSTR_REG(base) ((base)->ASRSTR) +#define ASRC_ASRPMn_REG(base,index) ((base)->ASRPMn[index]) +#define ASRC_ASRTFR1_REG(base) ((base)->ASRTFR1) +#define ASRC_ASRCCR_REG(base) ((base)->ASRCCR) +#define ASRC_ASRDI_REG(base,index) ((base)->ASRD[index].ASRDI) +#define ASRC_ASRDO_REG(base,index) ((base)->ASRD[index].ASRDO) +#define ASRC_ASRIDRHA_REG(base) ((base)->ASRIDRHA) +#define ASRC_ASRIDRLA_REG(base) ((base)->ASRIDRLA) +#define ASRC_ASRIDRHB_REG(base) ((base)->ASRIDRHB) +#define ASRC_ASRIDRLB_REG(base) ((base)->ASRIDRLB) +#define ASRC_ASRIDRHC_REG(base) ((base)->ASRIDRHC) +#define ASRC_ASRIDRLC_REG(base) ((base)->ASRIDRLC) +#define ASRC_ASR76K_REG(base) ((base)->ASR76K) +#define ASRC_ASR56K_REG(base) ((base)->ASR56K) +#define ASRC_ASRMCRA_REG(base) ((base)->ASRMCRA) +#define ASRC_ASRFSTA_REG(base) ((base)->ASRFSTA) +#define ASRC_ASRMCRB_REG(base) ((base)->ASRMCRB) +#define ASRC_ASRFSTB_REG(base) ((base)->ASRFSTB) +#define ASRC_ASRMCRC_REG(base) ((base)->ASRMCRC) +#define ASRC_ASRFSTC_REG(base) ((base)->ASRFSTC) +#define ASRC_ASRMCR1_REG(base,index) ((base)->ASRMCR1[index]) + +/*! + * @} + */ /* end of group ASRC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ASRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ASRC_Register_Masks ASRC Register Masks + * @{ + */ + +/* ASRCTR Bit Fields */ +#define ASRC_ASRCTR_ASRCEN_MASK 0x1u +#define ASRC_ASRCTR_ASRCEN_SHIFT 0 +#define ASRC_ASRCTR_ASREA_MASK 0x2u +#define ASRC_ASRCTR_ASREA_SHIFT 1 +#define ASRC_ASRCTR_ASREB_MASK 0x4u +#define ASRC_ASRCTR_ASREB_SHIFT 2 +#define ASRC_ASRCTR_ASREC_MASK 0x8u +#define ASRC_ASRCTR_ASREC_SHIFT 3 +#define ASRC_ASRCTR_SRST_MASK 0x10u +#define ASRC_ASRCTR_SRST_SHIFT 4 +#define ASRC_ASRCTR_IDRA_MASK 0x2000u +#define ASRC_ASRCTR_IDRA_SHIFT 13 +#define ASRC_ASRCTR_USRA_MASK 0x4000u +#define ASRC_ASRCTR_USRA_SHIFT 14 +#define ASRC_ASRCTR_IDRB_MASK 0x8000u +#define ASRC_ASRCTR_IDRB_SHIFT 15 +#define ASRC_ASRCTR_USRB_MASK 0x10000u +#define ASRC_ASRCTR_USRB_SHIFT 16 +#define ASRC_ASRCTR_IDRC_MASK 0x20000u +#define ASRC_ASRCTR_IDRC_SHIFT 17 +#define ASRC_ASRCTR_USRC_MASK 0x40000u +#define ASRC_ASRCTR_USRC_SHIFT 18 +#define ASRC_ASRCTR_ATSA_MASK 0x100000u +#define ASRC_ASRCTR_ATSA_SHIFT 20 +#define ASRC_ASRCTR_ATSB_MASK 0x200000u +#define ASRC_ASRCTR_ATSB_SHIFT 21 +#define ASRC_ASRCTR_ATSC_MASK 0x400000u +#define ASRC_ASRCTR_ATSC_SHIFT 22 +/* ASRIER Bit Fields */ +#define ASRC_ASRIER_ADIEA_MASK 0x1u +#define ASRC_ASRIER_ADIEA_SHIFT 0 +#define ASRC_ASRIER_ADIEB_MASK 0x2u +#define ASRC_ASRIER_ADIEB_SHIFT 1 +#define ASRC_ASRIER_ADIEC_MASK 0x4u +#define ASRC_ASRIER_ADIEC_SHIFT 2 +#define ASRC_ASRIER_ADOEA_MASK 0x8u +#define ASRC_ASRIER_ADOEA_SHIFT 3 +#define ASRC_ASRIER_ADOEB_MASK 0x10u +#define ASRC_ASRIER_ADOEB_SHIFT 4 +#define ASRC_ASRIER_ADOEC_MASK 0x20u +#define ASRC_ASRIER_ADOEC_SHIFT 5 +#define ASRC_ASRIER_AOLIE_MASK 0x40u +#define ASRC_ASRIER_AOLIE_SHIFT 6 +#define ASRC_ASRIER_AFPWE_MASK 0x80u +#define ASRC_ASRIER_AFPWE_SHIFT 7 +/* ASRCNCR Bit Fields */ +#define ASRC_ASRCNCR_ANCA_MASK 0xFu +#define ASRC_ASRCNCR_ANCA_SHIFT 0 +#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x))<PTCR1) +#define AUDMUX_PDCR1_REG(base) ((base)->PDCR1) +#define AUDMUX_PTCR2_REG(base) ((base)->PTCR2) +#define AUDMUX_PDCR2_REG(base) ((base)->PDCR2) +#define AUDMUX_PTCR3_REG(base) ((base)->PTCR3) +#define AUDMUX_PDCR3_REG(base) ((base)->PDCR3) +#define AUDMUX_PTCR4_REG(base) ((base)->PTCR4) +#define AUDMUX_PDCR4_REG(base) ((base)->PDCR4) +#define AUDMUX_PTCR5_REG(base) ((base)->PTCR5) +#define AUDMUX_PDCR5_REG(base) ((base)->PDCR5) +#define AUDMUX_PTCR6_REG(base) ((base)->PTCR6) +#define AUDMUX_PDCR6_REG(base) ((base)->PDCR6) +#define AUDMUX_PTCR7_REG(base) ((base)->PTCR7) +#define AUDMUX_PDCR7_REG(base) ((base)->PDCR7) + +/*! + * @} + */ /* end of group AUDMUX_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- AUDMUX Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup AUDMUX_Register_Masks AUDMUX Register Masks + * @{ + */ + +/* PTCR1 Bit Fields */ +#define AUDMUX_PTCR1_SYN_MASK 0x800u +#define AUDMUX_PTCR1_SYN_SHIFT 11 +#define AUDMUX_PTCR1_RCSEL_MASK 0xF000u +#define AUDMUX_PTCR1_RCSEL_SHIFT 12 +#define AUDMUX_PTCR1_RCSEL(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define BCH_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define BCH_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define BCH_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define BCH_STATUS0_REG(base) ((base)->STATUS0) +#define BCH_STATUS0_SET_REG(base) ((base)->STATUS0_SET) +#define BCH_STATUS0_CLR_REG(base) ((base)->STATUS0_CLR) +#define BCH_STATUS0_TOG_REG(base) ((base)->STATUS0_TOG) +#define BCH_MODE_REG(base) ((base)->MODE) +#define BCH_MODE_SET_REG(base) ((base)->MODE_SET) +#define BCH_MODE_CLR_REG(base) ((base)->MODE_CLR) +#define BCH_MODE_TOG_REG(base) ((base)->MODE_TOG) +#define BCH_ENCODEPTR_REG(base) ((base)->ENCODEPTR) +#define BCH_ENCODEPTR_SET_REG(base) ((base)->ENCODEPTR_SET) +#define BCH_ENCODEPTR_CLR_REG(base) ((base)->ENCODEPTR_CLR) +#define BCH_ENCODEPTR_TOG_REG(base) ((base)->ENCODEPTR_TOG) +#define BCH_DATAPTR_REG(base) ((base)->DATAPTR) +#define BCH_DATAPTR_SET_REG(base) ((base)->DATAPTR_SET) +#define BCH_DATAPTR_CLR_REG(base) ((base)->DATAPTR_CLR) +#define BCH_DATAPTR_TOG_REG(base) ((base)->DATAPTR_TOG) +#define BCH_METAPTR_REG(base) ((base)->METAPTR) +#define BCH_METAPTR_SET_REG(base) ((base)->METAPTR_SET) +#define BCH_METAPTR_CLR_REG(base) ((base)->METAPTR_CLR) +#define BCH_METAPTR_TOG_REG(base) ((base)->METAPTR_TOG) +#define BCH_LAYOUTSELECT_REG(base) ((base)->LAYOUTSELECT) +#define BCH_LAYOUTSELECT_SET_REG(base) ((base)->LAYOUTSELECT_SET) +#define BCH_LAYOUTSELECT_CLR_REG(base) ((base)->LAYOUTSELECT_CLR) +#define BCH_LAYOUTSELECT_TOG_REG(base) ((base)->LAYOUTSELECT_TOG) +#define BCH_FLASH0LAYOUT0_REG(base) ((base)->FLASH0LAYOUT0) +#define BCH_FLASH0LAYOUT0_SET_REG(base) ((base)->FLASH0LAYOUT0_SET) +#define BCH_FLASH0LAYOUT0_CLR_REG(base) ((base)->FLASH0LAYOUT0_CLR) +#define BCH_FLASH0LAYOUT0_TOG_REG(base) ((base)->FLASH0LAYOUT0_TOG) +#define BCH_FLASH0LAYOUT1_REG(base) ((base)->FLASH0LAYOUT1) +#define BCH_FLASH0LAYOUT1_SET_REG(base) ((base)->FLASH0LAYOUT1_SET) +#define BCH_FLASH0LAYOUT1_CLR_REG(base) ((base)->FLASH0LAYOUT1_CLR) +#define BCH_FLASH0LAYOUT1_TOG_REG(base) ((base)->FLASH0LAYOUT1_TOG) +#define BCH_FLASH1LAYOUT0_REG(base) ((base)->FLASH1LAYOUT0) +#define BCH_FLASH1LAYOUT0_SET_REG(base) ((base)->FLASH1LAYOUT0_SET) +#define BCH_FLASH1LAYOUT0_CLR_REG(base) ((base)->FLASH1LAYOUT0_CLR) +#define BCH_FLASH1LAYOUT0_TOG_REG(base) ((base)->FLASH1LAYOUT0_TOG) +#define BCH_FLASH1LAYOUT1_REG(base) ((base)->FLASH1LAYOUT1) +#define BCH_FLASH1LAYOUT1_SET_REG(base) ((base)->FLASH1LAYOUT1_SET) +#define BCH_FLASH1LAYOUT1_CLR_REG(base) ((base)->FLASH1LAYOUT1_CLR) +#define BCH_FLASH1LAYOUT1_TOG_REG(base) ((base)->FLASH1LAYOUT1_TOG) +#define BCH_FLASH2LAYOUT0_REG(base) ((base)->FLASH2LAYOUT0) +#define BCH_FLASH2LAYOUT0_SET_REG(base) ((base)->FLASH2LAYOUT0_SET) +#define BCH_FLASH2LAYOUT0_CLR_REG(base) ((base)->FLASH2LAYOUT0_CLR) +#define BCH_FLASH2LAYOUT0_TOG_REG(base) ((base)->FLASH2LAYOUT0_TOG) +#define BCH_FLASH2LAYOUT1_REG(base) ((base)->FLASH2LAYOUT1) +#define BCH_FLASH2LAYOUT1_SET_REG(base) ((base)->FLASH2LAYOUT1_SET) +#define BCH_FLASH2LAYOUT1_CLR_REG(base) ((base)->FLASH2LAYOUT1_CLR) +#define BCH_FLASH2LAYOUT1_TOG_REG(base) ((base)->FLASH2LAYOUT1_TOG) +#define BCH_FLASH3LAYOUT0_REG(base) ((base)->FLASH3LAYOUT0) +#define BCH_FLASH3LAYOUT0_SET_REG(base) ((base)->FLASH3LAYOUT0_SET) +#define BCH_FLASH3LAYOUT0_CLR_REG(base) ((base)->FLASH3LAYOUT0_CLR) +#define BCH_FLASH3LAYOUT0_TOG_REG(base) ((base)->FLASH3LAYOUT0_TOG) +#define BCH_FLASH3LAYOUT1_REG(base) ((base)->FLASH3LAYOUT1) +#define BCH_FLASH3LAYOUT1_SET_REG(base) ((base)->FLASH3LAYOUT1_SET) +#define BCH_FLASH3LAYOUT1_CLR_REG(base) ((base)->FLASH3LAYOUT1_CLR) +#define BCH_FLASH3LAYOUT1_TOG_REG(base) ((base)->FLASH3LAYOUT1_TOG) +#define BCH_DEBUG0_REG(base) ((base)->DEBUG0) +#define BCH_DEBUG0_SET_REG(base) ((base)->DEBUG0_SET) +#define BCH_DEBUG0_CLR_REG(base) ((base)->DEBUG0_CLR) +#define BCH_DEBUG0_TOG_REG(base) ((base)->DEBUG0_TOG) +#define BCH_DBGKESREAD_REG(base) ((base)->DBGKESREAD) +#define BCH_DBGKESREAD_SET_REG(base) ((base)->DBGKESREAD_SET) +#define BCH_DBGKESREAD_CLR_REG(base) ((base)->DBGKESREAD_CLR) +#define BCH_DBGKESREAD_TOG_REG(base) ((base)->DBGKESREAD_TOG) +#define BCH_DBGCSFEREAD_REG(base) ((base)->DBGCSFEREAD) +#define BCH_DBGCSFEREAD_SET_REG(base) ((base)->DBGCSFEREAD_SET) +#define BCH_DBGCSFEREAD_CLR_REG(base) ((base)->DBGCSFEREAD_CLR) +#define BCH_DBGCSFEREAD_TOG_REG(base) ((base)->DBGCSFEREAD_TOG) +#define BCH_DBGSYNDGENREAD_REG(base) ((base)->DBGSYNDGENREAD) +#define BCH_DBGSYNDGENREAD_SET_REG(base) ((base)->DBGSYNDGENREAD_SET) +#define BCH_DBGSYNDGENREAD_CLR_REG(base) ((base)->DBGSYNDGENREAD_CLR) +#define BCH_DBGSYNDGENREAD_TOG_REG(base) ((base)->DBGSYNDGENREAD_TOG) +#define BCH_DBGAHBMREAD_REG(base) ((base)->DBGAHBMREAD) +#define BCH_DBGAHBMREAD_SET_REG(base) ((base)->DBGAHBMREAD_SET) +#define BCH_DBGAHBMREAD_CLR_REG(base) ((base)->DBGAHBMREAD_CLR) +#define BCH_DBGAHBMREAD_TOG_REG(base) ((base)->DBGAHBMREAD_TOG) +#define BCH_BLOCKNAME_REG(base) ((base)->BLOCKNAME) +#define BCH_BLOCKNAME_SET_REG(base) ((base)->BLOCKNAME_SET) +#define BCH_BLOCKNAME_CLR_REG(base) ((base)->BLOCKNAME_CLR) +#define BCH_BLOCKNAME_TOG_REG(base) ((base)->BLOCKNAME_TOG) +#define BCH_VERSION_REG(base) ((base)->VERSION) +#define BCH_VERSION_SET_REG(base) ((base)->VERSION_SET) +#define BCH_VERSION_CLR_REG(base) ((base)->VERSION_CLR) +#define BCH_VERSION_TOG_REG(base) ((base)->VERSION_TOG) +#define BCH_DEBUG1_REG(base) ((base)->DEBUG1) +#define BCH_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) +#define BCH_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) +#define BCH_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) + +/*! + * @} + */ /* end of group BCH_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define BCH_CTRL_COMPLETE_IRQ_MASK 0x1u +#define BCH_CTRL_COMPLETE_IRQ_SHIFT 0 +#define BCH_CTRL_RSVD0_MASK 0x2u +#define BCH_CTRL_RSVD0_SHIFT 1 +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK 0x4u +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT 2 +#define BCH_CTRL_BM_ERROR_IRQ_MASK 0x8u +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT 3 +#define BCH_CTRL_RSVD1_MASK 0xF0u +#define BCH_CTRL_RSVD1_SHIFT 4 +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define CAN_CTRL1_REG(base) ((base)->CTRL1) +#define CAN_TIMER_REG(base) ((base)->TIMER) +#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) +#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) +#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) +#define CAN_ECR_REG(base) ((base)->ECR) +#define CAN_ESR1_REG(base) ((base)->ESR1) +#define CAN_IMASK2_REG(base) ((base)->IMASK2) +#define CAN_IMASK1_REG(base) ((base)->IMASK1) +#define CAN_IFLAG2_REG(base) ((base)->IFLAG2) +#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) +#define CAN_CTRL2_REG(base) ((base)->CTRL2) +#define CAN_ESR2_REG(base) ((base)->ESR2) +#define CAN_CRCR_REG(base) ((base)->CRCR) +#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) +#define CAN_RXFIR_REG(base) ((base)->RXFIR) +#define CAN_CS_REG(base,index) ((base)->MB[index].CS) +#define CAN_CS_COUNT 64 +#define CAN_ID_REG(base,index) ((base)->MB[index].ID) +#define CAN_ID_COUNT 64 +#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) +#define CAN_WORD0_COUNT 64 +#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) +#define CAN_WORD1_COUNT 64 +#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) +#define CAN_RXIMR_COUNT 64 +#define CAN_GFWR_REG(base) ((base)->GFWR) + +/*! + * @} + */ /* end of group CAN_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define CAN_MCR_MAXMB_MASK 0x7Fu +#define CAN_MCR_MAXMB_SHIFT 0 +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<CCR) +#define CCM_CCDR_REG(base) ((base)->CCDR) +#define CCM_CSR_REG(base) ((base)->CSR) +#define CCM_CCSR_REG(base) ((base)->CCSR) +#define CCM_CACRR_REG(base) ((base)->CACRR) +#define CCM_CBCDR_REG(base) ((base)->CBCDR) +#define CCM_CBCMR_REG(base) ((base)->CBCMR) +#define CCM_CSCMR1_REG(base) ((base)->CSCMR1) +#define CCM_CSCMR2_REG(base) ((base)->CSCMR2) +#define CCM_CSCDR1_REG(base) ((base)->CSCDR1) +#define CCM_CS1CDR_REG(base) ((base)->CS1CDR) +#define CCM_CS2CDR_REG(base) ((base)->CS2CDR) +#define CCM_CDCDR_REG(base) ((base)->CDCDR) +#define CCM_CHSCCDR_REG(base) ((base)->CHSCCDR) +#define CCM_CSCDR2_REG(base) ((base)->CSCDR2) +#define CCM_CSCDR3_REG(base) ((base)->CSCDR3) +#define CCM_CWDR_REG(base) ((base)->CWDR) +#define CCM_CDHIPR_REG(base) ((base)->CDHIPR) +#define CCM_CLPCR_REG(base) ((base)->CLPCR) +#define CCM_CISR_REG(base) ((base)->CISR) +#define CCM_CIMR_REG(base) ((base)->CIMR) +#define CCM_CCOSR_REG(base) ((base)->CCOSR) +#define CCM_CGPR_REG(base) ((base)->CGPR) +#define CCM_CCGR0_REG(base) ((base)->CCGR0) +#define CCM_CCGR1_REG(base) ((base)->CCGR1) +#define CCM_CCGR2_REG(base) ((base)->CCGR2) +#define CCM_CCGR3_REG(base) ((base)->CCGR3) +#define CCM_CCGR4_REG(base) ((base)->CCGR4) +#define CCM_CCGR5_REG(base) ((base)->CCGR5) +#define CCM_CCGR6_REG(base) ((base)->CCGR6) +#define CCM_CMEOR_REG(base) ((base)->CMEOR) + +/*! + * @} + */ /* end of group CCM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/* CCR Bit Fields */ +#define CCM_CCR_OSCNT_MASK 0x7Fu +#define CCM_CCR_OSCNT_SHIFT 0 +#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x))<PLL_ARM) +#define CCM_ANALOG_PLL_ARM_SET_REG(base) ((base)->PLL_ARM_SET) +#define CCM_ANALOG_PLL_ARM_CLR_REG(base) ((base)->PLL_ARM_CLR) +#define CCM_ANALOG_PLL_ARM_TOG_REG(base) ((base)->PLL_ARM_TOG) +#define CCM_ANALOG_PLL_USB1_REG(base) ((base)->PLL_USB1) +#define CCM_ANALOG_PLL_USB1_SET_REG(base) ((base)->PLL_USB1_SET) +#define CCM_ANALOG_PLL_USB1_CLR_REG(base) ((base)->PLL_USB1_CLR) +#define CCM_ANALOG_PLL_USB1_TOG_REG(base) ((base)->PLL_USB1_TOG) +#define CCM_ANALOG_PLL_USB2_REG(base) ((base)->PLL_USB2) +#define CCM_ANALOG_PLL_USB2_SET_REG(base) ((base)->PLL_USB2_SET) +#define CCM_ANALOG_PLL_USB2_CLR_REG(base) ((base)->PLL_USB2_CLR) +#define CCM_ANALOG_PLL_USB2_TOG_REG(base) ((base)->PLL_USB2_TOG) +#define CCM_ANALOG_PLL_SYS_REG(base) ((base)->PLL_SYS) +#define CCM_ANALOG_PLL_SYS_SET_REG(base) ((base)->PLL_SYS_SET) +#define CCM_ANALOG_PLL_SYS_CLR_REG(base) ((base)->PLL_SYS_CLR) +#define CCM_ANALOG_PLL_SYS_TOG_REG(base) ((base)->PLL_SYS_TOG) +#define CCM_ANALOG_PLL_SYS_SS_REG(base) ((base)->PLL_SYS_SS) +#define CCM_ANALOG_PLL_AUDIO_REG(base) ((base)->PLL_AUDIO) +#define CCM_ANALOG_PLL_AUDIO_SET_REG(base) ((base)->PLL_AUDIO_SET) +#define CCM_ANALOG_PLL_AUDIO_CLR_REG(base) ((base)->PLL_AUDIO_CLR) +#define CCM_ANALOG_PLL_AUDIO_TOG_REG(base) ((base)->PLL_AUDIO_TOG) +#define CCM_ANALOG_PLL_AUDIO_NUM_REG(base) ((base)->PLL_AUDIO_NUM) +#define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) ((base)->PLL_AUDIO_DENOM) +#define CCM_ANALOG_PLL_VIDEO_REG(base) ((base)->PLL_VIDEO) +#define CCM_ANALOG_PLL_VIDEO_SET_REG(base) ((base)->PLL_VIDEO_SET) +#define CCM_ANALOG_PLL_VIDEO_CLR_REG(base) ((base)->PLL_VIDEO_CLR) +#define CCM_ANALOG_PLL_VIDEO_TOG_REG(base) ((base)->PLL_VIDEO_TOG) +#define CCM_ANALOG_PLL_VIDEO_NUM_REG(base) ((base)->PLL_VIDEO_NUM) +#define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) ((base)->PLL_VIDEO_DENOM) +#define CCM_ANALOG_PLL_ENET_REG(base) ((base)->PLL_ENET) +#define CCM_ANALOG_PLL_ENET_SET_REG(base) ((base)->PLL_ENET_SET) +#define CCM_ANALOG_PLL_ENET_CLR_REG(base) ((base)->PLL_ENET_CLR) +#define CCM_ANALOG_PLL_ENET_TOG_REG(base) ((base)->PLL_ENET_TOG) +#define CCM_ANALOG_PFD_480_REG(base) ((base)->PFD_480) +#define CCM_ANALOG_PFD_480_SET_REG(base) ((base)->PFD_480_SET) +#define CCM_ANALOG_PFD_480_CLR_REG(base) ((base)->PFD_480_CLR) +#define CCM_ANALOG_PFD_480_TOG_REG(base) ((base)->PFD_480_TOG) +#define CCM_ANALOG_PFD_528_REG(base) ((base)->PFD_528) +#define CCM_ANALOG_PFD_528_SET_REG(base) ((base)->PFD_528_SET) +#define CCM_ANALOG_PFD_528_CLR_REG(base) ((base)->PFD_528_CLR) +#define CCM_ANALOG_PFD_528_TOG_REG(base) ((base)->PFD_528_TOG) +#define CCM_ANALOG_MISC0_REG(base) ((base)->MISC0) +#define CCM_ANALOG_MISC0_SET_REG(base) ((base)->MISC0_SET) +#define CCM_ANALOG_MISC0_CLR_REG(base) ((base)->MISC0_CLR) +#define CCM_ANALOG_MISC0_TOG_REG(base) ((base)->MISC0_TOG) +#define CCM_ANALOG_MISC1_REG(base) ((base)->MISC1) +#define CCM_ANALOG_MISC1_SET_REG(base) ((base)->MISC1_SET) +#define CCM_ANALOG_MISC1_CLR_REG(base) ((base)->MISC1_CLR) +#define CCM_ANALOG_MISC1_TOG_REG(base) ((base)->MISC1_TOG) +#define CCM_ANALOG_MISC2_REG(base) ((base)->MISC2) +#define CCM_ANALOG_MISC2_SET_REG(base) ((base)->MISC2_SET) +#define CCM_ANALOG_MISC2_CLR_REG(base) ((base)->MISC2_CLR) +#define CCM_ANALOG_MISC2_TOG_REG(base) ((base)->MISC2_TOG) + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/* PLL_ARM Bit Fields */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<CSICR1) +#define CSI_CSICR2_REG(base) ((base)->CSICR2) +#define CSI_CSICR3_REG(base) ((base)->CSICR3) +#define CSI_CSISTATFIFO_REG(base) ((base)->CSISTATFIFO) +#define CSI_CSIRFIFO_REG(base) ((base)->CSIRFIFO) +#define CSI_CSIRXCNT_REG(base) ((base)->CSIRXCNT) +#define CSI_CSISR_REG(base) ((base)->CSISR) +#define CSI_CSIDMASA_STATFIFO_REG(base) ((base)->CSIDMASA_STATFIFO) +#define CSI_CSIDMATS_STATFIFO_REG(base) ((base)->CSIDMATS_STATFIFO) +#define CSI_CSIDMASA_FB1_REG(base) ((base)->CSIDMASA_FB1) +#define CSI_CSIDMASA_FB2_REG(base) ((base)->CSIDMASA_FB2) +#define CSI_CSIFBUF_PARA_REG(base) ((base)->CSIFBUF_PARA) +#define CSI_CSIIMAG_PARA_REG(base) ((base)->CSIIMAG_PARA) +#define CSI_CSICR18_REG(base) ((base)->CSICR18) +#define CSI_CSICR19_REG(base) ((base)->CSICR19) + +/*! + * @} + */ /* end of group CSI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/* CSICR1 Bit Fields */ +#define CSI_CSICR1_PIXEL_BIT_MASK 0x1u +#define CSI_CSICR1_PIXEL_BIT_SHIFT 0 +#define CSI_CSICR1_REDGE_MASK 0x2u +#define CSI_CSICR1_REDGE_SHIFT 1 +#define CSI_CSICR1_INV_PCLK_MASK 0x4u +#define CSI_CSICR1_INV_PCLK_SHIFT 2 +#define CSI_CSICR1_INV_DATA_MASK 0x8u +#define CSI_CSICR1_INV_DATA_SHIFT 3 +#define CSI_CSICR1_GCLK_MODE_MASK 0x10u +#define CSI_CSICR1_GCLK_MODE_SHIFT 4 +#define CSI_CSICR1_CLR_RXFIFO_MASK 0x20u +#define CSI_CSICR1_CLR_RXFIFO_SHIFT 5 +#define CSI_CSICR1_CLR_STATFIFO_MASK 0x40u +#define CSI_CSICR1_CLR_STATFIFO_SHIFT 6 +#define CSI_CSICR1_PACK_DIR_MASK 0x80u +#define CSI_CSICR1_PACK_DIR_SHIFT 7 +#define CSI_CSICR1_FCC_MASK 0x100u +#define CSI_CSICR1_FCC_SHIFT 8 +#define CSI_CSICR1_CCIR_EN_MASK 0x400u +#define CSI_CSICR1_CCIR_EN_SHIFT 10 +#define CSI_CSICR1_HSYNC_POL_MASK 0x800u +#define CSI_CSICR1_HSYNC_POL_SHIFT 11 +#define CSI_CSICR1_SOF_INTEN_MASK 0x10000u +#define CSI_CSICR1_SOF_INTEN_SHIFT 16 +#define CSI_CSICR1_SOF_POL_MASK 0x20000u +#define CSI_CSICR1_SOF_POL_SHIFT 17 +#define CSI_CSICR1_RXFF_INTEN_MASK 0x40000u +#define CSI_CSICR1_RXFF_INTEN_SHIFT 18 +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK 0x80000u +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT 19 +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK 0x100000u +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT 20 +#define CSI_CSICR1_STATFF_INTEN_MASK 0x200000u +#define CSI_CSICR1_STATFF_INTEN_SHIFT 21 +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK 0x400000u +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT 22 +#define CSI_CSICR1_RF_OR_INTEN_MASK 0x1000000u +#define CSI_CSICR1_RF_OR_INTEN_SHIFT 24 +#define CSI_CSICR1_SF_OR_INTEN_MASK 0x2000000u +#define CSI_CSICR1_SF_OR_INTEN_SHIFT 25 +#define CSI_CSICR1_COF_INT_EN_MASK 0x4000000u +#define CSI_CSICR1_COF_INT_EN_SHIFT 26 +#define CSI_CSICR1_VIDEO_MODE_MASK 0x8000000u +#define CSI_CSICR1_VIDEO_MODE_SHIFT 27 +#define CSI_CSICR1_PrP_IF_EN_MASK 0x10000000u +#define CSI_CSICR1_PrP_IF_EN_SHIFT 28 +#define CSI_CSICR1_EOF_INT_EN_MASK 0x20000000u +#define CSI_CSICR1_EOF_INT_EN_SHIFT 29 +#define CSI_CSICR1_EXT_VSYNC_MASK 0x40000000u +#define CSI_CSICR1_EXT_VSYNC_SHIFT 30 +#define CSI_CSICR1_SWAP16_EN_MASK 0x80000000u +#define CSI_CSICR1_SWAP16_EN_SHIFT 31 +/* CSICR2 Bit Fields */ +#define CSI_CSICR2_HSC_MASK 0xFFu +#define CSI_CSICR2_HSC_SHIFT 0 +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x))<DCICC) +#define DCIC_DCICIC_REG(base) ((base)->DCICIC) +#define DCIC_DCICS_REG(base) ((base)->DCICS) +#define DCIC_DCICRC_REG(base) ((base)->DCICRC) +#define DCIC_DCICRS_REG(base) ((base)->DCICRS) +#define DCIC_DCICRRS_REG(base) ((base)->DCICRRS) +#define DCIC_DCICRCS_REG(base) ((base)->DCICRCS) + +/*! + * @} + */ /* end of group DCIC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- DCIC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DCIC_Register_Masks DCIC Register Masks + * @{ + */ + +/* DCICC Bit Fields */ +#define DCIC_DCICC_IC_EN_MASK 0x1u +#define DCIC_DCICC_IC_EN_SHIFT 0 +#define DCIC_DCICC_DE_POL_MASK 0x10u +#define DCIC_DCICC_DE_POL_SHIFT 4 +#define DCIC_DCICC_HSYNC_POL_MASK 0x20u +#define DCIC_DCICC_HSYNC_POL_SHIFT 5 +#define DCIC_DCICC_VSYNC_POL_MASK 0x40u +#define DCIC_DCICC_VSYNC_POL_SHIFT 6 +#define DCIC_DCICC_CLK_POL_MASK 0x80u +#define DCIC_DCICC_CLK_POL_SHIFT 7 +/* DCICIC Bit Fields */ +#define DCIC_DCICIC_EI_MASK_MASK 0x1u +#define DCIC_DCICIC_EI_MASK_SHIFT 0 +#define DCIC_DCICIC_FI_MASK_MASK 0x2u +#define DCIC_DCICIC_FI_MASK_SHIFT 1 +#define DCIC_DCICIC_FREEZE_MASK_MASK 0x8u +#define DCIC_DCICIC_FREEZE_MASK_SHIFT 3 +#define DCIC_DCICIC_EXT_SIG_EN_MASK 0x10000u +#define DCIC_DCICIC_EXT_SIG_EN_SHIFT 16 +/* DCICS Bit Fields */ +#define DCIC_DCICS_ROI_MATCH_STAT_MASK 0xFFFFu +#define DCIC_DCICS_ROI_MATCH_STAT_SHIFT 0 +#define DCIC_DCICS_ROI_MATCH_STAT(x) (((uint32_t)(((uint32_t)(x))<THRS) +#define DVFSC_COUN_REG(base) ((base)->COUN) +#define DVFSC_SIG1_REG(base) ((base)->SIG1) +#define DVFSC_DVFSSIG0_REG(base) ((base)->DVFSSIG0) +#define DVFSC_DVFSGPC0_REG(base) ((base)->DVFSGPC0) +#define DVFSC_DVFSGPC1_REG(base) ((base)->DVFSGPC1) +#define DVFSC_DVFSGPBT_REG(base) ((base)->DVFSGPBT) +#define DVFSC_DVFSEMAC_REG(base) ((base)->DVFSEMAC) +#define DVFSC_CNTR_REG(base) ((base)->CNTR) +#define DVFSC_DVFSLTR0_0_REG(base) ((base)->DVFSLTR0_0) +#define DVFSC_DVFSLTR0_1_REG(base) ((base)->DVFSLTR0_1) +#define DVFSC_DVFSLTR1_0_REG(base) ((base)->DVFSLTR1_0) +#define DVFSC_DVFSLTR1_1_REG(base) ((base)->DVFSLTR1_1) +#define DVFSC_DVFSPT0_REG(base) ((base)->DVFSPT0) +#define DVFSC_DVFSPT1_REG(base) ((base)->DVFSPT1) +#define DVFSC_DVFSPT2_REG(base) ((base)->DVFSPT2) +#define DVFSC_DVFSPT3_REG(base) ((base)->DVFSPT3) + +/*! + * @} + */ /* end of group DVFSC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- DVFSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DVFSC_Register_Masks DVFSC Register Masks + * @{ + */ + +/* THRS Bit Fields */ +#define DVFSC_THRS_PNCTHR_MASK 0x3Fu +#define DVFSC_THRS_PNCTHR_SHIFT 0 +#define DVFSC_THRS_PNCTHR(x) (((uint32_t)(((uint32_t)(x))<RXDATA) +#define ECSPI_TXDATA_REG(base) ((base)->TXDATA) +#define ECSPI_CONREG_REG(base) ((base)->CONREG) +#define ECSPI_CONFIGREG_REG(base) ((base)->CONFIGREG) +#define ECSPI_INTREG_REG(base) ((base)->INTREG) +#define ECSPI_DMAREG_REG(base) ((base)->DMAREG) +#define ECSPI_STATREG_REG(base) ((base)->STATREG) +#define ECSPI_PERIODREG_REG(base) ((base)->PERIODREG) +#define ECSPI_TESTREG_REG(base) ((base)->TESTREG) +#define ECSPI_MSGDATA_REG(base) ((base)->MSGDATA) + +/*! + * @} + */ /* end of group ECSPI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/* RXDATA Bit Fields */ +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK 0xFFFFFFFFu +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT 0 +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x))<CS[index].CSGCR1) +#define EIM_CSGCR2_REG(base,index) ((base)->CS[index].CSGCR2) +#define EIM_CSRCR1_REG(base,index) ((base)->CS[index].CSRCR1) +#define EIM_CSRCR2_REG(base,index) ((base)->CS[index].CSRCR2) +#define EIM_CSWCR1_REG(base,index) ((base)->CS[index].CSWCR1) +#define EIM_CSWCR2_REG(base,index) ((base)->CS[index].CSWCR2) +#define EIM_WCR_REG(base) ((base)->WCR) +#define EIM_DCR_REG(base) ((base)->DCR) +#define EIM_DSR_REG(base) ((base)->DSR) +#define EIM_WIAR_REG(base) ((base)->WIAR) +#define EIM_EAR_REG(base) ((base)->EAR) + +/*! + * @} + */ /* end of group EIM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/* CSGCR1 Bit Fields */ +#define EIM_CSGCR1_CSEN_MASK 0x1u +#define EIM_CSGCR1_CSEN_SHIFT 0 +#define EIM_CSGCR1_SWR_MASK 0x2u +#define EIM_CSGCR1_SWR_SHIFT 1 +#define EIM_CSGCR1_SRD_MASK 0x4u +#define EIM_CSGCR1_SRD_SHIFT 2 +#define EIM_CSGCR1_MUM_MASK 0x8u +#define EIM_CSGCR1_MUM_SHIFT 3 +#define EIM_CSGCR1_WFL_MASK 0x10u +#define EIM_CSGCR1_WFL_SHIFT 4 +#define EIM_CSGCR1_RFL_MASK 0x20u +#define EIM_CSGCR1_RFL_SHIFT 5 +#define EIM_CSGCR1_CRE_MASK 0x40u +#define EIM_CSGCR1_CRE_SHIFT 6 +#define EIM_CSGCR1_CREP_MASK 0x80u +#define EIM_CSGCR1_CREP_SHIFT 7 +#define EIM_CSGCR1_BL_MASK 0x700u +#define EIM_CSGCR1_BL_SHIFT 8 +#define EIM_CSGCR1_BL(x) (((uint32_t)(((uint32_t)(x))<EIR) +#define ENET_EIMR_REG(base) ((base)->EIMR) +#define ENET_RDAR_REG(base) ((base)->RDAR) +#define ENET_TDAR_REG(base) ((base)->TDAR) +#define ENET_ECR_REG(base) ((base)->ECR) +#define ENET_MMFR_REG(base) ((base)->MMFR) +#define ENET_MSCR_REG(base) ((base)->MSCR) +#define ENET_MIBC_REG(base) ((base)->MIBC) +#define ENET_RCR_REG(base) ((base)->RCR) +#define ENET_TCR_REG(base) ((base)->TCR) +#define ENET_PALR_REG(base) ((base)->PALR) +#define ENET_PAUR_REG(base) ((base)->PAUR) +#define ENET_OPD_REG(base) ((base)->OPD) +#define ENET_TXIC_REG(base,index) ((base)->TXIC[index]) +#define ENET_RXIC_REG(base,index) ((base)->RXIC[index]) +#define ENET_IAUR_REG(base) ((base)->IAUR) +#define ENET_IALR_REG(base) ((base)->IALR) +#define ENET_GAUR_REG(base) ((base)->GAUR) +#define ENET_GALR_REG(base) ((base)->GALR) +#define ENET_TFWR_REG(base) ((base)->TFWR) +#define ENET_RDSR1_REG(base) ((base)->RDSR1) +#define ENET_TDSR1_REG(base) ((base)->TDSR1) +#define ENET_MRBR1_REG(base) ((base)->MRBR1) +#define ENET_RDSR2_REG(base) ((base)->RDSR2) +#define ENET_TDSR2_REG(base) ((base)->TDSR2) +#define ENET_MRBR2_REG(base) ((base)->MRBR2) +#define ENET_RDSR_REG(base) ((base)->RDSR) +#define ENET_TDSR_REG(base) ((base)->TDSR) +#define ENET_MRBR_REG(base) ((base)->MRBR) +#define ENET_RSFL_REG(base) ((base)->RSFL) +#define ENET_RSEM_REG(base) ((base)->RSEM) +#define ENET_RAEM_REG(base) ((base)->RAEM) +#define ENET_RAFL_REG(base) ((base)->RAFL) +#define ENET_TSEM_REG(base) ((base)->TSEM) +#define ENET_TAEM_REG(base) ((base)->TAEM) +#define ENET_TAFL_REG(base) ((base)->TAFL) +#define ENET_TIPG_REG(base) ((base)->TIPG) +#define ENET_FTRL_REG(base) ((base)->FTRL) +#define ENET_TACC_REG(base) ((base)->TACC) +#define ENET_RACC_REG(base) ((base)->RACC) +#define ENET_RCMR_REG(base,index) ((base)->RCMR[index]) +#define ENET_DMACFG_REG(base,index) ((base)->DMACFG[index]) +#define ENET_RDAR1_REG(base) ((base)->RDAR1) +#define ENET_TDAR1_REG(base) ((base)->TDAR1) +#define ENET_RDAR2_REG(base) ((base)->RDAR2) +#define ENET_TDAR2_REG(base) ((base)->TDAR2) +#define ENET_QOS_REG(base) ((base)->QOS) +#define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) +#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) +#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) +#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) +#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) +#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) +#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) +#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) +#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) +#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) +#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) +#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) +#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) +#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) +#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) +#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) +#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) +#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) +#define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) +#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) +#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) +#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) +#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) +#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) +#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) +#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) +#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) +#define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) +#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) +#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) +#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) +#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) +#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) +#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) +#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) +#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) +#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) +#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) +#define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) +#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) +#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) +#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) +#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) +#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) +#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) +#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) +#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) +#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) +#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) +#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) +#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) +#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) +#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) +#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) +#define ENET_ATCR_REG(base) ((base)->ATCR) +#define ENET_ATVR_REG(base) ((base)->ATVR) +#define ENET_ATOFF_REG(base) ((base)->ATOFF) +#define ENET_ATPER_REG(base) ((base)->ATPER) +#define ENET_ATCOR_REG(base) ((base)->ATCOR) +#define ENET_ATINC_REG(base) ((base)->ATINC) +#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) +#define ENET_TGSR_REG(base) ((base)->TGSR) +#define ENET_TCSR_REG(base,index) ((base)->TC[index].TCSR) +#define ENET_TCCR_REG(base,index) ((base)->TC[index].TCCR) + +/*! + * @} + */ /* end of group ENET_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/* EIR Bit Fields */ +#define ENET_EIR_RXB1_MASK 0x1u +#define ENET_EIR_RXB1_SHIFT 0 +#define ENET_EIR_RXF1_MASK 0x2u +#define ENET_EIR_RXF1_SHIFT 1 +#define ENET_EIR_TXB1_MASK 0x4u +#define ENET_EIR_TXB1_SHIFT 2 +#define ENET_EIR_TXF1_MASK 0x8u +#define ENET_EIR_TXF1_SHIFT 3 +#define ENET_EIR_RXB2_MASK 0x10u +#define ENET_EIR_RXB2_SHIFT 4 +#define ENET_EIR_RXF2_MASK 0x20u +#define ENET_EIR_RXF2_SHIFT 5 +#define ENET_EIR_TXB2_MASK 0x40u +#define ENET_EIR_TXB2_SHIFT 6 +#define ENET_EIR_TXF2_MASK 0x80u +#define ENET_EIR_TXF2_SHIFT 7 +#define ENET_EIR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIR_RXFLUSH_0_SHIFT 12 +#define ENET_EIR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIR_RXFLUSH_1_SHIFT 13 +#define ENET_EIR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIR_RXFLUSH_2_SHIFT 14 +#define ENET_EIR_TS_TIMER_MASK 0x8000u +#define ENET_EIR_TS_TIMER_SHIFT 15 +#define ENET_EIR_TS_AVAIL_MASK 0x10000u +#define ENET_EIR_TS_AVAIL_SHIFT 16 +#define ENET_EIR_WAKEUP_MASK 0x20000u +#define ENET_EIR_WAKEUP_SHIFT 17 +#define ENET_EIR_PLR_MASK 0x40000u +#define ENET_EIR_PLR_SHIFT 18 +#define ENET_EIR_UN_MASK 0x80000u +#define ENET_EIR_UN_SHIFT 19 +#define ENET_EIR_RL_MASK 0x100000u +#define ENET_EIR_RL_SHIFT 20 +#define ENET_EIR_LC_MASK 0x200000u +#define ENET_EIR_LC_SHIFT 21 +#define ENET_EIR_EBERR_MASK 0x400000u +#define ENET_EIR_EBERR_SHIFT 22 +#define ENET_EIR_MII_MASK 0x800000u +#define ENET_EIR_MII_SHIFT 23 +#define ENET_EIR_RXB_MASK 0x1000000u +#define ENET_EIR_RXB_SHIFT 24 +#define ENET_EIR_RXF_MASK 0x2000000u +#define ENET_EIR_RXF_SHIFT 25 +#define ENET_EIR_TXB_MASK 0x4000000u +#define ENET_EIR_TXB_SHIFT 26 +#define ENET_EIR_TXF_MASK 0x8000000u +#define ENET_EIR_TXF_SHIFT 27 +#define ENET_EIR_GRA_MASK 0x10000000u +#define ENET_EIR_GRA_SHIFT 28 +#define ENET_EIR_BABT_MASK 0x20000000u +#define ENET_EIR_BABT_SHIFT 29 +#define ENET_EIR_BABR_MASK 0x40000000u +#define ENET_EIR_BABR_SHIFT 30 +/* EIMR Bit Fields */ +#define ENET_EIMR_RXB1_MASK 0x1u +#define ENET_EIMR_RXB1_SHIFT 0 +#define ENET_EIMR_RXF1_MASK 0x2u +#define ENET_EIMR_RXF1_SHIFT 1 +#define ENET_EIMR_TXB1_MASK 0x4u +#define ENET_EIMR_TXB1_SHIFT 2 +#define ENET_EIMR_TXF1_MASK 0x8u +#define ENET_EIMR_TXF1_SHIFT 3 +#define ENET_EIMR_RXB2_MASK 0x10u +#define ENET_EIMR_RXB2_SHIFT 4 +#define ENET_EIMR_RXF2_MASK 0x20u +#define ENET_EIMR_RXF2_SHIFT 5 +#define ENET_EIMR_TXB2_MASK 0x40u +#define ENET_EIMR_TXB2_SHIFT 6 +#define ENET_EIMR_TXF2_MASK 0x80u +#define ENET_EIMR_TXF2_SHIFT 7 +#define ENET_EIMR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIMR_RXFLUSH_0_SHIFT 12 +#define ENET_EIMR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIMR_RXFLUSH_1_SHIFT 13 +#define ENET_EIMR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIMR_RXFLUSH_2_SHIFT 14 +#define ENET_EIMR_TS_TIMER_MASK 0x8000u +#define ENET_EIMR_TS_TIMER_SHIFT 15 +#define ENET_EIMR_TS_AVAIL_MASK 0x10000u +#define ENET_EIMR_TS_AVAIL_SHIFT 16 +#define ENET_EIMR_WAKEUP_MASK 0x20000u +#define ENET_EIMR_WAKEUP_SHIFT 17 +#define ENET_EIMR_PLR_MASK 0x40000u +#define ENET_EIMR_PLR_SHIFT 18 +#define ENET_EIMR_UN_MASK 0x80000u +#define ENET_EIMR_UN_SHIFT 19 +#define ENET_EIMR_RL_MASK 0x100000u +#define ENET_EIMR_RL_SHIFT 20 +#define ENET_EIMR_LC_MASK 0x200000u +#define ENET_EIMR_LC_SHIFT 21 +#define ENET_EIMR_EBERR_MASK 0x400000u +#define ENET_EIMR_EBERR_SHIFT 22 +#define ENET_EIMR_MII_MASK 0x800000u +#define ENET_EIMR_MII_SHIFT 23 +#define ENET_EIMR_RXB_MASK 0x1000000u +#define ENET_EIMR_RXB_SHIFT 24 +#define ENET_EIMR_RXF_MASK 0x2000000u +#define ENET_EIMR_RXF_SHIFT 25 +#define ENET_EIMR_TXB_MASK 0x4000000u +#define ENET_EIMR_TXB_SHIFT 26 +#define ENET_EIMR_TXF_MASK 0x8000000u +#define ENET_EIMR_TXF_SHIFT 27 +#define ENET_EIMR_GRA_MASK 0x10000000u +#define ENET_EIMR_GRA_SHIFT 28 +#define ENET_EIMR_BABT_MASK 0x20000000u +#define ENET_EIMR_BABT_SHIFT 29 +#define ENET_EIMR_BABR_MASK 0x40000000u +#define ENET_EIMR_BABR_SHIFT 30 +/* RDAR Bit Fields */ +#define ENET_RDAR_RDAR_MASK 0x1000000u +#define ENET_RDAR_RDAR_SHIFT 24 +/* TDAR Bit Fields */ +#define ENET_TDAR_TDAR_MASK 0x1000000u +#define ENET_TDAR_TDAR_SHIFT 24 +/* ECR Bit Fields */ +#define ENET_ECR_RESET_MASK 0x1u +#define ENET_ECR_RESET_SHIFT 0 +#define ENET_ECR_ETHEREN_MASK 0x2u +#define ENET_ECR_ETHEREN_SHIFT 1 +#define ENET_ECR_MAGICEN_MASK 0x4u +#define ENET_ECR_MAGICEN_SHIFT 2 +#define ENET_ECR_SLEEP_MASK 0x8u +#define ENET_ECR_SLEEP_SHIFT 3 +#define ENET_ECR_EN1588_MASK 0x10u +#define ENET_ECR_EN1588_SHIFT 4 +#define ENET_ECR_SPEED_MASK 0x20u +#define ENET_ECR_SPEED_SHIFT 5 +#define ENET_ECR_DBGEN_MASK 0x40u +#define ENET_ECR_DBGEN_SHIFT 6 +#define ENET_ECR_DBSWP_MASK 0x100u +#define ENET_ECR_DBSWP_SHIFT 8 +#define ENET_ECR_SVLANEN_MASK 0x200u +#define ENET_ECR_SVLANEN_SHIFT 9 +#define ENET_ECR_VLANUSE2ND_MASK 0x400u +#define ENET_ECR_VLANUSE2ND_SHIFT 10 +#define ENET_ECR_SVLANDBL_MASK 0x800u +#define ENET_ECR_SVLANDBL_SHIFT 11 +/* MMFR Bit Fields */ +#define ENET_MMFR_DATA_MASK 0xFFFFu +#define ENET_MMFR_DATA_SHIFT 0 +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CR) +#define EPIT_SR_REG(base) ((base)->SR) +#define EPIT_LR_REG(base) ((base)->LR) +#define EPIT_CMPR_REG(base) ((base)->CMPR) +#define EPIT_CNR_REG(base) ((base)->CNR) + +/*! + * @} + */ /* end of group EPIT_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- EPIT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPIT_Register_Masks EPIT Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define EPIT_CR_EN_MASK 0x1u +#define EPIT_CR_EN_SHIFT 0 +#define EPIT_CR_ENMOD_MASK 0x2u +#define EPIT_CR_ENMOD_SHIFT 1 +#define EPIT_CR_OCIEN_MASK 0x4u +#define EPIT_CR_OCIEN_SHIFT 2 +#define EPIT_CR_RLD_MASK 0x8u +#define EPIT_CR_RLD_SHIFT 3 +#define EPIT_CR_PRESCALAR_MASK 0xFFF0u +#define EPIT_CR_PRESCALAR_SHIFT 4 +#define EPIT_CR_PRESCALAR(x) (((uint32_t)(((uint32_t)(x))<ETDR) +#define ESAI_ERDR_REG(base) ((base)->ERDR) +#define ESAI_ECR_REG(base) ((base)->ECR) +#define ESAI_ESR_REG(base) ((base)->ESR) +#define ESAI_TFCR_REG(base) ((base)->TFCR) +#define ESAI_TFSR_REG(base) ((base)->TFSR) +#define ESAI_RFCR_REG(base) ((base)->RFCR) +#define ESAI_RFSR_REG(base) ((base)->RFSR) +#define ESAI_TX_REG(base,index) ((base)->TX[index]) +#define ESAI_TSR_REG(base) ((base)->TSR) +#define ESAI_RX_REG(base,index) ((base)->RX[index]) +#define ESAI_SAISR_REG(base) ((base)->SAISR) +#define ESAI_SAICR_REG(base) ((base)->SAICR) +#define ESAI_TCR_REG(base) ((base)->TCR) +#define ESAI_TCCR_REG(base) ((base)->TCCR) +#define ESAI_RCR_REG(base) ((base)->RCR) +#define ESAI_RCCR_REG(base) ((base)->RCCR) +#define ESAI_TSMA_REG(base) ((base)->TSMA) +#define ESAI_TSMB_REG(base) ((base)->TSMB) +#define ESAI_RSMA_REG(base) ((base)->RSMA) +#define ESAI_RSMB_REG(base) ((base)->RSMB) +#define ESAI_PRRC_REG(base) ((base)->PRRC) +#define ESAI_PCRC_REG(base) ((base)->PCRC) + +/*! + * @} + */ /* end of group ESAI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ESAI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ESAI_Register_Masks ESAI Register Masks + * @{ + */ + +/* ETDR Bit Fields */ +#define ESAI_ETDR_ETDR_MASK 0xFFFFFFFFu +#define ESAI_ETDR_ETDR_SHIFT 0 +#define ESAI_ETDR_ETDR(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define GIS_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define GIS_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define GIS_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define GIS_CONFIG0_REG(base) ((base)->CONFIG0) +#define GIS_CONFIG0_SET_REG(base) ((base)->CONFIG0_SET) +#define GIS_CONFIG0_CLR_REG(base) ((base)->CONFIG0_CLR) +#define GIS_CONFIG0_TOG_REG(base) ((base)->CONFIG0_TOG) +#define GIS_CONFIG1_REG(base) ((base)->CONFIG1) +#define GIS_CONFIG1_SET_REG(base) ((base)->CONFIG1_SET) +#define GIS_CONFIG1_CLR_REG(base) ((base)->CONFIG1_CLR) +#define GIS_CONFIG1_TOG_REG(base) ((base)->CONFIG1_TOG) +#define GIS_FB0_REG(base) ((base)->FB0) +#define GIS_FB1_REG(base) ((base)->FB1) +#define GIS_PXP_FB0_REG(base) ((base)->PXP_FB0) +#define GIS_PXP_FB1_REG(base) ((base)->PXP_FB1) +#define GIS_CH0_CTRL_REG(base) ((base)->CH0_CTRL) +#define GIS_CH0_CTRL_SET_REG(base) ((base)->CH0_CTRL_SET) +#define GIS_CH0_CTRL_CLR_REG(base) ((base)->CH0_CTRL_CLR) +#define GIS_CH0_CTRL_TOG_REG(base) ((base)->CH0_CTRL_TOG) +#define GIS_CH0_ADDR0_REG(base) ((base)->CH0_ADDR0) +#define GIS_CH0_ADDR0_SET_REG(base) ((base)->CH0_ADDR0_SET) +#define GIS_CH0_ADDR0_CLR_REG(base) ((base)->CH0_ADDR0_CLR) +#define GIS_CH0_ADDR0_TOG_REG(base) ((base)->CH0_ADDR0_TOG) +#define GIS_CH0_DATA0_REG(base) ((base)->CH0_DATA0) +#define GIS_CH0_ADDR1_REG(base) ((base)->CH0_ADDR1) +#define GIS_CH0_ADDR1_SET_REG(base) ((base)->CH0_ADDR1_SET) +#define GIS_CH0_ADDR1_CLR_REG(base) ((base)->CH0_ADDR1_CLR) +#define GIS_CH0_ADDR1_TOG_REG(base) ((base)->CH0_ADDR1_TOG) +#define GIS_CH0_DATA1_REG(base) ((base)->CH0_DATA1) +#define GIS_CH0_ADDR2_REG(base) ((base)->CH0_ADDR2) +#define GIS_CH0_ADDR2_SET_REG(base) ((base)->CH0_ADDR2_SET) +#define GIS_CH0_ADDR2_CLR_REG(base) ((base)->CH0_ADDR2_CLR) +#define GIS_CH0_ADDR2_TOG_REG(base) ((base)->CH0_ADDR2_TOG) +#define GIS_CH0_DATA2_REG(base) ((base)->CH0_DATA2) +#define GIS_CH0_ADDR3_REG(base) ((base)->CH0_ADDR3) +#define GIS_CH0_ADDR3_SET_REG(base) ((base)->CH0_ADDR3_SET) +#define GIS_CH0_ADDR3_CLR_REG(base) ((base)->CH0_ADDR3_CLR) +#define GIS_CH0_ADDR3_TOG_REG(base) ((base)->CH0_ADDR3_TOG) +#define GIS_CH0_DATA3_REG(base) ((base)->CH0_DATA3) +#define GIS_CH1_CTRL_REG(base) ((base)->CH1_CTRL) +#define GIS_CH1_CTRL_SET_REG(base) ((base)->CH1_CTRL_SET) +#define GIS_CH1_CTRL_CLR_REG(base) ((base)->CH1_CTRL_CLR) +#define GIS_CH1_CTRL_TOG_REG(base) ((base)->CH1_CTRL_TOG) +#define GIS_CH1_ADDR0_REG(base) ((base)->CH1_ADDR0) +#define GIS_CH1_ADDR0_SET_REG(base) ((base)->CH1_ADDR0_SET) +#define GIS_CH1_ADDR0_CLR_REG(base) ((base)->CH1_ADDR0_CLR) +#define GIS_CH1_ADDR0_TOG_REG(base) ((base)->CH1_ADDR0_TOG) +#define GIS_CH1_DATA0_REG(base) ((base)->CH1_DATA0) +#define GIS_CH1_ADDR1_REG(base) ((base)->CH1_ADDR1) +#define GIS_CH1_ADDR1_SET_REG(base) ((base)->CH1_ADDR1_SET) +#define GIS_CH1_ADDR1_CLR_REG(base) ((base)->CH1_ADDR1_CLR) +#define GIS_CH1_ADDR1_TOG_REG(base) ((base)->CH1_ADDR1_TOG) +#define GIS_CH1_DATA1_REG(base) ((base)->CH1_DATA1) +#define GIS_CH1_ADDR2_REG(base) ((base)->CH1_ADDR2) +#define GIS_CH1_ADDR2_SET_REG(base) ((base)->CH1_ADDR2_SET) +#define GIS_CH1_ADDR2_CLR_REG(base) ((base)->CH1_ADDR2_CLR) +#define GIS_CH1_ADDR2_TOG_REG(base) ((base)->CH1_ADDR2_TOG) +#define GIS_CH1_DATA2_REG(base) ((base)->CH1_DATA2) +#define GIS_CH1_ADDR3_REG(base) ((base)->CH1_ADDR3) +#define GIS_CH1_ADDR3_SET_REG(base) ((base)->CH1_ADDR3_SET) +#define GIS_CH1_ADDR3_CLR_REG(base) ((base)->CH1_ADDR3_CLR) +#define GIS_CH1_ADDR3_TOG_REG(base) ((base)->CH1_ADDR3_TOG) +#define GIS_CH1_DATA3_REG(base) ((base)->CH1_DATA3) +#define GIS_CH2_CTRL_REG(base) ((base)->CH2_CTRL) +#define GIS_CH2_CTRL_SET_REG(base) ((base)->CH2_CTRL_SET) +#define GIS_CH2_CTRL_CLR_REG(base) ((base)->CH2_CTRL_CLR) +#define GIS_CH2_CTRL_TOG_REG(base) ((base)->CH2_CTRL_TOG) +#define GIS_CH2_ADDR0_REG(base) ((base)->CH2_ADDR0) +#define GIS_CH2_ADDR0_SET_REG(base) ((base)->CH2_ADDR0_SET) +#define GIS_CH2_ADDR0_CLR_REG(base) ((base)->CH2_ADDR0_CLR) +#define GIS_CH2_ADDR0_TOG_REG(base) ((base)->CH2_ADDR0_TOG) +#define GIS_CH2_DATA0_REG(base) ((base)->CH2_DATA0) +#define GIS_CH2_ADDR1_REG(base) ((base)->CH2_ADDR1) +#define GIS_CH2_ADDR1_SET_REG(base) ((base)->CH2_ADDR1_SET) +#define GIS_CH2_ADDR1_CLR_REG(base) ((base)->CH2_ADDR1_CLR) +#define GIS_CH2_ADDR1_TOG_REG(base) ((base)->CH2_ADDR1_TOG) +#define GIS_CH2_DATA1_REG(base) ((base)->CH2_DATA1) +#define GIS_CH2_ADDR2_REG(base) ((base)->CH2_ADDR2) +#define GIS_CH2_ADDR2_SET_REG(base) ((base)->CH2_ADDR2_SET) +#define GIS_CH2_ADDR2_CLR_REG(base) ((base)->CH2_ADDR2_CLR) +#define GIS_CH2_ADDR2_TOG_REG(base) ((base)->CH2_ADDR2_TOG) +#define GIS_CH2_DATA2_REG(base) ((base)->CH2_DATA2) +#define GIS_CH2_ADDR3_REG(base) ((base)->CH2_ADDR3) +#define GIS_CH2_ADDR3_SET_REG(base) ((base)->CH2_ADDR3_SET) +#define GIS_CH2_ADDR3_CLR_REG(base) ((base)->CH2_ADDR3_CLR) +#define GIS_CH2_ADDR3_TOG_REG(base) ((base)->CH2_ADDR3_TOG) +#define GIS_CH2_DATA3_REG(base) ((base)->CH2_DATA3) +#define GIS_CH3_CTRL_REG(base) ((base)->CH3_CTRL) +#define GIS_CH3_CTRL_SET_REG(base) ((base)->CH3_CTRL_SET) +#define GIS_CH3_CTRL_CLR_REG(base) ((base)->CH3_CTRL_CLR) +#define GIS_CH3_CTRL_TOG_REG(base) ((base)->CH3_CTRL_TOG) +#define GIS_CH3_ADDR0_REG(base) ((base)->CH3_ADDR0) +#define GIS_CH3_ADDR0_SET_REG(base) ((base)->CH3_ADDR0_SET) +#define GIS_CH3_ADDR0_CLR_REG(base) ((base)->CH3_ADDR0_CLR) +#define GIS_CH3_ADDR0_TOG_REG(base) ((base)->CH3_ADDR0_TOG) +#define GIS_CH3_DATA0_REG(base) ((base)->CH3_DATA0) +#define GIS_CH3_ADDR1_REG(base) ((base)->CH3_ADDR1) +#define GIS_CH3_ADDR1_SET_REG(base) ((base)->CH3_ADDR1_SET) +#define GIS_CH3_ADDR1_CLR_REG(base) ((base)->CH3_ADDR1_CLR) +#define GIS_CH3_ADDR1_TOG_REG(base) ((base)->CH3_ADDR1_TOG) +#define GIS_CH3_DATA1_REG(base) ((base)->CH3_DATA1) +#define GIS_CH3_ADDR2_REG(base) ((base)->CH3_ADDR2) +#define GIS_CH3_ADDR2_SET_REG(base) ((base)->CH3_ADDR2_SET) +#define GIS_CH3_ADDR2_CLR_REG(base) ((base)->CH3_ADDR2_CLR) +#define GIS_CH3_ADDR2_TOG_REG(base) ((base)->CH3_ADDR2_TOG) +#define GIS_CH3_DATA2_REG(base) ((base)->CH3_DATA2) +#define GIS_CH3_ADDR3_REG(base) ((base)->CH3_ADDR3) +#define GIS_CH3_ADDR3_SET_REG(base) ((base)->CH3_ADDR3_SET) +#define GIS_CH3_ADDR3_CLR_REG(base) ((base)->CH3_ADDR3_CLR) +#define GIS_CH3_ADDR3_TOG_REG(base) ((base)->CH3_ADDR3_TOG) +#define GIS_CH3_DATA3_REG(base) ((base)->CH3_DATA3) +#define GIS_CH4_CTRL_REG(base) ((base)->CH4_CTRL) +#define GIS_CH4_CTRL_SET_REG(base) ((base)->CH4_CTRL_SET) +#define GIS_CH4_CTRL_CLR_REG(base) ((base)->CH4_CTRL_CLR) +#define GIS_CH4_CTRL_TOG_REG(base) ((base)->CH4_CTRL_TOG) +#define GIS_CH4_ADDR0_REG(base) ((base)->CH4_ADDR0) +#define GIS_CH4_ADDR0_SET_REG(base) ((base)->CH4_ADDR0_SET) +#define GIS_CH4_ADDR0_CLR_REG(base) ((base)->CH4_ADDR0_CLR) +#define GIS_CH4_ADDR0_TOG_REG(base) ((base)->CH4_ADDR0_TOG) +#define GIS_CH4_DATA0_REG(base) ((base)->CH4_DATA0) +#define GIS_CH4_ADDR1_REG(base) ((base)->CH4_ADDR1) +#define GIS_CH4_ADDR1_SET_REG(base) ((base)->CH4_ADDR1_SET) +#define GIS_CH4_ADDR1_CLR_REG(base) ((base)->CH4_ADDR1_CLR) +#define GIS_CH4_ADDR1_TOG_REG(base) ((base)->CH4_ADDR1_TOG) +#define GIS_CH4_DATA1_REG(base) ((base)->CH4_DATA1) +#define GIS_CH4_ADDR2_REG(base) ((base)->CH4_ADDR2) +#define GIS_CH4_ADDR2_SET_REG(base) ((base)->CH4_ADDR2_SET) +#define GIS_CH4_ADDR2_CLR_REG(base) ((base)->CH4_ADDR2_CLR) +#define GIS_CH4_ADDR2_TOG_REG(base) ((base)->CH4_ADDR2_TOG) +#define GIS_CH4_DATA2_REG(base) ((base)->CH4_DATA2) +#define GIS_CH4_ADDR3_REG(base) ((base)->CH4_ADDR3) +#define GIS_CH4_ADDR3_SET_REG(base) ((base)->CH4_ADDR3_SET) +#define GIS_CH4_ADDR3_CLR_REG(base) ((base)->CH4_ADDR3_CLR) +#define GIS_CH4_ADDR3_TOG_REG(base) ((base)->CH4_ADDR3_TOG) +#define GIS_CH4_DATA3_REG(base) ((base)->CH4_DATA3) +#define GIS_CH5_CTRL_REG(base) ((base)->CH5_CTRL) +#define GIS_CH5_CTRL_SET_REG(base) ((base)->CH5_CTRL_SET) +#define GIS_CH5_CTRL_CLR_REG(base) ((base)->CH5_CTRL_CLR) +#define GIS_CH5_CTRL_TOG_REG(base) ((base)->CH5_CTRL_TOG) +#define GIS_CH5_ADDR0_REG(base) ((base)->CH5_ADDR0) +#define GIS_CH5_ADDR0_SET_REG(base) ((base)->CH5_ADDR0_SET) +#define GIS_CH5_ADDR0_CLR_REG(base) ((base)->CH5_ADDR0_CLR) +#define GIS_CH5_ADDR0_TOG_REG(base) ((base)->CH5_ADDR0_TOG) +#define GIS_CH5_DATA0_REG(base) ((base)->CH5_DATA0) +#define GIS_CH5_ADDR1_REG(base) ((base)->CH5_ADDR1) +#define GIS_CH5_ADDR1_SET_REG(base) ((base)->CH5_ADDR1_SET) +#define GIS_CH5_ADDR1_CLR_REG(base) ((base)->CH5_ADDR1_CLR) +#define GIS_CH5_ADDR1_TOG_REG(base) ((base)->CH5_ADDR1_TOG) +#define GIS_CH5_DATA1_REG(base) ((base)->CH5_DATA1) +#define GIS_CH5_ADDR2_REG(base) ((base)->CH5_ADDR2) +#define GIS_CH5_ADDR2_SET_REG(base) ((base)->CH5_ADDR2_SET) +#define GIS_CH5_ADDR2_CLR_REG(base) ((base)->CH5_ADDR2_CLR) +#define GIS_CH5_ADDR2_TOG_REG(base) ((base)->CH5_ADDR2_TOG) +#define GIS_CH5_DATA2_REG(base) ((base)->CH5_DATA2) +#define GIS_CH5_ADDR3_REG(base) ((base)->CH5_ADDR3) +#define GIS_CH5_ADDR3_SET_REG(base) ((base)->CH5_ADDR3_SET) +#define GIS_CH5_ADDR3_CLR_REG(base) ((base)->CH5_ADDR3_CLR) +#define GIS_CH5_ADDR3_TOG_REG(base) ((base)->CH5_ADDR3_TOG) +#define GIS_CH5_DATA3_REG(base) ((base)->CH5_DATA3) +#define GIS_DEBUG0_REG(base) ((base)->DEBUG0) +#define GIS_DEBUG1_REG(base) ((base)->DEBUG1) +#define GIS_VERSION_REG(base) ((base)->VERSION) + +/*! + * @} + */ /* end of group GIS_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GIS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GIS_Register_Masks GIS Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define GIS_CTRL_ENABLE_MASK 0x1u +#define GIS_CTRL_ENABLE_SHIFT 0 +#define GIS_CTRL_FB_START_MASK 0x2u +#define GIS_CTRL_FB_START_SHIFT 1 +#define GIS_CTRL_LCDIF_SEL_MASK 0x4u +#define GIS_CTRL_LCDIF_SEL_SHIFT 2 +#define GIS_CTRL_CSI_SEL_MASK 0x8u +#define GIS_CTRL_CSI_SEL_SHIFT 3 +#define GIS_CTRL_CSI0_IRQ_POLARITY_MASK 0x10u +#define GIS_CTRL_CSI0_IRQ_POLARITY_SHIFT 4 +#define GIS_CTRL_CSI1_IRQ_POLARITY_MASK 0x20u +#define GIS_CTRL_CSI1_IRQ_POLARITY_SHIFT 5 +#define GIS_CTRL_PXP_IRQ_POLARITY_MASK 0x40u +#define GIS_CTRL_PXP_IRQ_POLARITY_SHIFT 6 +#define GIS_CTRL_LCDIF0_IRQ_POLARITY_MASK 0x80u +#define GIS_CTRL_LCDIF0_IRQ_POLARITY_SHIFT 7 +#define GIS_CTRL_LCDIF1_IRQ_POLARITY_MASK 0x100u +#define GIS_CTRL_LCDIF1_IRQ_POLARITY_SHIFT 8 +#define GIS_CTRL_CLKGATE_MASK 0x40000000u +#define GIS_CTRL_CLKGATE_SHIFT 30 +#define GIS_CTRL_SFTRST_MASK 0x80000000u +#define GIS_CTRL_SFTRST_SHIFT 31 +/* CTRL_SET Bit Fields */ +#define GIS_CTRL_SET_ENABLE_MASK 0x1u +#define GIS_CTRL_SET_ENABLE_SHIFT 0 +#define GIS_CTRL_SET_FB_START_MASK 0x2u +#define GIS_CTRL_SET_FB_START_SHIFT 1 +#define GIS_CTRL_SET_LCDIF_SEL_MASK 0x4u +#define GIS_CTRL_SET_LCDIF_SEL_SHIFT 2 +#define GIS_CTRL_SET_CSI_SEL_MASK 0x8u +#define GIS_CTRL_SET_CSI_SEL_SHIFT 3 +#define GIS_CTRL_SET_CSI0_IRQ_POLARITY_MASK 0x10u +#define GIS_CTRL_SET_CSI0_IRQ_POLARITY_SHIFT 4 +#define GIS_CTRL_SET_CSI1_IRQ_POLARITY_MASK 0x20u +#define GIS_CTRL_SET_CSI1_IRQ_POLARITY_SHIFT 5 +#define GIS_CTRL_SET_PXP_IRQ_POLARITY_MASK 0x40u +#define GIS_CTRL_SET_PXP_IRQ_POLARITY_SHIFT 6 +#define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_MASK 0x80u +#define GIS_CTRL_SET_LCDIF0_IRQ_POLARITY_SHIFT 7 +#define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_MASK 0x100u +#define GIS_CTRL_SET_LCDIF1_IRQ_POLARITY_SHIFT 8 +#define GIS_CTRL_SET_CLKGATE_MASK 0x40000000u +#define GIS_CTRL_SET_CLKGATE_SHIFT 30 +#define GIS_CTRL_SET_SFTRST_MASK 0x80000000u +#define GIS_CTRL_SET_SFTRST_SHIFT 31 +/* CTRL_CLR Bit Fields */ +#define GIS_CTRL_CLR_ENABLE_MASK 0x1u +#define GIS_CTRL_CLR_ENABLE_SHIFT 0 +#define GIS_CTRL_CLR_FB_START_MASK 0x2u +#define GIS_CTRL_CLR_FB_START_SHIFT 1 +#define GIS_CTRL_CLR_LCDIF_SEL_MASK 0x4u +#define GIS_CTRL_CLR_LCDIF_SEL_SHIFT 2 +#define GIS_CTRL_CLR_CSI_SEL_MASK 0x8u +#define GIS_CTRL_CLR_CSI_SEL_SHIFT 3 +#define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_MASK 0x10u +#define GIS_CTRL_CLR_CSI0_IRQ_POLARITY_SHIFT 4 +#define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_MASK 0x20u +#define GIS_CTRL_CLR_CSI1_IRQ_POLARITY_SHIFT 5 +#define GIS_CTRL_CLR_PXP_IRQ_POLARITY_MASK 0x40u +#define GIS_CTRL_CLR_PXP_IRQ_POLARITY_SHIFT 6 +#define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_MASK 0x80u +#define GIS_CTRL_CLR_LCDIF0_IRQ_POLARITY_SHIFT 7 +#define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_MASK 0x100u +#define GIS_CTRL_CLR_LCDIF1_IRQ_POLARITY_SHIFT 8 +#define GIS_CTRL_CLR_CLKGATE_MASK 0x40000000u +#define GIS_CTRL_CLR_CLKGATE_SHIFT 30 +#define GIS_CTRL_CLR_SFTRST_MASK 0x80000000u +#define GIS_CTRL_CLR_SFTRST_SHIFT 31 +/* CTRL_TOG Bit Fields */ +#define GIS_CTRL_TOG_ENABLE_MASK 0x1u +#define GIS_CTRL_TOG_ENABLE_SHIFT 0 +#define GIS_CTRL_TOG_FB_START_MASK 0x2u +#define GIS_CTRL_TOG_FB_START_SHIFT 1 +#define GIS_CTRL_TOG_LCDIF_SEL_MASK 0x4u +#define GIS_CTRL_TOG_LCDIF_SEL_SHIFT 2 +#define GIS_CTRL_TOG_CSI_SEL_MASK 0x8u +#define GIS_CTRL_TOG_CSI_SEL_SHIFT 3 +#define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_MASK 0x10u +#define GIS_CTRL_TOG_CSI0_IRQ_POLARITY_SHIFT 4 +#define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_MASK 0x20u +#define GIS_CTRL_TOG_CSI1_IRQ_POLARITY_SHIFT 5 +#define GIS_CTRL_TOG_PXP_IRQ_POLARITY_MASK 0x40u +#define GIS_CTRL_TOG_PXP_IRQ_POLARITY_SHIFT 6 +#define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_MASK 0x80u +#define GIS_CTRL_TOG_LCDIF0_IRQ_POLARITY_SHIFT 7 +#define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_MASK 0x100u +#define GIS_CTRL_TOG_LCDIF1_IRQ_POLARITY_SHIFT 8 +#define GIS_CTRL_TOG_CLKGATE_MASK 0x40000000u +#define GIS_CTRL_TOG_CLKGATE_SHIFT 30 +#define GIS_CTRL_TOG_SFTRST_MASK 0x80000000u +#define GIS_CTRL_TOG_SFTRST_SHIFT 31 +/* CONFIG0 Bit Fields */ +#define GIS_CONFIG0_CH0_MAPPING_MASK 0x7u +#define GIS_CONFIG0_CH0_MAPPING_SHIFT 0 +#define GIS_CONFIG0_CH0_MAPPING(x) (((uint32_t)(((uint32_t)(x))<CNTR) +#define GPC_PGR_REG(base) ((base)->PGR) +#define GPC_IMR1_REG(base) ((base)->IMR1) +#define GPC_IMR2_REG(base) ((base)->IMR2) +#define GPC_IMR3_REG(base) ((base)->IMR3) +#define GPC_IMR4_REG(base) ((base)->IMR4) +#define GPC_ISR1_REG(base) ((base)->ISR1) +#define GPC_ISR2_REG(base) ((base)->ISR2) +#define GPC_ISR3_REG(base) ((base)->ISR3) +#define GPC_ISR4_REG(base) ((base)->ISR4) +#define GPC_A9_LPSR_REG(base) ((base)->A9_LPSR) +#define GPC_M4_LPSR_REG(base) ((base)->M4_LPSR) +#define GPC_DR_REG(base) ((base)->DR) + +/*! + * @} + */ /* end of group GPC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/* CNTR Bit Fields */ +#define GPC_CNTR_gpu_vpu_pdn_req_MASK 0x1u +#define GPC_CNTR_gpu_vpu_pdn_req_SHIFT 0 +#define GPC_CNTR_gpu_vpu_pup_req_MASK 0x2u +#define GPC_CNTR_gpu_vpu_pup_req_SHIFT 1 +#define GPC_CNTR_MEGA_PDN_REQ_MASK 0x4u +#define GPC_CNTR_MEGA_PDN_REQ_SHIFT 2 +#define GPC_CNTR_MEGA_PUP_REQ_MASK 0x8u +#define GPC_CNTR_MEGA_PUP_REQ_SHIFT 3 +#define GPC_CNTR_DISPLAY_PDN_REQ_MASK 0x10u +#define GPC_CNTR_DISPLAY_PDN_REQ_SHIFT 4 +#define GPC_CNTR_DISPLAY_PUP_REQ_MASK 0x20u +#define GPC_CNTR_DISPLAY_PUP_REQ_SHIFT 5 +#define GPC_CNTR_PCIE_PHY_PDN_REQ_MASK 0x40u +#define GPC_CNTR_PCIE_PHY_PDN_REQ_SHIFT 6 +#define GPC_CNTR_PCIE_PHY_PUP_REQ_MASK 0x80u +#define GPC_CNTR_PCIE_PHY_PUP_REQ_SHIFT 7 +#define GPC_CNTR_DVFS0CR_MASK 0x10000u +#define GPC_CNTR_DVFS0CR_SHIFT 16 +#define GPC_CNTR_VADC_ANALOG_OFF_MASK 0x20000u +#define GPC_CNTR_VADC_ANALOG_OFF_SHIFT 17 +#define GPC_CNTR_VADC_EXT_PWD_N_MASK 0x40000u +#define GPC_CNTR_VADC_EXT_PWD_N_SHIFT 18 +#define GPC_CNTR_GPCIRQM_MASK 0x200000u +#define GPC_CNTR_GPCIRQM_SHIFT 21 +#define GPC_CNTR_L2_PGE_MASK 0x400000u +#define GPC_CNTR_L2_PGE_SHIFT 22 +/* PGR Bit Fields */ +#define GPC_PGR_DRCIC_MASK 0x60000000u +#define GPC_PGR_DRCIC_SHIFT 29 +#define GPC_PGR_DRCIC(x) (((uint32_t)(((uint32_t)(x))<DR) +#define GPIO_GDIR_REG(base) ((base)->GDIR) +#define GPIO_PSR_REG(base) ((base)->PSR) +#define GPIO_ICR1_REG(base) ((base)->ICR1) +#define GPIO_ICR2_REG(base) ((base)->ICR2) +#define GPIO_IMR_REG(base) ((base)->IMR) +#define GPIO_ISR_REG(base) ((base)->ISR) +#define GPIO_EDGE_SEL_REG(base) ((base)->EDGE_SEL) + +/*! + * @} + */ /* end of group GPIO_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* DR Bit Fields */ +#define GPIO_DR_DR_MASK 0xFFFFFFFFu +#define GPIO_DR_DR_SHIFT 0 +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x))<CTRL0) +#define GPMI_CTRL0_SET_REG(base) ((base)->CTRL0_SET) +#define GPMI_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) +#define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) +#define GPMI_COMPARE_REG(base) ((base)->COMPARE) +#define GPMI_ECCCTRL_REG(base) ((base)->ECCCTRL) +#define GPMI_ECCCTRL_SET_REG(base) ((base)->ECCCTRL_SET) +#define GPMI_ECCCTRL_CLR_REG(base) ((base)->ECCCTRL_CLR) +#define GPMI_ECCCTRL_TOG_REG(base) ((base)->ECCCTRL_TOG) +#define GPMI_ECCCOUNT_REG(base) ((base)->ECCCOUNT) +#define GPMI_PAYLOAD_REG(base) ((base)->PAYLOAD) +#define GPMI_AUXILIARY_REG(base) ((base)->AUXILIARY) +#define GPMI_CTRL1_REG(base) ((base)->CTRL1) +#define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define GPMI_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define GPMI_TIMING0_REG(base) ((base)->TIMING0) +#define GPMI_TIMING1_REG(base) ((base)->TIMING1) +#define GPMI_TIMING2_REG(base) ((base)->TIMING2) +#define GPMI_DATA_REG(base) ((base)->DATA) +#define GPMI_STAT_REG(base) ((base)->STAT) +#define GPMI_DEBUG_REG(base) ((base)->DEBUG) +#define GPMI_VERSION_REG(base) ((base)->VERSION) +#define GPMI_DEBUG2_REG(base) ((base)->DEBUG2) +#define GPMI_DEBUG3_REG(base) ((base)->DEBUG3) +#define GPMI_READ_DDR_DLL_CTRL_REG(base) ((base)->READ_DDR_DLL_CTRL) +#define GPMI_WRITE_DDR_DLL_CTRL_REG(base) ((base)->WRITE_DDR_DLL_CTRL) +#define GPMI_READ_DDR_DLL_STS_REG(base) ((base)->READ_DDR_DLL_STS) +#define GPMI_WRITE_DDR_DLL_STS_REG(base) ((base)->WRITE_DDR_DLL_STS) + +/*! + * @} + */ /* end of group GPMI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/* CTRL0 Bit Fields */ +#define GPMI_CTRL0_XFER_COUNT_MASK 0xFFFFu +#define GPMI_CTRL0_XFER_COUNT_SHIFT 0 +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<CR) +#define GPT_PR_REG(base) ((base)->PR) +#define GPT_SR_REG(base) ((base)->SR) +#define GPT_IR_REG(base) ((base)->IR) +#define GPT_OCR1_REG(base) ((base)->OCR1) +#define GPT_OCR2_REG(base) ((base)->OCR2) +#define GPT_OCR3_REG(base) ((base)->OCR3) +#define GPT_ICR1_REG(base) ((base)->ICR1) +#define GPT_ICR2_REG(base) ((base)->ICR2) +#define GPT_CNT_REG(base) ((base)->CNT) + +/*! + * @} + */ /* end of group GPT_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define GPT_CR_EN_MASK 0x1u +#define GPT_CR_EN_SHIFT 0 +#define GPT_CR_ENMOD_MASK 0x2u +#define GPT_CR_ENMOD_SHIFT 1 +#define GPT_CR_DBGEN_MASK 0x4u +#define GPT_CR_DBGEN_SHIFT 2 +#define GPT_CR_WAITEN_MASK 0x8u +#define GPT_CR_WAITEN_SHIFT 3 +#define GPT_CR_DOZEEN_MASK 0x10u +#define GPT_CR_DOZEEN_SHIFT 4 +#define GPT_CR_STOPEN_MASK 0x20u +#define GPT_CR_STOPEN_SHIFT 5 +#define GPT_CR_CLKSRC_MASK 0x1C0u +#define GPT_CR_CLKSRC_SHIFT 6 +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<IADR) +#define I2C_IFDR_REG(base) ((base)->IFDR) +#define I2C_I2CR_REG(base) ((base)->I2CR) +#define I2C_I2SR_REG(base) ((base)->I2SR) +#define I2C_I2DR_REG(base) ((base)->I2DR) + +/*! + * @} + */ /* end of group I2C_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* IADR Bit Fields */ +#define I2C_IADR_ADR_MASK 0xFEu +#define I2C_IADR_ADR_SHIFT 1 +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x))<TCSR) +#define I2S_TCR1_REG(base) ((base)->TCR1) +#define I2S_TCR2_REG(base) ((base)->TCR2) +#define I2S_TCR3_REG(base) ((base)->TCR3) +#define I2S_TCR4_REG(base) ((base)->TCR4) +#define I2S_TCR5_REG(base) ((base)->TCR5) +#define I2S_TDR_REG(base,index) ((base)->TDR[index]) +#define I2S_TFR_REG(base,index) ((base)->TFR[index]) +#define I2S_TMR_REG(base) ((base)->TMR) +#define I2S_RCSR_REG(base) ((base)->RCSR) +#define I2S_RCR1_REG(base) ((base)->RCR1) +#define I2S_RCR2_REG(base) ((base)->RCR2) +#define I2S_RCR3_REG(base) ((base)->RCR3) +#define I2S_RCR4_REG(base) ((base)->RCR4) +#define I2S_RCR5_REG(base) ((base)->RCR5) +#define I2S_RDR_REG(base,index) ((base)->RDR[index]) +#define I2S_RFR_REG(base,index) ((base)->RFR[index]) +#define I2S_RMR_REG(base) ((base)->RMR) + +/*! + * @} + */ /* end of group I2S_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x1Fu +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<SW_MUX_CTL_PAD_GPIO1_IO00) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_HSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_MCLK) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_PIXCLK) +#define IOMUXC_SW_MUX_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_CSI_VSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_MDIO) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_COL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_CRS) +#define IOMUXC_SW_MUX_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_RX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET2_TX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL0) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL1) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL2) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL3) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_COL4) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW0) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW1) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW2) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW3) +#define IOMUXC_SW_MUX_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_MUX_CTL_PAD_KEY_ROW4) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA08) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA09) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA10) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA11) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA12) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA13) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA14) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA15) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA16) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA17) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA18) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA19) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA20) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA21) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA22) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_DATA23) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_ENABLE) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_HSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_RESET) +#define IOMUXC_SW_MUX_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD1_VSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_ALE) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE0_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CE1_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_CLE) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_RE_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_READY_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WE_B) +#define IOMUXC_SW_MUX_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_MUX_CTL_PAD_NAND_WP_B) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_DQS) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS0_B) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1A_SS1_B) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_DQS) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS0_B) +#define IOMUXC_SW_MUX_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_MUX_CTL_PAD_QSPI1B_SS1_B) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD0) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD1) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD2) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RD3) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_RXC) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD0) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD1) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD2) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TD3) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII1_TXC) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD0) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD1) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD2) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RD3) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_RXC) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD0) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD1) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD2) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TD3) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_RGMII2_TXC) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA4) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA5) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA6) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_DATA7) +#define IOMUXC_SW_MUX_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD4_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_USB_H_STROBE) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR00_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR00) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR01_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR01) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR02_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR02) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR03_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR03) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR04_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR04) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR05_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR05) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR06_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR06) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR07_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR07) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR08_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR08) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR09_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR09) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR10_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR10) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR11_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR11) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR12_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR12) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR13_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR13) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR14_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR14) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ADDR15_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ADDR15) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM1) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM2) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM3_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_DQM3) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RAS_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CAS_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS0_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_CS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_CS1_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDWE_B_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDWE_B) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_ODT1) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA1) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDBA2) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE0_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE0) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCKE1_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCKE1) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDCLK0_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS0_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS1_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS2_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS2_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS3_P_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_SDQS3_P) +#define IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_DRAM_RESET) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_HSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_MCLK) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_PIXCLK_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_PIXCLK) +#define IOMUXC_SW_PAD_CTL_PAD_CSI_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_CSI_VSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_MDIO_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_MDIO) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET2_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_COL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET2_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_CRS) +#define IOMUXC_SW_PAD_CTL_PAD_ENET2_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_RX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET2_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET2_TX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL0) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL1) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL2) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL3) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_COL4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_COL4) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW0_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW0) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW1_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW1) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW2_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW2) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW3_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW3) +#define IOMUXC_SW_PAD_CTL_PAD_KEY_ROW4_REG(base) ((base)->SW_PAD_CTL_PAD_KEY_ROW4) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA08) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA09) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA10) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA11) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA12) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA13) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA14) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA15) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA16) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA17) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA18) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA19) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA20) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA21) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA22) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_DATA23) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_ENABLE) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_HSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_RESET) +#define IOMUXC_SW_PAD_CTL_PAD_LCD1_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD1_VSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_ALE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_ALE) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_CE0_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE0_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_CE1_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CE1_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_CLE_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_CLE) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_RE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_RE_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_READY_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_READY_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_WE_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WE_B) +#define IOMUXC_SW_PAD_CTL_PAD_NAND_WP_B_REG(base) ((base)->SW_PAD_CTL_PAD_NAND_WP_B) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_DQS) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS0_B) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1A_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1A_SS1_B) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_DQS_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_DQS) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS0_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS0_B) +#define IOMUXC_SW_PAD_CTL_PAD_QSPI1B_SS1_B_REG(base) ((base)->SW_PAD_CTL_PAD_QSPI1B_SS1_B) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD0) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD1) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD2) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RD3) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_RXC) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD0) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD1) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD2) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TD3) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII1_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII1_TXC) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD0) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD1) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD2) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RD3) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_RXC) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD0) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD1) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD2) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TD3) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_RGMII2_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_RGMII2_TXC) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA4) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA5) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA6) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_DATA7) +#define IOMUXC_SW_PAD_CTL_PAD_SD4_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD4_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_USB_H_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_USB_H_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_USB_H_STROBE) +#define IOMUXC_SW_PAD_CTL_GRP_ADDDS_REG(base) ((base)->SW_PAD_CTL_GRP_ADDDS) +#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL_REG(base) ((base)->SW_PAD_CTL_GRP_DDRMODE_CTL) +#define IOMUXC_SW_PAD_CTL_GRP_DDRPKE_REG(base) ((base)->SW_PAD_CTL_GRP_DDRPKE) +#define IOMUXC_SW_PAD_CTL_GRP_DDRPK_REG(base) ((base)->SW_PAD_CTL_GRP_DDRPK) +#define IOMUXC_SW_PAD_CTL_GRP_DDRHYS_REG(base) ((base)->SW_PAD_CTL_GRP_DDRHYS) +#define IOMUXC_SW_PAD_CTL_GRP_DDRMODE_REG(base) ((base)->SW_PAD_CTL_GRP_DDRMODE) +#define IOMUXC_SW_PAD_CTL_GRP_B0DS_REG(base) ((base)->SW_PAD_CTL_GRP_B0DS) +#define IOMUXC_SW_PAD_CTL_GRP_B1DS_REG(base) ((base)->SW_PAD_CTL_GRP_B1DS) +#define IOMUXC_SW_PAD_CTL_GRP_CTLDS_REG(base) ((base)->SW_PAD_CTL_GRP_CTLDS) +#define IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE_REG(base) ((base)->SW_PAD_CTL_GRP_DDR_TYPE) +#define IOMUXC_SW_PAD_CTL_GRP_B2DS_REG(base) ((base)->SW_PAD_CTL_GRP_B2DS) +#define IOMUXC_SW_PAD_CTL_GRP_B3DS_REG(base) ((base)->SW_PAD_CTL_GRP_B3DS) +#define IOMUXC_ANATOP_USB_OTG_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_OTG_ID_SELECT_INPUT) +#define IOMUXC_ANATOP_USB_UH1_ID_SELECT_INPUT_REG(base) ((base)->ANATOP_USB_UH1_ID_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DA_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_DB_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_RXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P3_INPUT_TXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DA_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_DB_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_RXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P4_INPUT_TXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DA_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_DB_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_RXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P5_INPUT_TXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DA_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_DB_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_RXFS_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXCLK_AMX_SELECT_INPUT) +#define IOMUXC_AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT_REG(base) ((base)->AUDMUX_P6_INPUT_TXFS_AMX_SELECT_INPUT) +#define IOMUXC_CAN1_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN1_IPP_IND_CANRX_SELECT_INPUT) +#define IOMUXC_CAN2_IPP_IND_CANRX_SELECT_INPUT_REG(base) ((base)->CAN2_IPP_IND_CANRX_SELECT_INPUT) +#define IOMUXC_CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_VFUNCIONAL_READY_SELECT_INPUT) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_0_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_0) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_1_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_1) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_2_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_2) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_3_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_3) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_4_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_4) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_5_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_5) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_6_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_6) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_7_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_7) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_8_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_8) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_9_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_9) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_11_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_11) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_12_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_12) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_13_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_13) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_14_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_14) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_15_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_15) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_16_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_16) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_17_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_17) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_18_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_18) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_19_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_19) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_20_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_20) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_21_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_21) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_22_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_22) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_23_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_23) +#define IOMUXC_CSI1_IPP_CSI_D_SELECT_INPUT_10_REG(base) ((base)->CSI1_IPP_CSI_D_SELECT_INPUT_10) +#define IOMUXC_CSI1_IPP_CSI_HSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_HSYNC_SELECT_INPUT) +#define IOMUXC_CSI1_IPP_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_PIXCLK_SELECT_INPUT) +#define IOMUXC_CSI1_IPP_CSI_VSYNC_SELECT_INPUT_REG(base) ((base)->CSI1_IPP_CSI_VSYNC_SELECT_INPUT) +#define IOMUXC_CSI1_TVDECODER_IN_FIELD_SELECT_INPUT_REG(base) ((base)->CSI1_TVDECODER_IN_FIELD_SELECT_INPUT) +#define IOMUXC_ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI1_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI1_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI1_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI2_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI2_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI2_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI3_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI3_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI3_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI4_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI4_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI4_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_CSPI_CLK_IN_SELECT_INPUT) +#define IOMUXC_ECSPI5_IPP_IND_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI5_IPP_IND_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI5_IPP_IND_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0_REG(base) ((base)->ECSPI5_IPP_IND_SS_B_SELECT_INPUT_0) +#define IOMUXC_ENET1_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET1_IPG_CLK_RMII_SELECT_INPUT) +#define IOMUXC_ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_MDIO_SELECT_INPUT) +#define IOMUXC_ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET1_IPP_IND_MAC0_RXCLK_SELECT_INPUT) +#define IOMUXC_ENET2_IPG_CLK_RMII_SELECT_INPUT_REG(base) ((base)->ENET2_IPG_CLK_RMII_SELECT_INPUT) +#define IOMUXC_ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_MDIO_SELECT_INPUT) +#define IOMUXC_ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT_REG(base) ((base)->ENET2_IPP_IND_MAC0_RXCLK_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_FSR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FSR_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_FST_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_FST_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_HCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKR_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_HCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_HCKT_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SCKR_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKR_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SCKT_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SCKT_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO0_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO1_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO2_SDI3_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO3_SDI2_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO4_SDI1_SELECT_INPUT) +#define IOMUXC_ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT_REG(base) ((base)->ESAI_IPP_IND_SDO5_SDI0_SELECT_INPUT) +#define IOMUXC_I2C1_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SCL_IN_SELECT_INPUT) +#define IOMUXC_I2C1_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C1_IPP_SDA_IN_SELECT_INPUT) +#define IOMUXC_I2C2_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SCL_IN_SELECT_INPUT) +#define IOMUXC_I2C2_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C2_IPP_SDA_IN_SELECT_INPUT) +#define IOMUXC_I2C3_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SCL_IN_SELECT_INPUT) +#define IOMUXC_I2C3_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C3_IPP_SDA_IN_SELECT_INPUT) +#define IOMUXC_I2C4_IPP_SCL_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SCL_IN_SELECT_INPUT) +#define IOMUXC_I2C4_IPP_SDA_IN_SELECT_INPUT_REG(base) ((base)->I2C4_IPP_SDA_IN_SELECT_INPUT) +#define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_5) +#define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_6) +#define IOMUXC_KPP_IPP_IND_COL_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_COL_SELECT_INPUT_7) +#define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_5_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_5) +#define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_6_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_6) +#define IOMUXC_KPP_IPP_IND_ROW_SELECT_INPUT_7_REG(base) ((base)->KPP_IPP_IND_ROW_SELECT_INPUT_7) +#define IOMUXC_LCD1_BUSY_SELECT_INPUT_REG(base) ((base)->LCD1_BUSY_SELECT_INPUT) +#define IOMUXC_LCD2_BUSY_SELECT_INPUT_REG(base) ((base)->LCD2_BUSY_SELECT_INPUT) +#define IOMUXC_MLB_MLB_CLK_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_CLK_IN_SELECT_INPUT) +#define IOMUXC_MLB_MLB_DATA_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_DATA_IN_SELECT_INPUT) +#define IOMUXC_MLB_MLB_SIG_IN_SELECT_INPUT_REG(base) ((base)->MLB_MLB_SIG_IN_SELECT_INPUT) +#define IOMUXC_SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXBCLK_SELECT_INPUT) +#define IOMUXC_SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI1_IPP_IND_SAI_RXDATA_SELECT_INPUT_0) +#define IOMUXC_SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_RXSYNC_SELECT_INPUT) +#define IOMUXC_SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXBCLK_SELECT_INPUT) +#define IOMUXC_SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI1_IPP_IND_SAI_TXSYNC_SELECT_INPUT) +#define IOMUXC_SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXBCLK_SELECT_INPUT) +#define IOMUXC_SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0_REG(base) ((base)->SAI2_IPP_IND_SAI_RXDATA_SELECT_INPUT_0) +#define IOMUXC_SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_RXSYNC_SELECT_INPUT) +#define IOMUXC_SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXBCLK_SELECT_INPUT) +#define IOMUXC_SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT_REG(base) ((base)->SAI2_IPP_IND_SAI_TXSYNC_SELECT_INPUT) +#define IOMUXC_SDMA_EVENTS_SELECT_INPUT_14_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_14) +#define IOMUXC_SDMA_EVENTS_SELECT_INPUT_15_REG(base) ((base)->SDMA_EVENTS_SELECT_INPUT_15) +#define IOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT_REG(base) ((base)->SPDIF_SPDIF_IN1_SELECT_INPUT) +#define IOMUXC_SPDIF_TX_CLK2_SELECT_INPUT_REG(base) ((base)->SPDIF_TX_CLK2_SELECT_INPUT) +#define IOMUXC_UART1_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART1_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART1_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART2_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART2_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART2_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART3_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART3_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART3_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART4_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART4_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART4_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART5_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART5_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART5_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_UART6_IPP_UART_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RTS_B_SELECT_INPUT) +#define IOMUXC_UART6_IPP_UART_RXD_MUX_SELECT_INPUT_REG(base) ((base)->UART6_IPP_UART_RXD_MUX_SELECT_INPUT) +#define IOMUXC_USB_IPP_IND_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG2_OC_SELECT_INPUT) +#define IOMUXC_USB_IPP_IND_OTG_OC_SELECT_INPUT_REG(base) ((base)->USB_IPP_IND_OTG_OC_SELECT_INPUT) +#define IOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_CARD_DET_SELECT_INPUT) +#define IOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC1_IPP_WP_ON_SELECT_INPUT) +#define IOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_CARD_DET_SELECT_INPUT) +#define IOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC2_IPP_WP_ON_SELECT_INPUT) +#define IOMUXC_USDHC4_IPP_CARD_DET_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_CARD_DET_SELECT_INPUT) +#define IOMUXC_USDHC4_IPP_WP_ON_SELECT_INPUT_REG(base) ((base)->USDHC4_IPP_WP_ON_SELECT_INPUT) + +/*! + * @} + */ /* end of group IOMUXC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<GPR0) +#define IOMUXC_GPR_GPR1_REG(base) ((base)->GPR1) +#define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2) +#define IOMUXC_GPR_GPR3_REG(base) ((base)->GPR3) +#define IOMUXC_GPR_GPR4_REG(base) ((base)->GPR4) +#define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5) +#define IOMUXC_GPR_GPR6_REG(base) ((base)->GPR6) +#define IOMUXC_GPR_GPR7_REG(base) ((base)->GPR7) +#define IOMUXC_GPR_GPR8_REG(base) ((base)->GPR8) +#define IOMUXC_GPR_GPR9_REG(base) ((base)->GPR9) +#define IOMUXC_GPR_GPR10_REG(base) ((base)->GPR10) +#define IOMUXC_GPR_GPR11_REG(base) ((base)->GPR11) +#define IOMUXC_GPR_GPR12_REG(base) ((base)->GPR12) +#define IOMUXC_GPR_GPR13_REG(base) ((base)->GPR13) + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/* GPR0 Bit Fields */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_MASK 0x80u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL7_SHIFT 7 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_MASK 0x100u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL8_SHIFT 8 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_MASK 0x200u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL9_SHIFT 9 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_MASK 0x400u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL10_SHIFT 10 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_MASK 0x800u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL11_SHIFT 11 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_MASK 0x1000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL12_SHIFT 12 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_MASK 0x2000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL13_SHIFT 13 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_MASK 0x4000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL14_SHIFT 14 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_MASK 0x8000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL15_SHIFT 15 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_MASK 0x10000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL16_SHIFT 16 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_MASK 0x20000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL17_SHIFT 17 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_MASK 0x40000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL18_SHIFT 18 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_MASK 0x80000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL19_SHIFT 19 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_MASK 0x100000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL20_SHIFT 20 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_MASK 0x200000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL21_SHIFT 21 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_MASK 0x400000u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL22_SHIFT 22 +/* GPR1 Bit Fields */ +#define IOMUXC_GPR_GPR1_ACT_CS0_MASK 0x1u +#define IOMUXC_GPR_GPR1_ACT_CS0_SHIFT 0 +#define IOMUXC_GPR_GPR1_ADDRS0_MASK 0x6u +#define IOMUXC_GPR_GPR1_ADDRS0_SHIFT 1 +#define IOMUXC_GPR_GPR1_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<KPCR) +#define KPP_KPSR_REG(base) ((base)->KPSR) +#define KPP_KDDR_REG(base) ((base)->KDDR) +#define KPP_KPDR_REG(base) ((base)->KPDR) + +/*! + * @} + */ /* end of group KPP_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/* KPCR Bit Fields */ +#define KPP_KPCR_KRE_MASK 0xFFu +#define KPP_KPCR_KRE_SHIFT 0 +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x))<RL) +#define LCDIF_RL_SET_REG(base) ((base)->RL_SET) +#define LCDIF_RL_CLR_REG(base) ((base)->RL_CLR) +#define LCDIF_RL_TOG_REG(base) ((base)->RL_TOG) +#define LCDIF_CTRL1_REG(base) ((base)->CTRL1) +#define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define LCDIF_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define LCDIF_CTRL2_REG(base) ((base)->CTRL2) +#define LCDIF_CTRL2_SET_REG(base) ((base)->CTRL2_SET) +#define LCDIF_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) +#define LCDIF_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) +#define LCDIF_TRANSFER_COUNT_REG(base) ((base)->TRANSFER_COUNT) +#define LCDIF_CUR_BUF_REG(base) ((base)->CUR_BUF) +#define LCDIF_NEXT_BUF_REG(base) ((base)->NEXT_BUF) +#define LCDIF_TIMING_REG(base) ((base)->TIMING) +#define LCDIF_VDCTRL0_REG(base) ((base)->VDCTRL0) +#define LCDIF_VDCTRL0_SET_REG(base) ((base)->VDCTRL0_SET) +#define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR) +#define LCDIF_VDCTRL0_TOG_REG(base) ((base)->VDCTRL0_TOG) +#define LCDIF_VDCTRL1_REG(base) ((base)->VDCTRL1) +#define LCDIF_VDCTRL2_REG(base) ((base)->VDCTRL2) +#define LCDIF_VDCTRL3_REG(base) ((base)->VDCTRL3) +#define LCDIF_VDCTRL4_REG(base) ((base)->VDCTRL4) +#define LCDIF_DVICTRL0_REG(base) ((base)->DVICTRL0) +#define LCDIF_DVICTRL1_REG(base) ((base)->DVICTRL1) +#define LCDIF_DVICTRL2_REG(base) ((base)->DVICTRL2) +#define LCDIF_DVICTRL3_REG(base) ((base)->DVICTRL3) +#define LCDIF_DVICTRL4_REG(base) ((base)->DVICTRL4) +#define LCDIF_CSC_COEFF0_REG(base) ((base)->CSC_COEFF0) +#define LCDIF_CSC_COEFF1_REG(base) ((base)->CSC_COEFF1) +#define LCDIF_CSC_COEFF2_REG(base) ((base)->CSC_COEFF2) +#define LCDIF_CSC_COEFF3_REG(base) ((base)->CSC_COEFF3) +#define LCDIF_CSC_COEFF4_REG(base) ((base)->CSC_COEFF4) +#define LCDIF_CSC_OFFSET_REG(base) ((base)->CSC_OFFSET) +#define LCDIF_CSC_LIMIT_REG(base) ((base)->CSC_LIMIT) +#define LCDIF_DATA_REG(base) ((base)->DATA) +#define LCDIF_BM_ERROR_STAT_REG(base) ((base)->BM_ERROR_STAT) +#define LCDIF_CRC_STAT_REG(base) ((base)->CRC_STAT) +#define LCDIF_STAT_REG(base) ((base)->STAT) +#define LCDIF_VERSION_REG(base) ((base)->VERSION) +#define LCDIF_DEBUG0_REG(base) ((base)->DEBUG0) +#define LCDIF_DEBUG1_REG(base) ((base)->DEBUG1) +#define LCDIF_DEBUG2_REG(base) ((base)->DEBUG2) +#define LCDIF_THRES_REG(base) ((base)->THRES) +#define LCDIF_AS_CTRL_REG(base) ((base)->AS_CTRL) +#define LCDIF_AS_BUF_REG(base) ((base)->AS_BUF) +#define LCDIF_AS_NEXT_BUF_REG(base) ((base)->AS_NEXT_BUF) +#define LCDIF_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) +#define LCDIF_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) +#define LCDIF_SYNC_DELAY_REG(base) ((base)->SYNC_DELAY) +#define LCDIF_DEBUG3_REG(base) ((base)->DEBUG3) +#define LCDIF_DEBUG4_REG(base) ((base)->DEBUG4) +#define LCDIF_DEBUG5_REG(base) ((base)->DEBUG5) + +/*! + * @} + */ /* end of group LCDIF_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/* RL Bit Fields */ +#define LCDIF_RL_RUN_MASK 0x1u +#define LCDIF_RL_RUN_SHIFT 0 +#define LCDIF_RL_DATA_FORMAT_24_BIT_MASK 0x2u +#define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT 1 +#define LCDIF_RL_DATA_FORMAT_18_BIT_MASK 0x4u +#define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT 2 +#define LCDIF_RL_DATA_FORMAT_16_BIT_MASK 0x8u +#define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT 3 +#define LCDIF_RL_RSRVD0_MASK 0x10u +#define LCDIF_RL_RSRVD0_SHIFT 4 +#define LCDIF_RL_MASTER_MASK 0x20u +#define LCDIF_RL_MASTER_SHIFT 5 +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK 0x40u +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT 6 +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK 0x80u +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT 7 +#define LCDIF_RL_WORD_LENGTH_MASK 0x300u +#define LCDIF_RL_WORD_LENGTH_SHIFT 8 +#define LCDIF_RL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<CTRL) + +/*! + * @} + */ /* end of group LDB_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- LDB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LDB_Register_Masks LDB Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define LDB_CTRL_ch0_mode_MASK 0x3u +#define LDB_CTRL_ch0_mode_SHIFT 0 +#define LDB_CTRL_ch0_mode(x) (((uint32_t)(((uint32_t)(x))<PCCCR) +#define LMEM_PCCLCR_REG(base) ((base)->PCCLCR) +#define LMEM_PCCSAR_REG(base) ((base)->PCCSAR) +#define LMEM_PCCCVR_REG(base) ((base)->PCCCVR) +#define LMEM_PSCCR_REG(base) ((base)->PSCCR) +#define LMEM_PSCLCR_REG(base) ((base)->PSCLCR) +#define LMEM_PSCSAR_REG(base) ((base)->PSCSAR) +#define LMEM_PSCCVR_REG(base) ((base)->PSCCVR) + +/*! + * @} + */ /* end of group LMEM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- LMEM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Register_Masks LMEM Register Masks + * @{ + */ + +/* PCCCR Bit Fields */ +#define LMEM_PCCCR_ENCACHE_MASK 0x1u +#define LMEM_PCCCR_ENCACHE_SHIFT 0 +#define LMEM_PCCCR_ENWRBUF_MASK 0x2u +#define LMEM_PCCCR_ENWRBUF_SHIFT 1 +#define LMEM_PCCCR_PCCR2_MASK 0x4u +#define LMEM_PCCCR_PCCR2_SHIFT 2 +#define LMEM_PCCCR_PCCR3_MASK 0x8u +#define LMEM_PCCCR_PCCR3_SHIFT 3 +#define LMEM_PCCCR_INVW0_MASK 0x1000000u +#define LMEM_PCCCR_INVW0_SHIFT 24 +#define LMEM_PCCCR_PUSHW0_MASK 0x2000000u +#define LMEM_PCCCR_PUSHW0_SHIFT 25 +#define LMEM_PCCCR_INVW1_MASK 0x4000000u +#define LMEM_PCCCR_INVW1_SHIFT 26 +#define LMEM_PCCCR_PUSHW1_MASK 0x8000000u +#define LMEM_PCCCR_PUSHW1_SHIFT 27 +#define LMEM_PCCCR_GO_MASK 0x80000000u +#define LMEM_PCCCR_GO_SHIFT 31 +/* PCCLCR Bit Fields */ +#define LMEM_PCCLCR_LGO_MASK 0x1u +#define LMEM_PCCLCR_LGO_SHIFT 0 +#define LMEM_PCCLCR_CACHEADDR_MASK 0x1FFCu +#define LMEM_PCCLCR_CACHEADDR_SHIFT 2 +#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<PLASC) +#define MCM_PLAMC_REG(base) ((base)->PLAMC) +#define MCM_FADR_REG(base) ((base)->FADR) +#define MCM_FATR_REG(base) ((base)->FATR) +#define MCM_FDR_REG(base) ((base)->FDR) + +/*! + * @} + */ /* end of group MCM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/* PLASC Bit Fields */ +#define MCM_PLASC_ASC_MASK 0xFFu +#define MCM_PLASC_ASC_SHIFT 0 +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<MLBC0) +#define MLB_MS0_REG(base) ((base)->MS0) +#define MLB_MLBPC2_REG(base) ((base)->MLBPC2.MLBPC2) +#define MLB_MS1_REG(base) ((base)->MS1) +#define MLB_MSS_REG(base) ((base)->MSS) +#define MLB_MSD_REG(base) ((base)->MSD) +#define MLB_MIEN_REG(base) ((base)->MIEN) +#define MLB_MLBC1_REG(base) ((base)->MLBC1) +#define MLB_HCTL_REG(base) ((base)->HCTL) +#define MLB_HCMR0_REG(base) ((base)->HCMR0) +#define MLB_HCMR1_REG(base) ((base)->HCMR1) +#define MLB_HCER0_REG(base) ((base)->HCER0) +#define MLB_HCER1_REG(base) ((base)->HCER1) +#define MLB_HCBR0_REG(base) ((base)->HCBR0) +#define MLB_HCBR1_REG(base) ((base)->HCBR1) +#define MLB_MDAT0_REG(base) ((base)->MDAT0) +#define MLB_MDAT1_REG(base) ((base)->MDAT1) +#define MLB_MDAT2_REG(base) ((base)->MDAT2) +#define MLB_MDAT3_REG(base) ((base)->MDAT3) +#define MLB_MDWE0_REG(base) ((base)->MDWE0) +#define MLB_MDWE1_REG(base) ((base)->MDWE1) +#define MLB_MDWE2_REG(base) ((base)->MDWE2) +#define MLB_MDWE3_REG(base) ((base)->MDWE3) +#define MLB_MCTL_REG(base) ((base)->MCTL) +#define MLB_MADR_REG(base) ((base)->MADR) +#define MLB_ACTL_REG(base) ((base)->ACTL) +#define MLB_ACSR0_REG(base) ((base)->ACSR0) +#define MLB_ACSR1_REG(base) ((base)->ACSR1) +#define MLB_ACMR0_REG(base) ((base)->ACMR0) +#define MLB_ACMR1_REG(base) ((base)->ACMR1) + +/*! + * @} + */ /* end of group MLB_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- MLB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MLB_Register_Masks MLB Register Masks + * @{ + */ + +/* MLBC0 Bit Fields */ +#define MLB_MLBC0_MLBEN_MASK 0x1u +#define MLB_MLBC0_MLBEN_SHIFT 0 +#define MLB_MLBC0_MLBCLK_2_0_MASK 0x1Cu +#define MLB_MLBC0_MLBCLK_2_0_SHIFT 2 +#define MLB_MLBC0_MLBCLK_2_0(x) (((uint32_t)(((uint32_t)(x))<MDCTL) +#define MMDC_MDPDC_REG(base) ((base)->MDPDC) +#define MMDC_MDOTC_REG(base) ((base)->MDOTC) +#define MMDC_MDCFG0_REG(base) ((base)->MDCFG0) +#define MMDC_MDCFG1_REG(base) ((base)->MDCFG1) +#define MMDC_MDCFG2_REG(base) ((base)->MDCFG2) +#define MMDC_MDMISC_REG(base) ((base)->MDMISC) +#define MMDC_MDSCR_REG(base) ((base)->MDSCR) +#define MMDC_MDREF_REG(base) ((base)->MDREF) +#define MMDC_MDRWD_REG(base) ((base)->MDRWD) +#define MMDC_MDOR_REG(base) ((base)->MDOR) +#define MMDC_MDMRR_REG(base) ((base)->MDMRR) +#define MMDC_MDCFG3LP_REG(base) ((base)->MDCFG3LP) +#define MMDC_MDMR4_REG(base) ((base)->MDMR4) +#define MMDC_MDASP_REG(base) ((base)->MDASP) +#define MMDC_MAARCR_REG(base) ((base)->MAARCR) +#define MMDC_MAPSR_REG(base) ((base)->MAPSR) +#define MMDC_MAEXIDR0_REG(base) ((base)->MAEXIDR0) +#define MMDC_MAEXIDR1_REG(base) ((base)->MAEXIDR1) +#define MMDC_MADPCR0_REG(base) ((base)->MADPCR0) +#define MMDC_MADPCR1_REG(base) ((base)->MADPCR1) +#define MMDC_MADPSR0_REG(base) ((base)->MADPSR0) +#define MMDC_MADPSR1_REG(base) ((base)->MADPSR1) +#define MMDC_MADPSR2_REG(base) ((base)->MADPSR2) +#define MMDC_MADPSR3_REG(base) ((base)->MADPSR3) +#define MMDC_MADPSR4_REG(base) ((base)->MADPSR4) +#define MMDC_MADPSR5_REG(base) ((base)->MADPSR5) +#define MMDC_MASBS0_REG(base) ((base)->MASBS0) +#define MMDC_MASBS1_REG(base) ((base)->MASBS1) +#define MMDC_MAGENP_REG(base) ((base)->MAGENP) +#define MMDC_MPZQHWCTRL_REG(base) ((base)->MPZQHWCTRL) +#define MMDC_MPZQSWCTRL_REG(base) ((base)->MPZQSWCTRL) +#define MMDC_MPWLGCR_REG(base) ((base)->MPWLGCR) +#define MMDC_MPWLDECTRL0_REG(base) ((base)->MPWLDECTRL0) +#define MMDC_MPWLDECTRL1_REG(base) ((base)->MPWLDECTRL1) +#define MMDC_MPWLDLST_REG(base) ((base)->MPWLDLST) +#define MMDC_MPODTCTRL_REG(base) ((base)->MPODTCTRL) +#define MMDC_MPRDDQBY0DL_REG(base) ((base)->MPRDDQBY0DL) +#define MMDC_MPRDDQBY1DL_REG(base) ((base)->MPRDDQBY1DL) +#define MMDC_MPRDDQBY2DL_REG(base) ((base)->MPRDDQBY2DL) +#define MMDC_MPRDDQBY3DL_REG(base) ((base)->MPRDDQBY3DL) +#define MMDC_MPWRDQBY0DL_REG(base) ((base)->MPWRDQBY0DL) +#define MMDC_MPWRDQBY1DL_REG(base) ((base)->MPWRDQBY1DL) +#define MMDC_MPWRDQBY2DL_REG(base) ((base)->MPWRDQBY2DL) +#define MMDC_MPWRDQBY3DL_REG(base) ((base)->MPWRDQBY3DL) +#define MMDC_MPDGCTRL0_REG(base) ((base)->MPDGCTRL0) +#define MMDC_MPDGCTRL1_REG(base) ((base)->MPDGCTRL1) +#define MMDC_MPDGDLST0_REG(base) ((base)->MPDGDLST0) +#define MMDC_MPRDDLCTL_REG(base) ((base)->MPRDDLCTL) +#define MMDC_MPRDDLST_REG(base) ((base)->MPRDDLST) +#define MMDC_MPWRDLCTL_REG(base) ((base)->MPWRDLCTL) +#define MMDC_MPWRDLST_REG(base) ((base)->MPWRDLST) +#define MMDC_MPSDCTRL_REG(base) ((base)->MPSDCTRL) +#define MMDC_MPZQLP2CTL_REG(base) ((base)->MPZQLP2CTL) +#define MMDC_MPRDDLHWCTL_REG(base) ((base)->MPRDDLHWCTL) +#define MMDC_MPWRDLHWCTL_REG(base) ((base)->MPWRDLHWCTL) +#define MMDC_MPRDDLHWST0_REG(base) ((base)->MPRDDLHWST0) +#define MMDC_MPRDDLHWST1_REG(base) ((base)->MPRDDLHWST1) +#define MMDC_MPWRDLHWST0_REG(base) ((base)->MPWRDLHWST0) +#define MMDC_MPWRDLHWST1_REG(base) ((base)->MPWRDLHWST1) +#define MMDC_MPWLHWERR_REG(base) ((base)->MPWLHWERR) +#define MMDC_MPDGHWST0_REG(base) ((base)->MPDGHWST0) +#define MMDC_MPDGHWST1_REG(base) ((base)->MPDGHWST1) +#define MMDC_MPDGHWST2_REG(base) ((base)->MPDGHWST2) +#define MMDC_MPDGHWST3_REG(base) ((base)->MPDGHWST3) +#define MMDC_MPPDCMPR1_REG(base) ((base)->MPPDCMPR1) +#define MMDC_MPPDCMPR2_REG(base) ((base)->MPPDCMPR2) +#define MMDC_MPSWDAR0_REG(base) ((base)->MPSWDAR0) +#define MMDC_MPSWDRDR0_REG(base) ((base)->MPSWDRDR0) +#define MMDC_MPSWDRDR1_REG(base) ((base)->MPSWDRDR1) +#define MMDC_MPSWDRDR2_REG(base) ((base)->MPSWDRDR2) +#define MMDC_MPSWDRDR3_REG(base) ((base)->MPSWDRDR3) +#define MMDC_MPSWDRDR4_REG(base) ((base)->MPSWDRDR4) +#define MMDC_MPSWDRDR5_REG(base) ((base)->MPSWDRDR5) +#define MMDC_MPSWDRDR6_REG(base) ((base)->MPSWDRDR6) +#define MMDC_MPSWDRDR7_REG(base) ((base)->MPSWDRDR7) +#define MMDC_MPMUR0_REG(base) ((base)->MPMUR0) +#define MMDC_MPWRCADL_REG(base) ((base)->MPWRCADL) +#define MMDC_MPDCCR_REG(base) ((base)->MPDCCR) + +/*! + * @} + */ /* end of group MMDC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- MMDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MMDC_Register_Masks MMDC Register Masks + * @{ + */ + +/* MDCTL Bit Fields */ +#define MMDC_MDCTL_DSIZ_MASK 0x30000u +#define MMDC_MDCTL_DSIZ_SHIFT 16 +#define MMDC_MDCTL_DSIZ(x) (((uint32_t)(((uint32_t)(x))<TR[index]) +#define MU_TR_COUNT 4 +#define MU_RR_REG(base,index) ((base)->RR[index]) +#define MU_RR_COUNT 4 +#define MU_SR_REG(base) ((base)->SR) +#define MU_CR_REG(base) ((base)->CR) + +/*! + * @} + */ /* end of group MU_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ + +/* TR Bit Fields */ +#define MU_TR_TR0_MASK 0xFFFFFFFFu +#define MU_TR_TR0_SHIFT 0 +#define MU_TR_TR0(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define OCOTP_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define OCOTP_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define OCOTP_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define OCOTP_TIMING_REG(base) ((base)->TIMING) +#define OCOTP_DATA_REG(base) ((base)->DATA) +#define OCOTP_READ_CTRL_REG(base) ((base)->READ_CTRL) +#define OCOTP_READ_FUSE_DATA_REG(base) ((base)->READ_FUSE_DATA) +#define OCOTP_SW_STICKY_REG(base) ((base)->SW_STICKY) +#define OCOTP_SCS_REG(base) ((base)->SCS) +#define OCOTP_SCS_SET_REG(base) ((base)->SCS_SET) +#define OCOTP_SCS_CLR_REG(base) ((base)->SCS_CLR) +#define OCOTP_SCS_TOG_REG(base) ((base)->SCS_TOG) +#define OCOTP_VERSION_REG(base) ((base)->VERSION) +#define OCOTP_LOCK_REG(base) ((base)->LOCK) +#define OCOTP_CFG0_REG(base) ((base)->CFG0) +#define OCOTP_CFG1_REG(base) ((base)->CFG1) +#define OCOTP_CFG2_REG(base) ((base)->CFG2) +#define OCOTP_CFG3_REG(base) ((base)->CFG3) +#define OCOTP_CFG4_REG(base) ((base)->CFG4) +#define OCOTP_CFG5_REG(base) ((base)->CFG5) +#define OCOTP_CFG6_REG(base) ((base)->CFG6) +#define OCOTP_MEM0_REG(base) ((base)->MEM0) +#define OCOTP_MEM1_REG(base) ((base)->MEM1) +#define OCOTP_MEM2_REG(base) ((base)->MEM2) +#define OCOTP_MEM3_REG(base) ((base)->MEM3) +#define OCOTP_MEM4_REG(base) ((base)->MEM4) +#define OCOTP_ANA0_REG(base) ((base)->ANA0) +#define OCOTP_ANA1_REG(base) ((base)->ANA1) +#define OCOTP_ANA2_REG(base) ((base)->ANA2) +#define OCOTP_SRK0_REG(base) ((base)->SRK0) +#define OCOTP_SRK1_REG(base) ((base)->SRK1) +#define OCOTP_SRK2_REG(base) ((base)->SRK2) +#define OCOTP_SRK3_REG(base) ((base)->SRK3) +#define OCOTP_SRK4_REG(base) ((base)->SRK4) +#define OCOTP_SRK5_REG(base) ((base)->SRK5) +#define OCOTP_SRK6_REG(base) ((base)->SRK6) +#define OCOTP_SRK7_REG(base) ((base)->SRK7) +#define OCOTP_RESP0_REG(base) ((base)->RESP0) +#define OCOTP_HSJC_RESP1_REG(base) ((base)->HSJC_RESP1) +#define OCOTP_MAC0_REG(base) ((base)->MAC0) +#define OCOTP_MAC1_REG(base) ((base)->MAC1) +#define OCOTP_MAC2_REG(base) ((base)->MAC2) +#define OCOTP_GP1_REG(base) ((base)->GP1) +#define OCOTP_GP2_REG(base) ((base)->GP2) +#define OCOTP_MISC_CONF_REG(base) ((base)->MISC_CONF) +#define OCOTP_FIELD_RETURN_REG(base) ((base)->FIELD_RETURN) +#define OCOTP_SRK_REVOKE_REG(base) ((base)->SRK_REVOKE) +#define OCOTP_GP30_REG(base) ((base)->GP30) +#define OCOTP_GP31_REG(base) ((base)->GP31) +#define OCOTP_GP32_REG(base) ((base)->GP32) +#define OCOTP_GP33_REG(base) ((base)->GP33) +#define OCOTP_GP34_REG(base) ((base)->GP34) +#define OCOTP_GP35_REG(base) ((base)->GP35) +#define OCOTP_GP36_REG(base) ((base)->GP36) + +/*! + * @} + */ /* end of group OCOTP_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define OCOTP_CTRL_ADDR_MASK 0x7Fu +#define OCOTP_CTRL_ADDR_SHIFT 0 +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x))<PCIE_PHY_CTRL) +#define PGC_PCIE_PHY_PUPSCR_REG(base) ((base)->PCIE_PHY_PUPSCR) +#define PGC_PCIE_PHY_PDNSCR_REG(base) ((base)->PCIE_PHY_PDNSCR) +#define PGC_PCIE_PHY_SR_REG(base) ((base)->PCIE_PHY_SR) +#define PGC_MEGA_CTRL_REG(base) ((base)->MEGA_CTRL) +#define PGC_MEGA_PUPSCR_REG(base) ((base)->MEGA_PUPSCR) +#define PGC_MEGA_PDNSCR_REG(base) ((base)->MEGA_PDNSCR) +#define PGC_MEGA_SR_REG(base) ((base)->MEGA_SR) +#define PGC_DISPLAY_CTRL_REG(base) ((base)->DISPLAY_CTRL) +#define PGC_DISPLAY_PUPSCR_REG(base) ((base)->DISPLAY_PUPSCR) +#define PGC_DISPLAY_PDNSCR_REG(base) ((base)->DISPLAY_PDNSCR) +#define PGC_DISPLAY_SR_REG(base) ((base)->DISPLAY_SR) +#define PGC_GPU_CTRL_REG(base) ((base)->GPU_CTRL) +#define PGC_GPU_PUPSCR_REG(base) ((base)->GPU_PUPSCR) +#define PGC_GPU_PDNSCR_REG(base) ((base)->GPU_PDNSCR) +#define PGC_GPU_SR_REG(base) ((base)->GPU_SR) +#define PGC_CPU_CTRL_REG(base) ((base)->CPU_CTRL) +#define PGC_CPU_PUPSCR_REG(base) ((base)->CPU_PUPSCR) +#define PGC_CPU_PDNSCR_REG(base) ((base)->CPU_PDNSCR) +#define PGC_CPU_SR_REG(base) ((base)->CPU_SR) + +/*! + * @} + */ /* end of group PGC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PGC_Register_Masks PGC Register Masks + * @{ + */ + +/* PCIE_PHY_CTRL Bit Fields */ +#define PGC_PCIE_PHY_CTRL_PCR_MASK 0x1u +#define PGC_PCIE_PHY_CTRL_PCR_SHIFT 0 +/* PCIE_PHY_PUPSCR Bit Fields */ +#define PGC_PCIE_PHY_PUPSCR_SW_MASK 0x3Fu +#define PGC_PCIE_PHY_PUPSCR_SW_SHIFT 0 +#define PGC_PCIE_PHY_PUPSCR_SW(x) (((uint32_t)(((uint32_t)(x))<REG_1P1) +#define PMU_REG_3P0_REG(base) ((base)->REG_3P0) +#define PMU_REG_2P5_REG(base) ((base)->REG_2P5) +#define PMU_REG_CORE_REG(base) ((base)->REG_CORE) +#define PMU_MISC0_REG(base) ((base)->MISC0) +#define PMU_MISC1_REG(base) ((base)->MISC1) +#define PMU_MISC1_SET_REG(base) ((base)->MISC1_SET) +#define PMU_MISC1_CLR_REG(base) ((base)->MISC1_CLR) +#define PMU_MISC1_TOG_REG(base) ((base)->MISC1_TOG) +#define PMU_MISC2_REG(base) ((base)->MISC2) +#define PMU_MISC2_SET_REG(base) ((base)->MISC2_SET) +#define PMU_MISC2_CLR_REG(base) ((base)->MISC2_CLR) +#define PMU_MISC2_TOG_REG(base) ((base)->MISC2_TOG) +#define PMU_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) +#define PMU_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) +#define PMU_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) + +/*! + * @} + */ /* end of group PMU_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/* REG_1P1 Bit Fields */ +#define PMU_REG_1P1_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P1_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P1_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P1_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P1_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P1_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P1_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P1_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P1_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P1_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<PWMCR) +#define PWM_PWMSR_REG(base) ((base)->PWMSR) +#define PWM_PWMIR_REG(base) ((base)->PWMIR) +#define PWM_PWMSAR_REG(base) ((base)->PWMSAR) +#define PWM_PWMPR_REG(base) ((base)->PWMPR) +#define PWM_PWMCNR_REG(base) ((base)->PWMCNR) + +/*! + * @} + */ /* end of group PWM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/* PWMCR Bit Fields */ +#define PWM_PWMCR_EN_MASK 0x1u +#define PWM_PWMCR_EN_SHIFT 0 +#define PWM_PWMCR_REPEAT_MASK 0x6u +#define PWM_PWMCR_REPEAT_SHIFT 1 +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define PXP_STAT_REG(base) ((base)->STAT) +#define PXP_OUT_CTRL_REG(base) ((base)->OUT_CTRL) +#define PXP_OUT_BUF_REG(base) ((base)->OUT_BUF) +#define PXP_OUT_BUF2_REG(base) ((base)->OUT_BUF2) +#define PXP_OUT_PITCH_REG(base) ((base)->OUT_PITCH) +#define PXP_OUT_LRC_REG(base) ((base)->OUT_LRC) +#define PXP_OUT_PS_ULC_REG(base) ((base)->OUT_PS_ULC) +#define PXP_OUT_PS_LRC_REG(base) ((base)->OUT_PS_LRC) +#define PXP_OUT_AS_ULC_REG(base) ((base)->OUT_AS_ULC) +#define PXP_OUT_AS_LRC_REG(base) ((base)->OUT_AS_LRC) +#define PXP_PS_CTRL_REG(base) ((base)->PS_CTRL) +#define PXP_PS_BUF_REG(base) ((base)->PS_BUF) +#define PXP_PS_UBUF_REG(base) ((base)->PS_UBUF) +#define PXP_PS_VBUF_REG(base) ((base)->PS_VBUF) +#define PXP_PS_PITCH_REG(base) ((base)->PS_PITCH) +#define PXP_PS_BACKGROUND_REG(base) ((base)->PS_BACKGROUND) +#define PXP_PS_SCALE_REG(base) ((base)->PS_SCALE) +#define PXP_PS_OFFSET_REG(base) ((base)->PS_OFFSET) +#define PXP_PS_CLRKEYLOW_REG(base) ((base)->PS_CLRKEYLOW) +#define PXP_PS_CLRKEYHIGH_REG(base) ((base)->PS_CLRKEYHIGH) +#define PXP_AS_CTRL_REG(base) ((base)->AS_CTRL) +#define PXP_AS_BUF_REG(base) ((base)->AS_BUF) +#define PXP_AS_PITCH_REG(base) ((base)->AS_PITCH) +#define PXP_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) +#define PXP_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) +#define PXP_CSC1_COEF0_REG(base) ((base)->CSC1_COEF0) +#define PXP_CSC1_COEF1_REG(base) ((base)->CSC1_COEF1) +#define PXP_CSC1_COEF2_REG(base) ((base)->CSC1_COEF2) +#define PXP_CSC2_CTRL_REG(base) ((base)->CSC2_CTRL) +#define PXP_CSC2_COEF0_REG(base) ((base)->CSC2_COEF0) +#define PXP_CSC2_COEF1_REG(base) ((base)->CSC2_COEF1) +#define PXP_CSC2_COEF2_REG(base) ((base)->CSC2_COEF2) +#define PXP_CSC2_COEF3_REG(base) ((base)->CSC2_COEF3) +#define PXP_CSC2_COEF4_REG(base) ((base)->CSC2_COEF4) +#define PXP_CSC2_COEF5_REG(base) ((base)->CSC2_COEF5) +#define PXP_LUT_CTRL_REG(base) ((base)->LUT_CTRL) +#define PXP_LUT_ADDR_REG(base) ((base)->LUT_ADDR) +#define PXP_LUT_DATA_REG(base) ((base)->LUT_DATA) +#define PXP_LUT_EXTMEM_REG(base) ((base)->LUT_EXTMEM) +#define PXP_CFA_REG(base) ((base)->CFA) +#define PXP_HIST_CTRL_REG(base) ((base)->HIST_CTRL) +#define PXP_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) +#define PXP_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) +#define PXP_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) +#define PXP_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) +#define PXP_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) +#define PXP_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) +#define PXP_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) +#define PXP_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) +#define PXP_POWER_REG(base) ((base)->POWER) +#define PXP_NEXT_REG(base) ((base)->NEXT) + +/*! + * @} + */ /* end of group PXP_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define PXP_CTRL_ENABLE_MASK 0x1u +#define PXP_CTRL_ENABLE_SHIFT 0 +#define PXP_CTRL_IRQ_ENABLE_MASK 0x2u +#define PXP_CTRL_IRQ_ENABLE_SHIFT 1 +#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u +#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u +#define PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK 0x10u +#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT 4 +#define PXP_CTRL_RSVD0_MASK 0xE0u +#define PXP_CTRL_RSVD0_SHIFT 5 +#define PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define QuadSPI_IPCR_REG(base) ((base)->IPCR) +#define QuadSPI_FLSHCR_REG(base) ((base)->FLSHCR) +#define QuadSPI_BUF0CR_REG(base) ((base)->BUF0CR) +#define QuadSPI_BUF1CR_REG(base) ((base)->BUF1CR) +#define QuadSPI_BUF2CR_REG(base) ((base)->BUF2CR) +#define QuadSPI_BUF3CR_REG(base) ((base)->BUF3CR) +#define QuadSPI_BFGENCR_REG(base) ((base)->BFGENCR) +#define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND) +#define QuadSPI_BUF1IND_REG(base) ((base)->BUF1IND) +#define QuadSPI_BUF2IND_REG(base) ((base)->BUF2IND) +#define QuadSPI_SFAR_REG(base) ((base)->SFAR) +#define QuadSPI_SMPR_REG(base) ((base)->SMPR) +#define QuadSPI_RBSR_REG(base) ((base)->RBSR) +#define QuadSPI_RBCT_REG(base) ((base)->RBCT) +#define QuadSPI_TBSR_REG(base) ((base)->TBSR) +#define QuadSPI_TBDR_REG(base) ((base)->TBDR) +#define QuadSPI_SR_REG(base) ((base)->SR) +#define QuadSPI_FR_REG(base) ((base)->FR) +#define QuadSPI_RSER_REG(base) ((base)->RSER) +#define QuadSPI_SPNDST_REG(base) ((base)->SPNDST) +#define QuadSPI_SPTRCLR_REG(base) ((base)->SPTRCLR) +#define QuadSPI_SFA1AD_REG(base) ((base)->SFA1AD) +#define QuadSPI_SFA2AD_REG(base) ((base)->SFA2AD) +#define QuadSPI_SFB1AD_REG(base) ((base)->SFB1AD) +#define QuadSPI_SFB2AD_REG(base) ((base)->SFB2AD) +#define QuadSPI_RBDR_REG(base,index) ((base)->RBDR[index]) +#define QuadSPI_LUTKEY_REG(base) ((base)->LUTKEY) +#define QuadSPI_LCKCR_REG(base) ((base)->LCKCR) +#define QuadSPI_LUT_REG(base,index) ((base)->LUT[index]) + +/*! + * @} + */ /* end of group QuadSPI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define QuadSPI_MCR_SWRSTSD_MASK 0x1u +#define QuadSPI_MCR_SWRSTSD_SHIFT 0 +#define QuadSPI_MCR_SWRSTHD_MASK 0x2u +#define QuadSPI_MCR_SWRSTHD_SHIFT 1 +#define QuadSPI_MCR_DQS_EN_MASK 0x40u +#define QuadSPI_MCR_DQS_EN_SHIFT 6 +#define QuadSPI_MCR_DDR_EN_MASK 0x80u +#define QuadSPI_MCR_DDR_EN_SHIFT 7 +#define QuadSPI_MCR_CLR_RXF_MASK 0x400u +#define QuadSPI_MCR_CLR_RXF_SHIFT 10 +#define QuadSPI_MCR_CLR_TXF_MASK 0x800u +#define QuadSPI_MCR_CLR_TXF_SHIFT 11 +#define QuadSPI_MCR_MDIS_MASK 0x4000u +#define QuadSPI_MCR_MDIS_SHIFT 14 +#define QuadSPI_MCR_SCLKCFG_MASK 0xFF000000u +#define QuadSPI_MCR_SCLKCFG_SHIFT 24 +#define QuadSPI_MCR_SCLKCFG(x) (((uint32_t)(((uint32_t)(x))<VIR) +#define RDC_STAT_REG(base) ((base)->STAT) +#define RDC_INTCTRL_REG(base) ((base)->INTCTRL) +#define RDC_INTSTAT_REG(base) ((base)->INTSTAT) +#define RDC_MDA_REG(base,index) ((base)->MDA[index]) +#define RDC_PDAP_REG(base,index) ((base)->PDAP[index]) +#define RDC_MRSA_REG(base,index) ((base)->MR[index].MRSA) +#define RDC_MREA_REG(base,index) ((base)->MR[index].MREA) +#define RDC_MRC_REG(base,index) ((base)->MR[index].MRC) +#define RDC_MRVS_REG(base,index) ((base)->MR[index].MRVS) + +/*! + * @} + */ /* end of group RDC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- RDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Register_Masks RDC Register Masks + * @{ + */ + +/* VIR Bit Fields */ +#define RDC_VIR_NDID_MASK 0xFu +#define RDC_VIR_NDID_SHIFT 0 +#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x))<GATE[index]) +#define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W) +#define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks + * @{ + */ + +/* GATE Bit Fields */ +#define RDC_SEMAPHORE_GATE_GTFSM_MASK 0xFu +#define RDC_SEMAPHORE_GATE_GTFSM_SHIFT 0 +#define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x))<ROMPATCHD[index]) +#define ROMC_ROMPATCHCNTL_REG(base) ((base)->ROMPATCHCNTL) +#define ROMC_ROMPATCHENH_REG(base) ((base)->ROMPATCHENH) +#define ROMC_ROMPATCHENL_REG(base) ((base)->ROMPATCHENL) +#define ROMC_ROMPATCHA_REG(base,index) ((base)->ROMPATCHA[index]) +#define ROMC_ROMPATCHSR_REG(base) ((base)->ROMPATCHSR) + +/*! + * @} + */ /* end of group ROMC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/* ROMPATCHD Bit Fields */ +#define ROMC_ROMPATCHD_DATAX_MASK 0xFFFFFFFFu +#define ROMC_ROMPATCHD_DATAX_SHIFT 0 +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x))<MC0PTR) +#define SDMAARM_INTR_REG(base) ((base)->INTR) +#define SDMAARM_STOP_STAT_REG(base) ((base)->STOP_STAT) +#define SDMAARM_HSTART_REG(base) ((base)->HSTART) +#define SDMAARM_EVTOVR_REG(base) ((base)->EVTOVR) +#define SDMAARM_DSPOVR_REG(base) ((base)->DSPOVR) +#define SDMAARM_HOSTOVR_REG(base) ((base)->HOSTOVR) +#define SDMAARM_EVTPEND_REG(base) ((base)->EVTPEND) +#define SDMAARM_RESET_REG(base) ((base)->RESET) +#define SDMAARM_EVTERR_REG(base) ((base)->EVTERR) +#define SDMAARM_INTRMASK_REG(base) ((base)->INTRMASK) +#define SDMAARM_PSW_REG(base) ((base)->PSW) +#define SDMAARM_EVTERRDBG_REG(base) ((base)->EVTERRDBG) +#define SDMAARM_CONFIG_REG(base) ((base)->CONFIG) +#define SDMAARM_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK) +#define SDMAARM_ONCE_ENB_REG(base) ((base)->ONCE_ENB) +#define SDMAARM_ONCE_DATA_REG(base) ((base)->ONCE_DATA) +#define SDMAARM_ONCE_INSTR_REG(base) ((base)->ONCE_INSTR) +#define SDMAARM_ONCE_STAT_REG(base) ((base)->ONCE_STAT) +#define SDMAARM_ONCE_CMD_REG(base) ((base)->ONCE_CMD) +#define SDMAARM_ILLINSTADDR_REG(base) ((base)->ILLINSTADDR) +#define SDMAARM_CHN0ADDR_REG(base) ((base)->CHN0ADDR) +#define SDMAARM_EVT_MIRROR_REG(base) ((base)->EVT_MIRROR) +#define SDMAARM_EVT_MIRROR2_REG(base) ((base)->EVT_MIRROR2) +#define SDMAARM_XTRIG_CONF1_REG(base) ((base)->XTRIG_CONF1) +#define SDMAARM_XTRIG_CONF2_REG(base) ((base)->XTRIG_CONF2) +#define SDMAARM_SDMA_CHNPRI_REG(base,index) ((base)->SDMA_CHNPRI[index]) +#define SDMAARM_CHNENBL_REG(base,index) ((base)->CHNENBL[index]) + +/*! + * @} + */ /* end of group SDMAARM_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/* MC0PTR Bit Fields */ +#define SDMAARM_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu +#define SDMAARM_MC0PTR_MC0PTR_SHIFT 0 +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<DC0PTR) +#define SDMABP_INTR_REG(base) ((base)->INTR) +#define SDMABP_STOP_STAT_REG(base) ((base)->STOP_STAT) +#define SDMABP_DSTART_REG(base) ((base)->DSTART) +#define SDMABP_EVTERR_REG(base) ((base)->EVTERR) +#define SDMABP_INTRMASK_REG(base) ((base)->INTRMASK) +#define SDMABP_EVTERRDBG_REG(base) ((base)->EVTERRDBG) + +/*! + * @} + */ /* end of group SDMABP_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SDMABP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMABP_Register_Masks SDMABP Register Masks + * @{ + */ + +/* DC0PTR Bit Fields */ +#define SDMABP_DC0PTR_DC0PTR_MASK 0xFFFFFFFFu +#define SDMABP_DC0PTR_DC0PTR_SHIFT 0 +#define SDMABP_DC0PTR_DC0PTR(x) (((uint32_t)(((uint32_t)(x))<MC0PTR) +#define SDMACORE_CCPTR_REG(base) ((base)->CCPTR.CCPTR) +#define SDMACORE_CCR_REG(base) ((base)->CCR.CCR) +#define SDMACORE_NCR_REG(base) ((base)->NCR.NCR) +#define SDMACORE_EVENTS_REG(base) ((base)->EVENTS.EVENTS) +#define SDMACORE_CCPRI_REG(base) ((base)->CCPRI.CCPRI) +#define SDMACORE_NCPRI_REG(base) ((base)->NCPRI.NCPRI) +#define SDMACORE_ECOUNT_REG(base) ((base)->ECOUNT.ECOUNT) +#define SDMACORE_ECTL_REG(base) ((base)->ECTL.ECTL) +#define SDMACORE_EAA_REG(base) ((base)->EAA.EAA) +#define SDMACORE_EAB_REG(base) ((base)->EAB.EAB) +#define SDMACORE_EAM_REG(base) ((base)->EAM.EAM) +#define SDMACORE_ED_REG(base) ((base)->ED.ED) +#define SDMACORE_EDM_REG(base) ((base)->EDM.EDM) +#define SDMACORE_RTB_REG(base) ((base)->RTB) +#define SDMACORE_TB_REG(base) ((base)->TB.TB) +#define SDMACORE_OSTAT_REG(base) ((base)->OSTAT.OSTAT) +#define SDMACORE_MCHN0ADDR_REG(base) ((base)->MCHN0ADDR.MCHN0ADDR) +#define SDMACORE_ENDIANNESS_REG(base) ((base)->ENDIANNESS.ENDIANNESS) +#define SDMACORE_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK.SDMA_LOCK) +#define SDMACORE_EVENTS2_REG(base) ((base)->EVENTS2.EVENTS2) + +/*! + * @} + */ /* end of group SDMACORE_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SDMACORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMACORE_Register_Masks SDMACORE Register Masks + * @{ + */ + +/* MC0PTR Bit Fields */ +#define SDMACORE_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu +#define SDMACORE_MC0PTR_MC0PTR_SHIFT 0 +#define SDMACORE_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<GATE00) +#define SEMA4_GATE01_REG(base) ((base)->GATE01) +#define SEMA4_GATE02_REG(base) ((base)->GATE02) +#define SEMA4_GATE03_REG(base) ((base)->GATE03) +#define SEMA4_GATE04_REG(base) ((base)->GATE04) +#define SEMA4_GATE05_REG(base) ((base)->GATE05) +#define SEMA4_GATE06_REG(base) ((base)->GATE06) +#define SEMA4_GATE07_REG(base) ((base)->GATE07) +#define SEMA4_GATE08_REG(base) ((base)->GATE08) +#define SEMA4_GATE09_REG(base) ((base)->GATE09) +#define SEMA4_GATE10_REG(base) ((base)->GATE10) +#define SEMA4_GATE11_REG(base) ((base)->GATE11) +#define SEMA4_GATE12_REG(base) ((base)->GATE12) +#define SEMA4_GATE13_REG(base) ((base)->GATE13) +#define SEMA4_GATE14_REG(base) ((base)->GATE14) +#define SEMA4_GATE15_REG(base) ((base)->GATE15) +#define SEMA4_CPINE_REG(base,index) ((base)->CPnINE[index].INE) +#define SEMA4_CPNTF_REG(base,index) ((base)->CPnNTF[index].NTF) +#define SEMA4_RSTGT_REG(base) ((base)->RSTGT) +#define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) + +/*! + * @} + */ /* end of group SEMA4_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SEMA4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks + * @{ + */ + +/* GATE00 Bit Fields */ +#define SEMA4_GATE00_GTFSM_MASK 0x3u +#define SEMA4_GATE00_GTFSM_SHIFT 0 +#define SEMA4_GATE00_GTFSM(x) (((uint8_t)(((uint8_t)(x))<GPUSR1) +#define SJC_GPUSR2_REG(base) ((base)->GPUSR2.GPUSR2) +#define SJC_GPUSR3_REG(base) ((base)->GPUSR3.GPUSR3) +#define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) +#define SJC_DCR_REG(base) ((base)->DCR.DCR) +#define SJC_SSR_REG(base) ((base)->SSR.SSR) +#define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) + +/*! + * @} + */ /* end of group SJC_Register_Accessor_Macros */ + + /* ---------------------------------------------------------------------------- + -- SJC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SJC_Register_Masks SJC Register Masks + * @{ + */ + +/* GPUSR1 Bit Fields */ +#define SJC_GPUSR1_A_DBG_MASK 0x1u +#define SJC_GPUSR1_A_DBG_SHIFT 0 +#define SJC_GPUSR1_A_WFI_MASK 0x2u +#define SJC_GPUSR1_A_WFI_SHIFT 1 +#define SJC_GPUSR1_S_STAT_MASK 0x1Cu +#define SJC_GPUSR1_S_STAT_SHIFT 2 +#define SJC_GPUSR1_S_STAT(x) (((uint32_t)(((uint32_t)(x))<HPLR) +#define SNVS_HPCOMR_REG(base) ((base)->HPCOMR) +#define SNVS_HPCR_REG(base) ((base)->HPCR) +#define SNVS_HPSR_REG(base) ((base)->HPSR) +#define SNVS_HPRTCMR_REG(base) ((base)->HPRTCMR) +#define SNVS_HPRTCLR_REG(base) ((base)->HPRTCLR) +#define SNVS_HPTAMR_REG(base) ((base)->HPTAMR) +#define SNVS_HPTALR_REG(base) ((base)->HPTALR) +#define SNVS_LPLR_REG(base) ((base)->LPLR) +#define SNVS_LPCR_REG(base) ((base)->LPCR) +#define SNVS_LPSR_REG(base) ((base)->LPSR) +#define SNVS_LPSMCMR_REG(base) ((base)->LPSMCMR) +#define SNVS_LPSMCLR_REG(base) ((base)->LPSMCLR) +#define SNVS_LPGPR_REG(base) ((base)->LPGPR) +#define SNVS_HPVIDR1_REG(base) ((base)->HPVIDR1) +#define SNVS_HPVIDR2_REG(base) ((base)->HPVIDR2) + +/*! + * @} + */ /* end of group SNVS_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/* HPLR Bit Fields */ +#define SNVS_HPLR_MC_SL_MASK 0x10u +#define SNVS_HPLR_MC_SL_SHIFT 4 +#define SNVS_HPLR_GPR_SL_MASK 0x20u +#define SNVS_HPLR_GPR_SL_SHIFT 5 +/* HPCOMR Bit Fields */ +#define SNVS_HPCOMR_LP_SWR_MASK 0x10u +#define SNVS_HPCOMR_LP_SWR_SHIFT 4 +#define SNVS_HPCOMR_LP_SWR_DIS_MASK 0x20u +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT 5 +#define SNVS_HPCOMR_NPSWA_EN_MASK 0x80000000u +#define SNVS_HPCOMR_NPSWA_EN_SHIFT 31 +/* HPCR Bit Fields */ +#define SNVS_HPCR_RTC_EN_MASK 0x1u +#define SNVS_HPCR_RTC_EN_SHIFT 0 +#define SNVS_HPCR_HPTA_EN_MASK 0x2u +#define SNVS_HPCR_HPTA_EN_SHIFT 1 +#define SNVS_HPCR_PI_EN_MASK 0x8u +#define SNVS_HPCR_PI_EN_SHIFT 3 +#define SNVS_HPCR_PI_FREQ_MASK 0xF0u +#define SNVS_HPCR_PI_FREQ_SHIFT 4 +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x))<PRR[index]) + +/*! + * @} + */ /* end of group SPBA_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/* PRR Bit Fields */ +#define SPBA_PRR_RARA_MASK 0x1u +#define SPBA_PRR_RARA_SHIFT 0 +#define SPBA_PRR_RARB_MASK 0x2u +#define SPBA_PRR_RARB_SHIFT 1 +#define SPBA_PRR_RARC_MASK 0x4u +#define SPBA_PRR_RARC_SHIFT 2 +#define SPBA_PRR_ROI_MASK 0x30000u +#define SPBA_PRR_ROI_SHIFT 16 +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x))<SCR) +#define SPDIF_SRCD_REG(base) ((base)->SRCD) +#define SPDIF_SRPC_REG(base) ((base)->SRPC) +#define SPDIF_SIE_REG(base) ((base)->SIE) +#define SPDIF_SIS_REG(base) ((base)->SIS) +#define SPDIF_SIC_REG(base) ((base)->SIC) +#define SPDIF_SRL_REG(base) ((base)->SRL.SRL) +#define SPDIF_SRR_REG(base) ((base)->SRR.SRR) +#define SPDIF_SRCSH_REG(base) ((base)->SRCSH.SRCSH) +#define SPDIF_SRCSL_REG(base) ((base)->SRCSL.SRCSL) +#define SPDIF_SRU_REG(base) ((base)->SRU.SRU) +#define SPDIF_SRQ_REG(base) ((base)->SRQ.SRQ) +#define SPDIF_STL_REG(base) ((base)->STL.STL) +#define SPDIF_STR_REG(base) ((base)->STR.STR) +#define SPDIF_STCSCH_REG(base) ((base)->STCSCH.STCSCH) +#define SPDIF_STCSCL_REG(base) ((base)->STCSCL.STCSCL) +#define SPDIF_SRFM_REG(base) ((base)->SRFM) +#define SPDIF_STC_REG(base) ((base)->STC) + +/*! + * @} + */ /* end of group SPDIF_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SPDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPDIF_Register_Masks SPDIF Register Masks + * @{ + */ + +/* SCR Bit Fields */ +#define SPDIF_SCR_USrc_Sel_MASK 0x3u +#define SPDIF_SCR_USrc_Sel_SHIFT 0 +#define SPDIF_SCR_USrc_Sel(x) (((uint32_t)(((uint32_t)(x))<SCR) +#define SRC_SBMR1_REG(base) ((base)->SBMR1) +#define SRC_SRSR_REG(base) ((base)->SRSR) +#define SRC_SISR_REG(base) ((base)->SISR) +#define SRC_SIMR_REG(base) ((base)->SIMR) +#define SRC_SBMR2_REG(base) ((base)->SBMR2) +#define SRC_GPR1_REG(base) ((base)->GPR1) +#define SRC_GPR2_REG(base) ((base)->GPR2) +#define SRC_GPR3_REG(base) ((base)->GPR3) +#define SRC_GPR4_REG(base) ((base)->GPR4) +#define SRC_GPR5_REG(base) ((base)->GPR5) +#define SRC_GPR6_REG(base) ((base)->GPR6) +#define SRC_GPR7_REG(base) ((base)->GPR7) +#define SRC_GPR8_REG(base) ((base)->GPR8) +#define SRC_GPR9_REG(base) ((base)->GPR9) +#define SRC_GPR10_REG(base) ((base)->GPR10) + +/*! + * @} + */ /* end of group SRC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/* SCR Bit Fields */ +#define SRC_SCR_warm_reset_enable_MASK 0x1u +#define SRC_SCR_warm_reset_enable_SHIFT 0 +#define SRC_SCR_sw_gpu_rst_MASK 0x2u +#define SRC_SCR_sw_gpu_rst_SHIFT 1 +#define SRC_SCR_m4c_rst_MASK 0x8u +#define SRC_SCR_m4c_rst_SHIFT 3 +#define SRC_SCR_m4c_non_sclr_rst_MASK 0x10u +#define SRC_SCR_m4c_non_sclr_rst_SHIFT 4 +#define SRC_SCR_warm_rst_bypass_count_MASK 0x60u +#define SRC_SCR_warm_rst_bypass_count_SHIFT 5 +#define SRC_SCR_warm_rst_bypass_count(x) (((uint32_t)(((uint32_t)(x))<STX[index]) +#define SSI_SRX_REG(base,index) ((base)->SRX[index]) +#define SSI_SCR_REG(base) ((base)->SCR) +#define SSI_SISR_REG(base) ((base)->SISR) +#define SSI_SIER_REG(base) ((base)->SIER) +#define SSI_STCR_REG(base) ((base)->STCR) +#define SSI_SRCR_REG(base) ((base)->SRCR) +#define SSI_STCCR_REG(base) ((base)->STCCR) +#define SSI_SRCCR_REG(base) ((base)->SRCCR) +#define SSI_SFCSR_REG(base) ((base)->SFCSR) +#define SSI_SACNT_REG(base) ((base)->SACNT) +#define SSI_SACADD_REG(base) ((base)->SACADD) +#define SSI_SACDAT_REG(base) ((base)->SACDAT) +#define SSI_SATAG_REG(base) ((base)->SATAG) +#define SSI_STMSK_REG(base) ((base)->STMSK) +#define SSI_SRMSK_REG(base) ((base)->SRMSK) +#define SSI_SACCST_REG(base) ((base)->SACCST) +#define SSI_SACCEN_REG(base) ((base)->SACCEN) +#define SSI_SACCDIS_REG(base) ((base)->SACCDIS) + +/*! + * @} + */ /* end of group SSI_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- SSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SSI_Register_Masks SSI Register Masks + * @{ + */ + +/* STX Bit Fields */ +#define SSI_STX_STXn_MASK 0xFFFFFFFFu +#define SSI_STX_STXn_SHIFT 0 +#define SSI_STX_STXn(x) (((uint32_t)(((uint32_t)(x))<TEMPSENSE0) +#define TEMPMON_TEMPSENSE0_SET_REG(base) ((base)->TEMPSENSE0_SET) +#define TEMPMON_TEMPSENSE0_CLR_REG(base) ((base)->TEMPSENSE0_CLR) +#define TEMPMON_TEMPSENSE0_TOG_REG(base) ((base)->TEMPSENSE0_TOG) +#define TEMPMON_TEMPSENSE1_REG(base) ((base)->TEMPSENSE1) +#define TEMPMON_TEMPSENSE1_SET_REG(base) ((base)->TEMPSENSE1_SET) +#define TEMPMON_TEMPSENSE1_CLR_REG(base) ((base)->TEMPSENSE1_CLR) +#define TEMPMON_TEMPSENSE1_TOG_REG(base) ((base)->TEMPSENSE1_TOG) +#define TEMPMON_TEMPSENSE2_REG(base) ((base)->TEMPSENSE2) +#define TEMPMON_TEMPSENSE2_SET_REG(base) ((base)->TEMPSENSE2_SET) +#define TEMPMON_TEMPSENSE2_CLR_REG(base) ((base)->TEMPSENSE2_CLR) +#define TEMPMON_TEMPSENSE2_TOG_REG(base) ((base)->TEMPSENSE2_TOG) + +/*! + * @} + */ /* end of group TEMPMON_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/* TEMPSENSE0 Bit Fields */ +#define TEMPMON_TEMPSENSE0_POWER_DOWN_MASK 0x1u +#define TEMPMON_TEMPSENSE0_POWER_DOWN_SHIFT 0 +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_MASK 0x2u +#define TEMPMON_TEMPSENSE0_MEASURE_TEMP_SHIFT 1 +#define TEMPMON_TEMPSENSE0_FINISHED_MASK 0x4u +#define TEMPMON_TEMPSENSE0_FINISHED_SHIFT 2 +#define TEMPMON_TEMPSENSE0_TEMP_CNT_MASK 0xFFF00u +#define TEMPMON_TEMPSENSE0_TEMP_CNT_SHIFT 8 +#define TEMPMON_TEMPSENSE0_TEMP_CNT(x) (((uint32_t)(((uint32_t)(x))<URXD) +#define UART_UTXD_REG(base) ((base)->UTXD) +#define UART_UCR1_REG(base) ((base)->UCR1) +#define UART_UCR2_REG(base) ((base)->UCR2) +#define UART_UCR3_REG(base) ((base)->UCR3) +#define UART_UCR4_REG(base) ((base)->UCR4) +#define UART_UFCR_REG(base) ((base)->UFCR) +#define UART_USR1_REG(base) ((base)->USR1) +#define UART_USR2_REG(base) ((base)->USR2) +#define UART_UESC_REG(base) ((base)->UESC) +#define UART_UTIM_REG(base) ((base)->UTIM) +#define UART_UBIR_REG(base) ((base)->UBIR) +#define UART_UBMR_REG(base) ((base)->UBMR) +#define UART_UBRC_REG(base) ((base)->UBRC) +#define UART_ONEMS_REG(base) ((base)->ONEMS) +#define UART_UTS_REG(base) ((base)->UTS) +#define UART_UMCR_REG(base) ((base)->UMCR) + +/*! + * @} + */ /* end of group UART_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* URXD Bit Fields */ +#define UART_URXD_RX_DATA_MASK 0xFFu +#define UART_URXD_RX_DATA_SHIFT 0 +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<UOG1_ID) +#define USBC_UOG1_HWGENERAL_REG(base) ((base)->UOG1_HWGENERAL) +#define USBC_UOG1_HWHOST_REG(base) ((base)->UOG1_HWHOST) +#define USBC_UOG1_HWDEVICE_REG(base) ((base)->UOG1_HWDEVICE) +#define USBC_UOG1_HWTXBUF_REG(base) ((base)->UOG1_HWTXBUF) +#define USBC_UOG1_HWRXBUF_REG(base) ((base)->UOG1_HWRXBUF) +#define USBC_UOG1_GPTIMER0LD_REG(base) ((base)->UOG1_GPTIMER0LD) +#define USBC_UOG1_GPTIMER0CTRL_REG(base) ((base)->UOG1_GPTIMER0CTRL) +#define USBC_UOG1_GPTIMER1LD_REG(base) ((base)->UOG1_GPTIMER1LD) +#define USBC_UOG1_GPTIMER1CTRL_REG(base) ((base)->UOG1_GPTIMER1CTRL) +#define USBC_UOG1_SBUSCFG_REG(base) ((base)->UOG1_SBUSCFG) +#define USBC_UOG1_CAPLENGTH_REG(base) ((base)->UOG1_CAPLENGTH) +#define USBC_UOG1_HCIVERSION_REG(base) ((base)->UOG1_HCIVERSION) +#define USBC_UOG1_HCSPARAMS_REG(base) ((base)->UOG1_HCSPARAMS) +#define USBC_UOG1_HCCPARAMS_REG(base) ((base)->UOG1_HCCPARAMS) +#define USBC_UOG1_DCIVERSION_REG(base) ((base)->UOG1_DCIVERSION) +#define USBC_UOG1_DCCPARAMS_REG(base) ((base)->UOG1_DCCPARAMS) +#define USBC_UOG1_USBCMD_REG(base) ((base)->UOG1_USBCMD) +#define USBC_UOG1_USBSTS_REG(base) ((base)->UOG1_USBSTS) +#define USBC_UOG1_USBINTR_REG(base) ((base)->UOG1_USBINTR) +#define USBC_UOG1_FRINDEX_REG(base) ((base)->UOG1_FRINDEX) +#define USBC_UOG1_PERIODICLISTBASE_REG(base) ((base)->UOG1_PERIODICLISTBASE) +#define USBC_UOG1_DEVICEADDR_REG(base) ((base)->UOG1_DEVICEADDR) +#define USBC_UOG1_ASYNCLISTADDR_REG(base) ((base)->UOG1_ASYNCLISTADDR.UOG1_ASYNCLISTADDR) +#define USBC_UOG1_ENDPTLISTADDR_REG(base) ((base)->UOG1_ENDPTLISTADDR.UOG1_ENDPTLISTADDR) +#define USBC_UOG1_BURSTSIZE_REG(base) ((base)->UOG1_BURSTSIZE) +#define USBC_UOG1_TXFILLTUNING_REG(base) ((base)->UOG1_TXFILLTUNING) +#define USBC_UOG1_ENDPTNAK_REG(base) ((base)->UOG1_ENDPTNAK) +#define USBC_UOG1_ENDPTNAKEN_REG(base) ((base)->UOG1_ENDPTNAKEN) +#define USBC_UOG1_CONFIGFLAG_REG(base) ((base)->UOG1_CONFIGFLAG) +#define USBC_UOG1_PORTSC1_REG(base) ((base)->UOG1_PORTSC1) +#define USBC_UOG1_OTGSC_REG(base) ((base)->UOG1_OTGSC) +#define USBC_UOG1_USBMODE_REG(base) ((base)->UOG1_USBMODE) +#define USBC_UOG1_ENDPTSETUPSTAT_REG(base) ((base)->UOG1_ENDPTSETUPSTAT) +#define USBC_UOG1_ENDPTPRIME_REG(base) ((base)->UOG1_ENDPTPRIME) +#define USBC_UOG1_ENDPTFLUSH_REG(base) ((base)->UOG1_ENDPTFLUSH) +#define USBC_UOG1_ENDPTSTAT_REG(base) ((base)->UOG1_ENDPTSTAT) +#define USBC_UOG1_ENDPTCOMPLETE_REG(base) ((base)->UOG1_ENDPTCOMPLETE) +#define USBC_UOG1_ENDPTCTRL0_REG(base) ((base)->UOG1_ENDPTCTRL0) +#define USBC_UOG1_ENDPTCTRL1_REG(base) ((base)->UOG1_ENDPTCTRL1) +#define USBC_UOG1_ENDPTCTRL2_REG(base) ((base)->UOG1_ENDPTCTRL2) +#define USBC_UOG1_ENDPTCTRL3_REG(base) ((base)->UOG1_ENDPTCTRL3) +#define USBC_UOG1_ENDPTCTRL4_REG(base) ((base)->UOG1_ENDPTCTRL4) +#define USBC_UOG1_ENDPTCTRL5_REG(base) ((base)->UOG1_ENDPTCTRL5) +#define USBC_UOG1_ENDPTCTRL6_REG(base) ((base)->UOG1_ENDPTCTRL6) +#define USBC_UOG1_ENDPTCTRL7_REG(base) ((base)->UOG1_ENDPTCTRL7) +#define USBC_UOG2_ID_REG(base) ((base)->UOG2_ID) +#define USBC_UOG2_HWGENERAL_REG(base) ((base)->UOG2_HWGENERAL) +#define USBC_UOG2_HWHOST_REG(base) ((base)->UOG2_HWHOST) +#define USBC_UOG2_HWDEVICE_REG(base) ((base)->UOG2_HWDEVICE) +#define USBC_UOG2_HWTXBUF_REG(base) ((base)->UOG2_HWTXBUF) +#define USBC_UOG2_HWRXBUF_REG(base) ((base)->UOG2_HWRXBUF) +#define USBC_UOG2_GPTIMER0LD_REG(base) ((base)->UOG2_GPTIMER0LD) +#define USBC_UOG2_GPTIMER0CTRL_REG(base) ((base)->UOG2_GPTIMER0CTRL) +#define USBC_UOG2_GPTIMER1LD_REG(base) ((base)->UOG2_GPTIMER1LD) +#define USBC_UOG2_GPTIMER1CTRL_REG(base) ((base)->UOG2_GPTIMER1CTRL) +#define USBC_UOG2_SBUSCFG_REG(base) ((base)->UOG2_SBUSCFG) +#define USBC_UOG2_CAPLENGTH_REG(base) ((base)->UOG2_CAPLENGTH) +#define USBC_UOG2_HCIVERSION_REG(base) ((base)->UOG2_HCIVERSION) +#define USBC_UOG2_HCSPARAMS_REG(base) ((base)->UOG2_HCSPARAMS) +#define USBC_UOG2_HCCPARAMS_REG(base) ((base)->UOG2_HCCPARAMS) +#define USBC_UOG2_DCIVERSION_REG(base) ((base)->UOG2_DCIVERSION) +#define USBC_UOG2_DCCPARAMS_REG(base) ((base)->UOG2_DCCPARAMS) +#define USBC_UOG2_USBCMD_REG(base) ((base)->UOG2_USBCMD) +#define USBC_UOG2_USBSTS_REG(base) ((base)->UOG2_USBSTS) +#define USBC_UOG2_USBINTR_REG(base) ((base)->UOG2_USBINTR) +#define USBC_UOG2_FRINDEX_REG(base) ((base)->UOG2_FRINDEX) +#define USBC_UOG2_PERIODICLISTBASE_REG(base) ((base)->UOG2_PERIODICLISTBASE) +#define USBC_UOG2_DEVICEADDR_REG(base) ((base)->UOG2_DEVICEADDR) +#define USBC_UOG2_ASYNCLISTADDR_REG(base) ((base)->UOG2_ASYNCLISTADDR.UOG2_ASYNCLISTADDR) +#define USBC_UOG2_ENDPTLISTADDR_REG(base) ((base)->UOG2_ENDPTLISTADDR.UOG2_ENDPTLISTADDR) +#define USBC_UOG2_BURSTSIZE_REG(base) ((base)->UOG2_BURSTSIZE) +#define USBC_UOG2_TXFILLTUNING_REG(base) ((base)->UOG2_TXFILLTUNING) +#define USBC_UOG2_ENDPTNAK_REG(base) ((base)->UOG2_ENDPTNAK) +#define USBC_UOG2_ENDPTNAKEN_REG(base) ((base)->UOG2_ENDPTNAKEN) +#define USBC_UOG2_CONFIGFLAG_REG(base) ((base)->UOG2_CONFIGFLAG) +#define USBC_UOG2_PORTSC1_REG(base) ((base)->UOG2_PORTSC1) +#define USBC_UOG2_OTGSC_REG(base) ((base)->UOG2_OTGSC) +#define USBC_UOG2_USBMODE_REG(base) ((base)->UOG2_USBMODE) +#define USBC_UOG2_ENDPTSETUPSTAT_REG(base) ((base)->UOG2_ENDPTSETUPSTAT) +#define USBC_UOG2_ENDPTPRIME_REG(base) ((base)->UOG2_ENDPTPRIME) +#define USBC_UOG2_ENDPTFLUSH_REG(base) ((base)->UOG2_ENDPTFLUSH) +#define USBC_UOG2_ENDPTSTAT_REG(base) ((base)->UOG2_ENDPTSTAT) +#define USBC_UOG2_ENDPTCOMPLETE_REG(base) ((base)->UOG2_ENDPTCOMPLETE) +#define USBC_UOG2_ENDPTCTRL0_REG(base) ((base)->UOG2_ENDPTCTRL0) +#define USBC_UOG2_ENDPTCTRL1_REG(base) ((base)->UOG2_ENDPTCTRL1) +#define USBC_UOG2_ENDPTCTRL2_REG(base) ((base)->UOG2_ENDPTCTRL2) +#define USBC_UOG2_ENDPTCTRL3_REG(base) ((base)->UOG2_ENDPTCTRL3) +#define USBC_UOG2_ENDPTCTRL4_REG(base) ((base)->UOG2_ENDPTCTRL4) +#define USBC_UOG2_ENDPTCTRL5_REG(base) ((base)->UOG2_ENDPTCTRL5) +#define USBC_UOG2_ENDPTCTRL6_REG(base) ((base)->UOG2_ENDPTCTRL6) +#define USBC_UOG2_ENDPTCTRL7_REG(base) ((base)->UOG2_ENDPTCTRL7) +#define USBC_UH1_ID_REG(base) ((base)->UH1_ID) +#define USBC_UH1_HWGENERAL_REG(base) ((base)->UH1_HWGENERAL) +#define USBC_UH1_HWHOST_REG(base) ((base)->UH1_HWHOST) +#define USBC_UH1_HWTXBUF_REG(base) ((base)->UH1_HWTXBUF) +#define USBC_UH1_HWRXBUF_REG(base) ((base)->UH1_HWRXBUF) +#define USBC_UH1_GPTIMER0LD_REG(base) ((base)->UH1_GPTIMER0LD) +#define USBC_UH1_GPTIMER0CTRL_REG(base) ((base)->UH1_GPTIMER0CTRL) +#define USBC_UH1_GPTIMER1LD_REG(base) ((base)->UH1_GPTIMER1LD) +#define USBC_UH1_GPTIMER1CTRL_REG(base) ((base)->UH1_GPTIMER1CTRL) +#define USBC_UH1_SBUSCFG_REG(base) ((base)->UH1_SBUSCFG) +#define USBC_UH1_CAPLENGTH_REG(base) ((base)->UH1_CAPLENGTH) +#define USBC_UH1_HCIVERSION_REG(base) ((base)->UH1_HCIVERSION) +#define USBC_UH1_HCSPARAMS_REG(base) ((base)->UH1_HCSPARAMS) +#define USBC_UH1_HCCPARAMS_REG(base) ((base)->UH1_HCCPARAMS) +#define USBC_UH1_USBCMD_REG(base) ((base)->UH1_USBCMD) +#define USBC_UH1_USBSTS_REG(base) ((base)->UH1_USBSTS) +#define USBC_UH1_USBINTR_REG(base) ((base)->UH1_USBINTR) +#define USBC_UH1_FRINDEX_REG(base) ((base)->UH1_FRINDEX) +#define USBC_UH1_PERIODICLISTBASE_REG(base) ((base)->UH1_PERIODICLISTBASE) +#define USBC_UH1_ASYNCLISTADDR_REG(base) ((base)->UH1_ASYNCLISTADDR) +#define USBC_UH1_BURSTSIZE_REG(base) ((base)->UH1_BURSTSIZE) +#define USBC_UH1_TXFILLTUNING_REG(base) ((base)->UH1_TXFILLTUNING) +#define USBC_UH1_CONFIGFLAG_REG(base) ((base)->UH1_CONFIGFLAG) +#define USBC_UH1_PORTSC1_REG(base) ((base)->UH1_PORTSC1) +#define USBC_UH1_USBMODE_REG(base) ((base)->UH1_USBMODE) + +/*! + * @} + */ /* end of group USBC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- USBC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBC_Register_Masks USBC Register Masks + * @{ + */ + +/* UOG1_ID Bit Fields */ +#define USBC_UOG1_ID_ID_MASK 0x3Fu +#define USBC_UOG1_ID_ID_SHIFT 0 +#define USBC_UOG1_ID_ID(x) (((uint32_t)(((uint32_t)(x))<USB_x_PHY_STS) +#define USBNC_ADP_CFG2_REG(base) ((base)->ADP_CFG2) +#define USBNC_USB_OTG1_CTRL_REG(base) ((base)->USB_OTG1_CTRL) +#define USBNC_USB_OTG2_CTRL_REG(base) ((base)->USB_OTG2_CTRL) +#define USBNC_USB_UH_CTRL_REG(base) ((base)->USB_UH_CTRL) +#define USBNC_USB_UH_HSIC_CTRL_REG(base) ((base)->USB_UH_HSIC_CTRL) +#define USBNC_USB_OTG1_PHY_CTRL_0_REG(base) ((base)->USB_OTG1_PHY_CTRL_0) +#define USBNC_USB_OTG2_PHY_CTRL_0_REG(base) ((base)->USB_OTG2_PHY_CTRL_0) + +/*! + * @} + */ /* end of group USBNC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/* USB_x_PHY_STS Bit Fields */ +#define USBNC_USB_x_PHY_STS_LINE_STATE_MASK 0x3u +#define USBNC_USB_x_PHY_STS_LINE_STATE_SHIFT 0 +#define USBNC_USB_x_PHY_STS_LINE_STATE(x) (((uint32_t)(((uint32_t)(x))<PWD) +#define USBPHY_PWD_SET_REG(base) ((base)->PWD_SET) +#define USBPHY_PWD_CLR_REG(base) ((base)->PWD_CLR) +#define USBPHY_PWD_TOG_REG(base) ((base)->PWD_TOG) +#define USBPHY_TX_REG(base) ((base)->TX) +#define USBPHY_TX_SET_REG(base) ((base)->TX_SET) +#define USBPHY_TX_CLR_REG(base) ((base)->TX_CLR) +#define USBPHY_TX_TOG_REG(base) ((base)->TX_TOG) +#define USBPHY_RX_REG(base) ((base)->RX) +#define USBPHY_RX_SET_REG(base) ((base)->RX_SET) +#define USBPHY_RX_CLR_REG(base) ((base)->RX_CLR) +#define USBPHY_RX_TOG_REG(base) ((base)->RX_TOG) +#define USBPHY_CTRL_REG(base) ((base)->CTRL) +#define USBPHY_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define USBPHY_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define USBPHY_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define USBPHY_STATUS_REG(base) ((base)->STATUS) +#define USBPHY_DEBUG_REG(base) ((base)->DEBUG) +#define USBPHY_DEBUG_SET_REG(base) ((base)->DEBUG_SET) +#define USBPHY_DEBUG_CLR_REG(base) ((base)->DEBUG_CLR) +#define USBPHY_DEBUG_TOG_REG(base) ((base)->DEBUG_TOG) +#define USBPHY_DEBUG0_STATUS_REG(base) ((base)->DEBUG0_STATUS) +#define USBPHY_DEBUG1_REG(base) ((base)->DEBUG1) +#define USBPHY_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) +#define USBPHY_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) +#define USBPHY_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) +#define USBPHY_VERSION_REG(base) ((base)->VERSION) + +/*! + * @} + */ /* end of group USBPHY_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- USBPHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBPHY_Register_Masks USBPHY Register Masks + * @{ + */ + +/* PWD Bit Fields */ +#define USBPHY_PWD_RSVD0_MASK 0x3FFu +#define USBPHY_PWD_RSVD0_SHIFT 0 +#define USBPHY_PWD_RSVD0(x) (((uint32_t)(((uint32_t)(x))<USB1_VBUS_DETECT) +#define USB_ANALOG_USB1_VBUS_DETECT_SET_REG(base) ((base)->USB1_VBUS_DETECT_SET) +#define USB_ANALOG_USB1_VBUS_DETECT_CLR_REG(base) ((base)->USB1_VBUS_DETECT_CLR) +#define USB_ANALOG_USB1_VBUS_DETECT_TOG_REG(base) ((base)->USB1_VBUS_DETECT_TOG) +#define USB_ANALOG_USB1_CHRG_DETECT_REG(base) ((base)->USB1_CHRG_DETECT) +#define USB_ANALOG_USB1_CHRG_DETECT_SET_REG(base) ((base)->USB1_CHRG_DETECT_SET) +#define USB_ANALOG_USB1_CHRG_DETECT_CLR_REG(base) ((base)->USB1_CHRG_DETECT_CLR) +#define USB_ANALOG_USB1_CHRG_DETECT_TOG_REG(base) ((base)->USB1_CHRG_DETECT_TOG) +#define USB_ANALOG_USB1_VBUS_DETECT_STAT_REG(base) ((base)->USB1_VBUS_DETECT_STAT) +#define USB_ANALOG_USB1_CHRG_DETECT_STAT_REG(base) ((base)->USB1_CHRG_DETECT_STAT) +#define USB_ANALOG_USB1_MISC_REG(base) ((base)->USB1_MISC) +#define USB_ANALOG_USB1_MISC_SET_REG(base) ((base)->USB1_MISC_SET) +#define USB_ANALOG_USB1_MISC_CLR_REG(base) ((base)->USB1_MISC_CLR) +#define USB_ANALOG_USB1_MISC_TOG_REG(base) ((base)->USB1_MISC_TOG) +#define USB_ANALOG_USB2_VBUS_DETECT_REG(base) ((base)->USB2_VBUS_DETECT) +#define USB_ANALOG_USB2_VBUS_DETECT_SET_REG(base) ((base)->USB2_VBUS_DETECT_SET) +#define USB_ANALOG_USB2_VBUS_DETECT_CLR_REG(base) ((base)->USB2_VBUS_DETECT_CLR) +#define USB_ANALOG_USB2_VBUS_DETECT_TOG_REG(base) ((base)->USB2_VBUS_DETECT_TOG) +#define USB_ANALOG_USB2_CHRG_DETECT_REG(base) ((base)->USB2_CHRG_DETECT) +#define USB_ANALOG_USB2_CHRG_DETECT_SET_REG(base) ((base)->USB2_CHRG_DETECT_SET) +#define USB_ANALOG_USB2_CHRG_DETECT_CLR_REG(base) ((base)->USB2_CHRG_DETECT_CLR) +#define USB_ANALOG_USB2_CHRG_DETECT_TOG_REG(base) ((base)->USB2_CHRG_DETECT_TOG) +#define USB_ANALOG_USB2_VBUS_DETECT_STAT_REG(base) ((base)->USB2_VBUS_DETECT_STAT) +#define USB_ANALOG_USB2_CHRG_DETECT_STAT_REG(base) ((base)->USB2_CHRG_DETECT_STAT) +#define USB_ANALOG_USB2_MISC_REG(base) ((base)->USB2_MISC) +#define USB_ANALOG_USB2_MISC_SET_REG(base) ((base)->USB2_MISC_SET) +#define USB_ANALOG_USB2_MISC_CLR_REG(base) ((base)->USB2_MISC_CLR) +#define USB_ANALOG_USB2_MISC_TOG_REG(base) ((base)->USB2_MISC_TOG) +#define USB_ANALOG_DIGPROG_REG(base) ((base)->DIGPROG) + +/*! + * @} + */ /* end of group USB_ANALOG_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- USB_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_ANALOG_Register_Masks USB_ANALOG Register Masks + * @{ + */ + +/* USB1_VBUS_DETECT Bit Fields */ +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK 0x7u +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT 0 +#define USB_ANALOG_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x))<CFC1) +#define VDEC_BRSTGT_REG(base) ((base)->BRSTGT) +#define VDEC_HZPOS_REG(base) ((base)->HZPOS) +#define VDEC_VRTPOS_REG(base) ((base)->VRTPOS) +#define VDEC_HVSHFT_REG(base) ((base)->HVSHFT) +#define VDEC_HSIGS_REG(base) ((base)->HSIGS) +#define VDEC_HSIGE_REG(base) ((base)->HSIGE) +#define VDEC_VSCON1_REG(base) ((base)->VSCON1) +#define VDEC_VSCON2_REG(base) ((base)->VSCON2) +#define VDEC_YCDEL_REG(base) ((base)->YCDEL) +#define VDEC_AFTCLP_REG(base) ((base)->AFTCLP) +#define VDEC_DCOFF_REG(base) ((base)->DCOFF) +#define VDEC_CSID_REG(base) ((base)->CSID) +#define VDEC_CBGN_REG(base) ((base)->CBGN) +#define VDEC_CRGN_REG(base) ((base)->CRGN) +#define VDEC_CNTR_REG(base) ((base)->CNTR) +#define VDEC_BRT_REG(base) ((base)->BRT) +#define VDEC_HUE_REG(base) ((base)->HUE) +#define VDEC_CHBTH_REG(base) ((base)->CHBTH) +#define VDEC_SHPIMP_REG(base) ((base)->SHPIMP) +#define VDEC_CHPLLIM_REG(base) ((base)->CHPLLIM) +#define VDEC_VIDMOD_REG(base) ((base)->VIDMOD) +#define VDEC_VIDSTS_REG(base) ((base)->VIDSTS) +#define VDEC_NOISE_REG(base) ((base)->NOISE) +#define VDEC_STDDBG_REG(base) ((base)->STDDBG) +#define VDEC_MANOVR_REG(base) ((base)->MANOVR) +#define VDEC_VSSGTH_REG(base) ((base)->VSSGTH) +#define VDEC_DBGFBH_REG(base) ((base)->DBGFBH) +#define VDEC_DBGFBL_REG(base) ((base)->DBGFBL) +#define VDEC_HACTS_REG(base) ((base)->HACTS) +#define VDEC_HACTE_REG(base) ((base)->HACTE) +#define VDEC_VACTS_REG(base) ((base)->VACTS) +#define VDEC_VACTE_REG(base) ((base)->VACTE) +#define VDEC_HSTIP_REG(base) ((base)->HSTIP) +#define VDEC_BLSCRCR_REG(base) ((base)->BLSCRCR) +#define VDEC_BLSCRCB_REG(base) ((base)->BLSCRCB) +#define VDEC_LMAGC2_REG(base) ((base)->LMAGC2) +#define VDEC_CHAGC2_REG(base) ((base)->CHAGC2) +#define VDEC_MINTH_REG(base) ((base)->MINTH) +#define VDEC_VFRQOH_REG(base) ((base)->VFRQOH) +#define VDEC_VFRQOL_REG(base) ((base)->VFRQOL) +#define VDEC_ASYNCLKFREQ1_REG(base) ((base)->ASYNCLKFREQ1) +#define VDEC_ASYNCLKFREQ2_REG(base) ((base)->ASYNCLKFREQ2) +#define VDEC_ASYNCLKFREQ3_REG(base) ((base)->ASYNCLKFREQ3) +#define VDEC_ASYNCLKFREQ4_REG(base) ((base)->ASYNCLKFREQ4) + +/*! + * @} + */ /* end of group VDEC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- VDEC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup VDEC_Register_Masks VDEC Register Masks + * @{ + */ + +/* CFC1 Bit Fields */ +#define VDEC_CFC1_rc_combmode_override_MASK 0xFu +#define VDEC_CFC1_rc_combmode_override_SHIFT 0 +#define VDEC_CFC1_rc_combmode_override(x) (((uint32_t)(((uint32_t)(x))<WCR) +#define WDOG_WSR_REG(base) ((base)->WSR) +#define WDOG_WRSR_REG(base) ((base)->WRSR) +#define WDOG_WICR_REG(base) ((base)->WICR) +#define WDOG_WMCR_REG(base) ((base)->WMCR) + +/*! + * @} + */ /* end of group WDOG_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* WCR Bit Fields */ +#define WDOG_WCR_WDZST_MASK 0x1u +#define WDOG_WCR_WDZST_SHIFT 0 +#define WDOG_WCR_WDBG_MASK 0x2u +#define WDOG_WCR_WDBG_SHIFT 1 +#define WDOG_WCR_WDE_MASK 0x4u +#define WDOG_WCR_WDE_SHIFT 2 +#define WDOG_WCR_WDT_MASK 0x8u +#define WDOG_WCR_WDT_SHIFT 3 +#define WDOG_WCR_SRS_MASK 0x10u +#define WDOG_WCR_SRS_SHIFT 4 +#define WDOG_WCR_WDA_MASK 0x20u +#define WDOG_WCR_WDA_SHIFT 5 +#define WDOG_WCR_SRE_MASK 0x40u +#define WDOG_WCR_SRE_SHIFT 6 +#define WDOG_WCR_WDW_MASK 0x80u +#define WDOG_WCR_WDW_SHIFT 7 +#define WDOG_WCR_WT_MASK 0xFF00u +#define WDOG_WCR_WT_SHIFT 8 +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x))<MISC0) +#define XTALOSC24M_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL) +#define XTALOSC24M_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) +#define XTALOSC24M_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) +#define XTALOSC24M_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) +#define XTALOSC24M_OSC_CONFIG0_REG(base) ((base)->OSC_CONFIG0) +#define XTALOSC24M_OSC_CONFIG0_SET_REG(base) ((base)->OSC_CONFIG0_SET) +#define XTALOSC24M_OSC_CONFIG0_CLR_REG(base) ((base)->OSC_CONFIG0_CLR) +#define XTALOSC24M_OSC_CONFIG0_TOG_REG(base) ((base)->OSC_CONFIG0_TOG) +#define XTALOSC24M_OSC_CONFIG1_REG(base) ((base)->OSC_CONFIG1) +#define XTALOSC24M_OSC_CONFIG1_SET_REG(base) ((base)->OSC_CONFIG1_SET) +#define XTALOSC24M_OSC_CONFIG1_CLR_REG(base) ((base)->OSC_CONFIG1_CLR) +#define XTALOSC24M_OSC_CONFIG1_TOG_REG(base) ((base)->OSC_CONFIG1_TOG) +#define XTALOSC24M_OSC_CONFIG2_REG(base) ((base)->OSC_CONFIG2) +#define XTALOSC24M_OSC_CONFIG2_SET_REG(base) ((base)->OSC_CONFIG2_SET) +#define XTALOSC24M_OSC_CONFIG2_CLR_REG(base) ((base)->OSC_CONFIG2_CLR) +#define XTALOSC24M_OSC_CONFIG2_TOG_REG(base) ((base)->OSC_CONFIG2_TOG) + +/*! + * @} + */ /* end of group XTALOSC24M_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- XTALOSC24M Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC24M_Register_Masks XTALOSC24M Register Masks + * @{ + */ + +/* MISC0 Bit Fields */ +#define XTALOSC24M_MISC0_REFTOP_PWD_MASK 0x1u +#define XTALOSC24M_MISC0_REFTOP_PWD_SHIFT 0 +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_MASK 0x8u +#define XTALOSC24M_MISC0_REFTOP_SELFBIASOFF_SHIFT 3 +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_MASK 0x70u +#define XTALOSC24M_MISC0_REFTOP_VBGADJ_SHIFT 4 +#define XTALOSC24M_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x))<DS_ADDR) +#define uSDHC_BLK_ATT_REG(base) ((base)->BLK_ATT) +#define uSDHC_CMD_ARG_REG(base) ((base)->CMD_ARG) +#define uSDHC_CMD_XFR_TYP_REG(base) ((base)->CMD_XFR_TYP) +#define uSDHC_CMD_RSP0_REG(base) ((base)->CMD_RSP0) +#define uSDHC_CMD_RSP1_REG(base) ((base)->CMD_RSP1) +#define uSDHC_CMD_RSP2_REG(base) ((base)->CMD_RSP2) +#define uSDHC_CMD_RSP3_REG(base) ((base)->CMD_RSP3) +#define uSDHC_DATA_BUFF_ACC_PORT_REG(base) ((base)->DATA_BUFF_ACC_PORT) +#define uSDHC_PRES_STATE_REG(base) ((base)->PRES_STATE) +#define uSDHC_PROT_CTRL_REG(base) ((base)->PROT_CTRL) +#define uSDHC_SYS_CTRL_REG(base) ((base)->SYS_CTRL) +#define uSDHC_INT_STATUS_REG(base) ((base)->INT_STATUS) +#define uSDHC_INT_STATUS_EN_REG(base) ((base)->INT_STATUS_EN) +#define uSDHC_INT_SIGNAL_EN_REG(base) ((base)->INT_SIGNAL_EN) +#define uSDHC_AUTOCMD12_ERR_STATUS_REG(base) ((base)->AUTOCMD12_ERR_STATUS) +#define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP) +#define uSDHC_WTMK_LVL_REG(base) ((base)->WTMK_LVL) +#define uSDHC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) +#define uSDHC_FORCE_EVENT_REG(base) ((base)->FORCE_EVENT) +#define uSDHC_ADMA_ERR_STATUS_REG(base) ((base)->ADMA_ERR_STATUS) +#define uSDHC_ADMA_SYS_ADDR_REG(base) ((base)->ADMA_SYS_ADDR) +#define uSDHC_DLL_CTRL_REG(base) ((base)->DLL_CTRL) +#define uSDHC_DLL_STATUS_REG(base) ((base)->DLL_STATUS) +#define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base) ((base)->CLK_TUNE_CTRL_STATUS) +#define uSDHC_VEND_SPEC_REG(base) ((base)->VEND_SPEC) +#define uSDHC_MMC_BOOT_REG(base) ((base)->MMC_BOOT) +#define uSDHC_VEND_SPEC2_REG(base) ((base)->VEND_SPEC2) +#define uSDHC_TUNING_CTRL_REG(base) ((base)->TUNING_CTRL) + +/*! + * @} + */ /* end of group uSDHC_Register_Accessor_Macros */ + +/* ---------------------------------------------------------------------------- + -- uSDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup uSDHC_Register_Masks uSDHC Register Masks + * @{ + */ + +/* DS_ADDR Bit Fields */ +#define uSDHC_DS_ADDR_DS_ADDR_MASK 0xFFFFFFFCu +#define uSDHC_DS_ADDR_DS_ADDR_SHIFT 2 +#define uSDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x))<averageNumber != adcAvgNumNone) + { + ADC_GC_REG(base) |= ADC_GC_AVGE_MASK; + ADC_CFG_REG(base) |= ADC_CFG_AVGS(initConfig->averageNumber); + } + + /* Set resolution mode. */ + ADC_CFG_REG(base) |= ADC_CFG_MODE(initConfig->resolutionMode); + + /* Set clock source. */ + ADC_SetClockSource(base, initConfig->clockSource, initConfig->divideRatio); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_Deinit + * Description : This function reset ADC module register content to its + * default value. + * + *END**************************************************************************/ +void ADC_Deinit(ADC_Type* base) +{ + /* Reset ADC Module Register content to default value */ + ADC_HC0_REG(base) = ADC_HC0_ADCH_MASK; + ADC_HC1_REG(base) = ADC_HC1_ADCH_MASK; + ADC_R0_REG(base) = 0x0; + ADC_R1_REG(base) = 0x0; + ADC_CFG_REG(base) = ADC_CFG_ADSTS(2); + ADC_GC_REG(base) = 0x0; + ADC_GS_REG(base) = ADC_GS_CALF_MASK | ADC_GS_AWKST_MASK; + ADC_CV_REG(base) = 0x0; + ADC_OFS_REG(base) = 0x0; + ADC_CAL_REG(base) = 0x0; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertResultOverwrite + * Description : Enable or disable ADC overwrite conversion result register. + * + *END**************************************************************************/ +void ADC_SetConvertResultOverwrite(ADC_Type* base, bool enable) +{ + if(enable) + ADC_CFG_REG(base) |= ADC_CFG_OVWREN_MASK; + else + ADC_CFG_REG(base) &= ~ADC_CFG_OVWREN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertTrigMode + * Description : This function is used to set conversion trigger mode. + * + *END**************************************************************************/ +void ADC_SetConvertTrigMode(ADC_Type* base, uint8_t mode) +{ + assert(mode <= adcHardwareTrigger); + + if(mode == adcHardwareTrigger) + ADC_CFG_REG(base) |= ADC_CFG_ADTRG_MASK; + else + ADC_CFG_REG(base) &= ~ADC_CFG_ADTRG_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertSpeed + * Description : This function is used to set conversion speed mode. + * + *END**************************************************************************/ +void ADC_SetConvertSpeed(ADC_Type* base, uint8_t mode) +{ + assert(mode <= adcHighSpeed); + + if(mode == adcHighSpeed) + ADC_CFG_REG(base) |= ADC_CFG_ADHSC_MASK; + else + ADC_CFG_REG(base) &= ~ADC_CFG_ADHSC_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetSampleTimeDuration + * Description : This function is used to set sample time duration. + * + *END**************************************************************************/ +void ADC_SetSampleTimeDuration(ADC_Type* base, uint8_t duration) +{ + assert(duration <= adcSamplePeriodClock24); + + switch(duration) + { + case adcSamplePeriodClock2: + ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(0U); + break; + + case adcSamplePeriodClock4: + ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(1U); + break; + + case adcSamplePeriodClock6: + ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(2U); + break; + + case adcSamplePeriodClock8: + ADC_CFG_REG(base) &= ~ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(3U); + break; + + case adcSamplePeriodClock12: + ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(0U); + break; + + case adcSamplePeriodClock16: + ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(1U); + break; + + case adcSamplePeriodClock20: + ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(2U); + break; + + case adcSamplePeriodClock24: + ADC_CFG_REG(base) |= ADC_CFG_ADLSMP_MASK; + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADSTS_MASK)) | + ADC_CFG_ADSTS(3U); + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetPowerMode + * Description : This function is used to set power mode. + * + *END**************************************************************************/ +void ADC_SetPowerMode(ADC_Type* base, uint8_t powerMode) +{ + assert(powerMode <= adcLowPowerMode); + + if(powerMode == adcLowPowerMode) + ADC_CFG_REG(base) |= ADC_CFG_ADLPC_MASK; + else + ADC_CFG_REG(base) &= ~ADC_CFG_ADLPC_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetClockSource + * Description : This function is used to set ADC clock source. + * + *END**************************************************************************/ +void ADC_SetClockSource(ADC_Type* base, uint8_t source, uint8_t div) +{ + assert(source <= adcAsynClock); + assert(div <= adcInputClockDiv8); + + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADIV_MASK)) | + ADC_CFG_ADIV(div); + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_ADICLK_MASK)) | + ADC_CFG_ADICLK(source); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAsynClockOutput + * Description : This function is used to enable asynchronous clock source output + * regardless of the state of ADC. + * + *END**************************************************************************/ +void ADC_SetAsynClockOutput(ADC_Type* base, bool enable) +{ + if(enable) + ADC_GC_REG(base) |= ADC_GC_ADACKEN_MASK; + else + ADC_GC_REG(base) &= ~ADC_GC_ADACKEN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCalibration + * Description : Enable or disable calibration function. + * + *END**************************************************************************/ +void ADC_SetCalibration(ADC_Type* base, bool enable) +{ + if(enable) + ADC_GC_REG(base) |= ADC_GC_CAL_MASK; + else + ADC_GC_REG(base) &= ~ADC_GC_CAL_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertCmd + * Description : Enable continuous conversion and start a conversion on target channel. + * This function is only used for software trigger mode. If configured as + * hardware trigger mode, this function just enable continuous conversion + * and not start the conversion. + * + *END**************************************************************************/ +void ADC_SetConvertCmd(ADC_Type* base, uint8_t channel, bool enable) +{ + uint8_t triggerMode; + + /* Enable continuous conversion. */ + if(enable) + { + ADC_GC_REG(base) |= ADC_GC_ADCO_MASK; + /* Start the conversion. */ + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + ADC_HC0_REG(base) = (ADC_HC0_REG(base) & (~ADC_HC0_ADCH_MASK)) | + ADC_HC0_ADCH(channel); + else /* Just set the channel. */ + ADC_HC1_REG(base) = (ADC_HC1_REG(base) & (~ADC_HC1_ADCH_MASK)) | + ADC_HC1_ADCH(channel); + } + else + ADC_GC_REG(base) &= ~ADC_GC_ADCO_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_TriggerSingleConvert + * Description : Enable single conversion and trigger single time conversion + * on target imput channel. If configured as hardware trigger + * mode, this function just set input channel and not start a + * conversion. + * + *END**************************************************************************/ +void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t channel) +{ + uint8_t triggerMode; + + /* Enable single conversion. */ + ADC_GC_REG(base) &= ~ADC_GC_ADCO_MASK; + /* Start the conversion. */ + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + ADC_HC0_REG(base) = (ADC_HC0_REG(base) & (~ADC_HC0_ADCH_MASK)) | + ADC_HC0_ADCH(channel); + else /* Just set the channel. */ + ADC_HC1_REG(base) = (ADC_HC1_REG(base) & (~ADC_HC1_ADCH_MASK)) | + ADC_HC1_ADCH(channel); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAverageNum + * Description : This function is used to enable hardware aaverage function + * and set hardware average number. If avgNum is equal to + * adcAvgNumNone, it means disable hardware average function. + * + *END**************************************************************************/ +void ADC_SetAverageNum(ADC_Type* base, uint8_t avgNum) +{ + assert(avgNum <= adcAvgNumNone); + + if(avgNum != adcAvgNumNone) + { + /* Enable hardware average function. */ + ADC_GC_REG(base) |= ADC_GC_AVGE_MASK; + /* Set hardware average number. */ + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_AVGS_MASK)) | + ADC_CFG_AVGS(avgNum); + } + else + { + /* Disable hardware average function. */ + ADC_GC_REG(base) &= ~ADC_GC_AVGE_MASK; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_StopConvert + * Description : This function is used to stop all conversions. + * + *END**************************************************************************/ +void ADC_StopConvert(ADC_Type* base) +{ + uint8_t triggerMode; + + triggerMode = ADC_GetConvertTrigMode(base); + /* According trigger mode to set specific register. */ + if(triggerMode == adcSoftwareTrigger) + ADC_HC0_REG(base) |= ADC_HC0_ADCH_MASK; + else + ADC_HC1_REG(base) |= ADC_HC1_ADCH_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_GetConvertResult + * Description : This function is used to get conversion result. + * + *END**************************************************************************/ +uint16_t ADC_GetConvertResult(ADC_Type* base) +{ + uint8_t triggerMode; + + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + return (uint16_t)((ADC_R0_REG(base) & ADC_R0_D_MASK) >> ADC_R0_D_SHIFT); + else + return (uint16_t)((ADC_R1_REG(base) & ADC_R1_D_MASK) >> ADC_R1_D_SHIFT); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCmpMode + * Description : This function is used to enable compare function + * and set comparer mode. + * + *END**************************************************************************/ +void ADC_SetCmpMode(ADC_Type* base, uint8_t cmpMode, uint16_t cmpVal1, uint16_t cmpVal2) +{ + assert(cmpMode <= adcCmpModeDisable); + + switch(cmpMode) + { + case adcCmpModeLessThanCmpVal1: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) &= ~(ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + break; + + case adcCmpModeGreaterThanCmpVal1: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACFGT_MASK) & (~ADC_GC_ACREN_MASK); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + break; + + case adcCmpModeOutRangNotInclusive: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACREN_MASK) & (~ADC_GC_ACFGT_MASK); + if(cmpVal1 <= cmpVal2) + { + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2); + } + break; + + case adcCmpModeInRangNotInclusive: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) = (ADC_GC_REG(base) | ADC_GC_ACREN_MASK) & (~ADC_GC_ACFGT_MASK); + if(cmpVal1 > cmpVal2) + { + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2); + } + break; + + case adcCmpModeInRangInclusive: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) |= ADC_GC_ACREN_MASK | ADC_GC_ACFGT_MASK; + if(cmpVal1 <= cmpVal2) + { + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2); + } + break; + + case adcCmpModeOutRangInclusive: + ADC_GC_REG(base) |= ADC_GC_ACFE_MASK; + ADC_GC_REG(base) |= ADC_GC_ACREN_MASK | ADC_GC_ACFGT_MASK; + if(cmpVal1 > cmpVal2) + { + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV1_MASK)) | ADC_CV_CV1(cmpVal1); + ADC_CV_REG(base) = (ADC_CV_REG(base) & (~ADC_CV_CV2_MASK)) | ADC_CV_CV2(cmpVal2); + } + break; + + case adcCmpModeDisable: + ADC_GC_REG(base) &= ~ADC_GC_ACFE_MASK; + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCorrectionMode + * Description : This function is used to set offset correct mode. + * + *END**************************************************************************/ +void ADC_SetCorrectionMode(ADC_Type* base, bool correctMode) +{ + if(correctMode) + ADC_OFS_REG(base) |= ADC_OFS_SIGN_MASK; + else + ADC_OFS_REG(base) &= ~ADC_OFS_SIGN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetIntCmd + * Description : Enables or disables ADC conversion complete interrupt request. + * + *END**************************************************************************/ +void ADC_SetIntCmd(ADC_Type* base, bool enable) +{ + uint8_t triggerMode; + + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + { + if(enable) + ADC_HC0_REG(base) |= ADC_HC0_AIEN_MASK; + else + ADC_HC0_REG(base) &= ~ADC_HC0_AIEN_MASK; + } + else + { + if(enable) + ADC_HC1_REG(base) |= ADC_HC1_AIEN_MASK; + else + ADC_HC1_REG(base) &= ~ADC_HC1_AIEN_MASK; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_IsConvertComplete + * Description : This function is used to get ADC conversion complete status. + * + *END**************************************************************************/ +bool ADC_IsConvertComplete(ADC_Type* base) +{ + uint8_t triggerMode; + + triggerMode = ADC_GetConvertTrigMode(base); + if(triggerMode == adcSoftwareTrigger) + return (bool)((ADC_HS_REG(base) & ADC_HS_COCO0_MASK) >> ADC_HS_COCO0_SHIFT); + else + return (bool)((ADC_HS_REG(base) & ADC_HS_COCO1_MASK) >> ADC_HS_COCO1_SHIFT); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetDmaCmd + * Description : Enable or disable DMA request. + * + *END**************************************************************************/ +void ADC_SetDmaCmd(ADC_Type* base, bool enable) +{ + if (enable) + ADC_GC_REG(base) |= ADC_GC_DMAEN_MASK; + else + ADC_GC_REG(base) &= ~ADC_GC_DMAEN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX6X/drivers/adc_imx6sx.h b/devices/MCIMX6X/drivers/adc_imx6sx.h new file mode 100644 index 000000000..2b8f794c0 --- /dev/null +++ b/devices/MCIMX6X/drivers/adc_imx6sx.h @@ -0,0 +1,513 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ADC_IMX6SX_H__ +#define __ADC_IMX6SX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup adc_imx6sx_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief ADC module initialize structure. */ +typedef struct _adc_init_config +{ + uint8_t clockSource; /*!< Select input clock source to generate the internal conversion clock.*/ + uint8_t divideRatio; /*!< Selects divide ratio used to generate the internal conversion clock.*/ + uint8_t averageNumber; /*!< The average number for hardware average function.*/ + uint8_t resolutionMode; /*!< Set ADC resolution mode.*/ +} adc_init_config_t; + +/*! @brief ADC hardware average number. */ +enum _adc_average_number +{ + adcAvgNum4 = 0U, /*!< ADC Hardware Average Number is set to 4.*/ + adcAvgNum8 = 1U, /*!< ADC Hardware Average Number is set to 8.*/ + adcAvgNum16 = 2U, /*!< ADC Hardware Average Number is set to 16.*/ + adcAvgNum32 = 3U, /*!< ADC Hardware Average Number is set to 32.*/ + adcAvgNumNone = 4U, /*!< Disable ADC Hardware Average.*/ +}; + +/*! @brief ADC conversion trigger select. */ +enum _adc_convert_trigger_mode +{ + adcSoftwareTrigger = 0U, /*!< ADC software trigger a conversion.*/ + adcHardwareTrigger = 1U, /*!< ADC hardware trigger a conversion.*/ +}; + +/*! @brief ADC conversion speed configure. */ +enum _adc_convert_speed_config +{ + adcNormalSpeed = 0U, /*!< ADC set as normal conversion speed.*/ + adcHighSpeed = 1U, /*!< ADC set as high conversion speed.*/ +}; + +/*! @brief ADC sample time duration. */ +enum _adc_sample_time_duration +{ + adcSamplePeriodClock2, /*!< The sample time duration is set as 2 ADC clocks.*/ + adcSamplePeriodClock4, /*!< The sample time duration is set as 4 ADC clocks.*/ + adcSamplePeriodClock6, /*!< The sample time duration is set as 6 ADC clocks.*/ + adcSamplePeriodClock8, /*!< The sample time duration is set as 8 ADC clocks.*/ + adcSamplePeriodClock12, /*!< The sample time duration is set as 12 ADC clocks.*/ + adcSamplePeriodClock16, /*!< The sample time duration is set as 16 ADC clocks.*/ + adcSamplePeriodClock20, /*!< The sample time duration is set as 20 ADC clocks.*/ + adcSamplePeriodClock24, /*!< The sample time duration is set as 24 ADC clocks.*/ +}; + +/*! @brief ADC low power configure. */ +enum _adc_power_mode +{ + adcNormalPowerMode = 0U, /*!< ADC hard block set as normal power mode.*/ + adcLowPowerMode = 1U, /*!< ADC hard block set as low power mode.*/ +}; + +/*! @brief ADC conversion resolution mode. */ +enum _adc_resolution_mode +{ + adcResolutionBit8 = 0U, /*!< ADC resolution set as 8 bit conversion mode.*/ + adcResolutionBit10 = 1U, /*!< ADC resolution set as 10 bit conversion mode.*/ + adcResolutionBit12 = 2U, /*!< ADC resolution set as 12 bit conversion mode.*/ +}; + +/*! @brief ADC input clock divide. */ +enum _adc_clock_divide +{ + adcInputClockDiv1 = 0U, /*!< Input clock divide 1 to generate internal clock.*/ + adcInputClockDiv2 = 1U, /*!< Input clock divide 2 to generate internal clock.*/ + adcInputClockDiv4 = 2U, /*!< Input clock divide 4 to generate internal clock.*/ + adcInputClockDiv8 = 3U, /*!< Input clock divide 8 to generate internal clock.*/ +}; + +/*! @brief ADC clock source. */ +enum _adc_clock_source +{ + adcIpgClock = 0U, /*!< Select ipg clock as input clock source.*/ + adcIpgClockDivide2 = 1U, /*!< Select ipg clock divide 2 as input clock source.*/ + adcAsynClock = 3U, /*!< Select asynchronous clock as input clock source.*/ +}; + +/*! @brief ADC comparer work mode configuration. */ +enum _adc_compare_mode +{ + adcCmpModeLessThanCmpVal1, /*!< Compare true if the result is less than compare value 1.*/ + adcCmpModeGreaterThanCmpVal1, /*!< Compare true if the result is greater than or equal to compare value 1.*/ + adcCmpModeOutRangNotInclusive, /*!< Compare true if the result is less than compare value 1 or the result is Greater than compare value 2.*/ + adcCmpModeInRangNotInclusive, /*!< Compare true if the result is less than compare value 1 and the result is greater than compare value 2.*/ + adcCmpModeInRangInclusive, /*!< Compare true if the result is greater than or equal to compare value 1 and the result is less than or equal to compare value 2.*/ + adcCmpModeOutRangInclusive, /*!< Compare true if the result is greater than or equal to compare value 1 or the result is less than or equal to compare value 2.*/ + adcCmpModeDisable, /*!< ADC compare function disable.*/ +}; + +/*! @brief ADC general status flag. */ +enum _adc_general_status_flag +{ + adcFlagAsynWakeUpInt = 1U << 0, /*!< Indicate asynchronous wake up interrupt occurred in stop mode.*/ + adcFlagCalibrateFailed = 1U << 1, /*!< Indicate the result of the calibration sequence.*/ + adcFlagConvertActive = 1U << 2, /*!< Indicate a conversion is in the process.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name ADC Module Initialization and Configuration Functions. + * @{ + */ + +/*! + * @brief Initialize ADC to reset state and initialize with initialize structure. + * + * @param base ADC base pointer. + * @param initConfig ADC initialize structure. + */ +void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig); + +/*! + * @brief This function reset ADC module register content to its default value. + * + * @param base ADC base pointer. + */ +void ADC_Deinit(ADC_Type* base); + +/*! + * @brief Enable or disable ADC module overwrite conversion result. + * + * @param base ADC base pointer. + * @param enable Enable/Disable conversion result overwire function. + * - true: Enable conversion result overwire. + * - false: Disable conversion result overwrite. + */ +void ADC_SetConvertResultOverwrite(ADC_Type* base, bool enable); + +/*! + * @brief This function set ADC module conversion trigger mode. + * + * @param base ADC base pointer. + * @param mode Conversion trigger (see @ref _adc_convert_trigger_mode enumeration). + */ +void ADC_SetConvertTrigMode(ADC_Type* base, uint8_t mode); + +/*! + * @brief This function is used to get conversion trigger mode. + * + * @param base ADC base pointer. + * @return Conversion trigger mode (see @ref _adc_convert_trigger_mode enumeration). + */ +static inline uint8_t ADC_GetConvertTrigMode(ADC_Type* base) +{ + return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADTRG_MASK) >> ADC_CFG_ADTRG_SHIFT); +} + +/*! + * @brief This function set ADC module conversion speed mode. + * + * @param base ADC base pointer. + * @param mode Conversion speed mode (see @ref _adc_convert_speed_config enumeration). + */ +void ADC_SetConvertSpeed(ADC_Type* base, uint8_t mode); + +/*! + * @brief This function get ADC module conversion speed mode. + * + * @param base ADC base pointer. + * @return Conversion speed mode. + */ +static inline uint8_t ADC_GetConvertSpeed(ADC_Type* base) +{ + return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADHSC_MASK) >> ADC_CFG_ADHSC_SHIFT); +} + +/*! + * @brief This function set ADC module sample time duration. + * + * @param base ADC base pointer. + * @param duration Sample time duration (see @ref _adc_sample_time_duration enumeration). + */ +void ADC_SetSampleTimeDuration(ADC_Type* base, uint8_t duration); + +/*! + * @brief This function set ADC module power mode. + * + * @param base ADC base pointer. + * @param powerMode power mode (see @ref _adc_power_mode enumeration). + */ +void ADC_SetPowerMode(ADC_Type* base, uint8_t powerMode); + +/*! + * @brief This function get ADC module power mode. + * + * @param base ADC base pointer. + * @return Power mode. + */ +static inline uint8_t ADC_GetPowerMode(ADC_Type* base) +{ + return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_ADLPC_MASK) >> ADC_CFG_ADLPC_SHIFT); +} + +/*! + * @brief This function set ADC module clock source. + * + * @param base ADC base pointer. + * @param source Conversion clock source (see @ref _adc_clock_source enumeration). + * @param div Input clock divide ratio (see @ref _adc_clock_divide enumeration). + */ +void ADC_SetClockSource(ADC_Type* base, uint8_t source, uint8_t div); + +/*! + * @brief This function enable asynchronous clock source output regardless of the + * state of ADC and input clock select of ADC module. Setting this bit + * allows the clock to be used even while the ADC is idle or operating from + * a different clock source. + * + * @param base ADC base pointer. + * @param enable Asynchronous clock output enable. + * - true: Enable asynchronous clock output regardless of the state of ADC; + * - false: Only enable if selected as ADC input clock source and a + * ADC conversion is active. + */ +void ADC_SetAsynClockOutput(ADC_Type* base, bool enable); + +/*@}*/ + +/*! + * @name ADC Calibration Control Functions. + * @{ + */ + +/*! + * @brief This function is used to enable or disable calibration function. + * + * @param base ADC base pointer. + * @param enable Enable/Disable calibration function. + * - true: Enable calibration function. + * - false: Disable calibration function. + */ +void ADC_SetCalibration(ADC_Type* base, bool enable); + +/*! + * @brief This function is used to get calibrate result value. + * + * @param base ADC base pointer. + * @return Calibration result value. + */ +static inline uint8_t ADC_GetCalibrationResult(ADC_Type* base) +{ + return (uint8_t)((ADC_CAL_REG(base) & ADC_CAL_CAL_CODE_MASK) >> ADC_CAL_CAL_CODE_SHIFT); +} + +/*@}*/ + +/*! + * @name ADC Module Conversion Control Functions. + * @{ + */ + +/*! + * @brief Enable continuous conversion and start a conversion on target channel. + * This function is only used for software trigger mode. If configured as + * hardware trigger mode, this function just enable continuous conversion mode + * and not start the conversion. + * + * @param base ADC base pointer. + * @param channel Input channel selection. + * @param enable Enable/Disable continuous conversion. + * - true: Enable and start continuous conversion. + * - false: Disable continuous conversion. + */ +void ADC_SetConvertCmd(ADC_Type* base, uint8_t channel, bool enable); + +/*! + * @brief Enable single conversion and trigger single time conversion + * on target input channel.If configured as hardware trigger + * mode, this function just set input channel and not start a + * conversion. + * + * @param base ADC base pointer. + * @param channel Input channel selection. + */ +void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t channel); + +/*! + * @brief Enable hardware average function and set hardware average number. + * + * @param base ADC base pointer. + * @param avgNum Hardware average number (see @ref _adc_average_number enumeration). + * If avgNum is equal to adcAvgNumNone, it means disable hardware + * average function. + */ +void ADC_SetAverageNum(ADC_Type* base, uint8_t avgNum); + +/*! + * @brief Set conversion resolution mode. + * + * @param base ADC base pointer. + * @param mode resolution mode (see @ref _adc_resolution_mode enumeration). + */ +static inline void ADC_SetResolutionMode(ADC_Type* base, uint8_t mode) +{ + assert(mode <= adcResolutionBit12); + + ADC_CFG_REG(base) = (ADC_CFG_REG(base) & (~ADC_CFG_MODE_MASK)) | + ADC_CFG_MODE(mode); +} + +/*! + * @brief Set conversion resolution mode. + * + * @param base ADC base pointer. + * @return Resolution mode (see @ref _adc_resolution_mode enumeration). + */ +static inline uint8_t ADC_GetResolutionMode(ADC_Type* base) +{ + return (uint8_t)((ADC_CFG_REG(base) & ADC_CFG_MODE_MASK) >> ADC_CFG_MODE_SHIFT); +} + +/*! + * @brief Set conversion disabled. + * + * @param base ADC base pointer. + */ +void ADC_StopConvert(ADC_Type* base); + +/*! + * @brief Get right aligned conversion result. + * + * @param base ADC base pointer. + * @return Conversion result. + */ +uint16_t ADC_GetConvertResult(ADC_Type* base); + +/*@}*/ + +/*! + * @name ADC Comparer Control Functions. + * @{ + */ + +/*! + * @brief Enable compare function and set the compare work mode of ADC module. + * If cmpMode is equal to adcCmpModeDisable, it means to disable the compare function. + * @param base ADC base pointer. + * @param cmpMode Comparer work mode selected (see @ref _adc_compare_mode enumeration). + * - adcCmpModeLessThanCmpVal1: only set compare value 1; + * - adcCmpModeGreaterThanCmpVal1: only set compare value 1; + * - adcCmpModeOutRangNotInclusive: set compare value 1 less than or equal to compare value 2; + * - adcCmpModeInRangNotInclusive: set compare value 1 greater than compare value 2; + * - adcCmpModeInRangInclusive: set compare value 1 less than or equal to compare value 2; + * - adcCmpModeOutRangInclusive: set compare value 1 greater than compare value 2; + * - adcCmpModeDisable: unnecessary to set compare value 1 and compare value 2. + * @param cmpVal1 Compare threshold 1. + * @param cmpVal2 Compare threshold 2. + */ +void ADC_SetCmpMode(ADC_Type* base, uint8_t cmpMode, uint16_t cmpVal1, uint16_t cmpVal2); + +/*@}*/ + +/*! + * @name Offset Correction Control Functions. + * @{ + */ + +/*! + * @brief Set ADC module offset correct mode. + * + * @param base ADC base pointer. + * @param correctMode Offset correct mode. + * - true: The offset value is subtracted from the raw converted value; + * - false: The offset value is added with the raw result. + */ +void ADC_SetCorrectionMode(ADC_Type* base, bool correctMode); + +/*! + * @brief Set ADC module offset value. + * + * @param base ADC base pointer. + * @param val Offset value. + */ +static inline void ADC_SetOffsetVal(ADC_Type* base, uint16_t val) +{ + ADC_OFS_REG(base) = (ADC_OFS_REG(base) & (~ADC_OFS_OFS_MASK)) | + ADC_OFS_OFS(val); +} + +/*@}*/ + +/*! + * @name Interrupt and Flag Control Functions. + * @{ + */ + +/*! + * @brief Enables or disables ADC conversion complete interrupt request. + * + * @param base ADC base pointer. + * @param enable Enable/Disable ADC conversion complete interrupt. + * - true: Enable conversion complete interrupt. + * - false: Disable conversion complete interrupt. + */ +void ADC_SetIntCmd(ADC_Type* base, bool enable); + +/*! + * @brief Gets the ADC module conversion complete status flag state. + * + * @param base ADC base pointer. + * @retval true: A conversion is completed. + * @retval false: A conversion is not completed. + */ +bool ADC_IsConvertComplete(ADC_Type* base); + +/*! + * @brief Gets the ADC module general status flag state. + * + * @param base ADC base pointer. + * @param flags ADC status flag mask (see @ref _adc_general_status_flag enumeration). + * @return ADC status, each bit represents one status flag. + */ +static inline uint32_t ADC_GetStatusFlag(ADC_Type* base, uint32_t flags) +{ + return (uint32_t)(ADC_GS_REG(base) & flags); +} + +/*! + * @brief Clear one or more ADC status flag state. + * + * @param base ADC base pointer. + * @param flags ADC status flag mask (see @ref _adc_general_status_flag enumeration). + */ +static inline void ADC_ClearStatusFlag(ADC_Type* base, uint32_t flags) +{ + assert(flags < adcFlagConvertActive); + ADC_GS_REG(base) = flags; +} + +/*@}*/ + +/*! + * @name DMA Control Functions. + * @{ + */ + +/*! + * @brief Enable or Disable DMA request. + * + * @param base ADC base pointer. + * @param enable Enable/Disable ADC DMA request. + * - true: Enable DMA request. + * - false: Disable DMA request. + */ +void ADC_SetDmaCmd(ADC_Type* base, bool enable); + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __ADC_IMX6SX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX6X/drivers/ccm_analog_imx6sx.c b/devices/MCIMX6X/drivers/ccm_analog_imx6sx.c new file mode 100644 index 000000000..c0b417560 --- /dev/null +++ b/devices/MCIMX6X/drivers/ccm_analog_imx6sx.c @@ -0,0 +1,192 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ccm_analog_imx6sx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_PowerUpPll + * Description : Power up PLL. + * + *END**************************************************************************/ +void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + /* Judge PLL_USB1 and PLL_USB2 according to register offset value. + Because the definition of power control bit is different from the other PLL.*/ + if((CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x10) || (CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x20)) + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); + else + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_PowerDownPll + * Description : Power down PLL. + * + *END**************************************************************************/ +void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + /* Judge PLL_USB1 and PLL_USB2 according to register offset value. + Because the definition of power control bit is different from the other PLL.*/ + if((CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x10) || (CCM_ANALOG_TUPLE_OFFSET(pllControl) == 0x20)) + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); + else + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_SetPllBypass + * Description : PLL bypass setting. + * + *END**************************************************************************/ +void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllControl, bool bypass) +{ + if(bypass) + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK; + else + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetPllFreq + * Description : Get PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetPllFreq(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + uint8_t divSelect; + float numerator, denomitor; + uint32_t hz = 0; + + if (CCM_ANALOG_IsPllBypassed(base, pllControl)) + return 24000000; + + switch(CCM_ANALOG_TUPLE_OFFSET(pllControl)) + { + /* Get PLL_ARM frequency. */ + case 0x0: + { + divSelect = CCM_ANALOG_PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK; + hz = 24000000 * divSelect / 2; + break; + } + /* Get PLL_USB1(PLL3) frequency. */ + case 0x10: + { + divSelect = CCM_ANALOG_PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK; + if(divSelect == 0) + hz = 480000000; + else if(divSelect == 1) + hz = 528000000; + break; + } + /* Get PLL_USB2 frequency. */ + case 0x20: + { + divSelect = CCM_ANALOG_PLL_USB2 & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK; + if(divSelect == 0) + hz = 480000000; + else if(divSelect == 1) + hz = 528000000; + break; + } + /* Get PLL_SYS(PLL2) frequency. */ + case 0x30: + { + divSelect = CCM_ANALOG_PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK; + if(divSelect == 0) + hz = 480000000; + else + hz = 528000000; + break; + } + /* Get PLL_AUDIO frequency. */ + case 0x70: + { + divSelect = CCM_ANALOG_PLL_AUDIO & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK; + numerator = CCM_ANALOG_PLL_AUDIO_NUM & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK; + denomitor = CCM_ANALOG_PLL_AUDIO_DENOM & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK; + hz = (uint32_t)(24000000 * (divSelect + (numerator / denomitor))); + break; + } + /* Get PLL_VIDEO frequency. */ + case 0xA0: + { + divSelect = CCM_ANALOG_PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK; + numerator = CCM_ANALOG_PLL_VIDEO_NUM & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK; + denomitor = CCM_ANALOG_PLL_VIDEO_DENOM & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK; + hz = (uint32_t)(24000000 * (divSelect + (numerator / denomitor))); + break; + } + } + return hz; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetPfdFreq + * Description : Get PFD frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac) +{ + uint32_t main, frac; + + /* Judge whether pfdFrac is PLL2 PFD or not. */ + if(CCM_ANALOG_TUPLE_OFFSET(pfdFrac) == 0x100) + { + /* PFD should work with PLL2 without bypass */ + assert(!CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllSysControl)); + main = CCM_ANALOG_GetPllFreq(base, ccmAnalogPllSysControl); + } + else if(CCM_ANALOG_TUPLE_OFFSET(pfdFrac) == 0xF0) + { + /* PFD should work with PLL3 without bypass */ + assert(!CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllUsb1Control)); + main = CCM_ANALOG_GetPllFreq(base, ccmAnalogPllUsb1Control); + } + else + main = 0; + + frac = CCM_ANALOG_GetPfdFrac(base, pfdFrac); + + return main / frac * 18; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX6X/drivers/ccm_analog_imx6sx.h b/devices/MCIMX6X/drivers/ccm_analog_imx6sx.h new file mode 100644 index 000000000..fdec7e08f --- /dev/null +++ b/devices/MCIMX6X/drivers/ccm_analog_imx6sx.h @@ -0,0 +1,340 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCM_ANALOG_IMX6SX_H__ +#define __CCM_ANALOG_IMX6SX_H__ + +#include +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ccm_analog_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_ANALOG_TUPLE(reg, shift) ((offsetof(CCM_ANALOG_Type, reg) & 0xFFFF) | ((shift) << 16)) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) (*((volatile uint32_t *)((uint32_t)base + ((tuple) & 0xFFFF) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0) +#define CCM_ANALOG_TUPLE_REG_SET(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 4) +#define CCM_ANALOG_TUPLE_REG_CLR(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 8) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((tuple) >> 16) & 0x1F) +#define CCM_ANALOG_TUPLE_OFFSET(tuple) ((tuple) & 0xFFFF) + +/*! + * @brief PLL control names for PLL power/bypass/lock/frequency operations. + * + * These constants define the PLL control names for PLL power/bypass/lock operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Powerdown/Power bit shift. + */ +enum _ccm_analog_pll_control +{ + ccmAnalogPllArmControl = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT), /*!< CCM Analog ARM PLL Control.*/ + ccmAnalogPllUsb1Control = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_POWER_SHIFT), /*!< CCM Analog USB1 PLL Control.*/ + ccmAnalogPllUsb2Control = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_POWER_SHIFT), /*!< CCM Analog USB2 PLL Control.*/ + ccmAnalogPllSysControl = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT), /*!< CCM Analog SYSTEM PLL Control.*/ + ccmAnalogPllAudioControl = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT), /*!< CCM Analog AUDIO PLL Control.*/ + ccmAnalogPllVideoControl = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT), /*!< CCM Analog VIDEO PLL Control.*/ + ccmAnalogPllEnetControl = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT), /*!< CCM Analog ETHERNET PLL Control.*/ +}; + +/*! + * @brief PLL clock names for clock enable/disable settings. + * + * These constants define the PLL clock names for PLL clock enable/disable operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock enable bit shift. + */ +enum _ccm_analog_pll_clock +{ + ccmAnalogPllArmClock = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_SHIFT), /*!< CCM Analog ARM PLL Clock.*/ + ccmAnalogPllUsb1Clock = CCM_ANALOG_TUPLE(PLL_USB1, CCM_ANALOG_PLL_USB1_ENABLE_SHIFT), /*!< CCM Analog USB1 PLL Clock.*/ + ccmAnalogPllUsb2Clock = CCM_ANALOG_TUPLE(PLL_USB2, CCM_ANALOG_PLL_USB2_ENABLE_SHIFT), /*!< CCM Analog USB2 PLL Clock.*/ + ccmAnalogPllSysClock = CCM_ANALOG_TUPLE(PLL_SYS, CCM_ANALOG_PLL_SYS_ENABLE_SHIFT), /*!< CCM Analog SYSTEM PLL Clock.*/ + ccmAnalogPllAudioClock = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT), /*!< CCM Analog AUDIO PLL Clock.*/ + ccmAnalogPllVideoClock = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT), /*!< CCM Analog VIDEO PLL Clock.*/ + ccmAnalogPllEnetClock25Mhz = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT), /*!< CCM Analog ETHERNET 25MHz PLL Clock.*/ + ccmAnalogPllEnet2Clock125Mhz = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET2_125M_EN_SHIFT), /*!< CCM Analog ETHERNET2 125MHz PLL Clock.*/ + ccmAnalogPllEnet1Clock125Mhz = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENET1_125M_EN_SHIFT), /*!< CCM Analog ETHERNET1 125MHz PLL Clock.*/ +}; + +/*! + * @brief PFD gate names for clock gate settings, clock source is PLL2 and PLL3 + * + * These constants define the PFD gate names for PFD clock enable/disable operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock gate bit shift. + */ +enum _ccm_analog_pfd_clkgate +{ + ccmAnalogPll2Pfd0ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD0 Clock Gate.*/ + ccmAnalogPll2Pfd1ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD1 Clock Gate.*/ + ccmAnalogPll2Pfd2ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD2 Clock Gate.*/ + ccmAnalogPll2Pfd3ClkGate = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT), /*!< CCM Analog PLL2 PFD3 Clock Gate.*/ + ccmAnalogPll3Pfd0ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD0 Clock Gate.*/ + ccmAnalogPll3Pfd1ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD1 Clock Gate.*/ + ccmAnalogPll3Pfd2ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD2 Clock Gate.*/ + ccmAnalogPll3Pfd3ClkGate = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT), /*!< CCM Analog PLL3 PFD3 Clock Gate.*/ +}; + +/*! + * @brief PFD fraction names for clock fractional divider operations. + * + * These constants define the PFD fraction names for PFD fractional divider operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Fraction bits shift + */ +enum _ccm_analog_pfd_frac +{ + ccmAnalogPll2Pfd0Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD0 fractional divider.*/ + ccmAnalogPll2Pfd1Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD1 fractional divider.*/ + ccmAnalogPll2Pfd2Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD2 fractional divider.*/ + ccmAnalogPll2Pfd3Frac = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT), /*!< CCM Analog PLL2 PFD3 fractional divider.*/ + ccmAnalogPll3Pfd0Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD0 fractional divider.*/ + ccmAnalogPll3Pfd1Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD1 fractional divider.*/ + ccmAnalogPll3Pfd2Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD2 fractional divider.*/ + ccmAnalogPll3Pfd3Frac = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT), /*!< CCM Analog PLL3 PFD3 fractional divider.*/ +}; + +/*! + * @brief PFD stable names for clock stable query + * + * These constants define the PFD stable names for clock stable query.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Stable bit shift. + */ +enum _ccm_analog_pfd_stable +{ + ccmAnalogPll2Pfd0Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD0 clock stable query.*/ + ccmAnalogPll2Pfd1Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD1 clock stable query.*/ + ccmAnalogPll2Pfd2Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD2 clock stable query.*/ + ccmAnalogPll2Pfd3Stable = CCM_ANALOG_TUPLE(PFD_528, CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT), /*!< CCM Analog PLL2 PFD3 clock stable query.*/ + ccmAnalogPll3Pfd0Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD0 clock stable query.*/ + ccmAnalogPll3Pfd1Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD1 clock stable query.*/ + ccmAnalogPll3Pfd2Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD2 clock stable query.*/ + ccmAnalogPll3Pfd3Stable = CCM_ANALOG_TUPLE(PFD_480, CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT), /*!< CCM Analog PLL3 PFD3 clock stable query.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CCM Analog PLL Operation Functions + * @{ + */ + +/*! + * @brief Power up PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + */ +void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllControl); + +/*! + * @brief Power down PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + */ +void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllControl); + +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false: Do not bypass the PLL. + */ +void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllControl, bool bypass); + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CCM_ANALOG_IsPllBypassed(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_BYPASS_MASK); +} + +/*! + * @brief Check if PLL clock is locked + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL lock status. + * - true: The PLL is locked. + * - false: The PLL is not locked. + */ +static inline bool CCM_ANALOG_IsPllLocked(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_LOCK_MASK); +} + +/*! + * @brief Enable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) + */ +static inline void CCM_ANALOG_EnablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock); +} + +/*! + * @brief Disable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) + */ +static inline void CCM_ANALOG_DisablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock); +} + +/*! + * @brief Get PLL(involved all PLLs) clock frequency. + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL clock frequency in HZ. + */ +uint32_t CCM_ANALOG_GetPllFreq(CCM_ANALOG_Type * base, uint32_t pllControl); + +/*@}*/ + +/*! + * @name CCM Analog PFD Operation Functions + * @{ + */ + +/*! + * @brief Enable PFD clock + * + * @param base CCM_ANALOG base pointer. + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) + */ +static inline void CCM_ANALOG_EnablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate); +} + +/*! + * @brief Disable PFD clock + * + * @param base CCM_ANALOG base pointer. + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) + */ +static inline void CCM_ANALOG_DisablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate); +} + +/*! + * @brief Check if PFD clock is stable + * + * @param base CCM_ANALOG base pointer. + * @param pfdStable PFD stable identifier (see @ref _ccm_analog_pfd_stable enumeration) + * @return PFD clock stable status. + * - true: The PFD clock is stable. + * - false: The PFD clock is not stable. + */ +static inline bool CCM_ANALOG_IsPfdStable(CCM_ANALOG_Type * base, uint32_t pfdStable) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pfdStable) & (1 << CCM_ANALOG_TUPLE_SHIFT(pfdStable))); +} + + +/*! + * @brief Set PFD clock fraction + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @param value PFD clock fraction value + */ +static inline void CCM_ANALOG_SetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac, uint32_t value) +{ + assert(value >= 12 && value <= 35); + CCM_ANALOG_TUPLE_REG_CLR(base, pfdFrac) = CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK << CCM_ANALOG_TUPLE_SHIFT(pfdFrac); + CCM_ANALOG_TUPLE_REG_SET(base, pfdFrac) = value << CCM_ANALOG_TUPLE_SHIFT(pfdFrac); +} + +/*! + * @brief Get PFD clock fraction + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @return PFD clock fraction value + */ +static inline uint32_t CCM_ANALOG_GetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac) +{ + return (CCM_ANALOG_TUPLE_REG(base, pfdFrac) >> CCM_ANALOG_TUPLE_SHIFT(pfdFrac)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK; +} + +/*! + * @brief Get PFD clock frequency + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @return PFD clock frequency in HZ + */ +uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CCM_ANALOG_IMX6SX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX6X/drivers/ccm_imx6sx.c b/devices/MCIMX6X/drivers/ccm_imx6sx.c new file mode 100644 index 000000000..27b2c8e17 --- /dev/null +++ b/devices/MCIMX6X/drivers/ccm_imx6sx.c @@ -0,0 +1,67 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ccm_imx6sx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_SetClockEnableSignalOverrided + * Description : Override or do not override clock enable signal from module. + * + *END**************************************************************************/ +void CCM_SetClockEnableSignalOverrided(CCM_Type * base, uint32_t signal, bool control) +{ + if(control) + CCM_CMEOR_REG(base) |= signal; + else + CCM_CMEOR_REG(base) &= ~signal; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_SetMmdcHandshakeMask + * Description : Set handshake mask of MMDC module. + * + *END**************************************************************************/ +void CCM_SetMmdcHandshakeMask(CCM_Type * base, bool mask) +{ + if(mask) + CCM_CCDR_REG(base) |= CCM_CCDR_mmdc_mask_MASK; + else + CCM_CCDR_REG(base) &= ~CCM_CCDR_mmdc_mask_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX6X/drivers/ccm_imx6sx.h b/devices/MCIMX6X/drivers/ccm_imx6sx.h new file mode 100644 index 000000000..17546e8fa --- /dev/null +++ b/devices/MCIMX6X/drivers/ccm_imx6sx.h @@ -0,0 +1,785 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCM_IMX6SX_H__ +#define __CCM_IMX6SX_H__ + +#include +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ccm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_TUPLE(reg, shift, mask) ((offsetof(CCM_Type, reg) & 0xFF) | ((shift) << 8) | (((mask >> shift) & 0xFFFF) << 16)) +#define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)((uint32_t)base + ((tuple) & 0xFF)))) +#define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8) & 0x1F) +#define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 16) & 0xFFFF) << ((((tuple) >> 8) & 0x1F)))) + +/*! + * @brief Root control names for root clock setting. + * + * These constants define the root control names for root clock setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root clock setting bit field shift. + * - 16:31: Root clock setting bit field width. + */ +enum _ccm_root_clock_control +{ + ccmRootPll1SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll1_sw_clk_sel_SHIFT, CCM_CCSR_pll1_sw_clk_sel_MASK), /*!< PLL1 SW Clock control name.*/ + ccmRootStepSel = CCM_TUPLE(CCSR, CCM_CCSR_step_sel_SHIFT, CCM_CCSR_step_sel_MASK), /*!< Step SW Clock control name.*/ + ccmRootPeriph2ClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph2_clk_sel_SHIFT, CCM_CBCDR_periph2_clk_sel_MASK), /*!< Peripheral2 Clock control name.*/ + ccmRootPrePeriph2ClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pre_periph2_clk_sel_SHIFT, CCM_CBCMR_pre_periph2_clk_sel_MASK), /*!< Pre Peripheral2 Clock control name.*/ + ccmRootPeriph2Clk2Sel = CCM_TUPLE(CBCMR, CCM_CBCMR_periph2_clk2_sel_SHIFT, CCM_CBCMR_periph2_clk2_sel_MASK), /*!< Peripheral2 Clock2 Clock control name.*/ + ccmRootPll3SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll3_sw_clk_sel_SHIFT, CCM_CCSR_pll3_sw_clk_sel_MASK), /*!< PLL3 SW Clock control name.*/ + ccmRootOcramClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_clk_sel_SHIFT, CCM_CBCDR_ocram_clk_sel_MASK), /*!< OCRAM Clock control name.*/ + ccmRootOcramAltClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_alt_clk_sel_SHIFT, CCM_CBCDR_ocram_alt_clk_sel_MASK), /*!< OCRAM ALT Clock control name.*/ + ccmRootPeriphClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph_clk_sel_SHIFT, CCM_CBCDR_periph_clk_sel_MASK), /*!< Peripheral Clock control name.*/ + ccmRootPeriphClk2Sel = CCM_TUPLE(CBCMR, CCM_CBCMR_periph_clk2_sel_SHIFT, CCM_CBCMR_periph_clk2_sel_MASK), /*!< Peripheral Clock2 control name.*/ + ccmRootPrePeriphClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pre_periph_clk_sel_SHIFT, CCM_CBCMR_pre_periph_clk_sel_MASK), /*!< Pre Peripheral Clock control name.*/ + ccmRootPcieAxiClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pcie_axi_clk_sel_SHIFT, CCM_CBCMR_pcie_axi_clk_sel_MASK), /*!< PCIE AXI Clock control name.*/ + ccmRootPerclkClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_perclk_clk_sel_SHIFT, CCM_CSCMR1_perclk_clk_sel_MASK), /*!< Pre Clock control name.*/ + ccmRootUsdhc1ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc1_clk_sel_SHIFT, CCM_CSCMR1_usdhc1_clk_sel_MASK), /*!< USDHC1 Clock control name.*/ + ccmRootUsdhc2ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc2_clk_sel_SHIFT, CCM_CSCMR1_usdhc2_clk_sel_MASK), /*!< USDHC2 Clock control name.*/ + ccmRootUsdhc3ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc3_clk_sel_SHIFT, CCM_CSCMR1_usdhc3_clk_sel_MASK), /*!< USDHC3 Clock control name.*/ + ccmRootUsdhc4ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc4_clk_sel_SHIFT, CCM_CSCMR1_usdhc4_clk_sel_MASK), /*!< USDHC4 Clock control name.*/ + ccmRootAclkEimSlowSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_aclk_eim_slow_sel_SHIFT, CCM_CSCMR1_aclk_eim_slow_sel_MASK), /*!< ACLK EIM SLOW Clock control name.*/ + ccmRootGpuAxiSel = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_axi_sel_SHIFT, CCM_CBCMR_gpu_axi_sel_MASK), /*!< GPU AXI Clock control name.*/ + ccmRootGpuCoreSel = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_core_sel_SHIFT, CCM_CBCMR_gpu_core_sel_MASK), /*!< GPU Core Clock control name.*/ + ccmRootVidClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_vid_clk_sel_SHIFT, CCM_CSCMR2_vid_clk_sel_MASK), /*!< VID Clock control name.*/ + ccmRootEsaiClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_esai_clk_sel_SHIFT, CCM_CSCMR2_esai_clk_sel_MASK), /*!< ESAI Clock control name.*/ + ccmRootAudioClkSel = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_sel_SHIFT, CCM_CDCDR_audio_clk_sel_MASK), /*!< AUDIO Clock control name.*/ + ccmRootSpdif0ClkSel = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_sel_SHIFT, CCM_CDCDR_spdif0_clk_sel_MASK), /*!< SPDIF0 Clock control name.*/ + ccmRootSsi1ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi1_clk_sel_SHIFT, CCM_CSCMR1_ssi1_clk_sel_MASK), /*!< SSI1 Clock control name.*/ + ccmRootSsi2ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi2_clk_sel_SHIFT, CCM_CSCMR1_ssi2_clk_sel_MASK), /*!< SSI2 Clock control name.*/ + ccmRootSsi3ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi3_clk_sel_SHIFT, CCM_CSCMR1_ssi3_clk_sel_MASK), /*!< SSI3 Clock control name.*/ + ccmRootLcdif2ClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_clk_sel_SHIFT, CCM_CSCDR2_lcdif2_clk_sel_MASK), /*!< LCDIF2 Clock control name.*/ + ccmRootLcdif2PreClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_pre_clk_sel_SHIFT, CCM_CSCDR2_lcdif2_pre_clk_sel_MASK), /*!< LCDIF2 Pre Clock control name.*/ + ccmRootLdbDi1ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ldb_di1_clk_sel_SHIFT, CCM_CS2CDR_ldb_di1_clk_sel_MASK), /*!< LDB DI1 Clock control name.*/ + ccmRootLdbDi0ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ldb_di0_clk_sel_SHIFT, CCM_CS2CDR_ldb_di0_clk_sel_MASK), /*!< LDB DI0 Clock control name.*/ + ccmRootLcdif1ClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_clk_sel_SHIFT, CCM_CSCDR2_lcdif1_clk_sel_MASK), /*!< LCDIF1 Clock control name.*/ + ccmRootLcdif1PreClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_pre_clk_sel_SHIFT, CCM_CSCDR2_lcdif1_pre_clk_sel_MASK), /*!< LCDIF1 Pre Clock control name.*/ + ccmRootM4ClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_clk_sel_SHIFT, CCM_CHSCCDR_m4_clk_sel_MASK), /*!< M4 Clock control name.*/ + ccmRootM4PreClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_pre_clk_sel_SHIFT, CCM_CHSCCDR_m4_pre_clk_sel_MASK), /*!< M4 Pre Clock control name.*/ + ccmRootEnetClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_clk_sel_SHIFT, CCM_CHSCCDR_enet_clk_sel_MASK), /*!< Ethernet Clock control name.*/ + ccmRootEnetPreClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_pre_clk_sel_SHIFT, CCM_CHSCCDR_enet_pre_clk_sel_MASK), /*!< Ethernet Pre Clock control name.*/ + ccmRootQspi2ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_sel_SHIFT, CCM_CS2CDR_qspi2_clk_sel_MASK), /*!< QSPI2 Clock control name.*/ + ccmRootDisplayClkSel = CCM_TUPLE(CSCDR3, CCM_CSCDR3_display_clk_sel_SHIFT, CCM_CSCDR3_display_clk_sel_MASK), /*!< Display Clock control name.*/ + ccmRootCsiClkSel = CCM_TUPLE(CSCDR3, CCM_CSCDR3_csi_clk_sel_SHIFT, CCM_CSCDR3_csi_clk_sel_MASK), /*!< CSI Clock control name.*/ + ccmRootCanClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_can_clk_sel_SHIFT, CCM_CSCMR2_can_clk_sel_MASK), /*!< CAN Clock control name.*/ + ccmRootEcspiClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ecspi_clk_sel_SHIFT, CCM_CSCDR2_ecspi_clk_sel_MASK), /*!< ECSPI Clock control name.*/ + ccmRootUartClkSel = CCM_TUPLE(CSCDR1, CCM_CSCDR1_uart_clk_sel_SHIFT, CCM_CSCDR1_uart_clk_sel_MASK) /*!< UART Clock control name.*/ +}; + +/*! @brief Root clock select enumeration for pll1_sw_clk_sel. */ +enum _ccm_rootmux_pll1_sw_clk_sel +{ + ccmRootmuxPll1SwClkPll1MainClk = 0U, /*!< PLL1 SW Clock from PLL1 Main Clock.*/ + ccmRootmuxPll1SwClkStepClk = 1U, /*!< PLL1 SW Clock from Step Clock.*/ +}; + +/*! @brief Root clock select enumeration for step_sel. */ +enum _ccm_rootmux_step_sel +{ + ccmRootmuxStepOsc24m = 0U, /*!< Step Clock from OSC 24M.*/ + ccmRootmuxStepPll2Pfd2 = 1U, /*!< Step Clock from PLL2 PFD2.*/ +}; + +/*! @brief Root clock select enumeration for periph2_clk_sel. */ +enum _ccm_rootmux_periph2_clk_sel +{ + ccmRootmuxPeriph2ClkPrePeriph2Clk = 0U, /*!< Peripheral2 Clock from Pre Peripheral2 Clock.*/ + ccmRootmuxPeriph2ClkPeriph2Clk2 = 1U, /*!< Peripheral2 Clock from Peripheral2.*/ +}; + +/*! @brief Root clock select enumeration for pre_periph2_clk_sel. */ +enum _ccm_rootmux_pre_periph2_clk_sel +{ + ccmRootmuxPrePeriph2ClkPll2 = 0U, /*!< Pre Peripheral2 Clock from PLL2.*/ + ccmRootmuxPrePeriph2ClkPll2Pfd2 = 1U, /*!< Pre Peripheral2 Clock from PLL2 PFD2.*/ + ccmRootmuxPrePeriph2ClkPll2Pfd0 = 2U, /*!< Pre Peripheral2 Clock from PLL2 PFD0.*/ + ccmRootmuxPrePeriph2ClkPll4 = 3U, /*!< Pre Peripheral2 Clock from PLL4.*/ +}; + +/*! @brief Root clock select enumeration for periph2_clk2_sel. */ +enum _ccm_rootmux_periph2_clk2_sel +{ + ccmRootmuxPeriph2Clk2Pll3SwClk = 0U, /*!< Peripheral2 Clock from PLL3 SW Clock.*/ + ccmRootmuxPeriph2Clk2Osc24m = 1U, /*!< Peripheral2 Clock from OSC 24M.*/ +}; + +/*! @brief Root clock select enumeration for pll3_sw_clk_sel. */ +enum _ccm_rootmux_pll3_sw_clk_sel +{ + ccmRootmuxPll3SwClkPll3 = 0U, /*!< PLL3 SW Clock from PLL3.*/ + ccmRootmuxPll3SwClkPll3BypassClk = 1U, /*!< PLL3 SW Clock from PLL3 Bypass Clock.*/ +}; + +/*! @brief Root clock select enumeration for ocram_clk_sel. */ +enum _ccm_rootmux_ocram_clk_sel +{ + ccmRootmuxOcramClkPeriphClk = 0U, /*!< OCRAM Clock from Peripheral Clock.*/ + ccmRootmuxOcramClkOcramAltClk = 1U, /*!< OCRAM Clock from OCRAM ALT Clock.*/ +}; + +/*! @brief Root clock select enumeration for ocram_alt_clk_sel. */ +enum _ccm_rootmux_ocram_alt_clk_sel +{ + ccmRootmuxOcramAltClkPll2Pfd2 = 0U, /*!< OCRAM ALT Clock from PLL2 PFD2.*/ + ccmRootmuxOcramAltClkPll3Pfd1 = 1U, /*!< OCRAM ALT Clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for periph_clk_sel. */ +enum _ccm_rootmux_periph_clk_sel +{ + ccmRootmuxPeriphClkPrePeriphClkSel = 0U, /*!< Peripheral Clock from Pre Peripheral .*/ + ccmRootmuxPeriphClkPeriphClk2Sel = 1U, /*!< Peripheral Clock from Peripheral2.*/ +}; + +/*! @brief Root clock select enumeration for periph_clk2_sel. */ +enum _ccm_rootmux_periph_clk2_sel +{ + ccmRootmuxPeriphClk2Pll3SwClk = 0U, /*!< Peripheral Clock2 from from PLL3 SW Clock.*/ + ccmRootmuxPeriphClk2OSC24m = 1U, /*!< Peripheral Clock2 from OSC 24M.*/ + ccmRootmuxPeriphClk2Pll2 = 2U, /*!< Peripheral Clock2 from PLL2.*/ +}; + +/*! @brief Root clock select enumeration for pre_periph_clk_sel. */ +enum _ccm_rootmux_pre_periph_clk_sel +{ + ccmRootmuxPrePeriphClkPll2 = 0U, /*!< Pre Peripheral Clock from PLL2.*/ + ccmRootmuxPrePeriphClkPll2Pfd2 = 1U, /*!< Pre Peripheral Clock from PLL2 PFD2.*/ + ccmRootmuxPrePeriphClkPll2Pfd0 = 2U, /*!< Pre Peripheral Clock from PLL2 PFD0.*/ + ccmRootmuxPrePeriphClkPll2Pfd2div2 = 3U, /*!< Pre Peripheral Clock from PLL2 PFD2 divided by 2.*/ +}; + +/*! @brief Root clock select enumeration for pcie_axi_clk_sel. */ +enum _ccm_rootmux_pcie_axi_clk_sel +{ + ccmRootmuxPcieAxiClkAxiClk = 0U, /*!< PCIE AXI Clock from AXI Clock.*/ + ccmRootmuxPcieAxiClkAhbClk = 1U, /*!< PCIE AXI Clock from AHB Clock.*/ +}; + +/*! @brief Root clock select enumeration for perclk_clk_sel. */ +enum _ccm_rootmux_perclk_clk_sel +{ + ccmRootmuxPerclkClkIpgClkRoot = 0U, /*!< Perclk from IPG Clock Root.*/ + ccmRootmuxPerclkClkOsc24m = 1U, /*!< Perclk from OSC 24M.*/ +}; + +/*! @brief Root clock select enumeration for usdhc1_clk_sel. */ +enum _ccm_rootmux_usdhc1_clk_sel +{ + ccmRootmuxUsdhc1ClkPll2Pfd2 = 0U, /*!< USDHC1 Clock from PLL2 PFD2.*/ + ccmRootmuxUsdhc1ClkPll2Pfd0 = 1U, /*!< USDHC1 Clock from PLL2 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for usdhc2_clk_sel. */ +enum _ccm_rootmux_usdhc2_clk_sel +{ + ccmRootmuxUsdhc2ClkPll2Pfd2 = 0U, /*!< USDHC2 Clock from PLL2 PFD2.*/ + ccmRootmuxUsdhc2ClkPll2Pfd0 = 1U, /*!< USDHC2 Clock from PLL2 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for usdhc3_clk_sel. */ +enum _ccm_rootmux_usdhc3_clk_sel +{ + ccmRootmuxUsdhc3ClkPll2Pfd2 = 0U, /*!< USDHC3 Clock from PLL2 PFD2.*/ + ccmRootmuxUsdhc3ClkPll2Pfd0 = 1U, /*!< USDHC3 Clock from PLL2 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for usdhc4_clk_sel. */ +enum _ccm_rootmux_usdhc4_clk_sel +{ + ccmRootmuxUsdhc4ClkPll2Pfd2 = 0U, /*!< USDHC4 Clock from PLL2 PFD2.*/ + ccmRootmuxUsdhc4ClkPll2Pfd0 = 1U, /*!< USDHC4 Clock from PLL2 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for aclk_eim_slow_sel. */ +enum _ccm_rootmux_aclk_eim_slow_sel +{ + ccmRootmuxAclkEimSlowAxiClk = 0U, /*!< Aclk EimSlow Clock from AXI Clock.*/ + ccmRootmuxAclkEimSlowPll3SwClk = 1U, /*!< Aclk EimSlow Clock from PLL3 SW Clock.*/ + ccmRootmuxAclkEimSlowPll2Pfd2 = 2U, /*!< Aclk EimSlow Clock from PLL2 PFD2.*/ + ccmRootmuxAclkEimSlowPll3Pfd0 = 3U, /*!< Aclk EimSlow Clock from PLL3 PFD0.*/ +}; + +/*! @brief Root clock select enumeration for gpu_axi_sel. */ +enum _ccm_rootmux_gpu_axi_sel +{ + ccmRootmuxGpuAxiPll2Pfd2 = 0U, /*!< GPU AXI Clock from PLL2 PFD2.*/ + ccmRootmuxGpuAxiPll3Pfd0 = 1U, /*!< GPU AXI Clock from PLL3 PFD0.*/ + ccmRootmuxGpuAxiPll2Pfd1 = 2U, /*!< GPU AXI Clock from PLL2 PFD1.*/ + ccmRootmuxGpuAxiPll2 = 3U, /*!< GPU AXI Clock from PLL2.*/ +}; + +/*! @brief Root clock select enumeration for gpu_core_sel. */ +enum _ccm_rootmux_gpu_core_sel +{ + ccmRootmuxGpuCorePll3Pfd1 = 0U, /*!< GPU Core Clock from PLL3 PFD1.*/ + ccmRootmuxGpuCorePll3Pfd0 = 1U, /*!< GPU Core Clock from PLL3 PFD0.*/ + ccmRootmuxGpuCorePll2 = 2U, /*!< GPU Core Clock from PLL2.*/ + ccmRootmuxGpuCorePll2Pfd2 = 3U, /*!< GPU Core Clock from PLL2 PFD2.*/ +}; + +/*! @brief Root clock select enumeration for vid_clk_sel. */ +enum _ccm_rootmux_vid_clk_sel +{ + ccmRootmuxVidClkPll3Pfd1 = 0U, /*!< VID Clock from PLL3 PFD1.*/ + ccmRootmuxVidClkPll3 = 1U, /*!< VID Clock from PLL3.*/ + ccmRootmuxVidClkPll3Pfd3 = 2U, /*!< VID Clock from PLL3 PFD3.*/ + ccmRootmuxVidClkPll4 = 3U, /*!< VID Clock from PLL4.*/ + ccmRootmuxVidClkPll5 = 4U, /*!< VID Clock from PLL5.*/ +}; + +/*! @brief Root clock select enumeration for esai_clk_sel. */ +enum _ccm_rootmux_esai_clk_sel +{ + ccmRootmuxEsaiClkPll4 = 0U, /*!< ESAI Clock from PLL4.*/ + ccmRootmuxEsaiClkPll3Pfd2 = 1U, /*!< ESAI Clock from PLL3 PFD2.*/ + ccmRootmuxEsaiClkPll5 = 2U, /*!< ESAI Clock from PLL5.*/ + ccmRootmuxEsaiClkPll3SwClk = 3U, /*!< ESAI Clock from PLL3 SW Clock.*/ +}; + +/*! @brief Root clock select enumeration for audio_clk_sel. */ +enum _ccm_rootmux_audio_clk_sel +{ + ccmRootmuxAudioClkPll4 = 0U, /*!< Audio Clock from PLL4.*/ + ccmRootmuxAudioClkPll3Pfd2 = 1U, /*!< Audio Clock from PLL3 PFD2.*/ + ccmRootmuxAudioClkPll5 = 2U, /*!< Audio Clock from PLL5.*/ + ccmRootmuxAudioClkPll3SwClk = 3U, /*!< Audio Clock from PLL3 SW Clock.*/ +}; + +/*! @brief Root clock select enumeration for spdif0_clk_sel. */ +enum _ccm_rootmux_spdif0_clk_sel +{ + ccmRootmuxSpdif0ClkPll4 = 0U, /*!< SPDIF0 Clock from PLL4.*/ + ccmRootmuxSpdif0ClkPll3Pfd2 = 1U, /*!< SPDIF0 Clock from PLL3 PFD2.*/ + ccmRootmuxSpdif0ClkPll5 = 2U, /*!< SPDIF0 Clock from PLL5.*/ + ccmRootmuxSpdif0ClkPll3SwClk = 3U, /*!< SPDIF0 Clock from PLL3 SW Clock.*/ +}; + +/*! @brief Root clock select enumeration for ssi1_clk_sel. */ +enum _ccm_rootmux_ssi1_clk_sel +{ + ccmRootmuxSsi1ClkPll3Pfd2 = 0U, /*!< SSI1 Clock from PLL3 PFD2.*/ + ccmRootmuxSsi1ClkPll5 = 1U, /*!< SSI1 Clock from PLL5.*/ + ccmRootmuxSsi1ClkPll4 = 2U, /*!< SSI1 Clock from PLL4.*/ +}; + +/*! @brief Root clock select enumeration for ssi2_clk_sel. */ +enum _ccm_rootmux_ssi2_clk_sel +{ + ccmRootmuxSsi2ClkPll3Pfd2 = 0U, /*!< SSI2 Clock from PLL3 PFD2.*/ + ccmRootmuxSsi2ClkPll5 = 1U, /*!< SSI2 Clock from PLL5.*/ + ccmRootmuxSsi2ClkPll4 = 2U, /*!< SSI2 Clock from PLL4.*/ +}; + +/*! @brief Root clock select enumeration for ssi3_clk_sel. */ +enum _ccm_rootmux_ssi3_clk_sel +{ + ccmRootmuxSsi3ClkPll3Pfd2 = 0U, /*!< SSI3 Clock from PLL3 PFD2.*/ + ccmRootmuxSsi3ClkPll5 = 1U, /*!< SSI3 Clock from PLL5.*/ + ccmRootmuxSsi3ClkPll4 = 2U, /*!< SSI3 Clock from PLL4.*/ +}; + +/*! @brief Root clock select enumeration for lcdif2_clk_sel. */ +enum _ccm_rootmux_lcdif2_clk_sel +{ + ccmRootmuxLcdif2ClkLcdif2PreClk = 0U, /*!< LCDIF2 Clock from LCDIF2 Pre Clock.*/ + ccmRootmuxLcdif2ClkIppDi0Clk = 1U, /*!< LCDIF2 Clock from IPP DI0 Clock.*/ + ccmRootmuxLcdif2ClkIppDi1Clk = 2U, /*!< LCDIF2 Clock from IPP DI0 Clock.*/ + ccmRootmuxLcdif2ClkLdbDi0Clk = 3U, /*!< LCDIF2 Clock from LDB DI0 Clock.*/ + ccmRootmuxLcdif2ClkLdbDi1Clk = 4U, /*!< LCDIF2 Clock from LDB DI0 Clock.*/ +}; + +/*! @brief Root clock select enumeration for lcdif2_pre_clk_sel. */ +enum _ccm_rootmux_lcdif2_pre_clk_sel +{ + ccmRootmuxLcdif2ClkPrePll2 = 0U, /*!< LCDIF2 Pre Clock from PLL2.*/ + ccmRootmuxLcdif2ClkPrePll3Pfd3 = 1U, /*!< LCDIF2 Pre Clock from PLL3 PFD3.*/ + ccmRootmuxLcdif2ClkPrePll5 = 2U, /*!< LCDIF2 Pre Clock from PLL3 PFD5.*/ + ccmRootmuxLcdif2ClkPrePll2Pfd0 = 3U, /*!< LCDIF2 Pre Clock from PLL2 PFD0.*/ + ccmRootmuxLcdif2ClkPrePll2Pfd3 = 4U, /*!< LCDIF2 Pre Clock from PLL2 PFD3.*/ + ccmRootmuxLcdif2ClkPrePll3Pfd1 = 5U, /*!< LCDIF2 Pre Clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for ldb_di1_clk_sel. */ +enum _ccm_rootmux_ldb_di1_clk_sel +{ + ccmRootmuxLdbDi1ClkPll3SwClk = 0U, /*!< lDB DI1 Clock from PLL3 SW Clock.*/ + ccmRootmuxLdbDi1ClkPll2Pfd0 = 1U, /*!< lDB DI1 Clock from PLL2 PFD0.*/ + ccmRootmuxLdbDi1ClkPll2Pfd2 = 2U, /*!< lDB DI1 Clock from PLL2 PFD2.*/ + ccmRootmuxLdbDi1ClkPll2 = 3U, /*!< lDB DI1 Clock from PLL2.*/ + ccmRootmuxLdbDi1ClkPll3Pfd3 = 4U, /*!< lDB DI1 Clock from PLL3 PFD3.*/ + ccmRootmuxLdbDi1ClkPll3Pfd2 = 5U, /*!< lDB DI1 Clock from PLL3 PFD2.*/ +}; + +/*! @brief Root clock select enumeration for ldb_di0_clk_sel. */ +enum _ccm_rootmux_ldb_di0_clk_sel +{ + ccmRootmuxLdbDi0ClkPll5 = 0U, /*!< lDB DI0 Clock from PLL5.*/ + ccmRootmuxLdbDi0ClkPll2Pfd0 = 1U, /*!< lDB DI0 Clock from PLL2 PFD0.*/ + ccmRootmuxLdbDi0ClkPll2Pfd2 = 2U, /*!< lDB DI0 Clock from PLL2 PFD2.*/ + ccmRootmuxLdbDi0ClkPll2Pfd3 = 3U, /*!< lDB DI0 Clock from PLL2 PFD3.*/ + ccmRootmuxLdbDi0ClkPll3Pfd1 = 4U, /*!< lDB DI0 Clock from PLL3 PFD1.*/ + ccmRootmuxLdbDi0ClkPll3Pfd3 = 5U, /*!< lDB DI0 Clock from PLL3 PFD3.*/ +}; + +/*! @brief Root clock select enumeration for lcdif1_clk_sel. */ +enum _ccm_rootmux_lcdif1_clk_sel +{ + ccmRootmuxLcdif1ClkLcdif1PreClk = 0U, /*!< LCDIF1 clock from LCDIF1 Pre Clock.*/ + ccmRootmuxLcdif1ClkIppDi0Clk = 1U, /*!< LCDIF1 clock from IPP DI0 Clock.*/ + ccmRootmuxLcdif1ClkIppDi1Clk = 2U, /*!< LCDIF1 clock from IPP DI1 Clock.*/ + ccmRootmuxLcdif1ClkLdbDi0Clk = 3U, /*!< LCDIF1 clock from LDB DI0 Clock.*/ + ccmRootmuxLcdif1ClkLdbDi1Clk = 4U, /*!< LCDIF1 clock from LDB DI1 Clock.*/ +}; + +/*! @brief Root clock select enumeration for lcdif1_pre_clk_sel. */ +enum _ccm_rootmux_lcdif1_pre_clk_sel +{ + ccmRootmuxLcdif1PreClkPll2 = 0U, /*!< LCDIF1 pre clock from PLL2.*/ + ccmRootmuxLcdif1PreClkPll3Pfd3 = 1U, /*!< LCDIF1 pre clock from PLL3 PFD3.*/ + ccmRootmuxLcdif1PreClkPll5 = 2U, /*!< LCDIF1 pre clock from PLL5.*/ + ccmRootmuxLcdif1PreClkPll2Pfd0 = 3U, /*!< LCDIF1 pre clock from PLL2 PFD0.*/ + ccmRootmuxLcdif1PreClkPll2Pfd1 = 4U, /*!< LCDIF1 pre clock from PLL2 PFD1.*/ + ccmRootmuxLcdif1PreClkPll3Pfd1 = 5U, /*!< LCDIF1 pre clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for m4_clk_sel. */ +enum _ccm_rootmux_m4_clk_sel +{ + ccmRootmuxM4ClkM4PreClk = 0U, /*!< M4 clock from M4 Pre Clock.*/ + ccmRootmuxM4ClkPll3Pfd3 = 1U, /*!< M4 clock from PLL3 PFD3.*/ + ccmRootmuxM4ClkIppDi0Clk = 2U, /*!< M4 clock from IPP DI0 Clock.*/ + ccmRootmuxM4ClkIppDi1Clk = 3U, /*!< M4 clock from IPP DI1 Clock.*/ + ccmRootmuxM4ClkLdbDi0Clk = 4U, /*!< M4 clock from LDB DI0 Clock.*/ + ccmRootmuxM4ClkLdbDi1Clk = 5U, /*!< M4 clock from LDB DI1 Clock.*/ +}; + +/*! @brief Root clock select enumeration for m4_pre_clk_sel. */ +enum _ccm_rootmux_m4_pre_clk_sel +{ + ccmRootmuxM4PreClkPll2 = 0U, /*!< M4 pre clock from PLL2.*/ + ccmRootmuxM4PreClkPll3SwClk = 1U, /*!< M4 pre clock from PLL3 SW Clock.*/ + ccmRootmuxM4PreClkOsc24m = 2U, /*!< M4 pre clock from OSC 24M.*/ + ccmRootmuxM4PreClkPll2Pfd0 = 3U, /*!< M4 pre clock from PLL2 PFD0.*/ + ccmRootmuxM4PreClkPll2Pfd2 = 4U, /*!< M4 pre clock from PLL2 PFD2.*/ + ccmRootmuxM4PreClkPll3Pfd3 = 5U, /*!< M4 pre clock from PLL3 PFD3.*/ +}; + +/*! @brief Root clock select enumeration for nent_clk_sel. */ +enum _ccm_rootmux_enet_clk_sel +{ + ccmRootmuxEnetClkEnetPreClk = 0U, /*!< Ethernet clock from Ethernet Pre Clock.*/ + ccmRootmuxEnetClkIppDi0Clk = 1U, /*!< Ethernet clock from IPP DI0 Clock.*/ + ccmRootmuxEnetClkIppDi1Clk = 2U, /*!< Ethernet clock from IPP DI1 Clock.*/ + ccmRootmuxEnetClkLdbDi0Clk = 3U, /*!< Ethernet clock from LDB DI0 Clock.*/ + ccmRootmuxEnetClkLdbDi1Clk = 4U, /*!< Ethernet clock from LDB DI1 Clock.*/ +}; + +/*! @brief Root clock select enumeration for enet_pre_clk_sel. */ +enum _ccm_rootmux_enet_pre_clk_sel +{ + ccmRootmuxEnetPreClkPll2 = 0U, /*!< Ethernet Pre clock from PLL2.*/ + ccmRootmuxEnetPreClkPll3SwClk = 1U, /*!< Ethernet Pre clock from PLL3 SW Clock.*/ + ccmRootmuxEnetPreClkPll5 = 2U, /*!< Ethernet Pre clock from PLL5.*/ + ccmRootmuxEnetPreClkPll2Pfd0 = 3U, /*!< Ethernet Pre clock from PLL2 PFD0.*/ + ccmRootmuxEnetPreClkPll2Pfd2 = 4U, /*!< Ethernet Pre clock from PLL2 PFD2.*/ + ccmRootmuxEnetPreClkPll3Pfd2 = 5U, /*!< Ethernet Pre clock from PLL3 PFD2.*/ +}; + +/*! @brief Root clock select enumeration for qspi2_clk_sel. */ +enum _ccm_rootmux_qspi2_clk_sel +{ + ccmRootmuxQspi2ClkPll2Pfd0 = 0U, /*!< QSPI2 Clock from PLL2 PFD0.*/ + ccmRootmuxQspi2ClkPll2 = 1U, /*!< QSPI2 Clock from PLL2.*/ + ccmRootmuxQspi2ClkPll3SwClk = 2U, /*!< QSPI2 Clock from PLL3 SW Clock.*/ + ccmRootmuxQspi2ClkPll2Pfd2 = 3U, /*!< QSPI2 Clock from PLL2 PFD2.*/ + ccmRootmuxQspi2ClkPll3Pfd3 = 4U, /*!< QSPI2 Clock from PLL3 PFD3.*/ +}; + +/*! @brief Root clock select enumeration for display_clk_sel. */ +enum _ccm_rootmux_display_clk_sel +{ + ccmRootmuxDisplayClkPll2 = 0U, /*!< Display Clock from PLL2.*/ + ccmRootmuxDisplayClkPll2Pfd2 = 1U, /*!< Display Clock from PLL2 PFD2.*/ + ccmRootmuxDisplayClkPll3SwClk = 2U, /*!< Display Clock from PLL3 SW Clock.*/ + ccmRootmuxDisplayClkPll3Pfd1 = 3U, /*!< Display Clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for csi_clk_sel. */ +enum _ccm_rootmux_csi_clk_sel +{ + ccmRootmuxCsiClkOSC24m = 0U, /*!< CSI Clock from OSC 24M.*/ + ccmRootmuxCsiClkPll2Pfd2 = 1U, /*!< CSI Clock from PLL2 PFD2.*/ + ccmRootmuxCsiClkPll3SwClkDiv2 = 2U, /*!< CSI Clock from PLL3 SW clock divided by 2.*/ + ccmRootmuxCsiClkPll3Pfd1 = 3U, /*!< CSI Clock from PLL3 PFD1.*/ +}; + +/*! @brief Root clock select enumeration for can_clk_sel. */ +enum _ccm_rootmux_can_clk_sel +{ + ccmRootmuxCanClkPll3SwClkDiv8 = 0U, /*!< CAN Clock from PLL3 SW clock divided by 8.*/ + ccmRootmuxCanClkOsc24m = 1U, /*!< CAN Clock from OSC 24M.*/ + ccmRootmuxCanClkPll3SwClkDiv6 = 2U, /*!< CAN Clock from PLL3 SW clock divided by 6.*/ + ccmRootmuxCanClkDisableFlexcanClk = 3U, /*!< Disable FlexCAN clock.*/ +}; + +/*! @brief Root clock select enumeration for ecspi_clk_sel. */ +enum _ccm_rootmux_ecspi_clk_sel +{ + ccmRootmuxEcspiClkPll3SwClkDiv8 = 0U, /*!< ecSPI Clock from PLL3 SW clock divided by 8.*/ + ccmRootmuxEcspiClkOsc24m = 1U, /*!< ecSPI Clock from OSC 24M.*/ +}; + +/*! @brief Root clock select enumeration for uart_clk_sel. */ +enum _ccm_rootmux_uart_clk_sel +{ + ccmRootmuxUartClkPll3SwClkDiv6 = 0U, /*!< UART Clock from PLL3 SW clock divided by 6.*/ + ccmRootmuxUartClkOsc24m = 1U, /*!< UART Clock from OSC 24M.*/ +}; + +/*! + * @brief Root control names for root divider setting. + * + * These constants define the root control names for root divider setting.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root divider setting bit field shift. + * - 16:31: Root divider setting bit field width. + */ +enum _ccm_root_div_control +{ + ccmRootArmPodf = CCM_TUPLE(CACRR, CCM_CACRR_arm_podf_SHIFT, CCM_CACRR_arm_podf_MASK), /*!< ARM Clock post divider control names.*/ + ccmRootFabricMmdcPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_fabric_mmdc_podf_SHIFT, CCM_CBCDR_fabric_mmdc_podf_MASK), /*!< Fabric MMDC Clock post divider control names.*/ + ccmRootPeriph2Clk2Podf = CCM_TUPLE(CBCDR, CCM_CBCDR_periph2_clk2_podf_SHIFT, CCM_CBCDR_periph2_clk2_podf_MASK), /*!< Peripheral2 Clock2 post divider control names.*/ + ccmRootOcramPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_podf_SHIFT, CCM_CBCDR_ocram_podf_MASK), /*!< OCRAM Clock post divider control names.*/ + ccmRootAhbPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ahb_podf_SHIFT, CCM_CBCDR_ahb_podf_MASK), /*!< AHB Clock post divider control names.*/ + ccmRootPeriphClk2Podf = CCM_TUPLE(CBCDR, CCM_CBCDR_periph_clk2_podf_SHIFT, CCM_CBCDR_periph_clk2_podf_MASK), /*!< Peripheral Clock2 post divider control names.*/ + ccmRootPerclkPodf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_perclk_podf_SHIFT, CCM_CSCMR1_perclk_podf_MASK), /*!< Pre Clock post divider control names.*/ + ccmRootIpgPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ipg_podf_SHIFT, CCM_CBCDR_ipg_podf_MASK), /*!< IPG Clock post divider control names.*/ + ccmRootUsdhc1Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc1_podf_SHIFT, CCM_CSCDR1_usdhc1_podf_MASK), /*!< USDHC1 Clock post divider control names.*/ + ccmRootUsdhc2Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc2_podf_SHIFT, CCM_CSCDR1_usdhc2_podf_MASK), /*!< USDHC2 Clock post divider control names.*/ + ccmRootUsdhc3Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc3_podf_SHIFT, CCM_CSCDR1_usdhc3_podf_MASK), /*!< USDHC3 Clock post divider control names.*/ + ccmRootUsdhc4Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc4_podf_SHIFT, CCM_CSCDR1_usdhc4_podf_MASK), /*!< USDHC4 Clock post divider control names.*/ + ccmRootAclkEimSlowPodf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_aclk_eim_slow_podf_SHIFT, CCM_CSCMR1_aclk_eim_slow_podf_MASK), /*!< ACLK EIM SLOW Clock post divider control names.*/ + ccmRootGpuAxiPodf = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_axi_podf_SHIFT, CCM_CBCMR_gpu_axi_podf_MASK), /*!< GPU AXI Clock post divider control names.*/ + ccmRootGpuCorePodf = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_core_podf_SHIFT, CCM_CBCMR_gpu_core_podf_MASK), /*!< GPU Core Clock post divider control names.*/ + ccmRootVidClkPodf = CCM_TUPLE(CSCMR2, CCM_CSCMR2_vid_clk_podf_SHIFT, CCM_CSCMR2_vid_clk_podf_MASK), /*!< VID Clock post divider control names.*/ + ccmRootEsaiClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_esai_clk_podf_SHIFT, CCM_CS1CDR_esai_clk_podf_MASK), /*!< ESAI Clock pre divider control names.*/ + ccmRootEsaiClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_esai_clk_pred_SHIFT, CCM_CS1CDR_esai_clk_pred_MASK), /*!< ESAI Clock post divider control names.*/ + ccmRootAudioClkPodf = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_podf_SHIFT, CCM_CDCDR_audio_clk_podf_MASK), /*!< AUDIO Clock post divider control names.*/ + ccmRootAudioClkPred = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_pred_SHIFT, CCM_CDCDR_audio_clk_pred_MASK), /*!< AUDIO Clock pre divider control names.*/ + ccmRootSpdif0ClkPodf = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_podf_SHIFT, CCM_CDCDR_spdif0_clk_podf_MASK), /*!< SPDIF0 Clock post divider control names.*/ + ccmRootSpdif0ClkPred = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_pred_SHIFT, CCM_CDCDR_spdif0_clk_pred_MASK), /*!< SPDIF0 Clock pre divider control names.*/ + ccmRootSsi1ClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi1_clk_podf_SHIFT, CCM_CS1CDR_ssi1_clk_podf_MASK), /*!< SSI1 Clock post divider control names.*/ + ccmRootSsi1ClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi1_clk_pred_SHIFT, CCM_CS1CDR_ssi1_clk_pred_MASK), /*!< SSI1 Clock pre divider control names.*/ + ccmRootSsi2ClkPodf = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ssi2_clk_podf_SHIFT, CCM_CS2CDR_ssi2_clk_podf_MASK), /*!< SSI2 Clock post divider control names.*/ + ccmRootSsi2ClkPred = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ssi2_clk_pred_SHIFT, CCM_CS2CDR_ssi2_clk_pred_MASK), /*!< SSI2 Clock pre divider control names.*/ + ccmRootSsi3ClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi3_clk_podf_SHIFT, CCM_CS1CDR_ssi3_clk_podf_MASK), /*!< SSI3 Clock post divider control names.*/ + ccmRootSsi3ClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi3_clk_pred_SHIFT, CCM_CS1CDR_ssi3_clk_pred_MASK), /*!< SSI3 Clock pre divider control names.*/ + ccmRootLcdif2Podf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_lcdif2_podf_SHIFT, CCM_CSCMR1_lcdif2_podf_MASK), /*!< LCDIF2 Clock post divider control names.*/ + ccmRootLcdif2Pred = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_pred_SHIFT, CCM_CSCDR2_lcdif2_pred_MASK), /*!< LCDIF2 Clock pre divider control names.*/ + ccmRootLdbDi1Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ldb_di1_div_SHIFT, CCM_CSCMR2_ldb_di1_div_MASK), /*!< LDB DI1 Clock divider control names.*/ + ccmRootLdbDi0Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ldb_di0_div_SHIFT, CCM_CSCMR2_ldb_di0_div_MASK), /*!< LCDIDI0 Clock divider control names.*/ + ccmRootLcdif1Podf = CCM_TUPLE(CBCMR, CCM_CBCMR_lcdif1_podf_SHIFT, CCM_CBCMR_lcdif1_podf_MASK), /*!< LCDIF1 Clock post divider control names.*/ + ccmRootLcdif1Pred = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_pred_SHIFT, CCM_CSCDR2_lcdif1_pred_MASK), /*!< LCDIF1 Clock pre divider control names.*/ + ccmRootM4Podf = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_podf_SHIFT, CCM_CHSCCDR_m4_podf_MASK), /*!< M4 Clock post divider control names.*/ + ccmRootEnetPodf = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_podf_SHIFT, CCM_CHSCCDR_enet_podf_MASK), /*!< Ethernet Clock post divider control names.*/ + ccmRootQspi1Podf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_qspi1_podf_SHIFT, CCM_CSCMR1_qspi1_podf_MASK), /*!< QSPI1 Clock post divider control names.*/ + ccmRootQspi2ClkPodf = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_podf_SHIFT, CCM_CS2CDR_qspi2_clk_podf_MASK), /*!< QSPI2 Clock post divider control names.*/ + ccmRootQspi2ClkPred = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_pred_SHIFT, CCM_CS2CDR_qspi2_clk_pred_MASK), /*!< QSPI2 Clock pre divider control names.*/ + ccmRootDisplayPodf = CCM_TUPLE(CSCDR3, CCM_CSCDR3_display_podf_SHIFT, CCM_CSCDR3_display_podf_MASK), /*!< Display Clock post divider control names.*/ + ccmRootCsiPodf = CCM_TUPLE(CSCDR3, CCM_CSCDR3_csi_podf_SHIFT, CCM_CSCDR3_csi_podf_MASK), /*!< CSI Clock post divider control names.*/ + ccmRootCanClkPodf = CCM_TUPLE(CSCMR2, CCM_CSCMR2_can_clk_podf_SHIFT, CCM_CSCMR2_can_clk_podf_MASK), /*!< CAN Clock post divider control names.*/ + ccmRootEcspiClkPodf = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ecspi_clk_podf_SHIFT, CCM_CSCDR2_ecspi_clk_podf_MASK), /*!< ECSPI Clock post divider control names.*/ + ccmRootUartClkPodf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_uart_clk_podf_SHIFT, CCM_CSCDR1_uart_clk_podf_MASK) /*!< UART Clock post divider control names.*/ +}; + +/*! + * @brief CCM CCGR gate control for each module independently. + * + * These constants define the ccm ccgr clock gate for each module.\n + * - 0:7: REG offset to CCM_BASE in bytes. + * - 8:15: Root divider setting bit field shift. + * - 16:31: Root divider setting bit field width. + */ +enum _ccm_ccgr_gate +{ + ccmCcgrGateAipsTz1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG0_SHIFT, CCM_CCGR0_CG0_MASK), /*!< AipsTz1 Clock Gate.*/ + ccmCcgrGateAipsTz2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG1_SHIFT, CCM_CCGR0_CG1_MASK), /*!< AipsTz2 Clock Gate.*/ + ccmCcgrGateApbhdmaHclk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG2_SHIFT, CCM_CCGR0_CG2_MASK), /*!< ApbhdmaH Clock Gate.*/ + ccmCcgrGateAsrcClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG3_SHIFT, CCM_CCGR0_CG3_MASK), /*!< Asrc Clock Gate.*/ + ccmCcgrGateCaamSecureMemClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG4_SHIFT, CCM_CCGR0_CG4_MASK), /*!< CaamSecureMem Clock Gate.*/ + ccmCcgrGateCaamWrapperAclk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG5_SHIFT, CCM_CCGR0_CG5_MASK), /*!< CaamWrapperA Clock Gate.*/ + ccmCcgrGateCaamWrapperIpg = CCM_TUPLE(CCGR0, CCM_CCGR0_CG6_SHIFT, CCM_CCGR0_CG6_MASK), /*!< CaamWrapperIpg Clock Gate.*/ + ccmCcgrGateCan1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG7_SHIFT, CCM_CCGR0_CG7_MASK), /*!< Can1 Clock Gate.*/ + ccmCcgrGateCan1SerialClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG8_SHIFT, CCM_CCGR0_CG8_MASK), /*!< Can1 Serial Clock Gate.*/ + ccmCcgrGateCan2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG9_SHIFT, CCM_CCGR0_CG9_MASK), /*!< Can2 Clock Gate.*/ + ccmCcgrGateCan2SerialClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG10_SHIFT, CCM_CCGR0_CG10_MASK), /*!< Can2 Serial Clock Gate.*/ + ccmCcgrGateArmDbgClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG11_SHIFT, CCM_CCGR0_CG11_MASK), /*!< Arm Debug Clock Gate.*/ + ccmCcgrGateDcic1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG12_SHIFT, CCM_CCGR0_CG12_MASK), /*!< Dcic1 Clock Gate.*/ + ccmCcgrGateDcic2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG13_SHIFT, CCM_CCGR0_CG13_MASK), /*!< Dcic2 Clock Gate.*/ + ccmCcgrGateAipsTz3Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG15_SHIFT, CCM_CCGR0_CG15_MASK), /*!< AipsTz3 Clock Gate.*/ + ccmCcgrGateEcspi1Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG0_SHIFT, CCM_CCGR1_CG0_MASK), /*!< Ecspi1 Clock Gate.*/ + ccmCcgrGateEcspi2Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG1_SHIFT, CCM_CCGR1_CG1_MASK), /*!< Ecspi2 Clock Gate.*/ + ccmCcgrGateEcspi3Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG2_SHIFT, CCM_CCGR1_CG2_MASK), /*!< Ecspi3 Clock Gate.*/ + ccmCcgrGateEcspi4Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG3_SHIFT, CCM_CCGR1_CG3_MASK), /*!< Ecspi4 Clock Gate.*/ + ccmCcgrGateEcspi5Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG4_SHIFT, CCM_CCGR1_CG4_MASK), /*!< Ecspi5 Clock Gate.*/ + ccmCcgrGateEpit1Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG6_SHIFT, CCM_CCGR1_CG6_MASK), /*!< Epit1 Clock Gate.*/ + ccmCcgrGateEpit2Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG7_SHIFT, CCM_CCGR1_CG7_MASK), /*!< Epit2 Clock Gate.*/ + ccmCcgrGateEsaiClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG8_SHIFT, CCM_CCGR1_CG8_MASK), /*!< Esai Clock Gate.*/ + ccmCcgrGateWakeupClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG9_SHIFT, CCM_CCGR1_CG9_MASK), /*!< Wakeup Clock Gate.*/ + ccmCcgrGateGptClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG10_SHIFT, CCM_CCGR1_CG10_MASK), /*!< Gpt Clock Gate.*/ + ccmCcgrGateGptSerialClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG11_SHIFT, CCM_CCGR1_CG11_MASK), /*!< Gpt Serial Clock Gate.*/ + ccmCcgrGateGpuClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG13_SHIFT, CCM_CCGR1_CG13_MASK), /*!< Gpu Clock Gate.*/ + ccmCcgrGateOcramSClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG14_SHIFT, CCM_CCGR1_CG14_MASK), /*!< OcramS Clock Gate.*/ + ccmCcgrGateCanfdClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG15_SHIFT, CCM_CCGR1_CG15_MASK), /*!< Canfd Clock Gate.*/ + ccmCcgrGateCsiClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG1_SHIFT, CCM_CCGR2_CG1_MASK), /*!< Csi Clock Gate.*/ + ccmCcgrGateI2c1Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG3_SHIFT, CCM_CCGR2_CG3_MASK), /*!< I2c1 Serial Clock Gate.*/ + ccmCcgrGateI2c2Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG4_SHIFT, CCM_CCGR2_CG4_MASK), /*!< I2c2 Serial Clock Gate.*/ + ccmCcgrGateI2c3Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG5_SHIFT, CCM_CCGR2_CG5_MASK), /*!< I2c3 Serial Clock Gate.*/ + ccmCcgrGateIimClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG6_SHIFT, CCM_CCGR2_CG6_MASK), /*!< Iim Clock Gate.*/ + ccmCcgrGateIomuxIptClkIo = CCM_TUPLE(CCGR2, CCM_CCGR2_CG7_SHIFT, CCM_CCGR2_CG7_MASK), /*!< Iomux Ipt Clock Gate.*/ + ccmCcgrGateIpmux1Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG8_SHIFT, CCM_CCGR2_CG8_MASK), /*!< Ipmux1 Clock Gate.*/ + ccmCcgrGateIpmux2Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG9_SHIFT, CCM_CCGR2_CG9_MASK), /*!< Ipmux2 Clock Gate.*/ + ccmCcgrGateIpmux3Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG10_SHIFT, CCM_CCGR2_CG10_MASK), /*!< Ipmux3 Clock Gate.*/ + ccmCcgrGateIpsyncIp2apbtTasc1 = CCM_TUPLE(CCGR2, CCM_CCGR2_CG11_SHIFT, CCM_CCGR2_CG11_MASK), /*!< IpsyncIp2apbtTasc1 Clock Gate.*/ + ccmCcgrGateLcdClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG14_SHIFT, CCM_CCGR2_CG14_MASK), /*!< Lcd Clock Gate.*/ + ccmCcgrGatePxpClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG15_SHIFT, CCM_CCGR2_CG15_MASK), /*!< Pxp Clock Gate.*/ + ccmCcgrGateM4Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG1_SHIFT, CCM_CCGR3_CG1_MASK), /*!< M4 Clock Gate.*/ + ccmCcgrGateEnetClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG2_SHIFT, CCM_CCGR3_CG2_MASK), /*!< Enet Clock Gate.*/ + ccmCcgrGateDispAxiClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG3_SHIFT, CCM_CCGR3_CG3_MASK), /*!< DispAxi Clock Gate.*/ + ccmCcgrGateLcdif2PixClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG4_SHIFT, CCM_CCGR3_CG4_MASK), /*!< Lcdif2Pix Clock Gate.*/ + ccmCcgrGateLcdif1PixClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG5_SHIFT, CCM_CCGR3_CG5_MASK), /*!< Lcdif1Pix Clock Gate.*/ + ccmCcgrGateLdbDi0Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG6_SHIFT, CCM_CCGR3_CG6_MASK), /*!< LdbDi0 Clock Gate.*/ + ccmCcgrGateQspi1Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG7_SHIFT, CCM_CCGR3_CG7_MASK), /*!< Qspi1 Clock Gate.*/ + ccmCcgrGateMlbClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG9_SHIFT, CCM_CCGR3_CG9_MASK), /*!< Mlb Clock Gate.*/ + ccmCcgrGateMmdcCoreAclkFastP0 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG10_SHIFT, CCM_CCGR3_CG10_MASK), /*!< Mmdc Core Aclk FastP0 Clock Gate.*/ + ccmCcgrGateMmdcCoreIpgClkP0 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG12_SHIFT, CCM_CCGR3_CG12_MASK), /*!< Mmdc Core Ipg Clk P0 Clock Gate.*/ + ccmCcgrGateMmdcCoreIpgClkP1 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG13_SHIFT, CCM_CCGR3_CG13_MASK), /*!< Mmdc Core Ipg Clk P1 Clock Gate.*/ + ccmCcgrGateOcramClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG14_SHIFT, CCM_CCGR3_CG14_MASK), /*!< Ocram Clock Gate.*/ + ccmCcgrGatePcieRoot = CCM_TUPLE(CCGR4, CCM_CCGR4_CG0_SHIFT, CCM_CCGR4_CG0_MASK), /*!< Pcie Clock Gate.*/ + ccmCcgrGateQspi2Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG5_SHIFT, CCM_CCGR4_CG5_MASK), /*!< Qspi2 Clock Gate.*/ + ccmCcgrGatePl301Mx6qper1Bch = CCM_TUPLE(CCGR4, CCM_CCGR4_CG6_SHIFT, CCM_CCGR4_CG6_MASK), /*!< Pl301Mx6qper1Bch Clock Gate.*/ + ccmCcgrGatePl301Mx6qper2Main = CCM_TUPLE(CCGR4, CCM_CCGR4_CG7_SHIFT, CCM_CCGR4_CG7_MASK), /*!< Pl301Mx6qper2Main Clock Gate.*/ + ccmCcgrGatePwm1Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG8_SHIFT, CCM_CCGR4_CG8_MASK), /*!< Pwm1 Clock Gate.*/ + ccmCcgrGatePwm2Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG9_SHIFT, CCM_CCGR4_CG9_MASK), /*!< Pwm2 Clock Gate.*/ + ccmCcgrGatePwm3Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG10_SHIFT, CCM_CCGR4_CG10_MASK), /*!< Pwm3 Clock Gate.*/ + ccmCcgrGatePwm4Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG11_SHIFT, CCM_CCGR4_CG11_MASK), /*!< Pwm4 Clock Gate.*/ + ccmCcgrGateRawnandUBchInptApb = CCM_TUPLE(CCGR4, CCM_CCGR4_CG12_SHIFT, CCM_CCGR4_CG12_MASK), /*!< RawnandUBchInptApb Clock Gate.*/ + ccmCcgrGateRawnandUGpmiBch = CCM_TUPLE(CCGR4, CCM_CCGR4_CG13_SHIFT, CCM_CCGR4_CG13_MASK), /*!< RawnandUGpmiBch Clock Gate.*/ + ccmCcgrGateRawnandUGpmiGpmiIo = CCM_TUPLE(CCGR4, CCM_CCGR4_CG14_SHIFT, CCM_CCGR4_CG14_MASK), /*!< RawnandUGpmiGpmiIo Clock Gate.*/ + ccmCcgrGateRawnandUGpmiInpApb = CCM_TUPLE(CCGR4, CCM_CCGR4_CG15_SHIFT, CCM_CCGR4_CG15_MASK), /*!< RawnandUGpmiInpApb Clock Gate.*/ + ccmCcgrGateRomClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG0_SHIFT, CCM_CCGR5_CG0_MASK), /*!< Rom Clock Gate.*/ + ccmCcgrGateSdmaClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG3_SHIFT, CCM_CCGR5_CG3_MASK), /*!< Sdma Clock Gate.*/ + ccmCcgrGateSpbaClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG6_SHIFT, CCM_CCGR5_CG6_MASK), /*!< Spba Clock Gate.*/ + ccmCcgrGateSpdifAudioClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG7_SHIFT, CCM_CCGR5_CG7_MASK), /*!< SpdifAudio Clock Gate.*/ + ccmCcgrGateSsi1Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG9_SHIFT, CCM_CCGR5_CG9_MASK), /*!< Ssi1 Clock Gate.*/ + ccmCcgrGateSsi2Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG10_SHIFT, CCM_CCGR5_CG10_MASK), /*!< Ssi2 Clock Gate.*/ + ccmCcgrGateSsi3Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG11_SHIFT, CCM_CCGR5_CG11_MASK), /*!< Ssi3 Clock Gate.*/ + ccmCcgrGateUartClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG12_SHIFT, CCM_CCGR5_CG12_MASK), /*!< Uart Clock Gate.*/ + ccmCcgrGateUartSerialClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG13_SHIFT, CCM_CCGR5_CG13_MASK), /*!< Uart Serial Clock Gate.*/ + ccmCcgrGateSai1Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG14_SHIFT, CCM_CCGR5_CG14_MASK), /*!< Sai1 Clock Gate.*/ + ccmCcgrGateSai2Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG15_SHIFT, CCM_CCGR5_CG15_MASK), /*!< Sai2 Clock Gate.*/ + ccmCcgrGateUsboh3Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG0_SHIFT, CCM_CCGR6_CG0_MASK), /*!< Usboh3 Clock Gate.*/ + ccmCcgrGateUsdhc1Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG1_SHIFT, CCM_CCGR6_CG1_MASK), /*!< Usdhc1 Clock Gate.*/ + ccmCcgrGateUsdhc2Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG2_SHIFT, CCM_CCGR6_CG2_MASK), /*!< Usdhc2 Clock Gate.*/ + ccmCcgrGateUsdhc3Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG3_SHIFT, CCM_CCGR6_CG3_MASK), /*!< Usdhc3 Clock Gate.*/ + ccmCcgrGateUsdhc4Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG4_SHIFT, CCM_CCGR6_CG4_MASK), /*!< Usdhc4 Clock Gate.*/ + ccmCcgrGateEimSlowClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG5_SHIFT, CCM_CCGR6_CG5_MASK), /*!< EimSlow Clock Gate.*/ + ccmCcgrGatePwm8Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG8_SHIFT, CCM_CCGR6_CG8_MASK), /*!< Pwm8 Clock Gate.*/ + ccmCcgrGateVadcClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG10_SHIFT, CCM_CCGR6_CG10_MASK), /*!< Vadc Clock Gate.*/ + ccmCcgrGateGisClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG11_SHIFT, CCM_CCGR6_CG11_MASK), /*!< Gis Clock Gate.*/ + ccmCcgrGateI2c4SerialClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG12_SHIFT, CCM_CCGR6_CG12_MASK), /*!< I2c4 Serial Clock Gate.*/ + ccmCcgrGatePwm5Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG13_SHIFT, CCM_CCGR6_CG13_MASK), /*!< Pwm5 Clock Gate.*/ + ccmCcgrGatePwm6Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG14_SHIFT, CCM_CCGR6_CG14_MASK), /*!< Pwm6 Clock Gate.*/ + ccmCcgrGatePwm7Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG15_SHIFT, CCM_CCGR6_CG15_MASK), /*!< Pwm7 Clock Gate.*/ +}; + +/*! @brief CCM gate control value. */ +enum _ccm_gate_value +{ + ccmClockNotNeeded = 0U, /*!< Clock always disabled.*/ + ccmClockNeededRun = 1U, /*!< Clock enabled when CPU is running.*/ + ccmClockNeededAll = 3U /*!< Clock always enabled.*/ +}; + +/*! @brief CCM override clock enable signal from module. */ +enum _ccm_overrided_enable_signal +{ + ccmOverridedSignalFromGpt = 1U << 5, /*!< Override clock enable signal from GPT.*/ + ccmOverridedSignalFromEpit = 1U << 6, /*!< Override clock enable signal from EPIT.*/ + ccmOverridedSignalFromUsdhc = 1U << 7, /*!< Override clock enable signal from USDHC.*/ + ccmOverridedSignalFromGpu = 1U << 10, /*!< Override clock enable signal from GPU.*/ + ccmOverridedSignalFromCan2Cpi = 1U << 28, /*!< Override clock enable signal from CAN2.*/ + ccmOverridedSignalFromCan1Cpi = 1U << 30 /*!< Override clock enable signal from CAN1.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CCM Root Clock Setting + * @{ + */ + +/*! + * @brief Set clock root mux. + * User maybe need to set more than one mux node according to the clock tree + * description on the reference manual. + * + * @param base CCM base pointer. + * @param ccmRootClk Root clock control (see @ref _ccm_root_clock_control enumeration). + * @param mux Root mux value (see @ref _ccm_rootmux_xxx enumeration). + */ +static inline void CCM_SetRootMux(CCM_Type * base, uint32_t ccmRootClk, uint32_t mux) +{ + CCM_TUPLE_REG(base, ccmRootClk) = (CCM_TUPLE_REG(base, ccmRootClk) & (~CCM_TUPLE_MASK(ccmRootClk))) | + (((uint32_t)((mux) << CCM_TUPLE_SHIFT(ccmRootClk))) & CCM_TUPLE_MASK(ccmRootClk)); +} + +/*! + * @brief Get clock root mux. + * In order to get the clock source of root, user maybe need to get more than one + * node's mux value to obtain the final clock source of root. + * + * @param base CCM base pointer. + * @param ccmRootClk Root clock control (see @ref _ccm_root_clock_control enumeration). + * @return Root mux value (see @ref _ccm_rootmux_xxx enumeration). + */ +static inline uint32_t CCM_GetRootMux(CCM_Type * base, uint32_t ccmRootClk) +{ + return (CCM_TUPLE_REG(base, ccmRootClk) & CCM_TUPLE_MASK(ccmRootClk)) >> CCM_TUPLE_SHIFT(ccmRootClk); +} + +/*! + * @brief Set root clock divider. + * User should set the dividers carefully according to the clock tree on + * the reference manual. Take care of that the setting of one divider value + * may affect several clock root. + * + * @param base CCM base pointer. + * @param ccmRootDiv Root divider control (see @ref _ccm_root_div_control enumeration) + * @param div Divider value (divider = div + 1). + */ +static inline void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRootDiv, uint32_t div) +{ + CCM_TUPLE_REG(base, ccmRootDiv) = (CCM_TUPLE_REG(base, ccmRootDiv) & (~CCM_TUPLE_MASK(ccmRootDiv))) | + (((uint32_t)((div) << CCM_TUPLE_SHIFT(ccmRootDiv))) & CCM_TUPLE_MASK(ccmRootDiv)); +} + +/*! + * @brief Get root clock divider. + * In order to get divider value of clock root, user should get specific + * divider value according to the clock tree description on reference manual. + * Then calculate the root clock with those divider value. + * + * @param base CCM base pointer. + * @param ccmRootDiv Root control (see @ref _ccm_root_div_control enumeration). + * @param div Pointer to divider value store address. + * @return Root divider value. + */ +static inline uint32_t CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRootDiv) +{ + return (CCM_TUPLE_REG(base, ccmRootDiv) & CCM_TUPLE_MASK(ccmRootDiv)) >> CCM_TUPLE_SHIFT(ccmRootDiv); +} + +/*! + * @brief Set handshake mask of MMDC module. + * During divider ratio mmdc_axi_podf change or sync mux periph2_clk_sel + * change (but not jtag) or SRC request during warm reset, mask handshake with mmdc module. + * + * @param base CCM base pointer. + * @param mask True: mask handshake with MMDC; False: allow handshake with MMDC. + */ +void CCM_SetMmdcHandshakeMask(CCM_Type * base, bool mask); + +/*@}*/ + +/*! + * @name CCM Gate Control + * @{ + */ + +/*! + * @brief Set CCGR gate control for each module + * User should set specific gate for each module according to the description + * of the table of system clocks, gating and override in CCM chapter of + * reference manual. Take care of that one module may need to set more than + * one clock gate. + * + * @param base CCM base pointer. + * @param ccmGate Gate control for each module (see @ref _ccm_ccgr_gate enumeration). + * @param control Gate control value (see @ref _ccm_gate_value). + */ +static inline void CCM_ControlGate(CCM_Type * base, uint32_t ccmGate, uint32_t control) +{ + CCM_TUPLE_REG(base, ccmGate) = (CCM_TUPLE_REG(base, ccmGate) & (~CCM_TUPLE_MASK(ccmGate))) | + (((uint32_t)((control) << CCM_TUPLE_SHIFT(ccmGate))) & CCM_TUPLE_MASK(ccmGate)); +} + +/*! + * @brief Set override or do not override clock enable signal from module. + * This is applicable only for modules whose clock enable signals are used. + * + * @param base CCM base pointer. + * @param signal Overrided enable signal from module (see @ref _ccm_overrided_enable_signal enumeration). + * @param control Override / Do not override clock enable signal from module. + * - true: override clock enable signal. + * - false: Do not override clock enable signal. + */ +void CCM_SetClockEnableSignalOverrided(CCM_Type * base, uint32_t signal, bool control); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CCM_IMX6SX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX6X/drivers/clock_freq.c b/devices/MCIMX6X/drivers/clock_freq.c new file mode 100644 index 000000000..7aacbc41d --- /dev/null +++ b/devices/MCIMX6X/drivers/clock_freq.c @@ -0,0 +1,265 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "clock_freq.h" +#include "ccm_imx6sx.h" +#include "ccm_analog_imx6sx.h" + +/*FUNCTION********************************************************************** + * + * Function Name : get_epit_clock_freq + * Description : Get clock frequency applys to the EPIIT module + * + *END**************************************************************************/ +uint32_t get_epit_clock_freq(EPIT_Type* base) +{ + uint32_t root; + uint32_t hz; + uint32_t divPerclkPodf, divIpgPodf, divAhbPodf, divPeriphClk2Podf; + + /* Different instance has the same clock root, it's different from i.mx7d. */ + /* Get the clock root according to the mux node of clock tree. */ + if(CCM_GetRootMux(CCM, ccmRootPerclkClkSel) == ccmRootmuxPerclkClkOsc24m) + { + root = ccmRootmuxPerclkClkOsc24m; + hz = 24000000; + divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf); + divIpgPodf = 0; + divAhbPodf = 0; + divPeriphClk2Podf = 0; + } + else if(CCM_GetRootMux(CCM, ccmRootPeriphClkSel) == ccmRootmuxPeriphClkPrePeriphClkSel) + { + root = CCM_GetRootMux(CCM, ccmRootPrePeriphClkSel); + /* Here do not show all the clock root source, + if user use other clock root source, such as PLL2_PFD2, please + add it as follows according to the clock tree of CCM in reference manual. */ + switch(root) + { + case ccmRootmuxPrePeriphClkPll2: + hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllSysControl); + divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf); + divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf); + divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf); + divPeriphClk2Podf = 0; + break; + default: + return 0; + } + } + else if(CCM_GetRootMux(CCM, ccmRootPeriphClk2Sel) == ccmRootmuxPeriphClk2OSC24m) + { + root = ccmRootmuxPeriphClk2OSC24m; + hz = 24000000; + divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf); + divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf); + divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf); + divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf); + } + else + { + root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel); + /* Here do not show all the clock root source, + if user use other clock root source, such as PLL3_BYP, please + add it as follows according to the clock tree of CCM in reference manual. */ + switch(root) + { + case ccmRootmuxPll3SwClkPll3: + hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control); + divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf); + divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf); + divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf); + divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf); + break; + default: + return 0; + } + } + + return hz / (divPerclkPodf + 1) / (divIpgPodf + 1) / (divAhbPodf + 1) / (divPeriphClk2Podf + 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : get_I2C_clock_freq + * Description : Get clock frequency applys to the I2C module + * + *END**************************************************************************/ +uint32_t get_i2c_clock_freq(I2C_Type* base) +{ + uint32_t root; + uint32_t hz; + uint32_t divPerclkPodf, divIpgPodf, divAhbPodf, divPeriphClk2Podf; + + /* Different instance has the same clock root, it's different from i.mx7d. */ + /* Get the clock root according to the mux node of clock tree. */ + if(CCM_GetRootMux(CCM, ccmRootPerclkClkSel) == ccmRootmuxPerclkClkOsc24m) + { + root = ccmRootmuxPerclkClkOsc24m; + hz = 24000000; + divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf); + divIpgPodf = 0; + divAhbPodf = 0; + divPeriphClk2Podf = 0; + } + else if(CCM_GetRootMux(CCM, ccmRootPeriphClkSel) == ccmRootmuxPeriphClkPrePeriphClkSel) + { + root = CCM_GetRootMux(CCM, ccmRootPrePeriphClkSel); + /* Here do not show all the clock root source, + if user use other clock root source, such as PLL2_PFD2, please + add it as follows according to the clock tree of CCM in reference manual. */ + switch(root) + { + case ccmRootmuxPrePeriphClkPll2: + hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllSysControl); + divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf); + divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf); + divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf); + divPeriphClk2Podf = 0; + break; + default: + return 0; + } + } + else if(CCM_GetRootMux(CCM, ccmRootPeriphClk2Sel) == ccmRootmuxPeriphClk2OSC24m) + { + root = ccmRootmuxPeriphClk2OSC24m; + hz = 24000000; + divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf); + divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf); + divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf); + divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf); + } + else + { + root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel); + /* Here do not show all the clock root source, + if user use other clock root source, such as PLL3_BYP, please + add it as follows according to the clock tree of CCM in reference manual. */ + switch(root) + { + case ccmRootmuxPll3SwClkPll3: + hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control); + divPerclkPodf = CCM_GetRootDivider(CCM, ccmRootPerclkPodf); + divIpgPodf = CCM_GetRootDivider(CCM, ccmRootIpgPodf); + divAhbPodf = CCM_GetRootDivider(CCM, ccmRootAhbPodf); + divPeriphClk2Podf = CCM_GetRootDivider(CCM, ccmRootPeriphClk2Podf); + break; + default: + return 0; + } + } + + return hz / (divPerclkPodf + 1) / (divIpgPodf + 1) / (divAhbPodf + 1) / (divPeriphClk2Podf + 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : get_ecspi_clock_freq + * Description : Get clock frequency applys to the ECSPI module + * + *END**************************************************************************/ +uint32_t get_ecspi_clock_freq(ECSPI_Type* base) +{ + uint32_t root; + uint32_t hz; + uint32_t divEcspiClkPodf, divStatic; + + if(CCM_GetRootMux(CCM, ccmRootEcspiClkSel) == ccmRootmuxEcspiClkOsc24m) + { + root = ccmRootmuxEcspiClkOsc24m; + hz = 24000000; + divEcspiClkPodf = CCM_GetRootDivider(CCM, ccmRootEcspiClkPodf); + divStatic = 0; + } + else + { + root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel); + /* Here do not show all the clock root source, + if user use other clock root source, such as PLL3_BYP, please + add it as follows according to the clock tree of CCM in reference manual. */ + switch(root) + { + case ccmRootmuxPll3SwClkPll3: + hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control); + divEcspiClkPodf = CCM_GetRootDivider(CCM, ccmRootEcspiClkPodf); + divStatic = 7; + break; + default: + return 0; + } + } + + return hz / (divEcspiClkPodf + 1) / (divStatic + 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : get_uart_clock_freq + * Description : Get clock frequency applys to the UART module + * + *END**************************************************************************/ +uint32_t get_uart_clock_freq(UART_Type* base) +{ + uint32_t root; + uint32_t hz; + uint32_t divUartClkPodf, divStatic; + + if(CCM_GetRootMux(CCM, ccmRootUartClkSel) == ccmRootmuxUartClkOsc24m) + { + root = ccmRootmuxUartClkOsc24m; + hz = 24000000; + divUartClkPodf = CCM_GetRootDivider(CCM, ccmRootUartClkPodf); + divStatic = 0; + } + else + { + root = CCM_GetRootMux(CCM, ccmRootPll3SwClkSel); + /* Here do not show all the clock root source, + if user use other clock root source, such as PLL3_BYP, please + add it as follows according to the clock tree of CCM in reference manual. */ + switch(root) + { + case ccmRootmuxPll3SwClkPll3: + hz = CCM_ANALOG_GetPllFreq(CCM_ANALOG, ccmAnalogPllUsb1Control); + divUartClkPodf = CCM_GetRootDivider(CCM, ccmRootUartClkPodf); + divStatic = 5; + break; + default: + return 0; + } + } + + return hz / (divUartClkPodf + 1) / (divStatic + 1); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX6X/drivers/clock_freq.h b/devices/MCIMX6X/drivers/clock_freq.h new file mode 100644 index 000000000..1d05e29e0 --- /dev/null +++ b/devices/MCIMX6X/drivers/clock_freq.h @@ -0,0 +1,90 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CLOCK_FREQ_H__ +#define __CLOCK_FREQ_H__ + +#include "device_imx.h" + +/*! + * @addtogroup clock_freq_helper + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Get clock frequency applys to the EPIT module + * + * @param base EPIT base pointer. + * @return clock frequency (in HZ) applys to the EPIT module + */ +uint32_t get_epit_clock_freq(EPIT_Type* base); + +/*! + * @brief Get clock frequency applys to the I2C module + * + * @param base I2C base pointer. + * @return clock frequency (in HZ) applys to the I2C module + */ +uint32_t get_i2c_clock_freq(I2C_Type* base); + +/*! + * @brief Get clock frequency applys to the ECSPI module + * + * @param base ECSPI base pointer. + * @return clock frequency (in HZ) applys to the ECSPI module + */ +uint32_t get_ecspi_clock_freq(ECSPI_Type* base); + +/*! + * @brief Get clock frequency applys to the UART module + * + * @param base UART base pointer. + * @return clock frequency (in HZ) applys to the UART module + */ +uint32_t get_uart_clock_freq(UART_Type* base); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CLOCK_FREQ_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX6X/drivers/rdc_defs_imx6sx.h b/devices/MCIMX6X/drivers/rdc_defs_imx6sx.h new file mode 100644 index 000000000..abcfa1b5b --- /dev/null +++ b/devices/MCIMX6X/drivers/rdc_defs_imx6sx.h @@ -0,0 +1,210 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RDC_DEFS_IMX6SX__ +#define __RDC_DEFS_IMX6SX__ + +/*! + * @addtogroup rdc_def_imx6sx + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief RDC master assignment. */ +enum _rdc_mda +{ + rdcMdaA9L2Cache = 0U, /*!< A9 L2 Cache RDC Master. */ + rdcMdaM4 = 1U, /*!< M4 RDC Master. */ + rdcMdaGpu = 2U, /*!< GPU RDC Master. */ + rdcMdaCsi1 = 3U, /*!< Csi1 RDC Master. */ + rdcMdaCsi2 = 4U, /*!< Csi2 RDC Master. */ + rdcMdaLcdif1 = 5U, /*!< Lcdif1 RDC Master. */ + rdcMdaLcdif2 = 6U, /*!< Lcdif2 RDC Master. */ + rdcMdaPxp = 7U, /*!< Pxp RDC Master. */ + rdcMdaPcieCtrl = 8U, /*!< Pcie Ctrl RDC Master. */ + rdcMdaDap = 9U, /*!< Dap RDC Master. */ + rdcMdaCaam = 10U, /*!< Caam RDC Master. */ + rdcMdaSdmaPeriph = 11U, /*!< Sdma Periph RDC Master. */ + rdcMdaSdmaBurst = 12U, /*!< Sdma Burst RDC Master. */ + rdcMdaApbhdma = 13U, /*!< Apbhdma RDC Master. */ + rdcMdaRawnand = 14U, /*!< Rawnand RDC Master. */ + rdcMdaUsdhc1 = 15U, /*!< Usdhc1 RDC Master. */ + rdcMdaUsdhc2 = 16U, /*!< Usdhc2 RDC Master. */ + rdcMdaUsdhc3 = 17U, /*!< Usdhc3 RDC Master. */ + rdcMdaUsdhc4 = 18U, /*!< Usdhc4 RDC Master. */ + rdcMdaUsb = 19U, /*!< USB RDC Master. */ + rdcMdaMlb = 20U, /*!< MLB RDC Master. */ + rdcMdaTestPort = 21U, /*!< Test Port RDC Master. */ + rdcMdaEnet1Tx = 22U, /*!< Enet1 Tx RDC Master. */ + rdcMdaEnet1Rx = 23U, /*!< Enet1 Rx Master. */ + rdcMdaEnet2Tx = 24U, /*!< Enet2 Tx RDC Master. */ + rdcMdaEnet2Rx = 25U, /*!< Enet2 Rx RDC Master. */ + rdcMdaSdmaPort = 26U, /*!< Sdma Port RDC Master. */ +}; + +/*! @brief RDC peripheral assignment. */ +enum _rdc_pdap +{ + rdcPdapPwm1 = 0U, /*!< Pwm1 RDC Peripheral. */ + rdcPdapPwm2 = 1U, /*!< Pwm2 RDC Peripheral. */ + rdcPdapPwm3 = 2U, /*!< Pwm3 RDC Peripheral. */ + rdcPdapPwm4 = 3U, /*!< Pwm4 RDC Peripheral. */ + rdcPdapCan1 = 4U, /*!< Can1 RDC Peripheral. */ + rdcPdapCan2 = 5U, /*!< Can2 RDC Peripheral. */ + rdcPdapGpt = 6U, /*!< Gpt RDC Peripheral. */ + rdcPdapGpio1 = 7U, /*!< Gpio1 RDC Peripheral. */ + rdcPdapGpio2 = 8U, /*!< Gpio2 RDC Peripheral. */ + rdcPdapGpio3 = 9U, /*!< Gpio3 RDC Peripheral. */ + rdcPdapGpio4 = 10U, /*!< Gpio4 RDC Peripheral. */ + rdcPdapGpio5 = 11U, /*!< Gpio5 RDC Peripheral. */ + rdcPdapGpio6 = 12U, /*!< Gpio6 RDC Peripheral. */ + rdcPdapGpio7 = 13U, /*!< Gpio7 RDC Peripheral. */ + rdcPdapKpp = 14U, /*!< Kpp RDC Peripheral. */ + rdcPdapWdog1 = 15U, /*!< Wdog1 RDC Peripheral. */ + rdcPdapWdog2 = 16U, /*!< Wdog2 RDC Peripheral. */ + rdcPdapCcm = 17U, /*!< Ccm RDC Peripheral. */ + rdcPdapAnatopDig = 18U, /*!< AnatopDig RDC Peripheral. */ + rdcPdapSnvsHp = 19U, /*!< SnvsHp RDC Peripheral. */ + rdcPdapEpit1 = 20U, /*!< Epit1 RDC Peripheral. */ + rdcPdapEpit2 = 21U, /*!< Epit2 RDC Peripheral. */ + rdcPdapSrc = 22U, /*!< Src RDC Peripheral. */ + rdcPdapGpc = 23U, /*!< Gpc RDC Peripheral. */ + rdcPdapIomuxc = 24U, /*!< Iomuxc RDC Peripheral. */ + rdcPdapIomuxcGpr = 25U, /*!< IomuxcGpr RDC Peripheral. */ + rdcPdapCanfdCan1 = 26U, /*!< Canfd Can1 RDC Peripheral. */ + rdcPdapSdma = 27U, /*!< Sdma RDC Peripheral. */ + rdcPdapCanfdCan2 = 28U, /*!< Canfd Can2 RDC Peripheral. */ + rdcPdapRdcSema421 = 29U, /*!< Rdc Sema421 RDC Peripheral. */ + rdcPdapRdcSema422 = 30U, /*!< Rdc Sema422 RDC Peripheral. */ + rdcPdapRdc = 31U, /*!< Rdc RDC Peripheral. */ + rdcPdapAipsTz1GlobalEnable1 = 32U, /*!< AipsTz1GlobalEnable1 RDC Peripheral. */ + rdcPdapAipsTz1GlobalEnable2 = 33U, /*!< AipsTz1GlobalEnable2 RDC Peripheral. */ + rdcPdapUsb02hPl301 = 34U, /*!< Usb02hPl301 RDC Peripheral. */ + rdcPdapUsb02hUsb = 35U, /*!< Usb02hUsb RDC Peripheral. */ + rdcPdapEnet1 = 36U, /*!< Enet1 RDC Peripheral. */ + rdcPdapMlb2550 = 37U, /*!< Mlb2550 RDC Peripheral. */ + rdcPdapUsdhc1 = 38U, /*!< Usdhc1 RDC Peripheral. */ + rdcPdapUsdhc2 = 39U, /*!< Usdhc2 RDC Peripheral. */ + rdcPdapUsdhc3 = 40U, /*!< Usdhc3 RDC Peripheral. */ + rdcPdapUsdhc4 = 41U, /*!< Usdhc4 RDC Peripheral. */ + rdcPdapI2c1 = 42U, /*!< I2c1 RDC Peripheral. */ + rdcPdapI2c2 = 43U, /*!< I2c2 RDC Peripheral. */ + rdcPdapI2c3 = 44U, /*!< I2c3 RDC Peripheral. */ + rdcPdapRomcp = 45U, /*!< Romcp RDC Peripheral. */ + rdcPdapMmdc = 46U, /*!< Mmdc RDC Peripheral. */ + rdcPdapEnet2 = 47U, /*!< Enet2 RDC Peripheral. */ + rdcPdapEim = 48U, /*!< Eim RDC Peripheral. */ + rdcPdapOcotpCtrlWrapper = 49U, /*!< OcotpCtrlWrapper RDC Peripheral. */ + rdcPdapCsu = 50U, /*!< Csu RDC Peripheral. */ + rdcPdapPerfmon1 = 51U, /*!< Perfmon1 RDC Peripheral. */ + rdcPdapPerfmon2 = 52U, /*!< Perfmon2 RDC Peripheral. */ + rdcPdapAxiMon = 53U, /*!< AxiMon RDC Peripheral. */ + rdcPdapTzasc1 = 54U, /*!< Tzasc1 RDC Peripheral. */ + rdcPdapSai1 = 55U, /*!< Sai1 RDC Peripheral. */ + rdcPdapAudmux = 56U, /*!< Audmux RDC Peripheral. */ + rdcPdapSai2 = 57U, /*!< Sai2 RDC Peripheral. */ + rdcPdapQspi1 = 58U, /*!< Qspi1 RDC Peripheral. */ + rdcPdapQspi2 = 59U, /*!< Qspi2 RDC Peripheral. */ + rdcPdapUart2 = 60U, /*!< Uart2 RDC Peripheral. */ + rdcPdapUart3 = 61U, /*!< Uart3 RDC Peripheral. */ + rdcPdapUart4 = 62U, /*!< Uart4 RDC Peripheral. */ + rdcPdapUart5 = 63U, /*!< Uart5 RDC Peripheral. */ + rdcPdapI2c4 = 64U, /*!< I2c4 RDC Peripheral. */ + rdcPdapQosc = 65U, /*!< Qosc RDC Peripheral. */ + rdcPdapCaam = 66U, /*!< Caam RDC Peripheral. */ + rdcPdapDap = 67U, /*!< Dap RDC Peripheral. */ + rdcPdapAdc1 = 68U, /*!< Adc1 RDC Peripheral. */ + rdcPdapAdc2 = 69U, /*!< Adc2 RDC Peripheral. */ + rdcPdapWdog3 = 70U, /*!< Wdog3 RDC Peripheral. */ + rdcPdapEcspi5 = 71U, /*!< Ecspi5 RDC Peripheral. */ + rdcPdapSema4 = 72U, /*!< Sema4 RDC Peripheral. */ + rdcPdapMuA = 73U, /*!< MuA RDC Peripheral. */ + rdcPdapCanfdCpu = 74U, /*!< Canfd Cpu RDC Peripheral. */ + rdcPdapMuB = 75U, /*!< MuB RDC Peripheral. */ + rdcPdapUart6 = 76U, /*!< Uart6 RDC Peripheral. */ + rdcPdapPwm5 = 77U, /*!< Pwm5 RDC Peripheral. */ + rdcPdapPwm6 = 78U, /*!< Pwm6 RDC Peripheral. */ + rdcPdapPwm7 = 79U, /*!< Pwm7 RDC Peripheral. */ + rdcPdapPwm8 = 80U, /*!< Pwm8 RDC Peripheral. */ + rdcPdapAipsTz3GlobalEnable0 = 81U, /*!< AipsTz3GlobalEnable0 RDC Peripheral. */ + rdcPdapAipsTz3GlobalEnable1 = 82U, /*!< AipsTz3GlobalEnable1 RDC Peripheral. */ + rdcPdapSpdif = 84U, /*!< Spdif RDC Peripheral. */ + rdcPdapEcspi1 = 85U, /*!< Ecspi1 RDC Peripheral. */ + rdcPdapEcspi2 = 86U, /*!< Ecspi2 RDC Peripheral. */ + rdcPdapEcspi3 = 87U, /*!< Ecspi3 RDC Peripheral. */ + rdcPdapEcspi4 = 88U, /*!< Ecspi4 RDC Peripheral. */ + rdcPdapUart1 = 91U, /*!< Uart1 RDC Peripheral. */ + rdcPdapEsai = 92U, /*!< Esai RDC Peripheral. */ + rdcPdapSsi1 = 93U, /*!< Ssi1 RDC Peripheral. */ + rdcPdapSsi2 = 94U, /*!< Ssi2 RDC Peripheral. */ + rdcPdapSsi3 = 95U, /*!< Ssi3 RDC Peripheral. */ + rdcPdapAsrc = 96U, /*!< Asrc RDC Peripheral. */ + rdcPdapSpbaMaMegamix = 98U, /*!< SpbaMaMegamix RDC Peripheral. */ + rdcPdapGis = 99U, /*!< Gis RDC Peripheral. */ + rdcPdapDcic1 = 100U, /*!< Dcic1 RDC Peripheral. */ + rdcPdapDcic2 = 101U, /*!< Dcic2 RDC Peripheral. */ + rdcPdapCsi1 = 102U, /*!< Csi1 RDC Peripheral. */ + rdcPdapPxp = 103U, /*!< Pxp RDC Peripheral. */ + rdcPdapCsi2 = 104U, /*!< Csi2 RDC Peripheral. */ + rdcPdapLcdif1 = 105U, /*!< Lcdif1 RDC Peripheral. */ + rdcPdapLcdif2 = 106U, /*!< Lcdif2 RDC Peripheral. */ + rdcPdapVadc = 107U, /*!< Vadc RDC Peripheral. */ + rdcPdapVdec = 108U, /*!< Vdec RDC Peripheral. */ + rdcPdapSpDisplaymix = 109U, /*!< SpDisplaymix RDC Peripheral. */ +}; + +/*! @brief RDC memory region */ +enum _rdc_mr +{ + rdcMrMmdc = 0U, /*!< alignment 4096 */ + rdcMrMmdcLast = 7U, /*!< alignment 4096 */ + rdcMrQspi1 = 8U, /*!< alignment 4096 */ + rdcMrQspi1Last = 15U, /*!< alignment 4096 */ + rdcMrQspi2 = 16U, /*!< alignment 4096 */ + rdcMrQspi2Last = 23U, /*!< alignment 4096 */ + rdcMrWeim = 24U, /*!< alignment 4096 */ + rdcMrWeimLast = 31U, /*!< alignment 4096 */ + rdcMrPcie = 32U, /*!< alignment 4096 */ + rdcMrPcieLast = 39U, /*!< alignment 4096 */ + rdcMrOcram = 40U, /*!< alignment 128 */ + rdcMrOcramLast = 44U, /*!< alignment 128 */ + rdcMrOcramS = 45U, /*!< alignment 128 */ + rdcMrOcramSLast = 49U, /*!< alignment 128 */ + rdcMrOcramL2 = 50U, /*!< alignment 128 */ + rdcMrOcramL2Last = 54U, /*!< alignment 128 */ +}; + +#endif /* __RDC_DEFS_IMX6SX__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX7D/MCIMX7D_M4.h b/devices/MCIMX7D/MCIMX7D_M4.h new file mode 100644 index 000000000..710d8fd0f --- /dev/null +++ b/devices/MCIMX7D/MCIMX7D_M4.h @@ -0,0 +1,44765 @@ +/* +** ################################################################### +** Processors: MCIMX7D_M4 +** +** Compilers: Keil ARM C/C++ Compiler +** Freescale C/C++ for Embedded ARM +** GNU C Compiler +** GNU C Compiler - CodeSourcery Sourcery G++ +** IAR ANSI C/C++ Compiler for ARM +** +** Reference manual: +** Version: rev. 1.0, 2015-07-15 +** Build: b150715 +** +** Abstract: +** CMSIS Peripheral Access Layer for MCIMX7D_M4 +** +** Copyright (c) 1997 - 2015 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** Revisions: +** - rev. 1.0 (2015-07-15) +** Initial version . +** +** ################################################################### +*/ + +/*! + * @file MCIMX7D_M4.h + * @version 1.0 + * @date 2015-07-15 + * @brief CMSIS Peripheral Access Layer for MCIMX7D_M4 + * + * CMSIS Peripheral Access Layer for MCIMX7D_M4 + */ + + +/* ---------------------------------------------------------------------------- + -- MCU activation + ---------------------------------------------------------------------------- */ + +/* Prevention from multiple including the same memory map */ +#if !defined(MCIMX7D_M4_H_) /* Check if memory map has not been already included */ +#define MCIMX7D_M4_H_ +#define MCU_MCIMX7D_M4 + + +/* Check if another memory map has not been also included */ +#if (defined(MCU_ACTIVE)) + #error MCIMX7D_M4 memory map: There is already included another memory map. Only one memory map can be included. +#endif /* (defined(MCU_ACTIVE)) */ +#define MCU_ACTIVE + +#include + +/** Memory map major version (memory maps with equal major version number are + * compatible) */ +#define MCU_MEM_MAP_VERSION 0x0100u +/** Memory map minor version */ +#define MCU_MEM_MAP_VERSION_MINOR 0x0000u + + +/* ---------------------------------------------------------------------------- + -- Interrupt vector numbers + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Interrupt_vector_numbers Interrupt vector numbers + * @{ + */ + +/** Interrupt Number Definitions */ +#define NUMBER_OF_INT_VECTORS 144 /**< Number of interrupts in the Vector table */ + +typedef enum IRQn { + /* Auxiliary constants */ + NotAvail_IRQn = -128, /**< Not available device specific interrupt */ + + /* Core interrupts */ + NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */ + HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */ + MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */ + BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */ + UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */ + SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */ + DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */ + PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */ + SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */ + + /* Device specific interrupts */ + GPR_IRQn = 0, /**< Used to notify cores on exception condition while boot */ + DAP_IRQn = 1, /**< DAP Interrupt */ + SDMA_IRQn = 2, /**< AND of all 48 SDMA interrupts (events) from all the channels */ + DBGMON_IRQn = 3, /**< DBGMON Sync Interrupt */ + SNVS_IRQn = 4, /**< ON-OFF button press shorter than 5 seconds (pulse event) */ + LCDIF_IRQn = 5, /**< LCDIF Sync Interrupt */ + SIM2_IRQn = 6, /**< SIM Interrupt */ + CSI_IRQn = 7, /**< CSI Interrupt */ + PXP1_IRQn = 8, /**< PXP Interrupt */ + Reserved_IRQn = 9, /**< Reserved */ + WDOG3_IRQn = 10, /**< Watchdog Timer reset */ + SEMA4_HS_M4_IRQn = 11, /**< SEMA4-HS M4 Interrupt Request */ + APBHDMA_IRQn = 12, /**< GPMI operation channel 0 description complete interrupt */ + EIM_IRQn = 13, /**< EIM Interrupt */ + BCH_IRQn = 14, /**< BCH operation complete interrupt */ + GPMI_IRQn = 15, /**< GPMI operation TIMEOUT ERROR interrupt */ + UART6_IRQn = 16, /**< UART-6 ORed interrupt */ + FTM1_IRQn = 17, /**< Flex Timer1 Fault / Counter / Channel interrupt */ + FTM2_IRQn = 18, /**< Flex Timer2 Fault / Counter / Channel interrupt */ + SNVS_CONSOLIDATED_IRQn = 19, /**< SRTC Consolidated Interrupt. Non TZ. */ + SNVS_SECURITY_IRQn = 20, /**< SRTC Security Interrupt. TZ. */ + CSU_IRQn = 21, /**< CSU Interrupt Request. Indicates to the processor that one or more alarm inputs were asserted */ + uSDHC1_IRQn = 22, /**< uSDHC1 Enhanced SDHC Interrupt Request */ + uSDHC2_IRQn = 23, /**< uSDHC2 Enhanced SDHC Interrupt Request */ + uSDHC3_IRQn = 24, /**< uSDHC3 Enhanced SDHC Interrupt Request */ + MIPI_CSI_IRQn = 25, /**< MIPI CSI interrupt */ + UART1_IRQn = 26, /**< UART-1 ORed interrupt */ + UART2_IRQn = 27, /**< UART-2 ORed interrupt */ + UART3_IRQn = 28, /**< UART-3 ORed interrupt */ + UART4_IRQn = 29, /**< UART-4 ORed interrupt */ + UART5_IRQn = 30, /**< UART-5 ORed interrupt */ + eCSPI1_IRQn = 31, /**< eCSPI1 interrupt request line to the core. */ + eCSPI2_IRQn = 32, /**< eCSPI2 interrupt request line to the core. */ + eCSPI3_IRQn = 33, /**< eCSPI3 interrupt request line to the core. */ + eCSPI4_IRQn = 34, /**< eCSPI4 interrupt request line to the core. */ + I2C1_IRQn = 35, /**< I2C-1 Interrupt */ + I2C2_IRQn = 36, /**< I2C-2 Interrupt */ + I2C3_IRQn = 37, /**< I2C-3 Interrupt */ + I2C4_IRQn = 38, /**< I2C-4 Interrupt */ + RDC_IRQn = 39, /**< RDC interrupt */ + USB_OH3_OTG2_1_IRQn = 40, /**< USB OH3 OTG2 */ + MIPI_DSI_IRQn = 41, /**< MIPI CSI Interrupt */ + USB_OH3_OTG2_2_IRQn = 42, /**< USB OH3 OTG2 */ + USB_OH2_OTG_IRQn = 43, /**< USB OH2 OTG */ + USB_OTG1_IRQn = 44, /**< USB OTG1 Interrupt */ + USB_OTG2_IRQn = 45, /**< USB OTG2 Interrupt */ + PXP2_IRQn = 46, /**< PXP interrupt */ + SCTR1_IRQn = 47, /**< ISO7816IP Interrupt */ + SCTR2_IRQn = 48, /**< ISO7816IP Interrupt */ + Analog_TempSensor_IRQn = 49, /**< TempSensor (Temperature low alarm). */ + SAI3_IRQn = 50, /**< SAI3 Receive / Transmit Interrupt */ + Analog_brown_out_IRQn = 51, /**< Brown-out event on either analog regulators. */ + GPT4_IRQn = 52, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPT3_IRQn = 53, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPT2_IRQn = 54, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPT1_IRQn = 55, /**< OR of GPT Rollover interrupt line, Input Capture 1 and 2 lines, Output Compare 1,2, and 3 Interrupt lines */ + GPIO1_INT7_IRQn = 56, /**< Active HIGH Interrupt from INT7 from GPIO */ + GPIO1_INT6_IRQn = 57, /**< Active HIGH Interrupt from INT6 from GPIO */ + GPIO1_INT5_IRQn = 58, /**< Active HIGH Interrupt from INT5 from GPIO */ + GPIO1_INT4_IRQn = 59, /**< Active HIGH Interrupt from INT4 from GPIO */ + GPIO1_INT3_IRQn = 60, /**< Active HIGH Interrupt from INT3 from GPIO */ + GPIO1_INT2_IRQn = 61, /**< Active HIGH Interrupt from INT2 from GPIO */ + GPIO1_INT1_IRQn = 62, /**< Active HIGH Interrupt from INT1 from GPIO */ + GPIO1_INT0_IRQn = 63, /**< Active HIGH Interrupt from INT0 from GPIO */ + GPIO1_INT15_0_IRQn = 64, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */ + GPIO1_INT31_16_IRQn = 65, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */ + GPIO2_INT15_0_IRQn = 66, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */ + GPIO2_INT31_16_IRQn = 67, /**< Combined interrupt indication for GPIO2 signals 16 throughout 31 */ + GPIO3_INT15_0_IRQn = 68, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */ + GPIO3_INT31_16_IRQn = 69, /**< Combined interrupt indication for GPIO3 signals 16 throughout 31 */ + GPIO4_INT15_0_IRQn = 70, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */ + GPIO4_INT31_16_IRQn = 71, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */ + GPIO5_INT15_0_IRQn = 72, /**< Combined interrupt indication for GPIO5 signals 0 throughout 15 */ + GPIO5_INT31_16_IRQn = 73, /**< Combined interrupt indication for GPIO5 signals 16 throughout 31 */ + GPIO6_INT15_0_IRQn = 74, /**< Combined interrupt indication for GPIO6 signals 0 throughtout 15 */ + GPIO6_INT31_16_IRQn = 75, /**< Combined interrupt indication for GPIO6 signals 16 throughtout 31 */ + GPIO7_INT15_0_IRQn = 76, /**< Combined interrupt indication for GPIO7 signals 0 throughout 15 */ + GPIO7_INT31_16_IRQn = 77, /**< Combined interrupt indication for GPIO7 signals 16 throughout 31 */ + WDOG1_IRQn = 78, /**< Watchdog Timer reset */ + WDOG2_IRQn = 79, /**< Watchdog Timer reset */ + KPP_IRQn = 80, /**< Keypad Interrupt */ + PWM1_IRQn = 81, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM2_IRQn = 82, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM3_IRQn = 83, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + PWM4_IRQn = 84, /**< Cumulative interrupt line. OR of Rollover Interrupt line, Compare Interrupt line and FIFO Waterlevel crossing interrupt line */ + CCM1_IRQn = 85, /**< CCM, Interrupt Request 1 */ + CCM2_IRQn = 86, /**< CCM, Interrupt Request 2 */ + GPC_IRQn = 87, /**< GPC Interrupt Request 1 */ + MU_A7_IRQn = 88, /**< Interrupt to A7 */ + SRC_IRQn = 89, /**< SRC interrupt request */ + SIM1_IRQn = 90, /**< Sim Interrupt */ + RTIC_IRQn = 91, /**< RTIC Interrupt */ + CPU_IRQn = 92, /**< Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[0]) + Performance Unit Interrupts from Cheetah (interrnally: PMUIRQ[1]) */ + CPU_CTI_IRQn = 93, /**< CTI trigger outputs (internal: nCTIIRQ[0]) + CTI trigger outputs (internal: nCTIIRQ[1]) */ + CCM_SRC_GPC_IRQn = 94, /**< SRC GPC Combined CPU wdog interrupts (4x) out of SRC. */ + SAI1_IRQn = 95, /**< SAI1 Receive / Transmit Interrupt */ + SAI2_IRQn = 96, /**< SAI2 Receive / Transmit Interrupt */ + MU_M4_IRQn = 97, /**< Interrupt to M4 */ + ADC1_IRQn = 98, /**< ADC-1 Interrupt */ + ADC2_IRQn = 99, /**< ADC-2 Interrupt */ + ENET2_MAC0_TRANS1_IRQn = 100, /**< MAC 0 Receive / Transmit Frame / Buffer Done */ + ENET2_MAC0_TRANS2_IRQn = 101, /**< MAC 0 Receive / Transmit Frame / Buffer Done */ + ENET2_MAC0_IRQ_IRQn = 102, /**< MAC 0 IRQ */ + ENET2_1588_TIMER_IRQ_IRQn = 103, /**< MAC 0 1588 Timer Interrupt - synchronous */ + TPR_IRQn = 104, /**< IRQ TPR IRQ */ + CAAM_QUEUE_IRQn = 105, /**< WRAPPER CAAM interrupt queue for JQ */ + CAAM_ERROR_IRQn = 106, /**< WRAPPER CAAM interrupt queue for JQ */ + QSPI_IRQn = 107, /**< QSPI Interrupt */ + TZASC1_IRQn = 108, /**< TZASC (PL380) interrupt */ + WDOG4_IRQn = 109, /**< Watchdog Timer reset */ + FLEXCAN1_IRQn = 110, /**< FlexCAN1 Interrupt */ + FLEXCAN2_IRQn = 111, /**< FlexCAN2 Interrupt */ + PERFMON1_IRQn = 112, /**< General interrupt */ + PERFMON2_IRQn = 113, /**< General interrupt */ + CAAM_WRAPPER1_IRQn = 114, /**< CAAM interrupt queue for JQ */ + CAAM_WRAPPER2_IRQn = 115, /**< Recoverable error interrupt */ + SEMA4_HS_A7_IRQn = 116, /**< SEMA4-HS processor A7 Interrupt Request */ + EPDC_IRQn = 117, /**< EPDC Interrupt */ + ENET1_MAC0_TRANS1_IRQn = 118, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET1_MAC0_TRANS2_IRQn = 119, /**< MAC 0 Receive / Trasmit Frame / Buffer Done */ + ENET1_MAC0_IRQn = 120, /**< MAC 0 IRQ */ + ENET1_1588_TIMER_IRQn = 121, /**< MAC 0 1588 Timer Interrupt - synchronous */ + PCIE_CTRL1_IRQn = 122, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL2_IRQn = 123, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL3_IRQn = 124, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + PCIE_CTRL4_IRQn = 125, /**< Coming from GLUE logic, of set / reset FF, driven by PCIE signals. */ + UART7_IRQn = 126, /**< UART-7 ORed interrupt */ + PCIE_CTRL_REQUEST_IRQn = 127, /**< Channels [63:32] interrupts requests */ +} IRQn_Type; + +/*! + * @} + */ /* end of group Interrupt_vector_numbers */ + +/* ---------------------------------------------------------------------------- + -- Cortex M4 Core Configuration + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration + * @{ + */ + +#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */ +#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */ +#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */ +#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */ + +#include "core_cm4.h" /* Core Peripheral Access Layer */ + +/*! + * @} + */ /* end of group Cortex_Core_Configuration */ + + +/* ---------------------------------------------------------------------------- + -- Device Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup Peripheral_access_layer Device Peripheral Access Layer + * @{ + */ + + +/* +** Start of section using anonymous unions +*/ + +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif +/* ---------------------------------------------------------------------------- + -- ADC Peripheral Access Layer + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer + * @{ + */ + +/** ADC - Register Layout Typedef */ +typedef struct { + __IO uint32_t CH_A_CFG1; /**< Channel A configuration 1, offset: 0x0 */ + uint8_t RESERVED_0[12]; + __IO uint32_t CH_A_CFG2; /**< Channel A configuration 2, offset: 0x10 */ + uint8_t RESERVED_1[12]; + __IO uint32_t CH_B_CFG1; /**< , offset: 0x20 */ + uint8_t RESERVED_2[12]; + __IO uint32_t CH_B_CFG2; /**< Channel B Configuration 2, offset: 0x30 */ + uint8_t RESERVED_3[12]; + __IO uint32_t CH_C_CFG1; /**< Channel C Configuration 1, offset: 0x40 */ + uint8_t RESERVED_4[12]; + __IO uint32_t CH_C_CFG2; /**< Channel C Configuration 2, offset: 0x50 */ + uint8_t RESERVED_5[12]; + __IO uint32_t CH_D_CFG1; /**< Channel D Configuration 1, offset: 0x60 */ + uint8_t RESERVED_6[12]; + __IO uint32_t CH_D_CFG2; /**< Channel D Configuration 2, offset: 0x70 */ + uint8_t RESERVED_7[12]; + __IO uint32_t CH_SW_CFG; /**< Channel Software Configuration, offset: 0x80 */ + uint8_t RESERVED_8[12]; + __IO uint32_t TIMER_UNIT; /**< Timer Unit, offset: 0x90 */ + uint8_t RESERVED_9[12]; + __IO uint32_t DMA_FIFO; /**< DMA FIFO, offset: 0xA0 */ + uint8_t RESERVED_10[12]; + __IO uint32_t FIFO_STATUS; /**< FIFO Status, offset: 0xB0 */ + uint8_t RESERVED_11[12]; + __IO uint32_t INT_SIG_EN; /**< , offset: 0xC0 */ + uint8_t RESERVED_12[12]; + __IO uint32_t INT_EN; /**< Interrupt Enable, offset: 0xD0 */ + uint8_t RESERVED_13[12]; + __IO uint32_t INT_STATUS; /**< , offset: 0xE0 */ + uint8_t RESERVED_14[12]; + __IO uint32_t CHA_B_CNV_RSLT; /**< Channel A and B Conversion Result, offset: 0xF0 */ + uint8_t RESERVED_15[12]; + __IO uint32_t CHC_D_CNV_RSLT; /**< Channel C and D Conversion Result, offset: 0x100 */ + uint8_t RESERVED_16[12]; + __IO uint32_t CH_SW_CNV_RSLT; /**< Channel Software Conversion Result, offset: 0x110 */ + uint8_t RESERVED_17[12]; + __IO uint32_t DMA_FIFO_DAT; /**< DMA FIFO Data, offset: 0x120 */ + uint8_t RESERVED_18[12]; + __IO uint32_t ADC_CFG; /**< ADC Configuration, offset: 0x130 */ +} ADC_Type, *ADC_MemMapPtr; +/* ---------------------------------------------------------------------------- + -- ADC - Register accessor macros + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Accessor_Macros ADC - Register accessor macros + * @{ + */ + + +/* ADC - Register accessors */ +#define ADC_CH_A_CFG1_REG(base) ((base)->CH_A_CFG1) +#define ADC_CH_A_CFG2_REG(base) ((base)->CH_A_CFG2) +#define ADC_CH_B_CFG1_REG(base) ((base)->CH_B_CFG1) +#define ADC_CH_B_CFG2_REG(base) ((base)->CH_B_CFG2) +#define ADC_CH_C_CFG1_REG(base) ((base)->CH_C_CFG1) +#define ADC_CH_C_CFG2_REG(base) ((base)->CH_C_CFG2) +#define ADC_CH_D_CFG1_REG(base) ((base)->CH_D_CFG1) +#define ADC_CH_D_CFG2_REG(base) ((base)->CH_D_CFG2) +#define ADC_CH_SW_CFG_REG(base) ((base)->CH_SW_CFG) +#define ADC_TIMER_UNIT_REG(base) ((base)->TIMER_UNIT) +#define ADC_DMA_FIFO_REG(base) ((base)->DMA_FIFO) +#define ADC_FIFO_STATUS_REG(base) ((base)->FIFO_STATUS) +#define ADC_INT_SIG_EN_REG(base) ((base)->INT_SIG_EN) +#define ADC_INT_EN_REG(base) ((base)->INT_EN) +#define ADC_INT_STATUS_REG(base) ((base)->INT_STATUS) +#define ADC_CHA_B_CNV_RSLT_REG(base) ((base)->CHA_B_CNV_RSLT) +#define ADC_CHC_D_CNV_RSLT_REG(base) ((base)->CHC_D_CNV_RSLT) +#define ADC_CH_SW_CNV_RSLT_REG(base) ((base)->CH_SW_CNV_RSLT) +#define ADC_DMA_FIFO_DAT_REG(base) ((base)->DMA_FIFO_DAT) +#define ADC_ADC_CFG_REG(base) ((base)->ADC_CFG) + +/*! + * @} + */ /* end of group ADC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- ADC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ADC_Register_Masks ADC Register Masks + * @{ + */ + +/* CH_A_CFG1 Bit Fields */ +#define ADC_CH_A_CFG1_CHA_TIMER_MASK 0xFFFFFFu +#define ADC_CH_A_CFG1_CHA_TIMER_SHIFT 0 +#define ADC_CH_A_CFG1_CHA_TIMER(x) (((uint32_t)(((uint32_t)(x))<CTRL0) +#define APBH_CTRL0_SET_REG(base) ((base)->CTRL0_SET) +#define APBH_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) +#define APBH_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) +#define APBH_CTRL1_REG(base) ((base)->CTRL1) +#define APBH_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define APBH_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define APBH_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define APBH_CTRL2_REG(base) ((base)->CTRL2) +#define APBH_CTRL2_SET_REG(base) ((base)->CTRL2_SET) +#define APBH_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) +#define APBH_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) +#define APBH_CHANNEL_CTRL_REG(base) ((base)->CHANNEL_CTRL) +#define APBH_CHANNEL_CTRL_SET_REG(base) ((base)->CHANNEL_CTRL_SET) +#define APBH_CHANNEL_CTRL_CLR_REG(base) ((base)->CHANNEL_CTRL_CLR) +#define APBH_CHANNEL_CTRL_TOG_REG(base) ((base)->CHANNEL_CTRL_TOG) +#define APBH_DEVSEL_REG(base) ((base)->DEVSEL) +#define APBH_DMA_BURST_SIZE_REG(base) ((base)->DMA_BURST_SIZE) +#define APBH_DEBUG_REG(base) ((base)->DEBUG) +#define APBH_CH_CURCMDAR_REG(base,index) ((base)->CH[index].CH_CURCMDAR) +#define APBH_CH_NXTCMDAR_REG(base,index) ((base)->CH[index].CH_NXTCMDAR) +#define APBH_CH_CMD_REG(base,index) ((base)->CH[index].CH_CMD) +#define APBH_CH_BAR_REG(base,index) ((base)->CH[index].CH_BAR) +#define APBH_CH_SEMA_REG(base,index) ((base)->CH[index].CH_SEMA) +#define APBH_CH_DEBUG1_REG(base,index) ((base)->CH[index].CH_DEBUG1) +#define APBH_CH_DEBUG2_REG(base,index) ((base)->CH[index].CH_DEBUG2) +#define APBH_VERSION_REG(base) ((base)->VERSION) + +/*! + * @} + */ /* end of group APBH_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- APBH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup APBH_Register_Masks APBH Register Masks + * @{ + */ + +/* CTRL0 Bit Fields */ +#define APBH_CTRL0_CLKGATE_CHANNEL_MASK 0xFFFFu +#define APBH_CTRL0_CLKGATE_CHANNEL_SHIFT 0 +#define APBH_CTRL0_CLKGATE_CHANNEL(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define BCH_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define BCH_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define BCH_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define BCH_STATUS0_REG(base) ((base)->STATUS0) +#define BCH_STATUS0_SET_REG(base) ((base)->STATUS0_SET) +#define BCH_STATUS0_CLR_REG(base) ((base)->STATUS0_CLR) +#define BCH_STATUS0_TOG_REG(base) ((base)->STATUS0_TOG) +#define BCH_MODE_REG(base) ((base)->MODE) +#define BCH_MODE_SET_REG(base) ((base)->MODE_SET) +#define BCH_MODE_CLR_REG(base) ((base)->MODE_CLR) +#define BCH_MODE_TOG_REG(base) ((base)->MODE_TOG) +#define BCH_ENCODEPTR_REG(base) ((base)->ENCODEPTR) +#define BCH_ENCODEPTR_SET_REG(base) ((base)->ENCODEPTR_SET) +#define BCH_ENCODEPTR_CLR_REG(base) ((base)->ENCODEPTR_CLR) +#define BCH_ENCODEPTR_TOG_REG(base) ((base)->ENCODEPTR_TOG) +#define BCH_DATAPTR_REG(base) ((base)->DATAPTR) +#define BCH_DATAPTR_SET_REG(base) ((base)->DATAPTR_SET) +#define BCH_DATAPTR_CLR_REG(base) ((base)->DATAPTR_CLR) +#define BCH_DATAPTR_TOG_REG(base) ((base)->DATAPTR_TOG) +#define BCH_METAPTR_REG(base) ((base)->METAPTR) +#define BCH_METAPTR_SET_REG(base) ((base)->METAPTR_SET) +#define BCH_METAPTR_CLR_REG(base) ((base)->METAPTR_CLR) +#define BCH_METAPTR_TOG_REG(base) ((base)->METAPTR_TOG) +#define BCH_LAYOUTSELECT_REG(base) ((base)->LAYOUTSELECT) +#define BCH_LAYOUTSELECT_SET_REG(base) ((base)->LAYOUTSELECT_SET) +#define BCH_LAYOUTSELECT_CLR_REG(base) ((base)->LAYOUTSELECT_CLR) +#define BCH_LAYOUTSELECT_TOG_REG(base) ((base)->LAYOUTSELECT_TOG) +#define BCH_FLASH0LAYOUT0_REG(base) ((base)->FLASH0LAYOUT0) +#define BCH_FLASH0LAYOUT0_SET_REG(base) ((base)->FLASH0LAYOUT0_SET) +#define BCH_FLASH0LAYOUT0_CLR_REG(base) ((base)->FLASH0LAYOUT0_CLR) +#define BCH_FLASH0LAYOUT0_TOG_REG(base) ((base)->FLASH0LAYOUT0_TOG) +#define BCH_FLASH0LAYOUT1_REG(base) ((base)->FLASH0LAYOUT1) +#define BCH_FLASH0LAYOUT1_SET_REG(base) ((base)->FLASH0LAYOUT1_SET) +#define BCH_FLASH0LAYOUT1_CLR_REG(base) ((base)->FLASH0LAYOUT1_CLR) +#define BCH_FLASH0LAYOUT1_TOG_REG(base) ((base)->FLASH0LAYOUT1_TOG) +#define BCH_FLASH1LAYOUT0_REG(base) ((base)->FLASH1LAYOUT0) +#define BCH_FLASH1LAYOUT0_SET_REG(base) ((base)->FLASH1LAYOUT0_SET) +#define BCH_FLASH1LAYOUT0_CLR_REG(base) ((base)->FLASH1LAYOUT0_CLR) +#define BCH_FLASH1LAYOUT0_TOG_REG(base) ((base)->FLASH1LAYOUT0_TOG) +#define BCH_FLASH1LAYOUT1_REG(base) ((base)->FLASH1LAYOUT1) +#define BCH_FLASH1LAYOUT1_SET_REG(base) ((base)->FLASH1LAYOUT1_SET) +#define BCH_FLASH1LAYOUT1_CLR_REG(base) ((base)->FLASH1LAYOUT1_CLR) +#define BCH_FLASH1LAYOUT1_TOG_REG(base) ((base)->FLASH1LAYOUT1_TOG) +#define BCH_FLASH2LAYOUT0_REG(base) ((base)->FLASH2LAYOUT0) +#define BCH_FLASH2LAYOUT0_SET_REG(base) ((base)->FLASH2LAYOUT0_SET) +#define BCH_FLASH2LAYOUT0_CLR_REG(base) ((base)->FLASH2LAYOUT0_CLR) +#define BCH_FLASH2LAYOUT0_TOG_REG(base) ((base)->FLASH2LAYOUT0_TOG) +#define BCH_FLASH2LAYOUT1_REG(base) ((base)->FLASH2LAYOUT1) +#define BCH_FLASH2LAYOUT1_SET_REG(base) ((base)->FLASH2LAYOUT1_SET) +#define BCH_FLASH2LAYOUT1_CLR_REG(base) ((base)->FLASH2LAYOUT1_CLR) +#define BCH_FLASH2LAYOUT1_TOG_REG(base) ((base)->FLASH2LAYOUT1_TOG) +#define BCH_FLASH3LAYOUT0_REG(base) ((base)->FLASH3LAYOUT0) +#define BCH_FLASH3LAYOUT0_SET_REG(base) ((base)->FLASH3LAYOUT0_SET) +#define BCH_FLASH3LAYOUT0_CLR_REG(base) ((base)->FLASH3LAYOUT0_CLR) +#define BCH_FLASH3LAYOUT0_TOG_REG(base) ((base)->FLASH3LAYOUT0_TOG) +#define BCH_FLASH3LAYOUT1_REG(base) ((base)->FLASH3LAYOUT1) +#define BCH_FLASH3LAYOUT1_SET_REG(base) ((base)->FLASH3LAYOUT1_SET) +#define BCH_FLASH3LAYOUT1_CLR_REG(base) ((base)->FLASH3LAYOUT1_CLR) +#define BCH_FLASH3LAYOUT1_TOG_REG(base) ((base)->FLASH3LAYOUT1_TOG) +#define BCH_DEBUG0_REG(base) ((base)->DEBUG0) +#define BCH_DEBUG0_SET_REG(base) ((base)->DEBUG0_SET) +#define BCH_DEBUG0_CLR_REG(base) ((base)->DEBUG0_CLR) +#define BCH_DEBUG0_TOG_REG(base) ((base)->DEBUG0_TOG) +#define BCH_DBGKESREAD_REG(base) ((base)->DBGKESREAD) +#define BCH_DBGKESREAD_SET_REG(base) ((base)->DBGKESREAD_SET) +#define BCH_DBGKESREAD_CLR_REG(base) ((base)->DBGKESREAD_CLR) +#define BCH_DBGKESREAD_TOG_REG(base) ((base)->DBGKESREAD_TOG) +#define BCH_DBGCSFEREAD_REG(base) ((base)->DBGCSFEREAD) +#define BCH_DBGCSFEREAD_SET_REG(base) ((base)->DBGCSFEREAD_SET) +#define BCH_DBGCSFEREAD_CLR_REG(base) ((base)->DBGCSFEREAD_CLR) +#define BCH_DBGCSFEREAD_TOG_REG(base) ((base)->DBGCSFEREAD_TOG) +#define BCH_DBGSYNDGENREAD_REG(base) ((base)->DBGSYNDGENREAD) +#define BCH_DBGSYNDGENREAD_SET_REG(base) ((base)->DBGSYNDGENREAD_SET) +#define BCH_DBGSYNDGENREAD_CLR_REG(base) ((base)->DBGSYNDGENREAD_CLR) +#define BCH_DBGSYNDGENREAD_TOG_REG(base) ((base)->DBGSYNDGENREAD_TOG) +#define BCH_DBGAHBMREAD_REG(base) ((base)->DBGAHBMREAD) +#define BCH_DBGAHBMREAD_SET_REG(base) ((base)->DBGAHBMREAD_SET) +#define BCH_DBGAHBMREAD_CLR_REG(base) ((base)->DBGAHBMREAD_CLR) +#define BCH_DBGAHBMREAD_TOG_REG(base) ((base)->DBGAHBMREAD_TOG) +#define BCH_BLOCKNAME_REG(base) ((base)->BLOCKNAME) +#define BCH_BLOCKNAME_SET_REG(base) ((base)->BLOCKNAME_SET) +#define BCH_BLOCKNAME_CLR_REG(base) ((base)->BLOCKNAME_CLR) +#define BCH_BLOCKNAME_TOG_REG(base) ((base)->BLOCKNAME_TOG) +#define BCH_VERSION_REG(base) ((base)->VERSION) +#define BCH_VERSION_SET_REG(base) ((base)->VERSION_SET) +#define BCH_VERSION_CLR_REG(base) ((base)->VERSION_CLR) +#define BCH_VERSION_TOG_REG(base) ((base)->VERSION_TOG) +#define BCH_DEBUG1_REG(base) ((base)->DEBUG1) +#define BCH_DEBUG1_SET_REG(base) ((base)->DEBUG1_SET) +#define BCH_DEBUG1_CLR_REG(base) ((base)->DEBUG1_CLR) +#define BCH_DEBUG1_TOG_REG(base) ((base)->DEBUG1_TOG) + +/*! + * @} + */ /* end of group BCH_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- BCH Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup BCH_Register_Masks BCH Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define BCH_CTRL_COMPLETE_IRQ_MASK 0x1u +#define BCH_CTRL_COMPLETE_IRQ_SHIFT 0 +#define BCH_CTRL_RSVD0_MASK 0x2u +#define BCH_CTRL_RSVD0_SHIFT 1 +#define BCH_CTRL_DEBUG_STALL_IRQ_MASK 0x4u +#define BCH_CTRL_DEBUG_STALL_IRQ_SHIFT 2 +#define BCH_CTRL_BM_ERROR_IRQ_MASK 0x8u +#define BCH_CTRL_BM_ERROR_IRQ_SHIFT 3 +#define BCH_CTRL_RSVD1_MASK 0xF0u +#define BCH_CTRL_RSVD1_SHIFT 4 +#define BCH_CTRL_RSVD1(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define CAN_CTRL1_REG(base) ((base)->CTRL1) +#define CAN_TIMER_REG(base) ((base)->TIMER) +#define CAN_RXMGMASK_REG(base) ((base)->RXMGMASK) +#define CAN_RX14MASK_REG(base) ((base)->RX14MASK) +#define CAN_RX15MASK_REG(base) ((base)->RX15MASK) +#define CAN_ECR_REG(base) ((base)->ECR) +#define CAN_ESR1_REG(base) ((base)->ESR1) +#define CAN_IMASK2_REG(base) ((base)->IMASK2) +#define CAN_IMASK1_REG(base) ((base)->IMASK1) +#define CAN_IFLAG2_REG(base) ((base)->IFLAG2) +#define CAN_IFLAG1_REG(base) ((base)->IFLAG1) +#define CAN_CTRL2_REG(base) ((base)->CTRL2) +#define CAN_ESR2_REG(base) ((base)->ESR2) +#define CAN_CRCR_REG(base) ((base)->CRCR) +#define CAN_RXFGMASK_REG(base) ((base)->RXFGMASK) +#define CAN_RXFIR_REG(base) ((base)->RXFIR) +#define CAN_CS_REG(base,index) ((base)->MB[index].CS) +#define CAN_CS_COUNT 64 +#define CAN_ID_REG(base,index) ((base)->MB[index].ID) +#define CAN_ID_COUNT 64 +#define CAN_WORD0_REG(base,index) ((base)->MB[index].WORD0) +#define CAN_WORD0_COUNT 64 +#define CAN_WORD1_REG(base,index) ((base)->MB[index].WORD1) +#define CAN_WORD1_COUNT 64 +#define CAN_RXIMR_REG(base,index) ((base)->RXIMR[index]) +#define CAN_RXIMR_COUNT 64 +#define CAN_GFWR_REG(base) ((base)->GFWR) + +/*! + * @} + */ /* end of group CAN_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- CAN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CAN_Register_Masks CAN Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define CAN_MCR_MAXMB_MASK 0x7Fu +#define CAN_MCR_MAXMB_SHIFT 0 +#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x))<GPR0) +#define CCM_GPR0_SET_REG(base) ((base)->GPR0_SET) +#define CCM_GPR0_CLR_REG(base) ((base)->GPR0_CLR) +#define CCM_GPR0_TOG_REG(base) ((base)->GPR0_TOG) +#define CCM_PLL_CTRL_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL) +#define CCM_PLL_CTRL_SET_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL_SET) +#define CCM_PLL_CTRL_CLR_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL_CLR) +#define CCM_PLL_CTRL_TOG_REG(base,index) ((base)->PLL_CTRL[index].PLL_CTRL_TOG) +#define CCM_CCGR_REG(base,index) ((base)->CCGR[index].CCGR) +#define CCM_CCGR_SET_REG(base,index) ((base)->CCGR[index].CCGR_SET) +#define CCM_CCGR_CLR_REG(base,index) ((base)->CCGR[index].CCGR_CLR) +#define CCM_CCGR_TOG_REG(base,index) ((base)->CCGR[index].CCGR_TOG) +#define CCM_TARGET_ROOT_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT) +#define CCM_TARGET_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_SET) +#define CCM_TARGET_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_CLR) +#define CCM_TARGET_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].TARGET_ROOT_TOG) +#define CCM_MISC_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC) +#define CCM_MISC_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_SET) +#define CCM_MISC_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_CLR) +#define CCM_MISC_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].MISC_ROOT_TOG) +#define CCM_POST_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST) +#define CCM_POST_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_SET) +#define CCM_POST_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_CLR) +#define CCM_POST_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].POST_ROOT_TOG) +#define CCM_PRE_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE) +#define CCM_PRE_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_SET) +#define CCM_PRE_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_CLR) +#define CCM_PRE_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].PRE_ROOT_TOG) +#define CCM_ACCESS_CTRL_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL) +#define CCM_ACCESS_CTRL_ROOT_SET_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_SET) +#define CCM_ACCESS_CTRL_ROOT_CLR_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_CLR) +#define CCM_ACCESS_CTRL_ROOT_TOG_REG(base,index) ((base)->ACCESS_CTRL_ROOT_TOG[index].ACCESS_CTRL_ROOT_TOG) + +/*! + * @} + */ /* end of group CCM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- CCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_Register_Masks CCM Register Masks + * @{ + */ + +/* GPR0 Bit Fields */ +#define CCM_GPR0_GP0_MASK 0xFFFFFFFFu +#define CCM_GPR0_GP0_SHIFT 0 +#define CCM_GPR0_GP0(x) (((uint32_t)(((uint32_t)(x))<PLL_ARM) +#define CCM_ANALOG_PLL_ARM_SET_REG(base) ((base)->PLL_ARM_SET) +#define CCM_ANALOG_PLL_ARM_CLR_REG(base) ((base)->PLL_ARM_CLR) +#define CCM_ANALOG_PLL_ARM_TOG_REG(base) ((base)->PLL_ARM_TOG) +#define CCM_ANALOG_PLL_DDR_REG(base) ((base)->PLL_DDR) +#define CCM_ANALOG_PLL_DDR_SET_REG(base) ((base)->PLL_DDR_SET) +#define CCM_ANALOG_PLL_DDR_CLR_REG(base) ((base)->PLL_DDR_CLR) +#define CCM_ANALOG_PLL_DDR_TOG_REG(base) ((base)->PLL_DDR_TOG) +#define CCM_ANALOG_PLL_DDR_SS_REG(base) ((base)->PLL_DDR_SS) +#define CCM_ANALOG_PLL_DDR_NUM_REG(base) ((base)->PLL_DDR_NUM) +#define CCM_ANALOG_PLL_DDR_DENOM_REG(base) ((base)->PLL_DDR_DENOM) +#define CCM_ANALOG_PLL_480_REG(base) ((base)->PLL_480) +#define CCM_ANALOG_PLL_480_SET_REG(base) ((base)->PLL_480_SET) +#define CCM_ANALOG_PLL_480_CLR_REG(base) ((base)->PLL_480_CLR) +#define CCM_ANALOG_PLL_480_TOG_REG(base) ((base)->PLL_480_TOG) +#define CCM_ANALOG_PFD_480A_REG(base) ((base)->PFD_480A) +#define CCM_ANALOG_PFD_480A_SET_REG(base) ((base)->PFD_480A_SET) +#define CCM_ANALOG_PFD_480A_CLR_REG(base) ((base)->PFD_480A_CLR) +#define CCM_ANALOG_PFD_480A_TOG_REG(base) ((base)->PFD_480A_TOG) +#define CCM_ANALOG_PFD_480B_REG(base) ((base)->PFD_480B) +#define CCM_ANALOG_PFD_480B_SET_REG(base) ((base)->PFD_480B_SET) +#define CCM_ANALOG_PFD_480B_CLR_REG(base) ((base)->PFD_480B_CLR) +#define CCM_ANALOG_PFD_480B_TOG_REG(base) ((base)->PFD_480B_TOG) +#define CCM_ANALOG_PLL_ENET_REG(base) ((base)->PLL_ENET) +#define CCM_ANALOG_PLL_ENET_SET_REG(base) ((base)->PLL_ENET_SET) +#define CCM_ANALOG_PLL_ENET_CLR_REG(base) ((base)->PLL_ENET_CLR) +#define CCM_ANALOG_PLL_ENET_TOG_REG(base) ((base)->PLL_ENET_TOG) +#define CCM_ANALOG_PLL_AUDIO_REG(base) ((base)->PLL_AUDIO) +#define CCM_ANALOG_PLL_AUDIO_SET_REG(base) ((base)->PLL_AUDIO_SET) +#define CCM_ANALOG_PLL_AUDIO_CLR_REG(base) ((base)->PLL_AUDIO_CLR) +#define CCM_ANALOG_PLL_AUDIO_TOG_REG(base) ((base)->PLL_AUDIO_TOG) +#define CCM_ANALOG_PLL_AUDIO_SS_REG(base) ((base)->PLL_AUDIO_SS) +#define CCM_ANALOG_PLL_AUDIO_NUM_REG(base) ((base)->PLL_AUDIO_NUM) +#define CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) ((base)->PLL_AUDIO_DENOM) +#define CCM_ANALOG_PLL_VIDEO_REG(base) ((base)->PLL_VIDEO) +#define CCM_ANALOG_PLL_VIDEO_SET_REG(base) ((base)->PLL_VIDEO_SET) +#define CCM_ANALOG_PLL_VIDEO_CLR_REG(base) ((base)->PLL_VIDEO_CLR) +#define CCM_ANALOG_PLL_VIDEO_TOG_REG(base) ((base)->PLL_VIDEO_TOG) +#define CCM_ANALOG_PLL_VIDEO_SS_REG(base) ((base)->PLL_VIDEO_SS) +#define CCM_ANALOG_PLL_VIDEO_NUM_REG(base) ((base)->PLL_VIDEO_NUM) +#define CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) ((base)->PLL_VIDEO_DENOM) +#define CCM_ANALOG_CLK_MISC0_REG(base) ((base)->CLK_MISC0) +#define CCM_ANALOG_CLK_MISC0_SET_REG(base) ((base)->CLK_MISC0_SET) +#define CCM_ANALOG_CLK_MISC0_CLR_REG(base) ((base)->CLK_MISC0_CLR) +#define CCM_ANALOG_CLK_MISC0_TOG_REG(base) ((base)->CLK_MISC0_TOG) + +/*! + * @} + */ /* end of group CCM_ANALOG_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- CCM_ANALOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks + * @{ + */ + +/* PLL_ARM Bit Fields */ +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK 0x7Fu +#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT 0 +#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x))<CSICR1) +#define CSI_CSICR2_REG(base) ((base)->CSICR2) +#define CSI_CSICR3_REG(base) ((base)->CSICR3) +#define CSI_CSISTATFIFO_REG(base) ((base)->CSISTATFIFO) +#define CSI_CSIRFIFO_REG(base) ((base)->CSIRFIFO) +#define CSI_CSIRXCNT_REG(base) ((base)->CSIRXCNT) +#define CSI_CSISR_REG(base) ((base)->CSISR) +#define CSI_CSIDMASA_STATFIFO_REG(base) ((base)->CSIDMASA_STATFIFO) +#define CSI_CSIDMATS_STATFIFO_REG(base) ((base)->CSIDMATS_STATFIFO) +#define CSI_CSIDMASA_FB1_REG(base) ((base)->CSIDMASA_FB1) +#define CSI_CSIDMASA_FB2_REG(base) ((base)->CSIDMASA_FB2) +#define CSI_CSIFBUF_PARA_REG(base) ((base)->CSIFBUF_PARA) +#define CSI_CSIIMAG_PARA_REG(base) ((base)->CSIIMAG_PARA) +#define CSI_CSICR18_REG(base) ((base)->CSICR18) + +/*! + * @} + */ /* end of group CSI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- CSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup CSI_Register_Masks CSI Register Masks + * @{ + */ + +/* CSICR1 Bit Fields */ +#define CSI_CSICR1_PIXEL_BIT_MASK 0x1u +#define CSI_CSICR1_PIXEL_BIT_SHIFT 0 +#define CSI_CSICR1_REDGE_MASK 0x2u +#define CSI_CSICR1_REDGE_SHIFT 1 +#define CSI_CSICR1_INV_PCLK_MASK 0x4u +#define CSI_CSICR1_INV_PCLK_SHIFT 2 +#define CSI_CSICR1_INV_DATA_MASK 0x8u +#define CSI_CSICR1_INV_DATA_SHIFT 3 +#define CSI_CSICR1_GCLK_MODE_MASK 0x10u +#define CSI_CSICR1_GCLK_MODE_SHIFT 4 +#define CSI_CSICR1_CLR_RXFIFO_MASK 0x20u +#define CSI_CSICR1_CLR_RXFIFO_SHIFT 5 +#define CSI_CSICR1_CLR_STATFIFO_MASK 0x40u +#define CSI_CSICR1_CLR_STATFIFO_SHIFT 6 +#define CSI_CSICR1_PACK_DIR_MASK 0x80u +#define CSI_CSICR1_PACK_DIR_SHIFT 7 +#define CSI_CSICR1_FCC_MASK 0x100u +#define CSI_CSICR1_FCC_SHIFT 8 +#define CSI_CSICR1_CCIR_EN_MASK 0x400u +#define CSI_CSICR1_CCIR_EN_SHIFT 10 +#define CSI_CSICR1_HSYNC_POL_MASK 0x800u +#define CSI_CSICR1_HSYNC_POL_SHIFT 11 +#define CSI_CSICR1_SOF_INTEN_MASK 0x10000u +#define CSI_CSICR1_SOF_INTEN_SHIFT 16 +#define CSI_CSICR1_SOF_POL_MASK 0x20000u +#define CSI_CSICR1_SOF_POL_SHIFT 17 +#define CSI_CSICR1_RXFF_INTEN_MASK 0x40000u +#define CSI_CSICR1_RXFF_INTEN_SHIFT 18 +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK 0x80000u +#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT 19 +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK 0x100000u +#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT 20 +#define CSI_CSICR1_STATFF_INTEN_MASK 0x200000u +#define CSI_CSICR1_STATFF_INTEN_SHIFT 21 +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK 0x400000u +#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT 22 +#define CSI_CSICR1_RF_OR_INTEN_MASK 0x1000000u +#define CSI_CSICR1_RF_OR_INTEN_SHIFT 24 +#define CSI_CSICR1_SF_OR_INTEN_MASK 0x2000000u +#define CSI_CSICR1_SF_OR_INTEN_SHIFT 25 +#define CSI_CSICR1_COF_INT_EN_MASK 0x4000000u +#define CSI_CSICR1_COF_INT_EN_SHIFT 26 +#define CSI_CSICR1_VIDEO_MODE_MASK 0x8000000u +#define CSI_CSICR1_VIDEO_MODE_SHIFT 27 +#define CSI_CSICR1_PrP_IF_EN_MASK 0x10000000u +#define CSI_CSICR1_PrP_IF_EN_SHIFT 28 +#define CSI_CSICR1_EOF_INT_EN_MASK 0x20000000u +#define CSI_CSICR1_EOF_INT_EN_SHIFT 29 +#define CSI_CSICR1_EXT_VSYNC_MASK 0x40000000u +#define CSI_CSICR1_EXT_VSYNC_SHIFT 30 +#define CSI_CSICR1_SWAP16_EN_MASK 0x80000000u +#define CSI_CSICR1_SWAP16_EN_SHIFT 31 +/* CSICR2 Bit Fields */ +#define CSI_CSICR2_HSC_MASK 0xFFu +#define CSI_CSICR2_HSC_SHIFT 0 +#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x))<MSTR) +#define DDRC_STAT_REG(base) ((base)->STAT) +#define DDRC_MRCTRL0_REG(base) ((base)->MRCTRL0) +#define DDRC_MRCTRL1_REG(base) ((base)->MRCTRL1) +#define DDRC_MRSTAT_REG(base) ((base)->MRSTAT) +#define DDRC_DERATEEN_REG(base) ((base)->DERATEEN) +#define DDRC_DERATEINT_REG(base) ((base)->DERATEINT) +#define DDRC_PWRCTL_REG(base) ((base)->PWRCTL) +#define DDRC_PWRTMG_REG(base) ((base)->PWRTMG) +#define DDRC_HWLPCTL_REG(base) ((base)->HWLPCTL) +#define DDRC_RFSHCTL0_REG(base) ((base)->RFSHCTL0) +#define DDRC_RFSHCTL1_REG(base) ((base)->RFSHCTL1) +#define DDRC_RFSHCTL3_REG(base) ((base)->RFSHCTL3) +#define DDRC_RFSHTMG_REG(base) ((base)->RFSHTMG) +#define DDRC_INIT0_REG(base) ((base)->INIT0) +#define DDRC_INIT1_REG(base) ((base)->INIT1) +#define DDRC_INIT2_REG(base) ((base)->INIT2) +#define DDRC_INIT3_REG(base) ((base)->INIT3) +#define DDRC_INIT4_REG(base) ((base)->INIT4) +#define DDRC_INIT5_REG(base) ((base)->INIT5) +#define DDRC_RANKCTL_REG(base) ((base)->RANKCTL) +#define DDRC_DRAMTMG0_REG(base) ((base)->DRAMTMG0) +#define DDRC_DRAMTMG1_REG(base) ((base)->DRAMTMG1) +#define DDRC_DRAMTMG2_REG(base) ((base)->DRAMTMG2) +#define DDRC_DRAMTMG3_REG(base) ((base)->DRAMTMG3) +#define DDRC_DRAMTMG4_REG(base) ((base)->DRAMTMG4) +#define DDRC_DRAMTMG5_REG(base) ((base)->DRAMTMG5) +#define DDRC_DRAMTMG6_REG(base) ((base)->DRAMTMG6) +#define DDRC_DRAMTMG7_REG(base) ((base)->DRAMTMG7) +#define DDRC_DRAMTMG8_REG(base) ((base)->DRAMTMG8) +#define DDRC_ZQCTL0_REG(base) ((base)->ZQCTL0) +#define DDRC_ZQCTL1_REG(base) ((base)->ZQCTL1) +#define DDRC_ZQCTL2_REG(base) ((base)->ZQCTL2) +#define DDRC_ZQSTAT_REG(base) ((base)->ZQSTAT) +#define DDRC_DFITMG0_REG(base) ((base)->DFITMG0) +#define DDRC_DFITMG1_REG(base) ((base)->DFITMG1) +#define DDRC_DFILPCFG0_REG(base) ((base)->DFILPCFG0) +#define DDRC_DFIUPD0_REG(base) ((base)->DFIUPD0) +#define DDRC_DFIUPD1_REG(base) ((base)->DFIUPD1) +#define DDRC_DFIUPD2_REG(base) ((base)->DFIUPD2) +#define DDRC_DFIUPD3_REG(base) ((base)->DFIUPD3) +#define DDRC_DFIMISC_REG(base) ((base)->DFIMISC) +#define DDRC_ADDRMAP0_REG(base) ((base)->ADDRMAP0) +#define DDRC_ADDRMAP1_REG(base) ((base)->ADDRMAP1) +#define DDRC_ADDRMAP2_REG(base) ((base)->ADDRMAP2) +#define DDRC_ADDRMAP3_REG(base) ((base)->ADDRMAP3) +#define DDRC_ADDRMAP4_REG(base) ((base)->ADDRMAP4) +#define DDRC_ADDRMAP5_REG(base) ((base)->ADDRMAP5) +#define DDRC_ADDRMAP6_REG(base) ((base)->ADDRMAP6) +#define DDRC_ODTCFG_REG(base) ((base)->ODTCFG) +#define DDRC_ODTMAP_REG(base) ((base)->ODTMAP) +#define DDRC_SCHED_REG(base) ((base)->SCHED) +#define DDRC_SCHED1_REG(base) ((base)->SCHED1) +#define DDRC_PERFHPR1_REG(base) ((base)->PERFHPR1) +#define DDRC_PERFLPR1_REG(base) ((base)->PERFLPR1) +#define DDRC_PERFWR1_REG(base) ((base)->PERFWR1) +#define DDRC_PERFVPR1_REG(base) ((base)->PERFVPR1) +#define DDRC_PERFVPW1_REG(base) ((base)->PERFVPW1) +#define DDRC_DBG0_REG(base) ((base)->DBG0) +#define DDRC_DBG1_REG(base) ((base)->DBG1) +#define DDRC_DBGCAM_REG(base) ((base)->DBGCAM) +#define DDRC_DBGCMD_REG(base) ((base)->DBGCMD) +#define DDRC_DBGSTAT_REG(base) ((base)->DBGSTAT) +#define DDRC_SWCTL_REG(base) ((base)->SWCTL) +#define DDRC_SWSTAT_REG(base) ((base)->SWSTAT) + +/*! + * @} + */ /* end of group DDRC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- DDRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_Register_Masks DDRC Register Masks + * @{ + */ + +/* MSTR Bit Fields */ +#define DDRC_MSTR_DDR3_MASK 0x1u +#define DDRC_MSTR_DDR3_SHIFT 0 +#define DDRC_MSTR_LPDDR2_MASK 0x4u +#define DDRC_MSTR_LPDDR2_SHIFT 2 +#define DDRC_MSTR_LPDDR3_MASK 0x8u +#define DDRC_MSTR_LPDDR3_SHIFT 3 +#define DDRC_MSTR_BURST_MODE_MASK 0x100u +#define DDRC_MSTR_BURST_MODE_SHIFT 8 +#define DDRC_MSTR_BURSTCHOP_MASK 0x200u +#define DDRC_MSTR_BURSTCHOP_SHIFT 9 +#define DDRC_MSTR_DATA_BUS_WIDTH_MASK 0x3000u +#define DDRC_MSTR_DATA_BUS_WIDTH_SHIFT 12 +#define DDRC_MSTR_DATA_BUS_WIDTH(x) (((uint32_t)(((uint32_t)(x))<PSTAT) +#define DDRC_MP_PCCFG_REG(base) ((base)->PCCFG) +#define DDRC_MP_PCFGR_0_REG(base) ((base)->PCFGR_0) +#define DDRC_MP_PCFGW_0_REG(base) ((base)->PCFGW_0) +#define DDRC_MP_PCFGIDMASKCH_0_REG(base,index) ((base)->PCFGID[index].PCFGIDMASKCH_0) +#define DDRC_MP_PCFGIDVALUECH_0_REG(base,index) ((base)->PCFGID[index].PCFGIDVALUECH_0) +#define DDRC_MP_PCTRL_0_REG(base) ((base)->PCTRL_0) +#define DDRC_MP_PCFGQOS0_0_REG(base) ((base)->PCFGQOS0_0) +#define DDRC_MP_PCFGQOS1_0_REG(base) ((base)->PCFGQOS1_0) +#define DDRC_MP_PCFGWQOS0_0_REG(base) ((base)->PCFGWQOS0_0) +#define DDRC_MP_PCFGWQOS1_0_REG(base) ((base)->PCFGWQOS1_0) +#define DDRC_MP_SARBASE_REG(base,index) ((base)->SAR[index].SARBASE) +#define DDRC_MP_SARSIZE_REG(base,index) ((base)->SAR[index].SARSIZE) + +/*! + * @} + */ /* end of group DDRC_MP_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- DDRC_MP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDRC_MP_Register_Masks DDRC_MP Register Masks + * @{ + */ + +/* PSTAT Bit Fields */ +#define DDRC_MP_PSTAT_RD_PORT_BUSY_0_MASK 0x1u +#define DDRC_MP_PSTAT_RD_PORT_BUSY_0_SHIFT 0 +/* PCCFG Bit Fields */ +#define DDRC_MP_PCCFG_GO2CRITICAL_EN_MASK 0x1u +#define DDRC_MP_PCCFG_GO2CRITICAL_EN_SHIFT 0 +#define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_MASK 0x10u +#define DDRC_MP_PCCFG_PAGEMATCH_LIMIT_SHIFT 4 +/* PCFGR_0 Bit Fields */ +#define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_MASK 0x3FFu +#define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY_SHIFT 0 +#define DDRC_MP_PCFGR_0_RD_PORT_PRIORITY(x) (((uint32_t)(((uint32_t)(x))<PHY_CON0) +#define DDR_PHY_PHY_CON1_REG(base) ((base)->PHY_CON1) +#define DDR_PHY_PHY_CON2_REG(base) ((base)->PHY_CON2) +#define DDR_PHY_PHY_CON3_REG(base) ((base)->PHY_CON3) +#define DDR_PHY_PHY_CON4_REG(base) ((base)->PHY_CON4) +#define DDR_PHY_PHY_CON5_REG(base) ((base)->PHY_CON5) +#define DDR_PHY_LP_CON0_REG(base) ((base)->LP_CON0) +#define DDR_PHY_RODT_CON0_REG(base) ((base)->RODT_CON0) +#define DDR_PHY_OFFSET_RD_CON0_REG(base) ((base)->OFFSET_RD_CON0) +#define DDR_PHY_OFFSET_WR_CON0_REG(base) ((base)->OFFSET_WR_CON0) +#define DDR_PHY_GATE_CODE_CON0_REG(base) ((base)->GATE_CODE_CON0) +#define DDR_PHY_SHIFTC_CON0_REG(base) ((base)->SHIFTC_CON0) +#define DDR_PHY_CMD_SDLL_CON0_REG(base) ((base)->CMD_SDLL_CON0) +#define DDR_PHY_LVL_CON0_REG(base) ((base)->LVL_CON0) +#define DDR_PHY_LVL_CON3_REG(base) ((base)->LVL_CON3) +#define DDR_PHY_CMD_DESKEW_CON0_REG(base) ((base)->CMD_DESKEW_CON0) +#define DDR_PHY_CMD_DESKEW_CON1_REG(base) ((base)->CMD_DESKEW_CON1) +#define DDR_PHY_CMD_DESKEW_CON2_REG(base) ((base)->CMD_DESKEW_CON2) +#define DDR_PHY_CMD_DESKEW_CON3_REG(base) ((base)->CMD_DESKEW_CON3) +#define DDR_PHY_CMD_DESKEW_CON4_REG(base) ((base)->CMD_DESKEW_CON4) +#define DDR_PHY_DRVDS_CON0_REG(base) ((base)->DRVDS_CON0) +#define DDR_PHY_MDLL_CON0_REG(base) ((base)->MDLL_CON0) +#define DDR_PHY_MDLL_CON1_REG(base) ((base)->MDLL_CON1) +#define DDR_PHY_ZQ_CON0_REG(base) ((base)->ZQ_CON0) +#define DDR_PHY_ZQ_CON1_REG(base) ((base)->ZQ_CON1) +#define DDR_PHY_ZQ_CON2_REG(base) ((base)->ZQ_CON2) +#define DDR_PHY_RD_DESKEW_CON0_REG(base) ((base)->RD_DESKEW_CON0) +#define DDR_PHY_RD_DESKEW_CON3_REG(base) ((base)->RD_DESKEW_CON3) +#define DDR_PHY_RD_DESKEW_CON6_REG(base) ((base)->RD_DESKEW_CON6) +#define DDR_PHY_RD_DESKEW_CON9_REG(base) ((base)->RD_DESKEW_CON9) +#define DDR_PHY_RD_DESKEW_CON12_REG(base) ((base)->RD_DESKEW_CON12) +#define DDR_PHY_RD_DESKEW_CON15_REG(base) ((base)->RD_DESKEW_CON15) +#define DDR_PHY_RD_DESKEW_CON18_REG(base) ((base)->RD_DESKEW_CON18) +#define DDR_PHY_RD_DESKEW_CON21_REG(base) ((base)->RD_DESKEW_CON21) +#define DDR_PHY_WR_DESKEW_CON0_REG(base) ((base)->WR_DESKEW_CON0) +#define DDR_PHY_WR_DESKEW_CON3_REG(base) ((base)->WR_DESKEW_CON3) +#define DDR_PHY_WR_DESKEW_CON6_REG(base) ((base)->WR_DESKEW_CON6) +#define DDR_PHY_WR_DESKEW_CON9_REG(base) ((base)->WR_DESKEW_CON9) +#define DDR_PHY_WR_DESKEW_CON12_REG(base) ((base)->WR_DESKEW_CON12) +#define DDR_PHY_WR_DESKEW_CON15_REG(base) ((base)->WR_DESKEW_CON15) +#define DDR_PHY_WR_DESKEW_CON18_REG(base) ((base)->WR_DESKEW_CON18) +#define DDR_PHY_WR_DESKEW_CON21_REG(base) ((base)->WR_DESKEW_CON21) +#define DDR_PHY_DM_DESKEW_CON_REG(base) ((base)->DM_DESKEW_CON) +#define DDR_PHY_RDATA0_REG(base) ((base)->RDATA0) +#define DDR_PHY_STAT0_REG(base) ((base)->STAT0) + +/*! + * @} + */ /* end of group DDR_PHY_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- DDR_PHY Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup DDR_PHY_Register_Masks DDR_PHY Register Masks + * @{ + */ + +/* PHY_CON0 Bit Fields */ +#define DDR_PHY_PHY_CON0_CTRL_FNC_FB_MASK 0x7u +#define DDR_PHY_PHY_CON0_CTRL_FNC_FB_SHIFT 0 +#define DDR_PHY_PHY_CON0_CTRL_FNC_FB(x) (((uint32_t)(((uint32_t)(x))<RXDATA) +#define ECSPI_TXDATA_REG(base) ((base)->TXDATA) +#define ECSPI_CONREG_REG(base) ((base)->CONREG) +#define ECSPI_CONFIGREG_REG(base) ((base)->CONFIGREG) +#define ECSPI_INTREG_REG(base) ((base)->INTREG) +#define ECSPI_DMAREG_REG(base) ((base)->DMAREG) +#define ECSPI_STATREG_REG(base) ((base)->STATREG) +#define ECSPI_PERIODREG_REG(base) ((base)->PERIODREG) +#define ECSPI_TESTREG_REG(base) ((base)->TESTREG) +#define ECSPI_MSGDATA_REG(base) ((base)->MSGDATA) + +/*! + * @} + */ /* end of group ECSPI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- ECSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ECSPI_Register_Masks ECSPI Register Masks + * @{ + */ + +/* RXDATA Bit Fields */ +#define ECSPI_RXDATA_ECSPI_RXDATA_MASK 0xFFFFFFFFu +#define ECSPI_RXDATA_ECSPI_RXDATA_SHIFT 0 +#define ECSPI_RXDATA_ECSPI_RXDATA(x) (((uint32_t)(((uint32_t)(x))<CS[index].CSGCR1) +#define EIM_CSGCR2_REG(base,index) ((base)->CS[index].CSGCR2) +#define EIM_CSRCR1_REG(base,index) ((base)->CS[index].CSRCR1) +#define EIM_CSRCR2_REG(base,index) ((base)->CS[index].CSRCR2) +#define EIM_CSWCR1_REG(base,index) ((base)->CS[index].CSWCR1) +#define EIM_CSWCR2_REG(base,index) ((base)->CS[index].CSWCR2) +#define EIM_WCR_REG(base) ((base)->WCR) +#define EIM_DCR_REG(base) ((base)->DCR) +#define EIM_DSR_REG(base) ((base)->DSR) +#define EIM_WIAR_REG(base) ((base)->WIAR) +#define EIM_EAR_REG(base) ((base)->EAR) + +/*! + * @} + */ /* end of group EIM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- EIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EIM_Register_Masks EIM Register Masks + * @{ + */ + +/* CSGCR1 Bit Fields */ +#define EIM_CSGCR1_CSEN_MASK 0x1u +#define EIM_CSGCR1_CSEN_SHIFT 0 +#define EIM_CSGCR1_SWR_MASK 0x2u +#define EIM_CSGCR1_SWR_SHIFT 1 +#define EIM_CSGCR1_SRD_MASK 0x4u +#define EIM_CSGCR1_SRD_SHIFT 2 +#define EIM_CSGCR1_MUM_MASK 0x8u +#define EIM_CSGCR1_MUM_SHIFT 3 +#define EIM_CSGCR1_WFL_MASK 0x10u +#define EIM_CSGCR1_WFL_SHIFT 4 +#define EIM_CSGCR1_RFL_MASK 0x20u +#define EIM_CSGCR1_RFL_SHIFT 5 +#define EIM_CSGCR1_CRE_MASK 0x40u +#define EIM_CSGCR1_CRE_SHIFT 6 +#define EIM_CSGCR1_CREP_MASK 0x80u +#define EIM_CSGCR1_CREP_SHIFT 7 +#define EIM_CSGCR1_BL_MASK 0x700u +#define EIM_CSGCR1_BL_SHIFT 8 +#define EIM_CSGCR1_BL(x) (((uint32_t)(((uint32_t)(x))<EIR) +#define ENET_EIMR_REG(base) ((base)->EIMR) +#define ENET_RDAR_REG(base) ((base)->RDAR) +#define ENET_TDAR_REG(base) ((base)->TDAR) +#define ENET_ECR_REG(base) ((base)->ECR) +#define ENET_MMFR_REG(base) ((base)->MMFR) +#define ENET_MSCR_REG(base) ((base)->MSCR) +#define ENET_MIBC_REG(base) ((base)->MIBC) +#define ENET_RCR_REG(base) ((base)->RCR) +#define ENET_TCR_REG(base) ((base)->TCR) +#define ENET_PALR_REG(base) ((base)->PALR) +#define ENET_PAUR_REG(base) ((base)->PAUR) +#define ENET_OPD_REG(base) ((base)->OPD) +#define ENET_TXIC_REG(base,index) ((base)->TXIC[index]) +#define ENET_RXIC_REG(base,index) ((base)->RXIC[index]) +#define ENET_IAUR_REG(base) ((base)->IAUR) +#define ENET_IALR_REG(base) ((base)->IALR) +#define ENET_GAUR_REG(base) ((base)->GAUR) +#define ENET_GALR_REG(base) ((base)->GALR) +#define ENET_TFWR_REG(base) ((base)->TFWR) +#define ENET_RDSR1_REG(base) ((base)->RDSR1) +#define ENET_TDSR1_REG(base) ((base)->TDSR1) +#define ENET_MRBR1_REG(base) ((base)->MRBR1) +#define ENET_RDSR2_REG(base) ((base)->RDSR2) +#define ENET_TDSR2_REG(base) ((base)->TDSR2) +#define ENET_MRBR2_REG(base) ((base)->MRBR2) +#define ENET_RDSR_REG(base) ((base)->RDSR) +#define ENET_TDSR_REG(base) ((base)->TDSR) +#define ENET_MRBR_REG(base) ((base)->MRBR) +#define ENET_RSFL_REG(base) ((base)->RSFL) +#define ENET_RSEM_REG(base) ((base)->RSEM) +#define ENET_RAEM_REG(base) ((base)->RAEM) +#define ENET_RAFL_REG(base) ((base)->RAFL) +#define ENET_TSEM_REG(base) ((base)->TSEM) +#define ENET_TAEM_REG(base) ((base)->TAEM) +#define ENET_TAFL_REG(base) ((base)->TAFL) +#define ENET_TIPG_REG(base) ((base)->TIPG) +#define ENET_FTRL_REG(base) ((base)->FTRL) +#define ENET_TACC_REG(base) ((base)->TACC) +#define ENET_RACC_REG(base) ((base)->RACC) +#define ENET_RCMR_REG(base,index) ((base)->RCMR[index]) +#define ENET_DMACFG_REG(base,index) ((base)->DMACFG[index]) +#define ENET_RDAR1_REG(base) ((base)->RDAR1) +#define ENET_TDAR1_REG(base) ((base)->TDAR1) +#define ENET_RDAR2_REG(base) ((base)->RDAR2) +#define ENET_TDAR2_REG(base) ((base)->TDAR2) +#define ENET_QOS_REG(base) ((base)->QOS) +#define ENET_RMON_T_DROP_REG(base) ((base)->RMON_T_DROP) +#define ENET_RMON_T_PACKETS_REG(base) ((base)->RMON_T_PACKETS) +#define ENET_RMON_T_BC_PKT_REG(base) ((base)->RMON_T_BC_PKT) +#define ENET_RMON_T_MC_PKT_REG(base) ((base)->RMON_T_MC_PKT) +#define ENET_RMON_T_CRC_ALIGN_REG(base) ((base)->RMON_T_CRC_ALIGN) +#define ENET_RMON_T_UNDERSIZE_REG(base) ((base)->RMON_T_UNDERSIZE) +#define ENET_RMON_T_OVERSIZE_REG(base) ((base)->RMON_T_OVERSIZE) +#define ENET_RMON_T_FRAG_REG(base) ((base)->RMON_T_FRAG) +#define ENET_RMON_T_JAB_REG(base) ((base)->RMON_T_JAB) +#define ENET_RMON_T_COL_REG(base) ((base)->RMON_T_COL) +#define ENET_RMON_T_P64_REG(base) ((base)->RMON_T_P64) +#define ENET_RMON_T_P65TO127_REG(base) ((base)->RMON_T_P65TO127) +#define ENET_RMON_T_P128TO255_REG(base) ((base)->RMON_T_P128TO255) +#define ENET_RMON_T_P256TO511_REG(base) ((base)->RMON_T_P256TO511) +#define ENET_RMON_T_P512TO1023_REG(base) ((base)->RMON_T_P512TO1023) +#define ENET_RMON_T_P1024TO2047_REG(base) ((base)->RMON_T_P1024TO2047) +#define ENET_RMON_T_P_GTE2048_REG(base) ((base)->RMON_T_P_GTE2048) +#define ENET_RMON_T_OCTETS_REG(base) ((base)->RMON_T_OCTETS) +#define ENET_IEEE_T_DROP_REG(base) ((base)->IEEE_T_DROP) +#define ENET_IEEE_T_FRAME_OK_REG(base) ((base)->IEEE_T_FRAME_OK) +#define ENET_IEEE_T_1COL_REG(base) ((base)->IEEE_T_1COL) +#define ENET_IEEE_T_MCOL_REG(base) ((base)->IEEE_T_MCOL) +#define ENET_IEEE_T_DEF_REG(base) ((base)->IEEE_T_DEF) +#define ENET_IEEE_T_LCOL_REG(base) ((base)->IEEE_T_LCOL) +#define ENET_IEEE_T_EXCOL_REG(base) ((base)->IEEE_T_EXCOL) +#define ENET_IEEE_T_MACERR_REG(base) ((base)->IEEE_T_MACERR) +#define ENET_IEEE_T_CSERR_REG(base) ((base)->IEEE_T_CSERR) +#define ENET_IEEE_T_SQE_REG(base) ((base)->IEEE_T_SQE) +#define ENET_IEEE_T_FDXFC_REG(base) ((base)->IEEE_T_FDXFC) +#define ENET_IEEE_T_OCTETS_OK_REG(base) ((base)->IEEE_T_OCTETS_OK) +#define ENET_RMON_R_PACKETS_REG(base) ((base)->RMON_R_PACKETS) +#define ENET_RMON_R_BC_PKT_REG(base) ((base)->RMON_R_BC_PKT) +#define ENET_RMON_R_MC_PKT_REG(base) ((base)->RMON_R_MC_PKT) +#define ENET_RMON_R_CRC_ALIGN_REG(base) ((base)->RMON_R_CRC_ALIGN) +#define ENET_RMON_R_UNDERSIZE_REG(base) ((base)->RMON_R_UNDERSIZE) +#define ENET_RMON_R_OVERSIZE_REG(base) ((base)->RMON_R_OVERSIZE) +#define ENET_RMON_R_FRAG_REG(base) ((base)->RMON_R_FRAG) +#define ENET_RMON_R_JAB_REG(base) ((base)->RMON_R_JAB) +#define ENET_RMON_R_RESVD_0_REG(base) ((base)->RMON_R_RESVD_0) +#define ENET_RMON_R_P64_REG(base) ((base)->RMON_R_P64) +#define ENET_RMON_R_P65TO127_REG(base) ((base)->RMON_R_P65TO127) +#define ENET_RMON_R_P128TO255_REG(base) ((base)->RMON_R_P128TO255) +#define ENET_RMON_R_P256TO511_REG(base) ((base)->RMON_R_P256TO511) +#define ENET_RMON_R_P512TO1023_REG(base) ((base)->RMON_R_P512TO1023) +#define ENET_RMON_R_P1024TO2047_REG(base) ((base)->RMON_R_P1024TO2047) +#define ENET_RMON_R_P_GTE2048_REG(base) ((base)->RMON_R_P_GTE2048) +#define ENET_RMON_R_OCTETS_REG(base) ((base)->RMON_R_OCTETS) +#define ENET_IEEE_R_DROP_REG(base) ((base)->IEEE_R_DROP) +#define ENET_IEEE_R_FRAME_OK_REG(base) ((base)->IEEE_R_FRAME_OK) +#define ENET_IEEE_R_CRC_REG(base) ((base)->IEEE_R_CRC) +#define ENET_IEEE_R_ALIGN_REG(base) ((base)->IEEE_R_ALIGN) +#define ENET_IEEE_R_MACERR_REG(base) ((base)->IEEE_R_MACERR) +#define ENET_IEEE_R_FDXFC_REG(base) ((base)->IEEE_R_FDXFC) +#define ENET_IEEE_R_OCTETS_OK_REG(base) ((base)->IEEE_R_OCTETS_OK) +#define ENET_ATCR_REG(base) ((base)->ATCR) +#define ENET_ATVR_REG(base) ((base)->ATVR) +#define ENET_ATOFF_REG(base) ((base)->ATOFF) +#define ENET_ATPER_REG(base) ((base)->ATPER) +#define ENET_ATCOR_REG(base) ((base)->ATCOR) +#define ENET_ATINC_REG(base) ((base)->ATINC) +#define ENET_ATSTMP_REG(base) ((base)->ATSTMP) +#define ENET_TGSR_REG(base) ((base)->TGSR) +#define ENET_TCSR_REG(base,index) ((base)->TC[index].TCSR) +#define ENET_TCCR_REG(base,index) ((base)->TC[index].TCCR) + +/*! + * @} + */ /* end of group ENET_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- ENET Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ENET_Register_Masks ENET Register Masks + * @{ + */ + +/* EIR Bit Fields */ +#define ENET_EIR_RXB1_MASK 0x1u +#define ENET_EIR_RXB1_SHIFT 0 +#define ENET_EIR_RXF1_MASK 0x2u +#define ENET_EIR_RXF1_SHIFT 1 +#define ENET_EIR_TXB1_MASK 0x4u +#define ENET_EIR_TXB1_SHIFT 2 +#define ENET_EIR_TXF1_MASK 0x8u +#define ENET_EIR_TXF1_SHIFT 3 +#define ENET_EIR_RXB2_MASK 0x10u +#define ENET_EIR_RXB2_SHIFT 4 +#define ENET_EIR_RXF2_MASK 0x20u +#define ENET_EIR_RXF2_SHIFT 5 +#define ENET_EIR_TXB2_MASK 0x40u +#define ENET_EIR_TXB2_SHIFT 6 +#define ENET_EIR_TXF2_MASK 0x80u +#define ENET_EIR_TXF2_SHIFT 7 +#define ENET_EIR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIR_RXFLUSH_0_SHIFT 12 +#define ENET_EIR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIR_RXFLUSH_1_SHIFT 13 +#define ENET_EIR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIR_RXFLUSH_2_SHIFT 14 +#define ENET_EIR_TS_TIMER_MASK 0x8000u +#define ENET_EIR_TS_TIMER_SHIFT 15 +#define ENET_EIR_TS_AVAIL_MASK 0x10000u +#define ENET_EIR_TS_AVAIL_SHIFT 16 +#define ENET_EIR_WAKEUP_MASK 0x20000u +#define ENET_EIR_WAKEUP_SHIFT 17 +#define ENET_EIR_PLR_MASK 0x40000u +#define ENET_EIR_PLR_SHIFT 18 +#define ENET_EIR_UN_MASK 0x80000u +#define ENET_EIR_UN_SHIFT 19 +#define ENET_EIR_RL_MASK 0x100000u +#define ENET_EIR_RL_SHIFT 20 +#define ENET_EIR_LC_MASK 0x200000u +#define ENET_EIR_LC_SHIFT 21 +#define ENET_EIR_EBERR_MASK 0x400000u +#define ENET_EIR_EBERR_SHIFT 22 +#define ENET_EIR_MII_MASK 0x800000u +#define ENET_EIR_MII_SHIFT 23 +#define ENET_EIR_RXB_MASK 0x1000000u +#define ENET_EIR_RXB_SHIFT 24 +#define ENET_EIR_RXF_MASK 0x2000000u +#define ENET_EIR_RXF_SHIFT 25 +#define ENET_EIR_TXB_MASK 0x4000000u +#define ENET_EIR_TXB_SHIFT 26 +#define ENET_EIR_TXF_MASK 0x8000000u +#define ENET_EIR_TXF_SHIFT 27 +#define ENET_EIR_GRA_MASK 0x10000000u +#define ENET_EIR_GRA_SHIFT 28 +#define ENET_EIR_BABT_MASK 0x20000000u +#define ENET_EIR_BABT_SHIFT 29 +#define ENET_EIR_BABR_MASK 0x40000000u +#define ENET_EIR_BABR_SHIFT 30 +/* EIMR Bit Fields */ +#define ENET_EIMR_RXB1_MASK 0x1u +#define ENET_EIMR_RXB1_SHIFT 0 +#define ENET_EIMR_RXF1_MASK 0x2u +#define ENET_EIMR_RXF1_SHIFT 1 +#define ENET_EIMR_TXB1_MASK 0x4u +#define ENET_EIMR_TXB1_SHIFT 2 +#define ENET_EIMR_TXF1_MASK 0x8u +#define ENET_EIMR_TXF1_SHIFT 3 +#define ENET_EIMR_RXB2_MASK 0x10u +#define ENET_EIMR_RXB2_SHIFT 4 +#define ENET_EIMR_RXF2_MASK 0x20u +#define ENET_EIMR_RXF2_SHIFT 5 +#define ENET_EIMR_TXB2_MASK 0x40u +#define ENET_EIMR_TXB2_SHIFT 6 +#define ENET_EIMR_TXF2_MASK 0x80u +#define ENET_EIMR_TXF2_SHIFT 7 +#define ENET_EIMR_RXFLUSH_0_MASK 0x1000u +#define ENET_EIMR_RXFLUSH_0_SHIFT 12 +#define ENET_EIMR_RXFLUSH_1_MASK 0x2000u +#define ENET_EIMR_RXFLUSH_1_SHIFT 13 +#define ENET_EIMR_RXFLUSH_2_MASK 0x4000u +#define ENET_EIMR_RXFLUSH_2_SHIFT 14 +#define ENET_EIMR_TS_TIMER_MASK 0x8000u +#define ENET_EIMR_TS_TIMER_SHIFT 15 +#define ENET_EIMR_TS_AVAIL_MASK 0x10000u +#define ENET_EIMR_TS_AVAIL_SHIFT 16 +#define ENET_EIMR_WAKEUP_MASK 0x20000u +#define ENET_EIMR_WAKEUP_SHIFT 17 +#define ENET_EIMR_PLR_MASK 0x40000u +#define ENET_EIMR_PLR_SHIFT 18 +#define ENET_EIMR_UN_MASK 0x80000u +#define ENET_EIMR_UN_SHIFT 19 +#define ENET_EIMR_RL_MASK 0x100000u +#define ENET_EIMR_RL_SHIFT 20 +#define ENET_EIMR_LC_MASK 0x200000u +#define ENET_EIMR_LC_SHIFT 21 +#define ENET_EIMR_EBERR_MASK 0x400000u +#define ENET_EIMR_EBERR_SHIFT 22 +#define ENET_EIMR_MII_MASK 0x800000u +#define ENET_EIMR_MII_SHIFT 23 +#define ENET_EIMR_RXB_MASK 0x1000000u +#define ENET_EIMR_RXB_SHIFT 24 +#define ENET_EIMR_RXF_MASK 0x2000000u +#define ENET_EIMR_RXF_SHIFT 25 +#define ENET_EIMR_TXB_MASK 0x4000000u +#define ENET_EIMR_TXB_SHIFT 26 +#define ENET_EIMR_TXF_MASK 0x8000000u +#define ENET_EIMR_TXF_SHIFT 27 +#define ENET_EIMR_GRA_MASK 0x10000000u +#define ENET_EIMR_GRA_SHIFT 28 +#define ENET_EIMR_BABT_MASK 0x20000000u +#define ENET_EIMR_BABT_SHIFT 29 +#define ENET_EIMR_BABR_MASK 0x40000000u +#define ENET_EIMR_BABR_SHIFT 30 +/* RDAR Bit Fields */ +#define ENET_RDAR_RDAR_MASK 0x1000000u +#define ENET_RDAR_RDAR_SHIFT 24 +/* TDAR Bit Fields */ +#define ENET_TDAR_TDAR_MASK 0x1000000u +#define ENET_TDAR_TDAR_SHIFT 24 +/* ECR Bit Fields */ +#define ENET_ECR_RESET_MASK 0x1u +#define ENET_ECR_RESET_SHIFT 0 +#define ENET_ECR_ETHEREN_MASK 0x2u +#define ENET_ECR_ETHEREN_SHIFT 1 +#define ENET_ECR_MAGICEN_MASK 0x4u +#define ENET_ECR_MAGICEN_SHIFT 2 +#define ENET_ECR_SLEEP_MASK 0x8u +#define ENET_ECR_SLEEP_SHIFT 3 +#define ENET_ECR_EN1588_MASK 0x10u +#define ENET_ECR_EN1588_SHIFT 4 +#define ENET_ECR_SPEED_MASK 0x20u +#define ENET_ECR_SPEED_SHIFT 5 +#define ENET_ECR_DBGEN_MASK 0x40u +#define ENET_ECR_DBGEN_SHIFT 6 +#define ENET_ECR_DBSWP_MASK 0x100u +#define ENET_ECR_DBSWP_SHIFT 8 +#define ENET_ECR_SVLANEN_MASK 0x200u +#define ENET_ECR_SVLANEN_SHIFT 9 +#define ENET_ECR_VLANUSE2ND_MASK 0x400u +#define ENET_ECR_VLANUSE2ND_SHIFT 10 +#define ENET_ECR_SVLANDBL_MASK 0x800u +#define ENET_ECR_SVLANDBL_SHIFT 11 +/* MMFR Bit Fields */ +#define ENET_MMFR_DATA_MASK 0xFFFFu +#define ENET_MMFR_DATA_SHIFT 0 +#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define EPDC_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define EPDC_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define EPDC_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define EPDC_WB_ADDR_TCE_REG(base) ((base)->WB_ADDR_TCE) +#define EPDC_WVADDR_REG(base) ((base)->WVADDR) +#define EPDC_WB_ADDR_REG(base) ((base)->WB_ADDR) +#define EPDC_RES_REG(base) ((base)->RES) +#define EPDC_FORMAT_REG(base) ((base)->FORMAT) +#define EPDC_FORMAT_SET_REG(base) ((base)->FORMAT_SET) +#define EPDC_FORMAT_CLR_REG(base) ((base)->FORMAT_CLR) +#define EPDC_FORMAT_TOG_REG(base) ((base)->FORMAT_TOG) +#define EPDC_WB_FIELD0_REG(base) ((base)->WB_FIELD0) +#define EPDC_WB_FIELD1_REG(base) ((base)->WB_FIELD1) +#define EPDC_WB_FIELD2_REG(base) ((base)->WB_FIELD2) +#define EPDC_WB_FIELD3_REG(base) ((base)->WB_FIELD3) +#define EPDC_FIFOCTRL_REG(base) ((base)->FIFOCTRL) +#define EPDC_FIFOCTRL_SET_REG(base) ((base)->FIFOCTRL_SET) +#define EPDC_FIFOCTRL_CLR_REG(base) ((base)->FIFOCTRL_CLR) +#define EPDC_FIFOCTRL_TOG_REG(base) ((base)->FIFOCTRL_TOG) +#define EPDC_UPD_ADDR_REG(base) ((base)->UPD_ADDR) +#define EPDC_UPD_STRIDE_REG(base) ((base)->UPD_STRIDE) +#define EPDC_UPD_CORD_REG(base) ((base)->UPD_CORD) +#define EPDC_UPD_SIZE_REG(base) ((base)->UPD_SIZE) +#define EPDC_UPD_CTRL_REG(base) ((base)->UPD_CTRL) +#define EPDC_UPD_CTRL_SET_REG(base) ((base)->UPD_CTRL_SET) +#define EPDC_UPD_CTRL_CLR_REG(base) ((base)->UPD_CTRL_CLR) +#define EPDC_UPD_CTRL_TOG_REG(base) ((base)->UPD_CTRL_TOG) +#define EPDC_UPD_FIXED_REG(base) ((base)->UPD_FIXED) +#define EPDC_UPD_FIXED_SET_REG(base) ((base)->UPD_FIXED_SET) +#define EPDC_UPD_FIXED_CLR_REG(base) ((base)->UPD_FIXED_CLR) +#define EPDC_UPD_FIXED_TOG_REG(base) ((base)->UPD_FIXED_TOG) +#define EPDC_TEMP_REG(base) ((base)->TEMP) +#define EPDC_AUTOWV_LUT_REG(base) ((base)->AUTOWV_LUT) +#define EPDC_LUT_STANDBY1_REG(base) ((base)->LUT_STANDBY1) +#define EPDC_LUT_STANDBY1_SET_REG(base) ((base)->LUT_STANDBY1_SET) +#define EPDC_LUT_STANDBY1_CLR_REG(base) ((base)->LUT_STANDBY1_CLR) +#define EPDC_LUT_STANDBY1_TOG_REG(base) ((base)->LUT_STANDBY1_TOG) +#define EPDC_LUT_STANDBY2_REG(base) ((base)->LUT_STANDBY2) +#define EPDC_LUT_STANDBY2_SET_REG(base) ((base)->LUT_STANDBY2_SET) +#define EPDC_LUT_STANDBY2_CLR_REG(base) ((base)->LUT_STANDBY2_CLR) +#define EPDC_LUT_STANDBY2_TOG_REG(base) ((base)->LUT_STANDBY2_TOG) +#define EPDC_TCE_CTRL_REG(base) ((base)->TCE_CTRL) +#define EPDC_TCE_CTRL_SET_REG(base) ((base)->TCE_CTRL_SET) +#define EPDC_TCE_CTRL_CLR_REG(base) ((base)->TCE_CTRL_CLR) +#define EPDC_TCE_CTRL_TOG_REG(base) ((base)->TCE_CTRL_TOG) +#define EPDC_TCE_SDCFG_REG(base) ((base)->TCE_SDCFG) +#define EPDC_TCE_SDCFG_SET_REG(base) ((base)->TCE_SDCFG_SET) +#define EPDC_TCE_SDCFG_CLR_REG(base) ((base)->TCE_SDCFG_CLR) +#define EPDC_TCE_SDCFG_TOG_REG(base) ((base)->TCE_SDCFG_TOG) +#define EPDC_TCE_GDCFG_REG(base) ((base)->TCE_GDCFG) +#define EPDC_TCE_GDCFG_SET_REG(base) ((base)->TCE_GDCFG_SET) +#define EPDC_TCE_GDCFG_CLR_REG(base) ((base)->TCE_GDCFG_CLR) +#define EPDC_TCE_GDCFG_TOG_REG(base) ((base)->TCE_GDCFG_TOG) +#define EPDC_TCE_HSCAN1_REG(base) ((base)->TCE_HSCAN1) +#define EPDC_TCE_HSCAN1_SET_REG(base) ((base)->TCE_HSCAN1_SET) +#define EPDC_TCE_HSCAN1_CLR_REG(base) ((base)->TCE_HSCAN1_CLR) +#define EPDC_TCE_HSCAN1_TOG_REG(base) ((base)->TCE_HSCAN1_TOG) +#define EPDC_TCE_HSCAN2_REG(base) ((base)->TCE_HSCAN2) +#define EPDC_TCE_HSCAN2_SET_REG(base) ((base)->TCE_HSCAN2_SET) +#define EPDC_TCE_HSCAN2_CLR_REG(base) ((base)->TCE_HSCAN2_CLR) +#define EPDC_TCE_HSCAN2_TOG_REG(base) ((base)->TCE_HSCAN2_TOG) +#define EPDC_TCE_VSCAN_REG(base) ((base)->TCE_VSCAN) +#define EPDC_TCE_VSCAN_SET_REG(base) ((base)->TCE_VSCAN_SET) +#define EPDC_TCE_VSCAN_CLR_REG(base) ((base)->TCE_VSCAN_CLR) +#define EPDC_TCE_VSCAN_TOG_REG(base) ((base)->TCE_VSCAN_TOG) +#define EPDC_TCE_OE_REG(base) ((base)->TCE_OE) +#define EPDC_TCE_OE_SET_REG(base) ((base)->TCE_OE_SET) +#define EPDC_TCE_OE_CLR_REG(base) ((base)->TCE_OE_CLR) +#define EPDC_TCE_OE_TOG_REG(base) ((base)->TCE_OE_TOG) +#define EPDC_TCE_POLARITY_REG(base) ((base)->TCE_POLARITY) +#define EPDC_TCE_POLARITY_SET_REG(base) ((base)->TCE_POLARITY_SET) +#define EPDC_TCE_POLARITY_CLR_REG(base) ((base)->TCE_POLARITY_CLR) +#define EPDC_TCE_POLARITY_TOG_REG(base) ((base)->TCE_POLARITY_TOG) +#define EPDC_TCE_TIMING1_REG(base) ((base)->TCE_TIMING1) +#define EPDC_TCE_TIMING1_SET_REG(base) ((base)->TCE_TIMING1_SET) +#define EPDC_TCE_TIMING1_CLR_REG(base) ((base)->TCE_TIMING1_CLR) +#define EPDC_TCE_TIMING1_TOG_REG(base) ((base)->TCE_TIMING1_TOG) +#define EPDC_TCE_TIMING2_REG(base) ((base)->TCE_TIMING2) +#define EPDC_TCE_TIMING2_SET_REG(base) ((base)->TCE_TIMING2_SET) +#define EPDC_TCE_TIMING2_CLR_REG(base) ((base)->TCE_TIMING2_CLR) +#define EPDC_TCE_TIMING2_TOG_REG(base) ((base)->TCE_TIMING2_TOG) +#define EPDC_TCE_TIMING3_REG(base) ((base)->TCE_TIMING3) +#define EPDC_TCE_TIMING3_SET_REG(base) ((base)->TCE_TIMING3_SET) +#define EPDC_TCE_TIMING3_CLR_REG(base) ((base)->TCE_TIMING3_CLR) +#define EPDC_TCE_TIMING3_TOG_REG(base) ((base)->TCE_TIMING3_TOG) +#define EPDC_PIGEON_CTRL0_REG(base) ((base)->PIGEON_CTRL0) +#define EPDC_PIGEON_CTRL0_SET_REG(base) ((base)->PIGEON_CTRL0_SET) +#define EPDC_PIGEON_CTRL0_CLR_REG(base) ((base)->PIGEON_CTRL0_CLR) +#define EPDC_PIGEON_CTRL0_TOG_REG(base) ((base)->PIGEON_CTRL0_TOG) +#define EPDC_PIGEON_CTRL1_REG(base) ((base)->PIGEON_CTRL1) +#define EPDC_PIGEON_CTRL1_SET_REG(base) ((base)->PIGEON_CTRL1_SET) +#define EPDC_PIGEON_CTRL1_CLR_REG(base) ((base)->PIGEON_CTRL1_CLR) +#define EPDC_PIGEON_CTRL1_TOG_REG(base) ((base)->PIGEON_CTRL1_TOG) +#define EPDC_IRQ_MASK1_REG(base) ((base)->IRQ_MASK1) +#define EPDC_IRQ_MASK1_SET_REG(base) ((base)->IRQ_MASK1_SET) +#define EPDC_IRQ_MASK1_CLR_REG(base) ((base)->IRQ_MASK1_CLR) +#define EPDC_IRQ_MASK1_TOG_REG(base) ((base)->IRQ_MASK1_TOG) +#define EPDC_IRQ_MASK2_REG(base) ((base)->IRQ_MASK2) +#define EPDC_IRQ_MASK2_SET_REG(base) ((base)->IRQ_MASK2_SET) +#define EPDC_IRQ_MASK2_CLR_REG(base) ((base)->IRQ_MASK2_CLR) +#define EPDC_IRQ_MASK2_TOG_REG(base) ((base)->IRQ_MASK2_TOG) +#define EPDC_IRQ1_REG(base) ((base)->IRQ1) +#define EPDC_IRQ1_SET_REG(base) ((base)->IRQ1_SET) +#define EPDC_IRQ1_CLR_REG(base) ((base)->IRQ1_CLR) +#define EPDC_IRQ1_TOG_REG(base) ((base)->IRQ1_TOG) +#define EPDC_IRQ2_REG(base) ((base)->IRQ2) +#define EPDC_IRQ2_SET_REG(base) ((base)->IRQ2_SET) +#define EPDC_IRQ2_CLR_REG(base) ((base)->IRQ2_CLR) +#define EPDC_IRQ2_TOG_REG(base) ((base)->IRQ2_TOG) +#define EPDC_IRQ_MASK_REG(base) ((base)->IRQ_MASK) +#define EPDC_IRQ_MASK_SET_REG(base) ((base)->IRQ_MASK_SET) +#define EPDC_IRQ_MASK_CLR_REG(base) ((base)->IRQ_MASK_CLR) +#define EPDC_IRQ_MASK_TOG_REG(base) ((base)->IRQ_MASK_TOG) +#define EPDC_IRQ_REG(base) ((base)->IRQ) +#define EPDC_IRQ_SET_REG(base) ((base)->IRQ_SET) +#define EPDC_IRQ_CLR_REG(base) ((base)->IRQ_CLR) +#define EPDC_IRQ_TOG_REG(base) ((base)->IRQ_TOG) +#define EPDC_STATUS_LUTS1_REG(base) ((base)->STATUS_LUTS1) +#define EPDC_STATUS_LUTS1_SET_REG(base) ((base)->STATUS_LUTS1_SET) +#define EPDC_STATUS_LUTS1_CLR_REG(base) ((base)->STATUS_LUTS1_CLR) +#define EPDC_STATUS_LUTS1_TOG_REG(base) ((base)->STATUS_LUTS1_TOG) +#define EPDC_STATUS_LUTS2_REG(base) ((base)->STATUS_LUTS2) +#define EPDC_STATUS_LUTS2_SET_REG(base) ((base)->STATUS_LUTS2_SET) +#define EPDC_STATUS_LUTS2_CLR_REG(base) ((base)->STATUS_LUTS2_CLR) +#define EPDC_STATUS_LUTS2_TOG_REG(base) ((base)->STATUS_LUTS2_TOG) +#define EPDC_STATUS_NEXTLUT_REG(base) ((base)->STATUS_NEXTLUT) +#define EPDC_STATUS_COL1_REG(base) ((base)->STATUS_COL1) +#define EPDC_STATUS_COL1_SET_REG(base) ((base)->STATUS_COL1_SET) +#define EPDC_STATUS_COL1_CLR_REG(base) ((base)->STATUS_COL1_CLR) +#define EPDC_STATUS_COL1_TOG_REG(base) ((base)->STATUS_COL1_TOG) +#define EPDC_STATUS_COL2_REG(base) ((base)->STATUS_COL2) +#define EPDC_STATUS_COL2_SET_REG(base) ((base)->STATUS_COL2_SET) +#define EPDC_STATUS_COL2_CLR_REG(base) ((base)->STATUS_COL2_CLR) +#define EPDC_STATUS_COL2_TOG_REG(base) ((base)->STATUS_COL2_TOG) +#define EPDC_STATUS_REG(base) ((base)->STATUS) +#define EPDC_STATUS_SET_REG(base) ((base)->STATUS_SET) +#define EPDC_STATUS_CLR_REG(base) ((base)->STATUS_CLR) +#define EPDC_STATUS_TOG_REG(base) ((base)->STATUS_TOG) +#define EPDC_UPD_COL_CORD_REG(base) ((base)->UPD_COL_CORD) +#define EPDC_UPD_COL_SIZE_REG(base) ((base)->UPD_COL_SIZE) +#define EPDC_HIST1_PARAM_REG(base) ((base)->HIST1_PARAM) +#define EPDC_HIST2_PARAM_REG(base) ((base)->HIST2_PARAM) +#define EPDC_HIST4_PARAM_REG(base) ((base)->HIST4_PARAM) +#define EPDC_HIST8_PARAM0_REG(base) ((base)->HIST8_PARAM0) +#define EPDC_HIST8_PARAM1_REG(base) ((base)->HIST8_PARAM1) +#define EPDC_HIST16_PARAM0_REG(base) ((base)->HIST16_PARAM0) +#define EPDC_HIST16_PARAM1_REG(base) ((base)->HIST16_PARAM1) +#define EPDC_HIST16_PARAM2_REG(base) ((base)->HIST16_PARAM2) +#define EPDC_HIST16_PARAM3_REG(base) ((base)->HIST16_PARAM3) +#define EPDC_GPIO_REG(base) ((base)->GPIO) +#define EPDC_GPIO_SET_REG(base) ((base)->GPIO_SET) +#define EPDC_GPIO_CLR_REG(base) ((base)->GPIO_CLR) +#define EPDC_GPIO_TOG_REG(base) ((base)->GPIO_TOG) +#define EPDC_VERSION_REG(base) ((base)->VERSION) +#define EPDC_PIGEON_0_0_REG(base) ((base)->PIGEON_0_0) +#define EPDC_PIGEON_0_1_REG(base) ((base)->PIGEON_0_1) +#define EPDC_PIGEON_0_2_REG(base) ((base)->PIGEON_0_2) +#define EPDC_PIGEON_1_0_REG(base) ((base)->PIGEON_1_0) +#define EPDC_PIGEON_1_1_REG(base) ((base)->PIGEON_1_1) +#define EPDC_PIGEON_1_2_REG(base) ((base)->PIGEON_1_2) +#define EPDC_PIGEON_2_0_REG(base) ((base)->PIGEON_2_0) +#define EPDC_PIGEON_2_1_REG(base) ((base)->PIGEON_2_1) +#define EPDC_PIGEON_2_2_REG(base) ((base)->PIGEON_2_2) +#define EPDC_PIGEON_3_0_REG(base) ((base)->PIGEON_3_0) +#define EPDC_PIGEON_3_1_REG(base) ((base)->PIGEON_3_1) +#define EPDC_PIGEON_3_2_REG(base) ((base)->PIGEON_3_2) +#define EPDC_PIGEON_4_0_REG(base) ((base)->PIGEON_4_0) +#define EPDC_PIGEON_4_1_REG(base) ((base)->PIGEON_4_1) +#define EPDC_PIGEON_4_2_REG(base) ((base)->PIGEON_4_2) +#define EPDC_PIGEON_5_0_REG(base) ((base)->PIGEON_5_0) +#define EPDC_PIGEON_5_1_REG(base) ((base)->PIGEON_5_1) +#define EPDC_PIGEON_5_2_REG(base) ((base)->PIGEON_5_2) +#define EPDC_PIGEON_6_0_REG(base) ((base)->PIGEON_6_0) +#define EPDC_PIGEON_6_1_REG(base) ((base)->PIGEON_6_1) +#define EPDC_PIGEON_6_2_REG(base) ((base)->PIGEON_6_2) +#define EPDC_PIGEON_7_0_REG(base) ((base)->PIGEON_7_0) +#define EPDC_PIGEON_7_1_REG(base) ((base)->PIGEON_7_1) +#define EPDC_PIGEON_7_2_REG(base) ((base)->PIGEON_7_2) +#define EPDC_PIGEON_8_0_REG(base) ((base)->PIGEON_8_0) +#define EPDC_PIGEON_8_1_REG(base) ((base)->PIGEON_8_1) +#define EPDC_PIGEON_8_2_REG(base) ((base)->PIGEON_8_2) +#define EPDC_PIGEON_9_0_REG(base) ((base)->PIGEON_9_0) +#define EPDC_PIGEON_9_1_REG(base) ((base)->PIGEON_9_1) +#define EPDC_PIGEON_9_2_REG(base) ((base)->PIGEON_9_2) +#define EPDC_PIGEON_10_0_REG(base) ((base)->PIGEON_10_0) +#define EPDC_PIGEON_10_1_REG(base) ((base)->PIGEON_10_1) +#define EPDC_PIGEON_10_2_REG(base) ((base)->PIGEON_10_2) +#define EPDC_PIGEON_11_0_REG(base) ((base)->PIGEON_11_0) +#define EPDC_PIGEON_11_1_REG(base) ((base)->PIGEON_11_1) +#define EPDC_PIGEON_11_2_REG(base) ((base)->PIGEON_11_2) +#define EPDC_PIGEON_12_0_REG(base) ((base)->PIGEON_12_0) +#define EPDC_PIGEON_12_1_REG(base) ((base)->PIGEON_12_1) +#define EPDC_PIGEON_12_2_REG(base) ((base)->PIGEON_12_2) +#define EPDC_PIGEON_13_0_REG(base) ((base)->PIGEON_13_0) +#define EPDC_PIGEON_13_1_REG(base) ((base)->PIGEON_13_1) +#define EPDC_PIGEON_13_2_REG(base) ((base)->PIGEON_13_2) +#define EPDC_PIGEON_14_0_REG(base) ((base)->PIGEON_14_0) +#define EPDC_PIGEON_14_1_REG(base) ((base)->PIGEON_14_1) +#define EPDC_PIGEON_14_2_REG(base) ((base)->PIGEON_14_2) +#define EPDC_PIGEON_15_0_REG(base) ((base)->PIGEON_15_0) +#define EPDC_PIGEON_15_1_REG(base) ((base)->PIGEON_15_1) +#define EPDC_PIGEON_15_2_REG(base) ((base)->PIGEON_15_2) +#define EPDC_PIGEON_16_0_REG(base) ((base)->PIGEON_16_0) +#define EPDC_PIGEON_16_1_REG(base) ((base)->PIGEON_16_1) +#define EPDC_PIGEON_16_2_REG(base) ((base)->PIGEON_16_2) + +/*! + * @} + */ /* end of group EPDC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- EPDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup EPDC_Register_Masks EPDC Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define EPDC_CTRL_LUT_DATA_SWIZZLE_MASK 0x30u +#define EPDC_CTRL_LUT_DATA_SWIZZLE_SHIFT 4 +#define EPDC_CTRL_LUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x))<PORT1_CNTL) +#define SIM_SETUP_REG(base) ((base)->SETUP) +#define SIM_PORT1_DETECT_REG(base) ((base)->PORT1_DETECT) +#define SIM_XMT_BUF_REG(base) ((base)->XMT_BUF) +#define SIM_RCV_BUF_REG(base) ((base)->RCV_BUF) +#define SIM_PORT0_CNTL_REG(base) ((base)->PORT0_CNTL) +#define SIM_CNTL_REG(base) ((base)->CNTL) +#define SIM_CLK_PRESCALER_REG(base) ((base)->CLK_PRESCALER) +#define SIM_RCV_THRESHOLD_REG(base) ((base)->RCV_THRESHOLD) +#define SIM_ENABLE_REG(base) ((base)->ENABLE) +#define SIM_XMT_STATUS_REG(base) ((base)->XMT_STATUS) +#define SIM_RCV_STATUS_REG(base) ((base)->RCV_STATUS) +#define SIM_INT_MASK_REG(base) ((base)->INT_MASK) +#define SIM_PORT0_DETECT_REG(base) ((base)->PORT0_DETECT) +#define SIM_DATA_FORMAT_REG(base) ((base)->DATA_FORMAT) +#define SIM_XMT_THRESHOLD_REG(base) ((base)->XMT_THRESHOLD) +#define SIM_GUARD_CNTL_REG(base) ((base)->GUARD_CNTL) +#define SIM_OD_CONFIG_REG(base) ((base)->OD_CONFIG) +#define SIM_RESET_CNTL_REG(base) ((base)->RESET_CNTL) +#define SIM_CHAR_WAIT_REG(base) ((base)->CHAR_WAIT) +#define SIM_GPCNT_REG(base) ((base)->GPCNT) +#define SIM_DIVISOR_REG(base) ((base)->DIVISOR) +#define SIM_BWT_REG(base) ((base)->BWT) +#define SIM_BGT_REG(base) ((base)->BGT) +#define SIM_BWT_H_REG(base) ((base)->BWT_H) +#define SIM_XMT_FIFO_STAT_REG(base) ((base)->XMT_FIFO_STAT) +#define SIM_RCV_FIFO_CNT_REG(base) ((base)->RCV_FIFO_CNT) +#define SIM_RCV_FIFO_WPTR_REG(base) ((base)->RCV_FIFO_WPTR) +#define SIM_RCV_FIFO_RPTR_REG(base) ((base)->RCV_FIFO_RPTR) + +/*! + * @} + */ /* end of group SIM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SIM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SIM_Register_Masks SIM Register Masks + * @{ + */ + +/* PORT1_CNTL Bit Fields */ +#define SIM_PORT1_CNTL_SAPD1_MASK 0x1u +#define SIM_PORT1_CNTL_SAPD1_SHIFT 0 +#define SIM_PORT1_CNTL_SVEN1_MASK 0x2u +#define SIM_PORT1_CNTL_SVEN1_SHIFT 1 +#define SIM_PORT1_CNTL_STEN1_MASK 0x4u +#define SIM_PORT1_CNTL_STEN1_SHIFT 2 +#define SIM_PORT1_CNTL_SRST1_MASK 0x8u +#define SIM_PORT1_CNTL_SRST1_SHIFT 3 +#define SIM_PORT1_CNTL_SCEN1_MASK 0x10u +#define SIM_PORT1_CNTL_SCEN1_SHIFT 4 +#define SIM_PORT1_CNTL_SCSP1_MASK 0x20u +#define SIM_PORT1_CNTL_SCSP1_SHIFT 5 +#define SIM_PORT1_CNTL_VOLT3_1_MASK 0x40u +#define SIM_PORT1_CNTL_VOLT3_1_SHIFT 6 +#define SIM_PORT1_CNTL_SFPD1_MASK 0x80u +#define SIM_PORT1_CNTL_SFPD1_SHIFT 7 +/* SETUP Bit Fields */ +#define SIM_SETUP_AMODE_MASK 0x1u +#define SIM_SETUP_AMODE_SHIFT 0 +#define SIM_SETUP_SPS_MASK 0x2u +#define SIM_SETUP_SPS_SHIFT 1 +/* PORT1_DETECT Bit Fields */ +#define SIM_PORT1_DETECT_SDIM1_MASK 0x1u +#define SIM_PORT1_DETECT_SDIM1_SHIFT 0 +#define SIM_PORT1_DETECT_SDI1_MASK 0x2u +#define SIM_PORT1_DETECT_SDI1_SHIFT 1 +#define SIM_PORT1_DETECT_SPDP1_MASK 0x4u +#define SIM_PORT1_DETECT_SPDP1_SHIFT 2 +#define SIM_PORT1_DETECT_SPDS1_MASK 0x8u +#define SIM_PORT1_DETECT_SPDS1_SHIFT 3 +/* XMT_BUF Bit Fields */ +#define SIM_XMT_BUF_XMT_MASK 0xFFu +#define SIM_XMT_BUF_XMT_SHIFT 0 +#define SIM_XMT_BUF_XMT(x) (((uint32_t)(((uint32_t)(x))<SC) +#define FTM_CNT_REG(base) ((base)->CNT) +#define FTM_MOD_REG(base) ((base)->MOD) +#define FTM_CSC_REG(base,index) ((base)->C[index].CSC) +#define FTM_CV_REG(base,index) ((base)->C[index].CV) +#define FTM_CNTIN_REG(base) ((base)->CNTIN) +#define FTM_STATUS_REG(base) ((base)->STATUS) +#define FTM_MODE_REG(base) ((base)->MODE) +#define FTM_SYNC_REG(base) ((base)->SYNC) +#define FTM_OUTINIT_REG(base) ((base)->OUTINIT) +#define FTM_OUTMASK_REG(base) ((base)->OUTMASK) +#define FTM_COMBINE_REG(base) ((base)->COMBINE) +#define FTM_DEADTIME_REG(base) ((base)->DEADTIME) +#define FTM_EXTTRIG_REG(base) ((base)->EXTTRIG) +#define FTM_POL_REG(base) ((base)->POL) +#define FTM_FILTER_REG(base) ((base)->FILTER) +#define FTM_QDCTRL_REG(base) ((base)->QDCTRL) +#define FTM_CONF_REG(base) ((base)->CONF) +#define FTM_SYNCONF_REG(base) ((base)->SYNCONF) +#define FTM_INVCTRL_REG(base) ((base)->INVCTRL) +#define FTM_SWOCTRL_REG(base) ((base)->SWOCTRL) +#define FTM_PWMLOAD_REG(base) ((base)->PWMLOAD) + +/*! + * @} + */ /* end of group FTM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- FTM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup FTM_Register_Masks FTM Register Masks + * @{ + */ + +/* SC Bit Fields */ +#define FTM_SC_PS_MASK 0x7u +#define FTM_SC_PS_SHIFT 0 +#define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<LPCR_A7_BSC) +#define GPC_LPCR_A7_AD_REG(base) ((base)->LPCR_A7_AD) +#define GPC_LPCR_M4_REG(base) ((base)->LPCR_M4) +#define GPC_SLPCR_REG(base) ((base)->SLPCR) +#define GPC_MLPCR_REG(base) ((base)->MLPCR) +#define GPC_PGC_ACK_SEL_A7_REG(base) ((base)->PGC_ACK_SEL_A7) +#define GPC_PGC_ACK_SEL_M4_REG(base) ((base)->PGC_ACK_SEL_M4) +#define GPC_MISC_REG(base) ((base)->MISC) +#define GPC_IMR1_CORE0_A7_REG(base) ((base)->IMR1_CORE0_A7) +#define GPC_IMR2_CORE0_A7_REG(base) ((base)->IMR2_CORE0_A7) +#define GPC_IMR3_CORE0_A7_REG(base) ((base)->IMR3_CORE0_A7) +#define GPC_IMR4_CORE0_A7_REG(base) ((base)->IMR4_CORE0_A7) +#define GPC_IMR1_CORE1_A7_REG(base) ((base)->IMR1_CORE1_A7) +#define GPC_IMR2_CORE1_A7_REG(base) ((base)->IMR2_CORE1_A7) +#define GPC_IMR3_CORE1_A7_REG(base) ((base)->IMR3_CORE1_A7) +#define GPC_IMR4_CORE1_A7_REG(base) ((base)->IMR4_CORE1_A7) +#define GPC_IMR1_M4_REG(base) ((base)->IMR1_M4) +#define GPC_IMR2_M4_REG(base) ((base)->IMR2_M4) +#define GPC_IMR3_M4_REG(base) ((base)->IMR3_M4) +#define GPC_IMR4_M4_REG(base) ((base)->IMR4_M4) +#define GPC_ISR1_A7_REG(base) ((base)->ISR1_A7) +#define GPC_ISR2_A7_REG(base) ((base)->ISR2_A7) +#define GPC_ISR3_A7_REG(base) ((base)->ISR3_A7) +#define GPC_ISR4_A7_REG(base) ((base)->ISR4_A7) +#define GPC_ISR1_M4_REG(base) ((base)->ISR1_M4) +#define GPC_ISR2_M4_REG(base) ((base)->ISR2_M4) +#define GPC_ISR3_M4_REG(base) ((base)->ISR3_M4) +#define GPC_ISR4_M4_REG(base) ((base)->ISR4_M4) +#define GPC_SLT_CFG_REG(base,index) ((base)->SLT_CFG[index]) +#define GPC_PGC_CPU_MAPPING_REG(base) ((base)->PGC_CPU_MAPPING) +#define GPC_CPU_PGC_SW_PUP_REQ_REG(base) ((base)->CPU_PGC_SW_PUP_REQ) +#define GPC_PU_PGC_SW_PUP_REQ_REG(base) ((base)->PU_PGC_SW_PUP_REQ) +#define GPC_CPU_PGC_SW_PDN_REQ_REG(base) ((base)->CPU_PGC_SW_PDN_REQ) +#define GPC_PU_PGC_SW_PDN_REQ_REG(base) ((base)->PU_PGC_SW_PDN_REQ) +#define GPC_LPS_A7_REG(base) ((base)->LPS_A7) +#define GPC_LPS_M4_REG(base) ((base)->LPS_M4) +#define GPC_GPC_GPR_REG(base) ((base)->GPC_GPR) +#define GPC_GTOR_REG(base) ((base)->GTOR) +#define GPC_DEBUG_ADDR1_REG(base) ((base)->DEBUG_ADDR1) +#define GPC_DEBUG_ADDR2_REG(base) ((base)->DEBUG_ADDR2) +#define GPC_CPU_PGC_PUP_STATUS1_REG(base) ((base)->CPU_PGC_PUP_STATUS1) +#define GPC_A7_PU_PGC_PUP_STATUS_REG(base,index) ((base)->A7_PU_PGC_PUP_STATUS[index]) +#define GPC_M4_PU_PGC_PUP_STATUS_REG(base,index) ((base)->M4_PU_PGC_PUP_STATUS[index]) +#define GPC_CPU_PGC_PDN_STATUS1_REG(base) ((base)->CPU_PGC_PDN_STATUS1) +#define GPC_A7_PU_PGC_PDN_STATUS_REG(base,index) ((base)->A7_PU_PGC_PDN_STATUS[index]) +#define GPC_M4_PU_PGC_PDN_STATUS_REG(base,index) ((base)->M4_PU_PGC_PDN_STATUS[index]) +#define GPC_A7_MIX_PDN_FLG_REG(base) ((base)->A7_MIX_PDN_FLG) +#define GPC_A7_PU_PDN_FLG_REG(base) ((base)->A7_PU_PDN_FLG) +#define GPC_M4_MIX_PDN_FLG_REG(base) ((base)->M4_MIX_PDN_FLG) +#define GPC_M4_PU_PDN_FLG_REG(base) ((base)->M4_PU_PDN_FLG) + +/*! + * @} + */ /* end of group GPC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_Register_Masks GPC Register Masks + * @{ + */ + +/* LPCR_A7_BSC Bit Fields */ +#define GPC_LPCR_A7_BSC_LPM0_MASK 0x3u +#define GPC_LPCR_A7_BSC_LPM0_SHIFT 0 +#define GPC_LPCR_A7_BSC_LPM0(x) (((uint32_t)(((uint32_t)(x))<A7CORE0_CTRL) +#define GPC_PGC_A7CORE0_PUPSCR_REG(base) ((base)->A7CORE0_PUPSCR) +#define GPC_PGC_A7CORE0_PDNSCR_REG(base) ((base)->A7CORE0_PDNSCR) +#define GPC_PGC_A7CORE0_SR_REG(base) ((base)->A7CORE0_SR) +#define GPC_PGC_A7CORE1_CTRL_REG(base) ((base)->A7CORE1_CTRL) +#define GPC_PGC_A7CORE1_PUPSCR_REG(base) ((base)->A7CORE1_PUPSCR) +#define GPC_PGC_A7CORE1_PDNSCR_REG(base) ((base)->A7CORE1_PDNSCR) +#define GPC_PGC_A7CORE1_SR_REG(base) ((base)->A7CORE1_SR) +#define GPC_PGC_A7SCU_CTRL_REG(base) ((base)->A7SCU_CTRL) +#define GPC_PGC_A7SCU_PUPSCR_REG(base) ((base)->A7SCU_PUPSCR) +#define GPC_PGC_A7SCU_PDNSCR_REG(base) ((base)->A7SCU_PDNSCR) +#define GPC_PGC_A7SCU_SR_REG(base) ((base)->A7SCU_SR) +#define GPC_PGC_SCU_AUXSW_REG(base) ((base)->SCU_AUXSW) +#define GPC_PGC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) +#define GPC_PGC_MIX_PUPSCR_REG(base) ((base)->MIX_PUPSCR) +#define GPC_PGC_MIX_PDNSCR_REG(base) ((base)->MIX_PDNSCR) +#define GPC_PGC_MIX_SR_REG(base) ((base)->MIX_SR) +#define GPC_PGC_MIPI_CTRL_REG(base) ((base)->MIPI_CTRL) +#define GPC_PGC_MIPI_PUPSCR_REG(base) ((base)->MIPI_PUPSCR) +#define GPC_PGC_MIPI_PDNSCR_REG(base) ((base)->MIPI_PDNSCR) +#define GPC_PGC_MIPI_SR_REG(base) ((base)->MIPI_SR) +#define GPC_PGC_MIPI_AUXSW_REG(base) ((base)->MIPI_AUXSW) +#define GPC_PGC_PCIE_CTRL_REG(base) ((base)->PCIE_CTRL) +#define GPC_PGC_PCIE_PUPSCR_REG(base) ((base)->PCIE_PUPSCR) +#define GPC_PGC_PCIE_PDNSCR_REG(base) ((base)->PCIE_PDNSCR) +#define GPC_PGC_PCIE_SR_REG(base) ((base)->PCIE_SR) +#define GPC_PGC_PCIE_AUXSW_REG(base) ((base)->PCIE_AUXSW) +#define GPC_PGC_HSIC_CTRL_REG(base) ((base)->HSIC_CTRL) +#define GPC_PGC_HSIC_PUPSCR_REG(base) ((base)->HSIC_PUPSCR) +#define GPC_PGC_HSIC_PDNSCR_REG(base) ((base)->HSIC_PDNSCR) +#define GPC_PGC_HSIC_SR_REG(base) ((base)->HSIC_SR) + +/*! + * @} + */ /* end of group GPC_PGC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPC_PGC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPC_PGC_Register_Masks GPC_PGC Register Masks + * @{ + */ + +/* A7CORE0_CTRL Bit Fields */ +#define GPC_PGC_A7CORE0_CTRL_PCR_MASK 0x1u +#define GPC_PGC_A7CORE0_CTRL_PCR_SHIFT 0 +#define GPC_PGC_A7CORE0_CTRL_L2RSTDIS_MASK 0x7Eu +#define GPC_PGC_A7CORE0_CTRL_L2RSTDIS_SHIFT 1 +#define GPC_PGC_A7CORE0_CTRL_L2RSTDIS(x) (((uint32_t)(((uint32_t)(x))<DR) +#define GPIO_GDIR_REG(base) ((base)->GDIR) +#define GPIO_PSR_REG(base) ((base)->PSR) +#define GPIO_ICR1_REG(base) ((base)->ICR1) +#define GPIO_ICR2_REG(base) ((base)->ICR2) +#define GPIO_IMR_REG(base) ((base)->IMR) +#define GPIO_ISR_REG(base) ((base)->ISR) +#define GPIO_EDGE_SEL_REG(base) ((base)->EDGE_SEL) + +/*! + * @} + */ /* end of group GPIO_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPIO Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPIO_Register_Masks GPIO Register Masks + * @{ + */ + +/* DR Bit Fields */ +#define GPIO_DR_DR_MASK 0xFFFFFFFFu +#define GPIO_DR_DR_SHIFT 0 +#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x))<CTRL0) +#define GPMI_CTRL0_SET_REG(base) ((base)->CTRL0_SET) +#define GPMI_CTRL0_CLR_REG(base) ((base)->CTRL0_CLR) +#define GPMI_CTRL0_TOG_REG(base) ((base)->CTRL0_TOG) +#define GPMI_COMPARE_REG(base) ((base)->COMPARE) +#define GPMI_ECCCTRL_REG(base) ((base)->ECCCTRL) +#define GPMI_ECCCTRL_SET_REG(base) ((base)->ECCCTRL_SET) +#define GPMI_ECCCTRL_CLR_REG(base) ((base)->ECCCTRL_CLR) +#define GPMI_ECCCTRL_TOG_REG(base) ((base)->ECCCTRL_TOG) +#define GPMI_ECCCOUNT_REG(base) ((base)->ECCCOUNT) +#define GPMI_PAYLOAD_REG(base) ((base)->PAYLOAD) +#define GPMI_AUXILIARY_REG(base) ((base)->AUXILIARY) +#define GPMI_CTRL1_REG(base) ((base)->CTRL1) +#define GPMI_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define GPMI_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define GPMI_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define GPMI_TIMING0_REG(base) ((base)->TIMING0) +#define GPMI_TIMING1_REG(base) ((base)->TIMING1) +#define GPMI_TIMING2_REG(base) ((base)->TIMING2) +#define GPMI_DATA_REG(base) ((base)->DATA) +#define GPMI_STAT_REG(base) ((base)->STAT) +#define GPMI_DEBUG_REG(base) ((base)->DEBUG) +#define GPMI_VERSION_REG(base) ((base)->VERSION) +#define GPMI_DEBUG2_REG(base) ((base)->DEBUG2) +#define GPMI_DEBUG3_REG(base) ((base)->DEBUG3) +#define GPMI_READ_DDR_DLL_CTRL_REG(base) ((base)->READ_DDR_DLL_CTRL) +#define GPMI_READ_DDR_DLL_STS_REG(base) ((base)->READ_DDR_DLL_STS) + +/*! + * @} + */ /* end of group GPMI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPMI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPMI_Register_Masks GPMI Register Masks + * @{ + */ + +/* CTRL0 Bit Fields */ +#define GPMI_CTRL0_XFER_COUNT_MASK 0xFFFFu +#define GPMI_CTRL0_XFER_COUNT_SHIFT 0 +#define GPMI_CTRL0_XFER_COUNT(x) (((uint32_t)(((uint32_t)(x))<CR) +#define GPT_PR_REG(base) ((base)->PR) +#define GPT_SR_REG(base) ((base)->SR) +#define GPT_IR_REG(base) ((base)->IR) +#define GPT_OCR1_REG(base) ((base)->OCR1) +#define GPT_OCR2_REG(base) ((base)->OCR2) +#define GPT_OCR3_REG(base) ((base)->OCR3) +#define GPT_ICR1_REG(base) ((base)->ICR1) +#define GPT_ICR2_REG(base) ((base)->ICR2) +#define GPT_CNT_REG(base) ((base)->CNT) + +/*! + * @} + */ /* end of group GPT_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- GPT Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup GPT_Register_Masks GPT Register Masks + * @{ + */ + +/* CR Bit Fields */ +#define GPT_CR_EN_MASK 0x1u +#define GPT_CR_EN_SHIFT 0 +#define GPT_CR_ENMOD_MASK 0x2u +#define GPT_CR_ENMOD_SHIFT 1 +#define GPT_CR_DBGEN_MASK 0x4u +#define GPT_CR_DBGEN_SHIFT 2 +#define GPT_CR_WAITEN_MASK 0x8u +#define GPT_CR_WAITEN_SHIFT 3 +#define GPT_CR_DOZEEN_MASK 0x10u +#define GPT_CR_DOZEEN_SHIFT 4 +#define GPT_CR_STOPEN_MASK 0x20u +#define GPT_CR_STOPEN_SHIFT 5 +#define GPT_CR_CLKSRC_MASK 0x1C0u +#define GPT_CR_CLKSRC_SHIFT 6 +#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x))<IADR) +#define I2C_IFDR_REG(base) ((base)->IFDR) +#define I2C_I2CR_REG(base) ((base)->I2CR) +#define I2C_I2SR_REG(base) ((base)->I2SR) +#define I2C_I2DR_REG(base) ((base)->I2DR) + +/*! + * @} + */ /* end of group I2C_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- I2C Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2C_Register_Masks I2C Register Masks + * @{ + */ + +/* IADR Bit Fields */ +#define I2C_IADR_ADR_MASK 0xFEu +#define I2C_IADR_ADR_SHIFT 1 +#define I2C_IADR_ADR(x) (((uint16_t)(((uint16_t)(x))<TCSR) +#define I2S_TCR1_REG(base) ((base)->TCR1) +#define I2S_TCR2_REG(base) ((base)->TCR2) +#define I2S_TCR3_REG(base) ((base)->TCR3) +#define I2S_TCR4_REG(base) ((base)->TCR4) +#define I2S_TCR5_REG(base) ((base)->TCR5) +#define I2S_TDR_REG(base,index) ((base)->TDR[index]) +#define I2S_TFR_REG(base,index) ((base)->TFR[index]) +#define I2S_TMR_REG(base) ((base)->TMR) +#define I2S_RCSR_REG(base) ((base)->RCSR) +#define I2S_RCR1_REG(base) ((base)->RCR1) +#define I2S_RCR2_REG(base) ((base)->RCR2) +#define I2S_RCR3_REG(base) ((base)->RCR3) +#define I2S_RCR4_REG(base) ((base)->RCR4) +#define I2S_RCR5_REG(base) ((base)->RCR5) +#define I2S_RDR_REG(base,index) ((base)->RDR[index]) +#define I2S_RFR_REG(base,index) ((base)->RFR[index]) +#define I2S_RMR_REG(base) ((base)->RMR) + +/*! + * @} + */ /* end of group I2S_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- I2S Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup I2S_Register_Masks I2S Register Masks + * @{ + */ + +/* TCSR Bit Fields */ +#define I2S_TCSR_FRDE_MASK 0x1u +#define I2S_TCSR_FRDE_SHIFT 0 +#define I2S_TCSR_FWDE_MASK 0x2u +#define I2S_TCSR_FWDE_SHIFT 1 +#define I2S_TCSR_FRIE_MASK 0x100u +#define I2S_TCSR_FRIE_SHIFT 8 +#define I2S_TCSR_FWIE_MASK 0x200u +#define I2S_TCSR_FWIE_SHIFT 9 +#define I2S_TCSR_FEIE_MASK 0x400u +#define I2S_TCSR_FEIE_SHIFT 10 +#define I2S_TCSR_SEIE_MASK 0x800u +#define I2S_TCSR_SEIE_SHIFT 11 +#define I2S_TCSR_WSIE_MASK 0x1000u +#define I2S_TCSR_WSIE_SHIFT 12 +#define I2S_TCSR_FRF_MASK 0x10000u +#define I2S_TCSR_FRF_SHIFT 16 +#define I2S_TCSR_FWF_MASK 0x20000u +#define I2S_TCSR_FWF_SHIFT 17 +#define I2S_TCSR_FEF_MASK 0x40000u +#define I2S_TCSR_FEF_SHIFT 18 +#define I2S_TCSR_SEF_MASK 0x80000u +#define I2S_TCSR_SEF_SHIFT 19 +#define I2S_TCSR_WSF_MASK 0x100000u +#define I2S_TCSR_WSF_SHIFT 20 +#define I2S_TCSR_SR_MASK 0x1000000u +#define I2S_TCSR_SR_SHIFT 24 +#define I2S_TCSR_FR_MASK 0x2000000u +#define I2S_TCSR_FR_SHIFT 25 +#define I2S_TCSR_BCE_MASK 0x10000000u +#define I2S_TCSR_BCE_SHIFT 28 +#define I2S_TCSR_DBGE_MASK 0x20000000u +#define I2S_TCSR_DBGE_SHIFT 29 +#define I2S_TCSR_STOPE_MASK 0x40000000u +#define I2S_TCSR_STOPE_SHIFT 30 +#define I2S_TCSR_TE_MASK 0x80000000u +#define I2S_TCSR_TE_SHIFT 31 +/* TCR1 Bit Fields */ +#define I2S_TCR1_TFW_MASK 0x1Fu +#define I2S_TCR1_TFW_SHIFT 0 +#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x))<SW_MUX_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO14) +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO15) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA08) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA09) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA10) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA11) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA12) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA13) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA14) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_DATA15) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCLK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDLE) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDOE) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDSHR) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE0) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE1) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE2) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_SDCE3) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDCLK) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDOE) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDRL) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_GDSP) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR0) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_BDR1) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_COM) +#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_MUX_CTL_PAD_EPDC_PWR_STAT) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_ENABLE) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_HSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_VSYNC) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_RESET) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA00) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA01) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA02) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA03) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA04) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA05) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA06) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA07) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA08) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA09) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA10) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA11) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA12) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA13) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA14) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA15) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA16) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA17) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA18) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA19) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA20) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA21) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA22) +#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_MUX_CTL_PAD_LCD_DATA23) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART1_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART2_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_RTS_B) +#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_REG(base) ((base)->SW_MUX_CTL_PAD_UART3_CTS_B) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C1_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C2_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C3_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SCL) +#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_MUX_CTL_PAD_I2C4_SDA) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MOSI) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_MISO) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI1_SS0) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SCLK) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MOSI) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_MISO) +#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_MUX_CTL_PAD_ECSPI2_SS0) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CD_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_WP) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CD_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_WP) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_STROBE) +#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_MUX_CTL_PAD_SD3_RESET_B) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_BCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_SYNC) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_SYNC) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_RX_BCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI1_MCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_SYNC) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_BCLK) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_RX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_MUX_CTL_PAD_SAI2_TX_DATA) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD0) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD1) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD2) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RD3) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_RXC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD0) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD1) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD2) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TD3) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RGMII_TXC) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_MUX_CTL_PAD_ENET1_COL) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO08) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO09) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO10) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO11) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO12) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO13) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO14) +#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO15) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_MOD) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TCK) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDI) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TDO) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TMS) +#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_REG(base) ((base)->SW_PAD_CTL_PAD_JTAG_TRST_B) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA08) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA09) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA10) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA11) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA12) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA13) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA14) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_DATA15) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCLK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDLE) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDOE) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDSHR) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE0) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE1) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE2) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_SDCE3) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDCLK) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDOE) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDRL) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_GDSP) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR0) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_BDR1) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_COM) +#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_REG(base) ((base)->SW_PAD_CTL_PAD_EPDC_PWR_STAT) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_ENABLE) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_HSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_VSYNC) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_RESET) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA00) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA01) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA02) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA03) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA04) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA05) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA06) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA07) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA08) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA09) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA10) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA11) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA12) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA13) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA14) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA15) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA16) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA17) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA18) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA19) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA20) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA21) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA22) +#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_REG(base) ((base)->SW_PAD_CTL_PAD_LCD_DATA23) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART1_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART2_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_RTS_B) +#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_REG(base) ((base)->SW_PAD_CTL_PAD_UART3_CTS_B) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C1_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C2_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C3_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SCL) +#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_REG(base) ((base)->SW_PAD_CTL_PAD_I2C4_SDA) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MOSI) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_MISO) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI1_SS0) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SCLK) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MOSI) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_MISO) +#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_REG(base) ((base)->SW_PAD_CTL_PAD_ECSPI2_SS0) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CD_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_WP) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD1_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CD_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_WP) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD2_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_CMD) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA0) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA1) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA2) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA3) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA4) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA5) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA6) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_DATA7) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_STROBE) +#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_REG(base) ((base)->SW_PAD_CTL_PAD_SD3_RESET_B) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_BCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_SYNC) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_SYNC) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_RX_BCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI1_MCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_SYNC) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_BCLK) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_RX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_REG(base) ((base)->SW_PAD_CTL_PAD_SAI2_TX_DATA) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD0) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD1) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD2) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RD3) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_RXC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD0) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD1) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD2) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TD3) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RGMII_TXC) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_TX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_RX_CLK) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_CRS) +#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_REG(base) ((base)->SW_PAD_CTL_PAD_ENET1_COL) +#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN1_RX_SELECT_INPUT) +#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_REG(base) ((base)->FLEXCAN2_RX_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_1_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_2_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_3_SELECT_INPUT) +#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_REG(base) ((base)->CCM_EXT_CLK_4_SELECT_INPUT) +#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_REG(base) ((base)->CCM_PMIC_READY_SELECT_INPUT) +#define IOMUXC_CSI_DATA2_SELECT_INPUT_REG(base) ((base)->CSI_DATA2_SELECT_INPUT) +#define IOMUXC_CSI_DATA3_SELECT_INPUT_REG(base) ((base)->CSI_DATA3_SELECT_INPUT) +#define IOMUXC_CSI_DATA4_SELECT_INPUT_REG(base) ((base)->CSI_DATA4_SELECT_INPUT) +#define IOMUXC_CSI_DATA5_SELECT_INPUT_REG(base) ((base)->CSI_DATA5_SELECT_INPUT) +#define IOMUXC_CSI_DATA6_SELECT_INPUT_REG(base) ((base)->CSI_DATA6_SELECT_INPUT) +#define IOMUXC_CSI_DATA7_SELECT_INPUT_REG(base) ((base)->CSI_DATA7_SELECT_INPUT) +#define IOMUXC_CSI_DATA8_SELECT_INPUT_REG(base) ((base)->CSI_DATA8_SELECT_INPUT) +#define IOMUXC_CSI_DATA9_SELECT_INPUT_REG(base) ((base)->CSI_DATA9_SELECT_INPUT) +#define IOMUXC_CSI_HSYNC_SELECT_INPUT_REG(base) ((base)->CSI_HSYNC_SELECT_INPUT) +#define IOMUXC_CSI_PIXCLK_SELECT_INPUT_REG(base) ((base)->CSI_PIXCLK_SELECT_INPUT) +#define IOMUXC_CSI_VSYNC_SELECT_INPUT_REG(base) ((base)->CSI_VSYNC_SELECT_INPUT) +#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI1_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI1_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI1_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI1_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI1_SS0_B_SELECT_INPUT) +#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI2_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI2_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI2_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI2_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI2_SS0_B_SELECT_INPUT) +#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI3_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI3_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI3_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI3_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI3_SS0_B_SELECT_INPUT) +#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_REG(base) ((base)->ECSPI4_SCLK_SELECT_INPUT) +#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_REG(base) ((base)->ECSPI4_MISO_SELECT_INPUT) +#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_REG(base) ((base)->ECSPI4_MOSI_SELECT_INPUT) +#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_REG(base) ((base)->ECSPI4_SS0_B_SELECT_INPUT) +#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_REG(base) ((base)->CCM_ENET1_REF_CLK_SELECT_INPUT) +#define IOMUXC_ENET1_MDIO_SELECT_INPUT_REG(base) ((base)->ENET1_MDIO_SELECT_INPUT) +#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET1_RX_CLK_SELECT_INPUT) +#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_REG(base) ((base)->CCM_ENET2_REF_CLK_SELECT_INPUT) +#define IOMUXC_ENET2_MDIO_SELECT_INPUT_REG(base) ((base)->ENET2_MDIO_SELECT_INPUT) +#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_REG(base) ((base)->ENET2_RX_CLK_SELECT_INPUT) +#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_IRQ_SELECT_INPUT) +#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_REG(base) ((base)->EPDC_PWR_STAT_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH0_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH1_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH2_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH3_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH4_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH5_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH6_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_CH7_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHA_SELECT_INPUT) +#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER1_PHB_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH0_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH1_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH2_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH3_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH4_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH5_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH6_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_CH7_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHA_SELECT_INPUT) +#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_REG(base) ((base)->FLEXTIMER2_PHB_SELECT_INPUT) +#define IOMUXC_I2C1_SCL_SELECT_INPUT_REG(base) ((base)->I2C1_SCL_SELECT_INPUT) +#define IOMUXC_I2C1_SDA_SELECT_INPUT_REG(base) ((base)->I2C1_SDA_SELECT_INPUT) +#define IOMUXC_I2C2_SCL_SELECT_INPUT_REG(base) ((base)->I2C2_SCL_SELECT_INPUT) +#define IOMUXC_I2C2_SDA_SELECT_INPUT_REG(base) ((base)->I2C2_SDA_SELECT_INPUT) +#define IOMUXC_I2C3_SCL_SELECT_INPUT_REG(base) ((base)->I2C3_SCL_SELECT_INPUT) +#define IOMUXC_I2C3_SDA_SELECT_INPUT_REG(base) ((base)->I2C3_SDA_SELECT_INPUT) +#define IOMUXC_I2C4_SCL_SELECT_INPUT_REG(base) ((base)->I2C4_SCL_SELECT_INPUT) +#define IOMUXC_I2C4_SDA_SELECT_INPUT_REG(base) ((base)->I2C4_SDA_SELECT_INPUT) +#define IOMUXC_KPP_COL0_SELECT_INPUT_REG(base) ((base)->KPP_COL0_SELECT_INPUT) +#define IOMUXC_KPP_COL1_SELECT_INPUT_REG(base) ((base)->KPP_COL1_SELECT_INPUT) +#define IOMUXC_KPP_COL2_SELECT_INPUT_REG(base) ((base)->KPP_COL2_SELECT_INPUT) +#define IOMUXC_KPP_COL3_SELECT_INPUT_REG(base) ((base)->KPP_COL3_SELECT_INPUT) +#define IOMUXC_KPP_COL4_SELECT_INPUT_REG(base) ((base)->KPP_COL4_SELECT_INPUT) +#define IOMUXC_KPP_COL5_SELECT_INPUT_REG(base) ((base)->KPP_COL5_SELECT_INPUT) +#define IOMUXC_KPP_COL6_SELECT_INPUT_REG(base) ((base)->KPP_COL6_SELECT_INPUT) +#define IOMUXC_KPP_COL7_SELECT_INPUT_REG(base) ((base)->KPP_COL7_SELECT_INPUT) +#define IOMUXC_KPP_ROW0_SELECT_INPUT_REG(base) ((base)->KPP_ROW0_SELECT_INPUT) +#define IOMUXC_KPP_ROW1_SELECT_INPUT_REG(base) ((base)->KPP_ROW1_SELECT_INPUT) +#define IOMUXC_KPP_ROW2_SELECT_INPUT_REG(base) ((base)->KPP_ROW2_SELECT_INPUT) +#define IOMUXC_KPP_ROW3_SELECT_INPUT_REG(base) ((base)->KPP_ROW3_SELECT_INPUT) +#define IOMUXC_KPP_ROW4_SELECT_INPUT_REG(base) ((base)->KPP_ROW4_SELECT_INPUT) +#define IOMUXC_KPP_ROW5_SELECT_INPUT_REG(base) ((base)->KPP_ROW5_SELECT_INPUT) +#define IOMUXC_KPP_ROW6_SELECT_INPUT_REG(base) ((base)->KPP_ROW6_SELECT_INPUT) +#define IOMUXC_KPP_ROW7_SELECT_INPUT_REG(base) ((base)->KPP_ROW7_SELECT_INPUT) +#define IOMUXC_LCD_BUSY_SELECT_INPUT_REG(base) ((base)->LCD_BUSY_SELECT_INPUT) +#define IOMUXC_LCD_DATA00_SELECT_INPUT_REG(base) ((base)->LCD_DATA00_SELECT_INPUT) +#define IOMUXC_LCD_DATA01_SELECT_INPUT_REG(base) ((base)->LCD_DATA01_SELECT_INPUT) +#define IOMUXC_LCD_DATA02_SELECT_INPUT_REG(base) ((base)->LCD_DATA02_SELECT_INPUT) +#define IOMUXC_LCD_DATA03_SELECT_INPUT_REG(base) ((base)->LCD_DATA03_SELECT_INPUT) +#define IOMUXC_LCD_DATA04_SELECT_INPUT_REG(base) ((base)->LCD_DATA04_SELECT_INPUT) +#define IOMUXC_LCD_DATA05_SELECT_INPUT_REG(base) ((base)->LCD_DATA05_SELECT_INPUT) +#define IOMUXC_LCD_DATA06_SELECT_INPUT_REG(base) ((base)->LCD_DATA06_SELECT_INPUT) +#define IOMUXC_LCD_DATA07_SELECT_INPUT_REG(base) ((base)->LCD_DATA07_SELECT_INPUT) +#define IOMUXC_LCD_DATA08_SELECT_INPUT_REG(base) ((base)->LCD_DATA08_SELECT_INPUT) +#define IOMUXC_LCD_DATA09_SELECT_INPUT_REG(base) ((base)->LCD_DATA09_SELECT_INPUT) +#define IOMUXC_LCD_DATA10_SELECT_INPUT_REG(base) ((base)->LCD_DATA10_SELECT_INPUT) +#define IOMUXC_LCD_DATA11_SELECT_INPUT_REG(base) ((base)->LCD_DATA11_SELECT_INPUT) +#define IOMUXC_LCD_DATA12_SELECT_INPUT_REG(base) ((base)->LCD_DATA12_SELECT_INPUT) +#define IOMUXC_LCD_DATA13_SELECT_INPUT_REG(base) ((base)->LCD_DATA13_SELECT_INPUT) +#define IOMUXC_LCD_DATA14_SELECT_INPUT_REG(base) ((base)->LCD_DATA14_SELECT_INPUT) +#define IOMUXC_LCD_DATA15_SELECT_INPUT_REG(base) ((base)->LCD_DATA15_SELECT_INPUT) +#define IOMUXC_LCD_DATA16_SELECT_INPUT_REG(base) ((base)->LCD_DATA16_SELECT_INPUT) +#define IOMUXC_LCD_DATA17_SELECT_INPUT_REG(base) ((base)->LCD_DATA17_SELECT_INPUT) +#define IOMUXC_LCD_DATA18_SELECT_INPUT_REG(base) ((base)->LCD_DATA18_SELECT_INPUT) +#define IOMUXC_LCD_DATA19_SELECT_INPUT_REG(base) ((base)->LCD_DATA19_SELECT_INPUT) +#define IOMUXC_LCD_DATA20_SELECT_INPUT_REG(base) ((base)->LCD_DATA20_SELECT_INPUT) +#define IOMUXC_LCD_DATA21_SELECT_INPUT_REG(base) ((base)->LCD_DATA21_SELECT_INPUT) +#define IOMUXC_LCD_DATA22_SELECT_INPUT_REG(base) ((base)->LCD_DATA22_SELECT_INPUT) +#define IOMUXC_LCD_DATA23_SELECT_INPUT_REG(base) ((base)->LCD_DATA23_SELECT_INPUT) +#define IOMUXC_LCD_VSYNC_SELECT_INPUT_REG(base) ((base)->LCD_VSYNC_SELECT_INPUT) +#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_RX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI1_RX_DATA_SELECT_INPUT) +#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_RX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI1_TX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI1_TX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_RX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI2_RX_DATA_SELECT_INPUT) +#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_RX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI2_TX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI2_TX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_RX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_REG(base) ((base)->SAI3_RX_DATA_SELECT_INPUT) +#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_RX_SYNC_SELECT_INPUT) +#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_REG(base) ((base)->SAI3_TX_BCLK_SELECT_INPUT) +#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_REG(base) ((base)->SAI3_TX_SYNC_SELECT_INPUT) +#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS0_SELECT_INPUT) +#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_REG(base) ((base)->SDMA_EVENTS1_SELECT_INPUT) +#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_PD_SELECT_INPUT) +#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM1_PORT1_TRXD_SELECT_INPUT) +#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_PD_SELECT_INPUT) +#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_REG(base) ((base)->SIM2_PORT1_TRXD_SELECT_INPUT) +#define IOMUXC_UART1_RTS_B_SELECT_INPUT_REG(base) ((base)->UART1_RTS_B_SELECT_INPUT) +#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART1_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART2_RTS_B_SELECT_INPUT_REG(base) ((base)->UART2_RTS_B_SELECT_INPUT) +#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART2_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART3_RTS_B_SELECT_INPUT_REG(base) ((base)->UART3_RTS_B_SELECT_INPUT) +#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART3_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART4_RTS_B_SELECT_INPUT_REG(base) ((base)->UART4_RTS_B_SELECT_INPUT) +#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART4_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART5_RTS_B_SELECT_INPUT_REG(base) ((base)->UART5_RTS_B_SELECT_INPUT) +#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART5_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART6_RTS_B_SELECT_INPUT_REG(base) ((base)->UART6_RTS_B_SELECT_INPUT) +#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART6_RX_DATA_SELECT_INPUT) +#define IOMUXC_UART7_RTS_B_SELECT_INPUT_REG(base) ((base)->UART7_RTS_B_SELECT_INPUT) +#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_REG(base) ((base)->UART7_RX_DATA_SELECT_INPUT) +#define IOMUXC_USB_OTG2_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG2_OC_SELECT_INPUT) +#define IOMUXC_USB_OTG1_OC_SELECT_INPUT_REG(base) ((base)->USB_OTG1_OC_SELECT_INPUT) +#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG2_ID_SELECT_INPUT) +#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_REG(base) ((base)->USB_OTG1_ID_SELECT_INPUT) +#define IOMUXC_SD3_CD_B_SELECT_INPUT_REG(base) ((base)->SD3_CD_B_SELECT_INPUT) +#define IOMUXC_SD3_WP_SELECT_INPUT_REG(base) ((base)->SD3_WP_SELECT_INPUT) + +/*! + * @} + */ /* end of group IOMUXC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- IOMUXC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks + * @{ + */ + +/* SW_MUX_CTL_PAD_GPIO1_IO08 Bit Fields */ +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_MASK 0x7u +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE_SHIFT 0 +#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<GPR0) +#define IOMUXC_GPR_GPR1_REG(base) ((base)->GPR1) +#define IOMUXC_GPR_GPR2_REG(base) ((base)->GPR2) +#define IOMUXC_GPR_GPR3_REG(base) ((base)->GPR3) +#define IOMUXC_GPR_GPR4_REG(base) ((base)->GPR4) +#define IOMUXC_GPR_GPR5_REG(base) ((base)->GPR5) +#define IOMUXC_GPR_GPR6_REG(base) ((base)->GPR6) +#define IOMUXC_GPR_GPR7_REG(base) ((base)->GPR7) +#define IOMUXC_GPR_GPR8_REG(base) ((base)->GPR8) +#define IOMUXC_GPR_GPR9_REG(base) ((base)->GPR9) +#define IOMUXC_GPR_GPR10_REG(base) ((base)->GPR10) +#define IOMUXC_GPR_GPR11_REG(base) ((base)->GPR11) +#define IOMUXC_GPR_GPR12_REG(base) ((base)->GPR12) +#define IOMUXC_GPR_GPR13_REG(base) ((base)->GPR13) +#define IOMUXC_GPR_GPR14_REG(base) ((base)->GPR14) +#define IOMUXC_GPR_GPR15_REG(base) ((base)->GPR15) +#define IOMUXC_GPR_GPR16_REG(base) ((base)->GPR16) +#define IOMUXC_GPR_GPR17_REG(base) ((base)->GPR17) +#define IOMUXC_GPR_GPR18_REG(base) ((base)->GPR18) +#define IOMUXC_GPR_GPR19_REG(base) ((base)->GPR19) +#define IOMUXC_GPR_GPR20_REG(base) ((base)->GPR20) +#define IOMUXC_GPR_GPR21_REG(base) ((base)->GPR21) +#define IOMUXC_GPR_GPR22_REG(base) ((base)->GPR22) + +/*! + * @} + */ /* end of group IOMUXC_GPR_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- IOMUXC_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks + * @{ + */ + +/* GPR0 Bit Fields */ +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_MASK 0x1u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL0_SHIFT 0 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_MASK 0x2u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL1_SHIFT 1 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_MASK 0x4u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL2_SHIFT 2 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_MASK 0x8u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL3_SHIFT 3 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_MASK 0x10u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL4_SHIFT 4 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_MASK 0x20u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL5_SHIFT 5 +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_MASK 0x40u +#define IOMUXC_GPR_GPR0_DMAREQ_MUX_SEL6_SHIFT 6 +/* GPR1 Bit Fields */ +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS0_MASK 0x1u +#define IOMUXC_GPR_GPR1_WEIM_ACT_CS0_SHIFT 0 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS0_MASK 0x6u +#define IOMUXC_GPR_GPR1_WEIM_ADDRS0_SHIFT 1 +#define IOMUXC_GPR_GPR1_WEIM_ADDRS0(x) (((uint32_t)(((uint32_t)(x))<SW_MUX_CTL_PAD_GPIO1_IO00) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO01) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO02) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO03) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO04) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO05) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO06) +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_MUX_CTL_PAD_GPIO1_IO07) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_TEST_MODE_REG(base) ((base)->SW_PAD_CTL_PAD_TEST_MODE) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRC_POR_B_REG(base) ((base)->SW_PAD_CTL_PAD_SRC_POR_B) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE0_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE0) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_BOOT_MODE1_REG(base) ((base)->SW_PAD_CTL_PAD_BOOT_MODE1) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO00_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO00) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO01_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO01) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO02_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO02) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO03_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO03) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO04_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO04) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO05_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO05) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO06_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO06) +#define IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07_REG(base) ((base)->SW_PAD_CTL_PAD_GPIO1_IO07) + +/*! + * @} + */ /* end of group IOMUXC_LPSR_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_Register_Masks IOMUXC_LPSR Register Masks + * @{ + */ + +/* SW_MUX_CTL_PAD_GPIO1_IO00 Bit Fields */ +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_MASK 0x7u +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE_SHIFT 0 +#define IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO00_MUX_MODE(x) (((uint32_t)(((uint32_t)(x))<IOMUXC_LPSR_GPR0) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR1_REG(base) ((base)->IOMUXC_LPSR_GPR1) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR2_REG(base) ((base)->IOMUXC_LPSR_GPR2) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR3_REG(base) ((base)->IOMUXC_LPSR_GPR3) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR4_REG(base) ((base)->IOMUXC_LPSR_GPR4) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR5_REG(base) ((base)->IOMUXC_LPSR_GPR5) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR6_REG(base) ((base)->IOMUXC_LPSR_GPR6) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR7_REG(base) ((base)->IOMUXC_LPSR_GPR7) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR8_REG(base) ((base)->IOMUXC_LPSR_GPR8) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR9_REG(base) ((base)->IOMUXC_LPSR_GPR9) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR10_REG(base) ((base)->IOMUXC_LPSR_GPR10) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR11_REG(base) ((base)->IOMUXC_LPSR_GPR11) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR12_REG(base) ((base)->IOMUXC_LPSR_GPR12) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR13_REG(base) ((base)->IOMUXC_LPSR_GPR13) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR14_REG(base) ((base)->IOMUXC_LPSR_GPR14) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR15_REG(base) ((base)->IOMUXC_LPSR_GPR15) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR16_REG(base) ((base)->IOMUXC_LPSR_GPR16) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR17_REG(base) ((base)->IOMUXC_LPSR_GPR17) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR18_REG(base) ((base)->IOMUXC_LPSR_GPR18) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR19_REG(base) ((base)->IOMUXC_LPSR_GPR19) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR20_REG(base) ((base)->IOMUXC_LPSR_GPR20) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR21_REG(base) ((base)->IOMUXC_LPSR_GPR21) +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR22_REG(base) ((base)->IOMUXC_LPSR_GPR22) + +/*! + * @} + */ /* end of group IOMUXC_LPSR_GPR_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- IOMUXC_LPSR_GPR Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup IOMUXC_LPSR_GPR_Register_Masks IOMUXC_LPSR_GPR Register Masks + * @{ + */ + +/* IOMUXC_LPSR_GPR0 Bit Fields */ +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_MASK 0xFFFFFFFFu +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP_SHIFT 0 +#define IOMUXC_LPSR_GPR_IOMUXC_LPSR_GPR0_GP(x) (((uint32_t)(((uint32_t)(x))<KPCR) +#define KPP_KPSR_REG(base) ((base)->KPSR) +#define KPP_KDDR_REG(base) ((base)->KDDR) +#define KPP_KPDR_REG(base) ((base)->KPDR) + +/*! + * @} + */ /* end of group KPP_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- KPP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup KPP_Register_Masks KPP Register Masks + * @{ + */ + +/* KPCR Bit Fields */ +#define KPP_KPCR_KRE_MASK 0xFFu +#define KPP_KPCR_KRE_SHIFT 0 +#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x))<RL) +#define LCDIF_RL_SET_REG(base) ((base)->RL_SET) +#define LCDIF_RL_CLR_REG(base) ((base)->RL_CLR) +#define LCDIF_RL_TOG_REG(base) ((base)->RL_TOG) +#define LCDIF_CTRL1_REG(base) ((base)->CTRL1) +#define LCDIF_CTRL1_SET_REG(base) ((base)->CTRL1_SET) +#define LCDIF_CTRL1_CLR_REG(base) ((base)->CTRL1_CLR) +#define LCDIF_CTRL1_TOG_REG(base) ((base)->CTRL1_TOG) +#define LCDIF_CTRL2_REG(base) ((base)->CTRL2) +#define LCDIF_CTRL2_SET_REG(base) ((base)->CTRL2_SET) +#define LCDIF_CTRL2_CLR_REG(base) ((base)->CTRL2_CLR) +#define LCDIF_CTRL2_TOG_REG(base) ((base)->CTRL2_TOG) +#define LCDIF_TRANSFER_COUNT_REG(base) ((base)->TRANSFER_COUNT) +#define LCDIF_CUR_BUF_REG(base) ((base)->CUR_BUF) +#define LCDIF_NEXT_BUF_REG(base) ((base)->NEXT_BUF) +#define LCDIF_TIMING_REG(base) ((base)->TIMING) +#define LCDIF_VDCTRL0_REG(base) ((base)->VDCTRL0) +#define LCDIF_VDCTRL0_SET_REG(base) ((base)->VDCTRL0_SET) +#define LCDIF_VDCTRL0_CLR_REG(base) ((base)->VDCTRL0_CLR) +#define LCDIF_VDCTRL0_TOG_REG(base) ((base)->VDCTRL0_TOG) +#define LCDIF_VDCTRL1_REG(base) ((base)->VDCTRL1) +#define LCDIF_VDCTRL2_REG(base) ((base)->VDCTRL2) +#define LCDIF_VDCTRL3_REG(base) ((base)->VDCTRL3) +#define LCDIF_VDCTRL4_REG(base) ((base)->VDCTRL4) +#define LCDIF_DVICTRL0_REG(base) ((base)->DVICTRL0) +#define LCDIF_DVICTRL1_REG(base) ((base)->DVICTRL1) +#define LCDIF_DVICTRL2_REG(base) ((base)->DVICTRL2) +#define LCDIF_DVICTRL3_REG(base) ((base)->DVICTRL3) +#define LCDIF_DVICTRL4_REG(base) ((base)->DVICTRL4) +#define LCDIF_CSC_COEFF0_REG(base) ((base)->CSC_COEFF0) +#define LCDIF_CSC_COEFF1_REG(base) ((base)->CSC_COEFF1) +#define LCDIF_CSC_COEFF2_REG(base) ((base)->CSC_COEFF2) +#define LCDIF_CSC_COEFF3_REG(base) ((base)->CSC_COEFF3) +#define LCDIF_CSC_COEFF4_REG(base) ((base)->CSC_COEFF4) +#define LCDIF_CSC_OFFSET_REG(base) ((base)->CSC_OFFSET) +#define LCDIF_CSC_LIMIT_REG(base) ((base)->CSC_LIMIT) +#define LCDIF_DATA_REG(base) ((base)->DATA) +#define LCDIF_BM_ERROR_STAT_REG(base) ((base)->BM_ERROR_STAT) +#define LCDIF_CRC_STAT_REG(base) ((base)->CRC_STAT) +#define LCDIF_STAT_REG(base) ((base)->STAT) +#define LCDIF_VERSION_REG(base) ((base)->VERSION) +#define LCDIF_DEBUG0_REG(base) ((base)->DEBUG0) +#define LCDIF_DEBUG1_REG(base) ((base)->DEBUG1) +#define LCDIF_DEBUG2_REG(base) ((base)->DEBUG2) +#define LCDIF_THRES_REG(base) ((base)->THRES) +#define LCDIF_AS_CTRL_REG(base) ((base)->AS_CTRL) +#define LCDIF_AS_BUF_REG(base) ((base)->AS_BUF) +#define LCDIF_AS_NEXT_BUF_REG(base) ((base)->AS_NEXT_BUF) +#define LCDIF_AS_CLRKEYLOW_REG(base) ((base)->AS_CLRKEYLOW) +#define LCDIF_AS_CLRKEYHIGH_REG(base) ((base)->AS_CLRKEYHIGH) +#define LCDIF_SYNC_DELAY_REG(base) ((base)->SYNC_DELAY) +#define LCDIF_DEBUG3_REG(base) ((base)->DEBUG3) +#define LCDIF_DEBUG4_REG(base) ((base)->DEBUG4) +#define LCDIF_DEBUG5_REG(base) ((base)->DEBUG5) + +/*! + * @} + */ /* end of group LCDIF_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- LCDIF Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LCDIF_Register_Masks LCDIF Register Masks + * @{ + */ + +/* RL Bit Fields */ +#define LCDIF_RL_RUN_MASK 0x1u +#define LCDIF_RL_RUN_SHIFT 0 +#define LCDIF_RL_DATA_FORMAT_24_BIT_MASK 0x2u +#define LCDIF_RL_DATA_FORMAT_24_BIT_SHIFT 1 +#define LCDIF_RL_DATA_FORMAT_18_BIT_MASK 0x4u +#define LCDIF_RL_DATA_FORMAT_18_BIT_SHIFT 2 +#define LCDIF_RL_DATA_FORMAT_16_BIT_MASK 0x8u +#define LCDIF_RL_DATA_FORMAT_16_BIT_SHIFT 3 +#define LCDIF_RL_RSRVD0_MASK 0x10u +#define LCDIF_RL_RSRVD0_SHIFT 4 +#define LCDIF_RL_MASTER_MASK 0x20u +#define LCDIF_RL_MASTER_SHIFT 5 +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_MASK 0x40u +#define LCDIF_RL_ENABLE_PXP_HANDSHAKE_SHIFT 6 +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_MASK 0x80u +#define LCDIF_RL_RGB_TO_YCBCR422_CSC_SHIFT 7 +#define LCDIF_RL_WORD_LENGTH_MASK 0x300u +#define LCDIF_RL_WORD_LENGTH_SHIFT 8 +#define LCDIF_RL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x))<PCCCR) +#define LMEM_PCCLCR_REG(base) ((base)->PCCLCR) +#define LMEM_PCCSAR_REG(base) ((base)->PCCSAR) +#define LMEM_PCCCVR_REG(base) ((base)->PCCCVR) +#define LMEM_PSCCR_REG(base) ((base)->PSCCR) +#define LMEM_PSCLCR_REG(base) ((base)->PSCLCR) +#define LMEM_PSCSAR_REG(base) ((base)->PSCSAR) +#define LMEM_PSCCVR_REG(base) ((base)->PSCCVR) + +/*! + * @} + */ /* end of group LMEM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- LMEM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup LMEM_Register_Masks LMEM Register Masks + * @{ + */ + +/* PCCCR Bit Fields */ +#define LMEM_PCCCR_ENCACHE_MASK 0x1u +#define LMEM_PCCCR_ENCACHE_SHIFT 0 +#define LMEM_PCCCR_ENWRBUF_MASK 0x2u +#define LMEM_PCCCR_ENWRBUF_SHIFT 1 +#define LMEM_PCCCR_PCCR2_MASK 0x4u +#define LMEM_PCCCR_PCCR2_SHIFT 2 +#define LMEM_PCCCR_PCCR3_MASK 0x8u +#define LMEM_PCCCR_PCCR3_SHIFT 3 +#define LMEM_PCCCR_INVW0_MASK 0x1000000u +#define LMEM_PCCCR_INVW0_SHIFT 24 +#define LMEM_PCCCR_PUSHW0_MASK 0x2000000u +#define LMEM_PCCCR_PUSHW0_SHIFT 25 +#define LMEM_PCCCR_INVW1_MASK 0x4000000u +#define LMEM_PCCCR_INVW1_SHIFT 26 +#define LMEM_PCCCR_PUSHW1_MASK 0x8000000u +#define LMEM_PCCCR_PUSHW1_SHIFT 27 +#define LMEM_PCCCR_GO_MASK 0x80000000u +#define LMEM_PCCCR_GO_SHIFT 31 +/* PCCLCR Bit Fields */ +#define LMEM_PCCLCR_LGO_MASK 0x1u +#define LMEM_PCCLCR_LGO_SHIFT 0 +#define LMEM_PCCLCR_CACHEADDR_MASK 0x1FFCu +#define LMEM_PCCLCR_CACHEADDR_SHIFT 2 +#define LMEM_PCCLCR_CACHEADDR(x) (((uint32_t)(((uint32_t)(x))<PLASC) +#define MCM_PLAMC_REG(base) ((base)->PLAMC) +#define MCM_FADR_REG(base) ((base)->FADR) +#define MCM_FATR_REG(base) ((base)->FATR) +#define MCM_FDR_REG(base) ((base)->FDR) + +/*! + * @} + */ /* end of group MCM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- MCM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MCM_Register_Masks MCM Register Masks + * @{ + */ + +/* PLASC Bit Fields */ +#define MCM_PLASC_ASC_MASK 0xFFu +#define MCM_PLASC_ASC_SHIFT 0 +#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<CSIS_CMN_CTRL) +#define MIPI_CSI2_CSIS_CLK_CTRL_REG(base) ((base)->CSIS_CLK_CTRL) +#define MIPI_CSI2_CSIS_INT_MSK_REG(base) ((base)->CSIS_INT_MSK) +#define MIPI_CSI2_CSIS_INT_SRC_REG(base) ((base)->CSIS_INT_SRC) +#define MIPI_CSI2_DPHY_STATUS_REG(base) ((base)->DPHY_STATUS) +#define MIPI_CSI2_DPHY_CMN_CTRL_REG(base) ((base)->DPHY_CMN_CTRL) +#define MIPI_CSI2_DPHY_BCTRL_L_REG(base) ((base)->DPHY_BCTRL_L) +#define MIPI_CSI2_DPHY_BCTRL_H_REG(base) ((base)->DPHY_BCTRL_H) +#define MIPI_CSI2_DPHY_SCTRL_L_REG(base) ((base)->DPHY_SCTRL_L) +#define MIPI_CSI2_DPHY_SCTRL_H_REG(base) ((base)->DPHY_SCTRL_H) +#define MIPI_CSI2_ISP_CONFIG_CH0_REG(base) ((base)->ISP_CONFIG_CH0) +#define MIPI_CSI2_ISP_RESOL_CH0_REG(base) ((base)->ISP_RESOL_CH0) +#define MIPI_CSI2_ISP_SYNC_CH0_REG(base) ((base)->ISP_SYNC_CH0) +#define MIPI_CSI2_SDW_CONFIG_CH0_REG(base) ((base)->SDW_CONFIG_CH0) +#define MIPI_CSI2_SDW_RESOL_CH0_REG(base) ((base)->SDW_RESOL_CH0) +#define MIPI_CSI2_SDW_SYNC_CH0_REG(base) ((base)->SDW_SYNC_CH0) +#define MIPI_CSI2_DBG_CTRL_REG(base) ((base)->DBG_CTRL) +#define MIPI_CSI2_DBG_INTR_MSK_REG(base) ((base)->DBG_INTR_MSK) +#define MIPI_CSI2_DBG_INTR_SRC_REG(base) ((base)->DBG_INTR_SRC) +#define MIPI_CSI2_NON_IMG_DATA_REG(base) ((base)->NON_IMG_DATA) + +/*! + * @} + */ /* end of group MIPI_CSI2_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- MIPI_CSI2 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_CSI2_Register_Masks MIPI_CSI2 Register Masks + * @{ + */ + +/* CSIS_CMN_CTRL Bit Fields */ +#define MIPI_CSI2_CSIS_CMN_CTRL_CSI_EN_MASK 0x1u +#define MIPI_CSI2_CSIS_CMN_CTRL_CSI_EN_SHIFT 0 +#define MIPI_CSI2_CSIS_CMN_CTRL_SW_REST_MASK 0x2u +#define MIPI_CSI2_CSIS_CMN_CTRL_SW_REST_SHIFT 1 +#define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_MASK 0x4u +#define MIPI_CSI2_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL_SHIFT 2 +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_MASK 0xF8u +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3_SHIFT 3 +#define MIPI_CSI2_CSIS_CMN_CTRL_RSVD3(x) (((uint32_t)(((uint32_t)(x))<VERSION) +#define MIPI_DSI_STATUS_REG(base) ((base)->STATUS) +#define MIPI_DSI_RGB_STATUS_REG(base) ((base)->RGB_STATUS) +#define MIPI_DSI_SWRST_REG(base) ((base)->SWRST) +#define MIPI_DSI_CLKCTRL_REG(base) ((base)->CLKCTRL) +#define MIPI_DSI_TIMEOUT_REG(base) ((base)->TIMEOUT) +#define MIPI_DSI_CONFIG_REG(base) ((base)->CONFIG) +#define MIPI_DSI_ESCMODE_REG(base) ((base)->ESCMODE) +#define MIPI_DSI_MDRESOL_REG(base) ((base)->MDRESOL) +#define MIPI_DSI_MVPORCH_REG(base) ((base)->MVPORCH) +#define MIPI_DSI_MHPORCH_REG(base) ((base)->MHPORCH) +#define MIPI_DSI_MSYNC_REG(base) ((base)->MSYNC) +#define MIPI_DSI_SDRESOL_REG(base) ((base)->SDRESOL) +#define MIPI_DSI_INTSRC_REG(base) ((base)->INTSRC) +#define MIPI_DSI_INTMSK_REG(base) ((base)->INTMSK) +#define MIPI_DSI_PKTHDR_REG(base) ((base)->PKTHDR) +#define MIPI_DSI_PAYLOAD_REG(base) ((base)->PAYLOAD) +#define MIPI_DSI_RXFIFO_REG(base) ((base)->RXFIFO) +#define MIPI_DSI_FIFOTHLD_REG(base) ((base)->FIFOTHLD) +#define MIPI_DSI_FIFOCTRL_REG(base) ((base)->FIFOCTRL) +#define MIPI_DSI_MEMACCHR_REG(base) ((base)->MEMACCHR) +#define MIPI_DSI_MULTI_PKT_REG(base) ((base)->MULTI_PKT) +#define MIPI_DSI_PLLCTRL_1G_REG(base) ((base)->PLLCTRL_1G) +#define MIPI_DSI_PLLCTRL_REG(base) ((base)->PLLCTRL) +#define MIPI_DSI_PLLCTRL1_REG(base) ((base)->PLLCTRL1) +#define MIPI_DSI_PLLCTRL2_REG(base) ((base)->PLLCTRL2) +#define MIPI_DSI_PLLTMR_REG(base) ((base)->PLLTMR) +#define MIPI_DSI_PHYCTRL_B1_REG(base) ((base)->PHYCTRL_B1) +#define MIPI_DSI_PHYCTRL_B2_REG(base) ((base)->PHYCTRL_B2) +#define MIPI_DSI_PHYCTRL_M1_REG(base) ((base)->PHYCTRL_M1) +#define MIPI_DSI_PHYCTRL_M2_REG(base) ((base)->PHYCTRL_M2) +#define MIPI_DSI_PHYTIMING_REG(base) ((base)->PHYTIMING) +#define MIPI_DSI_PHYTIMING1_REG(base) ((base)->PHYTIMING1) +#define MIPI_DSI_PHYTIMING2_REG(base) ((base)->PHYTIMING2) + +/*! + * @} + */ /* end of group MIPI_DSI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- MIPI_DSI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MIPI_DSI_Register_Masks MIPI_DSI Register Masks + * @{ + */ + +/* VERSION Bit Fields */ +#define MIPI_DSI_VERSION_VERSION_MASK 0xFFFFFFFFu +#define MIPI_DSI_VERSION_VERSION_SHIFT 0 +#define MIPI_DSI_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x))<TR[index]) +#define MU_TR_COUNT 4 +#define MU_RR_REG(base,index) ((base)->RR[index]) +#define MU_RR_COUNT 4 +#define MU_SR_REG(base) ((base)->SR) +#define MU_CR_REG(base) ((base)->CR) + +/*! + * @} + */ /* end of group MU_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- MU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup MU_Register_Masks MU Register Masks + * @{ + */ + +/* TR Bit Fields */ +#define MU_TR_TR0_MASK 0xFFFFFFFFu +#define MU_TR_TR0_SHIFT 0 +#define MU_TR_TR0(x) (((uint32_t)(((uint32_t)(x))<CTRL) +#define OCOTP_CTRL_SET_REG(base) ((base)->CTRL_SET) +#define OCOTP_CTRL_CLR_REG(base) ((base)->CTRL_CLR) +#define OCOTP_CTRL_TOG_REG(base) ((base)->CTRL_TOG) +#define OCOTP_TIMING_REG(base) ((base)->TIMING) +#define OCOTP_DATA0_REG(base) ((base)->DATA0) +#define OCOTP_DATA1_REG(base) ((base)->DATA1) +#define OCOTP_DATA2_REG(base) ((base)->DATA2) +#define OCOTP_DATA3_REG(base) ((base)->DATA3) +#define OCOTP_READ_CTRL_REG(base) ((base)->READ_CTRL) +#define OCOTP_READ_FUSE_DATA0_REG(base) ((base)->READ_FUSE_DATA0) +#define OCOTP_READ_FUSE_DATA1_REG(base) ((base)->READ_FUSE_DATA1) +#define OCOTP_READ_FUSE_DATA2_REG(base) ((base)->READ_FUSE_DATA2) +#define OCOTP_READ_FUSE_DATA3_REG(base) ((base)->READ_FUSE_DATA3) +#define OCOTP_SW_STICKY_REG(base) ((base)->SW_STICKY) +#define OCOTP_SCS_REG(base) ((base)->SCS) +#define OCOTP_SCS_SET_REG(base) ((base)->SCS_SET) +#define OCOTP_SCS_CLR_REG(base) ((base)->SCS_CLR) +#define OCOTP_SCS_TOG_REG(base) ((base)->SCS_TOG) +#define OCOTP_CRC_ADDR_REG(base) ((base)->CRC_ADDR) +#define OCOTP_CRC_VALUE_REG(base) ((base)->CRC_VALUE) +#define OCOTP_VERSION_REG(base) ((base)->VERSION) +#define OCOTP_LOCK_REG(base) ((base)->LOCK) +#define OCOTP_TESTER0_REG(base) ((base)->TESTER0) +#define OCOTP_TESTER1_REG(base) ((base)->TESTER1) +#define OCOTP_TESTER2_REG(base) ((base)->TESTER2) +#define OCOTP_TESTER3_REG(base) ((base)->TESTER3) +#define OCOTP_TESTER4_REG(base) ((base)->TESTER4) +#define OCOTP_TESTER5_REG(base) ((base)->TESTER5) +#define OCOTP_BOOT_CFG0_REG(base) ((base)->BOOT_CFG0) +#define OCOTP_BOOT_CFG1_REG(base) ((base)->BOOT_CFG1) +#define OCOTP_BOOT_CFG2_REG(base) ((base)->BOOT_CFG2) +#define OCOTP_BOOT_CFG3_REG(base) ((base)->BOOT_CFG3) +#define OCOTP_BOOT_CFG4_REG(base) ((base)->BOOT_CFG4) +#define OCOTP_MEM_TRIM0_REG(base) ((base)->MEM_TRIM0) +#define OCOTP_MEM_TRIM1_REG(base) ((base)->MEM_TRIM1) +#define OCOTP_ANA0_REG(base) ((base)->ANA0) +#define OCOTP_ANA1_REG(base) ((base)->ANA1) +#define OCOTP_OTPMK0_REG(base) ((base)->OTPMK0) +#define OCOTP_OTPMK1_REG(base) ((base)->OTPMK1) +#define OCOTP_OTPMK2_REG(base) ((base)->OTPMK2) +#define OCOTP_OTPMK3_REG(base) ((base)->OTPMK3) +#define OCOTP_OTPMK4_REG(base) ((base)->OTPMK4) +#define OCOTP_OTPMK5_REG(base) ((base)->OTPMK5) +#define OCOTP_OTPMK6_REG(base) ((base)->OTPMK6) +#define OCOTP_OTPMK7_REG(base) ((base)->OTPMK7) +#define OCOTP_SRK0_REG(base) ((base)->SRK0) +#define OCOTP_SRK1_REG(base) ((base)->SRK1) +#define OCOTP_SRK2_REG(base) ((base)->SRK2) +#define OCOTP_SRK3_REG(base) ((base)->SRK3) +#define OCOTP_SRK4_REG(base) ((base)->SRK4) +#define OCOTP_SRK5_REG(base) ((base)->SRK5) +#define OCOTP_SRK6_REG(base) ((base)->SRK6) +#define OCOTP_SRK7_REG(base) ((base)->SRK7) +#define OCOTP_SJC_RESP0_REG(base) ((base)->SJC_RESP0) +#define OCOTP_SJC_RESP1_REG(base) ((base)->SJC_RESP1) +#define OCOTP_USB_ID_REG(base) ((base)->USB_ID) +#define OCOTP_FIELD_RETURN_REG(base) ((base)->FIELD_RETURN) +#define OCOTP_MAC_ADDR0_REG(base) ((base)->MAC_ADDR0) +#define OCOTP_MAC_ADDR1_REG(base) ((base)->MAC_ADDR1) +#define OCOTP_MAC_ADDR2_REG(base) ((base)->MAC_ADDR2) +#define OCOTP_SRK_REVOKE_REG(base) ((base)->SRK_REVOKE) +#define OCOTP_MAU_KEY0_REG(base) ((base)->MAU_KEY0) +#define OCOTP_MAU_KEY1_REG(base) ((base)->MAU_KEY1) +#define OCOTP_MAU_KEY2_REG(base) ((base)->MAU_KEY2) +#define OCOTP_MAU_KEY3_REG(base) ((base)->MAU_KEY3) +#define OCOTP_MAU_KEY4_REG(base) ((base)->MAU_KEY4) +#define OCOTP_MAU_KEY5_REG(base) ((base)->MAU_KEY5) +#define OCOTP_MAU_KEY6_REG(base) ((base)->MAU_KEY6) +#define OCOTP_MAU_KEY7_REG(base) ((base)->MAU_KEY7) +#define OCOTP_GP10_REG(base) ((base)->GP10) +#define OCOTP_GP11_REG(base) ((base)->GP11) +#define OCOTP_GP20_REG(base) ((base)->GP20) +#define OCOTP_GP21_REG(base) ((base)->GP21) +#define OCOTP_CRC_GP10_REG(base) ((base)->CRC_GP10) +#define OCOTP_CRC_GP11_REG(base) ((base)->CRC_GP11) +#define OCOTP_CRC_GP20_REG(base) ((base)->CRC_GP20) +#define OCOTP_CRC_GP21_REG(base) ((base)->CRC_GP21) + +/*! + * @} + */ /* end of group OCOTP_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- OCOTP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup OCOTP_Register_Masks OCOTP Register Masks + * @{ + */ + +/* CTRL Bit Fields */ +#define OCOTP_CTRL_ADDR_MASK 0xFu +#define OCOTP_CTRL_ADDR_SHIFT 0 +#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x))<REG01) +#define PCIE_PHY_CMN_REG02_REG(base) ((base)->REG02) +#define PCIE_PHY_CMN_REG03_REG(base) ((base)->REG03) +#define PCIE_PHY_CMN_REG04_REG(base) ((base)->REG04) +#define PCIE_PHY_CMN_REG05_REG(base) ((base)->REG05) +#define PCIE_PHY_CMN_REG06_REG(base) ((base)->REG06) +#define PCIE_PHY_CMN_REG07_REG(base) ((base)->REG07) +#define PCIE_PHY_CMN_REG0B_REG(base) ((base)->REG0B) +#define PCIE_PHY_CMN_REG08_REG(base) ((base)->REG08) +#define PCIE_PHY_CMN_REG09_REG(base) ((base)->REG09) +#define PCIE_PHY_CMN_REG11_REG(base) ((base)->REG11) +#define PCIE_PHY_CMN_REG15_REG(base) ((base)->REG15) +#define PCIE_PHY_CMN_REG16_REG(base) ((base)->REG16) +#define PCIE_PHY_CMN_REG17_REG(base) ((base)->REG17) +#define PCIE_PHY_CMN_REG18_REG(base) ((base)->REG18) +#define PCIE_PHY_CMN_REG19_REG(base) ((base)->REG19) +#define PCIE_PHY_CMN_REG1A_REG(base) ((base)->REG1A) + +/*! + * @} + */ /* end of group PCIE_PHY_CMN_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_CMN Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_CMN_Register_Masks PCIE_PHY_CMN Register Masks + * @{ + */ + +/* REG01 Bit Fields */ +#define PCIE_PHY_CMN_REG01_TCODE_MASK 0xFu +#define PCIE_PHY_CMN_REG01_TCODE_SHIFT 0 +#define PCIE_PHY_CMN_REG01_TCODE(x) (((uint32_t)(((uint32_t)(x))<REG21) +#define PCIE_PHY_TRSV_REG22_REG(base) ((base)->REG22) +#define PCIE_PHY_TRSV_REG24_REG(base) ((base)->REG24) +#define PCIE_PHY_TRSV_REG2B_REG(base) ((base)->REG2B) +#define PCIE_PHY_TRSV_REG3A_REG(base) ((base)->REG3A) +#define PCIE_PHY_TRSV_REG3E_REG(base) ((base)->REG3E) +#define PCIE_PHY_TRSV_REG25_REG(base) ((base)->REG25) +#define PCIE_PHY_TRSV_REG26_REG(base) ((base)->REG26) +#define PCIE_PHY_TRSV_REG29_REG(base) ((base)->REG29) +#define PCIE_PHY_TRSV_REG31_REG(base) ((base)->REG31) +#define PCIE_PHY_TRSV_REG33_REG(base) ((base)->REG33) +#define PCIE_PHY_TRSV_REG36_REG(base) ((base)->REG36) +#define PCIE_PHY_TRSV_REG37_REG(base) ((base)->REG37) +#define PCIE_PHY_TRSV_REG38_REG(base) ((base)->REG38) +#define PCIE_PHY_TRSV_REG39_REG(base) ((base)->REG39) +#define PCIE_PHY_TRSV_REG40_REG(base) ((base)->REG40) +#define PCIE_PHY_TRSV_REG42_REG(base) ((base)->REG42) + +/*! + * @} + */ /* end of group PCIE_PHY_TRSV_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PCIE_PHY_TRSV Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PCIE_PHY_TRSV_Register_Masks PCIE_PHY_TRSV Register Masks + * @{ + */ + +/* REG21 Bit Fields */ +#define PCIE_PHY_TRSV_REG21_EMP_LVL_MASK 0x1Fu +#define PCIE_PHY_TRSV_REG21_EMP_LVL_SHIFT 0 +#define PCIE_PHY_TRSV_REG21_EMP_LVL(x) (((uint32_t)(((uint32_t)(x))<REG_1P0A) +#define PMU_REG_1P0A_SET_REG(base) ((base)->REG_1P0A_SET) +#define PMU_REG_1P0A_CLR_REG(base) ((base)->REG_1P0A_CLR) +#define PMU_REG_1P0A_TOG_REG(base) ((base)->REG_1P0A_TOG) +#define PMU_REG_1P0D_REG(base) ((base)->REG_1P0D) +#define PMU_REG_1P0D_SET_REG(base) ((base)->REG_1P0D_SET) +#define PMU_REG_1P0D_CLR_REG(base) ((base)->REG_1P0D_CLR) +#define PMU_REG_1P0D_TOG_REG(base) ((base)->REG_1P0D_TOG) +#define PMU_REG_HSIC_1P2_REG(base) ((base)->REG_HSIC_1P2) +#define PMU_REG_HSIC_1P2_SET_REG(base) ((base)->REG_HSIC_1P2_SET) +#define PMU_REG_HSIC_1P2_CLR_REG(base) ((base)->REG_HSIC_1P2_CLR) +#define PMU_REG_HSIC_1P2_TOG_REG(base) ((base)->REG_HSIC_1P2_TOG) +#define PMU_REG_LPSR_1P0_REG(base) ((base)->REG_LPSR_1P0) +#define PMU_REG_LPSR_1P0_SET_REG(base) ((base)->REG_LPSR_1P0_SET) +#define PMU_REG_LPSR_1P0_CLR_REG(base) ((base)->REG_LPSR_1P0_CLR) +#define PMU_REG_LPSR_1P0_TOG_REG(base) ((base)->REG_LPSR_1P0_TOG) +#define PMU_REF_REG(base) ((base)->REF) +#define PMU_REF_SET_REG(base) ((base)->REF_SET) +#define PMU_REF_CLR_REG(base) ((base)->REF_CLR) +#define PMU_REF_TOG_REG(base) ((base)->REF_TOG) +#define PMU_LOWPWR_CTRL_REG(base) ((base)->LOWPWR_CTRL) +#define PMU_LOWPWR_CTRL_SET_REG(base) ((base)->LOWPWR_CTRL_SET) +#define PMU_LOWPWR_CTRL_CLR_REG(base) ((base)->LOWPWR_CTRL_CLR) +#define PMU_LOWPWR_CTRL_TOG_REG(base) ((base)->LOWPWR_CTRL_TOG) + +/*! + * @} + */ /* end of group PMU_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PMU Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PMU_Register_Masks PMU Register Masks + * @{ + */ + +/* REG_1P0A Bit Fields */ +#define PMU_REG_1P0A_ENABLE_LINREG_MASK 0x1u +#define PMU_REG_1P0A_ENABLE_LINREG_SHIFT 0 +#define PMU_REG_1P0A_ENABLE_BO_MASK 0x2u +#define PMU_REG_1P0A_ENABLE_BO_SHIFT 1 +#define PMU_REG_1P0A_ENABLE_ILIMIT_MASK 0x4u +#define PMU_REG_1P0A_ENABLE_ILIMIT_SHIFT 2 +#define PMU_REG_1P0A_ENABLE_PULLDOWN_MASK 0x8u +#define PMU_REG_1P0A_ENABLE_PULLDOWN_SHIFT 3 +#define PMU_REG_1P0A_BO_OFFSET_MASK 0x70u +#define PMU_REG_1P0A_BO_OFFSET_SHIFT 4 +#define PMU_REG_1P0A_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x))<PWMCR) +#define PWM_PWMSR_REG(base) ((base)->PWMSR) +#define PWM_PWMIR_REG(base) ((base)->PWMIR) +#define PWM_PWMSAR_REG(base) ((base)->PWMSAR) +#define PWM_PWMPR_REG(base) ((base)->PWMPR) +#define PWM_PWMCNR_REG(base) ((base)->PWMCNR) + +/*! + * @} + */ /* end of group PWM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PWM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PWM_Register_Masks PWM Register Masks + * @{ + */ + +/* PWMCR Bit Fields */ +#define PWM_PWMCR_EN_MASK 0x1u +#define PWM_PWMCR_EN_SHIFT 0 +#define PWM_PWMCR_REPEAT_MASK 0x6u +#define PWM_PWMCR_REPEAT_SHIFT 1 +#define PWM_PWMCR_REPEAT(x) (((uint32_t)(((uint32_t)(x))<HW_PXP_CTRL) +#define PXP_HW_PXP_STAT_REG(base) ((base)->HW_PXP_STAT) +#define PXP_HW_PXP_OUT_CTRL_REG(base) ((base)->HW_PXP_OUT_CTRL) +#define PXP_HW_PXP_OUT_BUF_REG(base) ((base)->HW_PXP_OUT_BUF) +#define PXP_HW_PXP_OUT_BUF2_REG(base) ((base)->HW_PXP_OUT_BUF2) +#define PXP_HW_PXP_OUT_PITCH_REG(base) ((base)->HW_PXP_OUT_PITCH) +#define PXP_HW_PXP_OUT_LRC_REG(base) ((base)->HW_PXP_OUT_LRC) +#define PXP_HW_PXP_OUT_PS_ULC_REG(base) ((base)->HW_PXP_OUT_PS_ULC) +#define PXP_HW_PXP_OUT_PS_LRC_REG(base) ((base)->HW_PXP_OUT_PS_LRC) +#define PXP_HW_PXP_OUT_AS_ULC_REG(base) ((base)->HW_PXP_OUT_AS_ULC) +#define PXP_HW_PXP_OUT_AS_LRC_REG(base) ((base)->HW_PXP_OUT_AS_LRC) +#define PXP_HW_PXP_PS_CTRL_REG(base) ((base)->HW_PXP_PS_CTRL) +#define PXP_HW_PXP_PS_BUF_REG(base) ((base)->HW_PXP_PS_BUF) +#define PXP_HW_PXP_PS_UBUF_REG(base) ((base)->HW_PXP_PS_UBUF) +#define PXP_HW_PXP_PS_VBUF_REG(base) ((base)->HW_PXP_PS_VBUF) +#define PXP_HW_PXP_PS_PITCH_REG(base) ((base)->HW_PXP_PS_PITCH) +#define PXP_HW_PXP_PS_BACKGROUND_0_REG(base) ((base)->HW_PXP_PS_BACKGROUND_0) +#define PXP_HW_PXP_PS_SCALE_REG(base) ((base)->HW_PXP_PS_SCALE) +#define PXP_HW_PXP_PS_OFFSET_REG(base) ((base)->HW_PXP_PS_OFFSET) +#define PXP_HW_PXP_PS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_PS_CLRKEYLOW_0) +#define PXP_HW_PXP_PS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_PS_CLRKEYHIGH_0) +#define PXP_HW_PXP_AS_CTRL_REG(base) ((base)->HW_PXP_AS_CTRL) +#define PXP_HW_PXP_AS_BUF_REG(base) ((base)->HW_PXP_AS_BUF) +#define PXP_HW_PXP_AS_PITCH_REG(base) ((base)->HW_PXP_AS_PITCH) +#define PXP_HW_PXP_AS_CLRKEYLOW_0_REG(base) ((base)->HW_PXP_AS_CLRKEYLOW_0) +#define PXP_HW_PXP_AS_CLRKEYHIGH_0_REG(base) ((base)->HW_PXP_AS_CLRKEYHIGH_0) +#define PXP_HW_PXP_CSC1_COEF0_REG(base) ((base)->HW_PXP_CSC1_COEF0) +#define PXP_HW_PXP_CSC1_COEF1_REG(base) ((base)->HW_PXP_CSC1_COEF1) +#define PXP_HW_PXP_CSC1_COEF2_REG(base) ((base)->HW_PXP_CSC1_COEF2) +#define PXP_HW_PXP_CSC2_CTRL_REG(base) ((base)->HW_PXP_CSC2_CTRL) +#define PXP_HW_PXP_CSC2_COEF0_REG(base) ((base)->HW_PXP_CSC2_COEF0) +#define PXP_HW_PXP_CSC2_COEF1_REG(base) ((base)->HW_PXP_CSC2_COEF1) +#define PXP_HW_PXP_CSC2_COEF2_REG(base) ((base)->HW_PXP_CSC2_COEF2) +#define PXP_HW_PXP_CSC2_COEF3_REG(base) ((base)->HW_PXP_CSC2_COEF3) +#define PXP_HW_PXP_CSC2_COEF4_REG(base) ((base)->HW_PXP_CSC2_COEF4) +#define PXP_HW_PXP_CSC2_COEF5_REG(base) ((base)->HW_PXP_CSC2_COEF5) +#define PXP_HW_PXP_LUT_CTRL_REG(base) ((base)->HW_PXP_LUT_CTRL) +#define PXP_HW_PXP_LUT_ADDR_REG(base) ((base)->HW_PXP_LUT_ADDR) +#define PXP_HW_PXP_LUT_DATA_REG(base) ((base)->HW_PXP_LUT_DATA) +#define PXP_HW_PXP_LUT_EXTMEM_REG(base) ((base)->HW_PXP_LUT_EXTMEM) +#define PXP_HW_PXP_CFA_REG(base) ((base)->HW_PXP_CFA) +#define PXP_HW_PXP_ALPHA_A_CTRL_REG(base) ((base)->HW_PXP_ALPHA_A_CTRL) +#define PXP_HW_PXP_ALPHA_B_CTRL_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL) +#define PXP_HW_PXP_ALPHA_B_CTRL_1_REG(base) ((base)->HW_PXP_ALPHA_B_CTRL_1) +#define PXP_HW_PXP_PS_BACKGROUND_1_REG(base) ((base)->HW_PXP_PS_BACKGROUND_1) +#define PXP_HW_PXP_PS_CLRKEYLOW_1_REG(base) ((base)->HW_PXP_PS_CLRKEYLOW_1) +#define PXP_HW_PXP_PS_CLRKEYHIGH_1_REG(base) ((base)->HW_PXP_PS_CLRKEYHIGH_1) +#define PXP_HW_PXP_AS_CLRKEYLOW_1_REG(base) ((base)->HW_PXP_AS_CLRKEYLOW_1) +#define PXP_HW_PXP_AS_CLRKEYHIGH_1_REG(base) ((base)->HW_PXP_AS_CLRKEYHIGH_1) +#define PXP_HW_PXP_CTRL2_REG(base) ((base)->HW_PXP_CTRL2) +#define PXP_HW_PXP_POWER_REG0_REG(base) ((base)->HW_PXP_POWER_REG0) +#define PXP_HW_PXP_POWER_REG1_REG(base) ((base)->HW_PXP_POWER_REG1) +#define PXP_HW_PXP_DATA_PATH_CTRL0_REG(base) ((base)->HW_PXP_DATA_PATH_CTRL0) +#define PXP_HW_PXP_DATA_PATH_CTRL1_REG(base) ((base)->HW_PXP_DATA_PATH_CTRL1) +#define PXP_HW_PXP_INIT_MEM_CTRL_REG(base) ((base)->HW_PXP_INIT_MEM_CTRL) +#define PXP_HW_PXP_INIT_MEM_DATA_REG(base) ((base)->HW_PXP_INIT_MEM_DATA) +#define PXP_HW_PXP_INIT_MEM_DATA_HIGH_REG(base) ((base)->HW_PXP_INIT_MEM_DATA_HIGH) +#define PXP_HW_PXP_IRQ_MASK_REG(base) ((base)->HW_PXP_IRQ_MASK) +#define PXP_HW_PXP_IRQ_REG(base) ((base)->HW_PXP_IRQ) +#define PXP_HW_PXP_NEXT_REG(base) ((base)->HW_PXP_NEXT) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH0) +#define PXP_HW_PXP_INPUT_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_CTRL_CH1) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH0) +#define PXP_HW_PXP_INPUT_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_STATUS_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_ULC_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ACTIVE_SIZE_LRC_CH1) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SIZE_CH1) +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH0) +#define PXP_HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_BACKGROUND_COLOR_CH1) +#define PXP_HW_PXP_INPUT_FETCH_PITCH_REG(base) ((base)->HW_PXP_INPUT_FETCH_PITCH) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_OFFSET_CH1) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH0) +#define PXP_HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_SHIFT_WIDTH_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH0) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_0_CH1) +#define PXP_HW_PXP_INPUT_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_FETCH_ADDR_1_CH1) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH0) +#define PXP_HW_PXP_INPUT_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_CTRL_CH1) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH0) +#define PXP_HW_PXP_INPUT_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_STATUS_CH1) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH0) +#define PXP_HW_PXP_INPUT_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SIZE_CH1) +#define PXP_HW_PXP_INPUT_STORE_PITCH_REG(base) ((base)->HW_PXP_INPUT_STORE_PITCH) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH0) +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH0) +#define PXP_HW_PXP_INPUT_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_FILL_DATA_CH0) +#define PXP_HW_PXP_INPUT_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_0_CH1) +#define PXP_HW_PXP_INPUT_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_INPUT_STORE_ADDR_1_CH1) +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK0_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK1_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK2_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK3_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK4_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK5_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK6_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_MASK7_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_D_SHIFT_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_SHIFT_H_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_L_CH0) +#define PXP_HW_PXP_INPUT_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_INPUT_STORE_F_MASK_H_CH0) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH0) +#define PXP_HW_PXP_DITHER_FETCH_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_CTRL_CH1) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH0) +#define PXP_HW_PXP_DITHER_FETCH_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_STATUS_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_ULC_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ACTIVE_SIZE_LRC_CH1) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SIZE_CH1) +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH0) +#define PXP_HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_BACKGROUND_COLOR_CH1) +#define PXP_HW_PXP_DITHER_FETCH_PITCH_REG(base) ((base)->HW_PXP_DITHER_FETCH_PITCH) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_OFFSET_CH1) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH0) +#define PXP_HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_SHIFT_WIDTH_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH0) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_0_CH1) +#define PXP_HW_PXP_DITHER_FETCH_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_FETCH_ADDR_1_CH1) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH0) +#define PXP_HW_PXP_DITHER_STORE_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_CTRL_CH1) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH0) +#define PXP_HW_PXP_DITHER_STORE_STATUS_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_STATUS_CH1) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH0) +#define PXP_HW_PXP_DITHER_STORE_SIZE_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SIZE_CH1) +#define PXP_HW_PXP_DITHER_STORE_PITCH_REG(base) ((base)->HW_PXP_DITHER_STORE_PITCH) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH0) +#define PXP_HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_SHIFT_CTRL_CH1) +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH0) +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH0) +#define PXP_HW_PXP_DITHER_STORE_FILL_DATA_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_FILL_DATA_CH0) +#define PXP_HW_PXP_DITHER_STORE_ADDR_0_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_0_CH1) +#define PXP_HW_PXP_DITHER_STORE_ADDR_1_CH1_REG(base) ((base)->HW_PXP_DITHER_STORE_ADDR_1_CH1) +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK0_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK0_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK1_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK1_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK2_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK2_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK3_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK3_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK4_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK4_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK5_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK5_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK6_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK6_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_MASK7_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_MASK7_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_D_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_D_SHIFT_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_SHIFT_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_SHIFT_H_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_L_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_L_CH0) +#define PXP_HW_PXP_DITHER_STORE_F_MASK_H_CH0_REG(base) ((base)->HW_PXP_DITHER_STORE_F_MASK_H_CH0) +#define PXP_HW_PXP_DITHER_CTRL_REG(base) ((base)->HW_PXP_DITHER_CTRL) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA0_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA0) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA1_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA1) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA2_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA2) +#define PXP_HW_PXP_DITHER_FINAL_LUT_DATA3_REG(base) ((base)->HW_PXP_DITHER_FINAL_LUT_DATA3) +#define PXP_HW_PXP_HIST_A_CTRL_REG(base) ((base)->HW_PXP_HIST_A_CTRL) +#define PXP_HW_PXP_HIST_A_MASK_REG(base) ((base)->HW_PXP_HIST_A_MASK) +#define PXP_HW_PXP_HIST_A_BUF_SIZE_REG(base) ((base)->HW_PXP_HIST_A_BUF_SIZE) +#define PXP_HW_PXP_HIST_A_TOTAL_PIXEL_REG(base) ((base)->HW_PXP_HIST_A_TOTAL_PIXEL) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_X) +#define PXP_HW_PXP_HIST_A_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_A_ACTIVE_AREA_Y) +#define PXP_HW_PXP_HIST_A_RAW_STAT0_REG(base) ((base)->HW_PXP_HIST_A_RAW_STAT0) +#define PXP_HW_PXP_HIST_A_RAW_STAT1_REG(base) ((base)->HW_PXP_HIST_A_RAW_STAT1) +#define PXP_HW_PXP_HIST_B_CTRL_REG(base) ((base)->HW_PXP_HIST_B_CTRL) +#define PXP_HW_PXP_HIST_B_MASK_REG(base) ((base)->HW_PXP_HIST_B_MASK) +#define PXP_HW_PXP_HIST_B_BUF_SIZE_REG(base) ((base)->HW_PXP_HIST_B_BUF_SIZE) +#define PXP_HW_PXP_HIST_B_TOTAL_PIXEL_REG(base) ((base)->HW_PXP_HIST_B_TOTAL_PIXEL) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_X_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_X) +#define PXP_HW_PXP_HIST_B_ACTIVE_AREA_Y_REG(base) ((base)->HW_PXP_HIST_B_ACTIVE_AREA_Y) +#define PXP_HW_PXP_HIST_B_RAW_STAT0_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT0) +#define PXP_HW_PXP_HIST_B_RAW_STAT1_REG(base) ((base)->HW_PXP_HIST_B_RAW_STAT1) +#define PXP_HW_PXP_HIST2_PARAM_REG(base) ((base)->HW_PXP_HIST2_PARAM) +#define PXP_HW_PXP_HIST4_PARAM_REG(base) ((base)->HW_PXP_HIST4_PARAM) +#define PXP_HW_PXP_HIST8_PARAM0_REG(base) ((base)->HW_PXP_HIST8_PARAM0) +#define PXP_HW_PXP_HIST8_PARAM1_REG(base) ((base)->HW_PXP_HIST8_PARAM1) +#define PXP_HW_PXP_HIST16_PARAM0_REG(base) ((base)->HW_PXP_HIST16_PARAM0) +#define PXP_HW_PXP_HIST16_PARAM1_REG(base) ((base)->HW_PXP_HIST16_PARAM1) +#define PXP_HW_PXP_HIST16_PARAM2_REG(base) ((base)->HW_PXP_HIST16_PARAM2) +#define PXP_HW_PXP_HIST16_PARAM3_REG(base) ((base)->HW_PXP_HIST16_PARAM3) +#define PXP_HW_PXP_HIST32_PARAM0_REG(base) ((base)->HW_PXP_HIST32_PARAM0) +#define PXP_HW_PXP_HIST32_PARAM1_REG(base) ((base)->HW_PXP_HIST32_PARAM1) +#define PXP_HW_PXP_HIST32_PARAM2_REG(base) ((base)->HW_PXP_HIST32_PARAM2) +#define PXP_HW_PXP_HIST32_PARAM3_REG(base) ((base)->HW_PXP_HIST32_PARAM3) +#define PXP_HW_PXP_HIST32_PARAM4_REG(base) ((base)->HW_PXP_HIST32_PARAM4) +#define PXP_HW_PXP_HIST32_PARAM5_REG(base) ((base)->HW_PXP_HIST32_PARAM5) +#define PXP_HW_PXP_HIST32_PARAM6_REG(base) ((base)->HW_PXP_HIST32_PARAM6) +#define PXP_HW_PXP_HIST32_PARAM7_REG(base) ((base)->HW_PXP_HIST32_PARAM7) +#define PXP_HW_PXP_COMP_CTRL_REG(base) ((base)->HW_PXP_COMP_CTRL) +#define PXP_HW_PXP_COMP_FORMAT0_REG(base) ((base)->HW_PXP_COMP_FORMAT0) +#define PXP_HW_PXP_COMP_FORMAT1_REG(base) ((base)->HW_PXP_COMP_FORMAT1) +#define PXP_HW_PXP_COMP_FORMAT2_REG(base) ((base)->HW_PXP_COMP_FORMAT2) +#define PXP_HW_PXP_COMP_MASK0_REG(base) ((base)->HW_PXP_COMP_MASK0) +#define PXP_HW_PXP_COMP_MASK1_REG(base) ((base)->HW_PXP_COMP_MASK1) +#define PXP_HW_PXP_COMP_BUFFER_SIZE_REG(base) ((base)->HW_PXP_COMP_BUFFER_SIZE) +#define PXP_HW_PXP_COMP_SOURCE_REG(base) ((base)->HW_PXP_COMP_SOURCE) +#define PXP_HW_PXP_COMP_TARGET_REG(base) ((base)->HW_PXP_COMP_TARGET) +#define PXP_HW_PXP_COMP_BUFFER_A_REG(base) ((base)->HW_PXP_COMP_BUFFER_A) +#define PXP_HW_PXP_COMP_BUFFER_B_REG(base) ((base)->HW_PXP_COMP_BUFFER_B) +#define PXP_HW_PXP_COMP_BUFFER_C_REG(base) ((base)->HW_PXP_COMP_BUFFER_C) +#define PXP_HW_PXP_COMP_BUFFER_D_REG(base) ((base)->HW_PXP_COMP_BUFFER_D) +#define PXP_HW_PXP_COMP_DEBUG_REG(base) ((base)->HW_PXP_COMP_DEBUG) +#define PXP_HW_PXP_BUS_MUX_REG(base) ((base)->HW_PXP_BUS_MUX) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX0) +#define PXP_HW_PXP_HANDSHAKE_READY_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_READY_MUX1) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX0_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX0) +#define PXP_HW_PXP_HANDSHAKE_DONE_MUX1_REG(base) ((base)->HW_PXP_HANDSHAKE_DONE_MUX1) +#define PXP_HW_PXP_HANDSHAKE_CPU_FETCH_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_FETCH) +#define PXP_HW_PXP_HANDSHAKE_CPU_STORE_REG(base) ((base)->HW_PXP_HANDSHAKE_CPU_STORE) + +/*! + * @} + */ /* end of group PXP_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- PXP Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup PXP_Register_Masks PXP Register Masks + * @{ + */ + +/* HW_PXP_CTRL Bit Fields */ +#define PXP_HW_PXP_CTRL_ENABLE_MASK 0x1u +#define PXP_HW_PXP_CTRL_ENABLE_SHIFT 0 +#define PXP_HW_PXP_CTRL_IRQ_ENABLE_MASK 0x2u +#define PXP_HW_PXP_CTRL_IRQ_ENABLE_SHIFT 1 +#define PXP_HW_PXP_CTRL_NEXT_IRQ_ENABLE_MASK 0x4u +#define PXP_HW_PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT 2 +#define PXP_HW_PXP_CTRL_LUT_DMA_IRQ_ENABLE_MASK 0x8u +#define PXP_HW_PXP_CTRL_LUT_DMA_IRQ_ENABLE_SHIFT 3 +#define PXP_HW_PXP_CTRL_ENABLE_LCD0_HANDSHAKE_MASK 0x10u +#define PXP_HW_PXP_CTRL_ENABLE_LCD0_HANDSHAKE_SHIFT 4 +#define PXP_HW_PXP_CTRL_HANDSHAKE_ABORT_SKIP_MASK 0x20u +#define PXP_HW_PXP_CTRL_HANDSHAKE_ABORT_SKIP_SHIFT 5 +#define PXP_HW_PXP_CTRL_RSVD0_MASK 0xC0u +#define PXP_HW_PXP_CTRL_RSVD0_SHIFT 6 +#define PXP_HW_PXP_CTRL_RSVD0(x) (((uint32_t)(((uint32_t)(x))<MCR) +#define QuadSPI_IPCR_REG(base) ((base)->IPCR) +#define QuadSPI_FLSHCR_REG(base) ((base)->FLSHCR) +#define QuadSPI_BUF0CR_REG(base) ((base)->BUF0CR) +#define QuadSPI_BUF1CR_REG(base) ((base)->BUF1CR) +#define QuadSPI_BUF2CR_REG(base) ((base)->BUF2CR) +#define QuadSPI_BUF3CR_REG(base) ((base)->BUF3CR) +#define QuadSPI_BFGENCR_REG(base) ((base)->BFGENCR) +#define QuadSPI_BUF0IND_REG(base) ((base)->BUF0IND) +#define QuadSPI_BUF1IND_REG(base) ((base)->BUF1IND) +#define QuadSPI_BUF2IND_REG(base) ((base)->BUF2IND) +#define QuadSPI_SFAR_REG(base) ((base)->SFAR) +#define QuadSPI_SMPR_REG(base) ((base)->SMPR) +#define QuadSPI_RBSR_REG(base) ((base)->RBSR) +#define QuadSPI_RBCT_REG(base) ((base)->RBCT) +#define QuadSPI_TBSR_REG(base) ((base)->TBSR) +#define QuadSPI_TBDR_REG(base) ((base)->TBDR) +#define QuadSPI_SR_REG(base) ((base)->SR) +#define QuadSPI_FR_REG(base) ((base)->FR) +#define QuadSPI_RSER_REG(base) ((base)->RSER) +#define QuadSPI_SPNDST_REG(base) ((base)->SPNDST) +#define QuadSPI_SPTRCLR_REG(base) ((base)->SPTRCLR) +#define QuadSPI_SFA1AD_REG(base) ((base)->SFA1AD) +#define QuadSPI_SFA2AD_REG(base) ((base)->SFA2AD) +#define QuadSPI_SFB1AD_REG(base) ((base)->SFB1AD) +#define QuadSPI_SFB2AD_REG(base) ((base)->SFB2AD) +#define QuadSPI_RBDR_REG(base,index) ((base)->RBDR[index]) +#define QuadSPI_LUTKEY_REG(base) ((base)->LUTKEY) +#define QuadSPI_LCKCR_REG(base) ((base)->LCKCR) +#define QuadSPI_LUT_REG(base,index) ((base)->LUT[index]) + +/*! + * @} + */ /* end of group QuadSPI_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- QuadSPI Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup QuadSPI_Register_Masks QuadSPI Register Masks + * @{ + */ + +/* MCR Bit Fields */ +#define QuadSPI_MCR_SWRSTSD_MASK 0x1u +#define QuadSPI_MCR_SWRSTSD_SHIFT 0 +#define QuadSPI_MCR_SWRSTHD_MASK 0x2u +#define QuadSPI_MCR_SWRSTHD_SHIFT 1 +#define QuadSPI_MCR_END_CFG_MASK 0xCu +#define QuadSPI_MCR_END_CFG_SHIFT 2 +#define QuadSPI_MCR_END_CFG(x) (((uint32_t)(((uint32_t)(x))<VIR) +#define RDC_STAT_REG(base) ((base)->STAT) +#define RDC_INTCTRL_REG(base) ((base)->INTCTRL) +#define RDC_INTSTAT_REG(base) ((base)->INTSTAT) +#define RDC_MDA_REG(base,index) ((base)->MDA[index]) +#define RDC_PDAP_REG(base,index) ((base)->PDAP[index]) +#define RDC_MRSA_REG(base,index) ((base)->MR[index].MRSA) +#define RDC_MREA_REG(base,index) ((base)->MR[index].MREA) +#define RDC_MRC_REG(base,index) ((base)->MR[index].MRC) +#define RDC_MRVS_REG(base,index) ((base)->MR[index].MRVS) + +/*! + * @} + */ /* end of group RDC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- RDC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_Register_Masks RDC Register Masks + * @{ + */ + +/* VIR Bit Fields */ +#define RDC_VIR_NDID_MASK 0xFu +#define RDC_VIR_NDID_SHIFT 0 +#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x))<GATE[index]) +#define RDC_SEMAPHORE_RSTGT_W_REG(base) ((base)->RSTGT_W) +#define RDC_SEMAPHORE_RSTGT_R_REG(base) ((base)->RSTGT_R) + +/*! + * @} + */ /* end of group RDC_SEMAPHORE_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- RDC_SEMAPHORE Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks + * @{ + */ + +/* GATE Bit Fields */ +#define RDC_SEMAPHORE_GATE_GTFSM_MASK 0xFu +#define RDC_SEMAPHORE_GATE_GTFSM_SHIFT 0 +#define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x))<ROMPATCHD[index]) +#define ROMC_ROMPATCHCNTL_REG(base) ((base)->ROMPATCHCNTL) +#define ROMC_ROMPATCHENH_REG(base) ((base)->ROMPATCHENH) +#define ROMC_ROMPATCHENL_REG(base) ((base)->ROMPATCHENL) +#define ROMC_ROMPATCHA_REG(base,index) ((base)->ROMPATCHA[index]) +#define ROMC_ROMPATCHSR_REG(base) ((base)->ROMPATCHSR) + +/*! + * @} + */ /* end of group ROMC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- ROMC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup ROMC_Register_Masks ROMC Register Masks + * @{ + */ + +/* ROMPATCHD Bit Fields */ +#define ROMC_ROMPATCHD_DATAX_MASK 0xFFFFFFFFu +#define ROMC_ROMPATCHD_DATAX_SHIFT 0 +#define ROMC_ROMPATCHD_DATAX(x) (((uint32_t)(((uint32_t)(x))<MC0PTR) +#define SDMAARM_INTR_REG(base) ((base)->INTR) +#define SDMAARM_STOP_STAT_REG(base) ((base)->STOP_STAT) +#define SDMAARM_HSTART_REG(base) ((base)->HSTART) +#define SDMAARM_EVTOVR_REG(base) ((base)->EVTOVR) +#define SDMAARM_DSPOVR_REG(base) ((base)->DSPOVR) +#define SDMAARM_HOSTOVR_REG(base) ((base)->HOSTOVR) +#define SDMAARM_EVTPEND_REG(base) ((base)->EVTPEND) +#define SDMAARM_RESET_REG(base) ((base)->RESET) +#define SDMAARM_EVTERR_REG(base) ((base)->EVTERR) +#define SDMAARM_INTRMASK_REG(base) ((base)->INTRMASK) +#define SDMAARM_PSW_REG(base) ((base)->PSW) +#define SDMAARM_EVTERRDBG_REG(base) ((base)->EVTERRDBG) +#define SDMAARM_CONFIG_REG(base) ((base)->CONFIG) +#define SDMAARM_SDMA_LOCK_REG(base) ((base)->SDMA_LOCK) +#define SDMAARM_ONCE_ENB_REG(base) ((base)->ONCE_ENB) +#define SDMAARM_ONCE_DATA_REG(base) ((base)->ONCE_DATA) +#define SDMAARM_ONCE_INSTR_REG(base) ((base)->ONCE_INSTR) +#define SDMAARM_ONCE_STAT_REG(base) ((base)->ONCE_STAT) +#define SDMAARM_ONCE_CMD_REG(base) ((base)->ONCE_CMD) +#define SDMAARM_ILLINSTADDR_REG(base) ((base)->ILLINSTADDR) +#define SDMAARM_CHN0ADDR_REG(base) ((base)->CHN0ADDR) +#define SDMAARM_EVT_MIRROR_REG(base) ((base)->EVT_MIRROR) +#define SDMAARM_EVT_MIRROR2_REG(base) ((base)->EVT_MIRROR2) +#define SDMAARM_XTRIG_CONF1_REG(base) ((base)->XTRIG_CONF1) +#define SDMAARM_XTRIG_CONF2_REG(base) ((base)->XTRIG_CONF2) +#define SDMAARM_SDMA_CHNPRI_REG(base,index) ((base)->SDMA_CHNPRI[index]) +#define SDMAARM_CHNENBL_REG(base,index) ((base)->CHNENBL[index]) + +/*! + * @} + */ /* end of group SDMAARM_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SDMAARM Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SDMAARM_Register_Masks SDMAARM Register Masks + * @{ + */ + +/* MC0PTR Bit Fields */ +#define SDMAARM_MC0PTR_MC0PTR_MASK 0xFFFFFFFFu +#define SDMAARM_MC0PTR_MC0PTR_SHIFT 0 +#define SDMAARM_MC0PTR_MC0PTR(x) (((uint32_t)(((uint32_t)(x))<GATE00) +#define SEMA4_GATE01_REG(base) ((base)->GATE01) +#define SEMA4_GATE02_REG(base) ((base)->GATE02) +#define SEMA4_GATE03_REG(base) ((base)->GATE03) +#define SEMA4_GATE04_REG(base) ((base)->GATE04) +#define SEMA4_GATE05_REG(base) ((base)->GATE05) +#define SEMA4_GATE06_REG(base) ((base)->GATE06) +#define SEMA4_GATE07_REG(base) ((base)->GATE07) +#define SEMA4_GATE08_REG(base) ((base)->GATE08) +#define SEMA4_GATE09_REG(base) ((base)->GATE09) +#define SEMA4_GATE10_REG(base) ((base)->GATE10) +#define SEMA4_GATE11_REG(base) ((base)->GATE11) +#define SEMA4_GATE12_REG(base) ((base)->GATE12) +#define SEMA4_GATE13_REG(base) ((base)->GATE13) +#define SEMA4_GATE14_REG(base) ((base)->GATE14) +#define SEMA4_GATE15_REG(base) ((base)->GATE15) +#define SEMA4_CPINE_REG(base,index) ((base)->CPnINE[index].INE) +#define SEMA4_CPNTF_REG(base,index) ((base)->CPnNTF[index].NTF) +#define SEMA4_RSTGT_REG(base) ((base)->RSTGT) +#define SEMA4_RSTNTF_REG(base) ((base)->RSTNTF) + +/*! + * @} + */ /* end of group SEMA4_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SEMA4 Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SEMA4_Register_Masks SEMA4 Register Masks + * @{ + */ + +/* GATE00 Bit Fields */ +#define SEMA4_GATE00_GTFSM_MASK 0x3u +#define SEMA4_GATE00_GTFSM_SHIFT 0 +#define SEMA4_GATE00_GTFSM(x) (((uint8_t)(((uint8_t)(x))<GPUSR1) +#define SJC_GPUSR2_REG(base) ((base)->GPUSR2.GPUSR2) +#define SJC_GPUSR3_REG(base) ((base)->GPUSR3.GPUSR3) +#define SJC_GPSSR_REG(base) ((base)->GPSSR.GPSSR) +#define SJC_DCR_REG(base) ((base)->DCR.DCR) +#define SJC_SSR_REG(base) ((base)->SSR.SSR) +#define SJC_GPCCR_REG(base) ((base)->GPCCR.GPCCR) + +/*! + * @} + */ /* end of group SJC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SJC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SJC_Register_Masks SJC Register Masks + * @{ + */ + +/* GPUSR1 Bit Fields */ +#define SJC_GPUSR1_A_DBG_MASK 0x1u +#define SJC_GPUSR1_A_DBG_SHIFT 0 +#define SJC_GPUSR1_A_WFI_MASK 0x2u +#define SJC_GPUSR1_A_WFI_SHIFT 1 +#define SJC_GPUSR1_S_STAT_MASK 0x1Cu +#define SJC_GPUSR1_S_STAT_SHIFT 2 +#define SJC_GPUSR1_S_STAT(x) (((uint32_t)(((uint32_t)(x))<HPLR) +#define SNVS_HPCOMR_REG(base) ((base)->HPCOMR) +#define SNVS_HPCR_REG(base) ((base)->HPCR) +#define SNVS_HPSR_REG(base) ((base)->HPSR) +#define SNVS_HPRTCMR_REG(base) ((base)->HPRTCMR) +#define SNVS_HPRTCLR_REG(base) ((base)->HPRTCLR) +#define SNVS_HPTAMR_REG(base) ((base)->HPTAMR) +#define SNVS_HPTALR_REG(base) ((base)->HPTALR) +#define SNVS_LPLR_REG(base) ((base)->LPLR) +#define SNVS_LPCR_REG(base) ((base)->LPCR) +#define SNVS_LPSR_REG(base) ((base)->LPSR) +#define SNVS_LPSMCMR_REG(base) ((base)->LPSMCMR) +#define SNVS_LPSMCLR_REG(base) ((base)->LPSMCLR) +#define SNVS_LPGPR_REG(base) ((base)->LPGPR) +#define SNVS_HPVIDR1_REG(base) ((base)->HPVIDR1) +#define SNVS_HPVIDR2_REG(base) ((base)->HPVIDR2) + +/*! + * @} + */ /* end of group SNVS_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SNVS Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SNVS_Register_Masks SNVS Register Masks + * @{ + */ + +/* HPLR Bit Fields */ +#define SNVS_HPLR_MC_SL_MASK 0x10u +#define SNVS_HPLR_MC_SL_SHIFT 4 +#define SNVS_HPLR_GPR_SL_MASK 0x20u +#define SNVS_HPLR_GPR_SL_SHIFT 5 +/* HPCOMR Bit Fields */ +#define SNVS_HPCOMR_LP_SWR_MASK 0x10u +#define SNVS_HPCOMR_LP_SWR_SHIFT 4 +#define SNVS_HPCOMR_LP_SWR_DIS_MASK 0x20u +#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT 5 +#define SNVS_HPCOMR_NPSWA_EN_MASK 0x80000000u +#define SNVS_HPCOMR_NPSWA_EN_SHIFT 31 +/* HPCR Bit Fields */ +#define SNVS_HPCR_RTC_EN_MASK 0x1u +#define SNVS_HPCR_RTC_EN_SHIFT 0 +#define SNVS_HPCR_HPTA_EN_MASK 0x2u +#define SNVS_HPCR_HPTA_EN_SHIFT 1 +#define SNVS_HPCR_PI_EN_MASK 0x8u +#define SNVS_HPCR_PI_EN_SHIFT 3 +#define SNVS_HPCR_PI_FREQ_MASK 0xF0u +#define SNVS_HPCR_PI_FREQ_SHIFT 4 +#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x))<PRR[index]) + +/*! + * @} + */ /* end of group SPBA_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SPBA Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SPBA_Register_Masks SPBA Register Masks + * @{ + */ + +/* PRR Bit Fields */ +#define SPBA_PRR_RARA_MASK 0x1u +#define SPBA_PRR_RARA_SHIFT 0 +#define SPBA_PRR_RARB_MASK 0x2u +#define SPBA_PRR_RARB_SHIFT 1 +#define SPBA_PRR_RARC_MASK 0x4u +#define SPBA_PRR_RARC_SHIFT 2 +#define SPBA_PRR_ROI_MASK 0x30000u +#define SPBA_PRR_ROI_SHIFT 16 +#define SPBA_PRR_ROI(x) (((uint32_t)(((uint32_t)(x))<SCR) +#define SRC_A7RCR0_REG(base) ((base)->A7RCR0) +#define SRC_A7RCR1_REG(base) ((base)->A7RCR1) +#define SRC_M4RCR_REG(base) ((base)->M4RCR) +#define SRC_ERCR_REG(base) ((base)->ERCR) +#define SRC_HSICPHY_RCR_REG(base) ((base)->HSICPHY_RCR) +#define SRC_USBOPHY1_RCR_REG(base) ((base)->USBOPHY1_RCR) +#define SRC_USBOPHY2_RCR_REG(base) ((base)->USBOPHY2_RCR) +#define SRC_MIPIPHY_RCR_REG(base) ((base)->MIPIPHY_RCR) +#define SRC_PCIEPHY_RCR_REG(base) ((base)->PCIEPHY_RCR) +#define SRC_SBMR1_REG(base) ((base)->SBMR1) +#define SRC_SRSR_REG(base) ((base)->SRSR) +#define SRC_SISR_REG(base) ((base)->SISR) +#define SRC_SIMR_REG(base) ((base)->SIMR) +#define SRC_SBMR2_REG(base) ((base)->SBMR2) +#define SRC_GPR1_REG(base) ((base)->GPR1) +#define SRC_GPR2_REG(base) ((base)->GPR2) +#define SRC_GPR3_REG(base) ((base)->GPR3) +#define SRC_GPR4_REG(base) ((base)->GPR4) +#define SRC_GPR5_REG(base) ((base)->GPR5) +#define SRC_GPR6_REG(base) ((base)->GPR6) +#define SRC_GPR7_REG(base) ((base)->GPR7) +#define SRC_GPR8_REG(base) ((base)->GPR8) +#define SRC_GPR9_REG(base) ((base)->GPR9) +#define SRC_GPR10_REG(base) ((base)->GPR10) +#define SRC_DDRC_RCR_REG(base) ((base)->DDRC_RCR) + +/*! + * @} + */ /* end of group SRC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- SRC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup SRC_Register_Masks SRC Register Masks + * @{ + */ + +/* SCR Bit Fields */ +#define SRC_SCR_MASK_TEMPSENSE_RESET_MASK 0xF0u +#define SRC_SCR_MASK_TEMPSENSE_RESET_SHIFT 4 +#define SRC_SCR_MASK_TEMPSENSE_RESET(x) (((uint32_t)(((uint32_t)(x))<HW_ANADIG_TEMPSENSE0) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_SET) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_CLR) +#define TEMPMON_HW_ANADIG_TEMPSENSE0_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE0_TOG) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_REG(base) ((base)->HW_ANADIG_TEMPSENSE1) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_SET) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_CLR) +#define TEMPMON_HW_ANADIG_TEMPSENSE1_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE1_TOG) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_SET_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_SET) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_CLR_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_CLR) +#define TEMPMON_HW_ANADIG_TEMPSENSE_TRIM_TOG_REG(base) ((base)->HW_ANADIG_TEMPSENSE_TRIM_TOG) + +/*! + * @} + */ /* end of group TEMPMON_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- TEMPMON Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup TEMPMON_Register_Masks TEMPMON Register Masks + * @{ + */ + +/* HW_ANADIG_TEMPSENSE0 Bit Fields */ +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_MASK 0x1FFu +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE_SHIFT 0 +#define TEMPMON_HW_ANADIG_TEMPSENSE0_LOW_ALARM_VALUE(x) (((uint32_t)(((uint32_t)(x))<URXD) +#define UART_UTXD_REG(base) ((base)->UTXD) +#define UART_UCR1_REG(base) ((base)->UCR1) +#define UART_UCR2_REG(base) ((base)->UCR2) +#define UART_UCR3_REG(base) ((base)->UCR3) +#define UART_UCR4_REG(base) ((base)->UCR4) +#define UART_UFCR_REG(base) ((base)->UFCR) +#define UART_USR1_REG(base) ((base)->USR1) +#define UART_USR2_REG(base) ((base)->USR2) +#define UART_UESC_REG(base) ((base)->UESC) +#define UART_UTIM_REG(base) ((base)->UTIM) +#define UART_UBIR_REG(base) ((base)->UBIR) +#define UART_UBMR_REG(base) ((base)->UBMR) +#define UART_UBRC_REG(base) ((base)->UBRC) +#define UART_ONEMS_REG(base) ((base)->ONEMS) +#define UART_UTS_REG(base) ((base)->UTS) +#define UART_UMCR_REG(base) ((base)->UMCR) + +/*! + * @} + */ /* end of group UART_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- UART Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup UART_Register_Masks UART Register Masks + * @{ + */ + +/* URXD Bit Fields */ +#define UART_URXD_RX_DATA_MASK 0xFFu +#define UART_URXD_RX_DATA_SHIFT 0 +#define UART_URXD_RX_DATA(x) (((uint32_t)(((uint32_t)(x))<ID) +#define USB_HWGENERAL_REG(base) ((base)->HWGENERAL) +#define USB_HWHOST_REG(base) ((base)->HWHOST) +#define USB_HWDEVICE_REG(base) ((base)->HWDEVICE) +#define USB_HWTXBUF_REG(base) ((base)->HWTXBUF) +#define USB_HWRXBUF_REG(base) ((base)->HWRXBUF) +#define USB_GPTIMER0LD_REG(base) ((base)->GPTIMER0LD) +#define USB_GPTIMER0CTRL_REG(base) ((base)->GPTIMER0CTRL) +#define USB_GPTIMER1LD_REG(base) ((base)->GPTIMER1LD) +#define USB_GPTIMER1CTRL_REG(base) ((base)->GPTIMER1CTRL) +#define USB_SBUSCFG_REG(base) ((base)->SBUSCFG) +#define USB_CAPLENGTH_REG(base) ((base)->CAPLENGTH) +#define USB_HCIVERSION_REG(base) ((base)->HCIVERSION) +#define USB_HCSPARAMS_REG(base) ((base)->HCSPARAMS) +#define USB_HCCPARAMS_REG(base) ((base)->HCCPARAMS) +#define USB_DCIVERSION_REG(base) ((base)->DCIVERSION) +#define USB_DCCPARAMS_REG(base) ((base)->DCCPARAMS) +#define USB_USBCMD_REG(base) ((base)->USBCMD) +#define USB_USBSTS_REG(base) ((base)->USBSTS) +#define USB_USBINTR_REG(base) ((base)->USBINTR) +#define USB_FRINDEX_REG(base) ((base)->FRINDEX) +#define USB_PERIODICLISTBASE_REG(base) ((base)->PERIODICLISTBASE) +#define USB_DEVICEADDR_REG(base) ((base)->DEVICEADDR) +#define USB_ASYNCLISTADDR_REG(base) ((base)->ASYNCLISTADDR.ASYNCLISTADDR) +#define USB_ENDPTLISTADDR_REG(base) ((base)->ENDPTLISTADDR.ENDPTLISTADDR) +#define USB_BURSTSIZE_REG(base) ((base)->BURSTSIZE) +#define USB_TXFILLTUNING_REG(base) ((base)->TXFILLTUNING) +#define USB_ENDPTNAK_REG(base) ((base)->ENDPTNAK) +#define USB_ENDPTNAKEN_REG(base) ((base)->ENDPTNAKEN) +#define USB_CONFIGFLAG_REG(base) ((base)->CONFIGFLAG) +#define USB_PORTSC1_REG(base) ((base)->PORTSC1) +#define USB_OTGSC_REG(base) ((base)->OTGSC) +#define USB_USBMODE_REG(base) ((base)->USBMODE) +#define USB_ENDPTSETUPSTAT_REG(base) ((base)->ENDPTSETUPSTAT) +#define USB_ENDPTPRIME_REG(base) ((base)->ENDPTPRIME) +#define USB_ENDPTFLUSH_REG(base) ((base)->ENDPTFLUSH) +#define USB_ENDPTSTAT_REG(base) ((base)->ENDPTSTAT) +#define USB_ENDPTCOMPLETE_REG(base) ((base)->ENDPTCOMPLETE) +#define USB_ENDPTCTRL0_REG(base) ((base)->ENDPTCTRL0) +#define USB_ENDPTCTRL1_REG(base) ((base)->ENDPTCTRL1) +#define USB_ENDPTCTRL2_REG(base) ((base)->ENDPTCTRL2) +#define USB_ENDPTCTRL3_REG(base) ((base)->ENDPTCTRL3) +#define USB_ENDPTCTRL4_REG(base) ((base)->ENDPTCTRL4) +#define USB_ENDPTCTRL5_REG(base) ((base)->ENDPTCTRL5) +#define USB_ENDPTCTRL6_REG(base) ((base)->ENDPTCTRL6) +#define USB_ENDPTCTRL7_REG(base) ((base)->ENDPTCTRL7) + +/*! + * @} + */ /* end of group USB_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- USB Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USB_Register_Masks USB Register Masks + * @{ + */ + +/* ID Bit Fields */ +#define USB_ID_ID_MASK 0x3Fu +#define USB_ID_ID_SHIFT 0 +#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x))<OTG1_CTRL1) +#define USBNC_OTG1_CTRL2_REG(base) ((base)->OTG1_CTRL2) +#define USBNC_OTG1_PHY_CFG1_REG(base) ((base)->OTG1_PHY_CFG1) +#define USBNC_OTG1_PHY_CFG2_REG(base) ((base)->OTG1_PHY_CFG2) +#define USBNC_OTG1_PHY_STATUS_REG(base) ((base)->OTG1_PHY_STATUS) +#define USBNC_ADP_CFG1_REG(base) ((base)->ADP_CFG1) +#define USBNC_ADP_CFG2_REG(base) ((base)->ADP_CFG2) +#define USBNC_ADP_STATUS_REG(base) ((base)->ADP_STATUS) +#define USBNC_OTG2_CTRL1_REG(base) ((base)->OTG2_CTRL1) +#define USBNC_OTG2_CTRL2_REG(base) ((base)->OTG2_CTRL2) +#define USBNC_OTG2_PHY_CFG1_REG(base) ((base)->OTG2_PHY_CFG1) +#define USBNC_OTG2_PHY_CFG2_REG(base) ((base)->OTG2_PHY_CFG2) +#define USBNC_OTG2_PHY_STATUS_REG(base) ((base)->OTG2_PHY_STATUS) +#define USBNC_HSIC_CTRL1_REG(base) ((base)->HSIC_CTRL1) +#define USBNC_HSIC_CTRL2_REG(base) ((base)->HSIC_CTRL2) +#define USBNC_UH_HSICPHY_CFG1_REG(base) ((base)->UH_HSICPHY_CFG1) + +/*! + * @} + */ /* end of group USBNC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- USBNC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup USBNC_Register_Masks USBNC Register Masks + * @{ + */ + +/* OTG1_CTRL1 Bit Fields */ +#define USBNC_OTG1_CTRL1_OVER_CUR_DIS_MASK 0x80u +#define USBNC_OTG1_CTRL1_OVER_CUR_DIS_SHIFT 7 +#define USBNC_OTG1_CTRL1_OVER_CUR_POL_MASK 0x100u +#define USBNC_OTG1_CTRL1_OVER_CUR_POL_SHIFT 8 +#define USBNC_OTG1_CTRL1_PWR_POL_MASK 0x200u +#define USBNC_OTG1_CTRL1_PWR_POL_SHIFT 9 +#define USBNC_OTG1_CTRL1_WIE_MASK 0x400u +#define USBNC_OTG1_CTRL1_WIE_SHIFT 10 +#define USBNC_OTG1_CTRL1_WKUP_SW_EN_MASK 0x4000u +#define USBNC_OTG1_CTRL1_WKUP_SW_EN_SHIFT 14 +#define USBNC_OTG1_CTRL1_WKUP_SW_MASK 0x8000u +#define USBNC_OTG1_CTRL1_WKUP_SW_SHIFT 15 +#define USBNC_OTG1_CTRL1_WKUP_ID_EN_MASK 0x10000u +#define USBNC_OTG1_CTRL1_WKUP_ID_EN_SHIFT 16 +#define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_MASK 0x20000u +#define USBNC_OTG1_CTRL1_WKUP_VBUS_EN_SHIFT 17 +#define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_MASK 0x20000000u +#define USBNC_OTG1_CTRL1_WKUP_DPDM_EN_SHIFT 29 +#define USBNC_OTG1_CTRL1_WIR_MASK 0x80000000u +#define USBNC_OTG1_CTRL1_WIR_SHIFT 31 +/* OTG1_CTRL2 Bit Fields */ +#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_MASK 0x3u +#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL_SHIFT 0 +#define USBNC_OTG1_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x))<WCR) +#define WDOG_WSR_REG(base) ((base)->WSR) +#define WDOG_WRSR_REG(base) ((base)->WRSR) +#define WDOG_WICR_REG(base) ((base)->WICR) +#define WDOG_WMCR_REG(base) ((base)->WMCR) + +/*! + * @} + */ /* end of group WDOG_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- WDOG Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup WDOG_Register_Masks WDOG Register Masks + * @{ + */ + +/* WCR Bit Fields */ +#define WDOG_WCR_WDZST_MASK 0x1u +#define WDOG_WCR_WDZST_SHIFT 0 +#define WDOG_WCR_WDBG_MASK 0x2u +#define WDOG_WCR_WDBG_SHIFT 1 +#define WDOG_WCR_WDE_MASK 0x4u +#define WDOG_WCR_WDE_SHIFT 2 +#define WDOG_WCR_WDT_MASK 0x8u +#define WDOG_WCR_WDT_SHIFT 3 +#define WDOG_WCR_SRS_MASK 0x10u +#define WDOG_WCR_SRS_SHIFT 4 +#define WDOG_WCR_WDA_MASK 0x20u +#define WDOG_WCR_WDA_SHIFT 5 +#define WDOG_WCR_SRE_MASK 0x40u +#define WDOG_WCR_SRE_SHIFT 6 +#define WDOG_WCR_WDW_MASK 0x80u +#define WDOG_WCR_WDW_SHIFT 7 +#define WDOG_WCR_WT_MASK 0xFF00u +#define WDOG_WCR_WT_SHIFT 8 +#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x))<CTRL_24M) +#define XTALOSC_CTRL_24M_SET_REG(base) ((base)->CTRL_24M_SET) +#define XTALOSC_CTRL_24M_CLR_REG(base) ((base)->CTRL_24M_CLR) +#define XTALOSC_CTRL_24M_TOG_REG(base) ((base)->CTRL_24M_TOG) +#define XTALOSC_RCOSC_CONFIG0_REG(base) ((base)->RCOSC_CONFIG0) +#define XTALOSC_RCOSC_CONFIG0_SET_REG(base) ((base)->RCOSC_CONFIG0_SET) +#define XTALOSC_RCOSC_CONFIG0_CLR_REG(base) ((base)->RCOSC_CONFIG0_CLR) +#define XTALOSC_RCOSC_CONFIG0_TOG_REG(base) ((base)->RCOSC_CONFIG0_TOG) +#define XTALOSC_RCOSC_CONFIG1_REG(base) ((base)->RCOSC_CONFIG1) +#define XTALOSC_RCOSC_CONFIG1_SET_REG(base) ((base)->RCOSC_CONFIG1_SET) +#define XTALOSC_RCOSC_CONFIG1_CLR_REG(base) ((base)->RCOSC_CONFIG1_CLR) +#define XTALOSC_RCOSC_CONFIG1_TOG_REG(base) ((base)->RCOSC_CONFIG1_TOG) +#define XTALOSC_RCOSC_CONFIG2_REG(base) ((base)->RCOSC_CONFIG2) +#define XTALOSC_RCOSC_CONFIG2_SET_REG(base) ((base)->RCOSC_CONFIG2_SET) +#define XTALOSC_RCOSC_CONFIG2_CLR_REG(base) ((base)->RCOSC_CONFIG2_CLR) +#define XTALOSC_RCOSC_CONFIG2_TOG_REG(base) ((base)->RCOSC_CONFIG2_TOG) +#define XTALOSC_OSC_32K_REG(base) ((base)->OSC_32K) +#define XTALOSC_OSC_32K_SET_REG(base) ((base)->OSC_32K_SET) +#define XTALOSC_OSC_32K_CLR_REG(base) ((base)->OSC_32K_CLR) +#define XTALOSC_OSC_32K_TOG_REG(base) ((base)->OSC_32K_TOG) + +/*! + * @} + */ /* end of group XTALOSC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- XTALOSC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup XTALOSC_Register_Masks XTALOSC Register Masks + * @{ + */ + +/* CTRL_24M Bit Fields */ +#define XTALOSC_CTRL_24M_XTAL_24M_PWD_MASK 0x1u +#define XTALOSC_CTRL_24M_XTAL_24M_PWD_SHIFT 0 +#define XTALOSC_CTRL_24M_XTAL_24M_EN_MASK 0x2u +#define XTALOSC_CTRL_24M_XTAL_24M_EN_SHIFT 1 +#define XTALOSC_CTRL_24M_OSC_XTALOK_MASK 0x4u +#define XTALOSC_CTRL_24M_OSC_XTALOK_SHIFT 2 +#define XTALOSC_CTRL_24M_OSC_XTALOK_EN_MASK 0x8u +#define XTALOSC_CTRL_24M_OSC_XTALOK_EN_SHIFT 3 +#define XTALOSC_CTRL_24M_CLKGATE_CTRL_MASK 0x10u +#define XTALOSC_CTRL_24M_CLKGATE_CTRL_SHIFT 4 +#define XTALOSC_CTRL_24M_CLKGATE_DELAY_MASK 0xE0u +#define XTALOSC_CTRL_24M_CLKGATE_DELAY_SHIFT 5 +#define XTALOSC_CTRL_24M_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x))<DS_ADDR) +#define uSDHC_BLK_ATT_REG(base) ((base)->BLK_ATT) +#define uSDHC_CMD_ARG_REG(base) ((base)->CMD_ARG) +#define uSDHC_CMD_XFR_TYP_REG(base) ((base)->CMD_XFR_TYP) +#define uSDHC_CMD_RSP0_REG(base) ((base)->CMD_RSP0) +#define uSDHC_CMD_RSP1_REG(base) ((base)->CMD_RSP1) +#define uSDHC_CMD_RSP2_REG(base) ((base)->CMD_RSP2) +#define uSDHC_CMD_RSP3_REG(base) ((base)->CMD_RSP3) +#define uSDHC_DATA_BUFF_ACC_PORT_REG(base) ((base)->DATA_BUFF_ACC_PORT) +#define uSDHC_PRES_STATE_REG(base) ((base)->PRES_STATE) +#define uSDHC_PROT_CTRL_REG(base) ((base)->PROT_CTRL) +#define uSDHC_SYS_CTRL_REG(base) ((base)->SYS_CTRL) +#define uSDHC_INT_STATUS_REG(base) ((base)->INT_STATUS) +#define uSDHC_INT_STATUS_EN_REG(base) ((base)->INT_STATUS_EN) +#define uSDHC_INT_SIGNAL_EN_REG(base) ((base)->INT_SIGNAL_EN) +#define uSDHC_AUTOCMD12_ERR_STATUS_REG(base) ((base)->AUTOCMD12_ERR_STATUS) +#define uSDHC_HOST_CTRL_CAP_REG(base) ((base)->HOST_CTRL_CAP) +#define uSDHC_WTMK_LVL_REG(base) ((base)->WTMK_LVL) +#define uSDHC_MIX_CTRL_REG(base) ((base)->MIX_CTRL) +#define uSDHC_FORCE_EVENT_REG(base) ((base)->FORCE_EVENT) +#define uSDHC_ADMA_ERR_STATUS_REG(base) ((base)->ADMA_ERR_STATUS) +#define uSDHC_ADMA_SYS_ADDR_REG(base) ((base)->ADMA_SYS_ADDR) +#define uSDHC_DLL_CTRL_REG(base) ((base)->DLL_CTRL) +#define uSDHC_DLL_STATUS_REG(base) ((base)->DLL_STATUS) +#define uSDHC_CLK_TUNE_CTRL_STATUS_REG(base) ((base)->CLK_TUNE_CTRL_STATUS) +#define uSDHC_STROBE_DLL_CTRL_REG(base) ((base)->STROBE_DLL_CTRL) +#define uSDHC_STROBE_DLL_STATUS_REG(base) ((base)->STROBE_DLL_STATUS) +#define uSDHC_VEND_SPEC_REG(base) ((base)->VEND_SPEC) +#define uSDHC_MMC_BOOT_REG(base) ((base)->MMC_BOOT) +#define uSDHC_VEND_SPEC2_REG(base) ((base)->VEND_SPEC2) +#define uSDHC_TUNING_CTRL_REG(base) ((base)->TUNING_CTRL) + +/*! + * @} + */ /* end of group uSDHC_Register_Accessor_Macros */ +/* ---------------------------------------------------------------------------- + -- uSDHC Register Masks + ---------------------------------------------------------------------------- */ + +/*! + * @addtogroup uSDHC_Register_Masks uSDHC Register Masks + * @{ + */ + +/* DS_ADDR Bit Fields */ +#define uSDHC_DS_ADDR_DS_ADDR_MASK 0xFFFFFFFCu +#define uSDHC_DS_ADDR_DS_ADDR_SHIFT 2 +#define uSDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x))<sampleRate); + + /* Enable ADC Build-in voltage level shifter */ + if (initConfig->levelShifterEnable) + ADC_LevelShifterEnable(base); + else + ADC_LevelShifterDisable(base); + + /* Wait until ADC module power-up completely. */ + while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_Deinit + * Description : This function reset ADC module register content to its + * default value. + * + *END**************************************************************************/ +void ADC_Deinit(ADC_Type* base) +{ + /* Stop all continues conversions */ + ADC_SetConvertCmd(base, adcLogicChA, false); + ADC_SetConvertCmd(base, adcLogicChB, false); + ADC_SetConvertCmd(base, adcLogicChC, false); + ADC_SetConvertCmd(base, adcLogicChD, false); + + /* Reset ADC Module Register content to default value */ + ADC_CH_A_CFG1_REG(base) = 0x0; + ADC_CH_A_CFG2_REG(base) = ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; + ADC_CH_B_CFG1_REG(base) = 0x0; + ADC_CH_B_CFG2_REG(base) = ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; + ADC_CH_C_CFG1_REG(base) = 0x0; + ADC_CH_C_CFG2_REG(base) = ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; + ADC_CH_D_CFG1_REG(base) = 0x0; + ADC_CH_D_CFG2_REG(base) = ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; + ADC_CH_SW_CFG_REG(base) = 0x0; + ADC_TIMER_UNIT_REG(base) = 0x0; + ADC_DMA_FIFO_REG(base) = ADC_DMA_FIFO_DMA_WM_LVL(0xF); + ADC_INT_SIG_EN_REG(base) = 0x0; + ADC_INT_EN_REG(base) = 0x0; + ADC_INT_STATUS_REG(base) = 0x0; + ADC_ADC_CFG_REG(base) = ADC_ADC_CFG_ADC_EN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetSampleRate + * Description : This function is used to set ADC module sample rate. + * + *END**************************************************************************/ +void ADC_SetSampleRate(ADC_Type* base, uint32_t sampleRate) +{ + uint8_t preDiv; + uint8_t coreTimerUnit; + + assert((sampleRate <= 1000000) && (sampleRate >= 1563)); + + for (preDiv = 0 ; preDiv < 6; preDiv++) + { + uint32_t divider = 24000000 >> (2 + preDiv); + divider /= sampleRate * 6; + if(divider <= 32) + { + coreTimerUnit = divider - 1; + break; + } + } + + if (0x6 == preDiv) + { + preDiv = 0x5; + coreTimerUnit = 0x1F; + } + + ADC_TIMER_UNIT_REG(base) = 0x0; + ADC_TIMER_UNIT_REG(base) = ADC_TIMER_UNIT_PRE_DIV(preDiv) | ADC_TIMER_UNIT_CORE_TIMER_UNIT(coreTimerUnit); +} + +/******************************************************************************* + * ADC Low power control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetClockDownCmd + * Description : This function is used to stop all digital part power. + * + *END**************************************************************************/ +void ADC_SetClockDownCmd(ADC_Type* base, bool clockDown) +{ + if (clockDown) + ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_CLK_DOWN_MASK; + else + ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_CLK_DOWN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetPowerDownCmd + * Description : This function is used to power down ADC analogue core. + * Before entering into stop-mode, power down ADC analogue + * core first. + * + *END**************************************************************************/ +void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown) +{ + if (powerDown) + { + ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_PD_MASK; + /* Wait until power down action finish. */ + while((ADC_ADC_CFG_REG(base) & ADC_ADC_CFG_ADC_PD_OK_MASK)); + } + else + { + ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_PD_MASK; + } +} + +/******************************************************************************* + * ADC Convert Channel Initialization and Configuration functions. + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_LogicChInit + * Description : Initialize ADC Logic channel with initialization structure. + * + *END**************************************************************************/ +void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, const adc_logic_ch_init_config_t* chInitConfig) +{ + assert(chInitConfig); + + /* Select input channel */ + ADC_SelectInputCh(base, logicCh, chInitConfig->inputChannel); + + /* Set Continuous Convert Rate. */ + if (chInitConfig->coutinuousEnable) + ADC_SetConvertRate(base, logicCh, chInitConfig->convertRate); + + /* Set Hardware average Number. */ + if (chInitConfig->averageEnable) + { + ADC_SetAverageNum(base, logicCh, chInitConfig->averageNumber); + ADC_SetAverageCmd(base, logicCh, true); + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_LogicChDeinit + * Description : Reset target ADC logic channel registers to default value. + * + *END**************************************************************************/ +void ADC_LogicChDeinit(ADC_Type* base, uint8_t logicCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) = 0x0; + ADC_CH_A_CFG2_REG(base) = 0x8000; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) = 0x0; + ADC_CH_B_CFG2_REG(base) = 0x8000; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) = 0x0; + ADC_CH_C_CFG2_REG(base) = 0x8000; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) = 0x0; + ADC_CH_D_CFG2_REG(base) = 0x8000; + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) = 0x0; + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SelectInputCh + * Description : Select input channel for target logic channel. + * + *END**************************************************************************/ +void ADC_SelectInputCh(ADC_Type* base, uint8_t logicCh, uint8_t inputCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SEL_MASK) | \ + ADC_CH_A_CFG1_CHA_SEL(inputCh); + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SEL_MASK) | \ + ADC_CH_B_CFG1_CHB_SEL(inputCh); + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SEL_MASK) | \ + ADC_CH_C_CFG1_CHC_SEL(inputCh); + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SEL_MASK) | \ + ADC_CH_D_CFG1_CHD_SEL(inputCh); + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_SEL_MASK) | \ + ADC_CH_SW_CFG_CH_SW_SEL(inputCh); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertRate + * Description : Set ADC conversion rate of target logic channel. + * + *END**************************************************************************/ +void ADC_SetConvertRate(ADC_Type* base, uint8_t logicCh, uint32_t convertRate) +{ + assert(logicCh <= adcLogicChD); + + /* Calculate ADC module's current sample rate */ + uint32_t sampleRate = (4000000 >> (2 + (ADC_TIMER_UNIT_REG(base) >> ADC_TIMER_UNIT_PRE_DIV_SHIFT))) / \ + ((ADC_TIMER_UNIT_REG(base) & ADC_TIMER_UNIT_CORE_TIMER_UNIT_MASK) + 1); + + uint32_t convertDiv = sampleRate / convertRate; + assert((sampleRate / convertRate) <= ADC_CH_A_CFG1_CHA_TIMER_MASK); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_TIMER_MASK) | \ + ADC_CH_A_CFG1_CHA_TIMER(convertDiv); + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_TIMER_MASK) | \ + ADC_CH_B_CFG1_CHB_TIMER(convertDiv); + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_TIMER_MASK) | \ + ADC_CH_C_CFG1_CHC_TIMER(convertDiv); + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_TIMER_MASK) | \ + ADC_CH_D_CFG1_CHD_TIMER(convertDiv); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAverageCmd + * Description : Set work state of hardware average feature of target + * logic channel. + * + *END**************************************************************************/ +void ADC_SetAverageCmd(ADC_Type* base, uint8_t logicCh, bool enable) +{ + assert(logicCh <= adcLogicChSW); + + if (enable) + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_AVG_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_AVG_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_AVG_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_AVG_EN_MASK; + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK; + break; + default: + break; + } + } + else + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_AVG_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_AVG_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_AVG_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_AVG_EN_MASK; + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) &= ~ADC_CH_SW_CFG_CH_SW_AVG_EN_MASK; + break; + default: + break; + } + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAverageNum + * Description : Set hardware average number of target logic channel. + * + *END**************************************************************************/ +void ADC_SetAverageNum(ADC_Type* base, uint8_t logicCh, uint8_t avgNum) +{ + assert(logicCh <= adcLogicChSW); + assert(avgNum <= adcAvgNum32); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_AVG_NUMBER_MASK) | \ + ADC_CH_A_CFG2_CHA_AVG_NUMBER(avgNum); + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_AVG_NUMBER_MASK) | \ + ADC_CH_B_CFG2_CHB_AVG_NUMBER(avgNum); + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_AVG_NUMBER_MASK) | \ + ADC_CH_C_CFG2_CHC_AVG_NUMBER(avgNum); + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_AVG_NUMBER_MASK) | \ + ADC_CH_D_CFG2_CHD_AVG_NUMBER(avgNum); + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) = (ADC_CH_SW_CFG_REG(base) & ~ADC_CH_SW_CFG_CH_SW_AVG_NUMBER_MASK) | \ + ADC_CH_SW_CFG_CH_SW_AVG_NUMBER(avgNum); + break; + default: + break; + } +} + +/******************************************************************************* + * ADC Conversion Control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetConvertCmd + * Description : Set continuous convert work mode of target logic channel. + * + *END**************************************************************************/ +void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable) +{ + assert(logicCh <= adcLogicChD); + + if (enable) + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) = (ADC_CH_A_CFG1_REG(base) & ~ADC_CH_A_CFG1_CHA_SINGLE_MASK) | + ADC_CH_A_CFG1_CHA_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) = (ADC_CH_B_CFG1_REG(base) & ~ADC_CH_B_CFG1_CHB_SINGLE_MASK) | + ADC_CH_B_CFG1_CHB_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) = (ADC_CH_C_CFG1_REG(base) & ~ADC_CH_C_CFG1_CHC_SINGLE_MASK) | + ADC_CH_C_CFG1_CHC_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) = (ADC_CH_D_CFG1_REG(base) & ~ADC_CH_D_CFG1_CHD_SINGLE_MASK) | + ADC_CH_D_CFG1_CHD_EN_MASK; + break; + default: + break; + } + } + else + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK; + break; + default: + break; + } + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_TriggerSingleConvert + * Description : Trigger single time convert on the target logic channel. + * + *END**************************************************************************/ +void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) |= ADC_CH_A_CFG1_CHA_SINGLE_MASK | ADC_CH_A_CFG1_CHA_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) |= ADC_CH_B_CFG1_CHB_SINGLE_MASK | ADC_CH_B_CFG1_CHB_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) |= ADC_CH_C_CFG1_CHC_SINGLE_MASK | ADC_CH_C_CFG1_CHC_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) |= ADC_CH_D_CFG1_CHD_SINGLE_MASK | ADC_CH_D_CFG1_CHD_EN_MASK; + break; + case adcLogicChSW: + ADC_CH_SW_CFG_REG(base) |= ADC_CH_SW_CFG_START_CONV_MASK; + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_StopConvert + * Description : Stop current convert on the target logic channel. + * + *END**************************************************************************/ +void ADC_StopConvert(ADC_Type* base, uint8_t logicCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG1_REG(base) &= ~ADC_CH_A_CFG1_CHA_EN_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG1_REG(base) &= ~ADC_CH_B_CFG1_CHB_EN_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG1_REG(base) &= ~ADC_CH_C_CFG1_CHC_EN_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG1_REG(base) &= ~ADC_CH_D_CFG1_CHD_EN_MASK; + break; + case adcLogicChSW: + /* Wait until ADC conversion finish. */ + while (ADC_CH_SW_CFG_REG(base) & ADC_CH_SW_CFG_START_CONV_MASK); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_GetConvertResult + * Description : Get 12-bit length right aligned convert result. + * + *END**************************************************************************/ +uint16_t ADC_GetConvertResult(ADC_Type* base, uint8_t logicCh) +{ + assert(logicCh <= adcLogicChSW); + + switch (logicCh) + { + case adcLogicChA: + return ADC_CHA_B_CNV_RSLT_REG(base) & ADC_CHA_B_CNV_RSLT_CHA_CNV_RSLT_MASK; + case adcLogicChB: + return ADC_CHA_B_CNV_RSLT_REG(base) >> ADC_CHA_B_CNV_RSLT_CHB_CNV_RSLT_SHIFT; + case adcLogicChC: + return ADC_CHC_D_CNV_RSLT_REG(base) & ADC_CHC_D_CNV_RSLT_CHC_CNV_RSLT_MASK; + case adcLogicChD: + return ADC_CHC_D_CNV_RSLT_REG(base) >> ADC_CHC_D_CNV_RSLT_CHD_CNV_RSLT_SHIFT; + case adcLogicChSW: + return ADC_CH_SW_CNV_RSLT_REG(base) & ADC_CH_SW_CNV_RSLT_CH_SW_CNV_RSLT_MASK; + default: + return 0; + } +} + +/******************************************************************************* + * ADC Comparer Control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCmpMode + * Description : Set the work mode of ADC module build-in comparer on target + * logic channel. + * + *END**************************************************************************/ +void ADC_SetCmpMode(ADC_Type* base, uint8_t logicCh, uint8_t cmpMode) +{ + assert(logicCh <= adcLogicChD); + assert(cmpMode <= adcCmpModeOutOffInterval); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_CMP_MODE_MASK) | \ + ADC_CH_A_CFG2_CHA_CMP_MODE(cmpMode); + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_CMP_MODE_MASK) | \ + ADC_CH_B_CFG2_CHB_CMP_MODE(cmpMode); + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_CMP_MODE_MASK) | \ + ADC_CH_C_CFG2_CHC_CMP_MODE(cmpMode); + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_CMP_MODE_MASK) | \ + ADC_CH_D_CFG2_CHD_CMP_MODE(cmpMode); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCmpHighThres + * Description : Set ADC module build-in comparer high threshold on target + * logic channel. + * + *END**************************************************************************/ +void ADC_SetCmpHighThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold) +{ + assert(logicCh <= adcLogicChD); + assert(threshold <= 0xFFF); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_HIGH_THRES_MASK) | \ + ADC_CH_A_CFG2_CHA_HIGH_THRES(threshold); + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_HIGH_THRES_MASK) | \ + ADC_CH_B_CFG2_CHB_HIGH_THRES(threshold); + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_HIGH_THRES_MASK) | \ + ADC_CH_C_CFG2_CHC_HIGH_THRES(threshold); + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_HIGH_THRES_MASK) | \ + ADC_CH_D_CFG2_CHD_HIGH_THRES(threshold); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetCmpLowThres + * Description : Set ADC module build-in comparer low threshold on target + * logic channel. + * + *END**************************************************************************/ +void ADC_SetCmpLowThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold) +{ + assert(logicCh <= adcLogicChD); + assert(threshold <= 0xFFF); + + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) = (ADC_CH_A_CFG2_REG(base) & ~ADC_CH_A_CFG2_CHA_LOW_THRES_MASK) | \ + ADC_CH_A_CFG2_CHA_LOW_THRES(threshold); + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) = (ADC_CH_B_CFG2_REG(base) & ~ADC_CH_B_CFG2_CHB_LOW_THRES_MASK) | \ + ADC_CH_B_CFG2_CHB_LOW_THRES(threshold); + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) = (ADC_CH_C_CFG2_REG(base) & ~ADC_CH_C_CFG2_CHC_LOW_THRES_MASK) | \ + ADC_CH_B_CFG2_CHB_LOW_THRES(threshold); + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) = (ADC_CH_D_CFG2_REG(base) & ~ADC_CH_D_CFG2_CHD_LOW_THRES_MASK) | \ + ADC_CH_D_CFG2_CHD_LOW_THRES(threshold); + break; + default: + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetAutoDisableCmd + * Description : Set the working mode of ADC module auto disable feature on + * target logic channel. + * + *END**************************************************************************/ +void ADC_SetAutoDisableCmd(ADC_Type* base, uint8_t logicCh, bool enable) +{ + assert(logicCh <= adcLogicChD); + + if (enable) + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) |= ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) |= ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) |= ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) |= ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; + break; + default: + break; + } + } + else + { + switch (logicCh) + { + case adcLogicChA: + ADC_CH_A_CFG2_REG(base) &= ~ADC_CH_A_CFG2_CHA_AUTO_DIS_MASK; + break; + case adcLogicChB: + ADC_CH_B_CFG2_REG(base) &= ~ADC_CH_B_CFG2_CHB_AUTO_DIS_MASK; + break; + case adcLogicChC: + ADC_CH_C_CFG2_REG(base) &= ~ADC_CH_C_CFG2_CHC_AUTO_DIS_MASK; + break; + case adcLogicChD: + ADC_CH_D_CFG2_REG(base) &= ~ADC_CH_D_CFG2_CHD_AUTO_DIS_MASK; + break; + default: + break; + } + } +} + +/******************************************************************************* + * Interrupt and Flag control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetIntCmd + * Description : Enables or disables ADC interrupt requests. + * + *END**************************************************************************/ +void ADC_SetIntCmd(ADC_Type* base, uint32_t intSource, bool enable) +{ + if (enable) + ADC_INT_EN_REG(base) |= intSource; + else + ADC_INT_EN_REG(base) &= ~intSource; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetIntSigCmd + * Description : Enables or disables ADC interrupt flag when interrupt + * condition met. + * + *END**************************************************************************/ +void ADC_SetIntSigCmd(ADC_Type* base, uint32_t intSignal, bool enable) +{ + if (enable) + ADC_INT_SIG_EN_REG(base) |= intSignal; + else + ADC_INT_SIG_EN_REG(base) &= ~intSignal; +} + +/******************************************************************************* + * DMA & FIFO control functions. + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetDmaReset + * Description : Set the reset state of ADC internal DMA part. + * + *END**************************************************************************/ +void ADC_SetDmaReset(ADC_Type* base, bool active) +{ + if (active) + ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_RST_MASK; + else + ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_RST_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetDmaCmd + * Description : Set the work mode of ADC DMA part. + * + *END**************************************************************************/ +void ADC_SetDmaCmd(ADC_Type* base, bool enable) +{ + if (enable) + ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_EN_MASK; + else + ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_EN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ADC_SetDmaFifoCmd + * Description : Set the work mode of ADC DMA FIFO part. + * + *END**************************************************************************/ +void ADC_SetDmaFifoCmd(ADC_Type* base, bool enable) +{ + if (enable) + ADC_DMA_FIFO_REG(base) |= ADC_DMA_FIFO_DMA_FIFO_EN_MASK; + else + ADC_DMA_FIFO_REG(base) &= ~ADC_DMA_FIFO_DMA_FIFO_EN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX7D/drivers/adc_imx7d.h b/devices/MCIMX7D/drivers/adc_imx7d.h new file mode 100644 index 000000000..57882597e --- /dev/null +++ b/devices/MCIMX7D/drivers/adc_imx7d.h @@ -0,0 +1,555 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ADC_IMX7D_H__ +#define __ADC_IMX7D_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup adc_imx7d_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief ADC module initialization structure. */ +typedef struct _adc_init_config +{ + uint32_t sampleRate; /*!< The desired ADC sample rate.*/ + bool levelShifterEnable; /*!< The level shifter module configuration(Enable to power on ADC module).*/ +} adc_init_config_t; + +/*! @brief ADC logic channel initialization structure. */ +typedef struct _adc_logic_ch_init_config +{ + uint32_t convertRate; /*!< The continuous rate when continuous sample enabled.*/ + uint8_t inputChannel; /*!< The logic channel to be set.*/ + uint8_t averageNumber; /*!< The average number for hardware average function.*/ + bool coutinuousEnable; /*!< Continuous sample mode enable configuration.*/ + bool averageEnable; /*!< Hardware average enable configuration.*/ +} adc_logic_ch_init_config_t; + +/*! @brief ADC logic channel selection enumeration. */ +enum _adc_logic_ch_selection +{ + adcLogicChA = 0x0, /*!< ADC Logic Channel A.*/ + adcLogicChB = 0x1, /*!< ADC Logic Channel B.*/ + adcLogicChC = 0x2, /*!< ADC Logic Channel C.*/ + adcLogicChD = 0x3, /*!< ADC Logic Channel D.*/ + adcLogicChSW = 0x4, /*!< ADC Logic Channel Software.*/ +}; + +/*! @brief ADC hardware average number enumeration. */ +enum _adc_average_number +{ + adcAvgNum4 = 0x0, /*!< ADC Hardware Average Number is set to 4.*/ + adcAvgNum8 = 0x1, /*!< ADC Hardware Average Number is set to 8.*/ + adcAvgNum16 = 0x2, /*!< ADC Hardware Average Number is set to 16.*/ + adcAvgNum32 = 0x3, /*!< ADC Hardware Average Number is set to 32.*/ +}; + +/*! @brief ADC build-in comparer work mode configuration enumeration. */ +enum _adc_compare_mode +{ + adcCmpModeDisable = 0x0, /*!< ADC build-in comparator is disabled.*/ + adcCmpModeGreaterThanLow = 0x1, /*!< ADC build-in comparator is triggered when sample value greater than low threshold.*/ + adcCmpModeLessThanLow = 0x2, /*!< ADC build-in comparator is triggered when sample value less than low threshold.*/ + adcCmpModeInInterval = 0x3, /*!< ADC build-in comparator is triggered when sample value in interval between low and high threshold.*/ + adcCmpModeGreaterThanHigh = 0x5, /*!< ADC build-in comparator is triggered when sample value greater than high threshold.*/ + adcCmpModeLessThanHigh = 0x6, /*!< ADC build-in comparator is triggered when sample value less than high threshold.*/ + adcCmpModeOutOffInterval = 0x7, /*!< ADC build-in comparator is triggered when sample value out of interval between low and high threshold.*/ +}; + +/*! @brief This enumeration contains the settings for all of the ADC interrupt configurations. */ +enum _adc_interrupt +{ + adcIntLastFifoDataRead = ADC_INT_EN_LAST_FIFO_DATA_READ_EN_MASK, /*!< Last FIFO Data Read Interrupt Enable.*/ + adcIntConvertTimeoutChSw = ADC_INT_EN_SW_CH_COV_TO_INT_EN_MASK, /*!< Software Channel Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChD = ADC_INT_EN_CHD_COV_TO_INT_EN_MASK, /*!< Channel D Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChC = ADC_INT_EN_CHC_COV_TO_INT_EN_MASK, /*!< Channel C Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChB = ADC_INT_EN_CHB_COV_TO_INT_EN_MASK, /*!< Channel B Conversion Time Out Interrupt Enable.*/ + adcIntConvertTimeoutChA = ADC_INT_EN_CHA_COV_TO_INT_EN_MASK, /*!< Channel A Conversion Time Out Interrupt Enable.*/ + adcIntConvertChSw = ADC_INT_EN_SW_CH_COV_INT_EN_MASK, /*!< Software Channel Conversion Interrupt Enable.*/ + adcIntConvertChD = ADC_INT_EN_CHD_COV_INT_EN_MASK, /*!< Channel D Conversion Interrupt Enable.*/ + adcIntConvertChC = ADC_INT_EN_CHC_COV_INT_EN_MASK, /*!< Channel C Conversion Interrupt Enable.*/ + adcIntConvertChB = ADC_INT_EN_CHB_COV_INT_EN_MASK, /*!< Channel B Conversion Interrupt Enable.*/ + adcIntConvertChA = ADC_INT_EN_CHA_COV_INT_EN_MASK, /*!< Channel A Conversion Interrupt Enable.*/ + adcIntFifoOverrun = ADC_INT_EN_FIFO_OVERRUN_INT_EN_MASK, /*!< FIFO overrun Interrupt Enable.*/ + adcIntFifoUnderrun = ADC_INT_EN_FIFO_UNDERRUN_INT_EN_MASK, /*!< FIFO underrun Interrupt Enable.*/ + adcIntDmaReachWatermark = ADC_INT_EN_DMA_REACH_WM_INT_EN_MASK, /*!< DMA Reach Watermark Level Interrupt Enable.*/ + adcIntCmpChD = ADC_INT_EN_CHD_CMP_INT_EN_MASK, /*!< Channel D Compare Interrupt Enable.*/ + adcIntCmpChC = ADC_INT_EN_CHC_CMP_INT_EN_MASK, /*!< Channel C Compare Interrupt Enable.*/ + adcIntCmpChB = ADC_INT_EN_CHB_CMP_INT_EN_MASK, /*!< Channel B Compare Interrupt Enable.*/ + adcIntCmpChA = ADC_INT_EN_CHA_CMP_INT_EN_MASK, /*!< Channel A Compare Interrupt Enable.*/ +}; + +/*! @brief Flag for ADC interrupt/DMA status check or polling status. */ +enum _adc_status_flag +{ + adcStatusLastFifoDataRead = ADC_INT_STATUS_LAST_FIFO_DATA_READ_MASK, /*!< Last FIFO Data Read status flag.*/ + adcStatusConvertTimeoutChSw = ADC_INT_STATUS_SW_CH_COV_TO_MASK, /*!< Software Channel Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChD = ADC_INT_STATUS_CHD_COV_TO_MASK, /*!< Channel D Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChC = ADC_INT_STATUS_CHC_COV_TO_MASK, /*!< Channel C Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChB = ADC_INT_STATUS_CHB_COV_TO_MASK, /*!< Channel B Conversion Time Out status flag.*/ + adcStatusConvertTimeoutChA = ADC_INT_STATUS_CHA_COV_TO_MASK, /*!< Channel A Conversion Time Out status flag.*/ + adcStatusConvertChSw = ADC_INT_STATUS_SW_CH_COV_MASK, /*!< Software Channel Conversion status flag.*/ + adcStatusConvertChD = ADC_INT_STATUS_CHD_COV_MASK, /*!< Channel D Conversion status flag.*/ + adcStatusConvertChC = ADC_INT_STATUS_CHC_COV_MASK, /*!< Channel C Conversion status flag.*/ + adcStatusConvertChB = ADC_INT_STATUS_CHB_COV_MASK, /*!< Channel B Conversion status flag.*/ + adcStatusConvertChA = ADC_INT_STATUS_CHA_COV_MASK, /*!< Channel A Conversion status flag.*/ + adcStatusFifoOverrun = ADC_INT_STATUS_FIFO_OVERRUN_MASK, /*!< FIFO Overrun status flag.*/ + adcStatusFifoUnderrun = ADC_INT_STATUS_FIFO_UNDERRUN_MASK, /*!< FIFO Underrun status flag.*/ + adcStatusDmaReachWatermark = ADC_INT_STATUS_DMA_REACH_WM_MASK, /*!< DMA Reach Watermark Level status flag.*/ + adcStatusCmpChD = ADC_INT_STATUS_CHD_CMP_MASK, /*!< Channel D Compare status flag.*/ + adcStatusCmpChC = ADC_INT_STATUS_CHC_CMP_MASK, /*!< Channel C Compare status flag.*/ + adcStatusCmpChB = ADC_INT_STATUS_CHB_CMP_MASK, /*!< Channel B Compare status flag.*/ + adcStatusCmpChA = ADC_INT_STATUS_CHA_CMP_MASK, /*!< Channel A Compare status flag.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name ADC Module Initialization and Configuration functions. + * @{ + */ + +/*! + * @brief Initialize ADC to reset state and initialize with initialization structure. + * + * @param base ADC base pointer. + * @param initConfig ADC initialization structure. + */ +void ADC_Init(ADC_Type* base, const adc_init_config_t* initConfig); + +/*! + * @brief This function reset ADC module register content to its default value. + * + * @param base ADC base pointer. + */ +void ADC_Deinit(ADC_Type* base); + +/*! + * @brief This function Enable ADC module build-in Level Shifter. + * For i.MX 7Dual, Level Shifter should always be enabled. + * User can disable Level Shifter to save power. + * + * @param base ADC base pointer. + */ +static inline void ADC_LevelShifterEnable(ADC_Type* base) +{ + ADC_ADC_CFG_REG(base) |= ADC_ADC_CFG_ADC_EN_MASK; +} + +/*! + * @brief This function Disable ADC module build-in Level Shifter + * to save power. + * + * @param base ADC base pointer. + */ +static inline void ADC_LevelShifterDisable(ADC_Type* base) +{ + ADC_ADC_CFG_REG(base) &= ~ADC_ADC_CFG_ADC_EN_MASK; +} + +/*! + * @brief This function is used to set ADC module sample rate. + * + * @param base ADC base pointer. + * @param sampleRate Desired ADC sample rate. + */ +void ADC_SetSampleRate(ADC_Type* base, uint32_t sampleRate); + +/*@}*/ + +/*! + * @name ADC Low power control functions. + * @{ + */ + +/*! + * @brief This function is used to stop all digital part power. + * + * @param base ADC base pointer. + * @param clockDown Stop all ADC digital part or not. + * - true: Clock down. + * - false: Clock running. + */ +void ADC_SetClockDownCmd(ADC_Type* base, bool clockDown); + +/*! + * @brief This function is used to power down ADC analogue core. + * Before entering into stop-mode, power down ADC analogue core first. + * @param base ADC base pointer. + * @param powerDown Power down ADC analogue core or not. + * - true: Power down the ADC analogue core. + * - false: Do not power down the ADC analogue core. + */ +void ADC_SetPowerDownCmd(ADC_Type* base, bool powerDown); + +/*@}*/ + +/*! + * @name ADC Convert Channel Initialization and Configuration functions. + * @{ + */ + +/*! + * @brief Initialize ADC Logic channel with initialization structure. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param chInitConfig ADC logic channel initialization structure. + */ +void ADC_LogicChInit(ADC_Type* base, uint8_t logicCh, const adc_logic_ch_init_config_t* chInitConfig); + +/*! + * @brief Reset target ADC logic channel registers to default value. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + */ +void ADC_LogicChDeinit(ADC_Type* base, uint8_t logicCh); + +/*! + * @brief Select input channel for target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param inputCh Input channel selection for target logic channel(vary from 0 to 15). + */ +void ADC_SelectInputCh(ADC_Type* base, uint8_t logicCh, uint8_t inputCh); + +/*! + * @brief Set ADC conversion rate of target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param convertRate ADC conversion rate in Hz. + */ +void ADC_SetConvertRate(ADC_Type* base, uint8_t logicCh, uint32_t convertRate); + +/*! + * @brief Set work state of hardware average feature of target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param enable Enable/Disable hardware average + * - true: Enable hardware average of given logic channel. + * - false: Disable hardware average of given logic channel. + */ +void ADC_SetAverageCmd(ADC_Type* base, uint8_t logicCh, bool enable); + +/*! + * @brief Set hardware average number of target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param avgNum hardware average number(should select from @ref _adc_average_number enumeration). + */ +void ADC_SetAverageNum(ADC_Type* base, uint8_t logicCh, uint8_t avgNum); + +/*@}*/ + +/*! + * @name ADC Conversion Control functions. + * @{ + */ + +/*! + * @brief Set continuous convert work mode of target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param enable Enable/Disable continuous convertion. + * - true: Enable continuous convertion. + * - false: Disable continuous convertion. + */ +void ADC_SetConvertCmd(ADC_Type* base, uint8_t logicCh, bool enable); + +/*! + * @brief Trigger single time convert on target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + */ +void ADC_TriggerSingleConvert(ADC_Type* base, uint8_t logicCh); + +/*! + * @brief Stop current convert on target logic channel. + * For logic channel A ~ D, current conversion stops immediately. + * For Software channel, this function is waited until current conversion is finished. + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + */ +void ADC_StopConvert(ADC_Type* base, uint8_t logicCh); + +/*! + * @brief Get 12-bit length right aligned convert result. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @return convert result on target logic channel. + */ +uint16_t ADC_GetConvertResult(ADC_Type* base, uint8_t logicCh); + +/*@}*/ + +/*! + * @name ADC Comparer Control functions. + * @{ + */ + +/*! + * @brief Set the work mode of ADC module build-in comparer on target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param cmpMode Comparer work mode selected from @ref _adc_compare_mode enumeration. + */ +void ADC_SetCmpMode(ADC_Type* base, uint8_t logicCh, uint8_t cmpMode); + +/*! + * @brief Set ADC module build-in comparer high threshold on target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param threshold Comparer threshold in 12-bit unsigned int formate. + */ +void ADC_SetCmpHighThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold); + +/*! + * @brief Set ADC module build-in comparer low threshold on target logic channel. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param threshold Comparer threshold in 12-bit unsigned int formate. + */ +void ADC_SetCmpLowThres(ADC_Type* base, uint8_t logicCh, uint16_t threshold); + +/*! + * @brief Set the working mode of ADC module auto disable feature on target logic channel. + * This feature can disable continuous conversion when CMP condition matched. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + * @param enable Enable/Disable Auto Disable feature. + * - true: Enable Auto Disable feature. + * - false: Disable Auto Disable feature. + */ +void ADC_SetAutoDisableCmd(ADC_Type* base, uint8_t logicCh, bool enable); + +/*@}*/ + +/*! + * @name Interrupt and Flag control functions. + * @{ + */ + +/*! + * @brief Enables or disables ADC interrupt requests. + * + * @param base ADC base pointer. + * @param intSource ADC interrupt sources to configuration. + * @param enable Enable/Disable given ADC interrupt. + * - true: Enable given ADC interrupt. + * - false: Disable given ADC interrupt. + */ +void ADC_SetIntCmd(ADC_Type* base, uint32_t intSource, bool enable); + +/*! + * @brief Enables or disables ADC interrupt flag when interrupt condition met. + * + * @param base ADC base pointer. + * @param intSignal ADC interrupt signals to configuration (see @ref _adc_interrupt enumeration). + * @param enable Enable/Disable given ADC interrupt flags. + * - true: Enable given ADC interrupt flags. + * - false: Disable given ADC interrupt flags. + */ +void ADC_SetIntSigCmd(ADC_Type* base, uint32_t intSignal, bool enable); + +/*! + * @brief Gets the ADC status flag state. + * + * @param base ADC base pointer. + * @param flags ADC status flag mask defined in @ref _adc_status_flag enumeration. + * @return ADC status, each bit represents one status flag + */ +static inline uint32_t ADC_GetStatusFlag(ADC_Type* base, uint32_t flags) +{ + return (ADC_INT_STATUS_REG(base) & flags); +} + +/*! + * @brief Clear one or more ADC status flag state. + * + * @param base ADC base pointer. + * @param flags ADC status flag mask defined in @ref _adc_status_flag enumeration. + */ +static inline void ADC_ClearStatusFlag(ADC_Type* base, uint32_t flags) +{ + ADC_INT_STATUS_REG(base) &= ~flags; +} + +/*@}*/ + +/*! + * @name DMA & FIFO control functions. + * @{ + */ + +/*! + * @brief Set the reset state of ADC internal DMA part. + * + * @param base ADC base pointer. + * @param active Reset DMA & DMA FIFO or not. + * - true: Reset the DMA and DMA FIFO return to its reset value. + * - false: Do not reset DMA and DMA FIFO. + */ +void ADC_SetDmaReset(ADC_Type* base, bool active); + +/*! + * @brief Set the work mode of ADC DMA part. + * + * @param base ADC base pointer. + * @param enable Enable/Disable ADC DMA part. + * - true: Enable DMA, the data in DMA FIFO should move by SDMA. + * - false: Disable DMA, the data in DMA FIFO can only move by CPU. + */ +void ADC_SetDmaCmd(ADC_Type* base, bool enable); + +/*! + * @brief Set the work mode of ADC DMA FIFO part. + * + * @param base ADC base pointer. + * @param enable Enable/Disable DMA FIFO. + * - true: Enable DMA FIFO. + * - false: Disable DMA FIFO. + */ +void ADC_SetDmaFifoCmd(ADC_Type* base, bool enable); + +/*! + * @brief Select the logic channel that uses the DMA transfer. + * + * @param base ADC base pointer. + * @param logicCh ADC module logic channel selection (see @ref _adc_logic_ch_selection enumeration). + */ +static inline void ADC_SetDmaCh(ADC_Type* base, uint32_t logicCh) +{ + assert(logicCh <= adcLogicChD); + ADC_DMA_FIFO_REG(base) = (ADC_DMA_FIFO_REG(base) & ~ADC_DMA_FIFO_DMA_CH_SEL_MASK) | \ + ADC_DMA_FIFO_DMA_CH_SEL(logicCh); +} + +/*! + * @brief Set the DMA request trigger watermark. + * + * @param base ADC base pointer. + * @param watermark DMA request trigger watermark. + */ +static inline void ADC_SetDmaWatermark(ADC_Type* base, uint32_t watermark) +{ + assert(watermark <= 0x1FF); + ADC_DMA_FIFO_REG(base) = (ADC_DMA_FIFO_REG(base) & ~ADC_DMA_FIFO_DMA_WM_LVL_MASK) | \ + ADC_DMA_FIFO_DMA_WM_LVL(watermark); +} + +/*! + * @brief Get the convert result from DMA FIFO. + * Data position: + * DMA_FIFO_DATA1(27~16bits) + * DMA_FIFO_DATA0(11~0bits) + * + * @param base ADC base pointer. + * @return Get 2 ADC transfer result from DMA FIFO. + */ +static inline uint32_t ADC_GetFifoData(ADC_Type* base) +{ + return ADC_DMA_FIFO_DAT_REG(base); +} + +/*! + * @brief Get the DMA FIFO full status + * + * @param base ADC base pointer. + * @retval true: DMA FIFO full. + * @retval false: DMA FIFO not full. + */ +static inline bool ADC_IsFifoFull(ADC_Type* base) +{ + return (bool)(ADC_FIFO_STATUS_REG(base) & ADC_FIFO_STATUS_FIFO_FULL_MASK); +} + +/*! + * @brief Get the DMA FIFO empty status + * + * @param base ADC base pointer. + * @retval true: DMA FIFO is empty. + * @retval false: DMA FIFO is not empty. + */ +static inline bool ADC_IsFifoEmpty(ADC_Type* base) +{ + return (bool)(ADC_FIFO_STATUS_REG(base) & ADC_FIFO_STATUS_FIFO_EMPTY_MASK); +} + +/*! + * @brief Get the entries number in DMA FIFO. + * + * @param base ADC base pointer. + * @return The numbers of data in DMA FIFO. + */ +static inline uint8_t ADC_GetFifoEntries(ADC_Type* base) +{ + return ADC_FIFO_STATUS_REG(base) & ADC_FIFO_STATUS_FIFO_ENTRIES_MASK; +} + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __ADC_IMX7D_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX7D/drivers/ccm_analog_imx7d.c b/devices/MCIMX7D/drivers/ccm_analog_imx7d.c new file mode 100644 index 000000000..6713eefed --- /dev/null +++ b/devices/MCIMX7D/drivers/ccm_analog_imx7d.c @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ccm_analog_imx7d.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetArmPllFreq + * Description : Get ARM PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetArmPllFreq(CCM_ANALOG_Type * base) +{ + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllArmControl)) + return 24000000ul; + + return 12000000ul * (CCM_ANALOG_PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetSysPllFreq + * Description : Get system PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetSysPllFreq(CCM_ANALOG_Type * base) +{ + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPll480Control)) + return 24000000ul; + + if (CCM_ANALOG_PLL_480 & CCM_ANALOG_PLL_480_DIV_SELECT_MASK) + return 528000000ul; + else + return 480000000ul; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetDdrPllFreq + * Description : Get DDR PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetDdrPllFreq(CCM_ANALOG_Type * base) +{ + uint8_t divSelect, divTestSelect; + float factor; + + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllDdrControl)) + return 24000000ul; + + divSelect = CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG) & CCM_ANALOG_PLL_DDR_DIV_SELECT_MASK; + divTestSelect = (CCM_ANALOG_PLL_DDR_REG(CCM_ANALOG) & CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_DDR_TEST_DIV_SELECT_SHIFT; + + switch (divTestSelect) + { + case 0x0: + divTestSelect = 2; + break; + case 0x1: + divTestSelect = 1; + break; + case 0x2: + case 0x3: + divTestSelect = 0; + break; + } + + if (CCM_ANALOG_PLL_DDR_SS_REG(base) & CCM_ANALOG_PLL_DDR_SS_ENABLE_MASK) + { + factor = ((float)(CCM_ANALOG_PLL_DDR_SS_REG(base) & CCM_ANALOG_PLL_DDR_SS_STEP_MASK)) / + ((float)(CCM_ANALOG_PLL_DDR_DENOM_REG(base) & CCM_ANALOG_PLL_DDR_DENOM_B_MASK)) * + ((float)(CCM_ANALOG_PLL_DDR_NUM_REG(base) & CCM_ANALOG_PLL_DDR_NUM_A_MASK)); + return (uint32_t)((24000000ul >> divTestSelect) * (divSelect + factor)); + } + else + { + return (24000000ul >> divTestSelect) * divSelect; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetEnetPllFreq + * Description : Get Ethernet PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetEnetPllFreq(CCM_ANALOG_Type * base) +{ + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllEnetControl)) + return 24000000ul; + + return 1000000000ul; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetAudioPllFreq + * Description : Get Ethernet PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetAudioPllFreq(CCM_ANALOG_Type * base) +{ + uint8_t divSelect, divPostSelect, divTestSelect; + float factor; + + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllAudioControl)) + return 24000000ul; + + divSelect = CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK; + divPostSelect = (CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_MASK) >> + CCM_ANALOG_PLL_AUDIO_POST_DIV_SEL_SHIFT; + divTestSelect = (CCM_ANALOG_PLL_AUDIO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_AUDIO_TEST_DIV_SELECT_SHIFT; + + switch (divPostSelect) + { + case 0x0: + case 0x2: + divPostSelect = 0; + break; + case 0x1: + divPostSelect = 1; + break; + case 0x3: + divPostSelect = 2; + break; + } + + switch (divTestSelect) + { + case 0x0: + divTestSelect = 2; + break; + case 0x1: + divTestSelect = 1; + break; + case 0x2: + case 0x3: + divTestSelect = 0; + break; + } + + if (CCM_ANALOG_PLL_AUDIO_SS_REG(base) & CCM_ANALOG_PLL_AUDIO_SS_ENABLE_MASK) + { + factor = ((float)(CCM_ANALOG_PLL_AUDIO_SS_REG(base) & CCM_ANALOG_PLL_AUDIO_SS_STEP_MASK)) / + ((float)(CCM_ANALOG_PLL_AUDIO_DENOM_REG(base) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)) * + ((float)(CCM_ANALOG_PLL_AUDIO_NUM_REG(base) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)); + return (uint32_t)(((24000000ul >> divTestSelect) >> divPostSelect) * (divSelect + factor)); + } + else + { + return ((24000000ul >> divTestSelect) >> divPostSelect) * divSelect; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetVideoPllFreq + * Description : Get Ethernet PLL frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetVideoPllFreq(CCM_ANALOG_Type * base) +{ + uint8_t divSelect, divPostSelect, divTestSelect; + float factor; + + if (CCM_ANALOG_IsPllBypassed(base, ccmAnalogPllVideoControl)) + return 24000000ul; + + divSelect = CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK; + divPostSelect = (CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_MASK) >> + CCM_ANALOG_PLL_VIDEO_POST_DIV_SEL_SHIFT; + divTestSelect = (CCM_ANALOG_PLL_VIDEO_REG(CCM_ANALOG) & CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_MASK) >> + CCM_ANALOG_PLL_VIDEO_TEST_DIV_SELECT_SHIFT; + + switch (divPostSelect) + { + case 0x0: + case 0x2: + divPostSelect = 0; + break; + case 0x1: + divPostSelect = 1; + break; + case 0x3: + divPostSelect = 2; + break; + } + + switch (divTestSelect) + { + case 0x0: + divTestSelect = 2; + break; + case 0x1: + divTestSelect = 1; + break; + case 0x2: + case 0x3: + divTestSelect = 0; + break; + } + + if (CCM_ANALOG_PLL_VIDEO_SS_REG(base) & CCM_ANALOG_PLL_VIDEO_SS_ENABLE_MASK) + { + factor = ((float)(CCM_ANALOG_PLL_VIDEO_SS_REG(base) & CCM_ANALOG_PLL_VIDEO_SS_STEP_MASK)) / + ((float)(CCM_ANALOG_PLL_VIDEO_DENOM_REG(base) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)) * + ((float)(CCM_ANALOG_PLL_VIDEO_NUM_REG(base) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)); + return (uint32_t)(((24000000ul >> divTestSelect) >> divPostSelect) * (divSelect + factor)); + } + else + { + return ((24000000ul >> divTestSelect) >> divPostSelect) * divSelect; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_ANALOG_GetPfdFreq + * Description : Get PFD frequency + * + *END**************************************************************************/ +uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac) +{ + uint32_t main, frac; + + /* PFD should work with system PLL without bypass */ + assert(!CCM_ANALOG_IsPllBypassed(base, ccmAnalogPll480Control)); + + main = CCM_ANALOG_GetSysPllFreq(base); + frac = CCM_ANALOG_GetPfdFrac(base, pfdFrac); + + return main / frac * 18; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX7D/drivers/ccm_analog_imx7d.h b/devices/MCIMX7D/drivers/ccm_analog_imx7d.h new file mode 100644 index 000000000..1af5baae5 --- /dev/null +++ b/devices/MCIMX7D/drivers/ccm_analog_imx7d.h @@ -0,0 +1,398 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCM_ANALOG_IMX7D_H__ +#define __CCM_ANALOG_IMX7D_H__ + +#include +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ccm_analog_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_ANALOG_TUPLE(reg, shift) ((offsetof(CCM_ANALOG_Type, reg) & 0xFFFF) | ((shift) << 16)) +#define CCM_ANALOG_TUPLE_REG_OFF(base, tuple, off) (*((volatile uint32_t *)((uint32_t)base + ((tuple) & 0xFFFF) + off))) +#define CCM_ANALOG_TUPLE_REG(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 0) +#define CCM_ANALOG_TUPLE_REG_SET(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 4) +#define CCM_ANALOG_TUPLE_REG_CLR(base, tuple) CCM_ANALOG_TUPLE_REG_OFF(base, tuple, 8) +#define CCM_ANALOG_TUPLE_SHIFT(tuple) (((tuple) >> 16) & 0x1F) + +/*! + * @brief PLL control names for PLL power/bypass/lock operations. + * + * These constants define the PLL control names for PLL power/bypass/lock operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Power down bit shift. + */ +enum _ccm_analog_pll_control +{ + ccmAnalogPllArmControl = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT), /*!< CCM Analog ARM PLL Control.*/ + ccmAnalogPllDdrControl = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_POWERDOWN_SHIFT), /*!< CCM Analog DDR PLL Control.*/ + ccmAnalogPll480Control = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_POWERDOWN_SHIFT), /*!< CCM Analog 480M PLL Control.*/ + ccmAnalogPllEnetControl = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT), /*!< CCM Analog Ethernet PLL Control.*/ + ccmAnalogPllAudioControl = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT), /*!< CCM Analog AUDIO PLL Control.*/ + ccmAnalogPllVideoControl = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT), /*!< CCM Analog VIDEO PLL Control.*/ +}; + +/*! + * @brief PLL clock names for clock enable/disable settings. + * + * These constants define the PLL clock names for PLL clock enable/disable operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock enable bit shift. + */ +enum _ccm_analog_pll_clock +{ + ccmAnalogPllArmClock = CCM_ANALOG_TUPLE(PLL_ARM, CCM_ANALOG_PLL_ARM_ENABLE_CLK_SHIFT), /*!< CCM Analog ARM PLL Clock.*/ + ccmAnalogPllDdrClock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_ENABLE_CLK_SHIFT), /*!< CCM Analog DDR PLL Clock.*/ + ccmAnalogPllDdrDiv2Clock = CCM_ANALOG_TUPLE(PLL_DDR, CCM_ANALOG_PLL_DDR_DIV2_ENABLE_CLK_SHIFT), /*!< CCM Analog DDR PLL divided by 2 Clock.*/ + ccmAnalogPll480Clock = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_ENABLE_CLK_SHIFT), /*!< CCM Analog 480M PLL Clock.*/ + ccmAnalogPllEnet25MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_25MHZ_SHIFT), /*!< CCM Analog Ethernet 25M PLL Clock.*/ + ccmAnalogPllEnet40MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_40MHZ_SHIFT), /*!< CCM Analog Ethernet 40M PLL Clock.*/ + ccmAnalogPllEnet50MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_50MHZ_SHIFT), /*!< CCM Analog Ethernet 50M PLL Clock.*/ + ccmAnalogPllEnet100MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_100MHZ_SHIFT), /*!< CCM Analog Ethernet 100M PLL Clock.*/ + ccmAnalogPllEnet125MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_125MHZ_SHIFT), /*!< CCM Analog Ethernet 125M PLL Clock.*/ + ccmAnalogPllEnet250MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_250MHZ_SHIFT), /*!< CCM Analog Ethernet 250M PLL Clock.*/ + ccmAnalogPllEnet500MhzClock = CCM_ANALOG_TUPLE(PLL_ENET, CCM_ANALOG_PLL_ENET_ENABLE_CLK_500MHZ_SHIFT), /*!< CCM Analog Ethernet 500M PLL Clock.*/ + ccmAnalogPllAudioClock = CCM_ANALOG_TUPLE(PLL_AUDIO, CCM_ANALOG_PLL_AUDIO_ENABLE_CLK_SHIFT), /*!< CCM Analog AUDIO PLL Clock.*/ + ccmAnalogPllVideoClock = CCM_ANALOG_TUPLE(PLL_VIDEO, CCM_ANALOG_PLL_VIDEO_ENABLE_CLK_SHIFT), /*!< CCM Analog VIDEO PLL Clock.*/ +}; + +/*! + * @brief PFD gate names for clock gate settings, clock source is system PLL(PLL_480) + * + * These constants define the PFD gate names for PFD clock enable/disable operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Clock gate bit shift. + */ +enum _ccm_analog_pfd_clkgate +{ + ccmAnalogMainDiv1ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480 MAIN DIV1 Clock Gate.*/ + ccmAnalogMainDiv2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 MAIN DIV2 Clock Gate.*/ + ccmAnalogMainDiv4ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_MAIN_DIV4_CLKGATE_SHIFT), /*!< CCM Analog 480 MAIN DIV4 Clock Gate.*/ + ccmAnalogPfd0Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD0_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 PFD0 DIV2 Clock Gate.*/ + ccmAnalogPfd1Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD1_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 PFD1 DIV2 Clock Gate.*/ + ccmAnalogPfd2Div2ClkGate = CCM_ANALOG_TUPLE(PLL_480, CCM_ANALOG_PLL_480_PFD2_DIV2_CLKGATE_SHIFT), /*!< CCM Analog 480 PFD2 DIV2 Clock Gate.*/ + ccmAnalogPfd0Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD0 DIV1 Clock Gate.*/ + ccmAnalogPfd1Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD1 DIV1 Clock Gate.*/ + ccmAnalogPfd2Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD2 DIV1 Clock Gate.*/ + ccmAnalogPfd3Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480A PFD3 DIV1 Clock Gate.*/ + ccmAnalogPfd4Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD4 DIV1 Clock Gate.*/ + ccmAnalogPfd5Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD5 DIV1 Clock Gate.*/ + ccmAnalogPfd6Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD6 DIV1 Clock Gate.*/ + ccmAnalogPfd7Div1ClkGate = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_DIV1_CLKGATE_SHIFT), /*!< CCM Analog 480B PFD7 DIV1 Clock Gate.*/ +}; + +/*! + * @brief PFD fraction names for clock fractional divider operations + * + * These constants define the PFD fraction names for PFD fractional divider operations.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Fraction bits shift. + */ +enum _ccm_analog_pfd_frac +{ + ccmAnalogPfd0Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_FRAC_SHIFT), /*!< CCM Analog 480A PFD0 fractional divider.*/ + ccmAnalogPfd1Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_FRAC_SHIFT), /*!< CCM Analog 480A PFD1 fractional divider.*/ + ccmAnalogPfd2Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_FRAC_SHIFT), /*!< CCM Analog 480A PFD2 fractional divider.*/ + ccmAnalogPfd3Frac = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_FRAC_SHIFT), /*!< CCM Analog 480A PFD3 fractional divider.*/ + ccmAnalogPfd4Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_FRAC_SHIFT), /*!< CCM Analog 480B PFD4 fractional divider.*/ + ccmAnalogPfd5Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_FRAC_SHIFT), /*!< CCM Analog 480B PFD5 fractional divider.*/ + ccmAnalogPfd6Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_FRAC_SHIFT), /*!< CCM Analog 480B PFD6 fractional divider.*/ + ccmAnalogPfd7Frac = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_FRAC_SHIFT), /*!< CCM Analog 480B PFD7 fractional divider.*/ +}; + +/*! + * @brief PFD stable names for clock stable query + * + * These constants define the PFD stable names for clock stable query.\n + * - 0:15: REG offset to CCM_ANALOG_BASE in bytes. + * - 16:20: Stable bit shift. + */ +enum _ccm_analog_pfd_stable +{ + ccmAnalogPfd0Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD0_STABLE_SHIFT), /*!< CCM Analog 480A PFD0 clock stable query.*/ + ccmAnalogPfd1Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD1_STABLE_SHIFT), /*!< CCM Analog 480A PFD1 clock stable query.*/ + ccmAnalogPfd2Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD2_STABLE_SHIFT), /*!< CCM Analog 480A PFD2 clock stable query.*/ + ccmAnalogPfd3Stable = CCM_ANALOG_TUPLE(PFD_480A, CCM_ANALOG_PFD_480A_PFD3_STABLE_SHIFT), /*!< CCM Analog 480A PFD3 clock stable query.*/ + ccmAnalogPfd4Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD4_STABLE_SHIFT), /*!< CCM Analog 480B PFD4 clock stable query.*/ + ccmAnalogPfd5Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD5_STABLE_SHIFT), /*!< CCM Analog 480B PFD5 clock stable query.*/ + ccmAnalogPfd6Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD6_STABLE_SHIFT), /*!< CCM Analog 480B PFD6 clock stable query.*/ + ccmAnalogPfd7Stable = CCM_ANALOG_TUPLE(PFD_480B, CCM_ANALOG_PFD_480B_PFD7_STABLE_SHIFT), /*!< CCM Analog 480B PFD7 clock stable query.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CCM Analog PLL Operatoin Functions + * @{ + */ + +/*! + * @brief Power up PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + */ +static inline void CCM_ANALOG_PowerUpPll(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); +} + +/*! + * @brief Power down PLL + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + */ +static inline void CCM_ANALOG_PowerDownPll(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllControl); +} + +/*! + * @brief PLL bypass setting + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @param bypass Bypass the PLL. + * - true: Bypass the PLL. + * - false: Do not bypass the PLL. + */ +static inline void CCM_ANALOG_SetPllBypass(CCM_ANALOG_Type * base, uint32_t pllControl, bool bypass) +{ + if (bypass) + CCM_ANALOG_TUPLE_REG_SET(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK; + else + CCM_ANALOG_TUPLE_REG_CLR(base, pllControl) = CCM_ANALOG_PLL_ARM_BYPASS_MASK; +} + +/*! + * @brief Check if PLL is bypassed + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL bypass status. + * - true: The PLL is bypassed. + * - false: The PLL is not bypassed. + */ +static inline bool CCM_ANALOG_IsPllBypassed(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_BYPASS_MASK); +} + +/*! + * @brief Check if PLL clock is locked + * + * @param base CCM_ANALOG base pointer. + * @param pllControl PLL control name (see @ref _ccm_analog_pll_control enumeration) + * @return PLL lock status. + * - true: The PLL clock is locked. + * - false: The PLL clock is not locked. + */ +static inline bool CCM_ANALOG_IsPllLocked(CCM_ANALOG_Type * base, uint32_t pllControl) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pllControl) & CCM_ANALOG_PLL_ARM_LOCK_MASK); +} + +/*! + * @brief Enable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) + */ +static inline void CCM_ANALOG_EnablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock); +} + +/*! + * @brief Disable PLL clock + * + * @param base CCM_ANALOG base pointer. + * @param pllClock PLL clock name (see @ref _ccm_analog_pll_clock enumeration) + */ +static inline void CCM_ANALOG_DisablePllClock(CCM_ANALOG_Type * base, uint32_t pllClock) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pllClock) = 1 << CCM_ANALOG_TUPLE_SHIFT(pllClock); +} + +/*! + * @brief Get ARM PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return ARM PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetArmPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get System PLL (PLL_480) clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return System PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetSysPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get DDR PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return DDR PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetDdrPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get ENET PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return ENET PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetEnetPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get Audio PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return Audio PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetAudioPllFreq(CCM_ANALOG_Type * base); + +/*! + * @brief Get Video PLL clock frequency + * + * @param base CCM_ANALOG base pointer. + * @return Video PLL clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetVideoPllFreq(CCM_ANALOG_Type * base); + +/*@}*/ + +/*! + * @name CCM Analog PFD Operatoin Functions + * @{ + */ + +/*! + * @brief Enable PFD clock + * + * @param base CCM_ANALOG base pointer. + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) + */ +static inline void CCM_ANALOG_EnablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) +{ + CCM_ANALOG_TUPLE_REG_CLR(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate); +} + +/*! + * @brief Disable PFD clock + * + * @param base CCM_ANALOG base pointer. + * @param pfdClkGate PFD clock gate (see @ref _ccm_analog_pfd_clkgate enumeration) + */ +static inline void CCM_ANALOG_DisablePfdClock(CCM_ANALOG_Type * base, uint32_t pfdClkGate) +{ + CCM_ANALOG_TUPLE_REG_SET(base, pfdClkGate) = 1 << CCM_ANALOG_TUPLE_SHIFT(pfdClkGate); +} + +/*! + * @brief Check if PFD clock is stable + * + * @param base CCM_ANALOG base pointer. + * @param pfdStable PFD stable identifier (see @ref _ccm_analog_pfd_stable enumeration) + * @return PFD clock stable status. + * - true: The PFD clock is stable. + * - false: The PFD clock is not stable. + */ +static inline bool CCM_ANALOG_IsPfdStable(CCM_ANALOG_Type * base, uint32_t pfdStable) +{ + return (bool)(CCM_ANALOG_TUPLE_REG(base, pfdStable) & (1 << CCM_ANALOG_TUPLE_SHIFT(pfdStable))); +} + +/*! + * @brief Set PFD clock fraction + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @param value PFD clock fraction value + */ +static inline void CCM_ANALOG_SetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac, uint32_t value) +{ + assert(value >= 12 && value <= 35); + CCM_ANALOG_TUPLE_REG_CLR(base, pfdFrac) = CCM_ANALOG_PFD_480A_CLR_PFD0_FRAC_MASK << CCM_ANALOG_TUPLE_SHIFT(pfdFrac); + CCM_ANALOG_TUPLE_REG_SET(base, pfdFrac) = value << CCM_ANALOG_TUPLE_SHIFT(pfdFrac); +} + +/*! + * @brief Get PFD clock fraction + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @return PFD clock fraction value + */ +static inline uint32_t CCM_ANALOG_GetPfdFrac(CCM_ANALOG_Type * base, uint32_t pfdFrac) +{ + return (CCM_ANALOG_TUPLE_REG(base, pfdFrac) >> CCM_ANALOG_TUPLE_SHIFT(pfdFrac)) & CCM_ANALOG_PFD_480A_PFD0_FRAC_MASK; +} + +/*! + * @brief Get PFD clock frequency + * + * @param base CCM_ANALOG base pointer. + * @param pfdFrac PFD clock fraction (see @ref _ccm_analog_pfd_frac enumeration) + * @return PFD clock frequency in Hz + */ +uint32_t CCM_ANALOG_GetPfdFreq(CCM_ANALOG_Type * base, uint32_t pfdFrac); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CCM_ANALOG_IMX7D_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX7D/drivers/ccm_imx7d.c b/devices/MCIMX7D/drivers/ccm_imx7d.c new file mode 100644 index 000000000..11f2889a2 --- /dev/null +++ b/devices/MCIMX7D/drivers/ccm_imx7d.c @@ -0,0 +1,85 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ccm_imx7d.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_SetDivider + * Description : Set root clock divider + * + *END**************************************************************************/ +void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t pre, uint32_t post) +{ + assert (pre < 8); + assert (post < 64); + + CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & + (~(CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) | + CCM_TARGET_ROOT_PRE_PODF(pre) | CCM_TARGET_ROOT_POST_PODF(post); +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_GetDivider + * Description : Get root clock divider + * + *END**************************************************************************/ +void CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t *pre, uint32_t *post) +{ + assert (pre && post); + + *pre = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_PRE_PODF_MASK) >> CCM_TARGET_ROOT_PRE_PODF_SHIFT; + *post = (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_POST_PODF_MASK) >> CCM_TARGET_ROOT_POST_PODF_SHIFT; +} + +/*FUNCTION********************************************************************** + * + * Function Name : CCM_UpdateRoot + * Description : Update clock root in one step, for dynamical clock switching + * + *END**************************************************************************/ +void CCM_UpdateRoot(CCM_Type * base, uint32_t ccmRoot, uint32_t mux, uint32_t pre, uint32_t post) +{ + assert (pre < 8); + assert (post < 64); + + CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & + (~(CCM_TARGET_ROOT_MUX_MASK | CCM_TARGET_ROOT_PRE_PODF_MASK | CCM_TARGET_ROOT_POST_PODF_MASK))) | + CCM_TARGET_ROOT_MUX(mux) | CCM_TARGET_ROOT_PRE_PODF(pre) | CCM_TARGET_ROOT_POST_PODF(post); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX7D/drivers/ccm_imx7d.h b/devices/MCIMX7D/drivers/ccm_imx7d.h new file mode 100644 index 000000000..088971829 --- /dev/null +++ b/devices/MCIMX7D/drivers/ccm_imx7d.h @@ -0,0 +1,470 @@ +/* + * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CCM_IMX7D_H__ +#define __CCM_IMX7D_H__ + +#include +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ccm_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define CCM_REG_OFF(root, off) (*((volatile uint32_t *)((uint32_t)root + off))) +#define CCM_REG(root) CCM_REG_OFF(root, 0) +#define CCM_REG_SET(root) CCM_REG_OFF(root, 4) +#define CCM_REG_CLR(root) CCM_REG_OFF(root, 8) + +/*! @brief Root control names for root clock setting. */ +enum _ccm_root_control +{ + ccmRootM4 = (uint32_t)(&CCM_TARGET_ROOT1), /*!< ARM Cortex-M4 Clock control name.*/ + ccmRootAxi = (uint32_t)(&CCM_TARGET_ROOT16), /*!< AXI Clock control name.*/ + ccmRootAhb = (uint32_t)(&CCM_TARGET_ROOT32), /*!< AHB Clock control name.*/ + ccmRootIpg = (uint32_t)(&CCM_TARGET_ROOT33), /*!< IPG Clock control name.*/ + ccmRootQspi = (uint32_t)(&CCM_TARGET_ROOT85), /*!< QSPI Clock control name.*/ + ccmRootCan1 = (uint32_t)(&CCM_TARGET_ROOT89), /*!< CAN1 Clock control name.*/ + ccmRootCan2 = (uint32_t)(&CCM_TARGET_ROOT90), /*!< CAN2 Clock control name.*/ + ccmRootI2c1 = (uint32_t)(&CCM_TARGET_ROOT91), /*!< I2C1 Clock control name.*/ + ccmRootI2c2 = (uint32_t)(&CCM_TARGET_ROOT92), /*!< I2C2 Clock control name.*/ + ccmRootI2c3 = (uint32_t)(&CCM_TARGET_ROOT93), /*!< I2C3 Clock control name.*/ + ccmRootI2c4 = (uint32_t)(&CCM_TARGET_ROOT94), /*!< I2C4 Clock control name.*/ + ccmRootUart1 = (uint32_t)(&CCM_TARGET_ROOT95), /*!< UART1 Clock control name.*/ + ccmRootUart2 = (uint32_t)(&CCM_TARGET_ROOT96), /*!< UART2 Clock control name.*/ + ccmRootUart3 = (uint32_t)(&CCM_TARGET_ROOT97), /*!< UART3 Clock control name.*/ + ccmRootUart4 = (uint32_t)(&CCM_TARGET_ROOT98), /*!< UART4 Clock control name.*/ + ccmRootUart5 = (uint32_t)(&CCM_TARGET_ROOT99), /*!< UART5 Clock control name.*/ + ccmRootUart6 = (uint32_t)(&CCM_TARGET_ROOT100), /*!< UART6 Clock control name.*/ + ccmRootUart7 = (uint32_t)(&CCM_TARGET_ROOT101), /*!< UART7 Clock control name.*/ + ccmRootEcspi1 = (uint32_t)(&CCM_TARGET_ROOT102), /*!< ECSPI1 Clock control name.*/ + ccmRootEcspi2 = (uint32_t)(&CCM_TARGET_ROOT103), /*!< ECSPI2 Clock control name.*/ + ccmRootEcspi3 = (uint32_t)(&CCM_TARGET_ROOT104), /*!< ECSPI3 Clock control name.*/ + ccmRootEcspi4 = (uint32_t)(&CCM_TARGET_ROOT105), /*!< ECSPI4 Clock control name.*/ + ccmRootFtm1 = (uint32_t)(&CCM_TARGET_ROOT110), /*!< FTM1 Clock control name.*/ + ccmRootFtm2 = (uint32_t)(&CCM_TARGET_ROOT111), /*!< FTM2 Clock control name.*/ + ccmRootGpt1 = (uint32_t)(&CCM_TARGET_ROOT114), /*!< GPT1 Clock control name.*/ + ccmRootGpt2 = (uint32_t)(&CCM_TARGET_ROOT115), /*!< GPT2 Clock control name.*/ + ccmRootGpt3 = (uint32_t)(&CCM_TARGET_ROOT116), /*!< GPT3 Clock control name.*/ + ccmRootGpt4 = (uint32_t)(&CCM_TARGET_ROOT117), /*!< GPT4 Clock control name.*/ + ccmRootWdog = (uint32_t)(&CCM_TARGET_ROOT119), /*!< WDOG Clock control name.*/ +}; + +/*! @brief Clock source enumeration for ARM Cortex-M4 core. */ +enum _ccm_rootmux_m4 +{ + ccmRootmuxM4Osc24m = 0U, /*!< ARM Cortex-M4 Clock from OSC 24M.*/ + ccmRootmuxM4SysPllDiv2 = 1U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxM4EnetPll250m = 2U, /*!< ARM Cortex-M4 Clock from Ethernet PLL 250M.*/ + ccmRootmuxM4SysPllPfd2 = 3U, /*!< ARM Cortex-M4 Clock from SYSTEM PLL PFD2.*/ + ccmRootmuxM4DdrPllDiv2 = 4U, /*!< ARM Cortex-M4 Clock from DDR PLL divided by 2.*/ + ccmRootmuxM4AudioPll = 5U, /*!< ARM Cortex-M4 Clock from AUDIO PLL.*/ + ccmRootmuxM4VideoPll = 6U, /*!< ARM Cortex-M4 Clock from VIDEO PLL.*/ + ccmRootmuxM4UsbPll = 7U, /*!< ARM Cortex-M4 Clock from USB PLL.*/ +}; + +/*! @brief Clock source enumeration for AXI bus. */ +enum _ccm_rootmux_axi +{ + ccmRootmuxAxiOsc24m = 0U, /*!< AXI Clock from OSC 24M.*/ + ccmRootmuxAxiSysPllPfd1 = 1U, /*!< AXI Clock from SYSTEM PLL PFD1.*/ + ccmRootmuxAxiDdrPllDiv2 = 2U, /*!< AXI Clock DDR PLL divided by 2.*/ + ccmRootmuxAxiEnetPll250m = 3U, /*!< AXI Clock Ethernet PLL 250M.*/ + ccmRootmuxAxiSysPllPfd5 = 4U, /*!< AXI Clock SYSTEM PLL PFD5.*/ + ccmRootmuxAxiAudioPll = 5U, /*!< AXI Clock AUDIO PLL.*/ + ccmRootmuxAxiVideoPll = 6U, /*!< AXI Clock VIDEO PLL.*/ + ccmRootmuxAxiSysPllPfd7 = 7U, /*!< AXI Clock SYSTEM PLL PFD7.*/ +}; + +/*! @brief Clock source enumeration for AHB bus. */ +enum _ccm_rootmux_ahb +{ + ccmRootmuxAhbOsc24m = 0U, /*!< AHB Clock from OSC 24M.*/ + ccmRootmuxAhbSysPllPfd2 = 1U, /*!< AHB Clock from SYSTEM PLL PFD2.*/ + ccmRootmuxAhbDdrPllDiv2 = 2U, /*!< AHB Clock from DDR PLL divided by 2.*/ + ccmRootmuxAhbSysPllPfd0 = 3U, /*!< AHB Clock from SYSTEM PLL PFD0.*/ + ccmRootmuxAhbEnetPll125m = 4U, /*!< AHB Clock from Ethernet PLL 125M.*/ + ccmRootmuxAhbUsbPll = 5U, /*!< AHB Clock from USB PLL.*/ + ccmRootmuxAhbAudioPll = 6U, /*!< AHB Clock from AUDIO PLL.*/ + ccmRootmuxAhbVideoPll = 7U, /*!< AHB Clock from VIDEO PLL.*/ +}; + +/*! @brief Clock source enumeration for IPG bus. */ +enum _ccm_rootmux_ipg +{ + ccmRootmuxIpgAHB = 0U, /*!< IPG Clock from AHB Clock.*/ +}; + +/*! @brief Clock source enumeration for QSPI peripheral. */ +enum _ccm_rootmux_qspi +{ + ccmRootmuxQspiOsc24m = 0U, /*!< QSPI Clock from OSC 24M.*/ + ccmRootmuxQspiSysPllPfd4 = 1U, /*!< QSPI Clock from SYSTEM PLL PFD4.*/ + ccmRootmuxQspiDdrPllDiv2 = 2U, /*!< QSPI Clock from DDR PLL divided by 2.*/ + ccmRootmuxQspiEnetPll500m = 3U, /*!< QSPI Clock from Ethernet PLL 500M.*/ + ccmRootmuxQspiSysPllPfd3 = 4U, /*!< QSPI Clock from SYSTEM PLL PFD3.*/ + ccmRootmuxQspiSysPllPfd2 = 5U, /*!< QSPI Clock from SYSTEM PLL PFD2.*/ + ccmRootmuxQspiSysPllPfd6 = 6U, /*!< QSPI Clock from SYSTEM PLL PFD6.*/ + ccmRootmuxQspiSysPllPfd7 = 7U, /*!< QSPI Clock from SYSTEM PLL PFD7.*/ +}; + +/*! @brief Clock source enumeration for CAN peripheral. */ +enum _ccm_rootmux_can +{ + ccmRootmuxCanOsc24m = 0U, /*!< CAN Clock from OSC 24M.*/ + ccmRootmuxCanSysPllDiv4 = 1U, /*!< CAN Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxCanDdrPllDiv2 = 2U, /*!< CAN Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxCanSysPllDiv1 = 3U, /*!< CAN Clock from SYSTEM PLL divided by 1.*/ + ccmRootmuxCanEnetPll40m = 4U, /*!< CAN Clock from Ethernet PLL 40M.*/ + ccmRootmuxCanUsbPll = 5U, /*!< CAN Clock from USB PLL.*/ + ccmRootmuxCanExtClk1 = 6U, /*!< CAN Clock from External Clock1.*/ + ccmRootmuxCanExtClk34 = 7U, /*!< CAN Clock from External Clock34.*/ +}; + +/*! @brief Clock source enumeration for ECSPI peripheral. */ +enum _ccm_rootmux_ecspi +{ + ccmRootmuxEcspiOsc24m = 0U, /*!< ECSPI Clock from OSC 24M.*/ + ccmRootmuxEcspiSysPllDiv2 = 1U, /*!< ECSPI Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxEcspiEnetPll40m = 2U, /*!< ECSPI Clock from Ethernet PLL 40M.*/ + ccmRootmuxEcspiSysPllDiv4 = 3U, /*!< ECSPI Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxEcspiSysPllDiv1 = 4U, /*!< ECSPI Clock from SYSTEM PLL divided by 1.*/ + ccmRootmuxEcspiSysPllPfd4 = 5U, /*!< ECSPI Clock from SYSTEM PLL PFD4.*/ + ccmRootmuxEcspiEnetPll250m = 6U, /*!< ECSPI Clock from Ethernet PLL 250M.*/ + ccmRootmuxEcspiUsbPll = 7U, /*!< ECSPI Clock from USB PLL.*/ +}; + +/*! @brief Clock source enumeration for I2C peripheral. */ +enum _ccm_rootmux_i2c +{ + ccmRootmuxI2cOsc24m = 0U, /*!< I2C Clock from OSC 24M.*/ + ccmRootmuxI2cSysPllDiv4 = 1U, /*!< I2C Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxI2cEnetPll50m = 2U, /*!< I2C Clock from Ethernet PLL 50M.*/ + ccmRootmuxI2cDdrPllDiv2 = 3U, /*!< I2C Clock from DDR PLL divided by .*/ + ccmRootmuxI2cAudioPll = 4U, /*!< I2C Clock from AUDIO PLL.*/ + ccmRootmuxI2cVideoPll = 5U, /*!< I2C Clock from VIDEO PLL.*/ + ccmRootmuxI2cUsbPll = 6U, /*!< I2C Clock from USB PLL.*/ + ccmRootmuxI2cSysPllPfd2Div2 = 7U, /*!< I2C Clock from SYSTEM PLL PFD2 divided by 2.*/ +}; + +/*! @brief Clock source enumeration for UART peripheral. */ +enum _ccm_rootmux_uart +{ + ccmRootmuxUartOsc24m = 0U, /*!< UART Clock from OSC 24M.*/ + ccmRootmuxUartSysPllDiv2 = 1U, /*!< UART Clock from SYSTEM PLL divided by 2.*/ + ccmRootmuxUartEnetPll40m = 2U, /*!< UART Clock from Ethernet PLL 40M.*/ + ccmRootmuxUartEnetPll100m = 3U, /*!< UART Clock from Ethernet PLL 100M.*/ + ccmRootmuxUartSysPllDiv1 = 4U, /*!< UART Clock from SYSTEM PLL divided by 1.*/ + ccmRootmuxUartExtClk2 = 5U, /*!< UART Clock from External Clock 2.*/ + ccmRootmuxUartExtClk34 = 6U, /*!< UART Clock from External Clock 34.*/ + ccmRootmuxUartUsbPll = 7U, /*!< UART Clock from USB PLL.*/ +}; + +/*! @brief Clock source enumeration for FlexTimer peripheral. */ +enum _ccm_rootmux_ftm +{ + ccmRootmuxFtmOsc24m = 0U, /*!< FTM Clock from OSC 24M.*/ + ccmRootmuxFtmEnetPll100m = 1U, /*!< FTM Clock from Ethernet PLL 100M.*/ + ccmRootmuxFtmSysPllDiv4 = 2U, /*!< FTM Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxFtmEnetPll40m = 3U, /*!< FTM Clock from Ethernet PLL 40M.*/ + ccmRootmuxFtmAudioPll = 4U, /*!< FTM Clock from AUDIO PLL.*/ + ccmRootmuxFtmExtClk3 = 5U, /*!< FTM Clock from External Clock 3.*/ + ccmRootmuxFtmRef1m = 6U, /*!< FTM Clock from Refernece Clock 1M.*/ + ccmRootmuxFtmVideoPll = 7U, /*!< FTM Clock from VIDEO PLL.*/ +}; + +/*! @brief Clock source enumeration for GPT peripheral. */ +enum _ccm_rootmux_gpt +{ + ccmRootmuxGptOsc24m = 0U, /*!< GPT Clock from OSC 24M.*/ + ccmRootmuxGptEnetPll100m = 1U, /*!< GPT Clock from Ethernet PLL 100M.*/ + ccmRootmuxGptSysPllPfd0 = 2U, /*!< GPT Clock from SYSTEM PLL PFD0.*/ + ccmRootmuxGptEnetPll40m = 3U, /*!< GPT Clock from Ethernet PLL 40M.*/ + ccmRootmuxGptVideoPll = 4U, /*!< GPT Clock from VIDEO PLL.*/ + ccmRootmuxGptRef1m = 5U, /*!< GPT Clock from Refernece Clock 1M.*/ + ccmRootmuxGptAudioPll = 6U, /*!< GPT Clock from AUDIO PLL.*/ + ccmRootmuxGptExtClk = 7U, /*!< GPT Clock from External Clock.*/ +}; + +/*! @brief Clock source enumeration for WDOG peripheral. */ +enum _ccm_rootmux_wdog +{ + ccmRootmuxWdogOsc24m = 0U, /*!< WDOG Clock from OSC 24M.*/ + ccmRootmuxWdogSysPllPfd2Div2 = 1U, /*!< WDOG Clock from SYSTEM PLL PFD2 divided by 2.*/ + ccmRootmuxWdogSysPllDiv4 = 2U, /*!< WDOG Clock from SYSTEM PLL divided by 4.*/ + ccmRootmuxWdogDdrPllDiv2 = 3U, /*!< WDOG Clock from DDR PLL divided by 2.*/ + ccmRootmuxWdogEnetPll125m = 4U, /*!< WDOG Clock from Ethernet PLL 125M.*/ + ccmRootmuxWdogUsbPll = 5U, /*!< WDOG Clock from USB PLL.*/ + ccmRootmuxWdogRef1m = 6U, /*!< WDOG Clock from Refernece Clock 1M.*/ + ccmRootmuxWdogSysPllPfd1Div2 = 7U, /*!< WDOG Clock from SYSTEM PLL PFD1 divided by 2.*/ +}; + +/*! @brief CCM PLL gate control. */ +enum _ccm_pll_gate +{ + ccmPllGateCkil = (uint32_t)(&CCM_PLL_CTRL0), /*!< Ckil PLL Gate.*/ + ccmPllGateArm = (uint32_t)(&CCM_PLL_CTRL1), /*!< ARM PLL Gate.*/ + ccmPllGateArmDiv1 = (uint32_t)(&CCM_PLL_CTRL2), /*!< ARM PLL Div1 Gate.*/ + ccmPllGateDdr = (uint32_t)(&CCM_PLL_CTRL3), /*!< DDR PLL Gate.*/ + ccmPllGateDdrDiv1 = (uint32_t)(&CCM_PLL_CTRL4), /*!< DDR PLL Div1 Gate.*/ + ccmPllGateDdrDiv2 = (uint32_t)(&CCM_PLL_CTRL5), /*!< DDR PLL Div2 Gate.*/ + ccmPllGateSys = (uint32_t)(&CCM_PLL_CTRL6), /*!< SYSTEM PLL Gate.*/ + ccmPllGateSysDiv1 = (uint32_t)(&CCM_PLL_CTRL7), /*!< SYSTEM PLL Div1 Gate.*/ + ccmPllGateSysDiv2 = (uint32_t)(&CCM_PLL_CTRL8), /*!< SYSTEM PLL Div2 Gate.*/ + ccmPllGateSysDiv4 = (uint32_t)(&CCM_PLL_CTRL9), /*!< SYSTEM PLL Div4 Gate.*/ + ccmPllGatePfd0 = (uint32_t)(&CCM_PLL_CTRL10), /*!< PFD0 Gate.*/ + ccmPllGatePfd0Div2 = (uint32_t)(&CCM_PLL_CTRL11), /*!< PFD0 Div2 Gate.*/ + ccmPllGatePfd1 = (uint32_t)(&CCM_PLL_CTRL12), /*!< PFD1 Gate.*/ + ccmPllGatePfd1Div2 = (uint32_t)(&CCM_PLL_CTRL13), /*!< PFD1 Div2 Gate.*/ + ccmPllGatePfd2 = (uint32_t)(&CCM_PLL_CTRL14), /*!< PFD2 Gate.*/ + ccmPllGatePfd2Div2 = (uint32_t)(&CCM_PLL_CTRL15), /*!< PDF2 Div2.*/ + ccmPllGatePfd3 = (uint32_t)(&CCM_PLL_CTRL16), /*!< PDF3 Gate.*/ + ccmPllGatePfd4 = (uint32_t)(&CCM_PLL_CTRL17), /*!< PDF4 Gate.*/ + ccmPllGatePfd5 = (uint32_t)(&CCM_PLL_CTRL18), /*!< PDF5 Gate.*/ + ccmPllGatePfd6 = (uint32_t)(&CCM_PLL_CTRL19), /*!< PDF6 Gate.*/ + ccmPllGatePfd7 = (uint32_t)(&CCM_PLL_CTRL20), /*!< PDF7 Gate.*/ + ccmPllGateEnet = (uint32_t)(&CCM_PLL_CTRL21), /*!< Ethernet PLL Gate.*/ + ccmPllGateEnet500m = (uint32_t)(&CCM_PLL_CTRL22), /*!< Ethernet 500M PLL Gate.*/ + ccmPllGateEnet250m = (uint32_t)(&CCM_PLL_CTRL23), /*!< Ethernet 250M PLL Gate.*/ + ccmPllGateEnet125m = (uint32_t)(&CCM_PLL_CTRL24), /*!< Ethernet 125M PLL Gate.*/ + ccmPllGateEnet100m = (uint32_t)(&CCM_PLL_CTRL25), /*!< Ethernet 100M PLL Gate.*/ + ccmPllGateEnet50m = (uint32_t)(&CCM_PLL_CTRL26), /*!< Ethernet 50M PLL Gate.*/ + ccmPllGateEnet40m = (uint32_t)(&CCM_PLL_CTRL27), /*!< Ethernet 40M PLL Gate.*/ + ccmPllGateEnet25m = (uint32_t)(&CCM_PLL_CTRL28), /*!< Ethernet 25M PLL Gate.*/ + ccmPllGateAudio = (uint32_t)(&CCM_PLL_CTRL29), /*!< AUDIO PLL Gate.*/ + ccmPllGateAudioDiv1 = (uint32_t)(&CCM_PLL_CTRL30), /*!< AUDIO PLL Div1 Gate.*/ + ccmPllGateVideo = (uint32_t)(&CCM_PLL_CTRL31), /*!< VIDEO PLL Gate.*/ + ccmPllGateVideoDiv1 = (uint32_t)(&CCM_PLL_CTRL32), /*!< VIDEO PLL Div1 Gate.*/ +}; + +/*! @brief CCM CCGR gate control. */ +enum _ccm_ccgr_gate +{ + ccmCcgrGateSimWakeup = (uint32_t)(&CCM_CCGR9), /*!< Wakeup Mix Bus Clock Gate.*/ + ccmCcgrGateIpmux1 = (uint32_t)(&CCM_CCGR10), /*!< IOMUX1 Clock Gate.*/ + ccmCcgrGateIpmux2 = (uint32_t)(&CCM_CCGR11), /*!< IOMUX2 Clock Gate.*/ + ccmCcgrGateIpmux3 = (uint32_t)(&CCM_CCGR12), /*!< IPMUX3 Clock Gate.*/ + ccmCcgrGateOcram = (uint32_t)(&CCM_CCGR17), /*!< OCRAM Clock Gate.*/ + ccmCcgrGateOcramS = (uint32_t)(&CCM_CCGR18), /*!< OCRAM S Clock Gate.*/ + ccmCcgrGateQspi = (uint32_t)(&CCM_CCGR21), /*!< QSPI Clock Gate.*/ + ccmCcgrGateAdc = (uint32_t)(&CCM_CCGR32), /*!< ADC Clock Gate.*/ + ccmCcgrGateRdc = (uint32_t)(&CCM_CCGR38), /*!< RDC Clock Gate.*/ + ccmCcgrGateMu = (uint32_t)(&CCM_CCGR39), /*!< MU Clock Gate.*/ + ccmCcgrGateSemaHs = (uint32_t)(&CCM_CCGR40), /*!< SEMA HS Clock Gate.*/ + ccmCcgrGateSema1 = (uint32_t)(&CCM_CCGR64), /*!< SEMA1 Clock Gate.*/ + ccmCcgrGateSema2 = (uint32_t)(&CCM_CCGR65), /*!< SEMA2 Clock Gate.*/ + ccmCcgrGateCan1 = (uint32_t)(&CCM_CCGR116), /*!< CAN1 Clock Gate.*/ + ccmCcgrGateCan2 = (uint32_t)(&CCM_CCGR117), /*!< CAN2 Clock Gate.*/ + ccmCcgrGateEcspi1 = (uint32_t)(&CCM_CCGR120), /*!< ECSPI1 Clock Gate.*/ + ccmCcgrGateEcspi2 = (uint32_t)(&CCM_CCGR121), /*!< ECSPI2 Clock Gate.*/ + ccmCcgrGateEcspi3 = (uint32_t)(&CCM_CCGR122), /*!< ECSPI3 Clock Gate.*/ + ccmCcgrGateEcspi4 = (uint32_t)(&CCM_CCGR123), /*!< ECSPI4 Clock Gate.*/ + ccmCcgrGateGpt1 = (uint32_t)(&CCM_CCGR124), /*!< GPT1 Clock Gate.*/ + ccmCcgrGateGpt2 = (uint32_t)(&CCM_CCGR125), /*!< GPT2 Clock Gate.*/ + ccmCcgrGateGpt3 = (uint32_t)(&CCM_CCGR126), /*!< GPT3 Clock Gate.*/ + ccmCcgrGateGpt4 = (uint32_t)(&CCM_CCGR127), /*!< GPT4 Clock Gate.*/ + ccmCcgrGateI2c1 = (uint32_t)(&CCM_CCGR136), /*!< I2C1 Clock Gate.*/ + ccmCcgrGateI2c2 = (uint32_t)(&CCM_CCGR137), /*!< I2C2 Clock Gate.*/ + ccmCcgrGateI2c3 = (uint32_t)(&CCM_CCGR138), /*!< I2C3 Clock Gate.*/ + ccmCcgrGateI2c4 = (uint32_t)(&CCM_CCGR139), /*!< I2C4 Clock Gate.*/ + ccmCcgrGateUart1 = (uint32_t)(&CCM_CCGR148), /*!< UART1 Clock Gate.*/ + ccmCcgrGateUart2 = (uint32_t)(&CCM_CCGR149), /*!< UART2 Clock Gate.*/ + ccmCcgrGateUart3 = (uint32_t)(&CCM_CCGR150), /*!< UART3 Clock Gate.*/ + ccmCcgrGateUart4 = (uint32_t)(&CCM_CCGR151), /*!< UART4 Clock Gate.*/ + ccmCcgrGateUart5 = (uint32_t)(&CCM_CCGR152), /*!< UART5 Clock Gate.*/ + ccmCcgrGateUart6 = (uint32_t)(&CCM_CCGR153), /*!< UART6 Clock Gate.*/ + ccmCcgrGateUart7 = (uint32_t)(&CCM_CCGR154), /*!< UART7 Clock Gate.*/ + ccmCcgrGateWdog1 = (uint32_t)(&CCM_CCGR156), /*!< WDOG1 Clock Gate.*/ + ccmCcgrGateWdog2 = (uint32_t)(&CCM_CCGR157), /*!< WDOG2 Clock Gate.*/ + ccmCcgrGateWdog3 = (uint32_t)(&CCM_CCGR158), /*!< WDOG3 Clock Gate.*/ + ccmCcgrGateWdog4 = (uint32_t)(&CCM_CCGR159), /*!< WDOG4 Clock Gate.*/ + ccmCcgrGateGpio1 = (uint32_t)(&CCM_CCGR160), /*!< GPIO1 Clock Gate.*/ + ccmCcgrGateGpio2 = (uint32_t)(&CCM_CCGR161), /*!< GPIO2 Clock Gate.*/ + ccmCcgrGateGpio3 = (uint32_t)(&CCM_CCGR162), /*!< GPIO3 Clock Gate.*/ + ccmCcgrGateGpio4 = (uint32_t)(&CCM_CCGR163), /*!< GPIO4 Clock Gate.*/ + ccmCcgrGateGpio5 = (uint32_t)(&CCM_CCGR164), /*!< GPIO5 Clock Gate.*/ + ccmCcgrGateGpio6 = (uint32_t)(&CCM_CCGR165), /*!< GPIO6 Clock Gate.*/ + ccmCcgrGateGpio7 = (uint32_t)(&CCM_CCGR166), /*!< GPIO7 Clock Gate.*/ + ccmCcgrGateIomux = (uint32_t)(&CCM_CCGR168), /*!< IOMUX Clock Gate.*/ + ccmCcgrGateIomuxLpsr = (uint32_t)(&CCM_CCGR169), /*!< IOMUX LPSR Clock Gate.*/ +}; + +/*! @brief CCM gate control value. */ +enum _ccm_gate_value +{ + ccmClockNotNeeded = 0x0U, /*!< Clock always disabled.*/ + ccmClockNeededRun = 0x1111U, /*!< Clock enabled when CPU is running.*/ + ccmClockNeededRunWait = 0x2222U, /*!< Clock enabled when CPU is running or in WAIT mode.*/ + ccmClockNeededAll = 0x3333U, /*!< Clock always enabled.*/ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name CCM Root Setting + * @{ + */ + +/*! + * @brief Set clock root mux + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param mux Root mux value (see @ref _ccm_rootmux_xxx enumeration) + */ +static inline void CCM_SetRootMux(CCM_Type * base, uint32_t ccmRoot, uint32_t mux) +{ + CCM_REG(ccmRoot) = (CCM_REG(ccmRoot) & (~CCM_TARGET_ROOT_MUX_MASK)) | + CCM_TARGET_ROOT_MUX(mux); +} + +/*! + * @brief Get clock root mux + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @return root mux value (see @ref _ccm_rootmux_xxx enumeration) + */ +static inline uint32_t CCM_GetRootMux(CCM_Type * base, uint32_t ccmRoot) +{ + return (CCM_REG(ccmRoot) & CCM_TARGET_ROOT_MUX_MASK) >> CCM_TARGET_ROOT_MUX_SHIFT; +} + +/*! + * @brief Enable clock root + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + */ +static inline void CCM_EnableRoot(CCM_Type * base, uint32_t ccmRoot) +{ + CCM_REG_SET(ccmRoot) = CCM_TARGET_ROOT_SET_ENABLE_MASK; +} + +/*! + * @brief Disable clock root + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + */ +static inline void CCM_DisableRoot(CCM_Type * base, uint32_t ccmRoot) +{ + CCM_REG_CLR(ccmRoot) = CCM_TARGET_ROOT_CLR_ENABLE_MASK; +} + +/*! + * @brief Check whether clock root is enabled + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @return CCM root enabled or not. + * - true: Clock root is enabled. + * - false: Clock root is disabled. + */ +static inline bool CCM_IsRootEnabled(CCM_Type * base, uint32_t ccmRoot) +{ + return (bool)(CCM_REG(ccmRoot) & CCM_TARGET_ROOT_ENABLE_MASK); +} + +/*! + * @brief Set root clock divider + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param pre Pre divider value (0-7, divider=n+1) + * @param post Post divider value (0-63, divider=n+1) + */ +void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t pre, uint32_t post); + +/*! + * @brief Get root clock divider + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param pre Pointer to pre divider value store address + * @param post Pointer to post divider value store address + */ +void CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRoot, uint32_t *pre, uint32_t *post); + +/*! + * @brief Update clock root in one step, for dynamical clock switching + * + * @param base CCM base pointer. + * @param ccmRoot Root control (see @ref _ccm_root_control enumeration) + * @param root mux value (see @ref _ccm_rootmux_xxx enumeration) + * @param pre Pre divider value (0-7, divider=n+1) + * @param post Post divider value (0-63, divider=n+1) + */ +void CCM_UpdateRoot(CCM_Type * base, uint32_t ccmRoot, uint32_t mux, uint32_t pre, uint32_t post); + +/*@}*/ + +/*! + * @name CCM Gate Control + * @{ + */ + +/*! + * @brief Set PLL or CCGR gate control + * + * @param base CCM base pointer. + * @param ccmGate Gate control (see @ref _ccm_pll_gate and @ref _ccm_ccgr_gate enumeration) + * @param control Gate control value (see @ref _ccm_gate_value) + */ +static inline void CCM_ControlGate(CCM_Type * base, uint32_t ccmGate, uint32_t control) +{ + CCM_REG(ccmGate) = control; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CCM_IMX7D_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX7D/drivers/clock_freq.c b/devices/MCIMX7D/drivers/clock_freq.c new file mode 100644 index 000000000..5c72d24e3 --- /dev/null +++ b/devices/MCIMX7D/drivers/clock_freq.c @@ -0,0 +1,267 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#include "clock_freq.h" +#include "ccm_imx7d.h" +#include "ccm_analog_imx7d.h" + +/*FUNCTION********************************************************************** + * + * Function Name : get_gpt_clock_freq + * Description : Get clock frequency applies to the GPT module + * + *END**************************************************************************/ +uint32_t get_gpt_clock_freq(GPT_Type *base) +{ + uint32_t root; + uint32_t hz; + uint32_t pre, post; + + switch ((uint32_t)base) { + case GPT3_BASE: + root = CCM_GetRootMux(CCM, ccmRootGpt3); + CCM_GetRootDivider(CCM, ccmRootGpt3, &pre, &post); + break; + case GPT4_BASE: + root = CCM_GetRootMux(CCM, ccmRootGpt4); + CCM_GetRootDivider(CCM, ccmRootGpt4, &pre, &post); + break; + default: + return 0; + } + + switch (root) { + case ccmRootmuxGptOsc24m: + hz = 24000000; + break; + case ccmRootmuxGptSysPllPfd0: + hz = CCM_ANALOG_GetPfdFreq(CCM_ANALOG, ccmAnalogPfd0Frac); + break; + default: + return 0; + } + + return hz / (pre + 1) / (post + 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : get_ecspi_clock_freq + * Description : Get clock frequency applys to the ECSPI module + * + *END**************************************************************************/ +uint32_t get_ecspi_clock_freq(ECSPI_Type *base) +{ + uint32_t root; + uint32_t hz; + uint32_t pre, post; + + switch ((uint32_t)base) { + case ECSPI1_BASE: + root = CCM_GetRootMux(CCM, ccmRootEcspi1); + CCM_GetRootDivider(CCM, ccmRootEcspi1, &pre, &post); + break; + case ECSPI2_BASE: + root = CCM_GetRootMux(CCM, ccmRootEcspi2); + CCM_GetRootDivider(CCM, ccmRootEcspi2, &pre, &post); + break; + default: + return 0; + } + + switch (root) { + case ccmRootmuxEcspiOsc24m: + hz = 24000000; + break; + case ccmRootmuxEcspiSysPllPfd4: + hz = CCM_ANALOG_GetPfdFreq(CCM_ANALOG, ccmAnalogPfd4Frac); + break; + default: + return 0; + } + + return hz / (pre + 1) / (post + 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : get_flexcan_clock_freq + * Description : Get clock frequency applys to the FLEXCAN module + * + *END**************************************************************************/ +uint32_t get_flexcan_clock_freq(CAN_Type *base) +{ + uint32_t root; + uint32_t hz; + uint32_t pre, post; + + switch ((uint32_t)base) { + case CAN1_BASE: + root = CCM_GetRootMux(CCM, ccmRootCan1); + CCM_GetRootDivider(CCM, ccmRootCan1, &pre, &post); + break; + case CAN2_BASE: + root = CCM_GetRootMux(CCM, ccmRootCan2); + CCM_GetRootDivider(CCM, ccmRootCan2, &pre, &post); + break; + default: + return 0; + } + + switch (root) { + case ccmRootmuxCanOsc24m: + hz = 24000000; + break; + case ccmRootmuxCanSysPllDiv4: + hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG) >> 2; + break; + case ccmRootmuxCanSysPllDiv1: + hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG); + break; + default: + return 0; + } + + return hz / (pre + 1) / (post + 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : get_I2C_clock_freq + * Description : Get clock frequency applys to the I2C module + * + *END**************************************************************************/ +uint32_t get_i2c_clock_freq(I2C_Type *base) +{ + uint32_t root; + uint32_t hz; + uint32_t pre, post; + + switch ((uint32_t)base) { + case I2C1_BASE: + root = CCM_GetRootMux(CCM, ccmRootI2c1); + CCM_GetRootDivider(CCM, ccmRootI2c1, &pre, &post); + break; + case I2C2_BASE: + root = CCM_GetRootMux(CCM, ccmRootI2c2); + CCM_GetRootDivider(CCM, ccmRootI2c2, &pre, &post); + break; + case I2C3_BASE: + root = CCM_GetRootMux(CCM, ccmRootI2c3); + CCM_GetRootDivider(CCM, ccmRootI2c3, &pre, &post); + break; + case I2C4_BASE: + root = CCM_GetRootMux(CCM, ccmRootI2c4); + CCM_GetRootDivider(CCM, ccmRootI2c4, &pre, &post); + break; + default: + return 0; + } + + switch (root) { + case ccmRootmuxI2cOsc24m: + hz = 24000000; + break; + case ccmRootmuxI2cSysPllDiv4: + hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG) >> 2; + break; + default: + return 0; + } + + return hz / (pre + 1) / (post + 1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : get_uart_clock_freq + * Description : Get clock frequency applys to the UART module + * + *END**************************************************************************/ +uint32_t get_uart_clock_freq(UART_Type *base) +{ + uint32_t root; + uint32_t hz; + uint32_t pre, post; + + switch ((uint32_t)base) { + case UART1_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart1); + CCM_GetRootDivider(CCM, ccmRootUart1, &pre, &post); + break; + case UART2_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart2); + CCM_GetRootDivider(CCM, ccmRootUart2, &pre, &post); + break; + case UART3_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart3); + CCM_GetRootDivider(CCM, ccmRootUart3, &pre, &post); + break; + case UART4_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart4); + CCM_GetRootDivider(CCM, ccmRootUart4, &pre, &post); + break; + case UART5_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart5); + CCM_GetRootDivider(CCM, ccmRootUart5, &pre, &post); + break; + case UART6_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart6); + CCM_GetRootDivider(CCM, ccmRootUart6, &pre, &post); + break; + case UART7_BASE: + root = CCM_GetRootMux(CCM, ccmRootUart7); + CCM_GetRootDivider(CCM, ccmRootUart7, &pre, &post); + break; + default: + return 0; + } + + switch (root) { + case ccmRootmuxUartOsc24m: + hz = 24000000; + break; + case ccmRootmuxUartSysPllDiv2: + hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG) >> 1; + break; + case ccmRootmuxUartSysPllDiv1: + hz = CCM_ANALOG_GetSysPllFreq(CCM_ANALOG); + break; + default: + return 0; + } + + return hz / (pre + 1) / (post + 1); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX7D/drivers/clock_freq.h b/devices/MCIMX7D/drivers/clock_freq.h new file mode 100644 index 000000000..38602620a --- /dev/null +++ b/devices/MCIMX7D/drivers/clock_freq.h @@ -0,0 +1,99 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this + * list of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE + * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __CLOCK_FREQ_H__ +#define __CLOCK_FREQ_H__ + +#include "device_imx.h" + +/*! + * @addtogroup clock_freq_helper + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @brief Get clock frequency applies to the GPT module + * + * @param base GPT base pointer. + * @return clock frequency (in HZ) applies to the GPT module + */ +uint32_t get_gpt_clock_freq(GPT_Type *base); + +/*! + * @brief Get clock frequency applies to the ECSPI module + * + * @param base ECSPI base pointer. + * @return clock frequency (in HZ) applies to the ECSPI module + */ +uint32_t get_ecspi_clock_freq(ECSPI_Type *base); + +/*! + * @brief Get clock frequency applies to the FLEXCAN module + * + * @param base CAN base pointer. + * @return clock frequency (in HZ) applies to the FLEXCAN module + */ +uint32_t get_flexcan_clock_freq(CAN_Type *base); + +/*! + * @brief Get clock frequency applies to the I2C module + * + * @param base I2C base pointer. + * @return clock frequency (in HZ) applies to the I2C module + */ +uint32_t get_i2c_clock_freq(I2C_Type *base); + +/*! + * @brief Get clock frequency applies to the UART module + * + * @param base UART base pointer. + * @return clock frequency (in HZ) applies to the UART module + */ +uint32_t get_uart_clock_freq(UART_Type *base); + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __CLOCK_FREQ_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/devices/MCIMX7D/drivers/rdc_defs_imx7d.h b/devices/MCIMX7D/drivers/rdc_defs_imx7d.h new file mode 100644 index 000000000..294d0ad64 --- /dev/null +++ b/devices/MCIMX7D/drivers/rdc_defs_imx7d.h @@ -0,0 +1,222 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RDC_DEFS_IMX7D__ +#define __RDC_DEFS_IMX7D__ + +/*! + * @addtogroup rdc_def_imx7d + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief RDC master assignment. */ +enum _rdc_mda +{ + rdcMdaA7 = 0U, /*!< ARM Cortex-A7 RDC Master. */ + rdcMdaM4 = 1U, /*!< ARM Cortex-M4 RDC Master. */ + rdcMdaPcie = 2U, /*!< PCIe RDC Master. */ + rdcMdaCsi = 3U, /*!< CSI RDC Master. */ + rdcMdaEpdc = 4U, /*!< EPDC RDC Master. */ + rdcMdaLcdif = 5U, /*!< LCDIF RDC Master. */ + rdcMdaDisplayPort = 6U, /*!< DISPLAY PORT RDC Master. */ + rdcMdaPxp = 7U, /*!< PXP RDC Master. */ + rdcMdaCoresight = 8U, /*!< CORESIGHT RDC Master. */ + rdcMdaDap = 9U, /*!< DAP RDC Master. */ + rdcMdaCaam = 10U, /*!< CAAM RDC Master. */ + rdcMdaSdmaPeriph = 11U, /*!< SDMA PERIPHERAL RDC Master. */ + rdcMdaSdmaBurst = 12U, /*!< SDMA BURST RDC Master. */ + rdcMdaApbhdma = 13U, /*!< APBH DMA RDC Master. */ + rdcMdaRawnand = 14U, /*!< RAW NAND RDC Master. */ + rdcMdaUsdhc1 = 15U, /*!< USDHC1 RDC Master. */ + rdcMdaUsdhc2 = 16U, /*!< USDHC2 RDC Master. */ + rdcMdaUsdhc3 = 17U, /*!< USDHC3 RDC Master. */ + rdcMdaNc1 = 18U, /*!< NC1 RDC Master. */ + rdcMdaUsb = 19U, /*!< USB RDC Master. */ + rdcMdaNc2 = 20U, /*!< NC2 RDC Master. */ + rdcMdaTest = 21U, /*!< TEST RDC Master. */ + rdcMdaEnet1Tx = 22U, /*!< Ethernet1 Tx RDC Master. */ + rdcMdaEnet1Rx = 23U, /*!< Ethernet1 Rx RDC Master. */ + rdcMdaEnet2Tx = 24U, /*!< Ethernet2 Tx RDC Master. */ + rdcMdaEnet2Rx = 25U, /*!< Ethernet2 Rx RDC Master. */ + rdcMdaSdmaPort = 26U, /*!< SDMA PORT RDC Master. */ +}; + +/*! @brief RDC peripheral assignment. */ +enum _rdc_pdap +{ + rdcPdapGpio1 = 0U, /*!< GPIO1 RDC Peripheral. */ + rdcPdapGpio2 = 1U, /*!< GPIO2 RDC Peripheral. */ + rdcPdapGpio3 = 2U, /*!< GPIO3 RDC Peripheral. */ + rdcPdapGpio4 = 3U, /*!< GPIO4 RDC Peripheral. */ + rdcPdapGpio5 = 4U, /*!< GPIO5 RDC Peripheral. */ + rdcPdapGpio6 = 5U, /*!< GPIO6 RDC Peripheral. */ + rdcPdapGpio7 = 6U, /*!< GPIO7 RDC Peripheral. */ + rdcPdapIomuxcLpsrGpr = 7U, /*!< IOMXUC LPSR GPR RDC Peripheral. */ + rdcPdapWdog1 = 8U, /*!< WDOG1 RDC Peripheral. */ + rdcPdapWdog2 = 9U, /*!< WDOG2 RDC Peripheral. */ + rdcPdapWdog3 = 10U, /*!< WDOG3 RDC Peripheral. */ + rdcPdapWdog4 = 11U, /*!< WDOG4 RDC Peripheral. */ + rdcPdapIomuxcLpsr = 12U, /*!< IOMUXC LPSR RDC Peripheral. */ + rdcPdapGpt1 = 13U, /*!< GPT1 RDC Peripheral. */ + rdcPdapGpt2 = 14U, /*!< GPT2 RDC Peripheral. */ + rdcPdapGpt3 = 15U, /*!< GPT3 RDC Peripheral. */ + rdcPdapGpt4 = 16U, /*!< GPT4 RDC Peripheral. */ + rdcPdapRomcp = 17U, /*!< ROMCP RDC Peripheral. */ + rdcPdapKpp = 18U, /*!< KPP RDC Peripheral. */ + rdcPdapIomuxc = 19U, /*!< IOMUXC RDC Peripheral. */ + rdcPdapIomuxcGpr = 20U, /*!< IOMUXC GPR RDC Peripheral. */ + rdcPdapOcotpCtrl = 21U, /*!< OCOTP CTRL RDC Peripheral. */ + rdcPdapAnatopDig = 22U, /*!< ANATOPDIG RDC Peripheral. */ + rdcPdapSnvs = 23U, /*!< SNVS RDC Peripheral. */ + rdcPdapCcm = 24U, /*!< CCM RDC Peripheral. */ + rdcPdapSrc = 25U, /*!< SRC RDC Peripheral. */ + rdcPdapGpc = 26U, /*!< GPC RDC Peripheral. */ + rdcPdapSemaphore1 = 27U, /*!< SEMAPHORE1 RDC Peripheral. */ + rdcPdapSemaphore2 = 28U, /*!< SEMAPHORE2 RDC Peripheral. */ + rdcPdapRdc = 29U, /*!< RDC RDC Peripheral. */ + rdcPdapCsu = 30U, /*!< CSU RDC Peripheral. */ + rdcPdapReserved1 = 31U, /*!< Reserved1 RDC Peripheral. */ + rdcPdapReserved2 = 32U, /*!< Reserved2 RDC Peripheral. */ + rdcPdapAdc1 = 33U, /*!< ADC1 RDC Peripheral. */ + rdcPdapAdc2 = 34U, /*!< ADC2 RDC Peripheral. */ + rdcPdapEcspi4 = 35U, /*!< ECSPI4 RDC Peripheral. */ + rdcPdapFlexTimer1 = 36U, /*!< FTM1 RDC Peripheral. */ + rdcPdapFlexTimer2 = 37U, /*!< FTM2 RDC Peripheral. */ + rdcPdapPwm1 = 38U, /*!< PWM1 RDC Peripheral. */ + rdcPdapPwm2 = 39U, /*!< PWM2 RDC Peripheral. */ + rdcPdapPwm3 = 40U, /*!< PWM3 RDC Peripheral. */ + rdcPdapPwm4 = 41U, /*!< PWM4 RDC Peripheral. */ + rdcPdapSystemCounterRead = 42U, /*!< System Counter Read RDC Peripheral. */ + rdcPdapSystemCounterCompare = 43U, /*!< System Counter Compare RDC Peripheral. */ + rdcPdapSystemCounterControl = 44U, /*!< System Counter Control RDC Peripheral. */ + rdcPdapPcie = 45U, /*!< PCIE RDC Peripheral. */ + rdcPdapReserved3 = 46U, /*!< Reserved3 RDC Peripheral. */ + rdcPdapEpdc = 47U, /*!< EPDC RDC Peripheral. */ + rdcPdapPxp = 48U, /*!< PXP RDC Peripheral. */ + rdcPdapCsi = 49U, /*!< CSI RDC Peripheral. */ + rdcPdapReserved4 = 50U, /*!< Reserved4 RDC Peripheral. */ + rdcPdapLcdif = 51U, /*!< LCDIF RDC Peripheral. */ + rdcPdapReserved5 = 52U, /*!< Reserved5 RDC Peripheral. */ + rdcPdapMipiCsi = 53U, /*!< MIPI CSI RDC Peripheral. */ + rdcPdapMipiDsi = 54U, /*!< MIPI DSI RDC Peripheral. */ + rdcPdapReserved6 = 55U, /*!< Reserved6 RDC Peripheral. */ + rdcPdapTzasc = 56U, /*!< TZASC RDC Peripheral. */ + rdcPdapDdrPhy = 57U, /*!< DDR PHY RDC Peripheral. */ + rdcPdapDdrc = 58U, /*!< DDRC RDC Peripheral. */ + rdcPdapReserved7 = 59U, /*!< Reserved7 RDC Peripheral. */ + rdcPdapPerfMon1 = 60U, /*!< PerfMon1 RDC Peripheral. */ + rdcPdapPerfMon2 = 61U, /*!< PerfMon2 RDC Peripheral. */ + rdcPdapAxi = 62U, /*!< AXI RDC Peripheral. */ + rdcPdapQosc = 63U, /*!< QOSC RDC Peripheral. */ + rdcPdapFlexCan1 = 64U, /*!< FLEXCAN1 RDC Peripheral. */ + rdcPdapFlexCan2 = 65U, /*!< FLEXCAN2 RDC Peripheral. */ + rdcPdapI2c1 = 66U, /*!< I2C1 RDC Peripheral. */ + rdcPdapI2c2 = 67U, /*!< I2C2 RDC Peripheral. */ + rdcPdapI2c3 = 68U, /*!< I2C3 RDC Peripheral. */ + rdcPdapI2c4 = 69U, /*!< I2C4 RDC Peripheral. */ + rdcPdapUart4 = 70U, /*!< UART4 RDC Peripheral. */ + rdcPdapUart5 = 71U, /*!< UART5 RDC Peripheral. */ + rdcPdapUart6 = 72U, /*!< UART6 RDC Peripheral. */ + rdcPdapUart7 = 73U, /*!< UART7 RDC Peripheral. */ + rdcPdapMuA = 74U, /*!< MUA RDC Peripheral. */ + rdcPdapMuB = 75U, /*!< MUB RDC Peripheral. */ + rdcPdapSemaphoreHs = 76U, /*!< SEMAPHORE HS RDC Peripheral. */ + rdcPdapUsbPl301 = 77U, /*!< USB PL301 RDC Peripheral. */ + rdcPdapReserved8 = 78U, /*!< Reserved8 RDC Peripheral. */ + rdcPdapReserved9 = 79U, /*!< Reserved9 RDC Peripheral. */ + rdcPdapReserved10 = 80U, /*!< Reserved10 RDC Peripheral. */ + rdcPdapUSB1Otg1 = 81U, /*!< USB2 OTG1 RDC Peripheral. */ + rdcPdapUSB2Otg2 = 82U, /*!< USB2 OTG2 RDC Peripheral. */ + rdcPdapUSB3Host = 83U, /*!< USB3 HOST RDC Peripheral. */ + rdcPdapUsdhc1 = 84U, /*!< USDHC1 RDC Peripheral. */ + rdcPdapUsdhc2 = 85U, /*!< USDHC2 RDC Peripheral. */ + rdcPdapUsdhc3 = 86U, /*!< USDHC3 RDC Peripheral. */ + rdcPdapReserved11 = 87U, /*!< Reserved11 RDC Peripheral. */ + rdcPdapReserved12 = 88U, /*!< Reserved12 RDC Peripheral. */ + rdcPdapSim1 = 89U, /*!< SIM1 RDC Peripheral. */ + rdcPdapSim2 = 90U, /*!< SIM2 RDC Peripheral. */ + rdcPdapQspi = 91U, /*!< QSPI RDC Peripheral. */ + rdcPdapWeim = 92U, /*!< WEIM RDC Peripheral. */ + rdcPdapSdma = 93U, /*!< SDMA RDC Peripheral. */ + rdcPdapEnet1 = 94U, /*!< Eneternet1 RDC Peripheral. */ + rdcPdapEnet2 = 95U, /*!< Eneternet2 RDC Peripheral. */ + rdcPdapReserved13 = 96U, /*!< Reserved13 RDC Peripheral. */ + rdcPdapReserved14 = 97U, /*!< Reserved14 RDC Peripheral. */ + rdcPdapEcspi1 = 98U, /*!< ECSPI1 RDC Peripheral. */ + rdcPdapEcspi2 = 99U, /*!< ECSPI2 RDC Peripheral. */ + rdcPdapEcspi3 = 100U, /*!< ECSPI3 RDC Peripheral. */ + rdcPdapReserved15 = 101U, /*!< Reserved15 RDC Peripheral. */ + rdcPdapUart1 = 102U, /*!< UART1 RDC Peripheral. */ + rdcPdapReserved16 = 103U, /*!< Reserved16 RDC Peripheral. */ + rdcPdapUart3 = 104U, /*!< UART3 RDC Peripheral. */ + rdcPdapUart2 = 105U, /*!< UART2 RDC Peripheral. */ + rdcPdapSai1 = 106U, /*!< SAI1 RDC Peripheral. */ + rdcPdapSai2 = 107U, /*!< SAI2 RDC Peripheral. */ + rdcPdapSai3 = 108U, /*!< SAI3 RDC Peripheral. */ + rdcPdapReserved17 = 109U, /*!< Reserved17 RDC Peripheral. */ + rdcPdapReserved18 = 110U, /*!< Reserved18 RDC Peripheral. */ + rdcPdapSpba = 111U, /*!< SPBA RDC Peripheral. */ + rdcPdapDap = 112U, /*!< DAP RDC Peripheral. */ + rdcPdapReserved19 = 113U, /*!< Reserved19 RDC Peripheral. */ + rdcPdapReserved20 = 114U, /*!< Reserved20 RDC Peripheral. */ + rdcPdapReserved21 = 115U, /*!< Reserved21 RDC Peripheral. */ + rdcPdapCaam = 116U, /*!< CAAM RDC Peripheral. */ + rdcPdapReserved22 = 117U, /*!< Reserved22 RDC Peripheral. */ +}; + +/*! @brief RDC memory region. */ +enum _rdc_mr +{ + rdcMrMmdc = 0U, /*!< alignment 4096 */ + rdcMrMmdcLast = 7U, /*!< alignment 4096 */ + rdcMrQspi = 8U, /*!< alignment 4096 */ + rdcMrQspiLast = 15U, /*!< alignment 4096 */ + rdcMrWeim = 16U, /*!< alignment 4096 */ + rdcMrWeimLast = 23U, /*!< alignment 4096 */ + rdcMrPcie = 24U, /*!< alignment 4096 */ + rdcMrPcieLast = 31U, /*!< alignment 4096 */ + rdcMrOcram = 32U, /*!< alignment 128 */ + rdcMrOcramLast = 36U, /*!< alignment 128 */ + rdcMrOcramS = 37U, /*!< alignment 128 */ + rdcMrOcramSLast = 41U, /*!< alignment 128 */ + rdcMrOcramEpdc = 42U, /*!< alignment 128 */ + rdcMrOcramEpdcLast = 46U, /*!< alignment 128 */ + rdcMrOcramPxp = 47U, /*!< alignment 128 */ + rdcMrOcramPxpLast = 51U, /*!< alignment 128 */ +}; + +#endif /* __RDC_DEFS_IMX7D__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/ecspi_imx/ecspi.c b/drivers/ecspi_imx/ecspi.c new file mode 100644 index 000000000..2a3a0c163 --- /dev/null +++ b/drivers/ecspi_imx/ecspi.c @@ -0,0 +1,205 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "ecspi.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * eCSPI Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_Init + * Description : Initializes the eCSPI module according to the specified + * parameters in the initConfig. + * + *END**************************************************************************/ +void ECSPI_Init(ECSPI_Type* base, const ecspi_init_config_t* initConfig) +{ + /* Disable eCSPI module */ + ECSPI_CONREG_REG(base) = 0; + + /* Enable the eCSPI module before write to other registers */ + ECSPI_Enable(base); + + /* eCSPI CONREG Configuration */ + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_BURST_LENGTH(initConfig->burstLength) | + ECSPI_CONREG_CHANNEL_SELECT(initConfig->channelSelect); + ECSPI_CONREG_REG(base) |= initConfig->ecspiAutoStart ? ECSPI_CONREG_SMC_MASK : 0; + + /* eCSPI CONFIGREG Configuration */ + ECSPI_CONFIGREG_REG(base) = ECSPI_CONFIGREG_SCLK_PHA(((initConfig->clockPhase) & 1) << (initConfig->channelSelect)) | + ECSPI_CONFIGREG_SCLK_POL(((initConfig->clockPolarity) & 1) << (initConfig->channelSelect)); + + /* Master or Slave mode Configuration */ + if(initConfig->mode == ecspiMasterMode) + { + /* Set baud rate in bits per second */ + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_CHANNEL_MODE(1 << (initConfig->channelSelect)); + ECSPI_SetBaudRate(base, initConfig->clockRate, initConfig->baudRate); + } + else + ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_CHANNEL_MODE(1 << (initConfig->channelSelect)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetSampClockSource + * Description : Configure the clock source for the sample period counter. + * + *END**************************************************************************/ +void ECSPI_SetSampClockSource(ECSPI_Type* base, uint32_t source) +{ + /* Select the clock source */ + if(source == ecspiSclk) + ECSPI_PERIODREG_REG(base) &= ~ECSPI_PERIODREG_CSRC_MASK; + else + ECSPI_PERIODREG_REG(base) |= ECSPI_PERIODREG_CSRC_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetBaudRate + * Description : Calculated the eCSPI baud rate in bits per second. + * + *END**************************************************************************/ +uint32_t ECSPI_SetBaudRate(ECSPI_Type* base, uint32_t sourceClockInHz, uint32_t bitsPerSec) +{ + uint32_t div, pre_div; + uint32_t post_baud; /* baud rate after post divider */ + uint32_t pre_baud; /* baud rate before pre divider */ + + if(sourceClockInHz <= bitsPerSec) + { + ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_PRE_DIVIDER_MASK; + ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_POST_DIVIDER_MASK; + return sourceClockInHz; + } + + div = sourceClockInHz / bitsPerSec; + if(div < 16) /* pre_divider is enough */ + { + if((sourceClockInHz - bitsPerSec * div) < ((bitsPerSec * (div + 1)) - sourceClockInHz)) + pre_div = div - 1; /* pre_divider value is one less than the real divider */ + else + pre_div = div; + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_PRE_DIVIDER_MASK)) | + ECSPI_CONREG_PRE_DIVIDER(pre_div); + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_POST_DIVIDER_MASK)) | + ECSPI_CONREG_POST_DIVIDER(0); + return sourceClockInHz / (pre_div + 1); + } + + pre_baud = bitsPerSec * 16; + for(div = 1; div < 16; div++) + { + post_baud = sourceClockInHz >> div; + if(post_baud < pre_baud) + break; + } + + if(div == 16) /* divider is not enough, set the biggest ones */ + { + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_PRE_DIVIDER(15); + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_POST_DIVIDER(15); + return post_baud / 16; + } + + /* find the closed one */ + if((post_baud - bitsPerSec * (post_baud / bitsPerSec)) < ((bitsPerSec * ((post_baud / bitsPerSec) + 1)) - post_baud)) + pre_div = post_baud / bitsPerSec - 1; + else + pre_div = post_baud / bitsPerSec; + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_PRE_DIVIDER_MASK)) | + ECSPI_CONREG_PRE_DIVIDER(pre_div); + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_POST_DIVIDER_MASK)) | + ECSPI_CONREG_POST_DIVIDER(div); + return post_baud / (pre_div + 1); +} + +/******************************************************************************* + * DMA management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetDMACmd + * Description : Enable or disable the specified DMA Source. + * + *END**************************************************************************/ +void ECSPI_SetDMACmd(ECSPI_Type* base, uint32_t source, bool enable) +{ + /* Configure the DAM source */ + if(enable) + ECSPI_DMAREG_REG(base) |= ((uint32_t)(1 << source)); + else + ECSPI_DMAREG_REG(base) &= ~((uint32_t)(1 << source)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetFIFOThreshold + * Description : Set the RXFIFO or TXFIFO threshold. + * + *END**************************************************************************/ +void ECSPI_SetFIFOThreshold(ECSPI_Type* base, uint32_t fifo, uint32_t threshold) +{ + /* configure the RXFIFO and TXFIFO threshold that can triggers a DMA/INT request */ + if(fifo == ecspiTxfifoThreshold) + ECSPI_DMAREG_REG(base) = (ECSPI_DMAREG_REG(base) & (~ECSPI_DMAREG_TX_THRESHOLD_MASK)) | + ECSPI_DMAREG_TX_THRESHOLD(threshold); + else + ECSPI_DMAREG_REG(base) = (ECSPI_DMAREG_REG(base) & (~ECSPI_DMAREG_RX_THRESHOLD_MASK)) | + ECSPI_DMAREG_RX_THRESHOLD(threshold); +} + +/******************************************************************************* + * Interrupts and flags management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : ECSPI_SetIntCmd + * Description : Enable or disable eCSPI interrupts. + * + *END**************************************************************************/ +void ECSPI_SetIntCmd(ECSPI_Type* base, uint32_t flags, bool enable) +{ + /* Configure the Interrupt source */ + if(enable) + ECSPI_INTREG_REG(base) |= flags; + else + ECSPI_INTREG_REG(base) &= ~flags; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/ecspi_imx/ecspi.h b/drivers/ecspi_imx/ecspi.h new file mode 100644 index 000000000..952ae14bb --- /dev/null +++ b/drivers/ecspi_imx/ecspi.h @@ -0,0 +1,493 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __ECSPI_H__ +#define __ECSPI_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup ecspi_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Channel select. */ +enum _ecspi_channel_select +{ + ecspiSelectChannel0 = 0U, /*!< Select Channel 0. Chip Select 0 (SS0) is asserted.*/ + ecspiSelectChannel1 = 1U, /*!< Select Channel 1. Chip Select 1 (SS1) is asserted.*/ + ecspiSelectChannel2 = 2U, /*!< Select Channel 2. Chip Select 2 (SS2) is asserted.*/ + ecspiSelectChannel3 = 3U, /*!< Select Channel 3. Chip Select 3 (SS3) is asserted.*/ +}; + +/*! @brief Channel mode. */ +enum _ecspi_master_slave_mode +{ + ecspiSlaveMode = 0U, /*!< Set Slave Mode.*/ + ecspiMasterMode = 1U, /*!< Set Master Mode.*/ +}; + +/*! @brief Clock phase. */ +enum _ecspi_clock_phase +{ + ecspiClockPhaseFirstEdge = 0U, /*!< Data is captured on the leading edge of the SCK and + changed on the following edge.*/ + ecspiClockPhaseSecondEdge = 1U, /*!< Data is changed on the leading edge of the SCK and + captured on the following edge.*/ +}; + +/*! @brief Clock polarity. */ +enum _ecspi_clock_polarity +{ + ecspiClockPolarityActiveHigh = 0U, /*!< Active-high eCSPI clock (idles low).*/ + ecspiClockPolarityActiveLow = 1U, /*!< Active-low eCSPI clock (idles high).*/ +}; + +/*! @brief SS signal polarity. */ +enum _ecspi_ss_polarity +{ + ecspiSSPolarityActiveLow = 0U, /*!< Active-low, eCSPI SS signal.*/ + ecspiSSPolarityActiveHigh = 1U, /*!< Active-high, eCSPI SS signal.*/ +}; + +/*! @brief Inactive state of data line. */ +enum _ecspi_dataline_inactivestate +{ + ecspiDataLineStayHigh = 0U, /*!< Data line inactive state stay high.*/ + ecspiDataLineStayLow = 1U, /*!< Data line inactive state stay low.*/ +}; + +/*! @brief Inactive state of SCLK. */ +enum _ecspi_sclk_inactivestate +{ + ecspiSclkStayLow = 0U, /*!< SCLK inactive state stay low.*/ + ecspiSclkStayHigh = 1U, /*!< SCLK line inactive state stay high.*/ +}; + +/*! @brief sample period counter clock source. */ +enum _ecspi_sampleperiod_clocksource +{ + ecspiSclk = 0U, /*!< Sample period counter clock from SCLK.*/ + ecspiLowFreq32K = 1U, /*!< Sample period counter clock from from LFRC (32.768 KHz).*/ +}; + +/*! @brief DMA Source definition. */ +enum _ecspi_dma_source +{ + ecspiDmaTxfifoEmpty = 7U, /*!< TXFIFO Empty DMA Request.*/ + ecspiDmaRxfifoRequest = 23U, /*!< RXFIFO DMA Request.*/ + ecspiDmaRxfifoTail = 31U, /*!< RXFIFO TAIL DMA Request.*/ +}; + +/*! @brief RXFIFO and TXFIFO threshold. */ +enum _ecspi_fifothreshold +{ + ecspiTxfifoThreshold = 0U, /*!< Defines the FIFO threshold that triggers a TX DMA/INT request.*/ + ecspiRxfifoThreshold = 16U, /*!< defines the FIFO threshold that triggers a RX DMA/INT request.*/ +}; + +/*! @brief Status flag. */ +enum _ecspi_status_flag +{ + ecspiFlagTxfifoEmpty = 1U << 0, /*!< TXFIFO Empty Flag.*/ + ecspiFlagTxfifoDataRequest = 1U << 1, /*!< TXFIFO Data Request Flag.*/ + ecspiFlagTxfifoFull = 1U << 2, /*!< TXFIFO Full Flag.*/ + ecspiFlagRxfifoReady = 1U << 3, /*!< RXFIFO Ready Flag.*/ + ecspiFlagRxfifoDataRequest = 1U << 4, /*!< RXFIFO Data Request Flag.*/ + ecspiFlagRxfifoFull = 1U << 5, /*!< RXFIFO Full Flag.*/ + ecspiFlagRxfifoOverflow = 1U << 6, /*!< RXFIFO Overflow Flag.*/ + ecspiFlagTxfifoTc = 1U << 7, /*!< TXFIFO Transform Completed Flag.*/ +}; + +/*! @brief Data Ready Control. */ +enum _ecspi_data_ready +{ + ecspiRdyNoCare = 0U, /*!< The SPI_RDY signal is ignored.*/ + ecspiRdyFallEdgeTrig = 1U, /*!< Burst is triggered by the falling edge of the SPI_RDY signal (edge-triggered).*/ + ecspiRdyLowLevelTrig = 2U, /*!< Burst is triggered by a low level of the SPI_RDY signal (level-triggered).*/ + ecspiRdyReserved = 3U, /*!< Reserved.*/ +}; + +/*! @brief Init structure. */ +typedef struct _ecspi_init_config +{ + uint32_t clockRate; /*!< Specifies ECSPII module clock freq.*/ + uint32_t baudRate; /*!< Specifies desired eCSPI baud rate.*/ + uint32_t channelSelect; /*!< Specifies the channel select.*/ + uint32_t mode; /*!< Specifies the mode.*/ + uint32_t burstLength; /*!< Specifies the length of a burst to be transferred.*/ + uint32_t clockPhase; /*!< Specifies the clock phase.*/ + uint32_t clockPolarity; /*!< Specifies the clock polarity.*/ + bool ecspiAutoStart; /*!< Specifies the start mode.*/ +} ecspi_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name eCSPI Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the eCSPI module. + * + * @param base eCSPI base pointer. + * @param initConfig eCSPI initialization structure. + */ +void ECSPI_Init(ECSPI_Type* base, const ecspi_init_config_t* initConfig); + +/*! + * @brief Enables the specified eCSPI module. + * + * @param base eCSPI base pointer. + */ +static inline void ECSPI_Enable(ECSPI_Type* base) +{ + /* Enable the eCSPI. */ + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_EN_MASK; +} + +/*! + * @brief Disable the specified eCSPI module. + * + * @param base eCSPI base pointer. + */ +static inline void ECSPI_Disable(ECSPI_Type* base) +{ + /* Enable the eCSPI. */ + ECSPI_CONREG_REG(base) &= ~ECSPI_CONREG_EN_MASK; +} + +/*! + * @brief Insert the number of wait states to be inserted in data transfers. + * + * @param base eCSPI base pointer. + * @param number the number of wait states. + */ +static inline void ECSPI_InsertWaitState(ECSPI_Type* base, uint32_t number) +{ + /* Configure the number of wait states inserted. */ + ECSPI_PERIODREG_REG(base) = (ECSPI_PERIODREG_REG(base) & (~ECSPI_PERIODREG_SAMPLE_PERIOD_MASK)) | + ECSPI_PERIODREG_SAMPLE_PERIOD(number); +} + +/*! + * @brief Set the clock source for the sample period counter. + * + * @param base eCSPI base pointer. + * @param source The clock source (see @ref _ecspi_sampleperiod_clocksource enumeration). + */ +void ECSPI_SetSampClockSource(ECSPI_Type* base, uint32_t source); + +/*! + * @brief Set the eCSPI clocks insert between the chip select active edge + * and the first eCSPI clock edge. + * + * @param base eCSPI base pointer. + * @param delay The number of wait states. + */ +static inline void ECSPI_SetDelay(ECSPI_Type* base, uint32_t delay) +{ + /* Set the number of clocks insert. */ + ECSPI_PERIODREG_REG(base) = (ECSPI_PERIODREG_REG(base) & (~ECSPI_PERIODREG_CSD_CTL_MASK)) | + ECSPI_PERIODREG_CSD_CTL(delay); +} + +/*! + * @brief Set the inactive state of SCLK. + * + * @param base eCSPI base pointer. + * @param channel eCSPI channel select (see @ref _ecspi_channel_select enumeration). + * @param state SCLK inactive state (see @ref _ecspi_sclk_inactivestate enumeration). + */ +static inline void ECSPI_SetSCLKInactiveState(ECSPI_Type* base, uint32_t channel, uint32_t state) +{ + /* Configure the inactive state of SCLK. */ + ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SCLK_CTL(1 << channel))) | + ECSPI_CONFIGREG_SCLK_CTL((state & 1) << channel); +} + +/*! + * @brief Set the inactive state of data line. + * + * @param base eCSPI base pointer. + * @param channel eCSPI channel select (see @ref _ecspi_channel_select enumeration). + * @param state Data line inactive state (see @ref _ecspi_dataline_inactivestate enumeration). + */ +static inline void ECSPI_SetDataInactiveState(ECSPI_Type* base, uint32_t channel, uint32_t state) +{ + /* Set the inactive state of Data Line. */ + ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_DATA_CTL(1 << channel))) | + ECSPI_CONFIGREG_DATA_CTL((state & 1) << channel); +} + +/*! + * @brief Trigger a burst. + * + * @param base eCSPI base pointer. + */ +static inline void ECSPI_StartBurst(ECSPI_Type* base) +{ + /* Start a burst. */ + ECSPI_CONREG_REG(base) |= ECSPI_CONREG_XCH_MASK; +} + +/*! + * @brief Set the burst length. + * + * @param base eCSPI base pointer. + * @param length The value of burst length. + */ +static inline void ECSPI_SetBurstLength(ECSPI_Type* base, uint32_t length) +{ + /* Set the burst length according to length. */ + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_BURST_LENGTH_MASK)) | + ECSPI_CONREG_BURST_LENGTH(length); +} + +/*! + * @brief Set eCSPI SS Wave Form. + * + * @param base eCSPI base pointer. + * @param channel eCSPI channel selected (see @ref _ecspi_channel_select enumeration). + * @param ssMultiBurst For master mode, set true for multiple burst and false for one burst. + * For slave mode, set true to complete burst by SS signal edges and false to complete + * burst by number of bits received. + */ +static inline void ECSPI_SetSSMultipleBurst(ECSPI_Type* base, uint32_t channel, bool ssMultiBurst) +{ + /* Set the SS wave form. */ + ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SS_CTL(1 << channel))) | + ECSPI_CONFIGREG_SS_CTL(ssMultiBurst << channel); +} + +/*! + * @brief Set eCSPI SS Polarity. + * + * @param base eCSPI base pointer. + * @param channel eCSPI channel selected (see @ref _ecspi_channel_select enumeration). + * @param polarity Set SS signal active logic (see @ref _ecspi_ss_polarity enumeration). + */ +static inline void ECSPI_SetSSPolarity(ECSPI_Type* base, uint32_t channel, uint32_t polarity) +{ + /* Set the SS polarity. */ + ECSPI_CONFIGREG_REG(base) = (ECSPI_CONFIGREG_REG(base) & (~ECSPI_CONFIGREG_SS_POL(1 << channel))) | + ECSPI_CONFIGREG_SS_POL(polarity << channel); +} + +/*! + * @brief Set the Data Ready Control. + * + * @param base eCSPI base pointer. + * @param spidataready eCSPI data ready control (see @ref _ecspi_data_ready enumeration). + */ +static inline void ECSPI_SetSPIDataReady(ECSPI_Type* base, uint32_t spidataready) +{ + /* Set the Data Ready Control. */ + ECSPI_CONREG_REG(base) = (ECSPI_CONREG_REG(base) & (~ECSPI_CONREG_DRCTL_MASK)) | + ECSPI_CONREG_DRCTL(spidataready); +} + +/*! + * @brief Calculated the eCSPI baud rate in bits per second. + * The calculated baud rate must not exceed the desired baud rate. + * + * @param base eCSPI base pointer. + * @param sourceClockInHz eCSPI Clock(SCLK) (in Hz). + * @param bitsPerSec the value of Baud Rate. + * @return The calculated baud rate in bits-per-second, the nearest possible + * baud rate without exceeding the desired baud rate. + */ +uint32_t ECSPI_SetBaudRate(ECSPI_Type* base, uint32_t sourceClockInHz, uint32_t bitsPerSec); + +/*@}*/ + +/*! + * @name Data transfers functions + * @{ + */ + +/*! + * @brief Transmits a data to TXFIFO. + * + * @param base eCSPI base pointer. + * @param data Data to be transmitted. + */ +static inline void ECSPI_SendData(ECSPI_Type* base, uint32_t data) +{ + /* Write data to Transmit Data Register. */ + ECSPI_TXDATA_REG(base) = data; +} + +/*! + * @brief Receives a data from RXFIFO. + * + * @param base eCSPI base pointer. + * @return The value of received data. + */ +static inline uint32_t ECSPI_ReceiveData(ECSPI_Type* base) +{ + /* Read data from Receive Data Register. */ + return ECSPI_RXDATA_REG(base); +} + +/*! + * @brief Read the number of words in the RXFIFO. + * + * @param base eCSPI base pointer. + * @return The number of words in the RXFIFO. + */ +static inline uint32_t ECSPI_GetRxfifoCounter(ECSPI_Type* base) +{ + /* Get the number of words in the RXFIFO. */ + return ((ECSPI_TESTREG_REG(base) & ECSPI_TESTREG_RXCNT_MASK) >> ECSPI_TESTREG_RXCNT_SHIFT); +} + +/*! + * @brief Read the number of words in the TXFIFO. + * + * @param base eCSPI base pointer. + * @return The number of words in the TXFIFO. + */ +static inline uint32_t ECSPI_GetTxfifoCounter(ECSPI_Type* base) +{ + /* Get the number of words in the RXFIFO. */ + return ((ECSPI_TESTREG_REG(base) & ECSPI_TESTREG_TXCNT_MASK) >> ECSPI_TESTREG_TXCNT_SHIFT); +} + +/*@}*/ + +/*! + * @name DMA management functions + * @{ + */ + +/*! + * @brief Enable or disable the specified DMA Source. + * + * @param base eCSPI base pointer. + * @param source specifies DMA source (see @ref _ecspi_dma_source enumeration). + * @param enable Enable/Disable specified DMA Source. + * - true: Enable specified DMA Source. + * - false: Disable specified DMA Source. + */ +void ECSPI_SetDMACmd(ECSPI_Type* base, uint32_t source, bool enable); + +/*! + * @brief Set the burst length of a DMA operation. + * + * @param base eCSPI base pointer. + * @param length Specifies the burst length of a DMA operation. + */ +static inline void ECSPI_SetDMABurstLength(ECSPI_Type* base, uint32_t length) +{ + /* Configure the burst length of a DMA operation. */ + ECSPI_DMAREG_REG(base) = (ECSPI_DMAREG_REG(base) & (~ECSPI_DMAREG_RX_DMA_LENGTH_MASK)) | + ECSPI_DMAREG_RX_DMA_LENGTH(length); +} + +/*! + * @brief Set the RXFIFO or TXFIFO threshold. + * + * @param base eCSPI base pointer. + * @param fifo Data transfer FIFO (see @ref _ecspi_fifothreshold enumeration). + * @param threshold Threshold value. + */ +void ECSPI_SetFIFOThreshold(ECSPI_Type* base, uint32_t fifo, uint32_t threshold); + +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Enable or disable the specified eCSPI interrupts. + * + * @param base eCSPI base pointer. + * @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition). + * @param enable Interrupt enable. + * - true: Enable specified eCSPI interrupts. + * - false: Disable specified eCSPI interrupts. + */ +void ECSPI_SetIntCmd(ECSPI_Type* base, uint32_t flags, bool enable); + +/*! + * @brief Checks whether the specified eCSPI flag is set or not. + * + * @param base eCSPI base pointer. + * @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition). + * @return eCSPI status, each bit represents one status flag. + */ +static inline uint32_t ECSPI_GetStatusFlag(ECSPI_Type* base, uint32_t flags) +{ + /* return the vale of eCSPI status. */ + return ECSPI_STATREG_REG(base) & flags; +} + +/*! + * @brief Clear one or more eCSPI status flag. + * + * @param base eCSPI base pointer. + * @param flags eCSPI status flag mask (see @ref _ecspi_status_flag for bit definition). + */ +static inline void ECSPI_ClearStatusFlag(ECSPI_Type* base, uint32_t flags) +{ + /* Write 1 to the status bit. */ + ECSPI_STATREG_REG(base) = flags; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /*__ECSPI_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/epit_imx/epit.c b/drivers/epit_imx/epit.c new file mode 100644 index 000000000..cf9aabdf6 --- /dev/null +++ b/drivers/epit_imx/epit.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "epit.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : EPIT_Init + * Description : Initializes the EPIT module according to the specified + * parameters in the initConfig. + * + *END**************************************************************************/ +void EPIT_Init(EPIT_Type* base, const epit_init_config_t* initConfig) +{ + assert(initConfig); + + EPIT_CR_REG(base) = 0; + + EPIT_SoftReset(base); + + EPIT_CR_REG(base) = (initConfig->freeRun ? EPIT_CR_RLD_MASK : 0) | + (initConfig->waitEnable ? EPIT_CR_WAITEN_MASK : 0) | + (initConfig->stopEnable ? EPIT_CR_STOPEN_MASK : 0) | + (initConfig->dbgEnable ? EPIT_CR_DBGEN_MASK : 0) | + (initConfig->enableMode ? EPIT_CR_ENMOD_MASK : 0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : EPIT_SetOverwriteCounter + * Description : Enable or disable EPIT overwrite counter immediately. + * + *END**************************************************************************/ +void EPIT_SetOverwriteCounter(EPIT_Type* base, bool enable) +{ + if(enable) + EPIT_CR_REG(base) |= EPIT_CR_IOVW_MASK; + else + EPIT_CR_REG(base) &= ~EPIT_CR_IOVW_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : EPIT_SetIntCmd + * Description : Enable or disable EPIT interrupt. + * + *END**************************************************************************/ +void EPIT_SetIntCmd(EPIT_Type* base, bool enable) +{ + if (enable) + EPIT_CR_REG(base) |= EPIT_CR_OCIEN_MASK; + else + EPIT_CR_REG(base) &= ~EPIT_CR_OCIEN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/epit_imx/epit.h b/drivers/epit_imx/epit.h new file mode 100644 index 000000000..dfe3f2ab8 --- /dev/null +++ b/drivers/epit_imx/epit.h @@ -0,0 +1,326 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __EPIT_H__ +#define __EPIT_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup epit_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Clock source. */ +enum _epit_clock_source +{ + epitClockSourceOff = 0U, /*!< EPIT Clock Source Off.*/ + epitClockSourcePeriph = 1U, /*!< EPIT Clock Source from Peripheral Clock.*/ + epitClockSourceHighFreq = 2U, /*!< EPIT Clock Source from High Frequency Reference Clock.*/ + epitClockSourceLowFreq = 3U, /*!< EPIT Clock Source from Low Frequency Reference Clock.*/ +}; + +/*! @brief Output compare operation mode. */ +enum _epit_output_operation_mode +{ + epitOutputOperationDisconnected = 0U, /*!< EPIT Output Operation: Disconnected from pad.*/ + epitOutputOperationToggle = 1U, /*!< EPIT Output Operation: Toggle output pin.*/ + epitOutputOperationClear = 2U, /*!< EPIT Output Operation: Clear output pin.*/ + epitOutputOperationSet = 3U, /*!< EPIT Output Operation: Set putput pin.*/ +}; + +/*! @brief Structure to configure the running mode. */ +typedef struct _epit_init_config +{ + bool freeRun; /*!< true: set-and-forget mode, false: free-running mode. */ + bool waitEnable; /*!< EPIT enabled in wait mode. */ + bool stopEnable; /*!< EPIT enabled in stop mode. */ + bool dbgEnable; /*!< EPIT enabled in debug mode. */ + bool enableMode; /*!< true: counter starts counting from load value (RLD=1) or 0xFFFF_FFFF (If RLD=0) when enabled, + false: counter restores the value that it was disabled when enabled. */ +} epit_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name EPIT State Control + * @{ + */ + +/*! + * @brief Initialize EPIT to reset state and initialize running mode. + * + * @param base EPIT base pointer. + * @param initConfig EPIT initialize structure. + */ +void EPIT_Init(EPIT_Type* base, const epit_init_config_t* initConfig); + +/*! + * @brief Software reset of EPIT module. + * + * @param base EPIT base pointer. + */ +static inline void EPIT_SoftReset(EPIT_Type* base) +{ + EPIT_CR_REG(base) |= EPIT_CR_SWR_MASK; + /* Wait reset finished. */ + while (EPIT_CR_REG(base) & EPIT_CR_SWR_MASK) { } +} + +/*! + * @brief Set clock source of EPIT. + * + * @param base EPIT base pointer. + * @param source clock source (see @ref _epit_clock_source enumeration). + */ +static inline void EPIT_SetClockSource(EPIT_Type* base, uint32_t source) +{ + EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_CLKSRC_MASK) | EPIT_CR_CLKSRC(source); +} + +/*! + * @brief Get clock source of EPIT. + * + * @param base EPIT base pointer. + * @return clock source (see @ref _epit_clock_source enumeration). + */ +static inline uint32_t EPIT_GetClockSource(EPIT_Type* base) +{ + return (EPIT_CR_REG(base) & EPIT_CR_CLKSRC_MASK) >> EPIT_CR_CLKSRC_SHIFT; +} + +/*! + * @brief Set pre scaler of EPIT. + * + * @param base EPIT base pointer. + * @param prescaler Pre-scaler of EPIT (0-4095, divider = prescaler + 1). + */ +static inline void EPIT_SetPrescaler(EPIT_Type* base, uint32_t prescaler) +{ + assert(prescaler <= (EPIT_CR_PRESCALAR_MASK >> EPIT_CR_PRESCALAR_SHIFT)); + EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_PRESCALAR_MASK) | EPIT_CR_PRESCALAR(prescaler); +} + +/*! + * @brief Get pre scaler of EPIT. + * + * @param base EPIT base pointer. + * @return Pre-scaler of EPIT (0-4095). + */ +static inline uint32_t EPIT_GetPrescaler(EPIT_Type* base) +{ + return (EPIT_CR_REG(base) & EPIT_CR_PRESCALAR_MASK) >> EPIT_CR_PRESCALAR_SHIFT; +} + +/*! + * @brief Enable EPIT module. + * + * @param base EPIT base pointer. + */ +static inline void EPIT_Enable(EPIT_Type* base) +{ + EPIT_CR_REG(base) |= EPIT_CR_EN_MASK; +} + +/*! + * @brief Disable EPIT module. + * + * @param base EPIT base pointer. + */ +static inline void EPIT_Disable(EPIT_Type* base) +{ + EPIT_CR_REG(base) &= ~EPIT_CR_EN_MASK; +} + +/*! + * @brief Get EPIT counter value. + * + * @param base EPIT base pointer. + * @return EPIT counter value. + */ +static inline uint32_t EPIT_ReadCounter(EPIT_Type* base) +{ + return EPIT_CNR_REG(base); +} + +/*@}*/ + +/*! + * @name EPIT Output Signal Control + * @{ + */ + +/*! + * @brief Set EPIT output compare operation mode. + * + * @param base EPIT base pointer. + * @param mode EPIT output compare operation mode (see @ref _epit_output_operation_mode enumeration). + */ +static inline void EPIT_SetOutputOperationMode(EPIT_Type* base, uint32_t mode) +{ + EPIT_CR_REG(base) = (EPIT_CR_REG(base) & ~EPIT_CR_OM_MASK) | EPIT_CR_OM(mode); +} + +/*! + * @brief Get EPIT output compare operation mode. + * + * @param base EPIT base pointer. + * @return EPIT output operation mode (see @ref _epit_output_operation_mode enumeration). + */ +static inline uint32_t EPIT_GetOutputOperationMode(EPIT_Type* base) +{ + return (EPIT_CR_REG(base) & EPIT_CR_OM_MASK) >> EPIT_CR_OM_SHIFT; +} + +/*! + * @brief Set EPIT output compare value. + * + * @param base EPIT base pointer. + * @param value EPIT output compare value. + */ +static inline void EPIT_SetOutputCompareValue(EPIT_Type* base, uint32_t value) +{ + EPIT_CMPR_REG(base) = value; +} + +/*! + * @brief Get EPIT output compare value. + * + * @param base EPIT base pointer. + * @return EPIT output compare value. + */ +static inline uint32_t EPIT_GetOutputCompareValue(EPIT_Type* base) +{ + return EPIT_CMPR_REG(base); +} + +/*@}*/ + +/*! + * @name EPIT Data Load Control + * @{ + */ + +/*! + * @brief Set the value that is to be loaded into counter register. + * + * @param base EPIT base pointer. + * @param value Counter load value. + */ +static inline void EPIT_SetCounterLoadValue(EPIT_Type* base, uint32_t value) +{ + EPIT_LR_REG(base) = value; +} + +/*! + * @brief Get the value that loaded into counter register. + * + * @param base EPIT base pointer. + * @return The counter load value. + */ +static inline uint32_t EPIT_GetCounterLoadValue(EPIT_Type* base) +{ + return EPIT_LR_REG(base); +} + +/*! + * @brief Enable or disable EPIT overwrite counter immediately. + * + * @param base EPIT base pointer. + * @param enable Enable/Disable EPIT overwrite counter immediately. + * - true: Enable overwrite counter immediately. + * - false: Disable overwrite counter immediately. + */ +void EPIT_SetOverwriteCounter(EPIT_Type* base, bool enable); + +/*@}*/ + +/*! + * @name EPIT Interrupt and Status Control + * @{ + */ + +/*! + * @brief Get EPIT status of output compare interrupt flag. + * + * @param base EPIT base pointer. + * @return EPIT status of output compare interrupt flag. + */ +static inline uint32_t EPIT_GetStatusFlag(EPIT_Type* base) +{ + return EPIT_SR_REG(base) & EPIT_SR_OCIF_MASK; +} + +/*! + * @brief Clear EPIT Output compare interrupt flag. + * + * @param base EPIT base pointer. + */ +static inline void EPIT_ClearStatusFlag(EPIT_Type* base) +{ + EPIT_SR_REG(base) = EPIT_SR_OCIF_MASK; +} + +/*! + * @brief Enable or disable EPIT interrupt. + * + * @param base EPIT base pointer. + * @param enable Enable/Disable EPIT interrupt. + * - true: Enable interrupt. + * - false: Disable interrupt. + */ +void EPIT_SetIntCmd(EPIT_Type* base, bool enable); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /*__EPIT_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/flexcan_imx/flexcan.c b/drivers/flexcan_imx/flexcan.c new file mode 100644 index 000000000..bd9290a81 --- /dev/null +++ b/drivers/flexcan_imx/flexcan.c @@ -0,0 +1,1073 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "flexcan.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT (31U) /*! format A&B RTR mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT (30U) /*! format A&B IDE mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT (15U) /*! format B RTR-2 mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT (14U) /*! format B IDE-2 mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK (0x3FFFFFFFU) /*! format A extended mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT (1U) /*! format A extended shift.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK (0x3FF80000U) /*! format A standard mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT (19U) /*! format A standard shift.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK (0x3FFFU) /*! format B extended mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1 (16U) /*! format B extended mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2 (0U) /*! format B extended mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK (0x7FFU) /*! format B standard mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1 (19U) /*! format B standard shift1.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2 (3U) /*! format B standard shift2.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK (0xFFU) /*! format C mask.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1 (24U) /*! format C shift1.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2 (16U) /*! format C shift2.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3 (8U) /*! format C shift3.*/ +#define FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4 (0U) /*! format C shift4.*/ +#define FLEXCAN_BYTE_DATA_FIELD_MASK (0xFFU) /*! masks for byte data field.*/ +#define RxFifoFilterElementNum(x) ((x + 1) * 8) + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * FLEXCAN Freeze control function + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_EnterFreezeMode + * Description : Set FlexCAN module enter freeze mode. + * + *END**************************************************************************/ +static void FLEXCAN_EnterFreezeMode(CAN_Type* base) +{ + /* Set Freeze, Halt */ + CAN_MCR_REG(base) |= CAN_MCR_FRZ_MASK; + CAN_MCR_REG(base) |= CAN_MCR_HALT_MASK; + /* Wait for entering the freeze mode */ + while (!(CAN_MCR_REG(base) & CAN_MCR_FRZ_ACK_MASK)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_ExitFreezeMode + * Description : Set FlexCAN module exit freeze mode. + * + *END**************************************************************************/ +static void FLEXCAN_ExitFreezeMode(CAN_Type* base) +{ + /* De-assert Freeze Mode */ + CAN_MCR_REG(base) &= ~CAN_MCR_HALT_MASK; + CAN_MCR_REG(base) &= ~CAN_MCR_FRZ_MASK; + /* Wait for exit the freeze mode */ + while (CAN_MCR_REG(base) & CAN_MCR_FRZ_ACK_MASK); +} + +/******************************************************************************* + * FlexCAN Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_Init + * Description : Initialize Flexcan module with given initialize structure. + * + *END**************************************************************************/ +void FLEXCAN_Init(CAN_Type* base, const flexcan_init_config_t* initConfig) +{ + assert(initConfig); + + /* Enable Flexcan module */ + FLEXCAN_Enable(base); + + /* Reset Flexcan module register content to default value */ + FLEXCAN_Deinit(base); + + /* Set maximum MessageBox numbers and + * Initialize all message buffers as inactive + */ + FLEXCAN_SetMaxMsgBufNum(base, initConfig->maxMsgBufNum); + + /* Initialize Flexcan module timing character */ + FLEXCAN_SetTiming(base, &initConfig->timing); + + /* Set desired operating mode */ + FLEXCAN_SetOperatingMode(base, initConfig->operatingMode); + + /* Disable Flexcan module */ + FLEXCAN_Disable(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_Deinit + * Description : This function reset Flexcan module register content to its + * default value. + * + *END**************************************************************************/ +void FLEXCAN_Deinit(CAN_Type* base) +{ + uint32_t i; + + /* Reset the FLEXCAN module */ + CAN_MCR_REG(base) |= CAN_MCR_SOFT_RST_MASK; + /* Wait for reset cycle to complete */ + while (CAN_MCR_REG(base) & CAN_MCR_SOFT_RST_MASK); + + /* Assert Flexcan module Freeze */ + FLEXCAN_EnterFreezeMode(base); + + /* Reset CTRL1 Register */ + CAN_CTRL1_REG(base) = 0x0; + + /* Reset CTRL2 Register */ + CAN_CTRL2_REG(base) = 0x0; + + /* Reset All Message Buffer Content */ + for (i = 0; i < CAN_CS_COUNT; i++) + { + base->MB[i].CS = 0x0; + base->MB[i].ID = 0x0; + base->MB[i].WORD0 = 0x0; + base->MB[i].WORD1 = 0x0; + } + + /* Reset Rx Individual Mask */ + for (i = 0; i < CAN_RXIMR_COUNT; i++) + CAN_RXIMR_REG(base, i) = 0x0; + + /* Reset Rx Mailboxes Global Mask */ + CAN_RXMGMASK_REG(base) = 0xFFFFFFFF; + + /* Reset Rx Buffer 14 Mask */ + CAN_RX14MASK_REG(base) = 0xFFFFFFFF; + + /* Reset Rx Buffer 15 Mask */ + CAN_RX15MASK_REG(base) = 0xFFFFFFFF; + + /* Rx FIFO Global Mask */ + CAN_RXFGMASK_REG(base) = 0xFFFFFFFF; + + /* Disable all MB interrupts */ + CAN_IMASK1_REG(base) = 0x0; + CAN_IMASK2_REG(base) = 0x0; + + // Clear all MB interrupt flags + CAN_IFLAG1_REG(base) = 0xFFFFFFFF; + CAN_IFLAG2_REG(base) = 0xFFFFFFFF; + + // Clear all Error interrupt flags + CAN_ESR1_REG(base) = 0xFFFFFFFF; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_Enable + * Description : This function is used to Enable the Flexcan Module. + * + *END**************************************************************************/ +void FLEXCAN_Enable(CAN_Type* base) +{ + /* Enable clock */ + CAN_MCR_REG(base) &= ~CAN_MCR_MDIS_MASK; + /* Wait until enabled */ + while (CAN_MCR_REG(base) & CAN_MCR_LPM_ACK_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_Disable + * Description : This function is used to Disable the CAN Module. + * + *END**************************************************************************/ +void FLEXCAN_Disable(CAN_Type* base) +{ + /* Disable clock*/ + CAN_MCR_REG(base) |= CAN_MCR_MDIS_MASK; + /* Wait until disabled */ + while (!(CAN_MCR_REG(base) & CAN_MCR_LPM_ACK_MASK)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetTiming + * Description : Sets the FlexCAN time segments for setting up bit rate. + * + *END**************************************************************************/ +void FLEXCAN_SetTiming(CAN_Type* base, const flexcan_timing_t* timing) +{ + assert(timing); + + /* Assert Flexcan module Freeze */ + FLEXCAN_EnterFreezeMode(base); + + /* Set Flexcan module Timing Character */ + CAN_CTRL1_REG(base) &= ~(CAN_CTRL1_PRESDIV_MASK | \ + CAN_CTRL1_RJW_MASK | \ + CAN_CTRL1_PSEG1_MASK | \ + CAN_CTRL1_PSEG2_MASK | \ + CAN_CTRL1_PROP_SEG_MASK); + CAN_CTRL1_REG(base) |= (CAN_CTRL1_PRESDIV(timing->preDiv) | \ + CAN_CTRL1_RJW(timing->rJumpwidth) | \ + CAN_CTRL1_PSEG1(timing->phaseSeg1) | \ + CAN_CTRL1_PSEG2(timing->phaseSeg2) | \ + CAN_CTRL1_PROP_SEG(timing->propSeg)); + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetOperatingMode + * Description : Set operation mode. + * + *END**************************************************************************/ +void FLEXCAN_SetOperatingMode(CAN_Type* base, uint8_t mode) +{ + assert((mode & flexcanNormalMode) || + (mode & flexcanListenOnlyMode) || + (mode & flexcanLoopBackMode)); + + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + if (mode & flexcanNormalMode) + CAN_MCR_REG(base) &= ~CAN_MCR_SUPV_MASK; + else + CAN_MCR_REG(base) |= CAN_MCR_SUPV_MASK; + + if (mode & flexcanListenOnlyMode) + CAN_CTRL1_REG(base) |= CAN_CTRL1_LOM_MASK; + else + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_LOM_MASK; + + if (mode & flexcanLoopBackMode) + CAN_CTRL1_REG(base) |= CAN_CTRL1_LPB_MASK; + else + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_LPB_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetMaxMsgBufNum + * Description : Set the maximum number of Message Buffers. + * + *END**************************************************************************/ +void FLEXCAN_SetMaxMsgBufNum(CAN_Type* base, uint32_t bufNum) +{ + assert((bufNum <= CAN_CS_COUNT) && (bufNum > 0)); + + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + /* Set the maximum number of MBs*/ + CAN_MCR_REG(base) = (CAN_MCR_REG(base) & (~CAN_MCR_MAXMB_MASK)) | CAN_MCR_MAXMB(bufNum-1); + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetAbortCmd + * Description : Set the Transmit abort feature enablement. + * + *END**************************************************************************/ +void FLEXCAN_SetAbortCmd(CAN_Type* base, bool enable) +{ + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_MCR_REG(base) |= CAN_MCR_AEN_MASK; + else + CAN_MCR_REG(base) &= ~CAN_MCR_AEN_MASK; + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetLocalPrioCmd + * Description : Set the local transmit priority enablement. + * + *END**************************************************************************/ +void FLEXCAN_SetLocalPrioCmd(CAN_Type* base, bool enable) +{ + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + { + CAN_MCR_REG(base) |= CAN_MCR_LPRIO_EN_MASK; + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_LBUF_MASK; + } + else + { + CAN_CTRL1_REG(base) |= CAN_CTRL1_LBUF_MASK; + CAN_MCR_REG(base) &= ~CAN_MCR_LPRIO_EN_MASK; + } + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetMatchPrioCmd + * Description : Set the Rx matching process priority. + * + *END**************************************************************************/ +void FLEXCAN_SetMatchPrioCmd(CAN_Type* base, bool priority) +{ + /* Assert Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + if (priority) + CAN_CTRL2_REG(base) |= CAN_CTRL2_MRP_MASK; + else + CAN_CTRL2_REG(base) &= ~CAN_CTRL2_MRP_MASK; + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/******************************************************************************* + * FlexCAN Message buffer control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetMsgBufPtr + * Description : Get message buffer pointer for transition. + * + *END**************************************************************************/ +flexcan_msgbuf_t* FLEXCAN_GetMsgBufPtr(CAN_Type* base, uint8_t msgBufIdx) +{ + assert(msgBufIdx < CAN_CS_COUNT); + + return (flexcan_msgbuf_t*) &base->MB[msgBufIdx]; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_LockRxMsgBuf + * Description : Locks the FlexCAN Rx message buffer. + * + *END**************************************************************************/ +bool FLEXCAN_LockRxMsgBuf(CAN_Type* base, uint8_t msgBufIdx) +{ + volatile uint32_t temp; + + /* Check if the MB to be Locked is enabled */ + if (msgBufIdx > (CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK)) + return false; + + /* ARM Core read MB's CS to lock MB */ + temp = base->MB[msgBufIdx].CS; + + /* Read temp itself to avoid ARMGCC warning */ + temp++; + + return true; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_UnlockAllRxMsgBuf + * Description : Unlocks the FlexCAN Rx message buffer. + * + *END**************************************************************************/ +uint16_t FLEXCAN_UnlockAllRxMsgBuf(CAN_Type* base) +{ + /* Read Free Running Timer to unlock all MessageBox */ + return CAN_TIMER_REG(base); +} + +/******************************************************************************* + * FlexCAN Interrupts and flags management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetMsgBufIntCmd + * Description : Enables/Disables the FlexCAN Message Buffer interrupt. + * + *END**************************************************************************/ +void FLEXCAN_SetMsgBufIntCmd(CAN_Type* base, uint8_t msgBufIdx, bool enable) +{ + volatile uint32_t* interruptMaskPtr; + uint8_t index; + + assert(msgBufIdx < CAN_CS_COUNT); + + if (msgBufIdx > 0x31) + { + index = msgBufIdx - 32; + interruptMaskPtr = &base->IMASK2; + } + else + { + index = msgBufIdx; + interruptMaskPtr = &base->IMASK1; + } + + if (enable) + *interruptMaskPtr |= 0x1 << index; + else + *interruptMaskPtr &= ~(0x1 << index); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetMsgBufStatusFlag + * Description : Gets the individual FlexCAN MB interrupt flag. + * + *END**************************************************************************/ +bool FLEXCAN_GetMsgBufStatusFlag(CAN_Type* base, uint8_t msgBufIdx) +{ + volatile uint32_t* interruptFlagPtr; + volatile uint8_t index; + + assert(msgBufIdx < CAN_CS_COUNT); + + if (msgBufIdx > 0x31) + { + index = msgBufIdx - 32; + interruptFlagPtr = &base->IFLAG2; + } + else + { + index = msgBufIdx; + interruptFlagPtr = &base->IFLAG1; + } + + return (bool)((*interruptFlagPtr >> index) & 0x1); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_ClearMsgBufStatusFlag + * Description : Clears the interrupt flag of the message buffers. + * + *END**************************************************************************/ +void FLEXCAN_ClearMsgBufStatusFlag(CAN_Type* base, uint32_t msgBufIdx) +{ + volatile uint8_t index; + + assert(msgBufIdx < CAN_CS_COUNT); + + if (msgBufIdx > 0x31) + { + index = msgBufIdx - 32; + /* write 1 to clear. */ + base->IFLAG2 = 0x1 << index; + } + else + { + index = msgBufIdx; + /* write 1 to clear. */ + base->IFLAG1 = 0x1 << index; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetErrIntCmd + * Description : Enables error interrupt of the FlexCAN module. + * + *END**************************************************************************/ +void FLEXCAN_SetErrIntCmd(CAN_Type* base, uint32_t errorType, bool enable) +{ + assert((errorType & flexcanIntRxWarning) || + (errorType & flexcanIntTxWarning) || + (errorType & flexcanIntWakeUp) || + (errorType & flexcanIntBusOff) || + (errorType & flexcanIntError)); + + if (enable) + { + if (errorType & flexcanIntRxWarning) + { + CAN_MCR_REG(base) |= CAN_MCR_WRN_EN_MASK; + CAN_CTRL1_REG(base) |= CAN_CTRL1_RWRN_MSK_MASK; + } + + if (errorType & flexcanIntTxWarning) + { + CAN_MCR_REG(base) |= CAN_MCR_WRN_EN_MASK; + CAN_CTRL1_REG(base) |= CAN_CTRL1_TWRN_MSK_MASK; + } + + if (errorType & flexcanIntWakeUp) + CAN_MCR_REG(base) |= CAN_MCR_WAK_MSK_MASK; + + if (errorType & flexcanIntBusOff) + CAN_CTRL1_REG(base) |= CAN_CTRL1_BOFF_MSK_MASK; + + if (errorType & flexcanIntError) + CAN_CTRL1_REG(base) |= CAN_CTRL1_ERR_MSK_MASK; + } + else + { + if (errorType & flexcanIntRxWarning) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_RWRN_MSK_MASK; + + if (errorType & flexcanIntTxWarning) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_TWRN_MSK_MASK; + + if (errorType & flexcanIntWakeUp) + CAN_MCR_REG(base) &= ~CAN_MCR_WAK_MSK_MASK; + + if (errorType & flexcanIntBusOff) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_BOFF_MSK_MASK; + + if (errorType & flexcanIntError) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_ERR_MSK_MASK; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetErrStatusFlag + * Description : Gets the FlexCAN module interrupt flag. + * + *END**************************************************************************/ +uint32_t FLEXCAN_GetErrStatusFlag(CAN_Type* base, uint32_t errFlags) +{ + return CAN_ESR1_REG(base) & errFlags; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_ClearErrStatusFlag + * Description : Clears the interrupt flag of the FlexCAN module. + * + *END**************************************************************************/ +void FLEXCAN_ClearErrStatusFlag(CAN_Type* base, uint32_t errorType) +{ + /* The Interrupt flag must be cleared by writing it to '1'. + * Writing '0' has no effect. + */ + CAN_ESR1_REG(base) = errorType; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetErrCounter + * Description : Get the error counter of FlexCAN module. + * + *END**************************************************************************/ +void FLEXCAN_GetErrCounter(CAN_Type* base, uint8_t* txError, uint8_t* rxError) +{ + *txError = CAN_ECR_REG(base) & CAN_ECR_Tx_Err_Counter_MASK; + *rxError = (CAN_ECR_REG(base) & CAN_ECR_Rx_Err_Counter_MASK) >> \ + CAN_ECR_Rx_Err_Counter_SHIFT; +} + +/******************************************************************************* + * Rx FIFO management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_EnableRxFifo + * Description : Enables the Rx FIFO. + * + *END**************************************************************************/ +void FLEXCAN_EnableRxFifo(CAN_Type* base, uint8_t numOfFilters) +{ + uint8_t maxNumMb; + + assert(numOfFilters <= 0xF); + + /* Set Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + /* Set the number of the RX FIFO filters needed*/ + CAN_CTRL2_REG(base) = (CAN_CTRL2_REG(base) & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(numOfFilters); + + /* Enable RX FIFO*/ + CAN_MCR_REG(base) |= CAN_MCR_RFEN_MASK; + + /* RX FIFO global mask*/ + CAN_RXFGMASK_REG(base) = CAN_RXFGMASK_FGM31_FGM0_MASK; + + maxNumMb = (CAN_MCR_REG(base) & CAN_MCR_MAXMB_MASK) + 1; + + for (uint8_t i = 0; i < maxNumMb; i++) + { + /* RX individual mask*/ + CAN_RXIMR_REG(base,i) = CAN_RXIMR0_RXIMR63_MI31_MI0_MASK; + } + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_DisableRxFifo + * Description : Disables the Rx FIFO. + * + *END**************************************************************************/ +void FLEXCAN_DisableRxFifo(CAN_Type* base) +{ + /* Set Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + /* Disable RX FIFO*/ + CAN_MCR_REG(base) &= ~CAN_MCR_RFEN_MASK; + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxFifoFilterNum + * Description : Set the number of the Rx FIFO filters. + * + *END**************************************************************************/ +void FLEXCAN_SetRxFifoFilterNum(CAN_Type* base, uint32_t numOfFilters) +{ + assert(numOfFilters <= 0xF); + + /* Set Freeze mode*/ + FLEXCAN_EnterFreezeMode(base); + + /* Set the number of RX FIFO ID filters*/ + CAN_CTRL2_REG(base) = (CAN_CTRL2_REG(base) & ~CAN_CTRL2_RFFN_MASK) | CAN_CTRL2_RFFN(numOfFilters); + + /* De-assert Freeze Mode*/ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxFifoFilter + * Description : Set the FlexCAN Rx FIFO fields. + * + *END**************************************************************************/ +void FLEXCAN_SetRxFifoFilter(CAN_Type* base, uint32_t idFormat, flexcan_id_table_t *idFilterTable) +{ + /* Set RX FIFO ID filter table elements*/ + uint32_t i, j, numOfFilters; + uint32_t val1 = 0, val2 = 0, val = 0; + volatile uint32_t *filterTable; + + numOfFilters = (CAN_CTRL2_REG(base) & CAN_CTRL2_RFFN_MASK) >> CAN_CTRL2_RFFN_SHIFT; + /* Rx FIFO Ocuppied First Message Box is MB6 */ + filterTable = (volatile uint32_t *)&(base->MB[6]); + + CAN_MCR_REG(base) |= CAN_MCR_IDAM(idFormat); + + switch (idFormat) + { + case flexcanRxFifoIdElementFormatA: + /* One full ID (standard and extended) per ID Filter Table element.*/ + if (idFilterTable->isRemoteFrame) + { + val = (uint32_t)0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT; + } + if (idFilterTable->isExtendedFrame) + { + val |= 0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT; + } + for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++) + { + if(idFilterTable->isExtendedFrame) + { + filterTable[i] = val + ((*(idFilterTable->idFilter + i)) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_SHIFT & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_EXT_MASK); + }else + { + filterTable[i] = val + ((*(idFilterTable->idFilter + i)) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_SHIFT & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATA_STD_MASK); + } + } + break; + case flexcanRxFifoIdElementFormatB: + /* Two full standard IDs or two partial 14-bit (standard and extended) IDs*/ + /* per ID Filter Table element.*/ + if (idFilterTable->isRemoteFrame) + { + val1 = (uint32_t)0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_RTR_SHIFT; + val2 = 0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_RTR_SHIFT; + } + if (idFilterTable->isExtendedFrame) + { + val1 |= 0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATAB_IDE_SHIFT; + val2 |= 0x1 << FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_IDE_SHIFT; + } + j = 0; + for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++) + { + if (idFilterTable->isExtendedFrame) + { + filterTable[i] = val1 + (((*(idFilterTable->idFilter + j)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT1); + filterTable[i] |= val2 + (((*(idFilterTable->idFilter + j + 1)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_EXT_SHIFT2); + }else + { + filterTable[i] = val1 + (((*(idFilterTable->idFilter + j)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT1); + filterTable[i] |= val2 + (((*(idFilterTable->idFilter + j + 1)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATB_STD_SHIFT2); + } + j = j + 2; + } + break; + case flexcanRxFifoIdElementFormatC: + /* Four partial 8-bit Standard IDs per ID Filter Table element.*/ + j = 0; + for (i = 0; i < RxFifoFilterElementNum(numOfFilters); i++) + { + filterTable[i] = (((*(idFilterTable->idFilter + j)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT1); + filterTable[i] = (((*(idFilterTable->idFilter + j + 1)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT2); + filterTable[i] = (((*(idFilterTable->idFilter + j + 2)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT3); + filterTable[i] = (((*(idFilterTable->idFilter + j + 3)) & + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_MASK) << + FLEXCAN_RX_FIFO_ID_FILTER_FORMATC_SHIFT4); + j = j + 4; + } + break; + case flexcanRxFifoIdElementFormatD: + /* All frames rejected.*/ + break; + } +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetRxFifoPtr + * Description : Gets the FlexCAN Rx FIFO data pointer. + * + *END**************************************************************************/ +flexcan_msgbuf_t* FLEXCAN_GetRxFifoPtr(CAN_Type* base) +{ + /* Rx-Fifo occupy MB0 ~ MB5 */ + return (flexcan_msgbuf_t*)&base->MB; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_GetRxFifoInfo + * Description : Set the FlexCAN RX Fifo global mask. + * + *END**************************************************************************/ +uint16_t FLEXCAN_GetRxFifoInfo(CAN_Type* base) +{ + return CAN_RXFIR_REG(base) & CAN_RXFIR_IDHIT_MASK; +} + +/******************************************************************************* + * Rx Mask Setting functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxMaskMode + * Description : Set the Rx masking mode. + * + *END**************************************************************************/ +void FLEXCAN_SetRxMaskMode(CAN_Type* base, uint32_t mode) +{ + assert((mode == flexcanRxMaskGlobal) || + (mode == flexcanRxMaskIndividual)); + + /* Assert Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (mode == flexcanRxMaskIndividual) + CAN_MCR_REG(base) |= CAN_MCR_IRMQ_MASK; + else + CAN_MCR_REG(base) &= ~CAN_MCR_IRMQ_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxMaskRtrCmd + * Description : Set the remote trasmit request mask enablement. + * + *END**************************************************************************/ +void FLEXCAN_SetRxMaskRtrCmd(CAN_Type* base, bool enable) +{ + /* Assert Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_CTRL2_REG(base) |= CAN_CTRL2_EACEN_MASK; + else + CAN_CTRL2_REG(base) &= ~CAN_CTRL2_EACEN_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxGlobalMask + * Description : Set the FlexCAN RX global mask. + * + *END**************************************************************************/ +void FLEXCAN_SetRxGlobalMask(CAN_Type* base, uint32_t mask) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + /* load mask */ + CAN_RXMGMASK_REG(base) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxIndividualMask + * Description : Set the FlexCAN Rx individual mask for ID filtering in + * the Rx MBs and the Rx FIFO. + * + *END**************************************************************************/ +void FLEXCAN_SetRxIndividualMask(CAN_Type* base, uint32_t msgBufIdx, uint32_t mask) +{ + assert(msgBufIdx < CAN_RXIMR_COUNT); + + /* Assert Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + CAN_RXIMR_REG(base,msgBufIdx) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxMsgBuff14Mask + * Description : Set the FlexCAN RX Message Buffer BUF14 mask. + * + *END**************************************************************************/ +void FLEXCAN_SetRxMsgBuff14Mask(CAN_Type* base, uint32_t mask) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + /* load mask */ + CAN_RX14MASK_REG(base) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxMsgBuff15Mask + * Description : Set the FlexCAN RX Message Buffer BUF15 mask. + * + *END**************************************************************************/ +void FLEXCAN_SetRxMsgBuff15Mask(CAN_Type* base, uint32_t mask) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + /* load mask */ + CAN_RX15MASK_REG(base) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxFifoGlobalMask + * Description : Set the FlexCAN RX Fifo global mask. + * + *END**************************************************************************/ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type* base, uint32_t mask) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + /* load mask */ + CAN_RXFGMASK_REG(base) = mask; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/******************************************************************************* + * Misc. Functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetSelfWakeUpCmd + * Description : Enable/disable the FlexCAN self wakeup feature. + * + *END**************************************************************************/ +void FLEXCAN_SetSelfWakeUpCmd(CAN_Type* base, bool lpfEnable, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (lpfEnable) + CAN_MCR_REG(base) |= CAN_MCR_WAK_SRC_MASK; + else + CAN_MCR_REG(base) &= ~CAN_MCR_WAK_SRC_MASK; + + if (enable) + CAN_MCR_REG(base) |= CAN_MCR_SLF_WAK_MASK; + else + CAN_MCR_REG(base) &= ~CAN_MCR_SLF_WAK_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetSelfReceptionCmd + * Description : Enable/disable the FlexCAN self reception feature. + * + *END**************************************************************************/ +void FLEXCAN_SetSelfReceptionCmd(CAN_Type* base, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_MCR_REG(base) &= ~CAN_MCR_SRX_DIS_MASK; + else + CAN_MCR_REG(base) |= CAN_MCR_SRX_DIS_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetRxVoteCmd + * Description : Enable/disable the enhance FlexCAN Rx vote. + * + *END**************************************************************************/ +void FLEXCAN_SetRxVoteCmd(CAN_Type* base, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_CTRL1_REG(base) |= CAN_CTRL1_SMP_MASK; + else + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_SMP_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetAutoBusOffRecoverCmd + * Description : Enable/disable the Auto Busoff recover feature. + * + *END**************************************************************************/ +void FLEXCAN_SetAutoBusOffRecoverCmd(CAN_Type* base, bool enable) +{ + if (enable) + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_BOFF_MSK_MASK; + else + CAN_CTRL1_REG(base) |= CAN_CTRL1_BOFF_MSK_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetTimeSyncCmd + * Description : Enable/disable the Time Sync feature. + * + *END**************************************************************************/ +void FLEXCAN_SetTimeSyncCmd(CAN_Type* base, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_CTRL1_REG(base) |= CAN_CTRL1_TSYN_MASK; + else + CAN_CTRL1_REG(base) &= ~CAN_CTRL1_TSYN_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/*FUNCTION********************************************************************** + * + * Function Name : FLEXCAN_SetAutoRemoteResponseCmd + * Description : Enable/disable the Auto Remote Response feature. + * + *END**************************************************************************/ +void FLEXCAN_SetAutoRemoteResponseCmd(CAN_Type* base, bool enable) +{ + /* Set Freeze mode */ + FLEXCAN_EnterFreezeMode(base); + + if (enable) + CAN_CTRL2_REG(base) &= ~CAN_CTRL2_RRS_MASK; + else + CAN_CTRL2_REG(base) |= CAN_CTRL2_RRS_MASK; + + /* De-assert Freeze Mode */ + FLEXCAN_ExitFreezeMode(base); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/flexcan_imx/flexcan.h b/drivers/flexcan_imx/flexcan.h new file mode 100644 index 000000000..5348364bc --- /dev/null +++ b/drivers/flexcan_imx/flexcan.h @@ -0,0 +1,712 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __FLEXCAN_H__ +#define __FLEXCAN_H__ + +#include +#include +#include +#include "device_imx.h" + +/* Start of section using anonymous unions. */ +#if defined(__ARMCC_VERSION) + #pragma push + #pragma anon_unions +#elif defined(__GNUC__) + /* anonymous unions are enabled by default */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=extended +#else + #error Not supported compiler type +#endif + +/*! + * @addtogroup flexcan_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief FlexCAN message buffer CODE for Rx buffers. */ +enum _flexcan_msgbuf_code_rx +{ + flexcanRxInactive = 0x0, /*!< MB is not active. */ + flexcanRxFull = 0x2, /*!< MB is full. */ + flexcanRxEmpty = 0x4, /*!< MB is active and empty. */ + flexcanRxOverrun = 0x6, /*!< MB is overwritten into a full buffer. */ + flexcanRxBusy = 0x8, /*!< FlexCAN is updating the contents of the MB. */ + /*! The CPU must not access the MB. */ + flexcanRxRanswer = 0xA, /*!< A frame was configured to recognize a Remote Request Frame */ + /*! and transmit a Response Frame in return. */ + flexcanRxNotUsed = 0xF, /*!< Not used. */ +}; + +/*! @brief FlexCAN message buffer CODE FOR Tx buffers. */ +enum _flexcan_msgbuf_code_tx +{ + flexcanTxInactive = 0x8, /*!< MB is not active. */ + flexcanTxAbort = 0x9, /*!< MB is aborted. */ + flexcanTxDataOrRemte = 0xC, /*!< MB is a TX Data Frame(when MB RTR = 0) or */ + /*!< MB is a TX Remote Request Frame (when MB RTR = 1). */ + flexcanTxTanswer = 0xE, /*!< MB is a TX Response Request Frame from. */ + /*! an incoming Remote Request Frame. */ + flexcanTxNotUsed = 0xF, /*!< Not used. */ +}; + +/*! @brief FlexCAN operation modes. */ +enum _flexcan_operatining_modes +{ + flexcanNormalMode = 0x1, /*!< Normal mode or user mode @internal gui name="Normal". */ + flexcanListenOnlyMode = 0x2, /*!< Listen-only mode @internal gui name="Listen-only". */ + flexcanLoopBackMode = 0x4, /*!< Loop-back mode @internal gui name="Loop back". */ +}; + +/*! @brief FlexCAN RX mask mode. */ +enum _flexcan_rx_mask_mode +{ + flexcanRxMaskGlobal = 0x0, /*!< Rx global mask. */ + flexcanRxMaskIndividual = 0x1, /*!< Rx individual mask. */ +}; + +/*! @brief The ID type used in rx matching process. */ +enum _flexcan_rx_mask_id_type +{ + flexcanRxMaskIdStd = 0x0, /*!< Standard ID. */ + flexcanRxMaskIdExt = 0x1, /*!< Extended ID. */ +}; + +/*! @brief FlexCAN error interrupt source enumeration. */ +enum _flexcan_interrutpt +{ + flexcanIntRxWarning = 0x01, /*!< Tx Warning interrupt source. */ + flexcanIntTxWarning = 0x02, /*!< Tx Warning interrupt source. */ + flexcanIntWakeUp = 0x04, /*!< Wake Up interrupt source. */ + flexcanIntBusOff = 0x08, /*!< Bus Off interrupt source. */ + flexcanIntError = 0x10, /*!< Error interrupt source. */ +}; + +/*! @brief FlexCAN error interrupt flags. */ +enum _flexcan_status_flag +{ + flexcanStatusSynch = CAN_ESR1_SYNCH_MASK, /*!< Bus Synchronized flag. */ + flexcanStatusTxWarningInt = CAN_ESR1_TWRN_INT_MASK, /*!< Tx Warning initerrupt flag. */ + flexcanStatusRxWarningInt = CAN_ESR1_RWRN_INT_MASK, /*!< Tx Warning initerrupt flag. */ + flexcanStatusBit1Err = CAN_ESR1_BIT1_ERR_MASK, /*!< Bit0 Error flag. */ + flexcanStatusBit0Err = CAN_ESR1_BIT0_ERR_MASK, /*!< Bit1 Error flag. */ + flexcanStatusAckErr = CAN_ESR1_ACK_ERR_MASK, /*!< Ack Error flag. */ + flexcanStatusCrcErr = CAN_ESR1_CRC_ERR_MASK, /*!< CRC Error flag. */ + flexcanStatusFrameErr = CAN_ESR1_FRM_ERR_MASK, /*!< Frame Error flag. */ + flexcanStatusStuffingErr = CAN_ESR1_STF_ERR_MASK, /*!< Stuffing Error flag. */ + flexcanStatusTxWarning = CAN_ESR1_TX_WRN_MASK, /*!< Tx Warning flag. */ + flexcanStatusRxWarning = CAN_ESR1_RX_WRN_MASK, /*!< Rx Warning flag. */ + flexcanStatusIdle = CAN_ESR1_IDLE_MASK, /*!< FlexCAN Idle flag. */ + flexcanStatusTransmitting = CAN_ESR1_TX_MASK, /*!< Trasmitting flag. */ + flexcanStatusFltConf = CAN_ESR1_FLT_CONF_MASK, /*!< Fault Config flag. */ + flexcanStatusReceiving = CAN_ESR1_RX_MASK, /*!< Receiving flag. */ + flexcanStatusBusOff = CAN_ESR1_BOFF_INT_MASK, /*!< Bus Off interrupt flag. */ + flexcanStatusError = CAN_ESR1_ERR_INT_MASK, /*!< Error interrupt flag. */ + flexcanStatusWake = CAN_ESR1_WAK_INT_MASK, /*!< Wake Up interrupt flag. */ +}; + +/*! @brief The id filter element type selection. */ +enum _flexcan_rx_fifo_id_element_format +{ + flexcanRxFifoIdElementFormatA = 0x0, /*!< One full ID (standard and extended) per ID Filter Table element. */ + flexcanRxFifoIdElementFormatB = 0x1, /*!< Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID Filter Table element. */ + flexcanRxFifoIdElementFormatC = 0x2, /*!< Four partial 8-bit Standard IDs per ID Filter Table element. */ + flexcanRxFifoIdElementFormatD = 0x3, /*!< All frames rejected. */ +}; + +/*! @brief FlexCAN Rx FIFO filters number. */ +enum _flexcan_rx_fifo_filter_id_number +{ + flexcanRxFifoIdFilterNum8 = 0x0, /*!< 8 Rx FIFO Filters. @internal gui name="8 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum16 = 0x1, /*!< 16 Rx FIFO Filters. @internal gui name="16 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum24 = 0x2, /*!< 24 Rx FIFO Filters. @internal gui name="24 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum32 = 0x3, /*!< 32 Rx FIFO Filters. @internal gui name="32 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum40 = 0x4, /*!< 40 Rx FIFO Filters. @internal gui name="40 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum48 = 0x5, /*!< 48 Rx FIFO Filters. @internal gui name="48 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum56 = 0x6, /*!< 56 Rx FIFO Filters. @internal gui name="56 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum64 = 0x7, /*!< 64 Rx FIFO Filters. @internal gui name="64 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum72 = 0x8, /*!< 72 Rx FIFO Filters. @internal gui name="72 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum80 = 0x9, /*!< 80 Rx FIFO Filters. @internal gui name="80 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum88 = 0xA, /*!< 88 Rx FIFO Filters. @internal gui name="88 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum96 = 0xB, /*!< 96 Rx FIFO Filters. @internal gui name="96 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum104 = 0xC, /*!< 104 Rx FIFO Filters. @internal gui name="104 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum112 = 0xD, /*!< 112 Rx FIFO Filters. @internal gui name="112 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum120 = 0xE, /*!< 120 Rx FIFO Filters. @internal gui name="120 Rx FIFO Filters" */ + flexcanRxFifoIdFilterNum128 = 0xF, /*!< 128 Rx FIFO Filters. @internal gui name="128 Rx FIFO Filters" */ +}; + +/*! @brief FlexCAN RX FIFO ID filter table structure. */ +typedef struct _flexcan_id_table +{ + uint32_t *idFilter; /*!< Rx FIFO ID filter elements. */ + bool isRemoteFrame; /*!< Remote frame. */ + bool isExtendedFrame; /*!< Extended frame. */ +} flexcan_id_table_t; + +/*! @brief FlexCAN message buffer structure. */ +typedef struct _flexcan_msgbuf +{ + union + { + uint32_t cs; /*!< Code and Status. */ + struct + { + uint32_t timeStamp : 16; + uint32_t dlc : 4; + uint32_t rtr : 1; + uint32_t ide : 1; + uint32_t srr : 1; + uint32_t reserved1 : 1; + uint32_t code : 4; + uint32_t reserved2 : 4; + }; + }; + + union + { + uint32_t id; /*!< Message Buffer ID. */ + struct + { + uint32_t idExt : 18; + uint32_t idStd : 11; + uint32_t prio : 3; + }; + }; + + union + { + uint32_t word0; /*!< Bytes of the FlexCAN message. */ + struct + { + uint8_t data3; + uint8_t data2; + uint8_t data1; + uint8_t data0; + }; + }; + + union + { + uint32_t word1; /*!< Bytes of the FlexCAN message. */ + struct + { + uint8_t data7; + uint8_t data6; + uint8_t data5; + uint8_t data4; + }; + }; +} flexcan_msgbuf_t; + +/*! @brief FlexCAN timing-related structures. */ +typedef struct _flexcan_timing +{ + uint32_t preDiv; /*!< Clock pre divider. */ + uint32_t rJumpwidth; /*!< Resync jump width. */ + uint32_t phaseSeg1; /*!< Phase segment 1. */ + uint32_t phaseSeg2; /*!< Phase segment 2. */ + uint32_t propSeg; /*!< Propagation segment. */ +} flexcan_timing_t; + +/*! @brief FlexCAN module initialization structure. */ +typedef struct _flexcan_init_config +{ + flexcan_timing_t timing; /*!< Desired FlexCAN module timing configuration. */ + uint32_t operatingMode; /*!< Desired FlexCAN module operating mode. */ + uint8_t maxMsgBufNum; /*!< The maximal number of available message buffer. */ +} flexcan_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name FlexCAN Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initialize FlexCAN module with given initialization structure. + * + * @param base CAN base pointer. + * @param initConfig CAN initialization structure (see @ref flexcan_init_config_t structure). + */ +void FLEXCAN_Init(CAN_Type* base, const flexcan_init_config_t* initConfig); + +/*! + * @brief This function reset FlexCAN module register content to its default value. + * + * @param base FlexCAN base pointer. + */ +void FLEXCAN_Deinit(CAN_Type* base); + +/*! + * @brief This function is used to Enable the FlexCAN Module. + * + * @param base FlexCAN base pointer. + */ +void FLEXCAN_Enable(CAN_Type* base); + +/*! + * @brief This function is used to Disable the FlexCAN Module. + * + * @param base FlexCAN base pointer. + */ +void FLEXCAN_Disable(CAN_Type* base); + +/*! + * @brief Sets the FlexCAN time segments for setting up bit rate. + * + * @param base FlexCAN base pointer. + * @param timing FlexCAN time segments, which need to be set for the bit rate (See @ref flexcan_timing_t structure). + */ +void FLEXCAN_SetTiming(CAN_Type* base, const flexcan_timing_t* timing); + +/*! + * @brief Set operation mode. + * + * @param base FlexCAN base pointer. + * @param mode Set an operation mode. + */ +void FLEXCAN_SetOperatingMode(CAN_Type* base, uint8_t mode); + +/*! + * @brief Set the maximum number of Message Buffers. + * + * @param base FlexCAN base pointer. + * @param bufNum Maximum number of message buffers. + */ +void FLEXCAN_SetMaxMsgBufNum(CAN_Type* base, uint32_t bufNum); + +/*! + * @brief Get the working status of FlexCAN module. + * + * @param base FlexCAN base pointer. + * @return - true: FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode. + * - false: FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode. + */ +static inline bool FLEXCAN_IsModuleReady(CAN_Type* base) +{ + return !((CAN_MCR_REG(base) >> CAN_MCR_NOT_RDY_SHIFT) & 0x1); +} + +/*! + * @brief Set the Transmit Abort feature enablement. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable Transmit Abort feature. + * - true: Enable Transmit Abort feature. + * - false: Disable Transmit Abort feature. + */ +void FLEXCAN_SetAbortCmd(CAN_Type* base, bool enable); + +/*! + * @brief Set the local transmit priority enablement. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable local transmit periority. + * - true: Transmit MB with highest local priority. + * - false: Transmit MB with lowest MB number. + */ +void FLEXCAN_SetLocalPrioCmd(CAN_Type* base, bool enable); + +/*! + * @brief Set the Rx matching process priority. + * + * @param base FlexCAN base pointer. + * @param priority Set Rx matching process priority. + * - true: Matching starts from Mailboxes and continues on Rx FIFO. + * - false: Matching starts from Rx FIFO and continues on Mailboxes. + */ +void FLEXCAN_SetMatchPrioCmd(CAN_Type* base, bool priority); + +/*@}*/ + +/*! + * @name FlexCAN Message buffer control functions + * @{ + */ + +/*! + * @brief Get message buffer pointer for transition. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx message buffer index. + * @return message buffer pointer. + */ +flexcan_msgbuf_t* FLEXCAN_GetMsgBufPtr(CAN_Type* base, uint8_t msgBufIdx); + +/*! + * @brief Locks the FlexCAN Rx message buffer. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer + * @return - true: Lock Rx Message Buffer successful. + * - false: Lock Rx Message Buffer failed. + */ +bool FLEXCAN_LockRxMsgBuf(CAN_Type* base, uint8_t msgBufIdx); + +/*! + * @brief Unlocks the FlexCAN Rx message buffer. + * + * @param base FlexCAN base pointer. + * @return current free run timer counter value. + */ +uint16_t FLEXCAN_UnlockAllRxMsgBuf(CAN_Type* base); + +/*@}*/ + +/*! + * @name FlexCAN Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Enables/Disables the FlexCAN Message Buffer interrupt. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + * @param enable Enables/Disables interrupt. + * - true: Enable Message Buffer interrupt. + * - disable: Disable Message Buffer interrupt. + */ +void FLEXCAN_SetMsgBufIntCmd(CAN_Type* base, uint8_t msgBufIdx, bool enable); + +/*! + * @brief Gets the individual FlexCAN MB interrupt flag. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + * @retval true: Message Buffer Interrupt is pending. + * @retval false: There is no Message Buffer Interrupt. + */ +bool FLEXCAN_GetMsgBufStatusFlag(CAN_Type* base, uint8_t msgBufIdx); + +/*! + * @brief Clears the interrupt flag of the message buffers. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + */ +void FLEXCAN_ClearMsgBufStatusFlag(CAN_Type* base, uint32_t msgBufIdx); + +/*! + * @brief Enables error interrupt of the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param errorSrc The interrupt source (see @ref _flexcan_interrutpt enumeration). + * @param enable Choose enable or disable. + */ +void FLEXCAN_SetErrIntCmd(CAN_Type* base, uint32_t errorSrc, bool enable); + +/*! + * @brief Gets the FlexCAN module interrupt flag. + * + * @param base FlexCAN base pointer. + * @param errFlags FlexCAN error flags (see @ref _flexcan_status_flag enumeration). + * @return The individual Message Buffer interrupt flag (0 and 1 are the flag value) + */ +uint32_t FLEXCAN_GetErrStatusFlag(CAN_Type* base, uint32_t errFlags); + +/*! + * @brief Clears the interrupt flag of the FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param errFlags The value to be written to the interrupt flag1 register (see @ref _flexcan_status_flag enumeration). + */ +void FLEXCAN_ClearErrStatusFlag(CAN_Type* base, uint32_t errFlags); + +/*! + * @brief Get the error counter of FlexCAN module. + * + * @param base FlexCAN base pointer. + * @param txError Tx_Err_Counter pointer. + * @param rxError Rx_Err_Counter pointer. + */ +void FLEXCAN_GetErrCounter(CAN_Type* base, uint8_t* txError, uint8_t* rxError); + +/*@}*/ + +/*! + * @name Rx FIFO management functions + * @{ + */ + +/*! + * @brief Enables the Rx FIFO. + * + * @param base FlexCAN base pointer. + * @param numOfFilters The number of Rx FIFO filters + */ +void FLEXCAN_EnableRxFifo(CAN_Type* base, uint8_t numOfFilters); + +/*! + * @brief Disables the Rx FIFO. + * + * @param base FlexCAN base pointer. + */ +void FLEXCAN_DisableRxFifo(CAN_Type* base); + +/*! + * @brief Set the number of the Rx FIFO filters. + * + * @param base FlexCAN base pointer. + * @param numOfFilters The number of Rx FIFO filters. + */ +void FLEXCAN_SetRxFifoFilterNum(CAN_Type* base, uint32_t numOfFilters); + +/*! + * @brief Set the FlexCAN Rx FIFO fields. + * + * @param base FlexCAN base pointer. + * @param idFormat The format of the Rx FIFO ID Filter Table Elements + * @param idFilterTable The ID filter table elements which contain RTR bit, IDE bit and RX message ID. + */ +void FLEXCAN_SetRxFifoFilter(CAN_Type* base, uint32_t idFormat, flexcan_id_table_t *idFilterTable); + +/*! + * @brief Gets the FlexCAN Rx FIFO data pointer. + * + * @param base FlexCAN base pointer. + * @return Rx FIFO data pointer. + */ +flexcan_msgbuf_t* FLEXCAN_GetRxFifoPtr(CAN_Type* base); + +/*! + * @brief Gets the FlexCAN Rx FIFO information. + * The return value indicates which Identifier Acceptance Filter + * (see Rx FIFO Structure) was hit by the received message. + * @param base FlexCAN base pointer. + * @return Rx FIFO filter number. + */ +uint16_t FLEXCAN_GetRxFifoInfo(CAN_Type* base); + +/*@}*/ + +/*! + * @name Rx Mask Setting functions + * @{ + */ + +/*! + * @brief Set the Rx masking mode. + * + * @param base FlexCAN base pointer. + * @param mode The FlexCAN Rx mask mode (see @ref _flexcan_rx_mask_mode enumeration). + */ +void FLEXCAN_SetRxMaskMode(CAN_Type* base, uint32_t mode); + +/*! + * @brief Set the remote trasmit request mask enablement. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable remote trasmit request mask. + * - true: Enable RTR matching judgement. + * - false: Disable RTR matching judgement. + */ +void FLEXCAN_SetRxMaskRtrCmd(CAN_Type* base, bool enable); + +/*! + * @brief Set the FlexCAN RX global mask. + * + * @param base FlexCAN base pointer. + * @param mask Rx Global mask. + */ +void FLEXCAN_SetRxGlobalMask(CAN_Type* base, uint32_t mask); + +/*! + * @brief Set the FlexCAN Rx individual mask for ID filtering in the Rx MBs and the Rx FIFO. + * + * @param base FlexCAN base pointer. + * @param msgBufIdx Index of the message buffer. + * @param mask Individual mask + */ +void FLEXCAN_SetRxIndividualMask(CAN_Type* base, uint32_t msgBufIdx, uint32_t mask); + +/*! + * @brief Set the FlexCAN RX Message Buffer BUF14 mask. + * + * @param base FlexCAN base pointer. + * @param mask Message Buffer BUF14 mask. + */ +void FLEXCAN_SetRxMsgBuff14Mask(CAN_Type* base, uint32_t mask); + +/*! + * @brief Set the FlexCAN RX Message Buffer BUF15 mask. + * + * @param base FlexCAN base pointer. + * @param mask Message Buffer BUF15 mask. + */ +void FLEXCAN_SetRxMsgBuff15Mask(CAN_Type* base, uint32_t mask); + +/*! + * @brief Set the FlexCAN RX Fifo global mask. + * + * @param base FlexCAN base pointer. + * @param mask Rx Fifo Global mask. + */ +void FLEXCAN_SetRxFifoGlobalMask(CAN_Type* base, uint32_t mask); + +/*@}*/ + +/*! + * @name Misc. Functions + * @{ + */ + +/*! + * @brief Enable/disable the FlexCAN self wakeup feature. + * + * @param base FlexCAN base pointer. + * @param lpfEnable The low pass filter for Rx self wakeup feature enablement. + * @param enable The self wakeup feature enablement. + */ +void FLEXCAN_SetSelfWakeUpCmd(CAN_Type* base, bool lpfEnable, bool enable); + +/*! + * @brief Enable/Disable the FlexCAN self reception feature. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable self reception feature. + * - true: Enable self reception feature. + * - false: Disable self reception feature. + */ +void FLEXCAN_SetSelfReceptionCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the enhance FlexCAN Rx vote. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable FlexCAN Rx vote mechanism + * - true: Three samples are used to determine the value of the received bit. + * - false: Just one sample is used to determine the bit value. + */ +void FLEXCAN_SetRxVoteCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the Auto Busoff recover feature. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable Auto Busoff Recover + * - true: Enable Auto Bus Off recover feature. + * - false: Disable Auto Bus Off recover feature. + */ +void FLEXCAN_SetAutoBusOffRecoverCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the Time Sync feature. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable the Time Sync + * - true: Enable Time Sync feature. + * - false: Disable Time Sync feature. + */ +void FLEXCAN_SetTimeSyncCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the Auto Remote Response feature. + * + * @param base FlexCAN base pointer. + * @param enable Enable/Disable the Auto Remote Response feature + * - true: Enable Auto Remote Response feature. + * - false: Disable Auto Remote Response feature. + */ +void FLEXCAN_SetAutoRemoteResponseCmd(CAN_Type* base, bool enable); + +/*! + * @brief Enable/disable the Glitch Filter Width when FLEXCAN enters the STOP mode. + * + * @param base FlexCAN base pointer. + * @param filterWidth The Glitch Filter Width. + */ +static inline void FLEXCAN_SetGlitchFilterWidth(CAN_Type* base, uint8_t filterWidth) +{ + CAN_GFWR_REG(base) = filterWidth; +} + +/*! + * @brief Get the lowest inactive message buffer number. + * + * @param base FlexCAN base pointer. + * @return bit 22-16 : The lowest number inactive Mailbox. + * bit 14 : Indicates whether the number content is valid or not. + * bit 13 : This bit indicates whether there is any inactive Mailbox. + */ +static inline uint32_t FLEXCAN_GetLowestInactiveMsgBuf(CAN_Type* base) +{ + return CAN_ESR2_REG(base); +} + +/*! + * @brief Set the Tx Arbitration Start Delay number. + * This function is used to optimize the transmit performance. + * For more information about to set this value, see the Chip Reference Manual. + * + * @param base FlexCAN base pointer. + * @param tasd The lowest number inactive Mailbox. + */ +static inline void FLEXCAN_SetTxArbitrationStartDelay(CAN_Type* base, uint8_t tasd) +{ + assert(tasd < 32); + CAN_CTRL2_REG(base) = (CAN_CTRL2_REG(base) & ~CAN_CTRL2_TASD_MASK) | CAN_CTRL2_TASD(tasd); +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#if defined(__ARMCC_VERSION) + #pragma pop +#elif defined(__GNUC__) + /* leave anonymous unions enabled */ +#elif defined(__IAR_SYSTEMS_ICC__) + #pragma language=default +#else + #error Not supported compiler type +#endif + +#endif /* __FLEXCAN_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/gpio_imx/gpio_imx.c b/drivers/gpio_imx/gpio_imx.c new file mode 100644 index 000000000..ffefaf203 --- /dev/null +++ b/drivers/gpio_imx/gpio_imx.c @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "gpio_imx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * GPIO Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : GPIO_Init + * Description : Initializes the GPIO module according to the specified + * parameters in the initConfig. + * + *END**************************************************************************/ +void GPIO_Init(GPIO_Type* base, const gpio_init_config_t* initConfig) +{ + uint32_t pin; + volatile uint32_t *icr; + + /* Register reset to default value */ + GPIO_IMR_REG(base) = 0; + GPIO_EDGE_SEL_REG(base) = 0; + + /* Get pin number */ + pin = initConfig->pin; + + /* Configure GPIO pin direction */ + if (initConfig->direction == gpioDigitalOutput) + GPIO_GDIR_REG(base) |= (1U << pin); + else + GPIO_GDIR_REG(base) &= ~(1U << pin); + + /* Configure GPIO pin interrupt mode */ + if(pin < 16) + icr = &GPIO_ICR1_REG(base); + else + { + icr = &GPIO_ICR2_REG(base); + pin -= 16; + } + switch(initConfig->interruptMode) + { + case(gpioIntLowLevel): + { + *icr &= ~(0x3<<(2*pin)); + break; + } + case(gpioIntHighLevel): + { + *icr = (*icr & (~(0x3<<(2*pin)))) | (0x1<<(2*pin)); + break; + } + case(gpioIntRisingEdge): + { + *icr = (*icr & (~(0x3<<(2*pin)))) | (0x2<<(2*pin)); + break; + } + case(gpioIntFallingEdge): + { + *icr |= (0x3<<(2*pin)); + break; + } + case(gpioNoIntmode): + { + break; + } + } +} + +/******************************************************************************* + * GPIO Read and Write Functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : GPIO_WritePinOutput + * Description : Sets the output level of the individual GPIO pin. + * + *END**************************************************************************/ +void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, gpio_pin_action_t pinVal) +{ + assert(pin < 32); + if (pinVal == gpioPinSet) + { + GPIO_DR_REG(base) |= (1U << pin); /* Set pin output to high level.*/ + } + else + { + GPIO_DR_REG(base) &= ~(1U << pin); /* Set pin output to low level.*/ + } +} + +/******************************************************************************* + * Interrupts and flags management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : GPIO_SetPinIntMode + * Description : Enable or Disable the specific pin interrupt. + * + *END**************************************************************************/ +void GPIO_SetPinIntMode(GPIO_Type* base, uint32_t pin, bool enable) +{ + assert(pin < 32); + + if(enable) + GPIO_IMR_REG(base) |= (1U << pin); + else + GPIO_IMR_REG(base) &= ~(1U << pin); +} + +/*FUNCTION********************************************************************** + * + * Function Name : GPIO_SetIntEdgeSelect + * Description : Enable or Disable the specific pin interrupt. + * + *END**************************************************************************/ + +void GPIO_SetIntEdgeSelect(GPIO_Type* base, uint32_t pin, bool enable) +{ + assert(pin < 32); + + if(enable) + GPIO_EDGE_SEL_REG(base) |= (1U << pin); + else + GPIO_EDGE_SEL_REG(base) &= ~(1U << pin); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/gpio_imx/gpio_imx.h b/drivers/gpio_imx/gpio_imx.h new file mode 100644 index 000000000..1af7cebfe --- /dev/null +++ b/drivers/gpio_imx/gpio_imx.h @@ -0,0 +1,272 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GPIO_IMX_H__ +#define __GPIO_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup gpio_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief GPIO direction definition. */ +typedef enum _gpio_pin_direction +{ + gpioDigitalInput = 0U, /*!< Set current pin as digital input.*/ + gpioDigitalOutput = 1U, /*!< Set current pin as digital output.*/ +} gpio_pin_direction_t; + +/*! @brief GPIO interrupt mode definition. */ +typedef enum _gpio_interrupt_mode +{ + gpioIntLowLevel = 0U, /*!< Set current pin interrupt is low-level sensitive.*/ + gpioIntHighLevel = 1U, /*!< Set current pin interrupt is high-level sensitive.*/ + gpioIntRisingEdge = 2U, /*!< Set current pin interrupt is rising-edge sensitive.*/ + gpioIntFallingEdge = 3U, /*!< Set current pin interrupt is falling-edge sensitive.*/ + gpioNoIntmode = 4U, /*!< Set current pin general IO functionality. */ +} gpio_interrupt_mode_t; + +/*! @brief GPIO pin(bit) value definition. */ +typedef enum _gpio_pin_action +{ + gpioPinClear = 0U, /*!< Clear GPIO Pin.*/ + gpioPinSet = 1U, /*!< Set GPIO Pin.*/ +} gpio_pin_action_t; + +/*! @brief GPIO Init structure definition. */ +typedef struct _gpio_init_config +{ + uint32_t pin; /*!< Specifies the pin number. */ + gpio_pin_direction_t direction; /*!< Specifies the pin direction. */ + gpio_interrupt_mode_t interruptMode; /*!< Specifies the pin interrupt mode, a value of @ref gpio_interrupt_mode_t. */ +} gpio_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPIO Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initializes the GPIO peripheral according to the specified + * parameters in the initConfig. + * + * @param base GPIO base pointer. + * @param initConfig pointer to a @ref gpio_init_config_t structure that + * contains the configuration information. + */ +void GPIO_Init(GPIO_Type* base, const gpio_init_config_t* initConfig); + +/*@}*/ + +/*! + * @name GPIO Read and Write Functions + * @{ + */ + +/*! + * @brief Reads the current input value of the pin when pin's direction is configured as input. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @return GPIO pin input value. + */ +static inline uint8_t GPIO_ReadPinInput(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)((GPIO_DR_REG(base) >> pin) & 1U); +} + +/*! + * @brief Reads the current input value of a specific GPIO port when port's direction are all configured as input. + * This function gets all 32-pin input as a 32-bit integer. + * + * @param base GPIO base pointer. + * @return GPIO port input data. + */ +static inline uint32_t GPIO_ReadPortInput(GPIO_Type* base) +{ + return GPIO_DR_REG(base); +} + +/*! + * @brief Reads the current pin output. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @return Current pin output value. + */ +static inline uint8_t GPIO_ReadPinOutput(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)((GPIO_DR_REG(base) >> pin) & 0x1U); +} + +/*! + * @brief Reads out all pin output status of the current port. + * This function operates all 32 port pins. + * + * @param base GPIO base pointer. + * @return Current port output status. + */ +static inline uint32_t GPIO_ReadPortOutput(GPIO_Type* base) +{ + return GPIO_DR_REG(base); +} + +/*! + * @brief Sets the output level of the individual GPIO pin to logic 1 or 0. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param pinVal pin output value (See @ref gpio_pin_action_t structure). + */ +void GPIO_WritePinOutput(GPIO_Type* base, uint32_t pin, gpio_pin_action_t pinVal); + +/*! + * @brief Sets the output of the GPIO port pins to a specific logic value. + * This function operates all 32 port pins. + * + * @param base GPIO base pointer. + * @param portVal data to configure the GPIO output. + */ +static inline void GPIO_WritePortOutput(GPIO_Type* base, uint32_t portVal) +{ + GPIO_DR_REG(base) = portVal; +} + +/*@}*/ + +/*! + * @name GPIO Read Pad Status Functions + * @{ + */ + + /*! + * @brief Reads the current GPIO pin pad status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @return GPIO pin pad status value. + */ +static inline uint8_t GPIO_ReadPadStatus(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (uint8_t)((GPIO_PSR_REG(base) >> pin) & 1U); +} + +/*@}*/ + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Enable or Disable the specific pin interrupt. + * + * @param base GPIO base pointer. + * @param pin GPIO pin number. + * @param enable Enable or disable interrupt. + * - true: Enable GPIO interrupt. + * - false: Disable GPIO interrupt. + */ +void GPIO_SetPinIntMode(GPIO_Type* base, uint32_t pin, bool enable); + +/*! + * @brief Check individual pin interrupt status. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @return current pin interrupt status flag. + */ +static inline bool GPIO_IsIntPending(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + return (bool)((GPIO_ISR_REG(base) >> pin) & 1U); +} + +/*! + * @brief Clear pin interrupt flag. Status flags are cleared by + * writing a 1 to the corresponding bit position. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + */ +static inline void GPIO_ClearStatusFlag(GPIO_Type* base, uint32_t pin) +{ + assert(pin < 32); + + GPIO_ISR_REG(base) = (1U << pin); +} + +/*! + * @brief Enable or disable the edge select bit to override + * the ICR register's configuration. + * + * @param base GPIO base pointer. + * @param pin GPIO port pin number. + * @param enable Enable or disable edge select bit. + */ +void GPIO_SetIntEdgeSelect(GPIO_Type* base, uint32_t pin, bool enable); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @} */ + +#endif /* __GPIO_IMX_H__*/ + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/gpt_imx/gpt.c b/drivers/gpt_imx/gpt.c new file mode 100644 index 000000000..6c6d12c93 --- /dev/null +++ b/drivers/gpt_imx/gpt.c @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "gpt.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : GPT_Init + * Description : Initialize GPT to reset state and initialize running mode + * + *END**************************************************************************/ +void GPT_Init(GPT_Type* base, const gpt_init_config_t* initConfig) +{ + assert(initConfig); + + base->CR = 0; + + GPT_SoftReset(base); + + base->CR = (initConfig->freeRun ? GPT_CR_FRR_MASK : 0) | + (initConfig->waitEnable ? GPT_CR_WAITEN_MASK : 0) | + (initConfig->stopEnable ? GPT_CR_STOPEN_MASK : 0) | + (initConfig->dozeEnable ? GPT_CR_DOZEEN_MASK : 0) | + (initConfig->dbgEnable ? GPT_CR_DBGEN_MASK : 0) | + (initConfig->enableMode ? GPT_CR_ENMOD_MASK : 0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : GPT_SetClockSource + * Description : Set clock source of GPT + * + *END**************************************************************************/ +void GPT_SetClockSource(GPT_Type* base, uint32_t source) +{ + assert(source <= gptClockSourceOsc); + + if (source == gptClockSourceOsc) + base->CR = (base->CR & ~GPT_CR_CLKSRC_MASK) | GPT_CR_EN_24M_MASK | GPT_CR_CLKSRC(source); + else + base->CR = (base->CR & ~(GPT_CR_CLKSRC_MASK | GPT_CR_EN_24M_MASK)) | GPT_CR_CLKSRC(source); +} + +/*FUNCTION********************************************************************** + * + * Function Name : GPT_SetIntCmd + * Description : Enable or disable GPT interrupts + * + *END**************************************************************************/ +void GPT_SetIntCmd(GPT_Type* base, uint32_t flags, bool enable) +{ + if (enable) + base->IR |= flags; + else + base->IR &= ~flags; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/gpt_imx/gpt.h b/drivers/gpt_imx/gpt.h new file mode 100644 index 000000000..3c95c1bc8 --- /dev/null +++ b/drivers/gpt_imx/gpt.h @@ -0,0 +1,414 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __GPT_H__ +#define __GPT_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup gpt_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Clock source. */ +enum _gpt_clock_source +{ + gptClockSourceNone = 0U, /*!< No source selected.*/ + gptClockSourcePeriph = 1U, /*!< Use peripheral module clock.*/ + gptClockSourceLowFreq = 4U, /*!< Use 32 K clock.*/ + gptClockSourceOsc = 5U, /*!< Use 24 M OSC clock.*/ +}; + +/*! @brief Input capture channel number. */ +enum _gpt_input_capture_channel +{ + gptInputCaptureChannel1 = 0U, /*!< Input Capture Channel1.*/ + gptInputCaptureChannel2 = 1U, /*!< Input Capture Channel2.*/ +}; + +/*! @brief Input capture operation mode. */ +enum _gpt_input_operation_mode +{ + gptInputOperationDisabled = 0U, /*!< Don't capture.*/ + gptInputOperationRiseEdge = 1U, /*!< Capture on rising edge of input pin.*/ + gptInputOperationFallEdge = 2U, /*!< Capture on falling edge of input pin.*/ + gptInputOperationBothEdge = 3U, /*!< Capture on both edges of input pin.*/ +}; + +/*! @brief Output compare channel number. */ +enum _gpt_output_compare_channel +{ + gptOutputCompareChannel1 = 0U, /*!< Output Compare Channel1.*/ + gptOutputCompareChannel2 = 1U, /*!< Output Compare Channel2.*/ + gptOutputCompareChannel3 = 2U, /*!< Output Compare Channel3.*/ +}; + +/*! @brief Output compare operation mode. */ +enum _gpt_output_operation_mode +{ + gptOutputOperationDisconnected = 0U, /*!< Don't change output pin.*/ + gptOutputOperationToggle = 1U, /*!< Toggle output pin.*/ + gptOutputOperationClear = 2U, /*!< Set output pin low.*/ + gptOutputOperationSet = 3U, /*!< Set output pin high.*/ + gptOutputOperationActivelow = 4U, /*!< Generate a active low pulse on output pin.*/ +}; + +/*! @brief Status flag. */ +enum _gpt_status_flag +{ + gptStatusFlagOutputCompare1 = 1U << 0, /*!< Output compare channel 1 event.*/ + gptStatusFlagOutputCompare2 = 1U << 1, /*!< Output compare channel 2 event.*/ + gptStatusFlagOutputCompare3 = 1U << 2, /*!< Output compare channel 3 event.*/ + gptStatusFlagInputCapture1 = 1U << 3, /*!< Capture channel 1 event.*/ + gptStatusFlagInputCapture2 = 1U << 4, /*!< Capture channel 2 event.*/ + gptStatusFlagRollOver = 1U << 5, /*!< Counter reaches maximum value and rolled over to 0 event.*/ +}; + +/*! @brief Structure to configure the running mode. */ +typedef struct _gpt_init_config +{ + bool freeRun; /*!< true: FreeRun mode, false: Restart mode. */ + bool waitEnable; /*!< GPT enabled in wait mode. */ + bool stopEnable; /*!< GPT enabled in stop mode. */ + bool dozeEnable; /*!< GPT enabled in doze mode. */ + bool dbgEnable; /*!< GPT enabled in debug mode. */ + bool enableMode; /*!< true: counter reset to 0 when enabled, false: counter retain its value when enabled. */ +} gpt_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name GPT State Control + * @{ + */ + +/*! + * @brief Initialize GPT to reset state and initialize running mode. + * + * @param base GPT base pointer. + * @param initConfig GPT mode setting configuration. + */ +void GPT_Init(GPT_Type* base, const gpt_init_config_t* initConfig); + +/*! + * @brief Software reset of GPT module. + * + * @param base GPT base pointer. + */ +static inline void GPT_SoftReset(GPT_Type* base) +{ + base->CR |= GPT_CR_SWR_MASK; + /* Wait reset finished. */ + while (base->CR & GPT_CR_SWR_MASK) {}; +} + +/*! + * @brief Set clock source of GPT. + * + * @param base GPT base pointer. + * @param source Clock source (see @ref _gpt_clock_source enumeration). + */ +void GPT_SetClockSource(GPT_Type* base, uint32_t source); + +/*! + * @brief Get clock source of GPT. + * + * @param base GPT base pointer. + * @return clock source (see @ref _gpt_clock_source enumeration). + */ +static inline uint32_t GPT_GetClockSource(GPT_Type* base) +{ + return (base->CR & GPT_CR_CLKSRC_MASK) >> GPT_CR_CLKSRC_SHIFT; +} + +/*! + * @brief Set pre scaler of GPT. + * + * @param base GPT base pointer. + * @param prescaler Pre-scaler of GPT (0-4095, divider = prescaler + 1). + */ +static inline void GPT_SetPrescaler(GPT_Type* base, uint32_t prescaler) +{ + assert(prescaler <= GPT_PR_PRESCALER_MASK); + + base->PR = (base->PR & ~GPT_PR_PRESCALER_MASK) | GPT_PR_PRESCALER(prescaler); +} + +/*! + * @brief Get pre scaler of GPT. + * + * @param base GPT base pointer. + * @return pre scaler of GPT (0-4095). + */ +static inline uint32_t GPT_GetPrescaler(GPT_Type* base) +{ + return (base->PR & GPT_PR_PRESCALER_MASK) >> GPT_PR_PRESCALER_SHIFT; +} + +/*! + * @brief OSC 24M pre-scaler before selected by clock source. + * + * @param base GPT base pointer. + * @param prescaler OSC pre-scaler(0-15, divider = prescaler + 1). + */ +static inline void GPT_SetOscPrescaler(GPT_Type* base, uint32_t prescaler) +{ + assert(prescaler <= (GPT_PR_PRESCALER24M_MASK >> GPT_PR_PRESCALER24M_SHIFT)); + + base->PR = (base->PR & ~GPT_PR_PRESCALER24M_MASK) | GPT_PR_PRESCALER24M(prescaler); +} + +/*! + * @brief Get pre-scaler of GPT. + * + * @param base GPT base pointer. + * @return OSC pre scaler of GPT (0-15). + */ +static inline uint32_t GPT_GetOscPrescaler(GPT_Type* base) +{ + return (base->PR & GPT_PR_PRESCALER24M_MASK) >> GPT_PR_PRESCALER24M_SHIFT; +} + +/*! + * @brief Enable GPT module. + * + * @param base GPT base pointer. + */ +static inline void GPT_Enable(GPT_Type* base) +{ + base->CR |= GPT_CR_EN_MASK; +} + +/*! + * @brief Disable GPT module. + * + * @param base GPT base pointer. + */ +static inline void GPT_Disable(GPT_Type* base) +{ + base->CR &= ~GPT_CR_EN_MASK; +} + +/*! + * @brief Get GPT counter value. + * + * @param base GPT base pointer. + * @return GPT counter value. + */ +static inline uint32_t GPT_ReadCounter(GPT_Type* base) +{ + return base->CNT; +} + +/*@}*/ + +/*! + * @name GPT Input/Output Signal Control + * @{ + */ + +/*! + * @brief Set GPT operation mode of input capture channel. + * + * @param base GPT base pointer. + * @param channel GPT capture channel (see @ref _gpt_input_capture_channel enumeration). + * @param mode GPT input capture operation mode (see @ref _gpt_input_operation_mode enumeration). + */ +static inline void GPT_SetInputOperationMode(GPT_Type* base, uint32_t channel, uint32_t mode) +{ + assert (channel <= gptInputCaptureChannel2); + + base->CR = (base->CR & ~(GPT_CR_IM1_MASK << (channel * 2))) | (GPT_CR_IM1(mode) << (channel * 2)); +} + +/*! + * @brief Get GPT operation mode of input capture channel. + * + * @param base GPT base pointer. + * @param channel GPT capture channel (see @ref _gpt_input_capture_channel enumeration). + * @return GPT input capture operation mode (see @ref _gpt_input_operation_mode enumeration). + */ +static inline uint32_t GPT_GetInputOperationMode(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptInputCaptureChannel2); + + return (base->CR >> (GPT_CR_IM1_SHIFT + channel * 2)) & (GPT_CR_IM1_MASK >> GPT_CR_IM1_SHIFT); +} + +/*! + * @brief Get GPT input capture value of certain channel. + * + * @param base GPT base pointer. + * @param channel GPT capture channel (see @ref _gpt_input_capture_channel enumeration). + * @return GPT input capture value. + */ +static inline uint32_t GPT_GetInputCaptureValue(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptInputCaptureChannel2); + + return *(&base->ICR1 + channel); +} + +/*! + * @brief Set GPT operation mode of output compare channel. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @param mode GPT output operation mode (see @ref _gpt_output_operation_mode enumeration). + */ +static inline void GPT_SetOutputOperationMode(GPT_Type* base, uint32_t channel, uint32_t mode) +{ + assert (channel <= gptOutputCompareChannel3); + + base->CR = (base->CR & ~(GPT_CR_OM1_MASK << (channel * 3))) | (GPT_CR_OM1(mode) << (channel * 3)); +} + +/*! + * @brief Get GPT operation mode of output compare channel. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @return GPT output operation mode (see @ref _gpt_output_operation_mode enumeration). + */ +static inline uint32_t GPT_GetOutputOperationMode(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptOutputCompareChannel3); + + return (base->CR >> (GPT_CR_OM1_SHIFT + channel * 3)) & (GPT_CR_OM1_MASK >> GPT_CR_OM1_SHIFT); +} + +/*! + * @brief Set GPT output compare value of output compare channel. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @param value GPT output compare value. + */ +static inline void GPT_SetOutputCompareValue(GPT_Type* base, uint32_t channel, uint32_t value) +{ + assert (channel <= gptOutputCompareChannel3); + + *(&base->OCR1 + channel) = value; +} + +/*! + * @brief Get GPT output compare value of output compare channel. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + * @return GPT output compare value. + */ +static inline uint32_t GPT_GetOutputCompareValue(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptOutputCompareChannel3); + + return *(&base->OCR1 + channel); +} + +/*! + * @brief Force GPT output action on output compare channel, ignoring comparator. + * + * @param base GPT base pointer. + * @param channel GPT output compare channel (see @ref _gpt_output_compare_channel enumeration). + */ +static inline void GPT_ForceOutput(GPT_Type* base, uint32_t channel) +{ + assert (channel <= gptOutputCompareChannel3); + + base->CR |= (GPT_CR_FO1_MASK << channel); +} + +/*@}*/ + +/*! + * @name GPT Interrupt and Status Control + * @{ + */ + +/*! + * @brief Get GPT status flag. + * + * @param base GPT base pointer. + * @param flags GPT status flag mask (see @ref _gpt_status_flag for bit definition). + * @return GPT status, each bit represents one status flag. + */ +static inline uint32_t GPT_GetStatusFlag(GPT_Type* base, uint32_t flags) +{ + return base->SR & flags; +} + +/*! + * @brief Clear one or more GPT status flag. + * + * @param base GPT base pointer. + * @param flags GPT status flag mask (see @ref _gpt_status_flag for bit definition). + */ +static inline void GPT_ClearStatusFlag(GPT_Type* base, uint32_t flags) +{ + base->SR = flags; +} + +/*! + * @brief Enable or Disable GPT interrupts. + * + * @param base GPT base pointer. + * @param flags GPT status flag mask (see @ref _gpt_status_flag for bit definition). + * @param enable Enable/Disable GPT interrupts. + * -true: Enable GPT interrupts. + * -false: Disable GPT interrupts. + */ +void GPT_SetIntCmd(GPT_Type* base, uint32_t flags, bool enable); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __GPT_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/i2c_imx/i2c_imx.c b/drivers/i2c_imx/i2c_imx.c new file mode 100644 index 000000000..1d7dc0202 --- /dev/null +++ b/drivers/i2c_imx/i2c_imx.c @@ -0,0 +1,167 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "i2c_imx.h" + +/******************************************************************************* + * Constant + ******************************************************************************/ +static const uint32_t i2cClkDivTab[][2] = +{ + {22, 0x20}, {24, 0x21}, {26, 0x22}, {28, 0x23}, {30, 0x00}, {32, 0x24}, {36, 0x25}, {40, 0x26}, + {42, 0x03}, {44, 0x27}, {48, 0x28}, {52, 0x05}, {56, 0x29}, {60, 0x06}, {64, 0x2A}, {72, 0x2B}, + {80, 0x2C}, {88, 0x09}, {96, 0x2D}, {104, 0x0A}, {112, 0x2E}, {128, 0x2F}, {144, 0x0C}, {160, 0x30}, + {192, 0x31}, {224, 0x32}, {240, 0x0F}, {256, 0x33}, {288, 0x10}, {320, 0x34}, {384, 0x35}, {448, 0x36}, + {480, 0x13}, {512, 0x37}, {576, 0x14}, {640, 0x38}, {768, 0x39}, {896, 0x3A}, {960, 0x17}, {1024, 0x3B}, + {1152, 0x18}, {1280, 0x3C}, {1536, 0x3D}, {1792, 0x3E}, {1920, 0x1B}, {2048, 0x3F}, {2304, 0x1C}, {2560, 0x1D}, + {3072, 0x1E}, {3840, 0x1F} +}; + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * I2C Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : I2C_Init + * Description : Initialize I2C module with given initialize structure. + * + *END**************************************************************************/ +void I2C_Init(I2C_Type* base, const i2c_init_config_t* initConfig) +{ + assert(initConfig); + + /* Disable I2C Module. */ + I2C_I2CR_REG(base) &= ~I2C_I2CR_IEN_MASK; + + /* Reset I2C register to its default value. */ + I2C_Deinit(base); + + /* Set I2C Module own Slave Address. */ + I2C_SetSlaveAddress(base, initConfig->slaveAddress); + + /* Set I2C BaudRate according to i2c initialize struct. */ + I2C_SetBaudRate(base, initConfig->clockRate, initConfig->baudRate); +} + +/*FUNCTION********************************************************************** + * + * Function Name : I2C_Deinit + * Description : This function reset I2C module register content to + * its default value. + * + *END**************************************************************************/ +void I2C_Deinit(I2C_Type* base) +{ + /* Disable I2C Module */ + I2C_I2CR_REG(base) &= ~I2C_I2CR_IEN_MASK; + + /* Reset I2C Module Register content to default value */ + I2C_IADR_REG(base) = 0x0; + I2C_IFDR_REG(base) = 0x0; + I2C_I2CR_REG(base) = 0x0; +} + +/*FUNCTION********************************************************************** + * + * Function Name : I2C_SetBaudRate + * Description : This function is used to set the baud rate of I2C Module. + * + *END**************************************************************************/ +void I2C_SetBaudRate(I2C_Type* base, uint32_t clockRate, uint32_t baudRate) +{ + uint32_t clockDiv; + uint8_t clkDivIndex = 0; + + assert(baudRate <= 400000); + + /* Calculate accurate baudRate divider. */ + clockDiv = clockRate / baudRate; + + if (clockDiv < i2cClkDivTab[0][0]) + { + /* If clock divider is too small, using smallest legal divider */ + clkDivIndex = 0; + } + else if (clockDiv > i2cClkDivTab[sizeof(i2cClkDivTab)/sizeof(i2cClkDivTab[0]) - 1][0]) + { + /* If clock divider is too large, using largest legal divider */ + clkDivIndex = sizeof(i2cClkDivTab)/sizeof(i2cClkDivTab[0]) - 1; + } + else + { + while (i2cClkDivTab[clkDivIndex][0] < clockDiv) + clkDivIndex++; + } + + I2C_IFDR_REG(base) = i2cClkDivTab[clkDivIndex][1]; +} + +/******************************************************************************* + * I2C Bus Control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : I2C_SetAckBit + * Description : This function is used to set the Transmit Acknowledge + * action when receive data from other device. + * + *END**************************************************************************/ +void I2C_SetAckBit(I2C_Type* base, bool ack) +{ + if (ack) + I2C_I2CR_REG(base) &= ~I2C_I2CR_TXAK_MASK; + else + I2C_I2CR_REG(base) |= I2C_I2CR_TXAK_MASK; +} + +/******************************************************************************* + * Interrupts and flags management functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : I2C_SetIntCmd + * Description : Enables or disables I2C interrupt requests. + * + *END**************************************************************************/ +void I2C_SetIntCmd(I2C_Type* base, bool enable) +{ + if (enable) + I2C_I2CR_REG(base) |= I2C_I2CR_IIEN_MASK; + else + I2C_I2CR_REG(base) &= ~I2C_I2CR_IIEN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/i2c_imx/i2c_imx.h b/drivers/i2c_imx/i2c_imx.h new file mode 100644 index 000000000..f5a2d2ad2 --- /dev/null +++ b/drivers/i2c_imx/i2c_imx.h @@ -0,0 +1,284 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __I2C_IMX_H__ +#define __I2C_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup i2c_imx_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief I2C module initialization structure. */ +typedef struct _i2c_init_config +{ + uint32_t clockRate; /*!< Current I2C module clock freq. */ + uint32_t baudRate; /*!< Desired I2C baud rate. */ + uint8_t slaveAddress; /*!< I2C module's own address when addressed as slave device. */ +} i2c_init_config_t; + +/*! @brief Flag for I2C interrupt status check or polling status. */ +enum _i2c_status_flag +{ + i2cStatusTransferComplete = I2C_I2SR_ICF_MASK, /*!< Data Transfer complete flag. */ + i2cStatusAddressedAsSlave = I2C_I2SR_IAAS_MASK, /*!< Addressed as a slave flag. */ + i2cStatusBusBusy = I2C_I2SR_IBB_MASK, /*!< Bus is busy flag. */ + i2cStatusArbitrationLost = I2C_I2SR_IAL_MASK, /*!< Arbitration is lost flag. */ + i2cStatusSlaveReadWrite = I2C_I2SR_SRW_MASK, /*!< Master reading from slave flag(De-assert if master writing to slave). */ + i2cStatusInterrupt = I2C_I2SR_IIF_MASK, /*!< An interrupt is pending flag. */ + i2cStatusReceivedAck = I2C_I2SR_RXAK_MASK, /*!< No acknowledge detected flag. */ +}; + +/*! @brief I2C Bus role of this module. */ +enum _i2c_work_mode +{ + i2cModeSlave = 0x0, /*!< This module works as I2C Slave. */ + i2cModeMaster = I2C_I2CR_MSTA_MASK, /*!< This module works as I2C Master. */ +}; + +/*! @brief Data transfer direction. */ +enum _i2c_direction_mode +{ + i2cDirectionReceive = 0x0, /*!< This module works at receive mode. */ + i2cDirectionTransmit = I2C_I2CR_MTX_MASK, /*!< This module works at transmit mode. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name I2C Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initialize I2C module with given initialization structure. + * + * @param base I2C base pointer. + * @param initConfig I2C initialization structure (see @ref i2c_init_config_t). + */ +void I2C_Init(I2C_Type* base, const i2c_init_config_t* initConfig); + +/*! + * @brief This function reset I2C module register content to its default value. + * + * @param base I2C base pointer. + */ +void I2C_Deinit(I2C_Type* base); + +/*! + * @brief This function is used to Enable the I2C Module. + * + * @param base I2C base pointer. + */ +static inline void I2C_Enable(I2C_Type* base) +{ + I2C_I2CR_REG(base) |= I2C_I2CR_IEN_MASK; +} + +/*! + * @brief This function is used to Disable the I2C Module. + * + * @param base I2C base pointer. + */ +static inline void I2C_Disable(I2C_Type* base) +{ + I2C_I2CR_REG(base) &= ~I2C_I2CR_IEN_MASK; +} + +/*! + * @brief This function is used to set the baud rate of I2C Module. + * + * @param base I2C base pointer. + * @param clockRate I2C module clock frequency. + * @param baudRate Desired I2C module baud rate. + */ +void I2C_SetBaudRate(I2C_Type* base, uint32_t clockRate, uint32_t baudRate); + +/*! + * @brief This function is used to set the own I2C bus address when addressed as a slave. + * + * @param base I2C base pointer. + * @param slaveAddress Own I2C Bus address. + */ +static inline void I2C_SetSlaveAddress(I2C_Type* base, uint8_t slaveAddress) +{ + assert(slaveAddress < 0x80); + + I2C_IADR_REG(base) = (I2C_IADR_REG(base) & ~I2C_IADR_ADR_MASK) | I2C_IADR_ADR(slaveAddress); +} + +/*! + * @name I2C Bus Control functions + * @{ + */ + +/*! + * @brief This function is used to Generate a Repeat Start Signal on I2C Bus. + * + * @param base I2C base pointer. + */ +static inline void I2C_SendRepeatStart(I2C_Type* base) +{ + I2C_I2CR_REG(base) |= I2C_I2CR_RSTA_MASK; +} + +/*! + * @brief This function is used to select the I2C bus role of this module, + * both I2C Bus Master and Slave can be select. + * + * @param base I2C base pointer. + * @param mode I2C Bus role to set (see @ref _i2c_work_mode enumeration). + */ +static inline void I2C_SetWorkMode(I2C_Type* base, uint32_t mode) +{ + assert((mode == i2cModeMaster) || (mode == i2cModeSlave)); + + I2C_I2CR_REG(base) = (I2C_I2CR_REG(base) & ~I2C_I2CR_MSTA_MASK) | mode; +} + +/*! + * @brief This function is used to select the data transfer direction of this module, + * both Transmit and Receive can be select. + * + * @param base I2C base pointer. + * @param direction I2C Bus data transfer direction (see @ref _i2c_direction_mode enumeration). + */ +static inline void I2C_SetDirMode(I2C_Type* base, uint32_t direction) +{ + assert((direction == i2cDirectionReceive) || (direction == i2cDirectionTransmit)); + + I2C_I2CR_REG(base) = (I2C_I2CR_REG(base) & ~I2C_I2CR_MTX_MASK) | direction; +} + +/*! + * @brief This function is used to set the Transmit Acknowledge action when receive + * data from other device. + * + * @param base I2C base pointer. + * @param ack The ACK value answerback to remote I2C device. + * - true: An acknowledge signal is sent to the bus at the ninth clock bit. + * - false: No acknowledge signal response is sent. + */ +void I2C_SetAckBit(I2C_Type* base, bool ack); + +/*! + * @name Data transfers functions + * @{ + */ + +/*! + * @brief Writes one byte of data to the I2C bus. + * + * @param base I2C base pointer. + * @param byte The byte of data to transmit. + */ +static inline void I2C_WriteByte(I2C_Type* base, uint8_t byte) +{ + I2C_I2DR_REG(base) = byte; +} + +/*! + * @brief Returns the last byte of data read from the bus and initiate another read. + * + * In a master receive mode, calling this function initiates receiving the next byte of data. + * + * @param base I2C base pointer. + * @return This function returns the last byte received while the I2C module is configured in master + * receive or slave receive mode. + */ +static inline uint8_t I2C_ReadByte(I2C_Type* base) +{ + return (uint8_t)(I2C_I2DR_REG(base) & I2C_I2DR_DATA_MASK); +} + +/*! + * @name Interrupts and flags management functions + * @{ + */ + +/*! + * @brief Enable or disable I2C interrupt requests. + * + * @param base I2C base pointer. + * @param enable Enable/Disbale I2C interrupt. + * - true: Enable I2C interrupt. + * - false: Disable I2C interrupt. + */ +void I2C_SetIntCmd(I2C_Type* base, bool enable); + +/*! + * @brief Gets the I2C status flag state. + * + * @param base I2C base pointer. + * @param flags I2C status flag mask (see @ref _i2c_status_flag enumeration.) + * @return I2C status, each bit represents one status flag + */ +static inline uint32_t I2C_GetStatusFlag(I2C_Type* base, uint32_t flags) +{ + return (I2C_I2SR_REG(base) & flags); +} + +/*! + * @brief Clear one or more I2C status flag state. + * + * @param base I2C base pointer. + * @param flags I2C status flag mask (see @ref _i2c_status_flag enumeration.) + */ +static inline void I2C_ClearStatusFlag(I2C_Type* base, uint32_t flags) +{ + /* Write 0 to clear. */ + I2C_I2SR_REG(base) &= ~flags; +} + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __I2C_IMX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/lmem_imx/lmem.c b/drivers/lmem_imx/lmem.c new file mode 100644 index 000000000..4245599e9 --- /dev/null +++ b/drivers/lmem_imx/lmem.c @@ -0,0 +1,348 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "lmem.h" + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define LMEM_CACHE_LINE_SIZE 32 + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * System Cache control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_EnableSystemCache + * Description : This function enable the System Cache. + * + *END**************************************************************************/ +void LMEM_EnableSystemCache(LMEM_Type *base) +{ + /* set command to invalidate all ways */ + /* and write GO bit to initiate command */ + LMEM_PSCCR_REG(base) = LMEM_PSCCR_INVW1_MASK | LMEM_PSCCR_INVW0_MASK; + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); + + /* Enable cache, enable write buffer */ + LMEM_PSCCR_REG(base) = (LMEM_PSCCR_ENWRBUF_MASK | LMEM_PSCCR_ENCACHE_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_DisableSystemCache + * Description : This function disable the System Cache. + * + *END**************************************************************************/ +void LMEM_DisableSystemCache(LMEM_Type *base) +{ + LMEM_PSCCR_REG(base) = 0x0; + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushSystemCache + * Description : This function flush the System Cache. + * + *END**************************************************************************/ +void LMEM_FlushSystemCache(LMEM_Type *base) +{ + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_PUSHW0_MASK | LMEM_PSCCR_PUSHW1_MASK ; + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushSystemCacheLine + * Description : This function is called to push a line out of the System Cache. + * + *END**************************************************************************/ +static void LMEM_FlushSystemCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address >= 0x20000000); + + /* Invalidate by physical address */ + LMEM_PSCLCR_REG(base) = LMEM_PSCLCR_LADSEL_MASK | LMEM_PSCLCR_LCMD(2); + /* Set physical address and activate command */ + LMEM_PSCSAR_REG(base) = ((uint32_t)address & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCSAR_REG(base) & LMEM_PSCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushSystemCacheLines + * Description : This function is called to flush the System Cache by + * performing cache copy-backs. It must determine how + * many cache lines need to be copied back and then + * perform the copy-backs. + * + *END**************************************************************************/ +void LMEM_FlushSystemCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + + address = (void *) ((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + do + { + LMEM_FlushSystemCacheLine(base, address); + address = (void *) ((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateSystemCache + * Description : This function invalidate the System Cache. + * + *END**************************************************************************/ +void LMEM_InvalidateSystemCache(LMEM_Type *base) +{ + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_INVW0_MASK | LMEM_PSCCR_INVW1_MASK; + LMEM_PSCCR_REG(base) |= LMEM_PSCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCCR_REG(base) & LMEM_PSCCR_GO_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateSystemCacheLine + * Description : This function is called to invalidate a line out of + * the System Cache. + * + *END**************************************************************************/ +static void LMEM_InvalidateSystemCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address >= 0x20000000); + + /* Invalidate by physical address */ + LMEM_PSCLCR_REG(base) = LMEM_PSCLCR_LADSEL_MASK | LMEM_PSCLCR_LCMD(1); + /* Set physical address and activate command */ + LMEM_PSCSAR_REG(base) = ((uint32_t)address & LMEM_PSCSAR_PHYADDR_MASK) | LMEM_PSCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PSCSAR_REG(base) & LMEM_PSCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateSystemCacheLines + * Description : This function is responsible for performing an data + * cache invalidate. It must determine how many cache + * lines need to be invalidated and then perform the + * invalidation. + * + *END**************************************************************************/ +void LMEM_InvalidateSystemCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + address = (void *)((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + + do + { + LMEM_InvalidateSystemCacheLine(base, address); + address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_EnableCodeCache + * Description : This function enable the Code Cache. + * + *END**************************************************************************/ +void LMEM_EnableCodeCache(LMEM_Type *base) +{ + /* set command to invalidate all ways, enable write buffer */ + /* and write GO bit to initiate command */ + LMEM_PCCCR_REG(base) = LMEM_PCCCR_INVW1_MASK | LMEM_PCCCR_INVW0_MASK; + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); + + /* Enable cache, enable write buffer */ + LMEM_PCCCR_REG(base) = (LMEM_PCCCR_ENWRBUF_MASK | LMEM_PCCCR_ENCACHE_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_DisableCodeCache + * Description : This function disable the Code Cache. + * + *END**************************************************************************/ +void LMEM_DisableCodeCache(LMEM_Type *base) +{ + LMEM_PCCCR_REG(base) = 0x0; + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushCodeCache + * Description : This function flush the Code Cache. + * + *END**************************************************************************/ +void LMEM_FlushCodeCache(LMEM_Type *base) +{ + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_PUSHW0_MASK | LMEM_PCCCR_PUSHW1_MASK; + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushCodeCacheLine + * Description : This function is called to push a line out of the + * Code Cache. + * + *END**************************************************************************/ +static void LMEM_FlushCodeCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address < 0x20000000); + + /* Invalidate by physical address */ + LMEM_PCCLCR_REG(base) = LMEM_PCCLCR_LADSEL_MASK | LMEM_PCCLCR_LCMD(2); + /* Set physical address and activate command */ + LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCSAR_REG(base) & LMEM_PCCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_FlushCodeCacheLines + * Description : This function is called to flush the instruction + * cache by performing cache copy-backs. It must + * determine how many cache lines need to be copied + * back and then perform the copy-backs. + * + *END**************************************************************************/ +void LMEM_FlushCodeCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + + address = (void *) ((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + do + { + LMEM_FlushCodeCacheLine(base, address); + address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateCodeCache + * Description : This function invalidate the Code Cache. + * + *END**************************************************************************/ +void LMEM_InvalidateCodeCache(LMEM_Type *base) +{ + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_INVW0_MASK | LMEM_PCCCR_INVW1_MASK; + LMEM_PCCCR_REG(base) |= LMEM_PCCCR_GO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCCR_REG(base) & LMEM_PCCCR_GO_MASK); + __ISB(); + __DSB(); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateCodeCacheLine + * Description : This function is called to invalidate a line out + * of the Code Cache. + * + *END**************************************************************************/ +static void LMEM_InvalidateCodeCacheLine(LMEM_Type *base, void *address) +{ + assert((uint32_t)address < 0x20000000); + + /* Invalidate by physical address */ + LMEM_PCCLCR_REG(base) = LMEM_PCCLCR_LADSEL_MASK | LMEM_PCCLCR_LCMD(1); + /* Set physical address and activate command */ + LMEM_PCCSAR_REG(base) = ((uint32_t)address & LMEM_PCCSAR_PHYADDR_MASK) | LMEM_PCCSAR_LGO_MASK; + + /* wait until the command completes */ + while (LMEM_PCCSAR_REG(base) & LMEM_PCCSAR_LGO_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : LMEM_InvalidateCodeCacheLines + * Description : This function is responsible for performing an + * Code Cache invalidate. It must determine + * how many cache lines need to be invalidated and then + * perform the invalidation. + * + *END**************************************************************************/ +void LMEM_InvalidateCodeCacheLines(LMEM_Type *base, void *address, uint32_t length) +{ + void *endAddress = (void *)((uint32_t)address + length); + address = (void *)((uint32_t)address & ~(LMEM_CACHE_LINE_SIZE - 1)); + + do + { + LMEM_InvalidateCodeCacheLine(base, address); + address = (void *)((uint32_t)address + LMEM_CACHE_LINE_SIZE); + } while (address < endAddress); + __ISB(); + __DSB(); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/lmem_imx/lmem.h b/drivers/lmem_imx/lmem.h new file mode 100644 index 000000000..be4d8599c --- /dev/null +++ b/drivers/lmem_imx/lmem.h @@ -0,0 +1,174 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __LMEM_H__ +#define __LMEM_H__ + +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup lmem_driver + * @{ + */ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Processor System Cache control functions + * @{ + */ + +/*! + * @brief This function enable the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_EnableSystemCache(LMEM_Type *base); + +/*! + * @brief This function disable the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_DisableSystemCache(LMEM_Type *base); + +/*! + * @brief This function flush the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_FlushSystemCache(LMEM_Type *base); + +/*! + * @brief This function is called to flush the System Cache by performing cache copy-backs. + * It must determine how many cache lines need to be copied back and then + * perform the copy-backs. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of flush address space. + */ +void LMEM_FlushSystemCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*! + * @brief This function invalidate the System Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_InvalidateSystemCache(LMEM_Type *base); + +/*! + * @brief This function is responsible for performing an System Cache invalidate. + * It must determine how many cache lines need to be invalidated and then + * perform the invalidation. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of invalidate address space. + */ +void LMEM_InvalidateSystemCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*@}*/ + +/*! + * @name Processor Code Cache control functions + * @{ + */ + +/*! + * @brief This function enable the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_EnableCodeCache(LMEM_Type *base); + +/*! + * @brief This function disable the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_DisableCodeCache(LMEM_Type *base); + +/*! + * @brief This function flush the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_FlushCodeCache(LMEM_Type *base); + +/*! + * @brief This function is called to flush the Code Cache by performing cache copy-backs. + * It must determine how many cache lines need to be copied back and then + * perform the copy-backs. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of flush address space. + */ +void LMEM_FlushCodeCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*! + * @brief This function invalidate the Code Cache. + * + * @param base LMEM base pointer. + */ +void LMEM_InvalidateCodeCache(LMEM_Type *base); + +/*! + * @brief This function is responsible for performing an Code Cache invalidate. + * It must determine how many cache lines need to be invalidated and then + * perform the invalidation. + * + * @param base LMEM base pointer. + * @param address The start address of cache line. + * @param length The length of invalidate address space. + */ +void LMEM_InvalidateCodeCacheLines(LMEM_Type *base, void *address, uint32_t length); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __LMEM_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/mu_imx/mu_imx.c b/drivers/mu_imx/mu_imx.c new file mode 100644 index 000000000..7a142fede --- /dev/null +++ b/drivers/mu_imx/mu_imx.c @@ -0,0 +1,155 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "mu_imx.h" + +/*FUNCTION********************************************************************** + * + * Function Name : MU_TrySendMsg + * Description : Try to send message to the other core. + * + *END**************************************************************************/ +mu_status_t MU_TrySendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg) +{ + assert(regIndex < MU_TR_COUNT); + + // TX register is empty. + if(MU_IsTxEmpty(base, regIndex)) + { + base->TR[regIndex] = msg; + return kStatus_MU_Success; + } + + return kStatus_MU_TxNotEmpty; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_SendMsg + * Description : Wait and send message to the other core. + * + *END**************************************************************************/ +void MU_SendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg) +{ + assert(regIndex < MU_TR_COUNT); + uint32_t mask = MU_SR_TE0_MASK >> regIndex; + // Wait TX register to be empty. + while (!(base->SR & mask)) { } + base->TR[regIndex] = msg; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_TryReceiveMsg + * Description : Try to receive message from the other core. + * + *END**************************************************************************/ +mu_status_t MU_TryReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg) +{ + assert(regIndex < MU_RR_COUNT); + + // RX register is full. + if(MU_IsRxFull(base, regIndex)) + { + *msg = base->RR[regIndex]; + return kStatus_MU_Success; + } + + return kStatus_MU_RxNotFull; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_ReceiveMsg + * Description : Wait to receive message from the other core. + * + *END**************************************************************************/ +void MU_ReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg) +{ + assert(regIndex < MU_TR_COUNT); + uint32_t mask = MU_SR_RF0_MASK >> regIndex; + + // Wait RX register to be full. + while (!(base->SR & mask)) { } + *msg = base->RR[regIndex]; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_TriggerGeneralInt + * Description : Trigger general purpose interrupt to the other core. + * + *END**************************************************************************/ +mu_status_t MU_TriggerGeneralInt(MU_Type * base, uint32_t index) +{ + // Previous interrupt has been accepted. + if (MU_IsGeneralIntAccepted(base, index)) + { + // All interrupts have been accepted, trigger now. + base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn + | (MU_CR_GIR0_MASK>>index); // Set GIRn + return kStatus_MU_Success; + } + + return kStatus_MU_IntPending; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_TrySetFlags + * Description : Try to set some bits of the 3-bit flag. + * + *END**************************************************************************/ +mu_status_t MU_TrySetFlags(MU_Type * base, uint32_t flags) +{ + if(MU_IsFlagPending(base)) + { + return kStatus_MU_FlagPending; + } + + base->CR = (base->CR & ~(MU_CR_GIRn_MASK | MU_CR_Fn_MASK)) | flags; + return kStatus_MU_Success; +} + +/*FUNCTION********************************************************************** + * + * Function Name : MU_SetFlags + * Description : Block to set some bits of the 3-bit flag. + * + *END**************************************************************************/ +void MU_SetFlags(MU_Type * base, uint32_t flags) +{ + while (MU_IsFlagPending(base)) { } + base->CR = (base->CR & ~(MU_CR_GIRn_MASK | MU_CR_Fn_MASK)) | flags; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/mu_imx/mu_imx.h b/drivers/mu_imx/mu_imx.h new file mode 100644 index 000000000..2e16afd7d --- /dev/null +++ b/drivers/mu_imx/mu_imx.h @@ -0,0 +1,569 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __MU_IMX_H__ +#define __MU_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup mu_driver + * @{ + */ + +/****************************************************************************** + * Definitions + *****************************************************************************/ + +/*!@brief Bit mask for general purpose interrupt 0 pending. */ +#define MU_SR_GIP0_MASK (1U<<31U) +/*!@brief Bit mask for RX full interrupt 0 pending. */ +#define MU_SR_RF0_MASK (1U<<27U) +/*!@brief Bit mask for TX empty interrupt 0 pending. */ +#define MU_SR_TE0_MASK (1U<<23U) +/*!@brief Bit mask for general purpose interrupt 0 enable. */ +#define MU_CR_GIE0_MASK (1U<<31U) +/*!@brief Bit mask for RX full interrupt 0 enable. */ +#define MU_CR_RIE0_MASK (1U<<27U) +/*!@brief Bit mask for TX empty interrupt 0 enable. */ +#define MU_CR_TIE0_MASK (1U<<23U) +/*!@brief Bit mask to trigger general purpose interrupt 0. */ +#define MU_CR_GIR0_MASK (1U<<19U) + +/*!@brief Number of general purpose interrupt. */ +#define MU_GPn_COUNT (4U) + +/* Mask for MU_CR_GIRN. When read-modify-write to MU_CR, should + pay attention to these bits in case of trigger interrupts by mistake.*/ + +/*! @brief MU status return codes. */ +typedef enum _mu_status +{ + kStatus_MU_Success = 0U, /*!< Success. */ + kStatus_MU_TxNotEmpty = 1U, /*!< TX register is not empty. */ + kStatus_MU_RxNotFull = 2U, /*!< RX register is not full. */ + kStatus_MU_FlagPending = 3U, /*!< Previous flags update pending. */ + kStatus_MU_EventPending = 4U, /*!< MU event is pending. */ + kStatus_MU_Initialized = 5U, /*!< MU driver has initialized previously. */ + kStatus_MU_IntPending = 6U, /*!< Previous general interrupt still pending. */ + kStatus_MU_Failed = 7U /*!< Execution failed. */ +} mu_status_t; + +/*! @brief MU message status. */ +typedef enum _mu_msg_status +{ + kMuTxEmpty0 = MU_SR_TE0_MASK, /*!< TX0 empty status. */ + kMuTxEmpty1 = MU_SR_TE0_MASK >> 1U, /*!< TX1 empty status. */ + kMuTxEmpty2 = MU_SR_TE0_MASK >> 2U, /*!< TX2 empty status. */ + kMuTxEmpty3 = MU_SR_TE0_MASK >> 3U, /*!< TX3 empty status. */ + kMuTxEmpty = kMuTxEmpty0 | + kMuTxEmpty1 | + kMuTxEmpty2 | + kMuTxEmpty3, /*!< TX empty status. */ + + kMuRxFull0 = MU_SR_RF0_MASK, /*!< RX0 full status. */ + kMuRxFull1 = MU_SR_RF0_MASK >> 1U, /*!< RX1 full status. */ + kMuRxFull2 = MU_SR_RF0_MASK >> 2U, /*!< RX2 full status. */ + kMuRxFull3 = MU_SR_RF0_MASK >> 3U, /*!< RX3 full status. */ + kMuRxFull = kMuRxFull0 | + kMuRxFull1 | + kMuRxFull2 | + kMuRxFull3, /*!< RX empty status. */ + + kMuGenInt0 = MU_SR_GIP0_MASK, /*!< General purpose interrupt 0 pending status. */ + kMuGenInt1 = MU_SR_GIP0_MASK >> 1U, /*!< General purpose interrupt 2 pending status. */ + kMuGenInt2 = MU_SR_GIP0_MASK >> 2U, /*!< General purpose interrupt 2 pending status. */ + kMuGenInt3 = MU_SR_GIP0_MASK >> 3U, /*!< General purpose interrupt 3 pending status. */ + kMuGenInt = kMuGenInt0 | + kMuGenInt1 | + kMuGenInt2 | + kMuGenInt3, /*!< General purpose interrupt pending status. */ + + kMuStatusAll = kMuTxEmpty | + kMuRxFull | + kMuGenInt, /*!< All MU status. */ + +} mu_msg_status_t; + +/*! @brief Power mode definition. */ +typedef enum _mu_power_mode +{ + kMuPowerModeRun = 0x00U, /*!< Run mode. */ + kMuPowerModeWait = 0x01U, /*!< WAIT mode. */ + kMuPowerModeStop = 0x02U, /*!< STOP mode. */ + kMuPowerModeDsm = 0x03U, /*!< DSM mode. */ +} mu_power_mode_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name Initialization. + * @{ + */ +/*! + * @brief Initializes the MU module to reset state. + * This function sets the MU module control register to its default reset value. + * + * @param base Register base address for the module. + */ +static inline void MU_Init(MU_Type * base) +{ + // Clear GIEn, RIEn, TIEn, GIRn and ABFn. + base->CR &= ~(MU_CR_GIEn_MASK | MU_CR_RIEn_MASK | MU_CR_TIEn_MASK | MU_CR_GIRn_MASK | MU_CR_Fn_MASK); +} + +/* @} */ + +/*! + * @name Send Messages. + * @{ + */ + +/*! + * @brief Try to send a message. + * + * This function tries to send a message, if the TX register is not empty, + * this function returns kStatus_MU_TxNotEmpty. + * + * @param base Register base address for the module. + * @param regIdex Tx register index. + * @param msg Message to send. + * @retval kStatus_MU_Success Message send successfully. + * @retval kStatus_MU_TxNotEmpty Message not send because TX is not empty. + */ +mu_status_t MU_TrySendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg); + +/*! + * @brief Block to send a message. + * + * This function waits until TX register is empty and send the message. + * + * @param base Register base address for the module. + * @param regIdex Tx register index. + * @param msg Message to send. + */ +void MU_SendMsg(MU_Type * base, uint32_t regIndex, uint32_t msg); + +/*! + * @brief Check TX empty status. + * + * This function checks the specific transmit register empty status. + * + * @param base Register base address for the module. + * @param index TX register index to check. + * @retval true TX register is empty. + * @retval false TX register is not empty. + */ +static inline bool MU_IsTxEmpty(MU_Type * base, uint32_t index) +{ + return (bool)(base->SR & (MU_SR_TE0_MASK >> index)); +} + +/*! + * @brief Enable TX empty interrupt. + * + * This function enables specific TX empty interrupt. + * + * @param base Register base address for the module. + * @param index TX interrupt index to enable. + * + * Example: + @code + // To enable TX0 empty interrupts. + MU_EnableTxEmptyInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_EnableTxEmptyInt(MU_Type * base, uint32_t index) +{ + base->CR = (base->CR & ~ MU_CR_GIRn_MASK) // Clear GIRn + | (MU_CR_TIE0_MASK>>index); // Set TIEn +} + +/*! + * @brief Disable TX empty interrupt. + * + * This function disables specific TX empty interrupt. + * + * @param base Register base address for the module. + * @param disableMask Bitmap of the interrupts to disable. + * + * Example: + @code + // To disable TX0 empty interrupts. + MU_DisableTxEmptyInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_DisableTxEmptyInt(MU_Type * base, uint32_t index) +{ + base->CR &= ~(MU_CR_GIRn_MASK | (MU_CR_TIE0_MASK>>index)); // Clear GIRn , clear TIEn +} + +/* @} */ + +/*! + * @name Receive Messages. + * @{ + */ + +/*! + * @brief Try to receive a message. + * + * This function tries to receive a message, if the RX register is not full, + * this function returns kStatus_MU_RxNotFull. + * + * @param base Register base address for the module. + * @param regIdex Rx register index. + * @param msg Message to receive. + * @retval kStatus_MU_Success Message receive successfully. + * @retval kStatus_MU_RxNotFull Message not received because RX is not full. + */ +mu_status_t MU_TryReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg); + +/*! + * @brief Block to receive a message. + * + * This function waits until RX register is full and receive the message. + * + * @param base Register base address for the module. + * @param regIdex Rx register index. + * @param msg Message to receive. + */ +void MU_ReceiveMsg(MU_Type * base, uint32_t regIndex, uint32_t *msg); + +/*! + * @brief Check RX full status. + * + * This function checks the specific receive register full status. + * + * @param base Register base address for the module. + * @param index RX register index to check. + * @retval true RX register is full. + * @retval false RX register is not full. + */ +static inline bool MU_IsRxFull(MU_Type * base, uint32_t index) +{ + return (bool)(base->SR & (MU_SR_RF0_MASK >> index)); +} + +/*! + * @brief Enable RX full interrupt. + * + * This function enables specific RX full interrupt. + * + * @param base Register base address for the module. + * @param index RX interrupt index to enable. + * + * Example: + @code + // To enable RX0 full interrupts. + MU_EnableRxFullInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_EnableRxFullInt(MU_Type * base, uint32_t index) +{ + base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn + | (MU_CR_RIE0_MASK>>index); // Set RIEn +} + +/*! + * @brief Disable RX full interrupt. + * + * This function disables specific RX full interrupt. + * + * @param base Register base address for the module. + * @param disableMask Bitmap of the interrupts to disable. + * + * Example: + @code + // To disable RX0 full interrupts. + MU_DisableRxFullInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_DisableRxFullInt(MU_Type * base, uint32_t index) +{ + base->CR &= ~(MU_CR_GIRn_MASK | (MU_CR_RIE0_MASK>>index)); // Clear GIRn, clear RIEn +} + +/* @} */ + +/*! + * @name General Purpose Interrupt. + * @{ + */ + +/*! + * @brief Enable general purpose interrupt. + * + * This function enables specific general purpose interrupt. + * + * @param base Register base address for the module. + * @param index General purpose interrupt index to enable. + * + * Example: + @code + // To enable general purpose interrupts 0. + MU_EnableGeneralInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_EnableGeneralInt(MU_Type * base, uint32_t index) +{ + base->CR = (base->CR & ~MU_CR_GIRn_MASK) // Clear GIRn + | (MU_CR_GIE0_MASK>>index); // Set GIEn +} + +/*! + * @brief Disable general purpose interrupt. + * + * This function disables specific general purpose interrupt. + * + * @param base Register base address for the module. + * @param index General purpose interrupt index to disable. + * + * Example: + @code + // To disable general purpose interrupts 0. + MU_DisableGeneralInt(MU0_BASE, 0U); + @endcode + */ +static inline void MU_DisableGeneralInt(MU_Type * base, uint32_t index) +{ + base->CR &= ~(MU_CR_GIRn_MASK | (MU_CR_GIE0_MASK>>index)); // Clear GIRn, clear GIEn +} + +/*! + * @brief Check specific general purpose interrupt pending flag. + * + * This function checks the specific general purpose interrupt pending status. + * + * @param base Register base address for the module. + * @param index Index of the general purpose interrupt flag to check. + * @retval true General purpose interrupt is pending. + * @retval false General purpose interrupt is not pending. + */ +static inline bool MU_IsGeneralIntPending(MU_Type * base, uint32_t index) +{ + return (bool)(base->SR & (MU_SR_GIP0_MASK >> index)); +} + +/*! + * @brief Clear specific general purpose interrupt pending flag. + * + * This function clears the specific general purpose interrupt pending status. + * + * @param base Register base address for the module. + * @param index Index of the general purpose interrupt flag to clear. + */ +static inline void MU_ClearGeneralIntPending(MU_Type * base, uint32_t index) +{ + base->SR = (MU_SR_GIP0_MASK >> index); +} + +/*! + * @brief Trigger specific general purpose interrupt. + * + * This function triggers specific general purpose interrupt to other core. + * + * To ensure proper operations, make sure the correspond general purpose + * interrupt triggered previously has been accepted by the other core. The + * function MU_IsGeneralIntAccepted can be used for this check. If the + * previous general interrupt has not been accepted by the other core, this + * function does not trigger interrupt actually and returns an error. + * + * @param base Register base address for the module. + * @param index Index of general purpose interrupt to trigger. + * @retval kStatus_MU_Success Interrupt has been triggered successfully. + * @retval kStatus_MU_IntPending Previous interrupt has not been accepted. + */ +mu_status_t MU_TriggerGeneralInt(MU_Type * base, uint32_t index); + +/*! + * @brief Check specific general purpose interrupt is accepted or not. + * + * This function checks whether the specific general purpose interrupt has + * been accepted by the other core or not. + * + * @param base Register base address for the module. + * @param index Index of the general purpose interrupt to check. + * @retval true General purpose interrupt is accepted. + * @retval false General purpose interrupt is not accepted. + */ +static inline bool MU_IsGeneralIntAccepted(MU_Type * base, uint32_t index) +{ + return !(bool)(base->CR & (MU_CR_GIR0_MASK >> index)); +} + +/* @} */ + +/*! + * @name Flags + * @{ + */ + +/*! + * @brief Try to set some bits of the 3-bit flag reflect on the other MU side. + * + * This functions tries to set some bits of the 3-bit flag. If previous flags + * update is still pending, this function returns kStatus_MU_FlagPending. + * + * @param base Register base address for the module. + * @retval kStatus_MU_Success Flag set successfully. + * @retval kStatus_MU_FlagPending Previous flag update is pending. + */ +mu_status_t MU_TrySetFlags(MU_Type * base, uint32_t flags); + +/*! + * @brief Set some bits of the 3-bit flag reflect on the other MU side. + * + * This functions set some bits of the 3-bit flag. If previous flags update is + * still pending, this function blocks and polls to set the flag. + * + * @param base Register base address for the module. + */ +void MU_SetFlags(MU_Type * base, uint32_t flags); + +/*! + * @brief Checks whether the previous flag update is pending. + * + * After setting flags, the flags update request is pending until internally + * acknowledged. During the pending period, it is not allowed to set flags again. + * This function is used to check the pending status, it can be used together + * with function MU_TrySetFlags. + * + * @param base Register base address for the module. + * @return True if pending, false if not. + */ +static inline bool MU_IsFlagPending(MU_Type * base) +{ + return (bool)(base->SR & MU_SR_FUP_MASK); +} + +/*! + * @brief Get the current value of the 3-bit flag set by other side. + * + * This functions gets the current value of the 3-bit flag. + * + * @param base Register base address for the module. + * @return flags Current value of the 3-bit flag. + */ +static inline uint32_t MU_GetFlags(MU_Type * base) +{ + return base->SR & MU_SR_Fn_MASK; +} + +/* @} */ + +/*! + * @name Misc. + * @{ + */ + +/*! + * @brief Get the power mode of the other core. + * + * This functions gets the power mode of the other core. + * + * @param base Register base address for the module. + * @return powermode Power mode of the other core. + */ +static inline mu_power_mode_t MU_GetOtherCorePowerMode(MU_Type * base) +{ + return (mu_power_mode_t)((base->SR & MU_SR_PM_MASK) >> MU_SR_PM_SHIFT); +} + +/*! + * @brief Get the event pending status. + * + * This functions gets the event pending status. To ensure events have been + * posted to the other side before entering STOP mode, verify the + * event pending status using this function. + * + * @param base Register base address for the module. + * @retval true Event is pending. + * @retval false Event is not pending. + */ +static inline bool MU_IsEventPending(MU_Type * base) +{ + return (bool)(base->SR & MU_SR_EP_MASK); +} + +/*! + * @brief Get the the MU message status. + * + * This functions gets TX/RX and general purpose interrupt pending status. The + * parameter is passed in as bitmask of the status to check. + * + * @param base Register base address for the module. + * @param statusToCheck The status to check, see mu_msg_status_t. + * @return Status checked. + * + * Example: + @code + // To check TX0 empty status. + MU_GetMsgStatus(MU0_BASE, kMuTxEmpty0); + + // To check all RX full status. + MU_GetMsgStatus(MU0_BASE, kMuRxFull); + + // To check general purpose interrupt 0 and 3 pending status. + MU_GetMsgStatus(MU0_BASE, kMuGenInt0 | kMuGenInt3); + + // To check all status. + MU_GetMsgStatus(MU0_BASE, kMuStatusAll); + + @endcode + */ +static inline uint32_t MU_GetMsgStatus(MU_Type * base, uint32_t statusToCheck) +{ + return base->SR & statusToCheck; +} + +/* @} */ + +#if defined(__cplusplus) +} +#endif + +/*! + * @} + */ + +#endif /* __MU_IMX_H__ */ +/****************************************************************************** + * EOF + *****************************************************************************/ diff --git a/drivers/rdc_imx/rdc.c b/drivers/rdc_imx/rdc.c new file mode 100644 index 000000000..30cba440a --- /dev/null +++ b/drivers/rdc_imx/rdc.c @@ -0,0 +1,89 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "rdc.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SetMrAccess + * Description : Set RDC memory region access permission for RDC domains + * + *END**************************************************************************/ +void RDC_SetMrAccess(RDC_Type * base, uint32_t mr, uint32_t startAddr, uint32_t endAddr, + uint8_t perm, bool enable, bool lock) +{ + base->MR[mr].MRSA = startAddr; + base->MR[mr].MREA = endAddr; + base->MR[mr].MRC = perm | (enable ? RDC_MRC_ENA_MASK : 0) | (lock ? RDC_MRC_LCK_MASK : 0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_GetMrAccess + * Description : Get RDC memory region access permission for RDC domains + * + *END**************************************************************************/ +uint8_t RDC_GetMrAccess(RDC_Type * base, uint32_t mr, uint32_t *startAddr, uint32_t *endAddr) +{ + if (startAddr) + *startAddr = base->MR[mr].MRSA; + if (endAddr) + *endAddr = base->MR[mr].MREA; + + return base->MR[mr].MRC & 0xFF; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_GetViolationStatus + * Description : Get RDC memory violation status + * + *END**************************************************************************/ +bool RDC_GetViolationStatus(RDC_Type * base, uint32_t mr, uint32_t *violationAddr, uint32_t *violationDomain) +{ + uint32_t mrvs; + + mrvs = base->MR[mr].MRVS; + + if (violationAddr) + *violationAddr = mrvs & RDC_MRVS_VADR_MASK; + if (violationDomain) + *violationDomain = (mrvs & RDC_MRVS_VDID_MASK) >> RDC_MRVS_VDID_SHIFT; + + return (bool)(mrvs & RDC_MRVS_AD_MASK); +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/rdc_imx/rdc.h b/drivers/rdc_imx/rdc.h new file mode 100644 index 000000000..872e39d40 --- /dev/null +++ b/drivers/rdc_imx/rdc.h @@ -0,0 +1,270 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RDC_H__ +#define __RDC_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup rdc_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name RDC State Control + * @{ + */ + +/*! + * @brief Get domain ID of core that is reading this + * + * @param base RDC base pointer. + * @return Domain ID of self core + */ +static inline uint32_t RDC_GetSelfDomainID(RDC_Type * base) +{ + return (base->STAT & RDC_STAT_DID_MASK) >> RDC_STAT_DID_SHIFT; +} + +/*! + * @brief Check whether memory region controlled by RDC is accessible after low power recovery + * + * @param base RDC base pointer. + * @return Memory region power status. + * - true: on and accessible. + * - false: off. + */ +static inline bool RDC_IsMemPowered(RDC_Type * base) +{ + return (bool)(base->STAT & RDC_STAT_PDS_MASK); +} + +/*! + * @brief Check whether there's pending RDC memory region restoration interrupt + * + * @param base RDC base pointer. + * @return RDC interrupt status + * - true: Interrupt pending. + * - false: No interrupt pending. + */ +static inline bool RDC_IsIntPending(RDC_Type * base) +{ + return (bool)(base->INTSTAT); +} + +/*! + * @brief Clear interrupt status + * + * @param base RDC base pointer. + */ +static inline void RDC_ClearStatusFlag(RDC_Type * base) +{ + base->INTSTAT = RDC_INTSTAT_INT_MASK; +} + +/*! + * @brief Set RDC interrupt mode + * + * @param base RDC base pointer + * @param enable RDC interrupt control. + * - true: enable interrupt. + * - false: disable interrupt. + */ +static inline void RDC_SetIntCmd(RDC_Type * base, bool enable) +{ + base->INTCTRL = enable ? RDC_INTCTRL_RCI_EN_MASK : 0; +} + +/*@}*/ + +/*! + * @name RDC Domain Control + * @{ + */ + +/*! + * @brief Set RDC domain ID for RDC master + * + * @param base RDC base pointer + * @param mda RDC master assignment (see @ref _rdc_mda in rdc_defs_.h) + * @param domainId RDC domain ID (0-3) + * @param lock Whether to lock this setting? Once locked, no one can change the domain assignment until reset + */ +static inline void RDC_SetDomainID(RDC_Type * base, uint32_t mda, uint32_t domainId, bool lock) +{ + assert (domainId <= RDC_MDA_DID_MASK); + + base->MDA[mda] = RDC_MDA_DID(domainId) | (lock ? RDC_MDA_LCK_MASK : 0); +} + +/*! + * @brief Get RDC domain ID for RDC master + * + * @param base RDC base pointer + * @param mda RDC master assignment (see @ref _rdc_mda in rdc_defs_.h) + * @return RDC domain ID (0-3) + */ +static inline uint32_t RDC_GetDomainID(RDC_Type * base, uint32_t mda) +{ + return base->MDA[mda] & RDC_MDA_DID_MASK; +} + +/*! + * @brief Set RDC peripheral access permission for RDC domains + * + * @param base RDC base pointer + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @param perm RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) + * @param sreq Force acquiring SEMA42 to access this peripheral or not + * @param lock Whether to lock this setting or not. Once locked, no one can change the RDC setting until reset + */ +static inline void RDC_SetPdapAccess(RDC_Type * base, uint32_t pdap, uint8_t perm, bool sreq, bool lock) +{ + base->PDAP[pdap] = perm | (sreq ? RDC_PDAP_SREQ_MASK : 0) | (lock ? RDC_PDAP_LCK_MASK : 0); +} + +/*! + * @brief Get RDC peripheral access permission for RDC domains + * + * @param base RDC base pointer + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @return RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) + */ +static inline uint8_t RDC_GetPdapAccess(RDC_Type * base, uint32_t pdap) +{ + return base->PDAP[pdap] & 0xFF; +} + +/*! + * @brief Check whether RDC semaphore is required to access the peripheral + * + * @param base RDC base pointer + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @return RDC semaphore required or not. + * - true: RDC semaphore is required. + * - false: RDC semaphore is not required. + */ +static inline bool RDC_IsPdapSemaphoreRequired(RDC_Type * base, uint32_t pdap) +{ + return (bool)(base->PDAP[pdap] & RDC_PDAP_SREQ_MASK); +} + +/*! + * @brief Set RDC memory region access permission for RDC domains + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_.h) + * @param startAddr memory region start address (inclusive) + * @param endAddr memory region end address (exclusive) + * @param perm RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) + * @param enable Enable this memory region for RDC control or not + * @param lock Whether to lock this setting or not. Once locked, no one can change the RDC setting until reset + */ +void RDC_SetMrAccess(RDC_Type * base, uint32_t mr, uint32_t startAddr, uint32_t endAddr, + uint8_t perm, bool enable, bool lock); + +/*! + * @brief Get RDC memory region access permission for RDC domains + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_.h) + * @param startAddr pointer to get memory region start address (inclusive), NULL is allowed. + * @param endAddr pointer to get memory region end address (exclusive), NULL is allowed. + * @return RDC access permission from RDC domain to peripheral (byte: D3R D3W D2R D2W D1R D1W D0R D0W) + */ +uint8_t RDC_GetMrAccess(RDC_Type * base, uint32_t mr, uint32_t *startAddr, uint32_t *endAddr); + + +/*! + * @brief Check whether the memory region is enabled + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see _rdc_mr in rdc_defs_.h) + * @return Memory region enabled or not. + * - true: Memory region is enabled. + * - false: Memory region is not enabled. + */ +static inline bool RDC_IsMrEnabled(RDC_Type * base, uint32_t mr) +{ + return (bool)(base->MR[mr].MRC & RDC_MRC_ENA_MASK); +} + +/*! + * @brief Get memory violation status + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_.h) + * @param violationAddr Pointer to store violation address, NULL allowed + * @param violationDomain Pointer to store domain ID causing violation, NULL allowed + * @return Memory violation occurred or not. + * - true: violation happened. + * - false: No violation happened. + */ +bool RDC_GetViolationStatus(RDC_Type * base, uint32_t mr, uint32_t *violationAddr, uint32_t *violationDomain); + +/*! + * @brief Clear RDC violation status + * + * @param base RDC base pointer + * @param mr RDC memory region assignment (see @ref _rdc_mr in rdc_defs_.h) + */ +static inline void RDC_ClearViolationStatus(RDC_Type * base, uint32_t mr) +{ + base->MR[mr].MRVS = RDC_MRVS_AD_MASK; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __RDC_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/rdc_sema_imx/rdc_semaphore.c b/drivers/rdc_sema_imx/rdc_semaphore.c new file mode 100644 index 000000000..3f97d90f9 --- /dev/null +++ b/drivers/rdc_sema_imx/rdc_semaphore.c @@ -0,0 +1,187 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "rdc_semaphore.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * Private Functions + ******************************************************************************/ +static RDC_SEMAPHORE_Type *RDC_SEMAPHORE_GetGate(uint32_t *pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + + if (*pdap < 64) + semaphore = RDC_SEMAPHORE1; + else + { + semaphore = RDC_SEMAPHORE2; + *pdap -= 64; + } + + return semaphore; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_TryLock + * Description : Lock RDC semaphore for shared peripheral access + * + *END**************************************************************************/ +rdc_semaphore_status_t RDC_SEMAPHORE_TryLock(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + semaphore->GATE[index] = RDC_SEMAPHORE_GATE_GTFSM(RDC_SEMAPHORE_MASTER_SELF + 1); + + return ((semaphore->GATE[index] & RDC_SEMAPHORE_GATE_GTFSM_MASK) == + RDC_SEMAPHORE_GATE_GTFSM(RDC_SEMAPHORE_MASTER_SELF + 1)) ? + statusRdcSemaphoreSuccess : statusRdcSemaphoreBusy; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_Lock + * Description : Lock RDC semaphore for shared peripheral access, polling until + * success. + * + *END**************************************************************************/ +void RDC_SEMAPHORE_Lock(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + do { + /* Wait gate status free */ + while (semaphore->GATE[index] & RDC_SEMAPHORE_GATE_GTFSM_MASK) { } + semaphore->GATE[index] = RDC_SEMAPHORE_GATE_GTFSM(RDC_SEMAPHORE_MASTER_SELF + 1); + } while ((semaphore->GATE[index] & RDC_SEMAPHORE_GATE_GTFSM_MASK) != + RDC_SEMAPHORE_GATE_GTFSM(RDC_SEMAPHORE_MASTER_SELF + 1)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_Unlock + * Description : Unlock RDC semaphore + * + *END**************************************************************************/ +void RDC_SEMAPHORE_Unlock(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + semaphore->GATE[index] = RDC_SEMAPHORE_GATE_GTFSM(0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_GetLockDomainID + * Description : Get domain ID which locks the semaphore + * + *END**************************************************************************/ +uint32_t RDC_SEMAPHORE_GetLockDomainID(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + return (semaphore->GATE[index] & RDC_SEMAPHORE_GATE_LDOM_MASK) >> RDC_SEMAPHORE_GATE_LDOM_SHIFT; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_GetLockMaster + * Description : Get master index which locks the semaphore + * + *END**************************************************************************/ +uint32_t RDC_SEMAPHORE_GetLockMaster(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + uint8_t master; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + master = (semaphore->GATE[index] & RDC_SEMAPHORE_GATE_GTFSM_MASK) >> RDC_SEMAPHORE_GATE_GTFSM_SHIFT; + + return master == 0 ? RDC_SEMAPHORE_MASTER_NONE : master - 1; +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_Reset + * Description : Reset RDC semaphore to unlocked status + * + *END**************************************************************************/ +void RDC_SEMAPHORE_Reset(uint32_t pdap) +{ + RDC_SEMAPHORE_Type *semaphore; + uint32_t index = pdap; + + semaphore = RDC_SEMAPHORE_GetGate(&index); + + /* The reset state machine must be in idle state */ + assert ((semaphore->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) == 0); + + semaphore->RSTGT_W = 0xE2; + semaphore->RSTGT_W = 0x1D | RDC_SEMAPHORE_RSTGT_W_RSTGTN(index); +} + +/*FUNCTION********************************************************************** + * + * Function Name : RDC_SEMAPHORE_ResetAll + * Description : Reset all RDC semaphores to unlocked status for certain + * RDC_SEMAPHORE instance + * + *END**************************************************************************/ +void RDC_SEMAPHORE_ResetAll(RDC_SEMAPHORE_Type *base) +{ + /* The reset state machine must be in idle state */ + assert ((base->RSTGT_R & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK) == 0); + + base->RSTGT_W = 0xE2; + base->RSTGT_W = 0x1D | RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/rdc_sema_imx/rdc_semaphore.h b/drivers/rdc_sema_imx/rdc_semaphore.h new file mode 100644 index 000000000..ec990b8b9 --- /dev/null +++ b/drivers/rdc_sema_imx/rdc_semaphore.h @@ -0,0 +1,140 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __RDC_SEMAPHORE_H__ +#define __RDC_SEMAPHORE_H__ + +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup rdc_semaphore_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define RDC_SEMAPHORE_MASTER_NONE (0xFF) + +/*! @brief RDC Semaphore status return codes. */ +typedef enum _rdc_semaphore_status +{ + statusRdcSemaphoreSuccess = 0U, /*!< Success. */ + statusRdcSemaphoreBusy = 1U, /*!< RDC semaphore has been locked by other processor. */ +} rdc_semaphore_status_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name RDC_SEMAPHORE State Control + * @{ + */ + +/*! + * @brief Lock RDC semaphore for shared peripheral access + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @retval statusRdcSemaphoreSuccess Lock the semaphore successfully. + * @retval statusRdcSemaphoreBusy Semaphore has been locked by other processor. + */ +rdc_semaphore_status_t RDC_SEMAPHORE_TryLock(uint32_t pdap); + +/*! + * @brief Lock RDC semaphore for shared peripheral access, polling until success. + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + */ +void RDC_SEMAPHORE_Lock(uint32_t pdap); + +/*! + * @brief Unlock RDC semaphore + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + */ +void RDC_SEMAPHORE_Unlock(uint32_t pdap); + +/*! + * @brief Get domain ID which locks the semaphore + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @return domain ID which locks the RDC semaphore + */ +uint32_t RDC_SEMAPHORE_GetLockDomainID(uint32_t pdap); + +/*! + * @brief Get master index which locks the semaphore + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + * @return master index which locks the RDC semaphore, or RDC_SEMAPHORE_MASTER_NONE + * to indicate it is not locked. + */ +uint32_t RDC_SEMAPHORE_GetLockMaster(uint32_t pdap); + +/*@}*/ + +/*! + * @name RDC_SEMAPHORE Reset Control + * @{ + */ + +/*! + * @brief Reset RDC semaphore to unlocked status + * + * @param pdap RDC peripheral assignment (see @ref _rdc_pdap in rdc_defs_.h) + */ +void RDC_SEMAPHORE_Reset(uint32_t pdap); + +/*! + * @brief Reset all RDC semaphore to unlocked status for certain RDC_SEMAPHORE instance + * + * @param base RDC semaphore base pointer. + */ +void RDC_SEMAPHORE_ResetAll(RDC_SEMAPHORE_Type *base); + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __RDC_SEMAPHORE_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/sema4_imx/sema4.c b/drivers/sema4_imx/sema4.c new file mode 100644 index 000000000..aabdfecef --- /dev/null +++ b/drivers/sema4_imx/sema4.c @@ -0,0 +1,199 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include +#include "sema4.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_TryLock + * Description : Lock SEMA4 gate for exclusive access between multicore + * + *END**************************************************************************/ +sema4_status_t SEMA4_TryLock(SEMA4_Type *base, uint32_t gateIndex) +{ + __IO uint8_t *gate; + + assert(gateIndex < 16); + + gate = &base->GATE00 + gateIndex; + + *gate = SEMA4_GATE00_GTFSM(SEMA4_PROCESSOR_SELF + 1); + + return ((*gate & SEMA4_GATE00_GTFSM_MASK) == SEMA4_GATE00_GTFSM(SEMA4_PROCESSOR_SELF + 1)) ? + statusSema4Success : statusSema4Busy; +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_Lock + * Description : Lock SEMA4 gate for exclusive access between multicore, + * polling until success + * + *END**************************************************************************/ +void SEMA4_Lock(SEMA4_Type *base, uint32_t gateIndex) +{ + __IO uint8_t *gate; + + assert(gateIndex < 16); + + gate = &base->GATE00 + gateIndex; + + do { + /* Wait gate status free */ + while (*gate & SEMA4_GATE00_GTFSM_MASK) { } + *gate = SEMA4_GATE00_GTFSM(SEMA4_PROCESSOR_SELF + 1); + } while ((*gate & SEMA4_GATE00_GTFSM_MASK) != SEMA4_GATE00_GTFSM(SEMA4_PROCESSOR_SELF + 1)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_Unlock + * Description : Unlock SEMA4 gate + * + *END**************************************************************************/ +void SEMA4_Unlock(SEMA4_Type *base, uint32_t gateIndex) +{ + __IO uint8_t *gate; + + assert(gateIndex < 16); + + gate = &base->GATE00 + gateIndex; + + *gate = SEMA4_GATE00_GTFSM(0); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_GetLockProcessor + * Description : Get master index which locks the semaphore + * + *END**************************************************************************/ +uint32_t SEMA4_GetLockProcessor(SEMA4_Type *base, uint32_t gateIndex) +{ + __IO uint8_t *gate; + uint8_t proc; + + assert(gateIndex < 16); + + gate = &base->GATE00 + gateIndex; + + proc = (*gate & SEMA4_GATE00_GTFSM_MASK) >> SEMA4_GATE00_GTFSM_SHIFT; + + return proc == 0 ? SEMA4_PROCESSOR_NONE : proc - 1; +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_ResetGate + * Description : Reset SEMA4 gate to unlocked status + * + *END**************************************************************************/ +void SEMA4_ResetGate(SEMA4_Type *base, uint32_t gateIndex) +{ + assert(gateIndex < 16); + + /* The reset state machine must be in idle state */ + assert ((base->RSTGT & 0x30) == 0); + + base->RSTGT = 0xE2; + base->RSTGT = 0x1D | SEMA4_RSTGT_RSTGTN(gateIndex); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_ResetAllGates + * Description : Reset all SEMA4 gates to unlocked status for certain + * SEMA4 instance + * + *END**************************************************************************/ +void SEMA4_ResetAllGates(SEMA4_Type *base) +{ + /* The reset state machine must be in idle state */ + assert ((base->RSTGT & 0x30) == 0); + + base->RSTGT = 0xE2; + base->RSTGT = 0x1D | SEMA4_RSTGT_RSTGTN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_ResetNotification + * Description : Reset SEMA4 IRQ notifications + * + *END**************************************************************************/ +void SEMA4_ResetNotification(SEMA4_Type *base, uint32_t gateIndex) +{ + assert(gateIndex < 16); + + /* The reset state machine must be in idle state */ + assert ((base->RSTNTF & 0x30) == 0); + + base->RSTNTF = 0x47; + base->RSTNTF = 0xB8 | SEMA4_RSTNTF_RSTNTN(gateIndex); +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_ResetAllNotifications + * Description : Reset all SEMA4 gates to unlocked status for certain + * SEMA4 instance + * + *END**************************************************************************/ +void SEMA4_ResetAllNotifications(SEMA4_Type *base) +{ + /* The reset state machine must be in idle state */ + assert ((base->RSTNTF & 0x30) == 0); + + base->RSTNTF = 0x47; + base->RSTNTF = 0xB8 | SEMA4_RSTNTF_RSTNTN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : SEMA4_SetIntCmd + * Description : Enable or disable SEMA4 IRQ notification. + * + *END**************************************************************************/ +void SEMA4_SetIntCmd(SEMA4_Type * base, uint16_t intMask, bool enable) +{ + if (enable) + base->CPnINE[SEMA4_PROCESSOR_SELF].INE |= intMask; + else + base->CPnINE[SEMA4_PROCESSOR_SELF].INE &= ~intMask; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/sema4_imx/sema4.h b/drivers/sema4_imx/sema4.h new file mode 100644 index 000000000..ff77185f0 --- /dev/null +++ b/drivers/sema4_imx/sema4.h @@ -0,0 +1,278 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __SEMA4_H__ +#define __SEMA4_H__ + +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup sema4_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +#define SEMA4_PROCESSOR_NONE (0xFF) +#define SEMA4_GATE_STATUS_FLAG(gate) ((uint16_t)(1U << ((gate) ^ 7))) + +/*! @brief Status flag. */ +enum _sema4_status_flag +{ + sema4StatusFlagGate0 = 1U << 7, /*!< Sema4 Gate 0 flag. */ + sema4StatusFlagGate1 = 1U << 6, /*!< Sema4 Gate 1 flag. */ + sema4StatusFlagGate2 = 1U << 5, /*!< Sema4 Gate 2 flag. */ + sema4StatusFlagGate3 = 1U << 4, /*!< Sema4 Gate 3 flag. */ + sema4StatusFlagGate4 = 1U << 3, /*!< Sema4 Gate 4 flag. */ + sema4StatusFlagGate5 = 1U << 2, /*!< Sema4 Gate 5 flag. */ + sema4StatusFlagGate6 = 1U << 1, /*!< Sema4 Gate 6 flag. */ + sema4StatusFlagGate7 = 1U << 0, /*!< Sema4 Gate 7 flag. */ + sema4StatusFlagGate8 = 1U << 15, /*!< Sema4 Gate 8 flag. */ + sema4StatusFlagGate9 = 1U << 14, /*!< Sema4 Gate 9 flag. */ + sema4StatusFlagGate10 = 1U << 13, /*!< Sema4 Gate 10 flag. */ + sema4StatusFlagGate11 = 1U << 12, /*!< Sema4 Gate 11 flag. */ + sema4StatusFlagGate12 = 1U << 11, /*!< Sema4 Gate 12 flag. */ + sema4StatusFlagGate13 = 1U << 10, /*!< Sema4 Gate 13 flag. */ + sema4StatusFlagGate14 = 1U << 9, /*!< Sema4 Gate 14 flag. */ + sema4StatusFlagGate15 = 1U << 8, /*!< Sema4 Gate 15 flag. */ +}; + +/*! @brief SEMA4 reset finite state machine. */ +enum _sema4_reset_state +{ + sema4ResetIdle = 0U, /*!< Idle, waiting for the first data pattern write. */ + sema4ResetMid = 1U, /*!< Waiting for the second data pattern write. */ + sema4ResetFinished = 2U, /*!< Reset completed. Software can't get this state. */ +}; + +/*! @brief SEMA4 status return codes. */ +typedef enum _sema4_status +{ + statusSema4Success = 0U, /*!< Success. */ + statusSema4Busy = 1U, /*!< SEMA4 gate has been locked by other processor. */ +} sema4_status_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name SEMA4 State Control + * @{ + */ + +/*! + * @brief Lock SEMA4 gate for exclusive access between multicore. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + * @retval statusSema4Success Lock the gate successfully. + * @retval statusSema4Busy SEMA4 gate has been locked by other processor. + */ +sema4_status_t SEMA4_TryLock(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Lock SEMA4 gate for exclusive access between multicore, polling until success. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + */ +void SEMA4_Lock(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Unlock SEMA4 gate. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + */ +void SEMA4_Unlock(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Get processor number which locks the SEMA4 gate. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + * @return processor number which locks the SEMA4 gate, or SEMA4_PROCESSOR_NONE + * to indicate the gate is not locked. + */ +uint32_t SEMA4_GetLockProcessor(SEMA4_Type *base, uint32_t gateIndex); + +/*@}*/ + +/*! + * @name SEMA4 Reset Control + * @{ + */ + +/*! + * @brief Reset SEMA4 gate to unlocked status. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + */ +void SEMA4_ResetGate(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Reset all SEMA4 gates to unlocked status. + * + * @param base SEMA4 base pointer. + */ +void SEMA4_ResetAllGates(SEMA4_Type *base); + +/*! + * @brief Get bus master number which performing the gate reset function. + * This function gets the bus master number which performing the + * gate reset function. + * + * @param base SEMA4 base pointer. + * @return Bus master number. + */ +static inline uint8_t SEMA4_GetGateResetBus(SEMA4_Type *base) +{ + return (uint8_t)(base->RSTGT & 7); +} + +/*! + * @brief Get sema4 gate reset state. + * This function gets current state of the sema4 reset gate finite + * state machine. + * + * @param base SEMA4 base pointer. + * @return Current state (see @ref _sema4_reset_state). + */ +static inline uint8_t SEMA4_GetGateResetState(SEMA4_Type *base) +{ + return (uint8_t)((base->RSTGT & 0x30) >> 4); +} + +/*! + * @brief Reset SEMA4 IRQ notification. + * + * @param base SEMA4 base pointer. + * @param gateIndex SEMA4 gate index. + */ +void SEMA4_ResetNotification(SEMA4_Type *base, uint32_t gateIndex); + +/*! + * @brief Reset all IRQ notifications. + * + * @param base SEMA4 base pointer. + */ +void SEMA4_ResetAllNotifications(SEMA4_Type *base); + +/*! + * @brief Get bus master number which performing the notification reset function. + * This function gets the bus master number which performing the notification + * reset function. + * + * @param base SEMA4 base pointer. + * @return Bus master number. + */ +static inline uint8_t SEMA4_GetNotificationResetBus(SEMA4_Type *base) +{ + return (uint8_t)(base->RSTNTF & 7); +} + +/*! + * @brief Get sema4 notification reset state. + * + * This function gets current state of the sema4 reset notification finite state machine. + * + * @param base SEMA4 base pointer. + * @return Current state (See @ref _sema4_reset_state). + */ +static inline uint8_t SEMA4_GetNotificationResetState(SEMA4_Type *base) +{ + return (uint8_t)((base->RSTNTF & 0x30) >> 4); +} + +/*@}*/ + +/*! + * @name SEMA4 Interrupt and Status Control + * @{ + */ + +/*! + * @brief Get SEMA4 notification status. + * + * @param base SEMA4 base pointer. + * @param flags SEMA4 gate status mask (See @ref _sema4_status_flag). + * @return SEMA4 notification status bits. If bit value is set, the corresponding + * gate's notification is available. + */ +static inline uint16_t SEMA4_GetStatusFlag(SEMA4_Type * base, uint16_t flags) +{ + return base->CPnNTF[SEMA4_PROCESSOR_SELF].NTF & flags; +} + +/*! + * @brief Enable or disable SEMA4 IRQ notification. + * + * @param base SEMA4 base pointer. + * @param intMask SEMA4 gate status mask (see @ref _sema4_status_flag). + * @param enable Enable/Disable Sema4 interrupt, only those gates whose intMask is set are affected. + * - true: Enable Sema4 interrupt. + * - false: Disable Sema4 interrupt. + */ +void SEMA4_SetIntCmd(SEMA4_Type * base, uint16_t intMask, bool enable); + +/*! + * @brief check whether SEMA4 IRQ notification enabled. + * + * @param base SEMA4 base pointer. + * @param flags SEMA4 gate status mask (see @ref _sema4_status_flag). + * @return SEMA4 notification interrupt enable status bits. If bit value is set, + * the corresponding gate's notification is enabled + */ +static inline uint16_t SEMA4_GetIntEnabled(SEMA4_Type * base, uint16_t flags) +{ + return base->CPnINE[SEMA4_PROCESSOR_SELF].INE & flags; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __SEMA4_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/uart_imx/uart_imx.c b/drivers/uart_imx/uart_imx.c new file mode 100644 index 000000000..e3bfcdf49 --- /dev/null +++ b/drivers/uart_imx/uart_imx.c @@ -0,0 +1,612 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "uart_imx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/******************************************************************************* + * Initialization and Configuration functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_Init + * Description : This function initializes the module according to uart + * initialize structure. + * + *END**************************************************************************/ +void UART_Init(UART_Type* base, const uart_init_config_t* initConfig) +{ + assert(initConfig); + + /* Disable UART Module. */ + UART_UCR1_REG(base) &= ~UART_UCR1_UARTEN_MASK; + + /* Reset UART register to its default value. */ + UART_Deinit(base); + + /* Set UART data word length, stop bit count, parity mode and communication + * direction according to uart init struct, disable RTS hardware flow + * control. */ + UART_UCR2_REG(base) |= (initConfig->wordLength | + initConfig->stopBitNum | + initConfig->parity | + initConfig->direction | + UART_UCR2_IRTS_MASK); + + /* For imx family device, UARTs are used in MUXED mode, + * so that this bit should always be set.*/ + UART_UCR3_REG(base) |= UART_UCR3_RXDMUXSEL_MASK; + + /* Set BaudRate according to uart initialize struct. */ + /* Baud Rate = Ref Freq / (16 * (UBMR + 1)/(UBIR+1)) */ + UART_SetBaudRate(base, initConfig->clockRate, initConfig->baudRate); +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_Deinit + * Description : This function reset Uart module register content to its + * default value. + * + *END**************************************************************************/ +void UART_Deinit(UART_Type* base) +{ + /* Disable UART Module */ + UART_UCR1_REG(base) &= ~UART_UCR1_UARTEN_MASK; + + /* Reset UART Module Register content to default value */ + UART_UCR1_REG(base) = 0x0; + UART_UCR2_REG(base) = UART_UCR2_SRST_MASK; + UART_UCR3_REG(base) = UART_UCR3_DSR_MASK | + UART_UCR3_DCD_MASK | + UART_UCR3_RI_MASK; + UART_UCR4_REG(base) = UART_UCR4_CTSTL(32); + UART_UFCR_REG(base) = UART_UFCR_TXTL(2) | UART_UFCR_RXTL(1); + UART_UESC_REG(base) = UART_UESC_ESC_CHAR(0x2B); + UART_UTIM_REG(base) = 0x0; + UART_ONEMS_REG(base) = 0x0; + UART_UTS_REG(base) = UART_UTS_TXEMPTY_MASK | UART_UTS_RXEMPTY_MASK; + UART_UMCR_REG(base) = 0x0; + + /* Reset the transmit and receive state machines, all FIFOs and register + * USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD and UTS[6-3]. */ + UART_UCR2_REG(base) &= ~UART_UCR2_SRST_MASK; + while (!(UART_UCR2_REG(base) & UART_UCR2_SRST_MASK)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetBaudRate + * Description : + * + *END**************************************************************************/ +void UART_SetBaudRate(UART_Type* base, uint32_t clockRate, uint32_t baudRate) +{ + uint32_t numerator; + uint32_t denominator; + uint32_t divisor; + uint32_t refFreqDiv; + uint32_t divider = 1; + + /* get the approximately maximum divisor */ + numerator = clockRate; + denominator = baudRate << 4; + divisor = 1; + + while (denominator != 0) + { + divisor = denominator; + denominator = numerator % denominator; + numerator = divisor; + } + + numerator = clockRate / divisor; + denominator = (baudRate << 4) / divisor; + + /* numerator ranges from 1 ~ 7 * 64k */ + /* denominator ranges from 1 ~ 64k */ + if ((numerator > (UART_UBIR_INC_MASK * 7)) || + (denominator > UART_UBIR_INC_MASK)) + { + uint32_t m = (numerator - 1) / (UART_UBIR_INC_MASK * 7) + 1; + uint32_t n = (denominator - 1) / UART_UBIR_INC_MASK + 1; + uint32_t max = m > n ? m : n; + numerator /= max; + denominator /= max; + if (0 == numerator) + numerator = 1; + if (0 == denominator) + denominator = 1; + } + divider = (numerator - 1) / UART_UBIR_INC_MASK + 1; + + switch (divider) + { + case 1: + refFreqDiv = 0x05; + break; + case 2: + refFreqDiv = 0x04; + break; + case 3: + refFreqDiv = 0x03; + break; + case 4: + refFreqDiv = 0x02; + break; + case 5: + refFreqDiv = 0x01; + break; + case 6: + refFreqDiv = 0x00; + break; + case 7: + refFreqDiv = 0x06; + break; + default: + refFreqDiv = 0x05; + } + + UART_UFCR_REG(base) &= ~UART_UFCR_RFDIV_MASK; + UART_UFCR_REG(base) |= UART_UFCR_RFDIV(refFreqDiv); + UART_UBIR_REG(base) = UART_UBIR_INC(denominator - 1); + UART_UBMR_REG(base) = UART_UBMR_MOD(numerator / divider - 1); + UART_ONEMS_REG(base) = UART_ONEMS_ONEMS(clockRate/(1000 * divider)); +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetInvertCmd + * Description : This function is used to set the polarity of UART signal. + * The polarity of Tx and Rx can be set separately. + * + *END**************************************************************************/ +void UART_SetInvertCmd(UART_Type* base, uint32_t direction, bool invert) +{ + assert((direction & uartDirectionTx) || (direction & uartDirectionRx)); + + if (invert) + { + if (direction & UART_UCR2_RXEN_MASK) + UART_UCR4_REG(base) |= UART_UCR4_INVR_MASK; + if (direction & UART_UCR2_TXEN_MASK) + UART_UCR3_REG(base) |= UART_UCR3_INVT_MASK; + } + else + { + if (direction & UART_UCR2_RXEN_MASK) + UART_UCR4_REG(base) &= ~UART_UCR4_INVR_MASK; + if (direction & UART_UCR2_TXEN_MASK) + UART_UCR3_REG(base) &= ~UART_UCR3_INVT_MASK; + } +} + +/******************************************************************************* + * Low Power Mode functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetDozeMode + * Description : This function is used to set UART enable condition in the + * DOZE state. + * + *END**************************************************************************/ +void UART_SetDozeMode(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR1_REG(base) &= UART_UCR1_DOZE_MASK; + else + UART_UCR1_REG(base) |= ~UART_UCR1_DOZE_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetLowPowerMode + * Description : This function is used to set UART enable condition of the + * UART low power feature. + * + *END**************************************************************************/ +void UART_SetLowPowerMode(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR4_REG(base) &= ~UART_UCR4_LPBYP_MASK; + else + UART_UCR4_REG(base) |= UART_UCR4_LPBYP_MASK; +} + +/******************************************************************************* + * Interrupt and Flag control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetIntCmd + * Description : This function is used to set the enable condition of + * specific UART interrupt source. The available interrupt + * source can be select from uart_int_source enumeration. + * + *END**************************************************************************/ +void UART_SetIntCmd(UART_Type* base, uint32_t intSource, bool enable) +{ + volatile uint32_t* uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (intSource >> 16)); + uart_mask = (1 << (intSource & 0x0000FFFF)); + + if (enable) + *uart_reg |= uart_mask; + else + *uart_reg &= ~uart_mask; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_GetStatusFlag + * Description : This function is used to get the current status of specific + * UART status flag. The available status flag can be select + * from uart_status_flag & uart_interrupt_flag enumeration. + * + *END**************************************************************************/ +/* +bool UART_GetStatusFlag(UART_Type* base, uint32_t flag) +{ + volatile uint32_t* uart_reg = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + return (bool)((*uart_reg >> (flag & 0x0000FFFF)) & 0x1); +} +*/ + +/*FUNCTION********************************************************************** + * + * Function Name : UART_ClearStatusFlag + * Description : This function is used to get the current status + * of specific UART status flag. The available status + * flag can be select from uart_status_flag & + * uart_interrupt_flag enumeration. + * + *END**************************************************************************/ +void UART_ClearStatusFlag(UART_Type* base, uint32_t flag) +{ + volatile uint32_t* uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + uart_mask = (1 << (flag & 0x0000FFFF)); + + /* write 1 to clear. */ + *uart_reg = uart_mask; +} + +/******************************************************************************* + * DMA control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetDmaCmd + * Description : This function is used to set the enable condition of + * specific UART DMA source. The available DMA + * source can be select from uart_dma_source enumeration. + * + *END**************************************************************************/ +void UART_SetDmaCmd(UART_Type* base, uint32_t dmaSource, bool enable) +{ + volatile uint32_t* uart_reg = 0; + uint32_t uart_mask = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (dmaSource >> 16)); + uart_mask = (1 << (dmaSource & 0x0000FFFF)); + if (enable) + *uart_reg |= uart_mask; + else + *uart_reg &= ~uart_mask; +} + +/******************************************************************************* + * Hardware Flow control and Modem Signal functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetRtsFlowCtrlCmd + * Description : This function is used to set the enable condition of RTS + * Hardware flow control. + * + *END**************************************************************************/ +void UART_SetRtsFlowCtrlCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR2_REG(base) &= ~UART_UCR2_IRTS_MASK; + else + UART_UCR2_REG(base) |= UART_UCR2_IRTS_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetCtsFlowCtrlCmd + * Description : This function is used to set the enable condition of CTS + * auto control. if CTS control is enabled, the CTS_B pin will + * be controlled by the receiver, otherwise the CTS_B pin will + * controlled by UART_CTSPinCtrl function. + * + *END**************************************************************************/ +void UART_SetCtsFlowCtrlCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR2_REG(base) |= UART_UCR2_CTSC_MASK; + else + UART_UCR2_REG(base) &= ~UART_UCR2_CTSC_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetCtsPinLevel + * Description : This function is used to control the CTS_B pin state when + * auto CTS control is disabled. + * The CTS_B pin is low (active) + * The CTS_B pin is high (inactive) + * + *END**************************************************************************/ +void UART_SetCtsPinLevel(UART_Type* base, bool active) +{ + if (active) + UART_UCR2_REG(base) |= UART_UCR2_CTS_MASK; + else + UART_UCR2_REG(base) &= ~UART_UCR2_CTS_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetModemMode + * Description : This function is used to set the role(DTE/DCE) of UART module + * in RS-232 communication. + * + *END**************************************************************************/ +void UART_SetModemMode(UART_Type* base, uint32_t mode) +{ + assert((mode == uartModemModeDce) || (mode == uartModemModeDte)); + + if (uartModemModeDce == mode) + UART_UFCR_REG(base) &= ~UART_UFCR_DCEDTE_MASK; + else + UART_UFCR_REG(base) |= UART_UFCR_DCEDTE_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetDtrPinLevel + * Description : This function is used to set the pin state of + * DSR pin(for DCE mode) or DTR pin(for DTE mode) for the + * modem interface. + * + *END**************************************************************************/ +void UART_SetDtrPinLevel(UART_Type* base, bool active) +{ + if (active) + UART_UCR3_REG(base) |= UART_UCR3_DSR_MASK; + else + UART_UCR3_REG(base) &= ~UART_UCR3_DSR_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetDcdPinLevel + * Description : This function is used to set the pin state of + * DCD pin. THIS FUNCTION IS FOR DCE MODE ONLY. + * + *END**************************************************************************/ +void UART_SetDcdPinLevel(UART_Type* base, bool active) +{ + if (active) + UART_UCR3_REG(base) |= UART_UCR3_DCD_MASK; + else + UART_UCR3_REG(base) &= ~UART_UCR3_DCD_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetRiPinLevel + * Description : This function is used to set the pin state of + * RI pin. THIS FUNCTION IS FOR DCE MODE ONLY. + * + *END**************************************************************************/ +void UART_SetRiPinLevel(UART_Type* base, bool active) +{ + if (active) + UART_UCR3_REG(base) |= UART_UCR3_RI_MASK; + else + UART_UCR3_REG(base) &= ~UART_UCR3_RI_MASK; +} + +/******************************************************************************* + * Multiprocessor and RS-485 functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_Putchar9 + * Description : This function is used to send 9 Bits length data in + * RS-485 Multidrop mode. + * + *END**************************************************************************/ +void UART_Putchar9(UART_Type* base, uint16_t data) +{ + assert(data <= 0x1FF); + + if (data & 0x0100) + UART_UMCR_REG(base) |= UART_UMCR_TXB8_MASK; + else + UART_UMCR_REG(base) &= ~UART_UMCR_TXB8_MASK; + UART_UTXD_REG(base) = (data & UART_UTXD_TX_DATA_MASK); +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_Getchar9 + * Description : This functions is used to receive 9 Bits length data in + * RS-485 Multidrop mode. + * + *END**************************************************************************/ +uint16_t UART_Getchar9(UART_Type* base) +{ + uint16_t rxData = UART_URXD_REG(base); + + if (rxData & UART_URXD_PRERR_MASK) + { + rxData = (rxData & 0x00FF) | 0x0100; + } + else + { + rxData &= 0x00FF; + } + + return rxData; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetMultidropMode + * Description : This function is used to set the enable condition of + * 9-Bits data or Multidrop mode. + * + *END**************************************************************************/ +void UART_SetMultidropMode(UART_Type* base, bool enable) +{ + if (enable) + UART_UMCR_REG(base) |= UART_UMCR_MDEN_MASK; + else + UART_UMCR_REG(base) &= ~UART_UMCR_MDEN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetSlaveAddressDetectCmd + * Description : This function is used to set the enable condition of + * Automatic Address Detect Mode. + * + *END**************************************************************************/ +void UART_SetSlaveAddressDetectCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UMCR_REG(base) |= UART_UMCR_SLAM_MASK; + else + UART_UMCR_REG(base) &= ~UART_UMCR_SLAM_MASK; +} + +/******************************************************************************* + * IrDA control functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetIrDACmd + * Description : This function is used to set the enable condition of + * IrDA Mode. + * + *END**************************************************************************/ +void UART_SetIrDACmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR1_REG(base) |= UART_UCR1_IREN_MASK; + else + UART_UCR1_REG(base) &= ~UART_UCR1_IREN_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetIrDAVoteClock + * Description : This function is used to set the clock for the IR pulsed + * vote logic. The available clock can be select from + * uart_irda_vote_clock enumeration. + * + *END**************************************************************************/ +void UART_SetIrDAVoteClock(UART_Type* base, uint32_t voteClock) +{ + assert((voteClock == uartIrdaVoteClockSampling) || \ + (voteClock == uartIrdaVoteClockReference)); + + if (uartIrdaVoteClockSampling == voteClock) + UART_UCR4_REG(base) |= UART_UCR4_IRSC_MASK; + else + UART_UCR4_REG(base) &= ~UART_UCR4_IRSC_MASK; +} + +/******************************************************************************* + * Misc. functions + ******************************************************************************/ +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetAutoBaudRateCmd + * Description : This function is used to set the enable condition of + * Automatic Baud Rate Detection feature. + * + *END**************************************************************************/ +void UART_SetAutoBaudRateCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR1_REG(base) |= UART_UCR1_ADBR_MASK; + else + UART_UCR1_REG(base) &= ~UART_UCR1_ADBR_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SendBreakChar + * Description : This function is used to send BREAK character.It is + * important that SNDBRK is asserted high for a sufficient + * period of time to generate a valid BREAK. + * + *END**************************************************************************/ +void UART_SendBreakChar(UART_Type* base, bool active) +{ + if (active) + UART_UCR1_REG(base) |= UART_UCR1_SNDBRK_MASK; + else + UART_UCR1_REG(base) &= ~UART_UCR1_SNDBRK_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : UART_SetEscapeDecectCmd + * Description : This function is used to set the enable condition of + * Escape Sequence Detection feature. + * + *END**************************************************************************/ +void UART_SetEscapeDecectCmd(UART_Type* base, bool enable) +{ + if (enable) + UART_UCR2_REG(base) |= UART_UCR2_ESCEN_MASK; + else + UART_UCR2_REG(base) &= ~UART_UCR2_ESCEN_MASK; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/uart_imx/uart_imx.h b/drivers/uart_imx/uart_imx.h new file mode 100644 index 000000000..911b4e683 --- /dev/null +++ b/drivers/uart_imx/uart_imx.h @@ -0,0 +1,779 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __UART_IMX_H__ +#define __UART_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup uart_imx_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ + +/*! @brief Uart module initialization structure. */ +typedef struct _uart_init_config +{ + uint32_t clockRate; /*!< Current UART module clock freq. */ + uint32_t baudRate; /*!< Desired UART baud rate. */ + uint32_t wordLength; /*!< Data bits in one frame. */ + uint32_t stopBitNum; /*!< Number of stop bits in one frame. */ + uint32_t parity; /*!< Parity error check mode of this module. */ + uint32_t direction; /*!< Data transfer direction of this module. */ +} uart_init_config_t; + +/*! @brief UART number of data bits in a character. */ +enum _uart_word_length +{ + uartWordLength7Bits = 0x0, /*!< One character has 7 bits. */ + uartWordLength8Bits = UART_UCR2_WS_MASK, /*!< One character has 8 bits. */ +}; + +/*! @brief UART number of stop bits. */ +enum _uart_stop_bit_num +{ + uartStopBitNumOne = 0x0, /*!< One bit Stop. */ + uartStopBitNumTwo = UART_UCR2_STPB_MASK, /*!< Two bits Stop. */ +}; + +/*! @brief UART parity mode. */ +enum _uart_partity_mode +{ + uartParityDisable = 0x0, /*!< Parity error check disabled. */ + uartParityEven = UART_UCR2_PREN_MASK, /*!< Even error check is selected. */ + uartParityOdd = UART_UCR2_PREN_MASK | UART_UCR2_PROE_MASK, /*!< Odd error check is selected. */ +}; + +/*! @brief Data transfer direction. */ +enum _uart_direction_mode +{ + uartDirectionDisable = 0x0, /*!< Both Tx and Rx are disabled. */ + uartDirectionTx = UART_UCR2_TXEN_MASK, /*!< Tx is enabled. */ + uartDirectionRx = UART_UCR2_RXEN_MASK, /*!< Rx is enabled. */ + uartDirectionTxRx = UART_UCR2_TXEN_MASK | UART_UCR2_RXEN_MASK, /*!< Both Tx and Rx are enabled. */ +}; + +/*! @brief This enumeration contains the settings for all of the UART interrupt configurations. */ +enum _uart_interrupt +{ + uartIntAutoBaud = 0x0080000F, /*!< Automatic baud rate detection Interrupt Enable. */ + uartIntTxReady = 0x0080000D, /*!< transmitter ready Interrupt Enable. */ + uartIntIdle = 0x0080000C, /*!< IDLE Interrupt Enable. */ + uartIntRxReady = 0x00800009, /*!< Receiver Ready Interrupt Enable. */ + uartIntTxEmpty = 0x00800006, /*!< Transmitter Empty Interrupt Enable. */ + uartIntRtsDelta = 0x00800005, /*!< RTS Delta Interrupt Enable. */ + uartIntEscape = 0x0084000F, /*!< Escape Sequence Interrupt Enable. */ + uartIntRts = 0x00840004, /*!< Request to Send Interrupt Enable. */ + uartIntAgingTimer = 0x00840003, /*!< Aging Timer Interrupt Enable. */ + uartIntDtr = 0x0088000D, /*!< Data Terminal Ready Interrupt Enable. */ + uartIntParityError = 0x0088000C, /*!< Parity Error Interrupt Enable. */ + uartIntFrameError = 0x0088000B, /*!< Frame Error Interrupt Enable. */ + uartIntDcd = 0x00880009, /*!< Data Carrier Detect Interrupt Enable. */ + uartIntRi = 0x00880008, /*!< Ring Indicator Interrupt Enable. */ + uartIntRxDs = 0x00880006, /*!< Receive Status Interrupt Enable. */ + uartInttAirWake = 0x00880005, /*!< Asynchronous IR WAKE Interrupt Enable. */ + uartIntAwake = 0x00880004, /*!< Asynchronous WAKE Interrupt Enable. */ + uartIntDtrDelta = 0x00880003, /*!< Data Terminal Ready Delta Interrupt Enable. */ + uartIntAutoBaudCnt = 0x00880000, /*!< Autobaud Counter Interrupt Enable. */ + uartIntIr = 0x008C0008, /*!< Serial Infrared Interrupt Enable. */ + uartIntWake = 0x008C0007, /*!< WAKE Interrupt Enable. */ + uartIntTxComplete = 0x008C0003, /*!< TransmitComplete Interrupt Enable. */ + uartIntBreakDetect = 0x008C0002, /*!< BREAK Condition Detected Interrupt Enable. */ + uartIntRxOverrun = 0x008C0001, /*!< Receiver Overrun Interrupt Enable. */ + uartIntRxDataReady = 0x008C0000, /*!< Receive Data Ready Interrupt Enable. */ + uartIntRs485SlaveAddrMatch = 0x00B80003, /*!< RS-485 Slave Address Detected Interrupt Enable. */ +}; + +/*! @brief Flag for UART interrupt/DMA status check or polling status. */ +enum _uart_status_flag +{ + uartStatusRxCharReady = 0x0000000F, /*!< Rx Character Ready Flag. */ + uartStatusRxError = 0x0000000E, /*!< Rx Error Detect Flag. */ + uartStatusRxOverrunError = 0x0000000D, /*!< Rx Overrun Flag. */ + uartStatusRxFrameError = 0x0000000C, /*!< Rx Frame Error Flag. */ + uartStatusRxBreakDetect = 0x0000000B, /*!< Rx Break Detect Flag. */ + uartStatusRxParityError = 0x0000000A, /*!< Rx Parity Error Flag. */ + uartStatusParityError = 0x0094000F, /*!< Parity Error Interrupt Flag. */ + uartStatusRtsStatus = 0x0094000E, /*!< RTS_B Pin Status Flag. */ + uartStatusTxReady = 0x0094000D, /*!< Transmitter Ready Interrupt/DMA Flag. */ + uartStatusRtsDelta = 0x0094000C, /*!< RTS Delta Flag. */ + uartStatusEscape = 0x0094000B, /*!< Escape Sequence Interrupt Flag. */ + uartStatusFrameError = 0x0094000A, /*!< Frame Error Interrupt Flag. */ + uartStatusRxReady = 0x00940009, /*!< Receiver Ready Interrupt/DMA Flag. */ + uartStatusAgingTimer = 0x00940008, /*!< Ageing Timer Interrupt Flag. */ + uartStatusDtrDelta = 0x00940007, /*!< DTR Delta Flag. */ + uartStatusRxDs = 0x00940006, /*!< Receiver IDLE Interrupt Flag. */ + uartStatustAirWake = 0x00940005, /*!< Asynchronous IR WAKE Interrupt Flag. */ + uartStatusAwake = 0x00940004, /*!< Asynchronous WAKE Interrupt Flag. */ + uartStatusRs485SlaveAddrMatch = 0x00940003, /*!< RS-485 Slave Address Detected Interrupt Flag. */ + uartStatusAutoBaud = 0x0098000F, /*!< Automatic Baud Rate Detect Complete Flag. */ + uartStatusTxEmpty = 0x0098000E, /*!< Transmit Buffer FIFO Empty. */ + uartStatusDtr = 0x0098000D, /*!< DTR edge triggered interrupt flag. */ + uartStatusIdle = 0x0098000C, /*!< Idle Condition Flag. */ + uartStatusAutoBaudCntStop = 0x0098000B, /*!< Autobaud Counter Stopped Flag. */ + uartStatusRiDelta = 0x0098000A, /*!< Ring Indicator Delta Flag. */ + uartStatusRi = 0x00980009, /*!< Ring Indicator Input Flag. */ + uartStatusIr = 0x00980008, /*!< Serial Infrared Interrupt Flag. */ + uartStatusWake = 0x00980007, /*!< Wake Flag. */ + uartStatusDcdDelta = 0x00980006, /*!< Data Carrier Detect Delta Flag. */ + uartStatusDcd = 0x00980005, /*!< Data Carrier Detect Input Flag. */ + uartStatusRts = 0x00980004, /*!< RTS Edge Triggered Interrupt Flag. */ + uartStatusTxComplete = 0x00980003, /*!< Transmitter Complete Flag. */ + uartStatusBreakDetect = 0x00980002, /*!< BREAK Condition Detected Flag. */ + uartStatusRxOverrun = 0x00980001, /*!< Overrun Error Flag. */ + uartStatusRxDataReady = 0x00980000, /*!< Receive Data Ready Flag. */ +}; + +/*! @brief The events generate the DMA Request. */ +enum _uart_dma +{ + uartDmaRxReady = 0x00800008, /*!< Receive Ready DMA Enable. */ + uartDmaTxReady = 0x00800003, /*!< Transmitter Ready DMA Enable. */ + uartDmaAgingTimer = 0x00800002, /*!< Aging DMA Timer Enable. */ + uartDmaIdle = 0x008C0006, /*!< DMA IDLE Condition Detected Interrupt Enable. */ +}; + +/*! @brief RTS pin interrupt trigger edge. */ +enum _uart_rts_int_trigger_edge +{ + uartRtsTriggerEdgeRising = UART_UCR2_RTEC(0), /*!< RTS pin interrupt triggered on rising edge. */ + uartRtsTriggerEdgeFalling = UART_UCR2_RTEC(1), /*!< RTS pin interrupt triggered on falling edge. */ + uartRtsTriggerEdgeBoth = UART_UCR2_RTEC(2), /*!< RTS pin interrupt triggered on both edge. */ +}; + +/*! @brief UART module modem role selections. */ +enum _uart_modem_mode +{ + uartModemModeDce = 0, /*!< UART module works as DCE. */ + uartModemModeDte = UART_UFCR_DCEDTE_MASK, /*!< UART module works as DTE. */ +}; + +/*! @brief DTR pin interrupt trigger edge. */ +enum _uart_dtr_int_trigger_edge +{ + uartDtrTriggerEdgeRising = UART_UCR3_DPEC(0), /*!< DTR pin interrupt triggered on rising edge. */ + uartDtrTriggerEdgeFalling = UART_UCR3_DPEC(1), /*!< DTR pin interrupt triggered on falling edge. */ + uartDtrTriggerEdgeBoth = UART_UCR3_DPEC(2), /*!< DTR pin interrupt triggered on both edge. */ +}; + +/*! @brief IrDA vote clock selections. */ +enum _uart_irda_vote_clock +{ + uartIrdaVoteClockSampling = 0x0, /*!< The vote logic uses the sampling clock (16x baud rate) for normal operation. */ + uartIrdaVoteClockReference = UART_UCR4_IRSC_MASK, /*!< The vote logic uses the UART reference clock. */ +}; + +/*! @brief UART module Rx Idle condition selections. */ +enum _uart_rx_idle_condition +{ + uartRxIdleMoreThan4Frames = UART_UCR1_ICD(0), /*!< Idle for more than 4 frames. */ + uartRxIdleMoreThan8Frames = UART_UCR1_ICD(1), /*!< Idle for more than 8 frames. */ + uartRxIdleMoreThan16Frames = UART_UCR1_ICD(2), /*!< Idle for more than 16 frames. */ + uartRxIdleMoreThan32Frames = UART_UCR1_ICD(3), /*!< Idle for more than 32 frames. */ +}; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name UART Initialization and Configuration functions + * @{ + */ + +/*! + * @brief Initialize UART module with given initialization structure. + * + * @param base UART base pointer. + * @param initConfig UART initialization structure (see @ref uart_init_config_t structure above). + */ +void UART_Init(UART_Type* base, const uart_init_config_t* initConfig); + +/*! + * @brief This function reset UART module register content to its default value. + * + * @param base UART base pointer. + */ +void UART_Deinit(UART_Type* base); + +/*! + * @brief This function is used to Enable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Enable(UART_Type* base) +{ + UART_UCR1_REG(base) |= UART_UCR1_UARTEN_MASK; +} + +/*! + * @brief This function is used to Disable the UART Module. + * + * @param base UART base pointer. + */ +static inline void UART_Disable(UART_Type* base) +{ + UART_UCR1_REG(base) &= ~UART_UCR1_UARTEN_MASK; +} + +/*! + * @brief This function is used to set the baud rate of UART Module. + * + * @param base UART base pointer. + * @param clockRate UART module clock frequency. + * @param baudRate Desired UART module baud rate. + */ +void UART_SetBaudRate(UART_Type* base, uint32_t clockRate, uint32_t baudRate); + +/*! + * @brief This function is used to set the transform direction of UART Module. + * + * @param base UART base pointer. + * @param direction UART transfer direction (see @ref _uart_direction_mode enumeration). + */ +static inline void UART_SetDirMode(UART_Type* base, uint32_t direction) +{ + assert((direction & uartDirectionTx) || (direction & uartDirectionRx)); + + UART_UCR2_REG(base) = (UART_UCR2_REG(base) & ~(UART_UCR2_RXEN_MASK | UART_UCR2_TXEN_MASK)) | direction; +} + +/*! + * @brief This function is used to set the number of frames RXD is allowed to + * be idle before an idle condition is reported. The available condition + * can be select from @ref _uart_idle_condition enumeration. + * + * @param base UART base pointer. + * @param idleCondition The condition that an idle condition is reported + * (see @ref _uart_idle_condition enumeration). + */ +static inline void UART_SetRxIdleCondition(UART_Type* base, uint32_t idleCondition) +{ + assert(idleCondition <= uartRxIdleMoreThan32Frames); + + UART_UCR1_REG(base) = (UART_UCR1_REG(base) & ~UART_UCR1_ICD_MASK) | idleCondition; +} + +/*! + * @brief This function is used to set the polarity of UART signal. The polarity + * of Tx and Rx can be set separately. + * + * @param base UART base pointer. + * @param direction UART transfer direction (see @ref _uart_direction_mode enumeration). + * @param invert Set true to invert the polarity of UART signal. + */ +void UART_SetInvertCmd(UART_Type* base, uint32_t direction, bool invert); + +/*@}*/ + +/*! + * @name Low Power Mode functions. + * @{ + */ + +/*! + * @brief This function is used to set UART enable condition in the DOZE state. + * + * @param base UART base pointer. + * @param enable Enable/Disable UART module in doze mode. + * - true: Enable UART module in doze mode. + * - false: Disable UART module in doze mode. + */ +void UART_SetDozeMode(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set UART enable condition of the UART low power feature. + * + * @param base UART base pointer. + * @param enable Enable/Disable UART module low power feature. + * - true: Enable UART module low power feature. + * - false: Disable UART module low power feature. + */ +void UART_SetLowPowerMode(UART_Type* base, bool enable); + +/*@}*/ + +/*! + * @name Data transfer functions. + * @{ + */ + +/*! + * @brief This function is used to send data in RS-232 and IrDA Mode. + * A independent 9 Bits RS-485 send data function is provided. + * + * @param base UART base pointer. + * @param data Data to be set through UART module. + */ +static inline void UART_Putchar(UART_Type* base, uint8_t data) +{ + UART_UTXD_REG(base) = (data & UART_UTXD_TX_DATA_MASK); +} + +/*! + * @brief This function is used to receive data in RS-232 and IrDA Mode. + * A independent 9 Bits RS-485 receive data function is provided. + * + * @param base UART base pointer. + * @return The data received from UART module. + */ +static inline uint8_t UART_Getchar(UART_Type* base) +{ + return (uint8_t)(UART_URXD_REG(base) & UART_URXD_RX_DATA_MASK); +} + +/*@}*/ + +/*! + * @name Interrupt and Flag control functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * specific UART interrupt source. The available interrupt + * source can be select from @ref _uart_interrupt enumeration. + * + * @param base UART base pointer. + * @param intSource Available interrupt source for this module. + * @param enable Enable/Disable corresponding interrupt. + * - true: Enable corresponding interrupt. + * - false: Disable corresponding interrupt. + */ +void UART_SetIntCmd(UART_Type* base, uint32_t intSource, bool enable); + +/*! + * @brief This function is used to get the current status of specific + * UART status flag(including interrupt flag). The available + * status flag can be select from @ref _uart_status_flag enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to check. + * @return current state of corresponding status flag. + */ +static inline bool UART_GetStatusFlag(UART_Type* base, uint32_t flag){ + volatile uint32_t* uart_reg = 0; + + uart_reg = (uint32_t *)((uint32_t)base + (flag >> 16)); + return (bool)((*uart_reg >> (flag & 0x0000FFFF)) & 0x1); +} + +/*! + * @brief This function is used to get the current status + * of specific UART status flag. The available status + * flag can be select from @ref _uart_status_flag enumeration. + * + * @param base UART base pointer. + * @param flag Status flag to clear. + */ +void UART_ClearStatusFlag(UART_Type* base, uint32_t flag); + +/*@}*/ + +/*! + * @name DMA control functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * specific UART DMA source. The available DMA source + * can be select from @ref _uart_dma enumeration. + * + * @param base UART base pointer. + * @param dmaSource The Event that can generate DMA request. + * @param enable Enable/Disable corresponding DMA source. + * - true: Enable corresponding DMA source. + * - false: Disable corresponding DMA source. + */ +void UART_SetDmaCmd(UART_Type* base, uint32_t dmaSource, bool enable); + +/*@}*/ + +/*! + * @name FIFO control functions. + * @{ + */ + +/*! + * @brief This function is used to set the watermark of UART Tx FIFO. + * A maskable interrupt is generated whenever the data level in + * the TxFIFO falls below the Tx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Tx FIFO watermark. + */ +static inline void UART_SetTxFifoWatermark(UART_Type* base, uint8_t watermark) +{ + assert((watermark >= 2) && (watermark <= 32)); + UART_UFCR_REG(base) = (UART_UFCR_REG(base) & ~UART_UFCR_TXTL_MASK) | UART_UFCR_TXTL(watermark); +} + +/*! + * @brief This function is used to set the watermark of UART Rx FIFO. + * A maskable interrupt is generated whenever the data level in + * the RxFIFO reaches the Rx FIFO watermark. + * + * @param base UART base pointer. + * @param watermark The Rx FIFO watermark. + */ +static inline void UART_SetRxFifoWatermark(UART_Type* base, uint8_t watermark) +{ + assert(watermark <= 32); + UART_UFCR_REG(base) = (UART_UFCR_REG(base) & ~UART_UFCR_RXTL_MASK) | UART_UFCR_RXTL(watermark); +} + +/*@}*/ + +/*! + * @name Hardware Flow control and Modem Signal functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of RTS + * Hardware flow control. + * + * @param base UART base pointer. + * @param enable Enable/Disbale RTS hardware flow control. + * - true: Enable RTS hardware flow control. + * - false: Disbale RTS hardware flow control. + */ +void UART_SetRtsFlowCtrlCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the RTS interrupt trigger edge. + * The available trigger edge can be select from + * @ref _uart_rts_trigger_edge enumeration. + * + * @param base UART base pointer. + * @param triggerEdge Available RTS pin interrupt trigger edge. + */ +static inline void UART_SetRtsIntTriggerEdge(UART_Type* base, uint32_t triggerEdge) +{ + assert((triggerEdge == uartRtsTriggerEdgeRising) || \ + (triggerEdge == uartRtsTriggerEdgeFalling) || \ + (triggerEdge == uartRtsTriggerEdgeBoth)); + + UART_UCR2_REG(base) = (UART_UCR2_REG(base) & ~UART_UCR2_RTEC_MASK) | triggerEdge; +} + + +/*! + * @brief This function is used to set the enable condition of CTS + * auto control. if CTS control is enabled, the CTS_B pin + * is controlled by the receiver, otherwise the CTS_B pin is + * controlled by UART_CTSPinCtrl function. + * + * @param base UART base pointer. + * @param enable Enable/Disable CTS auto control. + * - true: Enable CTS auto control. + * - false: Disable CTS auto control. + */ +void UART_SetCtsFlowCtrlCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to control the CTS_B pin state when + * auto CTS control is disabled. + * The CTS_B pin is low(active) + * The CTS_B pin is high(inactive) + * + * @param base UART base pointer. + * @param active The CTS_B pin state to set. + * - true: the CTS_B pin active; + * - false: the CTS_B pin inactive. + */ +void UART_SetCtsPinLevel(UART_Type* base, bool active); + +/*! + * @brief This function is used to set the auto CTS_B pin control + * trigger level. The CTS_B pin is de-asserted when + * Rx FIFO reach CTS trigger level. + * + * @param base UART base pointer. + * @param triggerLevel Auto CTS_B pin control trigger level. + */ +static inline void UART_SetCtsTriggerLevel(UART_Type* base, uint8_t triggerLevel) +{ + assert(triggerLevel <= 32); + UART_UCR4_REG(base) = (UART_UCR4_REG(base) & ~UART_UCR4_CTSTL_MASK) | UART_UCR4_CTSTL(triggerLevel); +} + +/*! + * @brief This function is used to set the role (DTE/DCE) of UART module + * in RS-232 communication. + * + * @param base UART base pointer. + * @param mode The role(DTE/DCE) of UART module (see @ref _uart_modem_mode enumeration). + */ +void UART_SetModemMode(UART_Type* base, uint32_t mode); + +/*! + * @brief This function is used to set the edge of DTR_B (DCE) or + * DSR_B (DTE) on which an interrupt is generated. + * + * @param base UART base pointer. + * @param triggerEdge The trigger edge on which an interrupt is generated + * (see @ref _uart_dtr_trigger_edge enumeration above). + */ +static inline void UART_SetDtrIntTriggerEdge(UART_Type* base, uint32_t triggerEdge) +{ + assert((triggerEdge == uartDtrTriggerEdgeRising) || \ + (triggerEdge == uartDtrTriggerEdgeFalling) || \ + (triggerEdge == uartDtrTriggerEdgeBoth)); + + UART_UCR3_REG(base) = (UART_UCR3_REG(base) & ~UART_UCR3_DPEC_MASK) | triggerEdge; +} + +/*! + * @brief This function is used to set the pin state of DSR pin(for DCE mode) + * or DTR pin(for DTE mode) for the modem interface. + * + * @param base UART base pointer. + * @param active The state of DSR pin. + * - true: DSR/DTR pin is logic one. + * - false: DSR/DTR pin is logic zero. + */ +void UART_SetDtrPinLevel(UART_Type* base, bool active); + +/*! + * @brief This function is used to set the pin state of + * DCD pin. THIS FUNCTION IS FOR DCE MODE ONLY. + * + * @param base UART base pointer. + * @param active The state of DCD pin. + * - true: DCD_B pin is logic one (DCE mode) + * - false: DCD_B pin is logic zero (DCE mode) + */ +void UART_SetDcdPinLevel(UART_Type* base, bool active); + +/*! + * @brief This function is used to set the pin state of + * RI pin. THIS FUNCTION IS FOR DCE MODE ONLY. + * + * @param base UART base pointer. + * @param active The state of RI pin. + * - true: RI_B pin is logic one (DCE mode) + * - false: RI_B pin is logic zero (DCE mode) + */ +void UART_SetRiPinLevel(UART_Type* base, bool active); + +/*@}*/ + +/*! + * @name Multiprocessor and RS-485 functions. + * @{ + */ + +/*! + * @brief This function is used to send 9 Bits length data in + * RS-485 Multidrop mode. + * + * @param base UART base pointer. + * @param data Data(9 bits) to be set through UART module. + */ +void UART_Putchar9(UART_Type* base, uint16_t data); + +/*! + * @brief This functions is used to receive 9 Bits length data in + * RS-485 Multidrop mode. + * + * @param base UART base pointer. + * @return The data(9 bits) received from UART module. + */ +uint16_t UART_Getchar9(UART_Type* base); + +/*! + * @brief This function is used to set the enable condition of + * 9-Bits data or Multidrop mode. + * + * @param base UART base pointer. + * @param enable Enable/Disable Multidrop mode. + * - true: Enable Multidrop mode. + * - false: Disable Multidrop mode. + */ +void UART_SetMultidropMode(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the enable condition of + * Automatic Address Detect Mode. + * + * @param base UART base pointer. + * @param enable Enable/Disable Automatic Address Detect mode. + * - true: Enable Automatic Address Detect mode. + * - false: Disable Automatic Address Detect mode. + */ +void UART_SetSlaveAddressDetectCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the slave address char + * that the receiver tries to detect. + * + * @param base UART base pointer. + * @param slaveAddress The slave to detect. + */ +static inline void UART_SetSlaveAddress(UART_Type* base, uint8_t slaveAddress) +{ + UART_UMCR_REG(base) = (UART_UMCR_REG(base) & ~UART_UMCR_SLADDR_MASK) | \ + UART_UMCR_SLADDR(slaveAddress); +} + +/*@}*/ + +/*! + * @name IrDA control functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * IrDA Mode. + * + * @param base UART base pointer. + * @param enable Enable/Disable IrDA mode. + * - true: Enable IrDA mode. + * - false: Disable IrDA mode. + */ +void UART_SetIrDACmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the clock for the IR pulsed + * vote logic. The available clock can be select from + * @ref _uart_irda_vote_clock enumeration. + * + * @param base UART base pointer. + * @param voteClock The available IrDA vote clock selection. + */ +void UART_SetIrDAVoteClock(UART_Type* base, uint32_t voteClock); + +/*@}*/ + +/*! + * @name Misc. functions. + * @{ + */ + +/*! + * @brief This function is used to set the enable condition of + * Automatic Baud Rate Detection feature. + * + * @param base UART base pointer. + * @param enable Enable/Disable Automatic Baud Rate Detection feature. + * - true: Enable Automatic Baud Rate Detection feature. + * - false: Disable Automatic Baud Rate Detection feature. + */ +void UART_SetAutoBaudRateCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to read the current value of Baud Rate + * Count Register value. this counter is used by Auto Baud Rate + * Detect feature. + * + * @param base UART base pointer. + * @return Current Baud Rate Count Register value. + */ +static inline uint16_t UART_ReadBaudRateCount(UART_Type* base) +{ + return (uint16_t)(UART_UBRC_REG(base) & UART_UBRC_BCNT_MASK); +} + +/*! + * @brief This function is used to send BREAK character.It is + * important that SNDBRK is asserted high for a sufficient + * period of time to generate a valid BREAK. + * + * @param base UART base pointer. + * @param active Asserted high to generate BREAK. + * - true: Generate BREAK character. + * - false: Stop generate BREAK character. + */ +void UART_SendBreakChar(UART_Type* base, bool active); + +/*! + * @brief This function is used to Enable/Disable the Escape + * Sequence Decection feature. + * + * @param base UART base pointer. + * @param enable Enable/Disable Escape Sequence Decection. + * - true: Enable Escape Sequence Decection. + * - false: Disable Escape Sequence Decection. + */ +void UART_SetEscapeDecectCmd(UART_Type* base, bool enable); + +/*! + * @brief This function is used to set the enable condition of + * Escape Sequence Detection feature. + * + * @param base UART base pointer. + * @param escapeChar The Escape Character to detect. + */ +static inline void UART_SetEscapeChar(UART_Type* base, uint8_t escapeChar) +{ + UART_UESC_REG(base) = (UART_UESC_REG(base) & ~UART_UESC_ESC_CHAR_MASK) | \ + UART_UESC_ESC_CHAR(escapeChar); +} + +/*! + * @brief This function is used to set the maximum time interval (in ms) + * allowed between escape characters. + * + * @param base UART base pointer. + * @param timerInterval Maximum time interval allowed between escape characters. + */ +static inline void UART_SetEscapeTimerInterval(UART_Type* base, uint16_t timerInterval) +{ + assert(timerInterval <= 0xFFF); + UART_UTIM_REG(base) = (UART_UTIM_REG(base) & ~UART_UTIM_TIM_MASK) | \ + UART_UTIM_TIM(timerInterval); +} + +/*@}*/ + +#ifdef __cplusplus +} +#endif + +/*! @}*/ + +#endif /* __UART_IMX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/wdog_imx/wdog_imx.c b/drivers/wdog_imx/wdog_imx.c new file mode 100644 index 000000000..c8c62d214 --- /dev/null +++ b/drivers/wdog_imx/wdog_imx.c @@ -0,0 +1,81 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#include "wdog_imx.h" + +/******************************************************************************* + * Code + ******************************************************************************/ + +/*FUNCTION********************************************************************** + * + * Function Name : WDOG_Enable + * Description : Configure WDOG funtions, call once only + * + *END**************************************************************************/ +void WDOG_Enable(WDOG_Type *base, uint8_t timeout) +{ + uint16_t wcr = base->WCR & (~WDOG_WCR_WT_MASK); + base->WCR = wcr | WDOG_WCR_WT(timeout) | WDOG_WCR_WDE_MASK; +} + +/*FUNCTION********************************************************************** + * + * Function Name : WDOG_Reset + * Description : Assert WDOG reset signal + * + *END**************************************************************************/ +void WDOG_Reset(WDOG_Type *base, bool wda, bool srs) +{ + uint16_t wcr = base->WCR; + + if (wda) + wcr &= ~WDOG_WCR_WDA_MASK; + if (srs) + wcr &= ~WDOG_WCR_SRS_MASK; + + base->WCR = wcr; +} + +/*FUNCTION********************************************************************** + * + * Function Name : WDOG_Refresh + * Description : Refresh the WDOG to prevent timeout + * + *END**************************************************************************/ +void WDOG_Refresh(WDOG_Type *base) +{ + base->WSR = 0x5555; + base->WSR = 0xAAAA; +} + +/******************************************************************************* + * EOF + ******************************************************************************/ diff --git a/drivers/wdog_imx/wdog_imx.h b/drivers/wdog_imx/wdog_imx.h new file mode 100644 index 000000000..8b053df10 --- /dev/null +++ b/drivers/wdog_imx/wdog_imx.h @@ -0,0 +1,193 @@ +/* + * Copyright (c) 2015, Freescale Semiconductor, Inc. + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * + * o Redistributions of source code must retain the above copyright notice, this list + * of conditions and the following disclaimer. + * + * o Redistributions in binary form must reproduce the above copyright notice, this + * list of conditions and the following disclaimer in the documentation and/or + * other materials provided with the distribution. + * + * o Neither the name of Freescale Semiconductor, Inc. nor the names of its + * contributors may be used to endorse or promote products derived from this + * software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND + * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED + * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR + * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; + * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __WDOG_IMX_H__ +#define __WDOG_IMX_H__ + +#include +#include +#include +#include "device_imx.h" + +/*! + * @addtogroup wdog_imx_driver + * @{ + */ + +/******************************************************************************* + * Definitions + ******************************************************************************/ +/*! @brief The reset source of latest reset. */ +enum _wdog_reset_source +{ + wdogResetSourcePor = WDOG_WRSR_POR_MASK, /*!< Indicates the reset is the result of a power on reset.*/ + wdogResetSourceTimeout = WDOG_WRSR_TOUT_MASK, /*!< Indicates the reset is the result of a WDOG timeout.*/ + wdogResetSourceSwRst = WDOG_WRSR_SFTW_MASK, /*!< Indicates the reset is the result of a software reset.*/ +}; + +/*! @brief Structure to configure the running mode. */ +typedef struct _wdog_init_config +{ + bool wdw; /*!< true: suspend in low power wait, false: not suspend */ + bool wdt; /*!< true: assert WDOG_B when timeout, false: not assert WDOG_B */ + bool wdbg; /*!< true: suspend in debug mode, false: not suspend */ + bool wdzst; /*!< true: suspend in doze and stop mode, false: not suspend */ +} wdog_init_config_t; + +/******************************************************************************* + * API + ******************************************************************************/ + +#if defined(__cplusplus) +extern "C" { +#endif + +/*! + * @name WDOG State Control + * @{ + */ + +/*! + * @brief Configure WDOG functions, call once only + * + * @param base WDOG base pointer. + * @param initConfig WDOG mode configuration + */ +static inline void WDOG_Init(WDOG_Type *base, const wdog_init_config_t *initConfig) +{ + base->WCR |= (initConfig->wdw ? WDOG_WCR_WDW_MASK : 0) | + (initConfig->wdt ? WDOG_WCR_WDT_MASK : 0) | + (initConfig->wdbg ? WDOG_WCR_WDBG_MASK : 0) | + (initConfig->wdzst ? WDOG_WCR_WDZST_MASK : 0); +} + +/*! + * @brief Enable WDOG with timeout, call once only + * + * @param base WDOG base pointer. + * @param timeout WDOG timeout ((n+1)/2 second) + */ +void WDOG_Enable(WDOG_Type *base, uint8_t timeout); + +/*! + * @brief Assert WDOG software reset signal + * + * @param base WDOG base pointer. + * @param wda WDOG reset. + * - true: Assert WDOG_B. + * - false: No impact on WDOG_B. + * @param srs System reset. + * - true: Assert system reset WDOG_RESET_B_DEB. + * - false: No impact on system reset. + */ +void WDOG_Reset(WDOG_Type *base, bool wda, bool srs); + +/*! + * @brief Get the latest reset source generated due to + * WatchDog Timer. + * + * @param base WDOG base pointer. + * @return The latest reset source (see @ref _wdog_reset_source enumeration). + */ +static inline uint32_t WDOG_GetResetSource(WDOG_Type *base) +{ + return base->WRSR; +} + +/*! + * @brief Refresh the WDOG to prevent timeout + * + * @param base WDOG base pointer. + */ +void WDOG_Refresh(WDOG_Type *base); + +/*! + * @brief Disable WDOG power down counter + * + * @param base WDOG base pointer. + */ +static inline void WDOG_DisablePowerdown(WDOG_Type *base) +{ + base->WMCR &= ~WDOG_WMCR_PDE_MASK; +} + +/*@}*/ + +/*! + * @name WDOG Interrupt Control + * @{ + */ + +/*! + * @brief Enable WDOG interrupt + * + * @param base WDOG base pointer. + * @param time how long before the timeout must the interrupt occur (n/2 seconds). + */ +static inline void WDOG_EnableInt(WDOG_Type *base, uint8_t time) +{ + base->WICR = WDOG_WICR_WIE_MASK | WDOG_WICR_WICT(time); +} + +/*! + * @brief Check whether WDOG interrupt is pending + * + * @param base WDOG base pointer. + * @return WDOG interrupt status. + * - true: Pending. + * - false: Not pending. + */ +static inline bool WDOG_IsIntPending(WDOG_Type *base) +{ + return (bool)(base->WICR & WDOG_WICR_WTIS_MASK); +} + +/*! + * @brief Clear WDOG interrupt status + * + * @param base WDOG base pointer. + */ +static inline void WDOG_ClearStatusFlag(WDOG_Type *base) +{ + base->WICR |= WDOG_WICR_WTIS_MASK; +} + +/*@}*/ + +#if defined(__cplusplus) +} +#endif + +/*! @}*/ + +#endif /* __WDOG_IMX_H__ */ +/******************************************************************************* + * EOF + ******************************************************************************/ From 58f866027b4534c13a9b2e1ad38ac0cf054b795b Mon Sep 17 00:00:00 2001 From: Susan Su Date: Sun, 30 Jan 2022 22:15:17 +0800 Subject: [PATCH 2/2] Update device_imx.h file to only include content for related device Signed-off-by: Susan Su --- devices/MCIMX6X/device_imx.h | 8 -------- devices/MCIMX7D/device_imx.h | 9 +-------- 2 files changed, 1 insertion(+), 16 deletions(-) diff --git a/devices/MCIMX6X/device_imx.h b/devices/MCIMX6X/device_imx.h index 00f1e8b15..641b97171 100644 --- a/devices/MCIMX6X/device_imx.h +++ b/devices/MCIMX6X/device_imx.h @@ -55,14 +55,6 @@ #define RDC_SEMAPHORE_MASTER_SELF (5) #define SEMA4_PROCESSOR_SELF (1) -#elif defined(CONFIG_SOC_MCIMX7_M4) - - /* CMSIS-style register definitions */ - #include "MCIMX7D_M4.h" - - #define RDC_SEMAPHORE_MASTER_SELF (6) - #define SEMA4_PROCESSOR_SELF (1) - #else #error "No valid CPU defined!" #endif diff --git a/devices/MCIMX7D/device_imx.h b/devices/MCIMX7D/device_imx.h index 00f1e8b15..8038bb64c 100644 --- a/devices/MCIMX7D/device_imx.h +++ b/devices/MCIMX7D/device_imx.h @@ -48,14 +48,7 @@ * * The CPU macro should be declared in the project or makefile. */ -#if defined(CONFIG_SOC_MCIMX6X_M4) - - /* CMSIS-style register definitions */ - #include "MCIMX6X_M4.h" - #define RDC_SEMAPHORE_MASTER_SELF (5) - #define SEMA4_PROCESSOR_SELF (1) - -#elif defined(CONFIG_SOC_MCIMX7_M4) +#if defined(CONFIG_SOC_MCIMX7_M4) /* CMSIS-style register definitions */ #include "MCIMX7D_M4.h"