diff --git a/bin/clonetb b/bin/clonetb index 525c5e7bfa..63157fc7ea 100755 --- a/bin/clonetb +++ b/bin/clonetb @@ -39,8 +39,9 @@ usage() { echo "usage: $0 [-x] [--clone] [--ignore] [--unignore]" - echo " -x clone cv32e40x subtree" - echo " --clone clone subtree based on env vars" + echo " -x clone cv32e40x subtree, known stable hash" + echo " --x-main clone cv32e40x subtree, latest main branch" + echo " --clone clone a subtree based on env vars" echo " --ignore tell git to ignore the cloned subtree" echo " --unignore tell git to not ignore the cloned subtree" @@ -80,7 +81,17 @@ clone() { clone_cv32e40x() { CV_CORE=cv32e40x VERIF_ENV_REPO=https://github.com/openhwgroup/cv32e40x-dv.git - VERIF_ENV_REF=e7bae19ebc7806021f909d49484c66d302b2f8a8 + VERIF_ENV_REF=be17b8902002f91803abde4bfb8caa91088575e1 + clone + + ignore_cloned_directory +} + +clone_cv32e40x_main() { + CV_CORE=cv32e40x + VERIF_ENV_REPO=https://github.com/openhwgroup/cv32e40x-dv.git + VERIF_ENV_REF=main + clone ignore_cloned_directory @@ -114,6 +125,9 @@ main() { "-x") clone_cv32e40x ;; + "--x-main") + clone_cv32e40x_main + ;; "--clone") clone ;; diff --git a/bin/csv2json b/bin/csv2json index b218fa80b3..883ec5fdce 100755 --- a/bin/csv2json +++ b/bin/csv2json @@ -57,11 +57,16 @@ csv_reader = csv.DictReader(csv_file) csv_rows = [] csv_row_previous = None +def should_fill_cell(cell_value, previous_row, row_key): + cell_is_empty = not cell_value + previous_row_exists = previous_row + column_should_repeat = row_key in ['Feature', 'Verification Goal'] + return cell_is_empty and previous_row_exists and column_should_repeat + for row in csv_reader: for key, value in row.items(): - if not value and csv_row_previous: + if should_fill_cell(value, csv_row_previous, key): row[key] = csv_row_previous[key] - # TODO not for "link-to-cov" etc csv_rows.append(row) csv_row_previous = row diff --git a/bin/merge.sh b/bin/merge.sh index 7b13e19e4a..fb132049eb 100755 --- a/bin/merge.sh +++ b/bin/merge.sh @@ -33,8 +33,10 @@ usage() { echo "--x-dv_into_s Do a merge of cv32e40x-dv main into core-v-verif cv32e40s/dev cv32e40s (not yet developed)" echo "--sdev_into_xdev Do a merge of core-v-verif cv32e40s/dev into core-v-verif cv32e40x/dev" echo "--xdev_into_sdev Do a merge of core-v-verif cv32e40x/dev into core-v-verif cv32e40s/dev" + echo "--rejection-diff Merge s/dev to x-dv, using 'theirs'" exit 1 + } @@ -64,12 +66,12 @@ merge_cv32e40s_into_cv32e40x-dv () { move_files_40s_into_40x () { - echo "=== Exchange 40x/X with 40s/S in file names ===" + echo "=== Replace 40s/S with 40x/X in file names ===" find . -type d | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | xargs -n1 dirname | awk '{gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 mkdir -p - find . -type d | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | awk '{printf $1; printf " "; gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 git mv + find . -type d | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | awk '{printf $1; printf " "; gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 git mv -f find . -type f | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | xargs -n1 dirname | awk '{gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 mkdir -p - find . -type f | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | awk '{printf $1; printf " "; gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 git mv + find . -type f | egrep -iv '\/\.|40sx|40xs' | grep -i 40s | awk '{printf $1; printf " "; gsub(/40s/, "40x"); gsub(/40S/, "40X"); print}' | xargs -n2 git mv -f } @@ -124,38 +126,53 @@ merge_xdev_into_sdev () { } -check_cv32e40x_repo() { +clone_x_dv() { + + echo "=== Cloning x-dv ===" - echo "=== Check if cv32e40x exist ===" - if [ ! -d "./cv32e40x/" ]; then - echo "Directory cv32e40x does not exists." - echo "Run: ./bin/clonetb -x" - echo "before running: ./bin/merge_script --s_into_x-dv" - exit 1 - fi - printf "OK\n\n" + read -p "This overwrites 'cv32e40x/'. Continue? y/n " yn + case $yn in + [Yy]* ) ;; + * ) echo "aborting"; exit;; + esac - echo "=== Check if cv32e40x is the core-v-verif repo ===" - if [ ! -d "./cv32e40x/.git/" ]; then - echo "Directory cv32e40x is a 'core-v-verif' repo and not a 'cv32e40x-dv' repo." - echo "Run: ./bin/clonetb -x" - echo "before running: ./bin/merge_script --s_into_x-dv" - exit 1 - fi - printf "OK\n\n" + ./bin/clonetb --x-main } check_merge_status() { + git status + +} + + +rejection_diff() { + + echo "=== Merging s/dev to x-dv, using 'theirs' ===" + echo "WARNING, this function is crude and makes assumptions." + + cd cv32e40x + branch_name_40s_subtree=$(git branch | grep ' cv32e40s') + branch_name_merge_normal=$(git branch | grep 'merge') + branch_name_merge_theirs=$(echo $branch_name_merge_normal | sed 's/merge/theirs/') + + git checkout main + git checkout -B $branch_name_merge_theirs + git merge -X theirs $branch_name_40s_subtree + + move_files_40s_into_40x + substitute_file_content_40s_into_40x + } main() { + case $1 in "--s_into_x-dv") - check_cv32e40x_repo + clone_x_dv merge_cv32e40s_into_cv32e40x-dv move_files_40s_into_40x substitute_file_content_40s_into_40x @@ -172,11 +189,14 @@ main() { merge_xdev_into_sdev check_merge_status ;; + "--rejection-diff") + rejection_diff + ;; *) usage ;; esac + } main "$@" - diff --git a/cv32e40s/bsp/bsp.h b/cv32e40s/bsp/bsp.h new file mode 100644 index 0000000000..b257d6ce85 --- /dev/null +++ b/cv32e40s/bsp/bsp.h @@ -0,0 +1,165 @@ +// Copyright 2022 Silicon Laboratories Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you +// may not use this file except in compliance with the License, or, at your +// option, the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +enum { + EXC_CAUSE_INSTR_ACC_FAULT = 1, + EXC_CAUSE_ILLEGAL_INSTR = 2, + EXC_CAUSE_BREAKPOINT = 3, + EXC_CAUSE_LOAD_ACC_FAULT = 5, + EXC_CAUSE_STORE_ACC_FAULT = 7, + EXC_CAUSE_ENV_CALL_U = 8, + EXC_CAUSE_ENV_CALL_M = 11, + EXC_CAUSE_INSTR_BUS_FAULT = 24, + EXC_CAUSE_INSTR_INTEGRITY_FAULT = 25, +}; + +typedef enum { + PMPMODE_OFF = 0, + PMPMODE_TOR = 1, + PMPMODE_NA4 = 2, + PMPMODE_NAPOT = 3 +} pmp_mode_t; + +// Verbosity levels (Akin to the uvm verbosity concept) +typedef enum { + V_OFF = 0, + V_LOW = 1, + V_MEDIUM = 2, + V_HIGH = 3, + V_DEBUG = 4 +} verbosity_t; + +// Matches funct3 values for CSR instructions +typedef enum { + CSRRW = 1, + CSRRS = 2, + CSRRC = 3, + CSRRWI = 5, + CSRRSI = 6, + CSRRCI = 7 +} csr_instr_access_t; + +typedef union { + struct { + volatile uint32_t opcode : 7; + volatile uint32_t rd : 5; + volatile uint32_t funct3 : 3; + volatile uint32_t rs1_uimm : 5; + volatile uint32_t csr : 12; + } volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) csr_instr_t; + +typedef union { + struct { + volatile uint32_t load : 1; + volatile uint32_t store : 1; + volatile uint32_t execute : 1; + volatile uint32_t u : 1; + volatile uint32_t s : 1; + volatile uint32_t res_5_5 : 1; + volatile uint32_t m : 1; + volatile uint32_t match : 4; + volatile uint32_t chain : 1; + volatile uint32_t action : 4; + volatile uint32_t size : 4; + volatile uint32_t timing : 1; + volatile uint32_t select : 1; + volatile uint32_t hit : 1; + volatile uint32_t vu : 1; + volatile uint32_t vs : 1; + volatile uint32_t res_26_25: 2; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) mcontrol6_t; + +typedef union { + struct { + volatile uint32_t uie : 1; // 0 + volatile uint32_t sie : 1; // 1 + volatile uint32_t wpri : 1; // 2 + volatile uint32_t mie : 1; // 3 + volatile uint32_t upie : 1; // 4 + volatile uint32_t spie : 1; // 5 + volatile uint32_t wpri0 : 1; // 6 + volatile uint32_t mpie : 1; // 7 + volatile uint32_t spp : 1; // 8 + volatile uint32_t wpri1 : 2; // 10: 9 + volatile uint32_t mpp : 2; // 12:11 + volatile uint32_t fs : 2; // 14:13 + volatile uint32_t xs : 2; // 16:15 + volatile uint32_t mprv : 1; // 17 + volatile uint32_t sum : 1; // 18 + volatile uint32_t mxr : 1; // 19 + volatile uint32_t tvm : 1; // 20 + volatile uint32_t tw : 1; // 21 + volatile uint32_t tsr : 1; // 22 + volatile uint32_t wpri3 : 8; // 30:23 + volatile uint32_t sd : 1; // 31 + } volatile fields; + volatile uint32_t raw; +} __attribute__((packed)) mstatus_t; + +typedef union { + struct { + volatile uint32_t mml : 1; + volatile uint32_t mmwp : 1; + volatile uint32_t rlb : 1; + volatile uint32_t reserved_31_3 : 29; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) mseccfg_t; + +typedef union { + struct { + volatile uint32_t reserved_1_0 : 2; + volatile uint32_t jvt_access : 1; + volatile uint32_t reserved_31_3 : 29; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) mstateen0_t; + +typedef union { + struct { + volatile uint32_t r : 1; + volatile uint32_t w : 1; + volatile uint32_t x : 1; + volatile uint32_t a : 1; + volatile uint32_t reserved_6_5 : 2; + volatile uint32_t l : 1; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 8; +} __attribute__((packed)) pmpsubcfg_t; + +typedef union { + struct { + volatile uint32_t cfg : 8; + } __attribute__((packed)) volatile reg_idx[4]; + volatile uint32_t raw : 32; +} __attribute__((packed)) pmpcfg_t; + +typedef union { + struct { + volatile uint32_t mode : 6; + volatile uint32_t base : 26; + } __attribute__((packed)) volatile fields; + volatile uint32_t raw : 32; +} __attribute__((packed)) jvt_t; diff --git a/cv32e40s/bsp/corev_uvmt.h b/cv32e40s/bsp/corev_uvmt.h index 30e460bb5a..d7022b3ca7 100644 --- a/cv32e40s/bsp/corev_uvmt.h +++ b/cv32e40s/bsp/corev_uvmt.h @@ -62,12 +62,13 @@ #define CV_VP_OBI_SLV_RESP_D_EXOKAY_ADDR_MAX ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*4)) #define CV_VP_OBI_SLV_RESP_D_EXOKAY_VALID ((volatile uint32_t*) (CV_VP_OBI_SLV_RESP_BASE + 6*4 + 4*5)) -// Bitfields for Debug Control VP register +// API for Debug Control VP register #define CV_VP_DEBUG_CONTROL_DBG_REQ(i) ((i) << 31) #define CV_VP_DEBUG_CONTROL_REQ_MODE(i) ((i) << 30) #define CV_VP_DEBUG_CONTROL_RAND_PULSE_DURATION(i) ((i) << 29) #define CV_VP_DEBUG_CONTROL_PULSE_DURATION(i) ((i) << 16) #define CV_VP_DEBUG_CONTROL_RAND_START_DELAY(i) ((i) << 15) #define CV_VP_DEBUG_CONTROL_START_DELAY(i) ((i) << 0) +#define CV_VP_DEBUG_CONTROL *((volatile uint32_t * volatile) (CV_VP_DEBUG_CONTROL_BASE)) #endif diff --git a/cv32e40s/bsp/handlers.S b/cv32e40s/bsp/handlers.S index f3f1dc89ad..6a0891542d 100644 --- a/cv32e40s/bsp/handlers.S +++ b/cv32e40s/bsp/handlers.S @@ -21,6 +21,7 @@ #define EXCEPTION_LOAD_ACCESS_FAULT 5 #define EXCEPTION_STORE_ACCESS_FAULT 7 #define EXCEPTION_ECALL_M 11 +#define EXCEPTION_ECALL_U 8 #define EXCEPTION_INSN_BUS_FAULT 24 /* NMI interrupt codes */ @@ -77,6 +78,8 @@ .weak handle_illegal_insn .weak handle_insn_access_fault .weak handle_insn_bus_fault +.weak handle_ecall +.weak handle_ecall_u /* exception handling */ __no_irq_handler: @@ -181,6 +184,8 @@ u_sw_irq_handler: beq t0, t1, handle_illegal_insn li t1, EXCEPTION_ECALL_M beq t0, t1, handle_ecall + li t1, EXCEPTION_ECALL_U + beq t0, t1, handle_ecall_u li t1, EXCEPTION_BREAKPOINT beq t0, t1, handle_ebreak li t1, EXCEPTION_INSN_BUS_FAULT @@ -191,6 +196,10 @@ handle_ecall: jal ra, handle_syscall j end_handler_incr_mepc +handle_ecall_u: + jal ra, handle_syscall + j end_handler_incr_mepc + handle_ebreak: /* TODO support debug handling requirements. */ la a0, ebreak_msg diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv index ef83342517..5bb219791d 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv +++ b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.csv @@ -1,6 +1,6 @@ Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Zc 1.0.1 ace0ee,Zca,c.f*,floating point load stores shall decode as illegal,"Verify that all variations of these instructions decode as illegal -Cross check with instructions used in Zcmp/t",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Cross check with instructions used in Zcmp/t",Check against ISS,Constrained-Random,Functional Coverage,"TODO: Should be checked, probably in an illegal instruction test.",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.*,"The remaining instructions in the C extension shall be verified, follow existing C extension verification plan",Verified in C extension ,N/A,N/A,N/A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,"Zcb @@ -9,122 +9,139 @@ Note: For instructions with an uncompressed equivalent, check with design which All possible rs1 registers are used. All possible rd registers are used. -All possible register combinations where rs1 == rd are used",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible register combinations where rs1 == rd are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Testcase,"No direct coverage, but a lot of variation is output from the debug_test2",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.lhu,"Load unsigned halfword, 16-bit encoding","Register operands: All possible rs1 registers are used. All possible rd registers are used. -All possible register combinations where rs1 == rd are used",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible register combinations where rs1 == rd are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Testcase,"No direct coverage, but some coverage can be found in corev_rand_instr_test",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.lh,"Load signed halfword, 16-bit encoding","Register operands: All possible rs1 registers are used. All possible rd registers are used. -All possible register combinations where rs1 == rd are used",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible register combinations where rs1 == rd are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,"No direct coverage, but some coverage can be found in corev_rand_instr_test",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.sb,"Store byte, 16-bit encoding","Register operands: All possible rs1 registers are used. All possible rs2 registers are used. -All possible register combinations where rs1 == rs2 are used",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible register combinations where rs1 == rs2 are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,"No direct coverage, but some coverage can be found in corev_rand_instr_test",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.sh,"Store halfword, 16-bit encoding","Register operands: All possible rs1 registers are used. All possible rs2 registers are used. -All possible register combinations where rs1 == rs2 are used",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible register combinations where rs1 == rs2 are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of uimm,Check against ISS,Constrained-Random,Functional Coverage,"No direct coverage, but some coverage can be found in corev_rand_instr_test",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.zext.b,"Zero extend byte, 16-bit encoding","Register operands: -All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.sext.b,"Sign extend byte, 16-bit encoding","Register operands: -All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,Verify illegal if Zbb is not configured,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.zext.h,"Zero extend halfword, 16-bit encoding","Register operands: -All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,Verify illegal if Zbb is not configured,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.sext.h,"Sign extend halfword, 16-bit encoding","Register operands: -All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,Verify illegal if Zbb is not configured,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.not,"Bitwise not, 16-bit encoding","Register operands: -All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible rsd registers are used.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,c.mul,"Multiply, 16-bit encoding",M_EXT=M_NONE shall result in c.mul decoding as an illegal instruction,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Register operands: All possible rsd registers are used. All possible rs2 registers are used. -All possible register combinations where rsd == rs2 are used",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,Zcmp,cm.push,"Create stack frame: store ra and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify instruction with watchpoint triggers on data address ,Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +All possible register combinations where rsd == rs2 are used",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,Zcmp,cm.push,"Create stack frame: store ra and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Testcase,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify instruction with watchpoint triggers on data address ,Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction -Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_push,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. (the order might change) -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,cm.pop,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify instruction with watchpoint triggers on data address ,Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.pop,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify instruction with watchpoint triggers on data address ,Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction -Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_pop,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,cm.popret,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.popret,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction -Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_popret,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,cm.popretz,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.popretz,"Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.",Verify all possible variations of rlist,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all possible variations of spimm,Check against ISS,Constrained-Random,Functional Coverage,corev_rand_interrupt++,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction -Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_popretz,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,cm.mva01s,Move a0-a1 into two registers of s0-s7,"Verify all possible variatons of sreg1, sreg2. Note that sreg1 = sreg2 is illegal",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.mva01s,Move a0-a1 into two registers of s0-s7,"Verify all possible variatons of sreg1, sreg2. Note that sreg1 = sreg2 is illegal",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction -Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_mva01s,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,cm.mvsa01,Move two s0-s7 registers into a0-a1,"Verify all possible variatons of sreg1, sreg2.",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.mvsa01,Move two s0-s7 registers into a0-a1,"Verify all possible variatons of sreg1, sreg2.",Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,"Covered in directed test ""zc_test""",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction -Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Note: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_mvsa01,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,"Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS. Note: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. -Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Coverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,"Zcmt @@ -133,15 +150,18 @@ Note: Deprioritize as this is furthest from ratification -",cm.jt,jump via table without link,Verify all possible variations of index,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,Verify all table jump-related fetches are checked by PMP/PMA. Specifically break/follow the rules for both systems,Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,cm.jalt,jump via table and link to ra,Verify all possible variations of index,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +",cm.jt,jump via table without link,Verify all possible variations of index,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,Verify all table jump-related fetches are checked by PMP/PMA. Specifically break/follow the rules for both systems,Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,cm.jalt,jump via table and link to ra,Verify all possible variations of index,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,"Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,JVT CSR,Table Jump base vector and control register,"csr stateen bit 2 controls user mode access, if bit is not set, cm.jt and cm.jalt should decode as illegal. -Access also controlled with smstateen, illegal if not enabled.",Check against ISS,Directed Non-Self-Checking,Testcase,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,JVT is used as base for jt/jalt,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, -,,,,JVT can be used to swap jump tables,Check against ISS,Directed Non-Self-Checking,Functional Coverage,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +Access also controlled with smstateen, illegal if not enabled.",Check against ISS,Directed Non-Self-Checking,Testcase,"Coverage hole, evaluate priority",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,JVT is used as base for jt/jalt,Check against ISS,Constrained-Random,Functional Coverage,"Imperas generated coverage, hierarchy path: +uvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]",,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, +,,,,JVT can be used to swap jump tables,Check against ISS,Constrained-Random,Code Coverage,N/A,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json new file mode 100644 index 0000000000..cb0c943680 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.json @@ -0,0 +1,1598 @@ +[ + { + "Requirement Location": "Zc 1.0.1 ace0ee", + "Feature": "Zca", + "Sub Feature": "c.f*", + "Feature Description": "floating point load stores shall decode as illegal", + "Verification Goal": "Verify that all variations of these instructions decode as illegal \nCross check with instructions used in Zcmp/t", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Should be checked, probably in an illegal instruction test.", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zca", + "Sub Feature": "c.*", + "Feature Description": "The remaining instructions in the C extension shall be verified, follow existing C extension verification plan", + "Verification Goal": "Verified in C extension ", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.lbu", + "Feature Description": "Load unsigned byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rd registers are used.\nAll possible register combinations where rs1 == rd are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Testcase", + "Link to Coverage": "No direct coverage, but a lot of variation is output from the debug_test2", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.lhu", + "Feature Description": "Load unsigned halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rd registers are used.\nAll possible register combinations where rs1 == rd are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Testcase", + "Link to Coverage": "No direct coverage, but some coverage can be found in corev_rand_instr_test", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.lh", + "Feature Description": "Load signed halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rd registers are used.\nAll possible register combinations where rs1 == rd are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "No direct coverage, but some coverage can be found in corev_rand_instr_test", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sb", + "Feature Description": "Store byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rs2 registers are used.\nAll possible register combinations where rs1 == rs2 are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "No direct coverage, but some coverage can be found in corev_rand_instr_test", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sh", + "Feature Description": "Store halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rs1 registers are used.\nAll possible rs2 registers are used.\nAll possible register combinations where rs1 == rs2 are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of uimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "No direct coverage, but some coverage can be found in corev_rand_instr_test", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.zext.b", + "Feature Description": "Zero extend byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sext.b", + "Feature Description": "Sign extend byte, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify illegal if Zbb is not configured", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.zext.h", + "Feature Description": "Zero extend halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify illegal if Zbb is not configured", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.sext.h", + "Feature Description": "Sign extend halfword, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify illegal if Zbb is not configured", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.not", + "Feature Description": "Bitwise not, 16-bit encoding", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "c.mul", + "Feature Description": "Multiply, 16-bit encoding", + "Verification Goal": "M_EXT=M_NONE shall result in c.mul decoding as an illegal instruction", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcb\n\n\nNote: For instructions with an uncompressed equivalent, check with design which are decoded to the 32b equivalent. For all others, consider a more thorough verification of the instruction, with regards to input values etc.", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Register operands:\n\nAll possible rsd registers are used.\nAll possible rs2 registers are used.\nAll possible register combinations where rsd == rs2 are used", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.push", + "Feature Description": "Create stack frame: store ra and 0 to 12 saved registers to the stack frame, optionally allocate additional stack space.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Testcase", + "Link to Coverage": "corev_rand_interrupt++", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify instruction with watchpoint triggers on data address ", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_push", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. (the order might change)\n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.pop", + "Feature Description": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "corev_rand_interrupt++", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify instruction with watchpoint triggers on data address ", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_pop", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.popret", + "Feature Description": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, return to ra.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "corev_rand_interrupt++", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_popret", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.popretz", + "Feature Description": "Destroy stack frame: load ra and 0 to 12 saved registers from the stack frame, deallocate the stack frame, move zero into a0, return to ra.", + "Verification Goal": "Verify all possible variations of rlist", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all possible variations of spimm", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "corev_rand_interrupt++", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_popretz", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.mva01s", + "Feature Description": "Move a0-a1 into two registers of s0-s7", + "Verification Goal": "Verify all possible variatons of sreg1, sreg2. Note that sreg1 = sreg2 is illegal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_mva01s", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "cm.mvsa01", + "Feature Description": "Move two s0-s7 registers into a0-a1", + "Verification Goal": "Verify all possible variatons of sreg1, sreg2.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in directed test \"zc_test\"", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, no following bus transaction: if a sub-operation triggers an exception, no further transaction shall arrive on the bus originating in the trapped instruction\n\nNote: this functionality is closely matched with items mentioned in other features of the 40s, such as PMP/PMA. Synchronize verification effort to avoid double work.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.u_zc_assert.a_multiop_exception_stop_dbus_mvsa01", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmp", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify exception behaviour, partially completed state shall match ISS: when a multi-operation instruction is stopped by an exception, state can have changed. Verify against ISS.\n\nNote: 40s implementation follows the example sequence in the Zc spec. ISS's should match this. \n\nCoverage note: cross between possible register lists and exception arriving between/at all sub-operations would be optimal", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "cm.jt", + "Feature Description": "jump via table without link", + "Verification Goal": "Verify all possible variations of index", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify all table jump-related fetches are checked by PMP/PMA. Specifically break/follow the rules for both systems", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "cm.jalt", + "Feature Description": "jump via table and link to ra", + "Verification Goal": "Verify all possible variations of index", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Imperas generated coverage, hierarchy path:\nuvmt_cv32e40s_tb.imperas_dv.idv_trace2cov.cov_1.obj_[instr]", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify interrupts(maskable and non-maskable), debug and single stepping can not stop execution after the instruction has started to change state. Make sure external interrupts happen at all stages of execution. Expect atomic execution", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.controller_i.controller_fsm_i.controller_fsm_sva.a_no_sequence_interrupt", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "JVT CSR", + "Feature Description": "Table Jump base vector and control register", + "Verification Goal": "csr stateen bit 2 controls user mode access, if bit is not set, cm.jt and cm.jalt should decode as illegal.\nAccess also controlled with smstateen, illegal if not enabled.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Coverage hole, evaluate priority", + "": "" + }, + { + "Requirement Location": "", + "Feature": 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+ }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": "", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + }, + { + "Requirement Location": " -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------", + "Feature": "Zcmt\n\n\n\nNote: Deprioritize as this is furthest from ratification\n\n\n\n", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "JVT can be used to swap jump tables", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx old mode 100755 new mode 100644 index 65429281a3..6ebd06788c Binary files a/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx and b/cv32e40s/docs/VerifPlans/Simulation/Zc/RV32Zc_Extension_Instructions.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv index 1618118c40..1b3d08821e 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv +++ b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.csv @@ -1,4 +1,4 @@ -Reference document,Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage,Review (Marton),Review (Robin),Review (Henrik),,,,,, +Reference document,Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage,Review (Marton),Review (Robin),Review (Henrik) "RISC-V ISM vol 1 (unpriv. ISA), 20191213 CV32E40P doc rev 46711ac","Section 2.8 @@ -13,14 +13,15 @@ Core switches into debug mode. Current PC must be saved to DPC Cause of debug must be saved to DCSR (cause=1) PC is updated to value on dm_haltaddr_i input -Core starts executing debug cod +Core starts executing debug code -Ensure exception routine is not enterred",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",?,Are Lee's corner cases handled in this vplan?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage," +Ensure exception routine is not enterred",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: mmode_ebreak_executes_debug_code",?,Are Lee's corner cases handled in this vplan?,? +,,,,,,Assertion Check,Other,Assertion Coverage," CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_with_ebreakm CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_with_ebreakm A :uvmt_cv32_tb.u_debug_assert.a_enter_debug -A: uvmt_cv32_tb.u_debug_assert.dcsr_cause",?,Is Mike's gh issue handled in this vplan?,?,,,,,, +A: uvmt_cv32_tb.u_debug_assert.dcsr_cause",?,Is Mike's gh issue handled in this vplan?,? "RISC-V ISM vol 1 (unpriv. ISA), 20191213 CV32E40P doc rev 46711ac","Section 2.8 @@ -37,11 +38,12 @@ PC of EBREAK instruction must be saved to DPC Cause of debug must be saved to DCSR (cause=1) PC is updated to value on dm_haltaddr_i input Core starts executing debug code -Ensure exception routine is not entered",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",?,Is the PMA overrule handled in this vplan?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"N/A: Hard to detect that we are executing an exception handler. +Ensure exception routine is not entered",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: exception_enters_debug_mode",?,Is the PMA overrule handled in this vplan?,? +,,,,,,Assertion Check,Other,Assertion Coverage,"N/A: Hard to detect that we are executing an exception handler. Covered in debug_test with ISS enabled. A: uvmt_cv32_tb.u_debug_assert.a_enter_debug -A: uvmt_cv32_tb.u_debug_assert.dcsr_cause",?,"Note: From OE about counters, ""vi burde også ha assert som sjekker at vi IKKE teller nå countinhibit, sleep, eller stopcount... de assertionene jeg har endre sjekker bare at de teller... vet du om vi har andre sjekker på dette?""",?,,,,,, +A: uvmt_cv32_tb.u_debug_assert.dcsr_cause",?,"Note: From OE about counters, ""vi burde også ha assert som sjekker at vi IKKE teller nå countinhibit, sleep, eller stopcount... de assertionene jeg har endre sjekker bare at de teller... vet du om vi har andre sjekker på dette?""",? "RISC-V ISM vol 1 (unpriv. ISA), 20191213 CV32E40P doc rev 46711ac","Section 2.8 @@ -52,12 +54,13 @@ Debug chapter",Enter ebreak exception,EBREAK instruction,"Enter ebreak exception 40S, same is true for ""dcsr.ebreaku"".","Add EBREAK or/and C.EBREAK to arbitrary code while ebreakm/u==0. Verify that: -Core does not switch to debug mode, but exception routine is entered as normal.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",?,?,"""[ebreakm=1?]""",,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage," +Core does not switch to debug mode, but exception routine is entered as normal.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: ebreak_behavior_m_mode",?,?,"""[ebreakm=1?]""" +,,,,,,Assertion Check,Other,Assertion Coverage," CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_regular_nodebug) CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_regular_nodebug) A: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception -A: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception",?,?,"""[ebreakm=1?]""",,,,,, +A: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception",?,?,"""[ebreakm=1?]""" "RISC-V ISM vol 1 (unpriv. ISA), 20191213 CV32E40P doc rev 46711ac","Section 2.8 @@ -73,13 +76,13 @@ DPC set to handler. Debug cause must be step (unless something else happened simultaneously). PC is updated to value on dm_haltaddr_i input Core starts executing debug code -Ensure exception routine is not entered",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_known_miscompares""",?,?,"""[ebreakm=1?]""",,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage," +Ensure exception routine is not entered",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_known_miscompares""",?,?,"""[ebreakm=1?]""" +,,,,,,Assertion Check,Other,Assertion Coverage," CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_step_nodebug) CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_step_nodebug) A: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception -A: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception",?,?,"""[ebreakm=1?]""",,,,,, +A: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception",?,?,"""[ebreakm=1?]""" CV32E40P doc rev 46711ac,Debug chapter,Enter DEBUG mode,External debug event,"Debug mode can be entered by asserting the external signal debug_req_i cause is set to = 3 (also see verification goal)","Assert debug_req_i while executing arbitrary code Verify that: @@ -87,13 +90,14 @@ Core switches into debug mode. Current PC must be saved to DPC Cause of debug must be saved to DCSR (cause=debugger(0x3)) PC is updated to value on dm_haltaddr_i input -Core starts executing debug code",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext +Core starts executing debug code",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: request_hw_debugger",,, +,,,,,,Assertion Check,Other,Assertion Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext A: uvmt_cv32_tb.u_debug_assert.a_enter_debug A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause A: uvmt_cv32_tb.u_debug_assert.a_debug_mode_pc A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_haltreq -A: uvmt_cv32_tb.u_debug_assert.a_debug_req_taken",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_debug_req_taken",,, "CV32E40P doc rev 46711ac RISCV-V External Debug Support Version 0.13.2","Debug chapter @@ -112,11 +116,11 @@ Verify that core enters debug mode on breakpoint addr Current PC is saved to DPC Cause of debug must be saved to DCSR (cause=2) PC is updated to value on dm_haltaddr_i input -Core starts executing debug code",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_trigger""",?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match +Core starts executing debug code",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_trigger""",?,?,? +,,,,,,Assertion Check,Other,Assertion Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger -A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",?,?,?,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug A:a_dt_instr_trigger_hit_*",?,?,? "CV32E40P doc rev 46711ac RISCV-V External Debug Support Version 0.13.2","Debug chapter @@ -127,177 +131,222 @@ Chapter 5",Trigger module,Trigger module match event,"When trigger module is dis Write (randomized) breakpoint addr to tdata2 and disable breakpoint in tdata1 Exit debug mode (dret instruction) Verify that core does not enter debug mode on breakpoint addr -",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_trigger""",,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: cg_trigger_match_disabled +",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_trigger""",,"Why is the ""Trigger module"" Feature in red text?", +,,,,,,Assertion Check,Other,Assertion Coverage,"CG: cg_trigger_match_disabled A: uvmt_cv32_tb.u_debug_assert.a_trigger_match_disabled -",,,,,,,,, +",,, 40S User Manual 0.8.0,Debug & Trigger,Trigger module,Number of triggers,"The number of triggers is determined by DBG_NUM_TRIGGERS. When num triggers is 0, accessing the trigger registers causes illegal instruction exception. Triggers never fire. -""tselect"" is 0.","Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. Check that no triggers ever fire. Check that ""tselect"" is 0.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,"""[40x? Also below.]""",,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, +""tselect"" is 0.","Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. Check that no triggers ever fire. Check that ""tselect"" is 0.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_0_trigger,?,?,"""[40x? Also below.]""" +,,,,,,Assertion Check,Other,Assertion Coverage,"A:a_dt_0_triggers_tdata1_access, a_dt_0_triggers_no_triggering",?,?,? ,,,,"The number of triggers is determined by DBG_NUM_TRIGGERS. DBG_NUM_TRIGGERS can be any value within 0-4. ""tselect"" is WARL (0x0 - (DBG_NUM_TRIGGERS-1)). -""tcontrol"" is WARL (0x0). All selectable triggers are functional. -All trigger registers are accessible except for ""mcontext"", ""mscontext"", ""hcontext"", and ""scontext"" (those four trap upon access).","For all number of triggers, use tselect to exercise each trigger with each supported type. (Also try writing to higher ""tselect"" than supported and check that a supported number is read back.) Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed.",Self Checking Test,Directed Self-Checking,Testcase,,"There are a lot of things to check in a single point here. Nothing is wrong with this point as I see it, so there is no need to change, but ideally this point should be split up.",?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -"40S User Manual - -Debug 1.0.0","Control and Status Registers - -Match Control Type 6",Trigger module,"""mcontrol6"" match types","The ""load"" and ""store"" bits are supported (so load/store addr matching is supported). -The ""execute"" bit is also supported. -The only supported match types are ""address match"" for {instr execution, load, store}, all using ""before"" timing so ""mcontrol6.timing"" is always 0. -Data matching is not supported (only addr matching), so ""mcontrol6.select"" is always 0.","Configure triggers for load/store/execute and combinations of them, configure tdata2, cause triggers to fire and check that debug mode is entered correctly. Also check that the tied fields are tied. All of these configurations must be crossed, also against match conditions.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -,,,"""mcontrol6"" match conditions","Supported match conditions in ""mcontrol6.match"" are {0 (eq), 2 (geq), 3 (less)}.","Configure triggers using all three match conditions, exercise them within and outside of the conditions, check that debug mode is/isn't entered. Must also cross against the ""match types"" item above.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, +All trigger registers are accessible except for ""mcontext"", ""mscontext"", ""hcontext"", and ""scontext"" (those four trap upon access).","For all number of triggers, use tselect to exercise each trigger with each supported type. (Also try writing to higher ""tselect"" than supported and check that a supported number is read back.) Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,"There are a lot of things to check in a single point here. Nothing is wrong with this point as I see it, so there is no need to change, but ideally this point should be split up.",?,? +,,,,,,Assertion Check,Other,Assertion Coverage,"A: a_dt_access_context, a_dt_tselect_higher_than_dbg_num_triggers, a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason. COV: c_trigger_i_has_type_mcontrol, c_trigger_i_has_type_etrigger, c_trigger_i_has_type_mcontrol6, c_trigger_i_has_type_disable",?,?,? +User Manual v0.9.0.,Control and Status Registers,Trigger module,tcontrol,"""tcontrol"" doesn't exist.","Check that attempts to access ""tcontrol"" raise an illegal instruction exception, always. (Unless overruled by a higher priority.)",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,,, +,,,,,,Assertion Check,Other,Assertion Coverage,A: a_dt_tcontrol_not_implemented,,, ,,,"""mcontrol6"" compare values"," Instr execute matching uses only one ""compare value"" (the PC itself). -Load/Store matching uses compare values depending on the size of the access {A, A+1, etc}.","Exercise address match triggers for instr/load/store with different sizes (16/32 for instr, 8/16/32 for loadstore). Check that instr match only happens on the exact address. Check that loadstore addr matching triggers on any byte.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -,,,"""mcontrol6"" enable","Triggers can be en/disabled in M-mode, ""mcontrol6.m"", default is 0. +Load/Store matching uses compare values depending on the size of the access {A, A+1, etc}.","Exercise address match triggers for instr/load/store with different sizes (16/32 for instr, 8/16/32 for loadstore). Check that instr match only happens on the exact address. Check that loadstore addr matching triggers on any byte.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,?,?,? +,,,,,,Assertion Check,Other,Assertion Coverage,"A: a_dt_enter_dbg_reason, a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*",?,?,? +"User Manual v0.9.0. + +Debug 1.0-STABLE fb7025",,,Mcontrol6Hit,"When a trigger fires, it's ""mcontrol6.hit"" field gets set to 1. +(This is also true when multiple triggers fire at once.)","Induce firing of a trigger. +Check that the corresponding ""hit"" field gets set. +Do the same for variations of multiple triggers firing at once. +Check that the field is WARL 0x0, 0x1.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,,, +,,,,,,Assertion Check,Other,Assertion Coverage,"A: a_dt_m6_hit_bit +a_dt_warl_tdata1_m6",,, +,,,Mcontrol6Match,"Supported match conditions in ""mcontrol6.match"" are {0 (eq), 2 (geq), 3 (less)}.","Configure triggers using all three match conditions, exercise them within and outside of the conditions, check that debug mode is/isn't entered. Must also cross against the ""match types"" item above.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,?,?,? +,,,,,,Assertion Check,Other,Assertion Coverage,"A: a_dt_enter_dbg_reason, a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*",?,?,? +,,,Mcontrol6UM,"Triggers can be en/disabled in M-mode, ""mcontrol6.m"", default is 0. 40S, triggers can be en/disabled in U-mode, ""mcontrol6.u"", default is 0. 40X, triggers cannot be enabled in U-mode, ""mcontrol6.u"", WARL (0x0). -The trigger action is always to enter D-mode, so ""mcontrol6.action"" is always 1.","Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -,,,"""mcontrol6"" atomics","40X, ""mcontrol6"" trigger behavior has specific descriptions for ""A"" extension.","40X, this section must be filled out when the time comes for planning atomics verification.",,,,,?,?,?,,,,,, +The trigger action is always to enter D-mode, so ""mcontrol6.action"" is always 1.","Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,?,?,? +,,,,,,Assertion Check,Other,Assertion Coverage,"A:a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_tie_offs_*",?,?,? +,,,Mcontrol6LoadStoreExecute,"The ""load"" and ""store"" bits are supported (so load/store addr matching is supported). +The ""execute"" bit is also supported. +The only supported match types are ""address match"" for {instr execution, load, store}, all using ""before"" timing. +Data matching is not supported (only addr matching), so ""mcontrol6.select"" is always 0.","Configure triggers for load/store/execute and combinations of them, configure tdata2, cause triggers to fire and check that debug mode is entered correctly. All of these configurations must be crossed, also against match conditions.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,?,"""tdata3"" and ""tcontrol"" should be removed.",? +,,,,,,Assertion Check,Other,Assertion Coverage,"A: a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*. ",?,?,? +User Manual v0.9.0.,,,trigger csrs,Some fields in the trigger csrs are hardwired.,Check that the tied fields are tied.,Assertion Check,Other,Assertion Coverage,"A: a_dt_tie_offs_tselect, a_dt_tie_offs_tdata1_mcontrol, a_dt_tie_offs_tdata1_etrigger, a_dt_tie_offs_tdata1_mcontrol6, a_dt_tie_offs_tdata1_disabled, a_dt_tie_offs_tdata2_etrigger. a_dt_tie_offs_tinfo.",,, +,,,"""mcontrol6"" atomics","40X, ""mcontrol6"" trigger behavior has specific descriptions for ""A"" extension.","40X, TODO this section must be filled out when the time comes for planning atomics verification.",,,,,?,?,? "40S User Manual Debug 1.0.0","Control and Status Registers -Trigger Data 1",Trigger module,"""tdata1.type""","The only supported types are ""2 = address match legacy"", ""5 = Exception trigger"", ""6 = Address match"", and ""15 = Disabled"".","Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is ""15"".",Self Checking Test,Directed Self-Checking,Testcase,,?,?,"""[type 2]""",,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,"""[type 2]""",,,,,, -,,,"""tdata1.dmode""","This bit is WARL (0x1), so only D-mode can write tdata registers. And this bit is still WARL (0x1) regardless of ""type"" (2, 5, 6, 15).","Try to write tdata registers outside of debug mode, check that it traps. Try changing ""tdata1.dmode"" and check that it is WARL (0x1). Cross the above checks with all supported types.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, +Trigger Data 1",Trigger module,"""tdata1.type""","The only supported types are ""2 = address match legacy"", ""5 = Exception trigger"", ""6 = Address match"", and ""15 = Disabled"".","Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is ""15"".",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,?,?,"""[type 2]""" +,,,,,,Assertion Check,Other,Assertion Coverage,A: a_dt_tdata1_types,?,?,"""[type 2]""" +,,,"""tdata1.dmode""","This bit is WARL (0x1), so only D-mode can write tdata registers. And this bit is still WARL (0x1) regardless of ""type"" (2, 5, 6, 15).","Try to write tdata registers outside of debug mode, check that they are not writable. Try changing ""tdata1.dmode"" and check that it is WARL (0x1). Cross the above checks with all supported types.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,?,?,? +,,,,,,Assertion Check,Other,Assertion Coverage,"A: a_dt_not_access_tdata1_dbg_mode, a_dt_not_access_tdata2_dbg_mode, a_dt_dmode",?,?,? "40S User Manual Debug 1.0.0","Control and Status Registers -Trigger Info",Trigger module,"""tinfo""","""tinfo.info"" holds the supported types {2, 5, 6, 15}, and the register is otherwise WARL (0x0).","When num triggers is 0, check that ""tinfo"" is 0. -For any other num triggers, check that ""tinfo.info"" is ""1"" for the three supported types, and that the remaining bits are 0.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,"""[type 2]""",,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,"""[type 2]""",,,,,, +Trigger Info",Trigger module,"""tinfo""","""tinfo.info"" holds the supported types {2, 5, 6, 15}, +""tinfo.version"" holds the ""Sdtrig"" spec version, +and the register is otherwise WARL (0x0)."," +When num triggers is more than 0, check that ""tinfo.info"" is ""1"" for the three supported types, +""tinfo.version"" is 0x1, +and that the remaining bits are 0.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,?,?,"""[type 2]""" +,,,,,,Assertion Check,Other,Assertion Coverage,A: a_dt_triggers_tinfo,?,?,"""[type 2]""" "40S User Manual Debug 1.0.0","Control and Status Registers -Exception Trigger",Trigger module,"""etrigger""","A trigger (""tdata1"") can be configured as an exception trigger (""etrigger""). Where ""tdata2"" configures the exceptions to fire upon.","Configure ""tdata1"" and ""tdata2"" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc).",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, +Exception Trigger",Trigger module,"""etrigger""","A trigger (""tdata1"") can be configured as an exception trigger (""etrigger""). Where ""tdata2"" configures the exceptions to fire upon.","Configure ""tdata1"" and ""tdata2"" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc).",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,?,?,? +,,,,,,Assertion Check,Other,Assertion Coverage,"A: a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_glitch_dt_exception_trigger_hit_*",?,?,? ,,,,"The bits {""hit"", ""vs"", ""vu"", ""s""} are not supported (WARL 0). ""nmi"" does not exist (mentioned because it briefly did). ""m"" is fully supported. 40S, ""u"" is fully supported. 40X, ""u"" is not supported (WARL0). -The triggers always enter D-mode, so ""etrigger.action"" is WARL 1.","Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -40s User Manual 0.8.0,Debug Chapter,debug_pc_o,,"Signal ""debug_pc_o"" is the PC of the last retired instruction The signal is only valid when ""debug_pc_valid_o"" is equal to 1",Verify that the signal can be matched with related rvfi signals,Assertion Check,Assertion Check,Assertion Coverage,"A: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o -A: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o_inv",,,,,,,,, +The triggers always enter D-mode, so ""etrigger.action"" is WARL 1.","Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields.",Self Checking Test,Directed Self-Checking,Testcase,DTC: debug_test_trigger,?,"""tdata3"" and ""tcontrol"" should be removed.",? +,,,,,,Assertion Check,Other,Assertion Coverage,"A: a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_warl_tselect, a_dt_warl_tdata1_general, a_dt_warl_tdata1_m2, a_dt_warl_tdata1_etrigger, a_dt_warl_tdata1_m6, a_dt_warl_tdata1_disabled, a_dt_warl_tdata2_etrigger, a_dt_warl_tinfo. ",?,?,? +40s User Manual 0.8.0,Debug Chapter,debug_pc_o,,"Signal ""debug_pc_o"" is the PC of the last retired instruction The signal is only valid when ""debug_pc_valid_o"" is equal to 1",Verify that the signal can be matched with related rvfi signals,Assertion Check,Other,Assertion Coverage,"A: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o +A: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o_inv",,, 40S User Manual 0.8.0,Debug chapter,Debug exception addr,,"If an exception occurs during debug mode, the PC should be set to the dm_exception_addr_i input without changing the status registers","Bring core into debug mode, generate all exception types and observe that the PC jumps to the address given by dm_exception_addr_i. Observe no change in status registers -According to specification, the core supports several types of exceptions: {instr access fault, illegal instruction, ... etc}",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""","Point mentions the exceptions supported by the e40p, need to match 40s/x capabilities and update text","""0.8.0""",,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_exception +According to specification, the core supports several types of exceptions: {instr access fault, illegal instruction, ... etc}",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: illegal_csr_in_dmode +tc: ecall_in_dmode +tc: mret_in_dmode +tc: single_step","Point mentions the exceptions supported by the e40p, need to match 40s/x capabilities and update text","""0.8.0""", +,,,,,,Assertion Check,Other,Assertion Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_exception CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ecall -A: uvmt_cv32_tb.u_debug_assert.a_debug_mode_exception",,,,,,,,, -40S User Manual 0.8.0,Debug chapter,Core debug registers,Illegal access,"Accessing the core debug registers - DCSR, DPC and DSCRATCH0/1 while NOT in debug mode causes an illegal instruction",Access all debug registers in M-mode and observe that illegal instruction exception is triggered.,Self Checking Test,Directed Non-Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_regs_m_mode -A: uvmt_cv32_tb.u_debug_assert.a_debug_regs_mmode",,,,,,,,, -Debug 1.0.0,Debug Control and Status,"""dcsr"" writability",,"All fields of ""dcsr"" (except some) are only writable by the external debugger. Exceptions are {""v"", ""prv"", ""cause"", ""nmip""}.","Keep track of whether an external debug request has happened, check that if there is a change in ""dcsr"" (except some) then there must have been an external debug request.",Assertion Check,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -40S User Manual 0.8.0,Debug chapter,Trigger module registers,Access from M-mode,"Accessing the trigger module registers - tselect, tdata1/2/3, tinfo, tcontrol are readable from M-mode, but not writeable. (And is not accessible at all from U-mode.)","Access all trigger module registers in M-mode and observe writes have no effects and reads should reflect register content. +A: uvmt_cv32_tb.u_debug_assert.a_debug_mode_exception",,, +40S User Manual 0.8.0,Debug chapter,Core debug registers,Illegal access,"Accessing the core debug registers - DCSR, DPC and DSCRATCH0/1 while NOT in debug mode causes an illegal instruction",Access all debug registers in M-mode and observe that illegal instruction exception is triggered.,Self Checking Test,Directed Non-Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: debug_csr_rw",,, +,,,,,,Assertion Check,Other,Assertion Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_regs_m_mode +A: uvmt_cv32_tb.u_debug_assert.a_debug_regs_mmode",,, +Debug 1.0.0,Debug Control and Status,"""dcsr"" writability",,"All fields of ""dcsr"" (except some) are only writable by the external debugger. Exceptions are {""v"", ""prv"", ""cause"", ""nmip""}.","Keep track of whether an external debug request has happened, check that if there is a change in ""dcsr"" (except some) then there must have been an external debug request.",Assertion Check,Constrained-Random,Functional Coverage,"TODO: might be covered by directed/random testing, no assert found",?,?,? +40S User Manual 0.8.0,Debug chapter,Trigger module registers,Access from M-mode,"Accessing the tdata1/2 registers are readable from M-mode, but not writeable. (And is not accessible at all from U-mode.)","Access all tdata registers in M-mode and observe writes have no effects and reads should reflect register content. Access registers from D-mode and observe full R/W access. -Access from U-mode and observe no access at all.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",Should we also check r/w in U-mode?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_regs -",?,?,?,,,,,, -Debug 1.0.0,Trigger Registers,Trigger module registers,"""tdata1"", writing zero","""it is guaranteed that writing 0 to tdata1 disables the trigger, and leaves it in a state where tdata2 and tdata3 can be written with any value that makes sense for any trigger type supported by this trigger."" - -More generally, ""When a selected trigger is disabled [type 15], tdata2 and tdata3 can be written with any value supported by any of the types this trigger supports"".","Write 0 to ""tdata1"", ensure that its state becomes disabled (type 15). Write values to ""tdata2"" (addresses and/or exception causes) and exercise would-have-been triggers and check that the trigger does not fire.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -,,,"""tdata2"" and ""tdata3""","""tdata2"" should always be RW (any), and ""tdata3"" is always WARL (0x0).","Change the type to 2/5/6/15 and write any data to ""tdata2"", read it back and check that it always gets set. Do the same for ""tdata3"" and check that it always reads back 0.",Self Checking Test,Directed Self-Checking,Testcase,,?,Type 2,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,Type 2,?,,,,,, -,,,Other tdata registers,"Writing one ""tdata*"" register must not modify other ""tdata*"" registers, and must not modify other triggers than the currently selected.","Read the state of all triggers, write to tdata1/2/3 (using all types in tdata1), read back the state of all triggers and check that nothing got changes except the one ""tdata*"" register that was written.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, +Access from U-mode and observe no access at all.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test"".",Should we also check r/w in U-mode?,"""tdata3"" should be removed.",? +,,,,,,Assertion Check,Other,Assertion Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_regs. A: a_dt_no_write_access_to_tdata_in_mmode, +a_dt_read_access_to_tdata1_in_mmode, +a_dt_read_access_to_tdata2_in_mmode, +a_dt_write_access_to_tdata1_in_dmode, +a_dt_write_access_to_tdata2_in_dmode, +a_dt_read_access_to_tdata1_in_dmode, +a_dt_read_access_to_tdata2_in_dmode, +a_dt_no_access_to_tdata_in_umode. +COV: c_dt_write_tdata1_in_mmode, +c_dt_write_tdata2_in_mmode. + +",?,?,? +Debug 1.0.0,Trigger Registers,Trigger module registers,"""tdata1"", writing zero","""it is guaranteed that writing 0 to tdata1 disables the trigger, and leaves it in a state where tdata2 can be written with any value that makes sense for any trigger type supported by this trigger."" + +More generally, ""When a selected trigger is disabled [type 15], tdata2 can be written with any value supported by any of the types this trigger supports"".","Write 0 to ""tdata1"", ensure that its state becomes disabled (type 15). Write values to ""tdata2"" (addresses and/or exception causes) and exercise would-have-been triggers and check that the trigger does not fire.",Assertion Check,Other,Assertion Coverage,"A: a_dt_write_0_to_tdata1, +a_dt_enter_dbg_reason",?,?,? +"Debug 1.0.0 +UserManual v0.9.0.",,,tdata2,"""tdata2"" should always be RW (any) for type 2/6/15.","Change the type to 2/6/15 and write any data to ""tdata2"", read it back and check that it always gets set.",Assertion Check,Other,Assertion Coverage,"A: a_dt_write_tdata2_random_in_dmode_type_2_6_15. COV: c_dt_w_csrrw_tdata2_m2_m6_disabled, +c_dt_w_csrrs_tdata2_m2_m6_disabled, +c_dt_w_csrrc_tdata2_m2_m6_disabled, +c_dt_w_csrrwi_tdata2_m2_m6_disabled, +c_dt_w_csrrsi_tdata2_m2_m6_disabled, +c_dt_w_csrrci_tdata2_m2_m6_disabled",?,"""tdata3"" should be removed.",? +User Manual v0.9.0.,,,tdata3,"""tdata3"" doesn't exist.","Check that attempts to access ""tdata3"" raise an illegal instruction exception, always. (Unless overruled by a higher priority.)",Assertion Check,Other,Assertion Coverage,A: a_dt_tdata3_not_implemented.,,, +Debug 1.0.0,,,Other tdata registers,"Writing one ""tdata*"" register must not modify other ""tdata*"" registers, and must not modify other triggers than the currently selected.","Read the state of all triggers, write to tdata1/2 (using all types in tdata1), read back the state of all triggers and check that nothing got changes except the one ""tdata*"" register that was written.",Assertion Check,Other,Assertion Coverage,"A: a_dt_write_only_tdata1, +a_dt_write_only_tdata2.",?,"""tdata3"" should be removed.",? RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt2,Program Buffer,Interrupts,"While in debug mode and executing from the program buffer, all interrupts are masked.","Enable interrupts (setting mstatus.mie field and mie register). Bring core into debug mode and start executing from program buffer. -Generate interrupts while in debug mode and ensure they are masked.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_in_debug -A: uvmt_cv32_tb.u_debug_assert.a_irq_in_debug",,,,,,,,, -RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt3,Program Buffer,Exceptions,"While in debug mode and executing from the program buffer, exceptions don’t update any registers but they DO end execution of PB (TBD: goes back to M-mode or restarts in debug(?)) [PZ] this is redundnant with dm_exception_addr_i (on line 10 & 11)","Bring core into debug mode and start executing from program buffer. Make sure PB includes code that will hit an exception. Make sure core doesn’t update any registers, and jumps out of debug mode into M-mode",Self Checking Test,,,N/A,,,,,,,,, -,,,,,,Check against ISS,,,N/A,,,,,,,,, -RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt4,Program Buffer,Triggers,"While in debug mode and executing from the program buffer, no action is taken on any trigger match.","Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). Continue execution in debug, and observe that no action is taken when the trigger matches.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match_disabled (d_match_with_en),,,,,,,,, -Debug 1.0.0,dcsr,Counters,,"Spec:Counters may be stopped, depending on stopcount in dscr","""dcsr.stopcount"" is WARL and we must test the counter bevaior for both values of stopcount.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",?,"Is wrong, need update.",?,,,,,, +Generate interrupts while in debug mode and ensure they are masked.",Assertion Check,Other,Assertion Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_in_debug +A: uvmt_cv32_tb.u_debug_assert.a_irq_in_debug",,, +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt3,Program Buffer,Exceptions,"While in debug mode and executing from the program buffer, exceptions don’t update any registers but they DO end execution of PB (TBD: goes back to M-mode or restarts in debug(?)) [PZ] this is redundnant with dm_exception_addr_i (on line 10 & 11)","Bring core into debug mode and start executing from program buffer. Make sure PB includes code that will hit an exception. Make sure core doesn’t update any registers, and jumps out of debug mode into M-mode",Self Checking Test,,,N/A,,, +,,,,,,Check against ISS,,,N/A,,, +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt4,Program Buffer,Triggers,"While in debug mode and executing from the program buffer, no action is taken on any trigger match.","Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). Continue execution in debug, and observe that no action is taken when the trigger matches.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test"". ",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match_disabled (d_match_with_en) A:a_dt_no_actions_on_trigger_matches_in_debug_dcsr +a_dt_no_actions_on_trigger_matches_in_debug_dpc",,, +Debug 1.0.0,dcsr,Counters,,"Spec:Counters may be stopped, depending on stopcount in dscr","""dcsr.stopcount"" is WARL and we must test the counter bevaior for both values of stopcount.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: test_stopcnt_bits",?,"Is wrong, need update.",? ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_counters_enabled A: uvmt_cv32_tb.u_debug_assert.a_minstret_count -A: uvmt_cv32_tb.u_debug_assert.a_mcycle_count",?,"Any other ""40p"" outdateds here? Marked them all.",?,,,,,, -RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt6,Program Buffer,Timers,"Timers may be stopped, depending on stoptime in dcsr","(See ""Counters"" above.)",,,,N/A,,"Fix ""40p""",,,,,,, -RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt7,Program Buffer,WFI instruction,"In debug, the WFI instruction acts as a NOP instruction","Bring core into debug mode. Ensure that an WFI instruction will be executed from the program buffer. Ensure that the WFI will act as a nop, not waiting for an interrupt to occur.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_mcycle_count",?,"Any other ""40p"" outdateds here? Marked them all.",? +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt6,Program Buffer,Timers,"Timers may be stopped, depending on stoptime in dcsr","(See ""Counters"" above.)",,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt7,Program Buffer,WFI instruction,"In debug, the WFI instruction acts as a NOP instruction","Bring core into debug mode. Ensure that an WFI instruction will be executed from the program buffer. Ensure that the WFI will act as a nop, not waiting for an interrupt to occur.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_in_debug -A: uvmt_cv32_tb.u_debug_assert.a_wfi_in_debug",,,,,,,,, -RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt8,Program Buffer,Priv. lvl changes,An ebreak instruction during debug shall result in relaunching the debugger entry code by setting the PC to the halt_addr_i and will not change any CSR in doing this.,"Bring hart into debug mode and start executing from the Program Buffer. Make sure the PB code includes an ebreak instruction. When the ebreak is executed, the hart must halt and not update dpc or dcsr. Ensure relaunch of debugger entry",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_wfi_in_debug",,, +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt8,Program Buffer,Priv. lvl changes,An ebreak instruction during debug shall result in relaunching the debugger entry code by setting the PC to the halt_addr_i and will not change any CSR in doing this.,"Bring hart into debug mode and start executing from the Program Buffer. Make sure the PB code includes an ebreak instruction. When the ebreak is executed, the hart must halt and not update dpc or dcsr. Ensure relaunch of debugger entry",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: request_ebreak_3x",,, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_with_ebreakm (.ebreak_in_debug) CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_with_ebreakm (.ebreak_in_debug) -A: uvmt_cv32_tb.u_debug_assert.a_ebreak_during_debug_mode",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_ebreak_during_debug_mode",,, RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt9,Program Buffer,Fence instructions,Completing program buffer execution is considered output for the purpose of the fence instruction.,"TBD - need to understand the fence instruction in cv32e40s. Is ""completing program buffer execution"" the same as executing dret? [PZ] waiting for more clarity from RISCV Foundation debug task group (see https://lists.riscv.org/g/tech-debug/topic/clarification_request/75725318?p=,,,20,0,0,0::recentpostdate%2Fsticky,,,20,2,0,75725318 ) -Nothing to do. That sentence was retracted here https://github.com/riscv/riscv-debug-spec/pull/601/files . Now it seems they just recommend debug software to do a fence when completing abstract commands.",,,,N/A,What are we doing here?,Added N/A disclaimer. Striking it.,,,,,,, -RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt10,Program Buffer,Ctrl. Transfer instr.,"All control transfer instructions may act as illegal instructions if destination is within program buffer. If one does, all must.",N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior,,,,N/A,,"Fix ""40p""",,,,,,, -RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt11,Program Buffer,Ctrl. Transfer instr.,"All control transfer instructions may as illegal instructions if destination is outside the program buffer. If one does, all must.",N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior,,,,N/A,,"Fix ""40p""",,,,,,, -RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt12,Program Buffer,Instr. Dependent of PC,Instructions that depend on the PC may act as illegal instructions,N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior,,,,N/A,,"Fix ""40p""",,,,,,, +Nothing to do. That sentence was retracted here https://github.com/riscv/riscv-debug-spec/pull/601/files . Now it seems they just recommend debug software to do a fence when completing abstract commands.",,,,N/A,What are we doing here?,Added N/A disclaimer. Striking it., +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt10,Program Buffer,Ctrl. Transfer instr.,"All control transfer instructions may act as illegal instructions if destination is within program buffer. If one does, all must.",N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior,,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt11,Program Buffer,Ctrl. Transfer instr.,"All control transfer instructions may as illegal instructions if destination is outside the program buffer. If one does, all must.",N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior,,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt12,Program Buffer,Instr. Dependent of PC,Instructions that depend on the PC may act as illegal instructions,N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior,,,,N/A,,"Fix ""40p""", RISC-V External Debug Support Version 0.13.2,4.1 Debug mode pt13,Program Buffer,Effective XLEN,Effective XLEN = DXLEN,"CV32E40s XLEN=1 (32 bits). DXLEN is defined as the widest supported XLEN. For now, this will be 1 (32 bits). Check XLEN M- and D-mode Mike: what exactly would a testcase actually do to check this? -ØK: As discussed in the meeting 02.July, this is probably a SW/DM problem. Leaving it here for reference.",,,,N/A,,,,,,,,, -,,,,,,,,,N/A,,"Fix ""40p""",,,,,,, -RISC-V External Debug Support Version 0.13.2,4.2 Load-Reserved/Store-Conditional,,,,"N/A for CV32E40s (requires A-extention) : need Arjan/Davide to sign-off on this. [PZ] This is not a test but a warning or assumption that debug entry should not occur between a lr and sc instruction pair. Moreover, CV32E40s does not support A-extension",,,,N/A,,"Fix ""40p""",,,,,,, -RISC-V External Debug Support Version 0.13.2,4.3 Wait for interrupt,Debug mode,WFI instruction,"If debug_req_i is asserted while waiting for interrupt (core_sleep_o = 1), WFI instruction must complete (core_sleep_o -> 0) and hart enters debug mode.","Insert WFI instruction into arbitrary code. While the hart is waiting for an interrupt, request debug mode. The hart must stop waiting for interrupt and enter debug mode. WFI at trigger will be converted to a NOP and should be a dedicated test. See #pz_ref2 in this sheet below",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""","Update reference document, applies to several following points",,,,,,,, +ØK: As discussed in the meeting 02.July, this is probably a SW/DM problem. Leaving it here for reference.",,,,N/A,,, +,,,,,,,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.2 Load-Reserved/Store-Conditional,,,,"N/A for CV32E40s (requires A-extention) : need Arjan/Davide to sign-off on this. [PZ] This is not a test but a warning or assumption that debug entry should not occur between a lr and sc instruction pair. Moreover, CV32E40s does not support A-extension",,,,N/A,,"Fix ""40p""", +RISC-V External Debug Support Version 0.13.2,4.3 Wait for interrupt,Debug mode,WFI instruction,"If debug_req_i is asserted while waiting for interrupt (core_sleep_o = 1), WFI instruction must complete (core_sleep_o -> 0) and hart enters debug mode.","Insert WFI instruction into arbitrary code. While the hart is waiting for an interrupt, request debug mode. The hart must stop waiting for interrupt and enter debug mode. WFI at trigger will be converted to a NOP and should be a dedicated test. See #pz_ref2 in this sheet below",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: wfi_before_dmode","Update reference document, applies to several following points",, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_debug_req A: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req_wu -A: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req",,,,,,,,, -RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"By setting step in dcsr[2] before resuming execution, a debugger can cause the hart to execute a single instructin before re-entering debug mode.",Bring the hart into debug mode. Set the step bit in dcsr[2] and then resume execution. Observe that the hart runs a single instruction and the goes back to debug mode.,Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req",,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"By setting step in dcsr[2] before resuming execution, a debugger can cause the hart to execute a single instructin before re-entering debug mode.",Bring the hart into debug mode. Set the step bit in dcsr[2] and then resume execution. Observe that the hart runs a single instruction and the goes back to debug mode.,Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step",,, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step) A: uvmt_cv32_tb.u_debug_assert.a_single_step -A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",,, RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the instruction being fetched or executed in a single step casues an exception, debug mode is entered immediately after the PC is changed to the exception handler and registers tval and cause are updated. Note: CV32E40S does not support tval (this might be supported in future cores)","Perform a single step. Make sure the instruction executed in the step will cause an exception. PC must jump to the exception handler address and update tval and cause and then immediately enter debug mode. -Check tval==0",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""","Update to reflect that we are now checking ""future cores""",,,,,,,, +Check tval==0",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step","Update to reflect that we are now checking ""future cores""",, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_illegal) -A: uvmt_cv32_tb.u_debug_assert.a_single_step_exception",,,,,,,,, -RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the instruction being fetched or executed in a single step causes a trigger, debug mode is entered immediately after the trigger fired. Cause is set to 2 instead of 4","Set up the trigger module to match on instruction address. Set up single stepping such that the match address will be executed in a step. The trigger module must fire during the step, and debug mode entered with cause = 2 to identify that the trigger was fired. (#1)",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_single_step_exception",,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the instruction being fetched or executed in a single step causes a trigger, debug mode is entered immediately after the trigger fired. Cause is set to 2 instead of 4","Set up the trigger module to match on instruction address. Set up single stepping such that the match address will be executed in a step. The trigger module must fire during the step, and debug mode entered with cause = 2 to identify that the trigger was fired. (#1)",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step",,, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_trigger_match) A: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger -A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",,,,,,,,, -RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the intruction executed in the single step results in a PC that will cause an exception, the exception will not execute until the next time the hart resumes.","Make sure that an instruction in the instruction memory will generate a PC that causes an exception. Set up single stepping and make sure to step through this specific instruction. Hart must go back to debug mode after stepping, and the exception must not start executing until the next time the hart resumes (either single step or exit debug mode)",Self Checking Test,,,N/A,,,,,,,,, -,,,,,,Check against ISS,,,N/A,,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the intruction executed in the single step results in a PC that will cause an exception, the exception will not execute until the next time the hart resumes.","Make sure that an instruction in the instruction memory will generate a PC that causes an exception. Set up single stepping and make sure to step through this specific instruction. Hart must go back to debug mode after stepping, and the exception must not start executing until the next time the hart resumes (either single step or exit debug mode)",Self Checking Test,,,N/A,,, +,,,,,,Check against ISS,,,N/A,,, RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the intruction executed in the single step results in a PC that will cause a trigger event, the trigger event will not take place until the instruction is executed.","This can be verified in the same steps as marked with (#1). -Mike: this may be difficult to accurately predict in the ISS. This is good input for the Imperas team.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, +Mike: this may be difficult to accurately predict in the ISS. This is good input for the Imperas team.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step",,, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_next_pc_will_match) A: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger -A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",,,,,,,,, -RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the single step instruction is WFI, it must be treated as a nop instead of stalling and waiting for interrupt. [PZ] #pz_ref2","Perform a single step where the instruction to be executed is a WFI instruction. The hart must not wait for interrupt, but treat the instruction as as NOP and re-enter debug after finishing the step.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_enter_debug",,, +RISC-V External Debug Support Version 0.13.2,4.4 Single step,Debug mode,Single stepping,"If the single step instruction is WFI, it must be treated as a nop instead of stalling and waiting for interrupt. [PZ] #pz_ref2","Perform a single step where the instruction to be executed is a WFI instruction. The hart must not wait for interrupt, but treat the instruction as as NOP and re-enter debug after finishing the step.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: single_step",,, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_wfi) -A: uvmt_cv32_tb.u_debug_assert.a_single_step_wfi",,,,,,,,, -RISC-V External Debug Support Version 0.13.2,4.5 Reset,Debug mode,Reset,"When the hart comes out of reset, it must immediately enter debug mode without executing any instructions if the halt signal or debug_req_i is asserted.","Assert the core reset AND the debug_req_i signal. The hart must not execute any instructions, but immediately enter debug mode.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_reset""",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_single_step_wfi",,, +RISC-V External Debug Support Version 0.13.2,4.5 Reset,Debug mode,Reset,"When the hart comes out of reset, it must immediately enter debug mode without executing any instructions if the halt signal or debug_req_i is asserted.","Assert the core reset AND the debug_req_i signal. The hart must not execute any instructions, but immediately enter debug mode.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_reset""",,, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_at_reset -A: uvmt_cv32_tb.u_debug_assert.a_debug_at_reset",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_debug_at_reset",,, RISC-V External Debug Support Version 0.13.2,4.6 dret instruction,Debug mode,dret instruction,Executing dret while NOT in debug mode will cause an illegal instruction exception.,"Insert dret into arbitrary code running in m-mode, observe that the illegal insctruction exception is thrown. -Can be tested in the same test as for debug entry",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, +Can be tested in the same test as for debug entry",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: dret_in_mmode",,, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret -A: uvmt_cv32_tb.u_debug_assert.a_mumode_dret",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_mumode_dret",,, RISC-V External Debug Support Version 0.13.2,4.6 dret instruction,Debug mode,dret instruction,Executing dret while in debug mode will restore PC to the value in dpc and exit debug mode.,"Bring hart into debug mode. Execute a dret instruction and observe that the hart resumes executing from the correct address as given by dpc. -Can be tested in the same test as for debug entry.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""","remove note, this is covered or 40s (U-Mode) in the next point",,,,,,,, +Can be tested in the same test as for debug entry.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: all testcases that enter and exit debug mode (most)","remove note, this is covered or 40s (U-Mode) in the next point",, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret -A: uvmt_cv32_tb.u_debug_assert.a_dmode_dret",,,,,,,,, -Debug 1.0.0,Execution Based,Debug mode,dret instruction,"40S, ""When dret is executed, […] normal execution resumes at the privilege set by prv""","Be in debug mode, note the value in ""dcsr.prv"", exit debug mode with a ""dret"", check that the mode being executed in is the one indicated by ""dcsr.prv"". (Note overlap with user mode vplan.)",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -Debug 1.0.0,Resume,Debug mode,dret instruction,"40S, ""If the new privilege mode is less privileged than M-mode, MPRV in mstatus is cleared.""","Be in debug mode, set ""dcsr.prv"" to U-mode, let ""mstatus.MPRV"" be set and clear (different runs), exit debug mode with a ""dret"", check that ""mstatus.MPRV"" ends up cleared. (Note overlap with user mode vplan.)",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_dmode_dret",,, +Debug 1.0.0,Execution Based,Debug mode,dret instruction,"40S, ""When dret is executed, […] normal execution resumes at the privilege set by prv""","Be in debug mode, note the value in ""dcsr.prv"", exit debug mode with a ""dret"", check that the mode being executed in is the one indicated by ""dcsr.prv"". (Note overlap with user mode vplan.)",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: mprv_dret_to_umode",?,?,? +,,,,,,Assertion Check,Other,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dret_prv,?,?,? +Debug 1.0.0,Resume,Debug mode,dret instruction,"40S, ""If the new privilege mode is less privileged than M-mode, MPRV in mstatus is cleared.""","Be in debug mode, set ""dcsr.prv"" to U-mode, let ""mstatus.MPRV"" be set and clear (different runs), exit debug mode with a ""dret"", check that ""mstatus.MPRV"" ends up cleared. (Note overlap with user mode vplan.)",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: mprv_dret_to_umode",?,?,? +,,,,,,Assertion Check,Other,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dret_mprv_umode,?,?,? Debug 1.0.0,Debug Control and Status,Debug mode,dret instruction,"""Upon entry into Debug Mode, v and prv are updated with the privilege level the hart was previously in""","40S, enter debug mode from different modes, check that ""dcsr.prv"" represents the previous mode. (Note overlap with user mode vplan.) -40X, check that ""dcsr.prv"" is always M-mode.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, +40X, check that ""dcsr.prv"" is always M-mode.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test2"" +tc: mprv_dret_to_umode",?,?,? +,,,,,,Assertion Check,Other,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prv_entry,?,?,? "RISC-V ISM vol 1 (unpriv. ISA), 20191213","Section 2.8 @@ -307,35 +356,33 @@ slli x0, x0, 0x1f # Entry NOP ebreak # Break to debugger srai x0, x0, 7 # NOP encoding the semihosting call number 7 -[PZ] This is a software convention and need not be tested in verification. As long as the above instructions work in general, then no need for dedicated semihosting testing.","If all points above passes, there should be nothing to verify here. Semihosting will be handled from SW.",,,,N/A,,,,,,,,, -,,Trigger,Exception handling,"If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.","Set up the trigger to match on an address containing an illegal instruction. When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.",Self Checking Test,Directed Self-Checking,Testcase,With timing=0 the core will not attempt to execute instruction at trigger address,,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"With timing=0 the core will not attempt to execute instruction at trigger address +[PZ] This is a software convention and need not be tested in verification. As long as the above instructions work in general, then no need for dedicated semihosting testing.","If all points above passes, there should be nothing to verify here. Semihosting will be handled from SW.",,,,N/A,,, +,,Trigger,Exception handling,"If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.","Set up the trigger to match on an address containing an illegal instruction. When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.",Self Checking Test,Directed Self-Checking,Testcase,"With ""before timing"" the core will not attempt to execute instruction at trigger address",,"""link to coverage"": Is this merely claimed? Can we either test it or change the relevant vplan items?", +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"With ""before timing"" the core will not attempt to execute instruction at trigger address A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause -A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger",,, ,,"Trigger, single step",Exception handling,"If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.","Set up the trigger to match on an address containing an illegal instruction. Set up single stepping such that the match address will be executed in the next step. -When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.",Self Checking Test,Directed Self-Checking,Testcase,With timing=0 the core will not attempt to execute instruction at trigger address,,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"With timing=0 the core will not attempt to execute instruction at trigger address +When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.",Self Checking Test,Directed Self-Checking,Testcase,"With ""before timing"" the core will not attempt to execute instruction at trigger address",,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"With ""before timing"" the core will not attempt to execute instruction at trigger address A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause -A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger",,, "40S User Manual 0.8.0 OBI-v1.4","Core Integration -dbg",OBI,,"OBI bus accesses shall indicate whether the core is in D-mode or not, signaled via ""instr_dbg_o"" and ""data_dbg_o"".","Be in debug mode and be out of debug mode, execute regular instructions and execute loads/stores, check that the corresponding OBI buses have ""dbg"" set correspondingly.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr +dbg",OBI,,"OBI bus accesses shall indicate whether the core is in D-mode or not, signaled via ""instr_dbg_o"" and ""data_dbg_o"".","Be in debug mode and be out of debug mode, execute regular instructions and execute loads/stores, check that the corresponding OBI buses have ""dbg"" set correspondingly.",Assertion Check,Other,Assertion Coverage,"A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr_inv A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data -A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data_inv",?,?,?,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data_inv",?,?,? "40S User Manual 0.8.0 Debug 1.0.0","Control and Status Registers Debug Control and Status",NMI,,"The ""dcsr.nmip"" bit is supported. -When a non-maskable interrupt is pending, then this bit must be high.","Cause an NMI to occur, read ""dcsr.nmip"", check that it is high as expected. Have no NMI pending, read ""dsr.nmip"", check that it is low.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, +When a non-maskable interrupt is pending, then this bit must be high.","Cause an NMI to occur, read ""dcsr.nmip"", check that it is high as expected. Have no NMI pending, read ""dsr.nmip"", check that it is low.",Assertion Check,Other,Functional Coverage,A: uvmt_cv32_tb.u_debug_assert.a_dcsr_nmip,?,?,? "40X/S user manual Debug 1.0.0 @@ -347,23 +394,20 @@ Debug Control and Status Machine Status Registers",MPRV,,"""dcsr.mprven"" is WARL 1. Since ""mprven"" is 1, then ""mstatus.MPRV"" always takes effect in D-mode.","Read ""dcsr.mprven"", check that it is always 1. -40S, be in debug mode, have ""mstatus.MPRV"" disabled, check that all instructions are treated as M-mode. Be in debug mode, have ""mstatus.MPRV"" enabled, have ""mstatus.MPP"" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -Silabs Internal,,Instruction boundaries,Haltreq and stepping,"External debug requests and single stepping can only cause debug entry on ""instruction boundaries"", so a multi-step instruction cannot be interrupted by this.","While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, -Debug 1.0.0,,Instruction boundaries,Synchronous entry,"Trigger matching can cause synchronous debug entry, and can interrupt ""within"" and instruction.","Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted ""midway"" and that debug mode is entered correctly.",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,?,?,?,,,,,, +40S, be in debug mode, have ""mstatus.MPRV"" disabled, check that all instructions are treated as M-mode. Be in debug mode, have ""mstatus.MPRV"" enabled, have ""mstatus.MPP"" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.",Assertion Check,Other,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mprven_tied,?,?,? +Silabs Internal,,Instruction boundaries,Haltreq and stepping,"External debug requests and single stepping can only cause debug entry on ""instruction boundaries"", so a multi-step instruction cannot be interrupted by this.","While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.",Self Checking Test,Directed Self-Checking,Testcase,TODO: not covered,?,?,? +Debug 1.0.0,,Instruction boundaries,Synchronous entry,"Trigger matching can cause synchronous debug entry, and can interrupt ""within"" and instruction.","Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted ""midway"" and that debug mode is entered correctly.",Self Checking Test,Directed Self-Checking,Testcase,"DTC: pushpop_debug_triggers +TODO: Increase coverage by checking triggers at first/last operation",?,?,? "RISC-V External Debug Support Version 0.13.2 CV32E40P doc rev 46711ac","4.8.1 DCSR -Control and Status Registers",Single step,Interrupts,"While single stepping, interrupts (maskable and non-maskable) may be enabled or disabled using the dcsr.stepie bit. ","Set up single stepping. Ensure interrupt is asserted while performing a step. Ensure that the interrupt is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",?,?,?,,,,,, +Control and Status Registers",Single step,Interrupts,"While single stepping, interrupts (maskable and non-maskable) may be enabled or disabled using the dcsr.stepie bit. ","Set up single stepping. Ensure interrupt is asserted while performing a step. Ensure that the interrupt is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.",Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",?,?,? ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (mmode_step_stepie) -A: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis",?,?,?,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis",?,?,? ,,,,,"Set up single stepping. Ensure NMI is asserted while performing a step. Ensure that the NMI is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0. -",Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvmt_cv32_tb.u_debug_assert.cov_step_stepie_nmi -A: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis",?,?,?,,,,,, -,,Interrupts,Simultaneous Interrupt,,Have debug_req_i and interrupt asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the interrupt exception address),Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,,,,,,,, +",Assertion Check,Other,Assertion Coverage,"CG: uvmt_cv32_tb.u_debug_assert.cov_step_stepie_nmi +A: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis, uvmt_cv32_tb.u_debug_assert.a_stepie_irq_en",?,?,? +,,Interrupts,Simultaneous Interrupt,,Have debug_req_i and interrupt asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the interrupt exception address),Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test""",,, ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq ""NOTE: not tested specifically, but is covered in formal verification of: @@ -371,27 +415,27 @@ A: uvmt_cv32_tb.u_debug_assert.a_enter_debug A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause"" -","What feature is this? Several points in this region lack context, or a merging of left hand cells",,,,,,,, -,,,Simultaneous NMI,,Have debug_req_i and NMI asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the NMI exception address),Self Checking Test,Directed Self-Checking,Testcase,,?,?,?,,,,,, +","What feature is this? Several points in this region lack context, or a merging of left hand cells",, +,,,Simultaneous NMI,,Have debug_req_i and NMI asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the NMI exception address),Self Checking Test,Directed Self-Checking,Testcase,,?,?,? ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"NOTE: not tested specifically, but is covered in formal verification of: A: uvmt_cv32_tb.u_debug_assert.a_enter_debug -A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",?,?,?,,,,,, -,,RISCV compliance,,All RISCV code should run in debug mode as well as M mode,[PZ] Run RISCV compliance tests all in debug mode,Self Checking Test,Directed Self-Checking,Testcase,Waived,,,,,,,,, -,,Corner Cases,Corner Cases,,[PZ] assert debug_req and interrupt at the same time as trigger is matching an address (with trigger enabled) and the instruction being 1) illegal instruction 2) exception call (e.g. ebreak with ebreakm==0) 3) branch 4) multicycle instruction (e.g. mulh),Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_trigger""",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",?,?,? +,,RISCV compliance,,All RISCV code should run in debug mode as well as M mode,[PZ] Run RISCV compliance tests all in debug mode,Self Checking Test,Directed Self-Checking,Testcase,Waived,,, +,,Corner Cases,Corner Cases,,[PZ] assert debug_req and interrupt at the same time as trigger is matching an address (with trigger enabled) and the instruction being 1) illegal instruction 2) exception call (e.g. ebreak with ebreakm==0) 3) branch 4) multicycle instruction (e.g. mulh),Self Checking Test,Directed Self-Checking,Testcase,"Covered in DTC ""debug_test_trigger""",,, ,,,,,,Check against ISS,Constrained-Random,Functional coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq (.irq_dreq_trig_ill/cebreak/ebreak/branch/multicycle) -",,,,,,,,, +",,, ,,,,,[PZ] Add coverage to ensure debug_req asserted on every FSM state,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext -",,,,,,,,, -,,,,,[PZ] Have trigger address match an instruction that has an illegal instruction (both in normal and single step mode). Ensure debug is enterred with cause set to trigger and PC is set to exception handler prior to debug entry,,,,"Not possible with timing=0, core will not execute instruction at match address before entering debug mode.",,,,,,,,, -,,,,"If a debug_req_i is asserted when an illegal instructions is being executed, the address of the trap handler must be stored to dpc instead of the address of the illegal instruction","Assert debug_req_i at the same time as an illegal instruction is being executed, observe that dpc is updated with the address of the trap handler instead of the address of the illegal instruction",Self Checking Test,Directed Self-Checking,Testcase,Covered in DTC debug_test_known_miscompares,Lacks verification goal,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,A: uvmt_cv32_tb.u_debug_assert.a_illegal_insn_debug_req,,,,,,,,, +",,, +,,,,,[PZ] Have trigger address match an instruction that has an illegal instruction (both in normal and single step mode). Ensure debug is enterred with cause set to trigger and PC is set to exception handler prior to debug entry,,,,"Not possible with ""before timing"", core will not execute instruction at match address before entering debug mode.",,, +,,,,"If a debug_req_i is asserted when an illegal instructions is being executed, the address of the trap handler must be stored to dpc instead of the address of the illegal instruction","Assert debug_req_i at the same time as an illegal instruction is being executed, observe that dpc is updated with the address of the trap handler instead of the address of the illegal instruction",Self Checking Test,Directed Self-Checking,Testcase,Covered in DTC debug_test_known_miscompares,Lacks verification goal,, +,,,,,,Check against ISS,Constrained-Random,Functional Coverage,A: uvmt_cv32_tb.u_debug_assert.a_illegal_insn_debug_req,,, ,,,,"Several causes exist for entering debug, the priority is specified in a table in the ""dcsr"" section of the debug spec. -Note: This changed going to v1.0.0","Ensure combinations of reasons exist simultaneously, and observer that the correct cause is stored to dcsr.",Self Checking Test,Directed Self-Checking,Testcase,"Partly covered in DTC ""debug_test"" and ""debug_test_trigger"", the rest will be covered by corev_rand_debug_ebreak and corev_rand_debug_single_step",?,?,?,,,,,, +Note: This changed going to v1.0.0","Ensure combinations of reasons exist simultaneously, and observer that the correct cause is stored to dcsr.",Self Checking Test,Directed Self-Checking,Testcase,"Partly covered in DTC ""debug_test"" and ""debug_test_trigger"", the rest will be covered by corev_rand_debug_ebreak and corev_rand_debug_single_step",?,?,? ,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.debug_causes (.trig_vs_ebreak, trig_vs_cebreak, trig_vs_dbg_req, trig_vs_step - ebreak_vs_req, cebreak_vs_req, ebreak_vs_step, cebreak_vs_step, dbg_req_vs_step)",?,?,?,,,,,, + ebreak_vs_req, cebreak_vs_req, ebreak_vs_step, cebreak_vs_step, dbg_req_vs_step)",?,?,? ,,,3-way Corners,"* Haltreq, then single-step ebreak * Single-step ebreak, then haltreq * Single-step ebreak with trigger @@ -400,53 +444,47 @@ Note: This changed going to v1.0.0","Ensure combinations of reasons exist simult * Haltreq, then ebreak, then trigger on next instr * Haltreq during ebreak with trigger * Haltreq during ebreak, then tirgger on next instr -(More 3-way corners could be possible, see ""Generated Corners"" below.)","Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.",Self Checking Test,Directed Self-Checking,Testcase,,,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"NOTE: not tested specifically, but is covered in formal verification of: +(More 3-way corners could be possible, see ""Generated Corners"" below.)","Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.",Assertion Check,Other,Assertion Coverage,"NOTE: not tested specifically, but is covered in formal verification of: A: uvmt_cv32_tb.u_debug_assert.a_enter_debug -A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",,, ,,,4-way Corners,"* Haltreq, then single-step ebreak with trigger * Haltreq, then single-step ebreak, then trigger on next instr * Single-step ebreak with trigger, then haltreq * Single-step ebreak, then haltreq and trigger on next instr -(More 4-way corners could be possible, see ""Generated Corners"" below.)","Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.",Self Checking Test,Directed Self-Checking,Testcase,,,,,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,"NOTE: not tested specifically, but is covered in formal verification of: +(More 4-way corners could be possible, see ""Generated Corners"" below.)","Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.",Assertion Check,Other,Assertion Coverage,"NOTE: not tested specifically, but is covered in formal verification of: A: uvmt_cv32_tb.u_debug_assert.a_enter_debug -A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",,, ,,,Generated Corners,There are many corners,"Write a covergroup with all events that can cause debug entry {haltreq, step, etc…} and include timing aspects of first/then (""e.g. haltreq right after step"", etc…). Then, create a cross of all of these, as that should in principle generate all possible corners if written comprehensively. Finally, review if all of these corners are covered by the assertion set.",Assertion Check,Constrained-Random,Functional Coverage,"NOTE: not tested specifically, but is covered in formal verification of: A: uvmt_cv32_tb.u_debug_assert.a_enter_debug -A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",,,,,,,,, -,,,Dret,https://github.com/openhwgroup/core-v-verif/issues/1476,"Execute ""dret"" in M-mode, followed by a haltreq (as early as possible), so D-mode is entered before the exception handler. Ensure the rest of debug modelling has predictions on all csr and rvfi signals needed for checking this outcome.",Assertion Check,Constrained-Random,Functional Coverage,A: uvmt_cv32_tb.u_debug_assert.a_mumode_dret,,,,,,,,, -,,External debug request,Startup / clock gating,"When the reset signal is deasserted, but before the fetch_enable_i signal is active, the internal clock of the core is gated. The cv32e40p would not miss this request, but on the 40s haltreq is no longer sticky and so it should not cause debug entry.","Assert short (1 cycle) debug_req_i randomly after reset, before the core starts executing. Observe that the core does not enter debug mode but instead starts executing instructions.",Self Checking Test,Directed Self-Checking,Testcase,Covered in DTC debug_test_boot_set,Deprecated as debug_req is now non-sticky,"Fix ""40p""",?,,,,,, -RISC-V Debug Support Version 1.0.0-STABLE 86e748abed738f8878707dc31fe2713f41868f2c,A.2 Execution Based,Program Buffer,PMP,"""the PMP must not disallow fetches, loads, or stores in the address range associated with the Debug Module when the hart is in Debug Mode, regardless of how the PMP is configured""","Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.",Self Checking Test,Directed Self-Checking,Testcase,,Any verdict on this now?,?,?,,,,,, -,,,,,,Check against ISS,Constrained-Random,Functional Coverage,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -, -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, -,,,,,,,,,,,,,,,,,, +A: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause",,, +,,,Dret,https://github.com/openhwgroup/core-v-verif/issues/1476,"Execute ""dret"" in M-mode, followed by a haltreq (as early as possible), so D-mode is entered before the exception handler. Ensure the rest of debug modelling has predictions on all csr and rvfi signals needed for checking this outcome.",Assertion Check,Constrained-Random,Functional Coverage,A: uvmt_cv32_tb.u_debug_assert.a_mumode_dret,,, +,,External debug request,Startup / clock gating,"When the reset signal is deasserted, but before the fetch_enable_i signal is active, the internal clock of the core is gated. The cv32e40p would not miss this request, but on the 40s haltreq is no longer sticky and so it should not cause debug entry.","Assert short (1 cycle) debug_req_i randomly after reset, before the core starts executing. Observe that the core does not enter debug mode but instead starts executing instructions.",Self Checking Test,Directed Self-Checking,Testcase,Covered in DTC debug_test_boot_set,Deprecated as debug_req is now non-sticky,"Fix ""40p""",? +RISC-V Debug Support Version 1.0.0-STABLE 86e748abed738f8878707dc31fe2713f41868f2c,A.2 Execution Based,Program Buffer,PMP,"""the PMP must not disallow fetches, loads, or stores in the address range associated with the Debug Module when the hart is in Debug Mode, regardless of how the PMP is configured""","Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.",Assertion Check,Other,Assertion Coverage,"A: [uvmt_cv32e40s_pmp_assert].a_accept_only_legal, [uvmt_cv32e40s_pmp_assert].a_deny_only_illegal",Any verdict on this now?,?,? +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,,,,,,,,,,,, +,---- END ----,,,,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json new file mode 100644 index 0000000000..e0406a6e24 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.json @@ -0,0 +1,2387 @@ +[ + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter DEBUG mode", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Debug mode can be entered by executing the EBREAK or C.EBREAK instruction when dcsr.ebreakm = 1\ncause = 1\n\n40S, same is true for \"dcsr.ebreaku\".", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\n\nEnsure exception routine is not enterred", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\" \ntc: mmode_ebreak_executes_debug_code", + "Review (Marton)": "?", + "Review (Robin)": "Are Lee's corner cases handled in this vplan?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter DEBUG mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\n\nEnsure exception routine is not enterred", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_with_ebreakm\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_with_ebreakm\nA :uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.dcsr_cause", + "Review (Marton)": "?", + "Review (Robin)": "Is Mike's gh issue handled in this vplan?", + "Review (Henrik)": "?" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter DEBUG mode", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Debug mode can be entered by executing the EBREAK or C.EBREAK instruction when dcsr.ebreakm = 1\ncause = 1\n\n40S, same is true for \"dcsr.ebreaku\".\n", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary exception code\nVerify that:\nCore switches into debug mode.\nPC of EBREAK instruction must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: exception_enters_debug_mode", + "Review (Marton)": "?", + "Review (Robin)": "Is the PMA overrule handled in this vplan?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter DEBUG mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary exception code\nVerify that:\nCore switches into debug mode.\nPC of EBREAK instruction must be saved to DPC\nCause of debug must be saved to DCSR (cause=1)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "N/A: Hard to detect that we are executing an exception handler.\nCovered in debug_test with ISS enabled.\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.dcsr_cause", + "Review (Marton)": "?", + "Review (Robin)": "Note: From OE about counters, \"vi burde ogs\u00e5 ha assert som sjekker at vi IKKE teller n\u00e5 countinhibit, sleep, eller stopcount... de assertionene jeg har endre sjekker bare at de teller... vet du om vi har andre sjekker p\u00e5 dette?\"", + "Review (Henrik)": "?" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter ebreak exception", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Enter ebreak exception routine when calling EBREAK or C.EBREAK when dcsr.ebreakm == 0.\n\n40S, same is true for \"dcsr.ebreaku\".", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code while ebreakm/u==0.\n\nVerify that:\nCore does not switch to debug mode, but exception routine is entered as normal.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: ebreak_behavior_m_mode", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter ebreak exception", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary code while ebreakm/u==0.\n\nVerify that:\nCore does not switch to debug mode, but exception routine is entered as normal.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_regular_nodebug)\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_regular_nodebug)\nA: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception\nA: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213\n\nCV32E40P doc rev 46711ac", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Enter ebreak exception during single stepping", + "Sub Feature": "EBREAK instruction", + "Feature Description": "Enter ebreak exception routine when calling EBREAK or C.EBREAK when dcsr.ebreakm == 0.\n\n40S, same is true for \"dcsr.ebreaku\".", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary single stepping code\n\nVerify that:\nCore switches into debug mode.\nDPC set to handler.\nDebug cause must be step (unless something else happened simultaneously).\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_known_miscompares\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter ebreak exception during single stepping", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Add EBREAK or/and C.EBREAK to arbitrary single stepping code\n\nVerify that:\nCore switches into debug mode.\nDPC set to handler.\nDebug cause must be step (unless something else happened simultaneously).\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code\nEnsure exception routine is not entered", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_execute_without_ebreakm (ebreak_step_nodebug)\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_execute_without_ebreakm (cebreak_step_nodebug)\n\nA: uvmt_cv32_tb.u_debug_assert.a_ebreak_umode_exception\nA: uvmt_cv32_tb.u_debug_assert.a.ebreak_mmode_exception", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[ebreakm=1?]\"" + }, + { + "Reference document": "CV32E40P doc rev 46711ac", + "Requirement Location": "Debug chapter", + "Feature": "Enter DEBUG mode", + "Sub Feature": "External debug event", + "Feature Description": "Debug mode can be entered by asserting the external signal debug_req_i\ncause is set to = 3 (also see verification goal)", + "Verification Goal": "Assert debug_req_i while executing arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=debugger(0x3))\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: request_hw_debugger", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Enter DEBUG mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert debug_req_i while executing arbitrary code\nVerify that:\nCore switches into debug mode.\nCurrent PC must be saved to DPC\nCause of debug must be saved to DCSR (cause=debugger(0x3))\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_debug_mode_pc\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_haltreq\nA: uvmt_cv32_tb.u_debug_assert.a_debug_req_taken", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "CV32E40P doc rev 46711ac\n\nRISCV-V External Debug Support Version 0.13.2", + "Requirement Location": "Debug chapter \n\n\n\nChapter 5", + "Feature": "Trigger module", + "Sub Feature": "Trigger module match event", + "Feature Description": "The core contains a trigger module with a configurable number of trigger register capable of triggering on i.a. instruction address match.\nSelect mcontrol6 for a trigger and enable instruction matching\nWrite breakpoint addr to tdata2 register\ncause = 2", + "Verification Goal": "Verify that core enters debug mode when the trigger matches on instruction address. NB! According to spec, the tdataN registers can only be written from debug mode, as m-mode writes are ignored.\n\nEnter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and enable breakpoint in tdata1[2]\nExit debug mode (dret instruction)\nVerify that core enters debug mode on breakpoint addr\nCurrent PC is saved to DPC\nCause of debug must be saved to DCSR (cause=2)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_trigger\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify that core enters debug mode when the trigger matches on instruction address. NB! According to spec, the tdataN registers can only be written from debug mode, as m-mode writes are ignored.\n\nEnter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and enable breakpoint in tdata1[2]\nExit debug mode (dret instruction)\nVerify that core enters debug mode on breakpoint addr\nCurrent PC is saved to DPC\nCause of debug must be saved to DCSR (cause=2)\nPC is updated to value on dm_haltaddr_i input\nCore starts executing debug code", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug A:a_dt_instr_trigger_hit_*", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "CV32E40P doc rev 46711ac\n\nRISCV-V External Debug Support Version 0.13.2", + "Requirement Location": "Debug chapter \n\n\n\nChapter 5", + "Feature": "Trigger module", + "Sub Feature": "Trigger module match event", + "Feature Description": "When trigger module is disabled, no trigger should fire even though the PC matches the address in tdata2.", + "Verification Goal": "Enter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and disable breakpoint in tdata1\nExit debug mode (dret instruction)\nVerify that core does not enter debug mode on breakpoint addr\n", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_trigger\"", + "Review (Marton)": "", + "Review (Robin)": "Why is the \"Trigger module\" Feature in red text?", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Enter debug mode by any of the above methods.\nWrite (randomized) breakpoint addr to tdata2 and disable breakpoint in tdata1\nExit debug mode (dret instruction)\nVerify that core does not enter debug mode on breakpoint addr\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "CG: cg_trigger_match_disabled\nA: uvmt_cv32_tb.u_debug_assert.a_trigger_match_disabled\n", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug & Trigger", + "Feature": "Trigger module", + "Sub Feature": "Number of triggers", + "Feature Description": "The number of triggers is determined by DBG_NUM_TRIGGERS.\nWhen num triggers is 0, accessing the trigger registers causes illegal instruction exception.\nTriggers never fire.\n\"tselect\" is 0.", + "Verification Goal": "Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. Check that no triggers ever fire. Check that \"tselect\" is 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_0_trigger", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[40x? Also below.]\"" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. Check that no triggers ever fire. Check that \"tselect\" is 0.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A:a_dt_0_triggers_tdata1_access, a_dt_0_triggers_no_triggering", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "The number of triggers is determined by DBG_NUM_TRIGGERS.\nDBG_NUM_TRIGGERS can be any value within 0-4.\n\"tselect\" is WARL (0x0 - (DBG_NUM_TRIGGERS-1)).\nAll selectable triggers are functional.\nAll trigger registers are accessible except for \"mcontext\", \"mscontext\", \"hcontext\", and \"scontext\" (those four trap upon access).", + "Verification Goal": "For all number of triggers, use tselect to exercise each trigger with each supported type. (Also try writing to higher \"tselect\" than supported and check that a supported number is read back.) Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "There are a lot of things to check in a single point here. Nothing is wrong with this point as I see it, so there is no need to change, but ideally this point should be split up.", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "For all number of triggers, use tselect to exercise each trigger with each supported type. (Also try writing to higher \"tselect\" than supported and check that a supported number is read back.) Make the triggers fire and check that debug mode is entered. Check also that the four context registers trap when accessed.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_access_context, a_dt_tselect_higher_than_dbg_num_triggers, a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason. COV: c_trigger_i_has_type_mcontrol, c_trigger_i_has_type_etrigger, c_trigger_i_has_type_mcontrol6, c_trigger_i_has_type_disable", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "User Manual v0.9.0.", + "Requirement Location": "Control and Status Registers", + "Feature": "Trigger module", + "Sub Feature": "tcontrol", + "Feature Description": "\"tcontrol\" doesn't exist.", + "Verification Goal": "Check that attempts to access \"tcontrol\" raise an illegal instruction exception, always. (Unless overruled by a higher priority.)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that attempts to access \"tcontrol\" raise an illegal instruction exception, always. (Unless overruled by a higher priority.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_tcontrol_not_implemented", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" compare values", + "Feature Description": "\nInstr execute matching uses only one \"compare value\" (the PC itself).\nLoad/Store matching uses compare values depending on the size of the access {A, A+1, etc}.", + "Verification Goal": "Exercise address match triggers for instr/load/store with different sizes (16/32 for instr, 8/16/32 for loadstore). Check that instr match only happens on the exact address. Check that loadstore addr matching triggers on any byte.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Exercise address match triggers for instr/load/store with different sizes (16/32 for instr, 8/16/32 for loadstore). Check that instr match only happens on the exact address. Check that loadstore addr matching triggers on any byte.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_enter_dbg_reason, a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "User Manual v0.9.0.\n\nDebug 1.0-STABLE fb7025", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "Mcontrol6Hit", + "Feature Description": "When a trigger fires, it's \"mcontrol6.hit\" field gets set to 1.\n(This is also true when multiple triggers fire at once.)", + "Verification Goal": "Induce firing of a trigger.\nCheck that the corresponding \"hit\" field gets set.\nDo the same for variations of multiple triggers firing at once.\nCheck that the field is WARL 0x0, 0x1.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Induce firing of a trigger.\nCheck that the corresponding \"hit\" field gets set.\nDo the same for variations of multiple triggers firing at once.\nCheck that the field is WARL 0x0, 0x1.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_m6_hit_bit\na_dt_warl_tdata1_m6", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "Mcontrol6Match", + "Feature Description": "Supported match conditions in \"mcontrol6.match\" are {0 (eq), 2 (geq), 3 (less)}.", + "Verification Goal": "Configure triggers using all three match conditions, exercise them within and outside of the conditions, check that debug mode is/isn't entered. Must also cross against the \"match types\" item above.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure triggers using all three match conditions, exercise them within and outside of the conditions, check that debug mode is/isn't entered. Must also cross against the \"match types\" item above.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_enter_dbg_reason, a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "Mcontrol6UM", + "Feature Description": "Triggers can be en/disabled in M-mode, \"mcontrol6.m\", default is 0.\n40S, triggers can be en/disabled in U-mode, \"mcontrol6.u\", default is 0.\n40X, triggers cannot be enabled in U-mode, \"mcontrol6.u\", WARL (0x0).\nThe trigger action is always to enter D-mode, so \"mcontrol6.action\" is always 1.", + "Verification Goal": "Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have triggers configured to be able to match, but enable/disable their corresponding mode bit, check that the trigger is either able to fire or is blocked from firing accordingly. Also check the tied values.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A:a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_tie_offs_*", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "Mcontrol6LoadStoreExecute", + "Feature Description": "The \"load\" and \"store\" bits are supported (so load/store addr matching is supported).\nThe \"execute\" bit is also supported.\nThe only supported match types are \"address match\" for {instr execution, load, store}, all using \"before\" timing.\nData matching is not supported (only addr matching), so \"mcontrol6.select\" is always 0.", + "Verification Goal": "Configure triggers for load/store/execute and combinations of them, configure tdata2, cause triggers to fire and check that debug mode is entered correctly. All of these configurations must be crossed, also against match conditions.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "?", + "Review (Robin)": "\"tdata3\" and \"tcontrol\" should be removed.", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure triggers for load/store/execute and combinations of them, configure tdata2, cause triggers to fire and check that debug mode is entered correctly. All of these configurations must be crossed, also against match conditions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*. ", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "User Manual v0.9.0.", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "trigger csrs", + "Feature Description": "Some fields in the trigger csrs are hardwired.", + "Verification Goal": "Check that the tied fields are tied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_tie_offs_tselect, a_dt_tie_offs_tdata1_mcontrol, a_dt_tie_offs_tdata1_etrigger, a_dt_tie_offs_tdata1_mcontrol6, a_dt_tie_offs_tdata1_disabled, a_dt_tie_offs_tdata2_etrigger. a_dt_tie_offs_tinfo.", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"mcontrol6\" atomics", + "Feature Description": "40X, \"mcontrol6\" trigger behavior has specific descriptions for \"A\" extension.", + "Verification Goal": "40X, TODO this section must be filled out when the time comes for planning atomics verification.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nTrigger Data 1", + "Feature": "Trigger module", + "Sub Feature": "\"tdata1.type\"", + "Feature Description": "The only supported types are \"2 = address match legacy\", \"5 = Exception trigger\", \"6 = Address match\", and \"15 = Disabled\".", + "Verification Goal": "Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is \"15\".", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that these types can be selected, and check that no other types can be selected. (Functionality of these types should be handled by other items in this plan.) Check also that the default is \"15\".", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_tdata1_types", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "\"tdata1.dmode\"", + "Feature Description": "This bit is WARL (0x1), so only D-mode can write tdata registers. And this bit is still WARL (0x1) regardless of \"type\" (2, 5, 6, 15).", + "Verification Goal": "Try to write tdata registers outside of debug mode, check that they are not writable. Try changing \"tdata1.dmode\" and check that it is WARL (0x1). Cross the above checks with all supported types.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try to write tdata registers outside of debug mode, check that they are not writable. Try changing \"tdata1.dmode\" and check that it is WARL (0x1). Cross the above checks with all supported types.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_not_access_tdata1_dbg_mode, a_dt_not_access_tdata2_dbg_mode, a_dt_dmode", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nTrigger Info", + "Feature": "Trigger module", + "Sub Feature": "\"tinfo\"", + "Feature Description": "\"tinfo.info\" holds the supported types {2, 5, 6, 15},\n\"tinfo.version\" holds the \"Sdtrig\" spec version,\nand the register is otherwise WARL (0x0).", + "Verification Goal": "\nWhen num triggers is more than 0, check that \"tinfo.info\" is \"1\" for the three supported types,\n\"tinfo.version\" is 0x1,\nand that the remaining bits are 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "\nWhen num triggers is more than 0, check that \"tinfo.info\" is \"1\" for the three supported types,\n\"tinfo.version\" is 0x1,\nand that the remaining bits are 0.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_triggers_tinfo", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "\"[type 2]\"" + }, + { + "Reference document": "40S User Manual\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nException Trigger", + "Feature": "Trigger module", + "Sub Feature": "\"etrigger\"", + "Feature Description": "A trigger (\"tdata1\") can be configured as an exception trigger (\"etrigger\"). Where \"tdata2\" configures the exceptions to fire upon.", + "Verification Goal": "Configure \"tdata1\" and \"tdata2\" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc).", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure \"tdata1\" and \"tdata2\" to fire on exceptions, try both individual and multiple exceptions in addition to supported and unsupported. Exercise scenarios that would trigger or not trigger according to the configuration and check that debug mode is either entered or not entered accordingly, and that the entry goes correctly (pc, dpc, cause, etc).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_glitch_dt_exception_trigger_hit_*", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "The bits {\"hit\", \"vs\", \"vu\", \"s\"} are not supported (WARL 0).\n\"nmi\" does not exist (mentioned because it briefly did).\n\"m\" is fully supported.\n40S, \"u\" is fully supported.\n40X, \"u\" is not supported (WARL0).\nThe triggers always enter D-mode, so \"etrigger.action\" is WARL 1.", + "Verification Goal": "Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: debug_test_trigger", + "Review (Marton)": "?", + "Review (Robin)": "\"tdata3\" and \"tcontrol\" should be removed.", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Configure an exception trigger, use the privmode bits to disable/enable the trigger, exercise the trigger conditions, check that it fires/not accordingly. Also check the WARL fields.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_warl_tselect, a_dt_warl_tdata1_general, a_dt_warl_tdata1_m2, a_dt_warl_tdata1_etrigger, a_dt_warl_tdata1_m6, a_dt_warl_tdata1_disabled, a_dt_warl_tdata2_etrigger, a_dt_warl_tinfo. ", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "40s User Manual 0.8.0", + "Requirement Location": "Debug Chapter", + "Feature": "debug_pc_o", + "Sub Feature": "", + "Feature Description": "Signal \"debug_pc_o\" is the PC of the last retired instruction The signal is only valid when \"debug_pc_valid_o\" is equal to 1", + "Verification Goal": "Verify that the signal can be matched with related rvfi signals", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o\nA: uvmt_cv32_tb.u_debug_assert.a_debug_pc_o_inv", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug chapter", + "Feature": "Debug exception addr", + "Sub Feature": "", + "Feature Description": "If an exception occurs during debug mode, the PC should be set to the dm_exception_addr_i input without changing the status registers", + "Verification Goal": "Bring core into debug mode, generate all exception types and observe that the PC jumps to the address given by dm_exception_addr_i. Observe no change in status registers\nAccording to specification, the core supports several types of exceptions: {instr access fault, illegal instruction, ... etc}", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: illegal_csr_in_dmode\ntc: ecall_in_dmode\ntc: mret_in_dmode\ntc: single_step", + "Review (Marton)": "Point mentions the exceptions supported by the e40p, need to match 40s/x capabilities and update text", + "Review (Robin)": "\"0.8.0\"", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug exception addr", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug mode, generate all exception types and observe that the PC jumps to the address given by dm_exception_addr_i. Observe no change in status registers\nAccording to specification, the core supports several types of exceptions: {instr access fault, illegal instruction, ... etc}", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_exception\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ecall\nA: uvmt_cv32_tb.u_debug_assert.a_debug_mode_exception", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug chapter", + "Feature": "Core debug registers", + "Sub Feature": "Illegal access", + "Feature Description": "Accessing the core debug registers - DCSR, DPC and DSCRATCH0/1 while NOT in debug mode causes an illegal instruction", + "Verification Goal": "Access all debug registers in M-mode and observe that illegal instruction exception is triggered.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: debug_csr_rw", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Core debug registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Access all debug registers in M-mode and observe that illegal instruction exception is triggered.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_regs_m_mode\nA: uvmt_cv32_tb.u_debug_assert.a_debug_regs_mmode", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Debug Control and Status", + "Feature": "\"dcsr\" writability", + "Sub Feature": "", + "Feature Description": "All fields of \"dcsr\" (except some) are only writable by the external debugger. Exceptions are {\"v\", \"prv\", \"cause\", \"nmip\"}.", + "Verification Goal": "Keep track of whether an external debug request has happened, check that if there is a change in \"dcsr\" (except some) then there must have been an external debug request.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: might be covered by directed/random testing, no assert found", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "40S User Manual 0.8.0", + "Requirement Location": "Debug chapter", + "Feature": "Trigger module registers", + "Sub Feature": "Access from M-mode", + "Feature Description": "Accessing the tdata1/2 registers are readable from M-mode, but not writeable. (And is not accessible at all from U-mode.)", + "Verification Goal": "Access all tdata registers in M-mode and observe writes have no effects and reads should reflect register content.\n\nAccess registers from D-mode and observe full R/W access.\n\nAccess from U-mode and observe no access at all.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\".", + "Review (Marton)": "Should we also check r/w in U-mode?", + "Review (Robin)": "\"tdata3\" should be removed.", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Access all tdata registers in M-mode and observe writes have no effects and reads should reflect register content.\n\nAccess registers from D-mode and observe full R/W access.\n\nAccess from U-mode and observe no access at all.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_regs. A: a_dt_no_write_access_to_tdata_in_mmode,\na_dt_read_access_to_tdata1_in_mmode,\na_dt_read_access_to_tdata2_in_mmode,\na_dt_write_access_to_tdata1_in_dmode,\na_dt_write_access_to_tdata2_in_dmode,\na_dt_read_access_to_tdata1_in_dmode,\na_dt_read_access_to_tdata2_in_dmode,\na_dt_no_access_to_tdata_in_umode.\nCOV: c_dt_write_tdata1_in_mmode,\nc_dt_write_tdata2_in_mmode.\n\n", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Trigger Registers", + "Feature": "Trigger module registers", + "Sub Feature": "\"tdata1\", writing zero", + "Feature Description": "\"it is guaranteed that writing 0 to tdata1 disables the trigger, and leaves it in a state where tdata2 can be written with any value that makes sense for any trigger type supported by this trigger.\"\n\nMore generally, \"When a selected trigger is disabled [type 15], tdata2 can be written with any value supported by any of the types this trigger supports\".", + "Verification Goal": "Write 0 to \"tdata1\", ensure that its state becomes disabled (type 15). Write values to \"tdata2\" (addresses and/or exception causes) and exercise would-have-been triggers and check that the trigger does not fire.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_write_0_to_tdata1,\na_dt_enter_dbg_reason", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "Debug 1.0.0\nUserManual v0.9.0.", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "tdata2", + "Feature Description": "\"tdata2\" should always be RW (any) for type 2/6/15.", + "Verification Goal": "Change the type to 2/6/15 and write any data to \"tdata2\", read it back and check that it always gets set.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_write_tdata2_random_in_dmode_type_2_6_15. COV: c_dt_w_csrrw_tdata2_m2_m6_disabled,\nc_dt_w_csrrs_tdata2_m2_m6_disabled,\nc_dt_w_csrrc_tdata2_m2_m6_disabled,\nc_dt_w_csrrwi_tdata2_m2_m6_disabled,\nc_dt_w_csrrsi_tdata2_m2_m6_disabled,\nc_dt_w_csrrci_tdata2_m2_m6_disabled", + "Review (Marton)": "?", + "Review (Robin)": "\"tdata3\" should be removed.", + "Review (Henrik)": "?" + }, + { + "Reference document": "User Manual v0.9.0.", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "tdata3", + "Feature Description": "\"tdata3\" doesn't exist.", + "Verification Goal": "Check that attempts to access \"tdata3\" raise an illegal instruction exception, always. (Unless overruled by a higher priority.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_tdata3_not_implemented.", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "", + "Feature": "Trigger module registers", + "Sub Feature": "Other tdata registers", + "Feature Description": "Writing one \"tdata*\" register must not modify other \"tdata*\" registers, and must not modify other triggers than the currently selected.", + "Verification Goal": "Read the state of all triggers, write to tdata1/2 (using all types in tdata1), read back the state of all triggers and check that nothing got changes except the one \"tdata*\" register that was written.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: a_dt_write_only_tdata1,\na_dt_write_only_tdata2.", + "Review (Marton)": "?", + "Review (Robin)": "\"tdata3\" should be removed.", + "Review (Henrik)": "?" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt2", + "Feature": "Program Buffer", + "Sub Feature": "Interrupts", + "Feature Description": "While in debug mode and executing from the program buffer, all interrupts are masked.", + "Verification Goal": "Enable interrupts (setting mstatus.mie field and mie register).\nBring core into debug mode and start executing from program buffer.\nGenerate interrupts while in debug mode and ensure they are masked.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_in_debug\nA: uvmt_cv32_tb.u_debug_assert.a_irq_in_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt3", + "Feature": "Program Buffer", + "Sub Feature": "Exceptions", + "Feature Description": "While in debug mode and executing from the program buffer, exceptions don\u2019t update any registers but they DO end execution of PB (TBD: goes back to M-mode or restarts in debug(?)) [PZ] this is redundnant with dm_exception_addr_i (on line 10 & 11)", + "Verification Goal": "Bring core into debug mode and start executing from program buffer. Make sure PB includes code that will hit an exception. Make sure core doesn\u2019t update any registers, and jumps out of debug mode into M-mode", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug mode and start executing from program buffer. Make sure PB includes code that will hit an exception. Make sure core doesn\u2019t update any registers, and jumps out of debug mode into M-mode", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt4", + "Feature": "Program Buffer", + "Sub Feature": "Triggers", + "Feature Description": "While in debug mode and executing from the program buffer, no action is taken on any trigger match.", + "Verification Goal": "Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). Continue execution in debug, and observe that no action is taken when the trigger matches.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\". ", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug and enable a trigger on the PC (pointing to the debug program buffer). Continue execution in debug, and observe that no action is taken when the trigger matches.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_trigger_match_disabled (d_match_with_en) A:a_dt_no_actions_on_trigger_matches_in_debug_dcsr\na_dt_no_actions_on_trigger_matches_in_debug_dpc", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "dcsr", + "Feature": "Counters", + "Sub Feature": "", + "Feature Description": "Spec:Counters may be stopped, depending on stopcount in dscr", + "Verification Goal": "\"dcsr.stopcount\" is WARL and we must test the counter bevaior for both values of stopcount.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: test_stopcnt_bits", + "Review (Marton)": "?", + "Review (Robin)": "Is wrong, need update.", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Counters", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "\"dcsr.stopcount\" is WARL and we must test the counter bevaior for both values of stopcount.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_counters_enabled\nA: uvmt_cv32_tb.u_debug_assert.a_minstret_count\nA: uvmt_cv32_tb.u_debug_assert.a_mcycle_count", + "Review (Marton)": "?", + "Review (Robin)": "Any other \"40p\" outdateds here? Marked them all.", + "Review (Henrik)": "?" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt6", + "Feature": "Program Buffer", + "Sub Feature": "Timers", + "Feature Description": "Timers may be stopped, depending on stoptime in dcsr", + "Verification Goal": "(See \"Counters\" above.)", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt7", + "Feature": "Program Buffer", + "Sub Feature": "WFI instruction", + "Feature Description": "In debug, the WFI instruction acts as a NOP instruction", + "Verification Goal": "Bring core into debug mode. Ensure that an WFI instruction will be executed from the program buffer. Ensure that the WFI will act as a nop, not waiting for an interrupt to occur.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring core into debug mode. Ensure that an WFI instruction will be executed from the program buffer. Ensure that the WFI will act as a nop, not waiting for an interrupt to occur.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_in_debug\nA: uvmt_cv32_tb.u_debug_assert.a_wfi_in_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt8", + "Feature": "Program Buffer", + "Sub Feature": "Priv. lvl changes", + "Feature Description": "An ebreak instruction during debug shall result in relaunching the debugger entry code by setting the PC to the halt_addr_i and will not change any CSR in doing this.", + "Verification Goal": "Bring hart into debug mode and start executing from the Program Buffer. Make sure the PB code includes an ebreak instruction. When the ebreak is executed, the hart must halt and not update dpc or dcsr. Ensure relaunch of debugger entry", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: request_ebreak_3x", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring hart into debug mode and start executing from the Program Buffer. Make sure the PB code includes an ebreak instruction. When the ebreak is executed, the hart must halt and not update dpc or dcsr. Ensure relaunch of debugger entry", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_ebreak_with_ebreakm (.ebreak_in_debug)\nCG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_cebreak_with_ebreakm (.ebreak_in_debug)\nA: uvmt_cv32_tb.u_debug_assert.a_ebreak_during_debug_mode", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt9", + "Feature": "Program Buffer", + "Sub Feature": "Fence instructions", + "Feature Description": "Completing program buffer execution is considered output for the purpose of the fence instruction.", + "Verification Goal": "TBD - need to understand the fence instruction in cv32e40s. Is \"completing program buffer execution\" the same as executing dret? [PZ] waiting for more clarity from RISCV Foundation debug task group (see https://lists.riscv.org/g/tech-debug/topic/clarification_request/75725318?p=,,,20,0,0,0::recentpostdate%2Fsticky,,,20,2,0,75725318 )\n\nNothing to do. That sentence was retracted here https://github.com/riscv/riscv-debug-spec/pull/601/files . Now it seems they just recommend debug software to do a fence when completing abstract commands.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "What are we doing here?", + "Review (Robin)": "Added N/A disclaimer. Striking it.", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt10", + "Feature": "Program Buffer", + "Sub Feature": "Ctrl. Transfer instr.", + "Feature Description": "All control transfer instructions may act as illegal instructions if destination is within program buffer. If one does, all must.", + "Verification Goal": "N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt11", + "Feature": "Program Buffer", + "Sub Feature": "Ctrl. Transfer instr.", + "Feature Description": "All control transfer instructions may as illegal instructions if destination is outside the program buffer. If one does, all must.", + "Verification Goal": "N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt12", + "Feature": "Program Buffer", + "Sub Feature": "Instr. Dependent of PC", + "Feature Description": "Instructions that depend on the PC may act as illegal instructions", + "Verification Goal": "N/A for CV32E40s : need Arjan/Davide to sign-off on this. [PZ] This is not supported and it is mentioned in the CV32E40s debug spec. No verification needed to prove nor dis-prove this behavior", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.1 Debug mode pt13", + "Feature": "Program Buffer", + "Sub Feature": "Effective XLEN", + "Feature Description": "Effective XLEN = DXLEN", + "Verification Goal": "CV32E40s XLEN=1 (32 bits). DXLEN is defined as the widest supported XLEN. For now, this will be 1 (32 bits). Check XLEN M- and D-mode\nMike: what exactly would a testcase actually do to check this?\n\u00d8K: As discussed in the meeting 02.July, this is probably a SW/DM problem. Leaving it here for reference.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "CV32E40s XLEN=1 (32 bits). DXLEN is defined as the widest supported XLEN. For now, this will be 1 (32 bits). Check XLEN M- and D-mode\nMike: what exactly would a testcase actually do to check this?\n\u00d8K: As discussed in the meeting 02.July, this is probably a SW/DM problem. Leaving it here for reference.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.2 Load-Reserved/Store-Conditional", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "N/A for CV32E40s (requires A-extention) : need Arjan/Davide to sign-off on this. [PZ] This is not a test but a warning or assumption that debug entry should not occur between a lr and sc instruction pair. Moreover, CV32E40s does not support A-extension", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.3 Wait for interrupt", + "Feature": "Debug mode", + "Sub Feature": "WFI instruction", + "Feature Description": "If debug_req_i is asserted while waiting for interrupt (core_sleep_o = 1), WFI instruction must complete (core_sleep_o -> 0) and hart enters debug mode.", + "Verification Goal": "Insert WFI instruction into arbitrary code. While the hart is waiting for an interrupt, request debug mode. The hart must stop waiting for interrupt and enter debug mode. WFI at trigger will be converted to a NOP and should be a dedicated test. See #pz_ref2 in this sheet below", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: wfi_before_dmode", + "Review (Marton)": "Update reference document, applies to several following points", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Insert WFI instruction into arbitrary code. While the hart is waiting for an interrupt, request debug mode. The hart must stop waiting for interrupt and enter debug mode. WFI at trigger will be converted to a NOP and should be a dedicated test. See #pz_ref2 in this sheet below", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_wfi_debug_req\nA: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req_wu\nA: uvmt_cv32_tb.u_debug_assert.a_sleep_debug_req", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "By setting step in dcsr[2] before resuming execution, a debugger can cause the hart to execute a single instructin before re-entering debug mode.", + "Verification Goal": "Bring the hart into debug mode. Set the step bit in dcsr[2] and then resume execution. Observe that the hart runs a single instruction and the goes back to debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: single_step", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring the hart into debug mode. Set the step bit in dcsr[2] and then resume execution. Observe that the hart runs a single instruction and the goes back to debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the instruction being fetched or executed in a single step casues an exception, debug mode is entered immediately after the PC is changed to the exception handler and registers tval and cause are updated.\n\nNote: CV32E40S does not support tval (this might be supported in future cores)", + "Verification Goal": "Perform a single step. Make sure the instruction executed in the step will cause an exception. PC must jump to the exception handler address and update tval and cause and then immediately enter debug mode.\n\nCheck tval==0", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: single_step", + "Review (Marton)": "Update to reflect that we are now checking \"future cores\"", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform a single step. Make sure the instruction executed in the step will cause an exception. PC must jump to the exception handler address and update tval and cause and then immediately enter debug mode.\n\nCheck tval==0", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_illegal)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_exception", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the instruction being fetched or executed in a single step causes a trigger, debug mode is entered immediately after the trigger fired. Cause is set to 2 instead of 4", + "Verification Goal": "Set up the trigger module to match on instruction address. Set up single stepping such that the match address will be executed in a step. The trigger module must fire during the step, and debug mode entered with cause = 2 to identify that the trigger was fired. (#1)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: single_step", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up the trigger module to match on instruction address. Set up single stepping such that the match address will be executed in a step. The trigger module must fire during the step, and debug mode entered with cause = 2 to identify that the trigger was fired. (#1)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_trigger_match)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the intruction executed in the single step results in a PC that will cause an exception, the exception will not execute until the next time the hart resumes.", + "Verification Goal": "Make sure that an instruction in the instruction memory will generate a PC that causes an exception. Set up single stepping and make sure to step through this specific instruction. Hart must go back to debug mode after stepping, and the exception must not start executing until the next time the hart resumes (either single step or exit debug mode)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Make sure that an instruction in the instruction memory will generate a PC that causes an exception. Set up single stepping and make sure to step through this specific instruction. Hart must go back to debug mode after stepping, and the exception must not start executing until the next time the hart resumes (either single step or exit debug mode)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the intruction executed in the single step results in a PC that will cause a trigger event, the trigger event will not take place until the instruction is executed.", + "Verification Goal": "This can be verified in the same steps as marked with (#1).\nMike: this may be difficult to accurately predict in the ISS. This is good input for the Imperas team.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: single_step", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "This can be verified in the same steps as marked with (#1).\nMike: this may be difficult to accurately predict in the ISS. This is good input for the Imperas team.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_next_pc_will_match)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_trigger\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.4 Single step", + "Feature": "Debug mode", + "Sub Feature": "Single stepping", + "Feature Description": "If the single step instruction is WFI, it must be treated as a nop instead of stalling and waiting for interrupt. [PZ] #pz_ref2", + "Verification Goal": "Perform a single step where the instruction to be executed is a WFI instruction. The hart must not wait for interrupt, but treat the instruction as as NOP and re-enter debug after finishing the step.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: single_step", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform a single step where the instruction to be executed is a WFI instruction. The hart must not wait for interrupt, but treat the instruction as as NOP and re-enter debug after finishing the step.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (.mmode_step_wfi)\nA: uvmt_cv32_tb.u_debug_assert.a_single_step_wfi", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.5 Reset", + "Feature": "Debug mode", + "Sub Feature": "Reset", + "Feature Description": "When the hart comes out of reset, it must immediately enter debug mode without executing any instructions if the halt signal or debug_req_i is asserted.", + "Verification Goal": "Assert the core reset AND the debug_req_i signal. The hart must not execute any instructions, but immediately enter debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_reset\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert the core reset AND the debug_req_i signal. The hart must not execute any instructions, but immediately enter debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_at_reset\nA: uvmt_cv32_tb.u_debug_assert.a_debug_at_reset", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.6 dret instruction", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "Executing dret while NOT in debug mode will cause an illegal instruction exception.", + "Verification Goal": "Insert dret into arbitrary code running in m-mode, observe that the illegal insctruction exception is thrown.\nCan be tested in the same test as for debug entry", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: dret_in_mmode", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Insert dret into arbitrary code running in m-mode, observe that the illegal insctruction exception is thrown.\nCan be tested in the same test as for debug entry", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret\nA: uvmt_cv32_tb.u_debug_assert.a_mumode_dret", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2", + "Requirement Location": "4.6 dret instruction", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "Executing dret while in debug mode will restore PC to the value in dpc and exit debug mode.", + "Verification Goal": "Bring hart into debug mode. Execute a dret instruction and observe that the hart resumes executing from the correct address as given by dpc. \nCan be tested in the same test as for debug entry.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: all testcases that enter and exit debug mode (most)", + "Review (Marton)": "remove note, this is covered or 40s (U-Mode) in the next point", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Bring hart into debug mode. Execute a dret instruction and observe that the hart resumes executing from the correct address as given by dpc. \nCan be tested in the same test as for debug entry.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_mmode_dret\nA: uvmt_cv32_tb.u_debug_assert.a_dmode_dret", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Execution Based", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "40S, \"When dret is executed, [\u2026] normal execution resumes at the privilege set by prv\"", + "Verification Goal": "Be in debug mode, note the value in \"dcsr.prv\", exit debug mode with a \"dret\", check that the mode being executed in is the one indicated by \"dcsr.prv\". (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: mprv_dret_to_umode", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Be in debug mode, note the value in \"dcsr.prv\", exit debug mode with a \"dret\", check that the mode being executed in is the one indicated by \"dcsr.prv\". (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dret_prv", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Resume", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "40S, \"If the new privilege mode is less privileged than M-mode, MPRV in mstatus is cleared.\"", + "Verification Goal": "Be in debug mode, set \"dcsr.prv\" to U-mode, let \"mstatus.MPRV\" be set and clear (different runs), exit debug mode with a \"dret\", check that \"mstatus.MPRV\" ends up cleared. (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: mprv_dret_to_umode", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Be in debug mode, set \"dcsr.prv\" to U-mode, let \"mstatus.MPRV\" be set and clear (different runs), exit debug mode with a \"dret\", check that \"mstatus.MPRV\" ends up cleared. (Note overlap with user mode vplan.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dret_mprv_umode", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "Debug Control and Status", + "Feature": "Debug mode", + "Sub Feature": "dret instruction", + "Feature Description": "\"Upon entry into Debug Mode, v and prv are updated with the privilege level the hart was previously in\"", + "Verification Goal": "40S, enter debug mode from different modes, check that \"dcsr.prv\" represents the previous mode. (Note overlap with user mode vplan.)\n\n40X, check that \"dcsr.prv\" is always M-mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test2\"\ntc: mprv_dret_to_umode", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "40S, enter debug mode from different modes, check that \"dcsr.prv\" represents the previous mode. (Note overlap with user mode vplan.)\n\n40X, check that \"dcsr.prv\" is always M-mode.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prv_entry", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "RISC-V ISM vol 1 (unpriv. ISA), 20191213", + "Requirement Location": "Section 2.8\n\n\nDebug chapter", + "Feature": "Semihosting", + "Sub Feature": "", + "Feature Description": "To enable semihosting, a special instruction sequence is needed as there is only a single EBREAK instruction available.\n\nslli x0, x0, 0x1f # Entry NOP\nebreak # Break to debugger\nsrai x0, x0, 7 # NOP encoding the semihosting call number 7\n\n[PZ] This is a software convention and need not be tested in verification. As long as the above instructions work in general, then no need for dedicated semihosting testing.", + "Verification Goal": "If all points above passes, there should be nothing to verify here. Semihosting will be handled from SW.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "N/A", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger", + "Sub Feature": "Exception handling", + "Feature Description": "If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "With \"before timing\" the core will not attempt to execute instruction at trigger address", + "Review (Marton)": "", + "Review (Robin)": "\"link to coverage\": Is this merely claimed? Can we either test it or change the relevant vplan items?", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. When the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "With \"before timing\" the core will not attempt to execute instruction at trigger address\n\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger, single step", + "Sub Feature": "Exception handling", + "Feature Description": "If the trigger matches on an illegal instruction, PC must be set to the exception handler prior to entering debug mode.", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. \nSet up single stepping such that the match address will be executed in the next step.\nWhen the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "With \"before timing\" the core will not attempt to execute instruction at trigger address", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Trigger, single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up the trigger to match on an address containing an illegal instruction. \nSet up single stepping such that the match address will be executed in the next step.\nWhen the trigger fires, ensure that cause=0x2(trigger) and that PC is set to the exception handler before entering debug mode.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "With \"before timing\" the core will not attempt to execute instruction at trigger address\n\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\nA: uvmt_cv32_tb.u_debug_assert.a_dpc_dbg_trigger", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "40S User Manual 0.8.0\n\nOBI-v1.4", + "Requirement Location": "Core Integration\n\ndbg", + "Feature": "OBI", + "Sub Feature": "", + "Feature Description": "OBI bus accesses shall indicate whether the core is in D-mode or not, signaled via \"instr_dbg_o\" and \"data_dbg_o\".", + "Verification Goal": "Be in debug mode and be out of debug mode, execute regular instructions and execute loads/stores, check that the corresponding OBI buses have \"dbg\" set correspondingly.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr\nA: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_instr_inv\nA: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data\nA: uvmt_cv32_tb.u_debug_assert.a_obi_dbg_data_inv", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "40S User Manual 0.8.0\n\nDebug 1.0.0", + "Requirement Location": "Control and Status Registers\n\nDebug Control and Status", + "Feature": "NMI", + "Sub Feature": "", + "Feature Description": "The \"dcsr.nmip\" bit is supported.\nWhen a non-maskable interrupt is pending, then this bit must be high.", + "Verification Goal": "Cause an NMI to occur, read \"dcsr.nmip\", check that it is high as expected. Have no NMI pending, read \"dsr.nmip\", check that it is low.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_dcsr_nmip", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "40X/S user manual\n\nDebug 1.0.0\n\nPrivspec 1.12", + "Requirement Location": "Control and Status Registers\n\nDebug Control and Status\n\nMachine Status Registers", + "Feature": "MPRV", + "Sub Feature": "", + "Feature Description": "\"dcsr.mprven\" is WARL 1.\nSince \"mprven\" is 1, then \"mstatus.MPRV\" always takes effect in D-mode.", + "Verification Goal": "Read \"dcsr.mprven\", check that it is always 1.\n\n40S, be in debug mode, have \"mstatus.MPRV\" disabled, check that all instructions are treated as M-mode. Be in debug mode, have \"mstatus.MPRV\" enabled, have \"mstatus.MPP\" set to M/U-mode (different runs), check that instructions take effect with the modified privilege mode.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mprven_tied", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "Silabs Internal", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "Haltreq and stepping", + "Feature Description": "External debug requests and single stepping can only cause debug entry on \"instruction boundaries\", so a multi-step instruction cannot be interrupted by this.", + "Verification Goal": "While single stepping, execute misaligned loads/stores, push/pops, and table jumps, cause an external debug request while the instruction has started its sub operations, check that the external debug request does not interrupt the instructions.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "TODO: not covered", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "Debug 1.0.0", + "Requirement Location": "", + "Feature": "Instruction boundaries", + "Sub Feature": "Synchronous entry", + "Feature Description": "Trigger matching can cause synchronous debug entry, and can interrupt \"within\" and instruction.", + "Verification Goal": "Set up triggers to match the following scenario, execute misaligned loads/stores, push/pops, and table jumps, have a trigger fire while the instruction has started its sub operations, check that the instruction gets interrupted \"midway\" and that debug mode is entered correctly.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: pushpop_debug_triggers\nTODO: Increase coverage by checking triggers at first/last operation", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "RISC-V External Debug Support Version 0.13.2\nCV32E40P doc rev 46711ac", + "Requirement Location": "4.8.1 DCSR\n\nControl and Status Registers", + "Feature": "Single step", + "Sub Feature": "Interrupts", + "Feature Description": "While single stepping, interrupts (maskable and non-maskable) may be enabled or disabled using the dcsr.stepie bit. ", + "Verification Goal": "Set up single stepping. Ensure interrupt is asserted while performing a step. Ensure that the interrupt is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up single stepping. Ensure interrupt is asserted while performing a step. Ensure that the interrupt is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_single_step (mmode_step_stepie)\nA: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Single step", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Set up single stepping. Ensure NMI is asserted while performing a step. Ensure that the NMI is taken when dcsr.stepie = 1, and not taken when dcsr.stepie = 0.\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "CG: uvmt_cv32_tb.u_debug_assert.cov_step_stepie_nmi\nA: uvmt_cv32_tb.u_debug_assert.a_stepie_irq_dis, uvmt_cv32_tb.u_debug_assert.a_stepie_irq_en", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "Simultaneous Interrupt", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and interrupt asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the interrupt exception address)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and interrupt asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the interrupt exception address)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq\n\n\"NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause\"\n\n\n", + "Review (Marton)": "What feature is this? Several points in this region lack context, or a merging of left hand cells", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "Simultaneous NMI", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and NMI asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the NMI exception address)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Interrupts", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Have debug_req_i and NMI asserted on same clock cycle. Ensure debugger entered with PC reflecting normal PC thread (not the NMI exception address)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "RISCV compliance", + "Sub Feature": "", + "Feature Description": "All RISCV code should run in debug mode as well as M mode", + "Verification Goal": "[PZ] Run RISCV compliance tests all in debug mode", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Waived", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "Corner Cases", + "Feature Description": "", + "Verification Goal": "[PZ] assert debug_req and interrupt at the same time as trigger is matching an address (with trigger enabled) and the instruction being 1) illegal instruction 2) exception call (e.g. ebreak with ebreakm==0) 3) branch 4) multicycle instruction (e.g. mulh)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC \"debug_test_trigger\"", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "[PZ] assert debug_req and interrupt at the same time as trigger is matching an address (with trigger enabled) and the instruction being 1) illegal instruction 2) exception call (e.g. ebreak with ebreakm==0) 3) branch 4) multicycle instruction (e.g. mulh)", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_irq_dreq\n (.irq_dreq_trig_ill/cebreak/ebreak/branch/multicycle)\n", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "[PZ] Add coverage to ensure debug_req asserted on every FSM state", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.cg_debug_mode_ext\n", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "[PZ] Have trigger address match an instruction that has an illegal instruction (both in normal and single step mode). Ensure debug is enterred with cause set to trigger and PC is set to exception handler prior to debug entry", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "Not possible with \"before timing\", core will not execute instruction at match address before entering debug mode.", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "If a debug_req_i is asserted when an illegal instructions is being executed, the address of the trap handler must be stored to dpc instead of the address of the illegal instruction", + "Verification Goal": "Assert debug_req_i at the same time as an illegal instruction is being executed, observe that dpc is updated with the address of the trap handler instead of the address of the illegal instruction", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC debug_test_known_miscompares", + "Review (Marton)": "Lacks verification goal", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert debug_req_i at the same time as an illegal instruction is being executed, observe that dpc is updated with the address of the trap handler instead of the address of the illegal instruction", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_illegal_insn_debug_req", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "Several causes exist for entering debug, the priority is specified in a table in the \"dcsr\" section of the debug spec.\n\nNote: This changed going to v1.0.0", + "Verification Goal": "Ensure combinations of reasons exist simultaneously, and observer that the correct cause is stored to dcsr.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Partly covered in DTC \"debug_test\" and \"debug_test_trigger\", the rest will be covered by corev_rand_debug_ebreak and corev_rand_debug_single_step", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure combinations of reasons exist simultaneously, and observer that the correct cause is stored to dcsr.", + "Pass/Fail Criteria": "Check against ISS", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "CG: uvm_pkg.uvm_test_top.env.cov_model.debug_covg.debug_causes\n (.trig_vs_ebreak, trig_vs_cebreak, trig_vs_dbg_req, trig_vs_step\n ebreak_vs_req, cebreak_vs_req, ebreak_vs_step, cebreak_vs_step, dbg_req_vs_step)", + "Review (Marton)": "?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "3-way Corners", + "Feature Description": "* Haltreq, then single-step ebreak\n* Single-step ebreak, then haltreq\n* Single-step ebreak with trigger\n* Single-step ebreak, then trigger on next instr\n* Haltreq, then ebreak with trigger\n* Haltreq, then ebreak, then trigger on next instr\n* Haltreq during ebreak with trigger\n* Haltreq during ebreak, then tirgger on next instr\n(More 3-way corners could be possible, see \"Generated Corners\" below.)", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "4-way Corners", + "Feature Description": "* Haltreq, then single-step ebreak with trigger\n* Haltreq, then single-step ebreak, then trigger on next instr\n* Single-step ebreak with trigger, then haltreq\n* Single-step ebreak, then haltreq and trigger on next instr\n(More 4-way corners could be possible, see \"Generated Corners\" below.)", + "Verification Goal": "Stimulate occurances of all cases, model the outcome (wrt dpc, cause priority, etc), check expectations.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "Generated Corners", + "Feature Description": "There are many corners", + "Verification Goal": "Write a covergroup with all events that can cause debug entry {haltreq, step, etc\u2026} and include timing aspects of first/then (\"e.g. haltreq right after step\", etc\u2026). Then, create a cross of all of these, as that should in principle generate all possible corners if written comprehensively. Finally, review if all of these corners are covered by the assertion set.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "NOTE: not tested specifically, but is covered in formal verification of:\nA: uvmt_cv32_tb.u_debug_assert.a_enter_debug\nA: uvmt_cv32_tb.u_debug_assert.a_dcsr_cause", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Corner Cases", + "Sub Feature": "Dret", + "Feature Description": "https://github.com/openhwgroup/core-v-verif/issues/1476", + "Verification Goal": "Execute \"dret\" in M-mode, followed by a haltreq (as early as possible), so D-mode is entered before the exception handler. Ensure the rest of debug modelling has predictions on all csr and rvfi signals needed for checking this outcome.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32_tb.u_debug_assert.a_mumode_dret", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "External debug request", + "Sub Feature": "Startup / clock gating", + "Feature Description": "When the reset signal is deasserted, but before the fetch_enable_i signal is active, the internal clock of the core is gated. The cv32e40p would not miss this request, but on the 40s haltreq is no longer sticky and so it should not cause debug entry.", + "Verification Goal": "Assert short (1 cycle) debug_req_i randomly after reset, before the core starts executing. Observe that the core does not enter debug mode but instead starts executing instructions.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Covered in DTC debug_test_boot_set", + "Review (Marton)": "Deprecated as debug_req is now non-sticky", + "Review (Robin)": "Fix \"40p\"", + "Review (Henrik)": "?" + }, + { + "Reference document": "RISC-V Debug Support Version 1.0.0-STABLE 86e748abed738f8878707dc31fe2713f41868f2c", + "Requirement Location": "A.2 Execution Based", + "Feature": "Program Buffer", + "Sub Feature": "PMP", + "Feature Description": "\"the PMP must not disallow fetches, loads, or stores in the address range associated with the Debug Module when the hart is in Debug Mode, regardless of how the PMP is configured\"", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Other", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: [uvmt_cv32e40s_pmp_assert].a_accept_only_legal, [uvmt_cv32e40s_pmp_assert].a_deny_only_illegal", + "Review (Marton)": "Any verdict on this now?", + "Review (Robin)": "?", + "Review (Henrik)": "?" + }, + { + "Reference document": "", + "Requirement Location": "", + "Feature": "Program Buffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt all kinds of accesses within the region and observe that it is never disallowed , and also attempt all kinds of accesses outside the region and observe both success and failure based on PMP settings.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Review (Marton)": "", + "Review (Robin)": "", + "Review (Henrik)": "" + }, + { + "Reference document": "", + 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file diff --git a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.xlsx b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.xlsx old mode 100755 new mode 100644 index 0e47baac25..a8541ecae3 Binary files a/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.xlsx and b/cv32e40s/docs/VerifPlans/Simulation/debug-trace/CV32E40XS_debug.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv index 5c5522108c..63683ff06a 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv +++ b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.csv @@ -1,89 +1,106 @@ Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage CLIC 8675ec,Reset behavior,CSR reset value,mintstatus.mil resets to 0,"CSR value check after reset -Do not implement in initial-block to include formal checking",Assertion Check,"ENV capability, not specific test",Functional Coverage, +Do not implement in initial-block to include formal checking",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mintstatus_mil_reset_to_zero CLIC 8675ec,Reset behavior,CSR reset value,"mstatus.mie resets to 0 ","CSR value check after reset -Do not implement in initial-block to include formal checking",Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,Reset behavior,CSR reset value,"mtvec resets to {mtvec_addr_i[31:7]. 5'b0_0000, 2'b11}",Assert that mtvec resets to the correct initialization value,Assertion Check,"ENV capability, not specific test",Functional Coverage, -Risc-V Priv. 1.12,Reset behavior,Interrupts never enabled out of reset,mstatus.mie resets to 0,Assert that interrupts are disabled and never taken immediately after deasserting reset,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Do not implement in initial-block to include formal checking",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mstatus_mie_reset_to_zero +UM v0.3.0 Common,Reset behavior,CSR reset value,"mtvec resets to {mtvec_addr_i[31:7]. 5'b0_0000, 2'b11}",Assert that mtvec resets to the correct initialization value,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mtvec_reset_value_correct +Risc-V Priv. 1.12,Reset behavior,Interrupts never enabled out of reset,mstatus.mie resets to 0,Assert that interrupts are disabled and never taken immediately after deasserting reset,Assertion Check,"ENV capability, not specific test",Functional Coverage,"a_mstatus_mie_reset_to_zero +a_irq_ack_valid +a_no_irq_no_ack" UM v0.3.0 Common,Constraints,Privilege Modes,CLIC interrupts only support machine mode,"Assert that clic_irq_priv_i[1:0] is always 2'b11 -Assume on input for formal",Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,Constraints,NMI,"NMI address is located at the 15th entry in the machine trap vector table, located at mtvec. In other words, nmi_addr = { mtvec[31:7], 5'b0_1111, 2'b00 }","Assert that nmi addr = { mtvec[31:7], 5'b0_1111, 2'b00 }",Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,Constraints,Interrupts,Support up to a maximum of 1024 CLIC interrupts,Assert that SMCLIC_ID_WIDTH is inside { 1 .. 10 },Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,Constraints,Interrupts,"Interrupt levels inside { 0, 2 .. 255 }",Correct functionality of interrupts of all valid levels,Check against RM,Constrained-Random,Functional Coverage, -UM v0.3.0 Common,Constraints,Input ports,irq_i[31:0] tied to zero,Assert that non-clic irq[31:0] signals are tied to 0,Assertion Check,"ENV capability, not specific test",Functional Coverage, -Silabs Internal,Eventually taken,Interrupt taken,"An interrupt that is both pending and enabled shall be taken, unless if the core is in debug mode or is blocked by external interfaces (rvalid, fence_flush_ack, etc), and the taking happens within a fixed number of cycles","Check that when conditions are right, then the interrupt gets taken within expected time",Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,Interrupt interface,Level sensitive,All interrupt lines are level-sensitive,All assertions and modeling of interrupts for checking assume no edges required to qualify an interrupt,Any/All,"ENV capability, not specific test",N/A, -Silabs Internal,Interrupt interface,Interrupt ack pulse,Interrupt acknowledge is always a pulse,Assert that irq_ack is always a pulse,Assertion Check,"ENV capability, not specific test",Functional Coverage, -Silabs Internal,Interrupt interface,Interrupt ack valid,Interrupt acknowledge is only asserted when a valid interrupt has been taken by the core,irq_ack never asserted unless core has taken an interrupt,Assertion Check,"ENV capability, not specific test",Functional Coverage, -Silabs Internal,Interrupt interface,NMI,NMI not reported on irq_ack,"Check that after an NMI is triggered, if there is no other interrupt occuring, then there should be no irq_ack",Assertion Check,"ENV capability, not specific test",Functional Coverage, -Silabs Internal,Interrupt Interface,Interrupt ID is valid,Interrupt valid ID matches the active interrupt during the cycle where interrupt acknowledge is asserted,Ensure that irq_id is the active interrupt when irq_ack is asserted,Assertion Check,"ENV capability, not specific test",Functional Coverage, -Silabs Internal,Interrupt Interface,Interrupt ID is never reserved,"Interrupt valid ID during interrupt acknowledge is never a reserved interrupt [15,14,13,12,10,9,8,6,5,4,2,1,0]",Assert irq_id is not a reserved valid when irq_ack is asserted,Assertion Check,"ENV capability, not specific test",Functional Coverage, -Silabs Internal,Interrupt Interface,Single interrupt ack per ISR,Interrupt acknowledge only asserted once per interrupt,irq_ack only asserts once for an interrupt service period,Assertion Check,"ENV capability, not specific test",Functional Coverage, -Silabs internal,Interrupt interface,RVFI,Every irq_ack must be followed by a corresponding rvfi_intr,"Check that whenever and irq_ack occurs, then the next rvfi retired instruction must have rvfi interrupt set correctly",Assertion Check,"ENV capability, not specific test",Functional Coverage, +Assume on input for formal",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_clic_mode_only +UM v0.3.0 Common,Constraints,NMI,"NMI address is located at the 15th entry in the machine trap vector table, located at mtvec. In other words, nmi_addr = { mtvec[31:7], 5'b0_1111, 2'b00 }","Assert that nmi addr = { mtvec[31:7], 5'b0_1111, 2'b00 }",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_nmi_to_mtvec_offset +UM v0.3.0 Common,Constraints,Interrupts,Support up to a maximum of 1024 CLIC interrupts,Assert that SMCLIC_ID_WIDTH is inside { 1 .. 10 },Assertion Check,"ENV capability, not specific test",Functional Coverage,a_clic_valid_setting +UM v0.3.0 Common,Constraints,Interrupts,Interrupt levels inside { 0 .. 255 },Correct functionality of interrupts of all valid levels,Check against RM,Constrained-Random,Functional Coverage,"Missing covergroup, vc should use all interrupt levels" +UM v0.3.0 Common,Constraints,Input ports,irq_i[31:0] tied to zero,Assert that non-clic irq[31:0] signals are tied to 0,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_tieoff_zero_irq_i +Silabs Internal,Eventually taken,Interrupt taken,"An interrupt that is both pending and enabled shall be taken, unless if the core is in debug mode or is blocked by external interfaces (rvalid, fence_flush_ack, etc), and the taking happens within a fixed number of cycles","Check that when conditions are right, then the interrupt gets taken within expected time",Assertion Check,"ENV capability, not specific test",Functional Coverage,"Waived on top level verification due to lack of visibility and precise specification of what prevents interrupts from being taken, and there exist no definite bound. + +Design assertion: +Core_i.gen_clic_interrupt.clic_int_controller_i.clic_int_controller.sva.a_clic_enable" +UM v0.3.0 Common,Interrupt interface,Level sensitive,All interrupt lines are level-sensitive,All assertions and modeling of interrupts for checking assume no edges required to qualify an interrupt,Any/All,"ENV capability, not specific test",N/A,N/A +Silabs Internal,Interrupt interface,Interrupt ack pulse,Interrupt acknowledge is always a pulse,Assert that irq_ack is always a pulse,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_irq_ack_is_always_single_cycle_pulse +Silabs Internal,Interrupt interface,Interrupt ack valid,Interrupt acknowledge is only asserted when a valid interrupt has been taken by the core,irq_ack never asserted unless core has taken an interrupt,Assertion Check,"ENV capability, not specific test",Functional Coverage,"a_irq_ack_valid +a_no_irq_no_ack" +Silabs Internal,Interrupt interface,NMI,NMI not reported on irq_ack,"Check that after an NMI is triggered, if there is no other interrupt occuring, then there should be no irq_ack",Assertion Check,"ENV capability, not specific test",Functional Coverage,"Waived - Ideally would like to have an assertion for this case, but it is not possible to separate cases on rvfi where the taken interrupts handler is interrupted by nmi, and thus appears to have an ack caused by nmi. + +a_no_irq_no_ack should suffice to prove that we do not take an interrupt without an actual pending interrupt." +Silabs Internal,Interrupt Interface,Interrupt ID is valid,Interrupt valid ID matches the active interrupt during the cycle where interrupt acknowledge is asserted,Ensure that irq_id is the active interrupt when irq_ack is asserted,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mintstatus_updated_on_isr_handler_entry +Silabs Internal,Interrupt Interface,Interrupt ID is never reserved,"Interrupt valid ID during interrupt acknowledge is never a reserved interrupt [15,14,13,12,10,9,8,6,5,4,2,1,0]",Assert irq_id is not a reserved valid when irq_ack is asserted,Assertion Check,"ENV capability, not specific test",Functional Coverage,This is not a CLIC requirement +Silabs Internal,Interrupt Interface,Single interrupt ack per ISR,Interrupt acknowledge only asserted once per interrupt,irq_ack only asserts once for an interrupt service period,Assertion Check,"ENV capability, not specific test",Functional Coverage,"Implied proof by + +a_irq_ack_is_always_single_cycle_pulse (single pulse only) + +a_irq_ack_valid (must be higher priority and enabled) + +a_no_irq_no_ack (must never happen unless higher pri and enabled)" +Silabs internal,Interrupt interface,RVFI,Every irq_ack must be followed by a corresponding rvfi_intr,"Check that whenever and irq_ack occurs, then the next rvfi retired instruction must have rvfi interrupt set correctly",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_every_ack_followed_by_rvfi_intr Silabs Internal,Interrupt CSR,mclicbase,12 least significant bits hardwired to zero,"Assert mclicbase[11:0] = 0 -Note: This register will possibly be removed in the future",Assertion Check,"ENV capability, not specific test",functional Coverage, -CLIC 8675ec,Interrupt CSR,mstatus.mpp,mstatus.mpp accessible through mcause.mpp,Read/Write mpp to mcause.mpp and read back through mstatus.mpp,Self Checking Test,Directed Self-Checking,Testcase, -CLIC 8675ec,Interrupt CSR,mcause.mpp,mcause.mpp accessible through mstatus.mpp,Read/Write mpp to mstatus.mpp and read back through mcause.mpp,Self Checking Test,Directed Self-Checking,Testcase, -CLIC 8675ec,Interrupt CSR,mstatus.mpie,mstatus.mpie accessible through mcause.mpie,Read/Write mpp to mcause.mpie and read back through mstatus.mpie,Self Checking Test,Directed Self-Checking,Testcase, -CLIC 8675ec,Interrupt CSR,mcause.mpie,mcause.mpie accessible through mstatus.mpie,Read/Write mpp to mstatus.mpie and read back through mcause.mpie,Self Checking Test,Directed Self-Checking,Testcase, -CLIC 8675ec,Interrupt CSR,mie,mie not used and hardwired to zero,Assert that mie always appears as hardwired 0,Assertion Check,"ENV capability, not specific test",Functional Coverage, -CLIC 8675ec,Interrupt CSR,mie,Writes to mie should not trap,Attempt writes to mie and ensure that 0 is read back,Self Checking Test,Directed Self-Checking,Testcase, -CLIC 8675ec,Interrupt CSR,mip,mip not used and hardwired to zero,Assert that mip always appears as hardwired 0,Assertion Check,"ENV capability, not specific test",Functional Coverage, -CLIC 8675ec,Interrupt CSR,mip,Writes should not trap,Attempt writes to mip and ensure that 0 is read back,Self Checking Test,Directed Self-Checking,Testcase, -UM v0.3.0 Common,Interrupt CSR,mtvec,Always aligned to 128 bytes,Assert that mtvec[6:2] always zero,Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,Interrupt CSR,mtvec,Always in CLIC mode (I.e. model can not switch between interrupt modes),Assert that mtvec.mode is always 2'b11 when CLIC is enabled,Assertion Check,"ENV capability, not specific test",Functional Coverage, -Silabs Internal,Interrupt CSR,mtvt,Memory writes to the vector table require an instruction barrier (fence.i) to guarantee that they are visible to the instruction fetch.,Verify that a fence.i instruction after writes to the vector table guarantees that the new vector table pointer taken matches the latest pointer written to the vector table.,Assertion Check,"ENV capability, not specific test",Functional Coverage, +Note: This register will possibly be removed in the future",Assertion Check,"ENV capability, not specific test",functional Coverage,"Outdated req, CSR removed" +CLIC 8675ec,Interrupt CSR,mstatus.mpp,mstatus.mpp accessible through mcause.mpp,Read/Write mpp to mcause.mpp and read back through mstatus.mpp,Self Checking Test,Directed Self-Checking,Testcase,"clic :: w_mcause_mpp_r_mstatus_mpp +clic :: w_mstatus_mpp_r_mcause_mpp" +CLIC 8675ec,Interrupt CSR,mcause.mpp,mcause.mpp accessible through mstatus.mpp,Read/Write mpp to mstatus.mpp and read back through mcause.mpp,Self Checking Test,Directed Self-Checking,Testcase,"clic :: w_mcause_mpp_r_mstatus_mpp +clic :: w_mstatus_mpp_r_mcause_mpp" +CLIC 8675ec,Interrupt CSR,mstatus.mpie,mstatus.mpie accessible through mcause.mpie,Read/Write mpp to mcause.mpie and read back through mstatus.mpie,Self Checking Test,Directed Self-Checking,Testcase,"clic :: w_mcause_mpie_r_mstatus_mpie +clic :: w_mstatus_mpie_r_mcause_mpie" +CLIC 8675ec,Interrupt CSR,mcause.mpie,mcause.mpie accessible through mstatus.mpie,Read/Write mpp to mstatus.mpie and read back through mcause.mpie,Self Checking Test,Directed Self-Checking,Testcase,"clic :: w_mcause_mpie_r_mstatus_mpie +clic :: w_mstatus_mpie_r_mcause_mpie" +CLIC 8675ec,Interrupt CSR,mie,mie not used and hardwired to zero,Assert that mie always appears as hardwired 0,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mie_unused_hardcode_zero +CLIC 8675ec,Interrupt CSR,mie,Writes to mie should not trap,Attempt writes to mie and ensure that 0 is read back,Self Checking Test,Directed Self-Checking,Testcase,w_mie_notrap_r_zero +CLIC 8675ec,Interrupt CSR,mip,mip not used and hardwired to zero,Assert that mip always appears as hardwired 0,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mip_unused_hardcode_zero +CLIC 8675ec,Interrupt CSR,mip,Writes should not trap,Attempt writes to mip and ensure that 0 is read back,Self Checking Test,Directed Self-Checking,Testcase,w_mip_notrap_r_zero +UM v0.3.0 Common,Interrupt CSR,mtvec,Always aligned to 128 bytes,Assert that mtvec[6:2] always zero,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mtvec_aligned_to_128_bytes +UM v0.3.0 Common,Interrupt CSR,mtvec,Always in CLIC mode (I.e. model can not switch between interrupt modes),Assert that mtvec.mode is always 2'b11 when CLIC is enabled,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mtvec_mode_always_clic +Silabs Internal,Interrupt CSR,mtvt,Memory writes to the vector table require an instruction barrier (fence.i) to guarantee that they are visible to the instruction fetch.,Verify that a fence.i instruction after writes to the vector table guarantees that the new vector table pointer taken matches the latest pointer written to the vector table.,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_fencei_guarantee_visible_mtvt_write CLIC 8675ec,Interrupt CSR,mtvt,"Function ptr reads treated as instruction fetch, adhering to configured PMA settings (CV32E40S): PMP settings apply as for any other instruction fetch","Assert that interrupts accessing the vector table pointers do so through the instruction interface, and that a lack of PMP execute and PMA main-memory settings causes the instruction fetch to fail. Note, instruction fetch is treated as an implicit read, thus do not require PMP read permissions, but execute permission is required. -Both the pointer fetch and the fetch of the actual instruction located at the pointer address should be covered by the above restrictions. ",Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,Interrupt CSR,mtvt,"Always aligned to 2^(max(6, 2+SMCLIC_ID_WIDTH)","Assert that mtvt [max(6, 2+SMCLIC_ID_WIDTH)-1:0] = 0",Assertion Check,"ENV capability, not specific test",Functional Coverage, +Both the pointer fetch and the fetch of the actual instruction located at the pointer address should be covered by the above restrictions. ",Assertion Check,"ENV capability, not specific test",Functional Coverage,TODO: Directed clic test should add case to test this +UM v0.3.0 Common,Interrupt CSR,mtvt,"Always aligned to 2^(max(6, 2+SMCLIC_ID_WIDTH)","Assert that mtvt [max(6, 2+SMCLIC_ID_WIDTH)-1:0] = 0",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mtvt_alignment_correct CLIC 8675ec,Interrupt CSR,mtvt,"Determine alignment by software access, -Write ones to lower order bits and read back",Test that correct alignment can be inferred by writing to these fields and read back.,Self Checking Test,Directed Self-Checking,Testcase, +Write ones to lower order bits and read back",Test that correct alignment can be inferred by writing to these fields and read back.,Self Checking Test,Directed Self-Checking,Testcase,clic :: w_mtvt_rd_alignment CLIC 8675ec,Interrupt CSR,mepc,The CSR mepc is set to the PC of the interrupted application code or preempted interrupt handler,"Ensure that MEPC in ISR is value of saved PC. -",Assertion Check,"ENV capability, not specific test",Functional Coverage, -Risc-V Priv. 1.12,Interrupt CSR,mcause,mcause.interrupt flag always set during ISR regardless of the active interrupt,mcause[31] is set when an interrupt is taken,Assertion Check,"ENV capability, not specific test",Functional Coverage, -CLIC 8675ec,Interrupt CSR,mcause,mcause.exccode is set to the active interrupt code,mcause.exccode reflects the taken interrupt,Assertion Check,"ENV capability, not specific test",Functional Coverage, -CLIC 8675ec,Interrupt CSR,mcause,mcause.mpil: Previous interrupt level,mpil reflects the previous privilege level,Assertion Check,"ENV capability, not specific test",Functional Coverage, -CLIC 8675ec,Interrupt CSR,mcause,mcause.mpp: Previous privilege mode,Ensure that mcause.mpp reflects mstatus.mpp previous privilege mode after taking a trap,Assertion Check,"ENV capability, not specific test",Functional Coverage, -CLIC 8675ec,Interrupt CSR,mcause,mcause.mpie: Previous interrupt enable,Ensure that mcause.mpie reflects mstatus.mpie previous interrupt enable value after taking a trap,Assertion Check,"ENV capability, not specific test",Functional Coverage, +",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mepc_set_correct_after_irq +Risc-V Priv. 1.12,Interrupt CSR,mcause,mcause.interrupt flag always set during ISR regardless of the active interrupt,mcause[31] is set when an interrupt is taken,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mcause_interupt_always_set_on_taken_irq +CLIC 8675ec,Interrupt CSR,mcause,mcause.exccode is set to the active interrupt code,mcause.exccode reflects the taken interrupt,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mcause_exccode_always_set_correctly_on_taken_irq +CLIC 8675ec,Interrupt CSR,mcause,mcause.mpil: Previous interrupt level,mpil reflects the previous privilege level,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mcause_mpil_reflects_previous_interrupt_lvl +CLIC 8675ec,Interrupt CSR,mcause,mcause.mpp: Previous privilege mode,Ensure that mcause.mpp reflects mstatus.mpp previous privilege mode after taking a trap,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mcause_mpp_reflects_previous_privilege_mode +CLIC 8675ec,Interrupt CSR,mcause,mcause.mpie: Previous interrupt enable,Ensure that mcause.mpie reflects mstatus.mpie previous interrupt enable value after taking a trap,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mcause_mpie_reflects_previous_interrupt_enable CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: Case 1: ""The II is still the ranking interrupt (no change). In this case, as the level of the II will still be higher than pil from the OIC, xil and exccode will be rewritten with the same value that they already had (effectively unchanged), and xnxti will return the table entry for the II."" (II: Initital interrupt, -OIC: Original interrupted context)",Assert that mnxti returns the table entry for the initial interrupt when the current interrupt is still being signalled to the core as the highest enabled and pending interrupt.,Assertion Check,"ENV capability, not specific test",Functional Coverage, +OIC: Original interrupted context)",Assert that mnxti returns the table entry for the initial interrupt when the current interrupt is still being signalled to the core as the highest enabled and pending interrupt.,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mnxti_case_1_irq_req_unchanged CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: Case 2: -""The II has been superceded by a higher-level non-SHV interrupt. In this case, xil will be set to the new higher interrupt level, exccode will be updated to the new interrupt id, and xnxti will return the vector table entry for the new higher-level interrupt. The OIC is not disturbed, retaining the original epc and the original pil. This case reduces latency to service a more-important interrupt that arrives after the state-save sequence was begun for the less-important II. The II, if still pending-enabled, will be serviced sometime after the higher-level interrupt as described below.""","Assert that mnxti returns the table entry for the new higher-level interrupt when the current interrupt is being interrupted by a higher level, non-shv interrupt",Assertion Check,"ENV capability, not specific test",Functional Coverage, +""The II has been superceded by a higher-level non-SHV interrupt. In this case, xil will be set to the new higher interrupt level, exccode will be updated to the new interrupt id, and xnxti will return the vector table entry for the new higher-level interrupt. The OIC is not disturbed, retaining the original epc and the original pil. This case reduces latency to service a more-important interrupt that arrives after the state-save sequence was begun for the less-important II. The II, if still pending-enabled, will be serviced sometime after the higher-level interrupt as described below.""","Assert that mnxti returns the table entry for the new higher-level interrupt when the current interrupt is being interrupted by a higher level, non-shv interrupt",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mnxti_case_2_replaced_by_higher_level_non_shv_irq CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: Case 3: ""The II has been superceded by a higher-priority non-SHV interrupt at the same level. This operates similarly to the previous case, with exccode updated to the new interrupt id. Because the lower-priority interrupt had not begun to run its service routine, this optimization preserves the property that interrupt handlers at the same interrupt level but different priorities execute atomically with respect to each other (i.e., they do not preempt each other).""","Only machine mode interrupts are supported, an interrupt of the same level but higher priority cannot occur -",N/A,N/A,N/A, +",N/A,N/A,N/A,N/A - cannot take assertions in U-mode CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: Case 4: -""The II has disappeared and a lower-ranked non-SHV interrupt, which has interrupt level greater than the OIC’s pil is present in CLIC. In this case, the xil of the handler will be reduced to the lower-ranked interrupt’s level, exccode will be updated with the new interrupt id, and xnxti will return a pointer to the appropriate handler in table. In this case, the new lower-ranked interrupt would still have caused the original context to have been interrupted to run the handler, and the disappearing II has simply caused the lower-ranked interrupt’s entry and state-save sequence to begin earlier.""","Assert that mnxti returns the table entry for the new lower-level interrupt when the current interrupt is no longer present in the CLIC, and replaced by a new lower-leveled interrupt, with a greater interrupt level than the original interrupted context's pil",Assertion Check,"ENV capability, not specific test",Functional Coverage, +""The II has disappeared and a lower-ranked non-SHV interrupt, which has interrupt level greater than the OIC’s pil is present in CLIC. In this case, the xil of the handler will be reduced to the lower-ranked interrupt’s level, exccode will be updated with the new interrupt id, and xnxti will return a pointer to the appropriate handler in table. In this case, the new lower-ranked interrupt would still have caused the original context to have been interrupted to run the handler, and the disappearing II has simply caused the lower-ranked interrupt’s entry and state-save sequence to begin earlier.""","Assert that mnxti returns the table entry for the new lower-level interrupt when the current interrupt is no longer present in the CLIC, and replaced by a new lower-leveled interrupt, with a greater interrupt level than the original interrupted context's pil",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mnxti_case_4_replaced_by_lower_level_irq CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: Case 5: -""The II has disappeared and either there is no current interrupt from the CLIC, or the current ranking interrupt is a non-SHV interrupt with level lower than xpil. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. The following trampoline code will then not fetch a vector from the table, and instead just restore the OIC context and mret back to it. This preserves the property that the OIC completes execution before servicing any new interrupt with a lower or equal interrupt level.""","Ensure that mnxti returns 0 in case the initial interrupt is no longer signalled, nor replaced by a new interrupt from the CLIC",Assertion Check,"ENV capability, not specific test",Functional Coverage, +""The II has disappeared and either there is no current interrupt from the CLIC, or the current ranking interrupt is a non-SHV interrupt with level lower than xpil. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. The following trampoline code will then not fetch a vector from the table, and instead just restore the OIC context and mret back to it. This preserves the property that the OIC completes execution before servicing any new interrupt with a lower or equal interrupt level.""","Ensure that mnxti returns 0 in case the initial interrupt is no longer signalled, nor replaced by a new interrupt from the CLIC",Assertion Check,"ENV capability, not specific test",Functional Coverage,"a_mnxti_case_5_1_no_current_irq +a_mnxti_case_5_2_lvl_nonshv_pending" CLIC 8675ec,Interrupt CSR,mnxti,"mnxti read value after ISR is entered: Case 6: -""The II has been superceded by a higher-level SHV interrupt. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. Once interrupts are reenabled for the following instruction, the hart will preempt the current handler and execute the vectored interrupt at a higher interrupt level using the function pointer stored in the vector table.""",Assert that mnxti will return 0 in case of a higher-leveled SHV interrupt pending,Assertion Check,"ENV capability, not specific test",Functional Coverage, +""The II has been superceded by a higher-level SHV interrupt. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. Once interrupts are reenabled for the following instruction, the hart will preempt the current handler and execute the vectored interrupt at a higher interrupt level using the function pointer stored in the vector table.""",Assert that mnxti will return 0 in case of a higher-leveled SHV interrupt pending,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mnxti_case_6_higher_level_irq_superceed UM v0.9.0 Common,Interrupt CSR,mintstatus,"R/O CSR, Holds active interrupt level for each supported privilege mode","Assert that the mil field gets updated with the current interrupt level when an interrupt is taken, and that sil and uil-fields are hard-coded zero. -Note: NMIs explicitly leave ""mintstatus"" unchanged.",Assertion Check,"ENV capability, not specific test",Functional Coverage, +Note: NMIs explicitly leave ""mintstatus"" unchanged.",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_mintstatus_updated_on_isr_handler_entry UM v0.3.0 Common,CSR,CSR access,CSR registers should be accessible as defined in UM,"Add new CLIC-specific registers to CSR access tests and ensure that the registers and their fields can be read/written according to specification mtvt @@ -94,23 +111,43 @@ mscratchcsw mscratchcswl Note: ""mclicbase"" was removed. -Note: ""mintstatus"" got moved.",Self Checking Test,Directed Self-Checking,Testcase, -CLIC 8675ec,Interrupt CSR,Hardware vectoring,mcause.minhv: Set at start of hw vectoring,Assert that mcause.minhv is set when a hw-vectored interrupt is taken,Assertion Check,Constrained-Random,Functional Coverage, -CLIC 8675ec,Interrupt CSR,Hardware vectoring,mcause.minhv: Cleared at end of hw vectoring,Assert that mcause.minhv is cleared when pointer fetch of hw-vectored interrupt is taken successfully,Assertion Check,Constrained-Random,Functional Coverage, +Note: ""mintstatus"" got moved.",Self Checking Test,Directed Self-Checking,Testcase,"clic :: r_mnxti_without_irq +clic :: rw_mnxti_without_irq_legal +clic :: r_mnxti_with_pending_irq +clic :: r_mnxti_with_lower_lvl_pending_irq +clic :: w_mnxti_side_effects +clic :: rw_mscratchcsw +clic :: rw_mscratchcsw_illegal +clic :: rw_mscratchcswl +clic :: rw_mscratchcswl_illegal + +mintthresh write implicitly tested by +clic :: mintthresh_higher +clic :: mintthresh_equal +clic :: mintthresh_lower +and compared with ISS + +mintstatus read implicitly tested by +clic :: w_mnxti_side_effects" +CLIC 8675ec,Interrupt CSR,Hardware vectoring,mcause.minhv: Set at start of hw vectoring,Assert that mcause.minhv is set when a hw-vectored interrupt is taken,Assertion Check,Constrained-Random,Functional Coverage,"a_mcause_minhv_set_at_failing_ptr_fetch +a_mcause_minhv_set_valid +a_mcause_minhv_clear_valid" +CLIC 8675ec,Interrupt CSR,Hardware vectoring,mcause.minhv: Cleared at end of hw vectoring,Assert that mcause.minhv is cleared when pointer fetch of hw-vectored interrupt is taken successfully,Assertion Check,Constrained-Random,Functional Coverage,Waived - Outdated requirement CLIC 8675ec,Interrupt Vector,Hardware vectoring,"Exception on fetch: mepc : set to faulting address (pointer, rather than address for an instruction) mcause: exception type","Write invalid (not pointing to a valid instruction or a region with pmp restricted execute access) pointer to the mtvt table, and trigger this handler. -",Check against RM,Directed Non-Self-Checking,Testcase, -Silabs Internal,Interrupt Vector,Hardware vectoring,Prefetcher: no prefetches between pointer fetch and fetch of final vectored target,Assert that no new instructions get fetched that does not match the final vectored target after a pointer fetch is attempted,Assertion Check,"ENV capability, not specific test",Functional Coverage, +",Check against RM,Directed Non-Self-Checking,Testcase,clic :: invalid_mtvt_ptr_exec +Silabs Internal,Interrupt Vector,Hardware vectoring,Prefetcher: no prefetches between pointer fetch and fetch of final vectored target,Assert that no new instructions get fetched that does not match the final vectored target after a pointer fetch is attempted,Assertion Check,"ENV capability, not specific test",Functional Coverage,Waived - No RVFI visibility CLIC 8675ec,Interrupt Vector,Hardware vectoring,Interrupt executes trap handler function pointer located at the address specified in mtvt when shv = 1,"Assert that first pc after a taken, shv interrupt always matches address fetched from mtvt -",Assertion Check,"ENV capability, not specific test",Functional Coverage, -CLIC 8675ec,Interrupt Vector,Hardware vectoring,Interrupt jumps to common code at mtvec when shv = 0,Assert that first pc after a taken non-shv interrupt matches ,Assertion Check,"ENV capability, not specific test",Functional Coverage, +",Assertion Check,"ENV capability, not specific test",Functional Coverage,"a_pc_to_mtvt_for_taken_shv_interrupt_outstanding_obi +a_pc_to_mtvt_for_taken_shv_interrupt" +CLIC 8675ec,Interrupt Vector,Hardware vectoring,Interrupt jumps to common code at mtvec when shv = 0,Assert that first pc after a taken non-shv interrupt matches ,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_pc_to_mtvec_for_taken_nonshv_interrupt UM v0.3.0 Common,Interrupt Vector,PC,"non-shv: taken trap handler always has address[6:0] = 0; implied by mtvec alignment restriction","Assert that first pc after a taken, non-shv interrupt always has bits [6:0] = 0 -",Assertion Check,"ENV capability, not specific test",Functional Coverage, +",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_pc_alignment_of_taken_non_shv_interrupt CLIC 8675ec,Interrupt arbitration,Interrupts ignored,"Interrupts ignored when new privilege mode (nP) lower than current privilege mode (P)","Not allowed, assuming clic_irq_priv_i always = 2'b11 -Covered by assertion that asserts that clic_irq_priv_i is always 2'b11 in sim and assumed in formal",N/A,N/A,N/A, +Covered by assertion that asserts that clic_irq_priv_i is always 2'b11 in sim and assumed in formal",N/A,N/A,N/A,N/A - cannot take assertions in U-mode CLIC 8675ec,Interrupt arbitration,Interrupts ignored,"Interrupts ignored when new privilege mode (nP) = current privilege mode(P) and new interrupt level (nL) != 0 and nL < current interrupt level (L)","During constrained random testing, the following should be true @@ -123,11 +160,13 @@ clic_irq_lvl > 0 and < current level clic_irq_priv_i = 2'b11 assumed always true clic_irq_shv_i = random 0 .. 1 -Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage, +Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage,a_no_irq_no_ack CLIC 8675ec,Interrupt arbitration,Interupts disabled,"Interrupts disabled when mtatus.mie and clicintie[i] = 0","mstatus.mie = 0 should disallow any pending and enabled interrupts from being taken as we only have one level where interrupts can be taken (M-mode), so no other higher modes exist -Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage, +Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage,"clicintie is external to core, only mstatus.mie fans in to core assertions/tests + +a_no_irq_no_ack" CLIC 8675ec,Interrupt arbitration,No interrupt,"No interrupt when new privilege mode (nP) = current privilege mode (P) clic.level = 0 @@ -143,7 +182,7 @@ clic_irq_lvl = 0 clic_irq_priv_i = 2'b11 assumed always true clic_irq_shv_i = random 0 .. 1 -Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage, +Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage,a_no_irq_no_ack CLIC 8675ec,Interrupt arbitration,No interrupt,"No interrupt when new privilege mode (nP) > current privilege mode (P) clic.level = 0 @@ -160,7 +199,7 @@ clic_irq_lvl = 0 clic_irq_priv_i = 2'b11 assumed always true clic_irq_shv_i = random 0 .. 1 -Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage, +Check that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt",Check against RM,Constrained-Random,Functional Coverage,a_no_irq_no_ack CLIC 8675ec,Interrupt arbitration,"Horizontal interrupt taken (Nested)","Horizontal interrupt taken when mtatus.mie and clicintie[i] = 1 @@ -178,7 +217,7 @@ clic_irq_priv_i = 2'b11 assumed always true clic_irq_shv_i = random 0 .. 1 Check that an interrupt that should be taken under the given circumstances always get taken -Check that system behaves correctly when a pending and enabled interrupt gets taken",Check against RM,Constrained-Random,Functional Coverage, +Check that system behaves correctly when a pending and enabled interrupt gets taken",Check against RM,Constrained-Random,Functional Coverage,a_irq_ack_valid CLIC 8675ec,Interrupt arbitration,Vertical interrupt taken,"Vertical interrupt taken when new privilege mode (nP) > current privilege mode (P) new privilege level (nL) > 0 @@ -196,7 +235,7 @@ clic_irq_priv_i = 2'b11 assumed always true clic_irq_shv_i = random 0 .. 1 Check that an interrupt that should be taken under the given circumstances always gets taken -Check that the system behaves correctly when a pending and enabled interrupt gets taken",Check against RM,Constrained-Random,Functional Coverage, +Check that the system behaves correctly when a pending and enabled interrupt gets taken",Check against RM,Constrained-Random,Functional Coverage,a_irq_ack_valid CLIC 8675ec,Interrupt arbitration,Interrupt taken,"mstatus.mie = 1 nP = P = M nL > L @@ -204,9 +243,10 @@ nL > L or nP > P (i.e. nP = M, P = U) -nL > 0",Assert that an interrupt is taken if and only if any of the two conditions are true,Assertion Check,"ENV capability, not specific test",Assertion Coverage, -CLIC 8675ec,Interrupt preemption,mintthresh,Higher level interrupts than mintthresh.th can preempt execution,Assert that interrupts with the same privilege mode and higher privilege level than the running ISR can interrupt the currently running ISR,Assertion Check,"ENV capability, not specific test",Assertion Coverage, -CLIC 8675ec,Interrupt preemption,mintthresh,Lower level interrupts than mintthresh.th cannot preempt execution,Assert that interrupts with the same privilege mode and lower privilege level than the running ISR cannot interrupt the currently running ISR,Assertion Check,"ENV capability, not specific test",Assertion Coverage, +nL > 0",Assert that an interrupt is taken if and only if any of the two conditions are true,Assertion Check,"ENV capability, not specific test",Assertion Coverage,"a_irq_ack_valid +a_no_irq_no_ack" +CLIC 8675ec,Interrupt preemption,mintthresh,Higher level interrupts than mintthresh.th can preempt execution,Assert that interrupts with the same privilege mode and higher privilege level than the running ISR can interrupt the currently running ISR,Assertion Check,"ENV capability, not specific test",Assertion Coverage,a_higher_lvl_than_mintthresh_th_can_preempt +CLIC 8675ec,Interrupt preemption,mintthresh,Lower level interrupts than mintthresh.th cannot preempt execution,Assert that interrupts with the same privilege mode and lower privilege level than the running ISR cannot interrupt the currently running ISR,Assertion Check,"ENV capability, not specific test",Assertion Coverage,a_lower_lvl_than_mintthresh_th_cannot_preempt CLIC 8675ec,WFI resume,Resumes,"when nP > P interrupt is highest among pending-and-enabled interrupts @@ -217,7 +257,7 @@ nP = M, P = U (CV32E40S)","clic_irq_i = 1 clic_irq_lvl > 0 P = U -nP = M",Check against RM,Constrained-Random,Functional Coverage, +nP = M",Check against RM,Constrained-Random,Functional Coverage,a_wfi_wfe_wakeup_condition_valid CLIC 8675ec,WFI resume,Resumes,"when nP = P interrupt is highest among pending-and-enabled interrupts @@ -228,16 +268,17 @@ nP, P = M","clic_irq_i = 1 clic_irq_lvl > max(mintstatus.mil, mintthresh.th) P, nP = M -Test that only interrupts with a sufficiently high interrupt level are able to preempt execution with both true or temporarily risen interrupt level",Check against RM,Constrained-Random,Functional Coverage, +Test that only interrupts with a sufficiently high interrupt level are able to preempt execution with both true or temporarily risen interrupt level",Check against RM,Constrained-Random,Functional Coverage,a_wfi_wfe_wakeup_condition_valid CLIC 8675ec,WFI resume,Resumes,"nP < P interrupt is highest among pending-and-enabled interrupts i.level != 0 Can not occur 40S/40X as new privilege mode signalled on the CLIC interface can never be less than current privilege mode","nP < P cannot occur as we assume clic_irq_lvl = 2'b11 -No test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs",N/A,N/A,N/A, -CLIC 8675ec,WFI resume,Ignores,Everything not covered above,Core does not resume operation unless any of the above resume conditions are true,Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,Interrupt instruction,Killed instructions have no side-effects,"When an instruction is interrupted, it is killed, meaning that it has no side-effects: 1) load/store instructions don't reach the bus, 2) control transfer instructions don't jump, 3) CSRs don't get updated, 4) GPRs don't get updated","Check that bus, jumps, and registers are unaffected by killed instructions",Check against RM,"ENV capability, not specific test",Functional Coverage, +No test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs",N/A,N/A,N/A,a_wfi_wfe_wakeup_condition_valid +CLIC 8675ec,WFI resume,Ignores,Everything not covered above,Core does not resume operation unless any of the above resume conditions are true,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_wfi_wfe_wakeup_condition_not_valid +UM v0.3.0 Common,Interrupt instruction,Killed instructions have no side-effects,"When an instruction is interrupted, it is killed, meaning that it has no side-effects: 1) load/store instructions don't reach the bus, 2) control transfer instructions don't jump, 3) CSRs don't get updated, 4) GPRs don't get updated","Check that bus, jumps, and registers are unaffected by killed instructions",Check against RM,"ENV capability, not specific test",Functional Coverage," +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq" CLIC 8675ec,Return from handler,mret,"Execution continues at Privilege mode = mcause.mpp pc = mepc @@ -246,7 +287,7 @@ global interrupt enable mie = mcause.mpie mcause.mpil unchanged mcause.mpp = least privileged mode -mcause.mpie = 1",Correct update of CSR values when core returns from an ISR,Check against RM,Constrained-Random,Functional Coverage, +mcause.mpie = 1",Correct update of CSR values when core returns from an ISR,Check against RM,Constrained-Random,Functional Coverage,Covered by assertions below CLIC 8675ec,Return from handler,mret,"Execution continues at P = mcause.mpp pc = mepc @@ -256,157 +297,217 @@ ie = mcause.mpie mcause.mpil unchanged mcause.mpp = least privileged mode mcause.mpie = 1","Correct update of CSR values when core returns from an ISR -Added assertion for formal coverage",Assertion Check,"ENV capability, not specific test",Functional Coverage, +Added assertion for formal coverage",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.clic_assert_i.gen_clic_assertions.a_mret_pc_intended, +[clic_assert].a_mret_pc_not_vectored, +[clic_assert].a_mret_mode_mpp, +[clic_assert].a_mret_mil_mpil, +[clic_assert].a_mret_mil_mpil_intended, +[clic_assert].a_mret_mie_mpie" CLIC 0.9-draft 4/11/2023,Return from handler,mret,"""If the hart is currently running at some privilege mode x, an MRET or SRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.""","Use ""mret"" to enter U-mode. -Check that ""mintthresh"" is written to zero upon executing the mret.",Assertion Check,"ENV capability, not specific test",Assertion Coverage, +Check that ""mintthresh"" is written to zero upon executing the mret.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.clic_assert_i.gen_clic_assertions.a_mret_umode_clear_mintthresh CLIC 0.9-draft 4/11/2023,Return from debug mode,dret,"""Likewise, if the RISC-V debug specification is implemented and the hart is currently running at some privilege mode x, a DRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.""","Use ""dret"" to enter U-mode. -Check that ""mintthresh"" is written to zero upon executing the dret.",Assertion Check,"ENV capability, not specific test",Assertion Coverage, +Check that ""mintthresh"" is written to zero upon executing the dret.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,Requirement removed CLIC 8675ec,WFI,Wakeup conditions,"A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i • has a higher privilege mode than the current privilege mode and • the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and -• the interrupt i level is not equal to 0.",Test that interrupts of higher privilege modes than the current privilege mode can wakeup the core from wfi,Check against RM,Constrained-Random,Functional Coverage, +• the interrupt i level is not equal to 0.",Test that interrupts of higher privilege modes than the current privilege mode can wakeup the core from wfi,Check against RM,Constrained-Random,Functional Coverage,a_wfi_wfe_wakeup_condition_valid CLIC 8675ec,WFI,Wakeup conditions,"A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i • has the same privilege mode as the current privilege mode and • the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and - • the interrupt i level is greater than max(xintstatus.xil, xintthresh.th )",Test that interrupts of higher privilege level than the current privilege level can wake the core from WFI,Check against RM,Constrained-Random,Functional Coverage, + • the interrupt i level is greater than max(xintstatus.xil, xintthresh.th )",Test that interrupts of higher privilege level than the current privilege level can wake the core from WFI,Check against RM,Constrained-Random,Functional Coverage,a_wfi_wfe_wakeup_condition_valid CLIC 8675ec,WFI,Wakeup conditions,"A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i • has a lower privilege mode than the current privilege mode and • the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and • the interrupt i level is not equal to 0.","nP < P cannot occur as we assume clic_irq_lvl = 2'b11 -No test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs",N/A,N/A,N/A, -CLIC 8675ec,WFI,Wakeup conditions,Core only wakes up if any of the conditions mentioned above is true,Assert that core remains in WFI mode unless correct wakeup conditions occur,Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,WFI ,Entry,Execution of WFI causes the core to stop,In normal execution the core stop within a certain time period after execution.,Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,WFI ,Clock gating,WFI entry causes the clock to be gated,The core is not clocked during WFI,Assertion Check,"ENV capability, not specific test",Functional Coverage, -UM v0.3.0 Common,WFI ,Output signal,core_sleep_o output signal is only asserted during active WFI,Assert the proper operation of core_sleep_o,Assertion Check,"ENV capability, not specific test",Functional Coverage, +No test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs",N/A,N/A,N/A,a_wfi_wfe_wakeup_condition_valid +CLIC 8675ec,WFI,Wakeup conditions,Core only wakes up if any of the conditions mentioned above is true,Assert that core remains in WFI mode unless correct wakeup conditions occur,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_wfi_wfe_wakeup_condition_not_valid +UM v0.3.0 Common,WFI ,Entry,Execution of WFI causes the core to stop,In normal execution the core stop within a certain time period after execution.,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_wfi_wfe_causes_core_to_stop +UM v0.3.0 Common,WFI ,Clock gating,WFI entry causes the clock to be gated,The core is not clocked during WFI,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_wfi_wfe_causes_clock_gating +UM v0.3.0 Common,WFI ,Output signal,core_sleep_o output signal is only asserted during active WFI,Assert the proper operation of core_sleep_o,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_core_sleep_o_only_during_wfi_wfe CLIC 8675ec,Synchronous exception handling,Horizontal synchronous exception traps,Serviced at same privilege mode with same interrupt level as instruction that raised exception ,"Assert that interrupt level is not changed when entering the exception handler -(Can only occur in machine mode)",Assertion Check,"ENV capability, not specific test",Functional Coverage, +(Can only occur in machine mode)",Assertion Check,"ENV capability, not specific test",Functional Coverage,a_horizontal_exception_service CLIC 8675ec,Synchronous exception handling,Vertical synchronous exception traps,"Serviced at higher privilege mode at interrupt level 0 in the higher privilege mode -(CV32E40S)",Assert that user mode traps are taken in machine mode with interrupt level 0,Assertion Check,"ENV capability, not specific test",Functional Coverage, +(CV32E40S)",Assert that user mode traps are taken in machine mode with interrupt level 0,Assertion Check,"ENV capability, not specific test",Functional Coverage,a_vertical_exception_service UM v0.3.0 Common,Trap priority,Interrupt + WFI,Proper interactions between interrupts and WFI,"Corner case -Test random combinations of streams containing WFI-instructions with random interrupt requests",Check against RM,Constrained-Random,Functional Coverage, +Test random combinations of streams containing WFI-instructions with random interrupt requests",Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_wfi +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_wfi" UM v0.3.0 Common,Trap priority,Interrupt + Back to back WFI,Correct interactions between interrupts and back-to-back WFI instructions,"Corner case -In embedded context WFI is used often, ensure that WFI can be re-entered ASAP after servicing a ISR for a previous WFI",Check against RM,Constrained-Random,Functional Coverage, +In embedded context WFI is used often, ensure that WFI can be re-entered ASAP after servicing a ISR for a previous WFI",Check against RM,Constrained-Random,Functional Coverage," +Should apply to both wfi and wfe, the following tests use back to back wfe and wfi-instructions + randomly toggled interrupts/wfe-pin. +wfe_test :: wfe_wakeup_umode +wfe_test :: wfe_wakeup +wfe_test :: wfi_mstatus_tw_umode_illegal + +TODO: covergroups" UM v0.3.0 Common,Trap priority,Interrupt + Debug,Correct interaction between interrupts and debug,"Corner case Test random streams of instructions interrupted by debug and random interrupt requests. Goal is to verify that interrupts are never taken in debug mode, and that interrupt- and debug transitions are handled correctly -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Interrupt + Exceptions,Correct interaction between interrupts and exceptions,"Corner case Test random streams of instructions interrupted by exceptions and random interrupt requests. Generated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten) -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Interrupt + Bus Error,Correct interaction between interrupts and bus errors,"Corner case Test random streams of instructions interrupted by random interrupt requests and random bus errors. Aims to verify that interrupts and bus errors are correctly prioritized by the system. -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Interrupt + Debug + Bus Error,"Correct interaction between interrupts, debug and bus errors ","Corner case Test random streams of instructions, -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Interrupt + Debug + WFI,"Correct interaction between interrupts, debug and WFI ","Test random instruction streams containing WFI, where control flow changes occur due to random debug requests and random interrupts -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Interrupt + Debug + WFI + Bus Error,"Correct interaction between interrupts, debug, wfi and bus errors","Test random instruction streams containing WFI instructions, where control flow changes occur due to random debug requests, random bus errors, random interrupts -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Interrupt + Debug + WFI + Bus Error + Exceptions,Correct interaction between all trap sources,"Trap priority stress test Test random streams containing all trap sources to verify correct behavior -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Nested Interrupts,Correct interactions between nested interrupts,"Verify potential corner case Implement nested ISR. Randomly modify mintthresh.th to mask out certain interrupts and randomly trigger new interrupts with higher or lower priority to verify that interrupts with a higher privilege level are allowed to preempt -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Nested Interrupts + exceptions,Correct interactions between nested interrupts and exceptions,"Verify potential corner case Same as nested interrupts, but random streams include randomly inserted exception-causing instructions Generated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten) -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Nested interrupts + Debug,Correct interactions between nested interrupts and debug,"Verify potential corner case Same as nested interrupts, but random streams also gets control flow modified by random debug requests. -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Nested Interrupts + Debug + Bus Error," Correct interactions between nested inteerrupts, debug and bus-errors","Verify potential corner case Same as nested interrupts with debug, but also includes random bus errors -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Nested interrupts + Debug + WFI,"Correct interactions between nested interrupts, debug and WFI","Verify potential corner case Same as nested interrupts with debug, but the instruction stream should also include WFI instructions. -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account UM v0.3.0 Common,Trap priority,Nested interrupts + Debug + WFI + Bus Error + Exceptions,Correct interactions between nested interrupts and all other trap types,"Verify potential corner case Test nested interrupts with randomly traps (all types) Generated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten) -Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 32-bit Load instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 32-bit Store instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 32-bit Shift instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 32-bit logical instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 32-bit compare instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 32-bit jump instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 32-bit FENCE instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 32-bit system instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Nontaken BEQ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Taken BEQ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Nontaken BNE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Taken BNE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Nontaken BLT instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Taken BLT instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Nontaken BGE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Taken BGE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Nontaken BLTU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Taken BLTU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Nontaken BGEU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Taken BGEU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 16-bit load instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 16-bit store instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 16-bit arithmetic instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 16-bit shift instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 16-bit jump instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All 16-bit system instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Nontaken C.BEQZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Taken C.BEQZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Nontaken C.BNEZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Taken C.BNEZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All RV32 M instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zba instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zbb instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zbc instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zbs instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zicsr instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zifencei instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zc instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +Note, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.",Check against RM,Constrained-Random,Functional Coverage,TODO: Expect this to be covered by assertions taking correct priority into account +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit Load instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit Store instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit Shift instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit logical instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit compare instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit jump instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit FENCE instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 32-bit system instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq + +Missing: ecall, csrrwi, csrrc" +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BEQ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Taken BEQ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BNE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Taken BNE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BLT instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Taken BLT instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BGE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Taken BGE instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BLTU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Taken BLTU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Nontaken BGEU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Taken BGEU instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit load instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq + +Missing: c.lw" +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit store instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit arithmetic instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq + +See below, coverage model does not support Zcb, cmp, cmt" +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit shift instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit jump instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All 16-bit system instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,Nontaken C.BEQZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Taken C.BEQZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Nontaken C.BNEZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,Taken C.BNEZ instruction interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"Needs coverage model update, currently taken/not taken is not tracked +" +Risc-V Priv. 1.12,Interrupt instruction,All RV32 M instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zba instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zbb instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zbc instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zbs instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zicsr instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq + +Missing: csrrwi, csrrc" +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zifencei instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zc instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,"uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq +uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq + +Missing: c.lw, c.addi16sp, c.addi4spn" Risc-V Priv. 1.12,Interrupt instruction,"All RV32 Zca instructions interrupted -",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,Awaiting isacov update Risc-V Priv. 1.12,Interrupt instruction,"All RV32 Zcb instructions interrupted -",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,Awaiting isacov update Risc-V Priv. 1.12,Interrupt instruction,"All RV32 Zcmb instructions interrupted -",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,Awaiting isacov update Risc-V Priv. 1.12,Interrupt instruction,"All RV32 Zcmt instructions interrupted -",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zcmp instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, -Risc-V Priv. 1.12,Interrupt instruction,Illegal instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,Awaiting isacov update +Risc-V Priv. 1.12,Interrupt instruction,All RV32 Zcmp instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,Awaiting isacov update +Risc-V Priv. 1.12,Interrupt instruction,Illegal instructions interrupted,A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,Missing covergroup Risc-V Priv. 1.12,Interrupt instruction,"All RV32 A instructions interrupted -(CV32E40X)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +(CV32E40X)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,Missing covergroup Risc-V Priv. 1.12,Interrupt instruction,"All X interface instructions interrupted -(CV32E40X)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +(CV32E40X)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,N/A Risc-V Priv. 1.12,Interrupt instruction,"All RV32F instructions interrupted -(CV32E40X XIF only if supported)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +(CV32E40X XIF only if supported)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,N/A Risc-V Priv. 1.12,Interrupt instruction,"All RV32 P instructions interrupted -(CV32E40X XIF only if supported)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +(CV32E40X XIF only if supported)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,N/A Risc-V Priv. 1.12,Interrupt instruction,"All RV32V instructions interrupted -(CV32E40X XIF only if supported)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage, +(CV32E40X XIF only if supported)",A specific instruction is interrupted properly,Randomness check on interrupts versus instruction stream,Check against RM,Constrained-Random,Functional Coverage,N/A ,,,,,,,, ,,,,,,,, ,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json new file mode 100644 index 0000000000..31fe7aaf06 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.json @@ -0,0 +1,1663 @@ +[ + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Reset behavior", + "Sub Feature": "CSR reset value", + "Feature Description": "mintstatus.mil resets to 0", + "Verification Goal": "CSR value check after reset\n\nDo not implement in initial-block to include formal checking", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mintstatus_mil_reset_to_zero" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Reset behavior", + "Sub Feature": "CSR reset value", + "Feature Description": "mstatus.mie resets to 0\n", + "Verification Goal": "CSR value check after reset\n\nDo not implement in initial-block to include formal checking", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mstatus_mie_reset_to_zero" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Reset behavior", + "Sub Feature": "CSR reset value", + "Feature Description": "mtvec resets to {mtvec_addr_i[31:7]. 5'b0_0000, 2'b11}", + "Verification Goal": "Assert that mtvec resets to the correct initialization value", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mtvec_reset_value_correct" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Reset behavior", + "Sub Feature": "Interrupts never enabled out of reset", + "Feature Description": "mstatus.mie resets to 0", + "Verification Goal": "Assert that interrupts are disabled and never taken immediately after deasserting reset", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mstatus_mie_reset_to_zero\na_irq_ack_valid\na_no_irq_no_ack" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Privilege Modes", + "Feature Description": "CLIC interrupts only support machine mode", + "Verification Goal": "Assert that clic_irq_priv_i[1:0] is always 2'b11\nAssume on input for formal", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_clic_mode_only" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "NMI", + "Feature Description": "NMI address is located at the 15th entry in the machine trap vector table, located at mtvec. In other words, nmi_addr = { mtvec[31:7], 5'b0_1111, 2'b00 }", + "Verification Goal": "Assert that nmi addr = { mtvec[31:7], 5'b0_1111, 2'b00 }", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_nmi_to_mtvec_offset" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Interrupts", + "Feature Description": "Support up to a maximum of 1024 CLIC interrupts", + "Verification Goal": "Assert that SMCLIC_ID_WIDTH is inside { 1 .. 10 }", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_clic_valid_setting" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Interrupts", + "Feature Description": "Interrupt levels inside { 0 .. 255 }", + "Verification Goal": "Correct functionality of interrupts of all valid levels", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Missing covergroup, vc should use all interrupt levels" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Constraints", + "Sub Feature": "Input ports", + "Feature Description": "irq_i[31:0] tied to zero", + "Verification Goal": "Assert that non-clic irq[31:0] signals are tied to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_tieoff_zero_irq_i" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Eventually taken", + "Sub Feature": "Interrupt taken", + "Feature Description": "An interrupt that is both pending and enabled shall be taken, unless if the core is in debug mode or is blocked by external interfaces (rvalid, fence_flush_ack, etc), and the taking happens within a fixed number of cycles", + "Verification Goal": "Check that when conditions are right, then the interrupt gets taken within expected time", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Waived on top level verification due to lack of visibility and precise specification of what prevents interrupts from being taken, and there exist no definite bound. \n\nDesign assertion:\nCore_i.gen_clic_interrupt.clic_int_controller_i.clic_int_controller.sva.a_clic_enable" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt interface", + "Sub Feature": "Level sensitive", + "Feature Description": "All interrupt lines are level-sensitive", + "Verification Goal": "All assertions and modeling of interrupts for checking assume no edges required to qualify an interrupt", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt interface", + "Sub Feature": "Interrupt ack pulse", + "Feature Description": "Interrupt acknowledge is always a pulse", + "Verification Goal": "Assert that irq_ack is always a pulse", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_irq_ack_is_always_single_cycle_pulse" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt interface", + "Sub Feature": "Interrupt ack valid", + "Feature Description": "Interrupt acknowledge is only asserted when a valid interrupt has been taken by the core", + "Verification Goal": "irq_ack never asserted unless core has taken an interrupt", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_irq_ack_valid\na_no_irq_no_ack" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt interface", + "Sub Feature": "NMI", + "Feature Description": "NMI not reported on irq_ack", + "Verification Goal": "Check that after an NMI is triggered, if there is no other interrupt occuring, then there should be no irq_ack", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Waived - Ideally would like to have an assertion for this case, but it is not possible to separate cases on rvfi where the taken interrupts handler is interrupted by nmi, and thus appears to have an ack caused by nmi. \n\na_no_irq_no_ack should suffice to prove that we do not take an interrupt without an actual pending interrupt." + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Interface", + "Sub Feature": "Interrupt ID is valid", + "Feature Description": "Interrupt valid ID matches the active interrupt during the cycle where interrupt acknowledge is asserted", + "Verification Goal": "Ensure that irq_id is the active interrupt when irq_ack is asserted", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mintstatus_updated_on_isr_handler_entry" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Interface", + "Sub Feature": "Interrupt ID is never reserved", + "Feature Description": "Interrupt valid ID during interrupt acknowledge is never a reserved interrupt [15,14,13,12,10,9,8,6,5,4,2,1,0]", + "Verification Goal": "Assert irq_id is not a reserved valid when irq_ack is asserted", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "This is not a CLIC requirement" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Interface", + "Sub Feature": "Single interrupt ack per ISR", + "Feature Description": "Interrupt acknowledge only asserted once per interrupt", + "Verification Goal": "irq_ack only asserts once for an interrupt service period", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Implied proof by\n\na_irq_ack_is_always_single_cycle_pulse (single pulse only) +\na_irq_ack_valid (must be higher priority and enabled) +\na_no_irq_no_ack (must never happen unless higher pri and enabled)" + }, + { + "Requirement Location": "Silabs internal", + "Feature": "Interrupt interface", + "Sub Feature": "RVFI", + "Feature Description": "Every irq_ack must be followed by a corresponding rvfi_intr", + "Verification Goal": "Check that whenever and irq_ack occurs, then the next rvfi retired instruction must have rvfi interrupt set correctly", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_every_ack_followed_by_rvfi_intr" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt CSR", + "Sub Feature": "mclicbase", + "Feature Description": "12 least significant bits hardwired to zero", + "Verification Goal": "Assert mclicbase[11:0] = 0 \n\nNote: This register will possibly be removed in the future", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "functional Coverage", + "Link to Coverage": "Outdated req, CSR removed" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mstatus.mpp", + "Feature Description": "mstatus.mpp accessible through mcause.mpp", + "Verification Goal": "Read/Write mpp to mcause.mpp and read back through mstatus.mpp", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "clic :: w_mcause_mpp_r_mstatus_mpp\nclic :: w_mstatus_mpp_r_mcause_mpp" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause.mpp", + "Feature Description": "mcause.mpp accessible through mstatus.mpp", + "Verification Goal": "Read/Write mpp to mstatus.mpp and read back through mcause.mpp", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "clic :: w_mcause_mpp_r_mstatus_mpp\nclic :: w_mstatus_mpp_r_mcause_mpp" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mstatus.mpie", + "Feature Description": "mstatus.mpie accessible through mcause.mpie", + "Verification Goal": "Read/Write mpp to mcause.mpie and read back through mstatus.mpie", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "clic :: w_mcause_mpie_r_mstatus_mpie\nclic :: w_mstatus_mpie_r_mcause_mpie" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause.mpie", + "Feature Description": "mcause.mpie accessible through mstatus.mpie", + "Verification Goal": "Read/Write mpp to mstatus.mpie and read back through mcause.mpie", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "clic :: w_mcause_mpie_r_mstatus_mpie\nclic :: w_mstatus_mpie_r_mcause_mpie" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mie", + "Feature Description": "mie not used and hardwired to zero", + "Verification Goal": "Assert that mie always appears as hardwired 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mie_unused_hardcode_zero" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mie", + "Feature Description": "Writes to mie should not trap", + "Verification Goal": "Attempt writes to mie and ensure that 0 is read back", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "w_mie_notrap_r_zero" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mip", + "Feature Description": "mip not used and hardwired to zero", + "Verification Goal": "Assert that mip always appears as hardwired 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mip_unused_hardcode_zero" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mip", + "Feature Description": "Writes should not trap", + "Verification Goal": "Attempt writes to mip and ensure that 0 is read back", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "w_mip_notrap_r_zero" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvec", + "Feature Description": "Always aligned to 128 bytes", + "Verification Goal": "Assert that mtvec[6:2] always zero", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mtvec_aligned_to_128_bytes" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvec", + "Feature Description": "Always in CLIC mode (I.e. model can not switch between interrupt modes)", + "Verification Goal": "Assert that mtvec.mode is always 2'b11 when CLIC is enabled", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mtvec_mode_always_clic" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Memory writes to the vector table require an instruction barrier (fence.i) to guarantee that they are visible to the instruction fetch.", + "Verification Goal": "Verify that a fence.i instruction after writes to the vector table guarantees that the new vector table pointer taken matches the latest pointer written to the vector table.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_fencei_guarantee_visible_mtvt_write" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Function ptr reads treated as instruction fetch, adhering to configured PMA settings \n(CV32E40S): PMP settings apply as for any other instruction fetch", + "Verification Goal": "Assert that interrupts accessing the vector table pointers do so through the instruction interface, and that a lack of PMP execute and PMA main-memory settings causes the instruction fetch to fail.\n\nNote, instruction fetch is treated as an implicit read, thus do not require PMP read permissions, but execute permission is required.\n\nBoth the pointer fetch and the fetch of the actual instruction located at the pointer address should be covered by the above restrictions. ", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Directed clic test should add case to test this" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Always aligned to 2^(max(6, 2+SMCLIC_ID_WIDTH)", + "Verification Goal": "Assert that mtvt [max(6, 2+SMCLIC_ID_WIDTH)-1:0] = 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mtvt_alignment_correct" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mtvt", + "Feature Description": "Determine alignment by software access,\nWrite ones to lower order bits and read back", + "Verification Goal": "Test that correct alignment can be inferred by writing to these fields and read back.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "clic :: w_mtvt_rd_alignment" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mepc", + "Feature Description": "The CSR\u00a0mepc\u00a0is set to the PC of the interrupted application code or preempted interrupt handler", + "Verification Goal": "Ensure that MEPC in ISR is value of saved PC.\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mepc_set_correct_after_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.interrupt flag always set during ISR regardless of the active interrupt", + "Verification Goal": "mcause[31] is set when an interrupt is taken", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mcause_interupt_always_set_on_taken_irq" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.exccode is set to the active interrupt code", + "Verification Goal": "mcause.exccode reflects the taken interrupt", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mcause_exccode_always_set_correctly_on_taken_irq" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.mpil: Previous interrupt level", + "Verification Goal": "mpil reflects the previous privilege level", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mcause_mpil_reflects_previous_interrupt_lvl" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.mpp: Previous privilege mode", + "Verification Goal": "Ensure that mcause.mpp reflects mstatus.mpp previous privilege mode after taking a trap", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mcause_mpp_reflects_previous_privilege_mode" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mcause", + "Feature Description": "mcause.mpie: Previous interrupt enable", + "Verification Goal": "Ensure that mcause.mpie reflects mstatus.mpie previous interrupt enable value after taking a trap", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mcause_mpie_reflects_previous_interrupt_enable" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 1:\n\"The II is still the ranking interrupt (no change). In this case, as the level of the II will still be higher than pil from the OIC, xil and exccode will be rewritten with the same value that they already had (effectively unchanged), and xnxti will return the table entry for the II.\"\n\n(II: Initital interrupt,\nOIC: Original interrupted context)", + "Verification Goal": "Assert that mnxti returns the table entry for the initial interrupt when the current interrupt is still being signalled to the core as the highest enabled and pending interrupt.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mnxti_case_1_irq_req_unchanged" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 2:\n\"The II has been superceded by a higher-level non-SHV interrupt. In this case, xil will be set to the new higher interrupt level, exccode will be updated to the new interrupt id, and xnxti will return the vector table entry for the new higher-level interrupt. The OIC is not disturbed, retaining the original epc and the original pil. This case reduces latency to service a more-important interrupt that arrives after the state-save sequence was begun for the less-important II. The II, if still pending-enabled, will be serviced sometime after the higher-level interrupt as described below.\"", + "Verification Goal": "Assert that mnxti returns the table entry for the new higher-level interrupt when the current interrupt is being interrupted by a higher level, non-shv interrupt", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mnxti_case_2_replaced_by_higher_level_non_shv_irq" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 3: \n\"The II has been superceded by a higher-priority non-SHV interrupt at the same level. This operates similarly to the previous case, with exccode updated to the new interrupt id. Because the lower-priority interrupt had not begun to run its service routine, this optimization preserves the property that interrupt handlers at the same interrupt level but different priorities execute atomically with respect to each other (i.e., they do not preempt each other).\"", + "Verification Goal": "Only machine mode interrupts are supported, an interrupt of the same level but higher priority cannot occur\n", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "N/A - cannot take assertions in U-mode" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 4:\n\"The II has disappeared and a lower-ranked non-SHV interrupt, which has interrupt level greater than the OIC\u2019s pil is present in CLIC. In this case, the xil of the handler will be reduced to the lower-ranked interrupt\u2019s level, exccode will be updated with the new interrupt id, and xnxti will return a pointer to the appropriate handler in table. In this case, the new lower-ranked interrupt would still have caused the original context to have been interrupted to run the handler, and the disappearing II has simply caused the lower-ranked interrupt\u2019s entry and state-save sequence to begin earlier.\"", + "Verification Goal": "Assert that mnxti returns the table entry for the new lower-level interrupt when the current interrupt is no longer present in the CLIC, and replaced by a new lower-leveled interrupt, with a greater interrupt level than the original interrupted context's pil", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mnxti_case_4_replaced_by_lower_level_irq" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 5:\n\"The II has disappeared and either there is no current interrupt from the CLIC, or the current ranking interrupt is a non-SHV interrupt with level lower than xpil. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. The following trampoline code will then not fetch a vector from the table, and instead just restore the OIC context and mret back to it. This preserves the property that the OIC completes execution before servicing any new interrupt with a lower or equal interrupt level.\"", + "Verification Goal": "Ensure that mnxti returns 0 in case the initial interrupt is no longer signalled, nor replaced by a new interrupt from the CLIC", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mnxti_case_5_1_no_current_irq\na_mnxti_case_5_2_lvl_nonshv_pending" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "mnxti", + "Feature Description": "mnxti read value after ISR is entered:\n\nCase 6:\n\"The II has been superceded by a higher-level SHV interrupt. In this case, the xil and exccode are not updated, and 0 is returned by xnxti. Once interrupts are reenabled for the following instruction, the hart will preempt the current handler and execute the vectored interrupt at a higher interrupt level using the function pointer stored in the vector table.\"", + "Verification Goal": "Assert that mnxti will return 0 in case of a higher-leveled SHV interrupt pending", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mnxti_case_6_higher_level_irq_superceed" + }, + { + "Requirement Location": "UM v0.9.0 Common", + "Feature": "Interrupt CSR", + "Sub Feature": "mintstatus", + "Feature Description": "R/O CSR, Holds active interrupt level for each supported privilege mode", + "Verification Goal": "Assert that the mil field gets updated with the current interrupt level when an interrupt is taken, and that sil and uil-fields are hard-coded zero.\n\nNote: NMIs explicitly leave \"mintstatus\" unchanged.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mintstatus_updated_on_isr_handler_entry" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "CSR", + "Sub Feature": "CSR access", + "Feature Description": "CSR registers should be accessible as defined in UM", + "Verification Goal": "Add new CLIC-specific registers to CSR access tests and ensure that the registers and their fields can be read/written according to specification\n\nmtvt\nmnxti\nmintstatus\nmintthresh\nmscratchcsw\nmscratchcswl\n\nNote: \"mclicbase\" was removed.\nNote: \"mintstatus\" got moved.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "clic :: r_mnxti_without_irq\nclic :: rw_mnxti_without_irq_legal\nclic :: r_mnxti_with_pending_irq\nclic :: r_mnxti_with_lower_lvl_pending_irq\nclic :: w_mnxti_side_effects\nclic :: rw_mscratchcsw\nclic :: rw_mscratchcsw_illegal\nclic :: rw_mscratchcswl\nclic :: rw_mscratchcswl_illegal\n\nmintthresh write implicitly tested by \nclic :: mintthresh_higher\nclic :: mintthresh_equal\nclic :: mintthresh_lower\nand compared with ISS\n\nmintstatus read implicitly tested by\nclic :: w_mnxti_side_effects" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "Hardware vectoring", + "Feature Description": "mcause.minhv: Set at start of hw vectoring", + "Verification Goal": "Assert that mcause.minhv is set when a hw-vectored interrupt is taken", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_mcause_minhv_set_at_failing_ptr_fetch\na_mcause_minhv_set_valid\na_mcause_minhv_clear_valid" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt CSR", + "Sub Feature": "Hardware vectoring", + "Feature Description": "mcause.minhv: Cleared at end of hw vectoring", + "Verification Goal": "Assert that mcause.minhv is cleared when pointer fetch of hw-vectored interrupt is taken successfully", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Waived - Outdated requirement" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Exception on fetch:\nmepc : set to faulting address (pointer, rather than address for an instruction)\nmcause: exception type", + "Verification Goal": "Write invalid (not pointing to a valid instruction or a region with pmp restricted execute access) pointer to the mtvt table, and trigger this handler. \n", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "clic :: invalid_mtvt_ptr_exec" + }, + { + "Requirement Location": "Silabs Internal", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Prefetcher: no prefetches between pointer fetch and fetch of final vectored target", + "Verification Goal": "Assert that no new instructions get fetched that does not match the final vectored target after a pointer fetch is attempted", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Waived - No RVFI visibility" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Interrupt executes trap handler function pointer located at the address specified in mtvt when shv = 1", + "Verification Goal": "Assert that first pc after a taken, shv interrupt always matches address fetched from mtvt\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_pc_to_mtvt_for_taken_shv_interrupt_outstanding_obi\na_pc_to_mtvt_for_taken_shv_interrupt" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt Vector", + "Sub Feature": "Hardware vectoring", + "Feature Description": "Interrupt jumps to common code at mtvec when shv = 0", + "Verification Goal": "Assert that first pc after a taken non-shv interrupt matches ", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_pc_to_mtvec_for_taken_nonshv_interrupt" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt Vector", + "Sub Feature": "PC", + "Feature Description": "non-shv: taken trap handler always has address[6:0] = 0;\nimplied by mtvec alignment restriction", + "Verification Goal": "Assert that first pc after a taken, non-shv interrupt always has bits [6:0] = 0\n", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_pc_alignment_of_taken_non_shv_interrupt" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interrupts ignored", + "Feature Description": "Interrupts ignored when \nnew privilege mode (nP) lower than current privilege mode (P)", + "Verification Goal": "Not allowed, assuming clic_irq_priv_i always = 2'b11\nCovered by assertion that asserts that clic_irq_priv_i is always 2'b11 in sim and assumed in formal", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "N/A - cannot take assertions in U-mode" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interrupts ignored", + "Feature Description": "Interrupts ignored when \nnew privilege mode (nP) = current privilege mode(P) and new interrupt level (nL) != 0 and nL < current interrupt level (L)", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: M-mode\nInside interrupt handler (Nested)\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_irq_lvl > 0 and < current level\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_no_irq_no_ack" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interupts disabled", + "Feature Description": "Interrupts disabled when\nmtatus.mie and clicintie[i] = 0", + "Verification Goal": "mstatus.mie = 0 should disallow any pending and enabled interrupts from being taken as we only have one level where interrupts can be taken (M-mode), so no other higher modes exist\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "clicintie is external to core, only mstatus.mie fans in to core assertions/tests\n\na_no_irq_no_ack" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "No interrupt", + "Feature Description": "No interrupt when \nnew privilege mode (nP) = current privilege mode (P) \nclic.level = 0\n\nP, nP in M, U", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: M-mode (Cannot signal U-mode)\nTest in both nested and non-nested cases\n\nclic_irq_i = 1 \nclic_irq_id_i = random 0 .. max index\nclic_irq_lvl = 0\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_no_irq_no_ack" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "No interrupt", + "Feature Description": "No interrupt when \nnew privilege mode (nP) > current privilege mode (P)\nclic.level = 0\n\nnP = M, P = U, clic.level = 0\n(CV32E40S)", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: U-mode\nTest for both nested and non-nested cases\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_irq_lvl = 0\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that no inadvertent state/register change occurs from a pending, enabled but not taken interrupt", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_no_irq_no_ack" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Horizontal interrupt taken\n(Nested)", + "Feature Description": "Horizontal interrupt taken when\nmtatus.mie and clicintie[i] = 1\nnew privilege mode (nP) = current privilege mode (P)\nnew privilege level (nL) > current privilege level (L)\n\nOnly applicable for M-mode (P, nP = M) as horizontal user mode traps are not supported (N-extension) in neither CV32E40X nor S", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: M-mode (Cannot signal U-mode)\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_lvl > current_lvl\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that an interrupt that should be taken under the given circumstances always get taken\nCheck that system behaves correctly when a pending and enabled interrupt gets taken", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_irq_ack_valid" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Vertical interrupt taken", + "Feature Description": "Vertical interrupt taken when\nnew privilege mode (nP) > current privilege mode (P)\nnew privilege level (nL) > 0\n\nnP = M, P = U\n\n(CV32E40S)", + "Verification Goal": "During constrained random testing, the following should be true\n\nCurrent privilege mode: U-mode\n\nclic_irq_i = 1\nclic_irq_id_i = random 0 .. max_index\nclic_lvl > 0\nclic_irq_priv_i = 2'b11 assumed always true\nclic_irq_shv_i = random 0 .. 1\n\nCheck that an interrupt that should be taken under the given circumstances always gets taken\nCheck that the system behaves correctly when a pending and enabled interrupt gets taken", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_irq_ack_valid" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt arbitration", + "Sub Feature": "Interrupt taken", + "Feature Description": "mstatus.mie = 1\nnP = P = M\nnL > L\n\nor\n\nnP > P (i.e. nP = M, P = U)\nnL > 0", + "Verification Goal": "Assert that an interrupt is taken if and only if any of the two conditions are true", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "a_irq_ack_valid\na_no_irq_no_ack" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt preemption", + "Sub Feature": "mintthresh", + "Feature Description": "Higher level interrupts than mintthresh.th can preempt execution", + "Verification Goal": "Assert that interrupts with the same privilege mode and higher privilege level than the running ISR can interrupt the currently running ISR", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "a_higher_lvl_than_mintthresh_th_can_preempt" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Interrupt preemption", + "Sub Feature": "mintthresh", + "Feature Description": "Lower level interrupts than mintthresh.th cannot preempt execution", + "Verification Goal": "Assert that interrupts with the same privilege mode and lower privilege level than the running ISR cannot interrupt the currently running ISR", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "a_lower_lvl_than_mintthresh_th_cannot_preempt" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Resumes", + "Feature Description": "when \nnP > P\ninterrupt is highest among pending-and-enabled interrupts\ni.level != 0\n\nnP = M, P = U\n\n(CV32E40S)", + "Verification Goal": "clic_irq_i = 1\nclic_irq_lvl > 0\nP = U\nnP = M", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_wfi_wfe_wakeup_condition_valid" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Resumes", + "Feature Description": "when\nnP = P\ninterrupt is highest among pending-and-enabled interrupts\ni.level > max(xintstatus.xil, xintthresh.th)\n\n(xintthresh only applies to current privilege mode)\nnP, P = M", + "Verification Goal": "clic_irq_i = 1\nclic_irq_lvl > max(mintstatus.mil, mintthresh.th)\nP, nP = M\n\nTest that only interrupts with a sufficiently high interrupt level are able to preempt execution with both true or temporarily risen interrupt level", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_wfi_wfe_wakeup_condition_valid" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Resumes", + "Feature Description": "nP < P\ninterrupt is highest among pending-and-enabled interrupts\ni.level != 0\n\nCan not occur 40S/40X as new privilege mode signalled on the CLIC interface can never be less than current privilege mode", + "Verification Goal": "nP < P cannot occur as we assume clic_irq_lvl = 2'b11\n\nNo test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "a_wfi_wfe_wakeup_condition_valid" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI resume", + "Sub Feature": "Ignores", + "Feature Description": "Everything not covered above", + "Verification Goal": "Core does not resume operation unless any of the above resume conditions are true", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_wfi_wfe_wakeup_condition_not_valid" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Interrupt instruction", + "Sub Feature": "Killed instructions have no side-effects", + "Feature Description": "When an instruction is interrupted, it is killed, meaning that it has no side-effects: 1) load/store instructions don't reach the bus, 2) control transfer instructions don't jump, 3) CSRs don't get updated, 4) GPRs don't get updated", + "Verification Goal": "Check that bus, jumps, and registers are unaffected by killed instructions", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Return from handler", + "Sub Feature": "mret", + "Feature Description": "Execution continues at \nPrivilege mode = mcause.mpp\npc = mepc\ninterrupt level = mcause.mpil\nglobal interrupt enable mie = mcause.mpie\n\nmcause.mpil unchanged\nmcause.mpp = least privileged mode\nmcause.mpie = 1", + "Verification Goal": "Correct update of CSR values when core returns from an ISR", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Covered by assertions below" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Return from handler", + "Sub Feature": "mret", + "Feature Description": "Execution continues at \nP = mcause.mpp\npc = mepc\nL = mcause.mpil\nie = mcause.mpie\n\nmcause.mpil unchanged\nmcause.mpp = least privileged mode\nmcause.mpie = 1", + "Verification Goal": "Correct update of CSR values when core returns from an ISR\nAdded assertion for formal coverage", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.clic_assert_i.gen_clic_assertions.a_mret_pc_intended,\n[clic_assert].a_mret_pc_not_vectored, \n[clic_assert].a_mret_mode_mpp, \n[clic_assert].a_mret_mil_mpil, \n[clic_assert].a_mret_mil_mpil_intended, \n[clic_assert].a_mret_mie_mpie" + }, + { + "Requirement Location": "CLIC 0.9-draft 4/11/2023", + "Feature": "Return from handler", + "Sub Feature": "mret", + "Feature Description": "\"If the hart is currently running at some privilege mode x, an MRET or SRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.\"", + "Verification Goal": "Use \"mret\" to enter U-mode.\nCheck that \"mintthresh\" is written to zero upon executing the mret.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.clic_assert_i.gen_clic_assertions.a_mret_umode_clear_mintthresh" + }, + { + "Requirement Location": "CLIC 0.9-draft 4/11/2023", + "Feature": "Return from debug mode", + "Sub Feature": "dret", + "Feature Description": "\"Likewise, if the RISC-V debug specification is implemented and the hart is currently running at some privilege mode x, a DRET instruction that changes the privilege mode to a mode less privileged than x also sets xintthresh = 0.\"", + "Verification Goal": "Use \"dret\" to enter U-mode.\nCheck that \"mintthresh\" is written to zero upon executing the dret.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "Requirement removed" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i\n\u2022 has a higher privilege mode than the current privilege mode and\n\u2022 the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled\ninterrupts and\n\u2022 the interrupt i level is not equal to 0.", + "Verification Goal": "Test that interrupts of higher privilege modes than the current privilege mode can wakeup the core from wfi", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_wfi_wfe_wakeup_condition_valid" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i\n \u2022 has the same privilege mode as the current privilege mode and\n \u2022 the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and\n \u2022 the interrupt i level is greater than max(xintstatus.xil, xintthresh.th )", + "Verification Goal": "Test that interrupts of higher privilege level than the current privilege level can wake the core from WFI", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_wfi_wfe_wakeup_condition_valid" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "A pending-and-enabled interrupt i causes the hart to resume execution if interrupt i \n\u2022 has a lower privilege mode than the current privilege mode and \n\u2022 the interrupt priority reduction tree selects interrupt i as the maximum across all pending-and-enabled interrupts and \n\u2022 the interrupt i level is not equal to 0.", + "Verification Goal": "nP < P cannot occur as we assume clic_irq_lvl = 2'b11\n\nNo test/assertion applicable, should be covered by clic_irq_lvl assertion ensuring that an interrupt with irq_lvl != 2'b11 never occurs", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "a_wfi_wfe_wakeup_condition_valid" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "WFI", + "Sub Feature": "Wakeup conditions", + "Feature Description": "Core only wakes up if any of the conditions mentioned above is true", + "Verification Goal": "Assert that core remains in WFI mode unless correct wakeup conditions occur", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_wfi_wfe_wakeup_condition_not_valid" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "WFI ", + "Sub Feature": "Entry", + "Feature Description": "Execution of WFI causes the core to stop", + "Verification Goal": "In normal execution the core stop within a certain time period after execution.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_wfi_wfe_causes_core_to_stop" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "WFI ", + "Sub Feature": "Clock gating", + "Feature Description": "WFI entry causes the clock to be gated", + "Verification Goal": "The core is not clocked during WFI", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_wfi_wfe_causes_clock_gating" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "WFI ", + "Sub Feature": "Output signal", + "Feature Description": "core_sleep_o output signal is only asserted during active WFI", + "Verification Goal": "Assert the proper operation of core_sleep_o", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_core_sleep_o_only_during_wfi_wfe" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Synchronous exception handling", + "Sub Feature": "Horizontal synchronous exception traps", + "Feature Description": "Serviced at same privilege mode with same interrupt level as instruction that raised exception ", + "Verification Goal": "Assert that interrupt level is not changed when entering the exception handler\n(Can only occur in machine mode)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_horizontal_exception_service" + }, + { + "Requirement Location": "CLIC 8675ec", + "Feature": "Synchronous exception handling", + "Sub Feature": "Vertical synchronous exception traps", + "Feature Description": "Serviced at higher privilege mode at interrupt level 0 in the higher privilege mode\n\n(CV32E40S)", + "Verification Goal": "Assert that user mode traps are taken in machine mode with interrupt level 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "a_vertical_exception_service" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + WFI", + "Feature Description": "Proper interactions between interrupts and WFI", + "Verification Goal": "Corner case\n\nTest random combinations of streams containing WFI-instructions with random interrupt requests", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_wfi\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_wfi" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Back to back WFI", + "Feature Description": "Correct interactions between interrupts and back-to-back WFI instructions", + "Verification Goal": "Corner case\n\nIn embedded context WFI is used often, ensure that WFI can be re-entered ASAP after servicing a ISR for a previous WFI", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "\nShould apply to both wfi and wfe, the following tests use back to back wfe and wfi-instructions + randomly toggled interrupts/wfe-pin. \nwfe_test :: wfe_wakeup_umode\nwfe_test :: wfe_wakeup\nwfe_test :: wfi_mstatus_tw_umode_illegal\n\nTODO: covergroups" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug", + "Feature Description": "Correct interaction between interrupts and debug", + "Verification Goal": "Corner case\nTest random streams of instructions interrupted by debug and random interrupt requests.\nGoal is to verify that interrupts are never taken in debug mode, and that interrupt- and debug transitions are handled correctly\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Exceptions", + "Feature Description": "Correct interaction between interrupts and exceptions", + "Verification Goal": "Corner case\nTest random streams of instructions interrupted by exceptions and random interrupt requests.\nGenerated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten)\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Bus Error", + "Feature Description": "Correct interaction between interrupts and bus errors", + "Verification Goal": "Corner case\nTest random streams of instructions interrupted by random interrupt requests and random bus errors. Aims to verify that interrupts and bus errors are correctly prioritized by the system.\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + Bus Error", + "Feature Description": "Correct interaction between interrupts, debug and bus errors\n", + "Verification Goal": "Corner case\nTest random streams of instructions, \n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + WFI", + "Feature Description": "Correct interaction between interrupts, debug and WFI\n", + "Verification Goal": "Test random instruction streams containing WFI, where control flow changes occur due to random debug requests and random interrupts\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + WFI + Bus Error", + "Feature Description": "Correct interaction between interrupts, debug, wfi and bus errors", + "Verification Goal": "Test random instruction streams containing WFI instructions, where control flow changes occur due to random debug requests, random bus errors, random interrupts\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Interrupt + Debug + WFI + Bus Error + Exceptions", + "Feature Description": "Correct interaction between all trap sources", + "Verification Goal": "Trap priority stress test\nTest random streams containing all trap sources to verify correct behavior\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested Interrupts", + "Feature Description": "Correct interactions between nested interrupts", + "Verification Goal": "Verify potential corner case\n\nImplement nested ISR. Randomly modify mintthresh.th to mask out certain interrupts and randomly trigger new interrupts with higher or lower priority to verify that interrupts with a higher privilege level are allowed to preempt\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested Interrupts + exceptions", + "Feature Description": "Correct interactions between nested interrupts and exceptions", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts, but random streams include randomly inserted exception-causing instructions\nGenerated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten)\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested interrupts + Debug", + "Feature Description": "Correct interactions between nested interrupts and debug", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts, but random streams also gets control flow modified by random debug requests.\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested Interrupts + Debug + Bus Error", + "Feature Description": "\nCorrect interactions between nested inteerrupts, debug and bus-errors", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts with debug, but also includes random bus errors\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested interrupts + Debug + WFI", + "Feature Description": "Correct interactions between nested interrupts, debug and WFI", + "Verification Goal": "Verify potential corner case\nSame as nested interrupts with debug, but the instruction stream should also include WFI instructions.\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "UM v0.3.0 Common", + "Feature": "Trap priority", + "Sub Feature": "Nested interrupts + Debug + WFI + Bus Error + Exceptions", + "Feature Description": "Correct interactions between nested interrupts and all other trap types", + "Verification Goal": "Verify potential corner case\nTest nested interrupts with randomly traps (all types)\nGenerated exception code must take care to back up mepc, mcause when triggering exceptions to avoid corrupting program flow (these CSRs will be overwritten)\n\nNote, these potential corners are deliberately mentioned separately to be able to more easily pinpoint any bugs that may occur in regressions - thus ideally should be implemented with different tests.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "TODO: Expect this to be covered by assertions taking correct priority into account" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit Load instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit Store instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit Shift instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit logical instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit compare instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit jump instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit FENCE instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 32-bit system instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq\n\nMissing: ecall, csrrwi, csrrc" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BEQ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BEQ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BNE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BNE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BLT instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BLT instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BGE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BGE instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BLTU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BLTU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken BGEU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken BGEU instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit load instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq\n\nMissing: c.lw" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit store instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit arithmetic instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq\n\nSee below, coverage model does not support Zcb, cmp, cmt" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit shift instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit jump instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All 16-bit system instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken C.BEQZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken C.BEQZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Nontaken C.BNEZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Taken C.BNEZ instruction interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Needs coverage model update, currently taken/not taken is not tracked\n" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 M instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zba instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zbb instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zbc instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zbs instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zicsr instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq\n\nMissing: csrrwi, csrrc" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zifencei instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zc instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "uvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_entry.cp_irq\nuvm_pkg.uvm_test_top.env.cov_model.clic_covg.clic_irq_exit.cp_irq\n\nMissing: c.lw, c.addi16sp, c.addi4spn" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zca instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Awaiting isacov update" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcb instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Awaiting isacov update" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcmb instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Awaiting isacov update" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcmt instructions interrupted\n", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Awaiting isacov update" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 Zcmp instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Awaiting isacov update" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "Illegal instructions interrupted", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Missing covergroup" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 A instructions interrupted\n(CV32E40X)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "Missing covergroup" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All X interface instructions interrupted\n(CV32E40X)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "N/A" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32F instructions interrupted\n(CV32E40X XIF only if supported)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "N/A" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32 P instructions interrupted\n(CV32E40X XIF only if supported)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "N/A" + }, + { + "Requirement Location": "Risc-V Priv. 1.12", + "Feature": "Interrupt instruction", + "Sub Feature": "All RV32V instructions interrupted\n(CV32E40X XIF only if supported)", + "Feature Description": "A specific instruction is interrupted properly", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "N/A" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": "", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + }, + { + "Requirement Location": " ---- END ----", + "Feature": "Interrupt instruction", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Randomness check on interrupts versus instruction stream", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx old mode 100755 new mode 100644 index 46b4f09d99..73ee087bab Binary files a/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx and b/cv32e40s/docs/VerifPlans/Simulation/interrupts/CV32E40SX_CLIC.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.csv b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.csv index 8e80af5236..ff7710eac2 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.csv +++ b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.csv @@ -1,20 +1,20 @@ Requirement Location,Feature,Sub Feature,Feature Description,Verification Goal,Pass/Fail Criteria,Test Type,Coverage Method,Link to Coverage,Comment Riscv spec,StoresVisible,StoresVisible,"After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction.","Do a fencei, but right before the fencei do a store to the instruction following the fencei, then see that the newly stored value is executed instead of the old instruction (e.g. change addi to use a different immediate)",Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/ -COV: ???",TODO must be added to regression lists +COV: uvmt_cv32e40s_fencei_assert.sv, ""cov_stores_visible_store_fencei_exec"".", ,,,,"Do a fencei followed by any instruction, but let the environment detect when the fencei is being executed and change the memory holding the next instruction, then see that the old instruction is not executed",Check against RM,Directed Non-Self-Checking,Functional Coverage,"DTC: cv32e40s/tests/programs/custom/fencei/ -COV: ???",TODO missing cover +COV: (SKIPPED).","Cover skipped because of low reward/effort ratio, and because other testing is good enough." ,,,,"Let the instruction right before a fence.i write a different instruction to the address following the fence.i, then observe that the written instruction is executed instead of the original one and that no side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit instructions to force a noticable difference)",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/fencei/, -,,,,"Check that after having read one value from an address, then after storing a value to that same address, if executing that address then the value shall always be that which was written (should work well in both sim/formal)",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: ???,TODO missing assert. (Note was ignored because of the difficulty of writing this as an assert for fv.) +,,,,"Check that after having read one value from an address, then after storing a value to that same address, if executing that address then the value shall always be that which was written (should work well in both sim/formal)",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: (SKIPPED).,"Assertion skipped because +1) it makes little sense in formal, +2) the simulation tests handle this scenario." User manual,ExternalHandshake,ReqHigh,"When executing a fence.i instruction, fencei_flush_req_o shall rise sometime before executing the next instruction",Check that when executing a fence.i instruction there will be a rising req before has retired,Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_rise_before_retire, ,,ReqWaitLsu,"When executing a fence.i instruction, if there is an ongoing store instruction (not limited to rv32i) that has not completed (data_rvalid_i clocked in as 1), then fencei_flush_req_o shall be low","Make sure a store instruction is run right before a fence.i, and (possibly using obi stalls) ensure that the fence.i is pending retirement but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o was low until this point where it now goes high",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_bus -COV: ???",TODO missing cover -,,ReqWaitWritebuffer,"When executing a fence.i instruction, if the write buffer is not empty, then fencei_flush_req_o shall be low until the write buffer has been emptied and the corresponding data_rvalid_i have been clocked in as 1",Fill up the write buffer prior to executing a fence.i and ensure that fencei_flush_req_o holds off going high until the write buffer to has been emptied,Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_buffer - -COV: ???",TODO missing cover -,,ReqWaitXinterface,"When executing a fence.i instruction, if the X interface is busy with any store operations, then fencei_flush_req_o shall be low until all the store operations are done",Issue one or more store instructions that uses the X interface and ensure that fencei_flush_req_o waits until the stores have all completed before going high,Assertion Check,Constrained-Random,Functional Coverage,(Not relevant for the 40s), +COV: uvmt_cv32e40s_fencei_assert.sv, ""cov_req_wait_bus"".", +,,ReqWaitWritebuffer,"When executing a fence.i instruction, if the write buffer is not empty, then fencei_flush_req_o shall be low until the write buffer has been emptied and the corresponding data_rvalid_i have been clocked in as 1",Fill up the write buffer prior to executing a fence.i and ensure that fencei_flush_req_o holds off going high until the write buffer to has been emptied,Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_buffer, +,,ReqWaitXinterface,"When executing a fence.i instruction, if the X interface is busy with any store operations, then fencei_flush_req_o shall be low until all the store operations are done",Issue one or more store instructions that uses the X interface and ensure that fencei_flush_req_o waits until the stores have all completed before going high,Assertion Check,Constrained-Random,Functional Coverage,(Not relevant for the 40s),40x future! ,,ReqWaitObi,fencei_flush_req_o shall not go high while there are outstanding stores on the obi bus,Check vs the OBI monitors that there are no outstanding stores at the time fencei_flush_req_o goes high,Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_outstanding COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.gen_c_req_wait_outstanding_1.cov_req_wait_outstanding_1", @@ -37,22 +37,14 @@ User manual,Fetching,Fetching,Instruction data for the next PC must be fetched a User manual,MultiCycle,MultiCycle,"Given zero stalls on neither instr-side and data-side obi nor on fencei_flush_ack_i, then the execution of fence.i takes a fixed number of cycles.","Check that, given ideal conditions, the cycle count of fence.i is as expected",Assertion Check,"ENV capability, not specific test",Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_cycle_count_minimum, User manual,StoresComplete,StoresComplete,"Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted)","Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged)",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/fencei/, ,,,,,Check against RM,Constrained-Random,Testcase,RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/, -User manual,Flush,Flush,"When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually supressed","Check that a fence.i will cause flushing of the pipeline, prefetcher, write buffer, and data_req_o",Assertion Check,"ENV capability, not specific test",Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_supress_datareq - -A: ???",TODO missing assert. (Have not checked/covered that the pipeline/writebuffer content is actually purged. Or that any memory change WILL be the next instr word.) +User manual,Flush,Flush,"When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually supressed","Check that a fence.i will cause flushing of the: +1) pipeline, +2) prefetcher, +3) write buffer, +4) data_req_o.",Assertion Check,"ENV capability, not specific test",Assertion Coverage,"A: uvmt_cv32e40s_fencei_assert.sv, ""a_flush_pipeline"". + +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_supress_datareq","This is somewhat complex to check, so +1) the pipeline and prefetcher asserts use rvfi retires as a ""proxy"", and +2) the write buffer and data req asserts use only data req." Riscv spec,UnusedFields,UnusedFields,"imm[11:0], rs1, rd are reserved for future extensions, and implementations shall ignore them",Try giving random values in those fields and see that all else works as expected,Check against RM,Constrained-Random,Functional Coverage,COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.reserved_cg, ,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, -,,,,,,,,, - -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------,,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json new file mode 100644 index 0000000000..a992299b67 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.json @@ -0,0 +1,254 @@ +[ + { + "Requirement Location": "Riscv spec", + "Feature": "StoresVisible", + "Sub Feature": "StoresVisible", + "Feature Description": "After a fence.i instruction has been executed, all preceding store instructions shall have their effects visible to the instruction fetch of the instructions that are to be executed after the fence.i instruction.", + "Verification Goal": "Do a fencei, but right before the fencei do a store to the instruction following the fencei, then see that the newly stored value is executed instead of the old instruction (e.g. change addi to use a different immediate)", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/\n\nCOV: uvmt_cv32e40s_fencei_assert.sv, \"cov_stores_visible_store_fencei_exec\".", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "StoresVisible", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Do a fencei followed by any instruction, but let the environment detect when the fencei is being executed and change the memory holding the next instruction, then see that the old instruction is not executed", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/fencei/\n\nCOV: (SKIPPED).", + "Comment": "Cover skipped because of low reward/effort ratio, and because other testing is good enough." + }, + { + "Requirement Location": "", + "Feature": "StoresVisible", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Let the instruction right before a fence.i write a different instruction to the address following the fence.i, then observe that the written instruction is executed instead of the original one and that no side-effects (csr updates or otherwise) occur (can possibly mix 16bit/32bit instructions to force a noticable difference)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/fencei/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "StoresVisible", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that after having read one value from an address, then after storing a value to that same address, if executing that address then the value shall always be that which was written (should work well in both sim/formal)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: (SKIPPED).", + "Comment": "Assertion skipped because\n1) it makes little sense in formal,\n2) the simulation tests handle this scenario." + }, + { + "Requirement Location": "User manual", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqHigh", + "Feature Description": "When executing a fence.i instruction, fencei_flush_req_o shall rise sometime before executing the next instruction", + "Verification Goal": "Check that when executing a fence.i instruction there will be a rising req before has retired", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_rise_before_retire", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitLsu", + "Feature Description": "When executing a fence.i instruction, if there is an ongoing store instruction (not limited to rv32i) that has not completed (data_rvalid_i clocked in as 1), then fencei_flush_req_o shall be low", + "Verification Goal": "Make sure a store instruction is run right before a fence.i, and (possibly using obi stalls) ensure that the fence.i is pending retirement but holds off until the store's data_rvalid_i is clocked in and that fencei_flush_req_o was low until this point where it now goes high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_bus\n\nCOV: uvmt_cv32e40s_fencei_assert.sv, \"cov_req_wait_bus\".", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitWritebuffer", + "Feature Description": "When executing a fence.i instruction, if the write buffer is not empty, then fencei_flush_req_o shall be low until the write buffer has been emptied and the corresponding data_rvalid_i have been clocked in as 1", + "Verification Goal": "Fill up the write buffer prior to executing a fence.i and ensure that fencei_flush_req_o holds off going high until the write buffer to has been emptied", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_buffer", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitXinterface", + "Feature Description": "When executing a fence.i instruction, if the X interface is busy with any store operations, then fencei_flush_req_o shall be low until all the store operations are done", + "Verification Goal": "Issue one or more store instructions that uses the X interface and ensure that fencei_flush_req_o waits until the stores have all completed before going high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "(Not relevant for the 40s)", + "Comment": "40x future!" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqWaitObi", + "Feature Description": "fencei_flush_req_o shall not go high while there are outstanding stores on the obi bus", + "Verification Goal": "Check vs the OBI monitors that there are no outstanding stores at the time fencei_flush_req_o goes high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_wait_outstanding\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.gen_c_req_wait_outstanding_1.cov_req_wait_outstanding_1", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ReqLow", + "Feature Description": "When fencei_flush_req_o is high, it shall stay high until fencei_flush_req_o and fencei_flush_ack_i has been sampled high simultaneously, and then then it shall go low", + "Verification Goal": "Check that when fencei_flush_req_o is high, then it behaves correctly with regards to fencei_flush_ack_i", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_stay_high\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_drop_lo", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "AckChange", + "Feature Description": "fencei_flush_ack_i is allowed to change freely on any clock cycle: It can be permanently high, go high without fence.i and retract, go high at the same cycle as the req, it can delay arbitrarily after req and then go high, etc", + "Verification Goal": "Drive ack to test all permutations of rising/falling before/after/on req, acking without req, retracting an early ack, delaying ack after req, etc.", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.reqack_cg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "AckWithold", + "Feature Description": "If req is high, but ack never comes, then the core keeps on stalling and the fence.i is blocked from completing", + "Verification Goal": "Upon a req, try witholding ack for a long time and see that the fence.i can be stalled arbitrarily long (should have covers for ack delays of at least {[0:5]})", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_stall_until_ack\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.gen_ack_delayed[*].cov_ack_delayed", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "BranchInitiated", + "Feature Description": "After req and ack has been sampled simultaneously high and when req is low again, then the core takes a branch to the instruction after the fence.i instruction", + "Verification Goal": "Check that the branch is taken at the point after req and ack has been simultaneously high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_branch_after_retire\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_branch_after_retire", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "ExternalHandshake", + "Sub Feature": "ShadowingBranch", + "Feature Description": "If the fence.i ends up not retiring because it was preceeded by a taken branch or a jump, then the fencei_flush_req_o shall not go high", + "Verification Goal": "Take a branch or do a jump to skip a fence.i, and ensure that fencei_flush_req_o doesn't go high", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_req_must_retire\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_retire_without_req\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.cov_no_retire", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "Fetching", + "Sub Feature": "Fetching", + "Feature Description": "Instruction data for the next PC must be fetched after the fence.i instruction has executed (because only then can data-side stores have completed and caches have been updated)", + "Verification Goal": "Check that after a fence.i instruction retires then instr-side obi fetches the next instruction to be executed", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_fetch_after_retire", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "MultiCycle", + "Sub Feature": "MultiCycle", + "Feature Description": "Given zero stalls on neither instr-side and data-side obi nor on fencei_flush_ack_i, then the execution of fence.i takes a fixed number of cycles.", + "Verification Goal": "Check that, given ideal conditions, the cycle count of fence.i is as expected", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_cycle_count_minimum", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "StoresComplete", + "Sub Feature": "StoresComplete", + "Feature Description": "Any store instruction that is successfully executed before a fence.i will fully complete and have its effect visible (this is not about syncronization with instruction fetch, but rather seeing that the stores are not aborted)", + "Verification Goal": "Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged)", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/fencei/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "StoresComplete", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Check that all stores (either to next pc or other places) preceding a fence.i will complete on the bus (excluding exceptions/interrupts/etc) and be readable afterwards (particularly, ensure that the write buffer isn't just purged)", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Testcase", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_fencei/", + "Comment": "" + }, + { + "Requirement Location": "User manual", + "Feature": "Flush", + "Sub Feature": "Flush", + "Feature Description": "When fence.i is executed, then any prefetched instructions shall be flushed; meaning that pipeline stages are flushed, prefetcher is flushed, write buffer is flushed, and data_req_o is eventually supressed", + "Verification Goal": "Check that a fence.i will cause flushing of the:\n1) pipeline,\n2) prefetcher,\n3) write buffer,\n4) data_req_o.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_fencei_assert.sv, \"a_flush_pipeline\".\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.a_supress_datareq", + "Comment": "This is somewhat complex to check, so\n1) the pipeline and prefetcher asserts use rvfi retires as a \"proxy\", and\n2) the write buffer and data req asserts use only data req." + }, + { + "Requirement Location": "Riscv spec", + "Feature": "UnusedFields", + "Sub Feature": "UnusedFields", + "Feature Description": "imm[11:0], rs1, rd are reserved for future extensions, and implementations shall ignore them", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.fencei_assert_i.reserved_cg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "UnusedFields", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Try giving random values in those fields and see that all else works as expected", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.xlsx b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.xlsx index f232835cea..df00b3686f 100755 Binary files a/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.xlsx and b/cv32e40s/docs/VerifPlans/Simulation/micro_architecture/CV32E40SX_fencei.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv index b4fae49113..b73b1938cf 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.csv @@ -124,11 +124,11 @@ Address map may be modified to better suit actual implementations, but R[15] mus Note: Not very feasible to match on every single cfg index, because some are overshadowed by overlapping regions and to model this is expensive." ,,,Load instruction coverpoint,Region index or default IO unmapped region crossed with passing load instruction,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*, ,,,Store instruction coverpoint,Region index or default IO unmapped region crossed with passing store instruction,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*, -,,,Atomic instruction coverpoint,Region index or default IO unmapped region crossed with atomic operation,N/A,N/A,N/A,, +,,,(40X) Atomic instruction coverpoint,Region index or default IO unmapped region crossed with atomic operation,N/A,N/A,N/A,, ,,,Load alignment error coverpoint,Region index or default IO unmapped region crossed with load alignment error,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*, ,,,Store alignment error coverpoint,Region index or default IO unmapped region crossed with store alignment error,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*, -,,,Atomic load-reserved unallowed error coverpoint,Region index or default IO unmapped region crossed with atomic load-reserved unallowed error,N/A,N/A,N/A,, -,,,Atomic store-conditional unallowed error coverpoint,Region index or default IO unmapped region crossed with atomic store-conditional unallowed error,N/A,N/A,N/A,, +,,,(40X )Atomic load-reserved unallowed error coverpoint,Region index or default IO unmapped region crossed with atomic load-reserved unallowed error,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *x_lrw_firstfail*, +,,,(40X) Atomic store-conditional unallowed error coverpoint,Region index or default IO unmapped region crossed with atomic store-conditional unallowed error,Check against RM,"ENV capability, not specific test",Functional Coverage,COV: *x_scw_firstfail*, Risc-V Priv. spec,PMA Readability,PMA readable by SW,Design must support SW readback of attributes,"N/A. Can be SW-readable via a C-header, or is otherwise the responsibility of integration- or system-level testing.",N/A,N/A,N/A,, UM 0e447ac,Code Execution,Code Execution only from main memory,"Code execution is not allowed from IO region, any attempts to do so should result in an instruction access fault (exception code 1)","Verify that attempted code execution from an address located in a PMA region classified as IO always yields an instruction access fault (code 1). Accesses from Memory should never yield this access fault as no eXecutable flag exists, only Memory/IO classification @@ -166,14 +166,14 @@ Accesses not matching attribute regions should be treated as: Memory Non-Bufferable Non-Cacheable -Atomic operations not allowed","Arbitrary accesses to non-configured PMA-areas. +Atomic operations allowed","Arbitrary accesses to non-configured PMA-areas. Self checking test should attempt the following: - Non-aligned load/store accesses: should pass -- Atomic lr/sc operations (if supported by core): should fail +- Atomic lr/sc operations (if supported by core): should pass - Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply) - Instruction fetch and execute: should pass",Self Checking Test,Directed Self-Checking,Testcase,DTC: cv32e40s/tests/programs/custom/pma_0reg/, ,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: TODO - +A: TODO, a_atomic_access_no_pma_regions_LRW, a_atomic_access_no_pma_regions_SCW COV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*",TODO is the random stream run without pma regions? ,,,"PMA_NUM_REGIONS>0 Accesses not matching attribute regions should be treated as: @@ -188,6 +188,8 @@ Self checking test should attempt the following: - Instruction fetch and execute: should fail",Self Checking Test,Directed Self-Checking,Testcase,DTC: TODO,TODO missing directed test? ,,,,,Check against RM,Constrained-Random,Functional Coverage,"RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/ +A: TODO, a_atomic_access_outside_pma_regions_LRW, a_atomic_access_outside_pma_regions_SCW + COV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*", UM 0e447ac,OBI transfer flags,InstructionFetches,"Bufferable flag effects - For any instruction fetch marked bufferable, the corresponding OBI transfer instr_memtype[0] signal should be set to match the bufferable flag.","Ensure that instr_memtype[0] is set to 1 when an instruction fetch attempt is performed with the bufferable flag set to 1. (Which is never, because ""Accesses to regions marked as bufferable (bufferable=1) will result in the OBI mem_type[0] bit being set, except if the access was an instruction fetch [...]"".)",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_bufoff @@ -327,14 +329,14 @@ A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.p A: (The other cases are covered by all other testing.) COV: *.pma_cov_instr_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_dmregion_dmode_*", -UM 0e447ac,Atomic operations,Atomic operations shall only occur for regions in which Atomic operations are allowed. (Only applies for cores with A-extension),Load-Reserved attempts to a region where atomic operations are not permitted shall cause a precise load access fault (exception code 5),"Attempt arbitrary load-reserved memory operations to regions where atomic operations are not permitted and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that these operations do not generate these exceptions when performed on supported regions. +UM 0e447ac,40x: Atomic operations,Atomic operations shall only occur for regions in which Atomic operations are allowed. (Only applies for cores with A-extension),Load-Reserved attempts to a region where atomic operations are not permitted shall cause a precise load access fault (exception code 5),"Attempt arbitrary load-reserved memory operations to regions where atomic operations are not permitted and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that these operations do not generate these exceptions when performed on supported regions. -The following CSRs must be verified: Verify mcause, mepc, mtval",Self Checking Test,Directed Self-Checking,Testcase,(N/A for 40s), -,,,,,Check against RM,Constrained-Random,Functional Coverage,(N/A for 40s), +The following CSRs must be verified: Verify mcause, mepc, mtval",Self Checking Test,Directed Self-Checking,Testcase,Fow now: covered by assertions only., +,,,,,Check against RM,Constrained-Random,Functional Coverage,"A: a_atomic_access_atomic_regions_LRW, a_atomic_access_nonatomic_regions_LRW", ,,,Store-Conditional or Atomic Memory Operation (AMO) attempts to a region where Atomic operations are not allowed shall cause a precise store/AMO access fault (exception code 7).,"Attempt arbitrary store-conditional and atomic memory operations to regions where atomic operations are not allowed and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that this fault is not triggered when performing these operations on supported regions. -The following CSRs must be verified: Verify mcause, mepc, mtval",Self Checking Test,Directed Self-Checking,Testcase,(N/A for 40s), -,,,,,Check against RM,Constrained-Random,Functional Coverage,(N/A for 40s), +The following CSRs must be verified: Verify mcause, mepc, mtval",Self Checking Test,Directed Self-Checking,Testcase,Fow now: covered by assertions only., +,,,,,Check against RM,Constrained-Random,Functional Coverage,"A: a_atomic_access_atomic_regions_SCW, a_atomic_access_nonatomic_regions_SCW", UM 0e447ac,Fence* instructions,Fence instructions disregards distinction between memory and IO,Fence instruction shall not be impacted by PMA memory/IO attribute and execute as a conservative fence on all operations ,"Coverpoint - Fence instructions (Fence, fence.i) should not be impacted by PMA.",Check against RM,Constrained-Random,Functional Coverage,"RTC: TODO COV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_waspmafault_wasmain_wasloadstore_fence_*",TODO missing random test? diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json new file mode 100644 index 0000000000..15f4039e83 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.json @@ -0,0 +1,866 @@ +[ + { + "Requirement Location": "UM 0e447ac", + "Feature": "Regions", + "Sub Feature": "Valid number of regions", + "Feature Description": "There shall be between 0 and 16 PMA regions configured.", + "Verification Goal": "Assert that highest numbered PMA region < 16 (assuming 0-indexed)\n\nCover: Having 0 regions, having maximum num regions, and having something in between.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_valid_num_regions\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_valid_num_regions\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_index\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_index\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_cov_instr_i.cg_inst.cp_numregions", + "Comment": "TODO tests must be added to regression lists.\n\nTODO directed tests has parts to uncomment if RTL is ready.\n\nTODO everything \"atomics\" must be changed to \"integrity\" for 40s." + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "Configuration to be tested", + "Feature Description": "0 Regions - Deconfigured", + "Verification Goal": "Test configuration 1, aims to verify the following:\n1. Default parameters for entire memory range", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "No cover, but fascilitates other covers below.\n\nTODO these regions are out of date vs testbench.\n\nTODO must be used in formal regressions too." + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "1 Region: \nR[0]: 0x0000_0000-0xFFFF_FFFF (MBCA = 1111)\n\nMBCA = M(ain memory)\n B(ufferable)\n C(acheable)\n A(tomic operations allowed)\n\n", + "Verification Goal": "Test configuration 2, aims to verify the following:\n1. System configured with 1 PMA region only\n2. Full address range of maximum size\n3. Upper/Lower bounds for first region set to min/max values", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "1 Region: \nR[0]: 0x0000_0000-0x7FFF_FFFF (MBCA = 1111)", + "Verification Goal": "Test configuration 3, aims to verify the following:\n1. Correct functionality for 1 defined region\n2. Correct behavior for undefined regions when a region is defined", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "7 Regions:\nR[0]: 0x0000_0000-0x1FFF_FFFF (MBCA = 1111)\nR[1]: 0x2000_0000-0x3FFF_FFFF (MBCA = 1101)\nR[2]: 0x4000_0000-0x5FFF_FFFF (MBCA = 0101)\nR[3]: 0x6000_0000-0x9FFF_FFFF (MBCA = 1001)\nR[4]: 0xA000_0000-0xDFFF_FFFF (MBCA = 0101)\nR[5]: 0xE000_0000-0xE00F_FFFF (MBCA = 0000)\nR[6]: 0xE010_0000-0xFFFF_FFFF (MBCA = 0101)", + "Verification Goal": "Test configuration 4, aims to verify the following:\n1. A standard memory map (Based on ARM Cortex)\n2. A fully defined, contiguous memory map with no undefined regions\n3. Multiple, non-overlapping regions", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "16 Regions:\nR[0]: 0x4800_0000-0x49FF_FFFF (MBCA = 1011)\nR[1]: 0x4400_0000-0x4BFF_FFFF (MBCA = 0001)\nR[2]: 0x3ACE_0000-0x4ABC_FFFF (MBCA = 0100)\nR[3]: 0x3600_A000-0x4F99_FFFF (MBCA = 1111)\nR[4]: 0x3420_C854-0x5000_ABFF (MBCA = 1101)\nR[5]: 0x3100_FCAB-0x5000_BCCA (MBCA = 1001)\nR[6]: 0x3000_1353-0x5140_FFFF (MBCA = 0000)\nR[7]: 0x2C5A_3200-0x52FF_FFFF (MBCA = 0101)\nR[8]: 0x2A00_0000-0x56FF_FFFF (MBCA = 1111)\nR[9]: 0x2340_000A-0x600F_FFFF (MBCA = 0001)\nR[10]: 0x2000_0000-0x63FF_FFFF (MBCA = 0101)\nR[11]: 0x13AC_AA55-0x7FFF_FFFF (MBCA = 1011)\nR[12]: 0x1000_000F1-0x82FF_FFFF (MBCA = 1101)\nR[13]: 0x0500_0000-0x8459_FFFF (MBCA = 0100)\nR[14]: 0x0200_0000-0xEFFF_FFFF (MBCA = 0000)\nR[15]: 0x0000_A000-0xFFFE_FFFF (MBCA = 1111)", + "Verification Goal": "Test configuration 5, aims to verify the following:\n1. Region match priority\n2. Maximum number of separate areas in memory (33)\n\nAddress may be modified to better suit implementation and verification enviornment, but the following criteria must be met:\n1. Each defined region must be enclosed by the adjacent region of lower priority\n2. No region boundaries must overlap\n3. There shall be undefined space prior to and aft of largest, highest numbered region\n", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "16 Regions:\nR[0]: 0x0001_0000-0x001F_FFFF (MBCA = 1001)\nR[1]: 0x0030_0000-0x04FF_FFFF (MBCA = 1111)\nR[2]: 0x1000_0000-0x1001_0000 (MBCA = 0100)\nR[3]: 0x1800_1234-0x18FF_AB21 (MBCA = 0000)\nR[4]: 0x2020_0010-0x2FFF_0000 (MBCA = 0001)\nR[5]: 0x3100_A000-0x32FF_FFFF (MBCA = 1111)\nR[6]: 0x3440_0000-0x3800_FFFF (MBCA = 0100)\nR[7]: 0x4AAA_F000-0x4C00_FFFF (MBCA = 1101)\nR[8]: 0x4D00_5555-0x4FFF_ABCD (MBCA = 1011)\nR[9]: 0x5100_0000-0x52FF_FFFF (MBCA = 0000)\nR[10]: 0x5400_0000-0x5FFF_FFFF (MBCA = 1111)\nR[11]: 0x6300_0000-0x6700_FFFF (MBCA = 0101)\nR[12]: 0xA000_0000-0xAFFF_FFFF (MBCA = 1001)\nR[13]: 0xBC00_0000-0xBCFF_FFFF (MBCA = 1101)\nR[14]: 0xC000_0000-0xDFFF_FFFF (MBCA = 0001)\nR[15]: 0xE700_EF00-0xE9FF_FFFF (MBCA = 0101)", + "Verification Goal": "Test configuration 6, aims to verify designs with the following characteristic:\n1. Non-contiguously defined maximum number of memory regions\n2. Maximum number of separate areas In memory (33)\n3. No overlap, single matching regions\n4. Non-defined areas prior and aft of each defined region\n\nAddress map may be modified to better suit actual implemetations, but the above criteria must be adhered to.", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "16 Regions:\nNote: Zero length regions are intentional\nR[0]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[1]: 0x5555_5555-0x5555_5555 (MBCA = 0000)\nR[2]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[3]: 0xAAAA_AAAA-0xAAAA_AAAA (MBCA = 0000)\nR[4]: 0xCCCC_CCCC-0xCCCC_CCCC (MBCA = 0000)\nR[5]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[6]: 0xE38E_E38E-0xE38E_E38E (MBCA = 0000)\nR[7]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[8]: 0xFFFF_FFFF-0xFFFF_FFFF (MBCA = 0000)\nR[9]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[10]: 0x9249_2492-0x9249_2492 (MBCA = 0000)\nR[11]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[12]: 0xDB6D_B6DB-0xDB6D_B6DB (MBCA = 0000)\nR[13]: 0x0000_0000-0x0000_0000 (MBCA = 0000)\nR[14]: 0x1249_2492-0x1249_2492 (MBCA = 0000)\nOnly one non-zero region:\nR[15]: 0x0000_0000-0xFFFF_FFFF (MBCA = 1111)", + "Verification Goal": "Test configuration 7, aims to verify the following:\n1. Zero length regions does not match any accesses\n2. Upper/Lower bound of outlier (last) region set to min/max of address range\n\nAddress map may be modified to better suit actual implementations, but R[15] must be defined to min/max possible address range. Remaining regions shall have 0 length.\n", + "Pass/Fail Criteria": "Any/All", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "N/A", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "Coverpoints", + "Feature Description": "Instruction fetch coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with passing instruction fetch", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "Note: These could also have used RVFI instead.\n\nNote: Not very feasible to match on every single cfg index, because some are overshadowed by overlapping regions and to model this is expensive." + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Load instruction coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with passing load instruction", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Store instruction coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with passing store instruction", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "(40X) Atomic instruction coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with atomic operation", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Load alignment error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with load alignment error", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "Store alignment error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with store alignment error", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *.pma_cov_data_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_multimatch_aligned_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "(40X )Atomic load-reserved unallowed error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with atomic load-reserved unallowed error", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *x_lrw_firstfail*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Regions", + "Sub Feature": "", + "Feature Description": "(40X) Atomic store-conditional unallowed error coverpoint", + "Verification Goal": "Region index or default IO unmapped region crossed with atomic store-conditional unallowed error", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: *x_scw_firstfail*", + "Comment": "" + }, + { + "Requirement Location": "Risc-V Priv. spec", + "Feature": "PMA Readability", + "Sub Feature": "PMA readable by SW", + "Feature Description": "Design must support SW readback of attributes", + "Verification Goal": "N/A. Can be SW-readable via a C-header, or is otherwise the responsibility of integration- or system-level testing.", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Code Execution", + "Sub Feature": "Code Execution only from main memory", + "Feature Description": "Code execution is not allowed from IO region, any attempts to do so should result in an instruction access fault (exception code 1)", + "Verification Goal": "Verify that attempted code execution from an address located in a PMA region classified as IO always yields an instruction access fault (code 1). Accesses from Memory should never yield this access fault as no eXecutable flag exists, only Memory/IO classification\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nE.g. execute a JMP instruction to an area defined as IO (and/or unconfigured PMA region) and verify that an instruction access fault is triggered", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Code Execution", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Verify that attempted code execution from an address located in a PMA region classified as IO always yields an instruction access fault (code 1). Accesses from Memory should never yield this access fault as no eXecutable flag exists, only Memory/IO classification\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nE.g. execute a JMP instruction to an area defined as IO (and/or unconfigured PMA region) and verify that an instruction access fault is triggered", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg.cross_pma", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Code Execution", + "Sub Feature": "Instruction fetch violation coverpoints", + "Feature Description": "Instruction group type for failing instruction fetch violations", + "Verification Goal": "Instruction group type cover from ISACOV for each violated PMA instruction fetch", + "Pass/Fail Criteria": "Other", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: TODO", + "Comment": "TODO missing cover. (Problem: Depends on ISACOV updates.)" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Access match", + "Sub Feature": "Non-Overlapping PMA Regions", + "Feature Description": "A match should always be inside its matching region, \nLower_bound[region] <= addr[addr_max:2] < Upper_bound[region]", + "Verification Goal": "Assert that match[region] always implies that the following holds: \nlower[region] & 2'b00 <= addr[31:0] < upper[region] 2'b00", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_bounds\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_bounds", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses: Verify that accesses are matched to their respective memory regions", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "ENV capability, not specific test", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_lowest\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_lowest", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses: Verify that accesses are matched to their respective memory regions", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_multimatch*\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_matchregion*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "Overlapping PMA Regions", + "Feature Description": "Any access matching multiple regions should attain the attributes of the lowest numbered matching region", + "Verification Goal": "Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region.\n\nCoverage: Multiple regions matching at once.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region.\n\nCoverage: Multiple regions matching at once.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_coverpoint_cp_multimatch*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Perform arbitrary accesses and verify that addr[lowest byte] is always interpreted with the attributes of the lowest numbered matching region.\n\nCoverage: Multiple regions matching at once.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk2.a_pma_match_lowest\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk2.a_pma_match_lowest", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "Non-Matching Accesses", + "Feature Description": "PMA_NUM_REGIONS==0: \nAccesses not matching attribute regions should be treated as: \nMemory\nNon-Bufferable\nNon-Cacheable\nAtomic operations allowed", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should pass\n- Atomic lr/sc operations (if supported by core): should pass\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should pass", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma_0reg/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should pass\n- Atomic lr/sc operations (if supported by core): should pass\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should pass", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\nA: TODO, a_atomic_access_no_pma_regions_LRW, a_atomic_access_no_pma_regions_SCW\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*", + "Comment": "TODO is the random stream run without pma regions?" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "PMA_NUM_REGIONS>0\nAccesses not matching attribute regions should be treated as: \nIO\nNon-Bufferable\nNon-Cacheable\nAtomic operations not allowed", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should fail\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should fail", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "", + "Feature": "Access match", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Arbitrary accesses to non-configured PMA-areas.\nSelf checking test should attempt the following: \n- Non-aligned load/store accesses: should fail\n- Atomic lr/sc operations (if supported by core): should fail\n- Cacheable/Bufferable operations - verify instr and data_memtype[x] for correct behavior. (Assertions in OBI section should apply)\n- Instruction fetch and execute: should fail", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nA: TODO, a_atomic_access_outside_pma_regions_LRW, a_atomic_access_outside_pma_regions_SCW\n\nCOV: *pma_cov_*_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_multimatch_aligned_loadstoreexec_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "OBI transfer flags", + "Sub Feature": "InstructionFetches", + "Feature Description": "Bufferable flag effects - For any instruction fetch marked bufferable, the corresponding OBI transfer instr_memtype[0] signal should be set to match the bufferable flag.", + "Verification Goal": "Ensure that instr_memtype[0] is set to 1 when an instruction fetch attempt is performed with the bufferable flag set to 1. (Which is never, because \"Accesses to regions marked as bufferable (bufferable=1) will result in the OBI mem_type[0] bit being set, except if the access was an instruction fetch [...]\".)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_bufoff\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk4.a_pma_obi_bufon_unreachable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that instr_memtype[0] is set to 0 when an instruction fetch attempt is performed with the bufferable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_bufoff\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk4.a_pma_obi_bufon_unreachable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Cacheable flag effects - For any instruction fetch marked cacheable, the corresponding OBI transfer instr_memtype[1] signal should be set to match the cacheable flag.", + "Verification Goal": "Ensure that instr_memtype[1] is set to 1 when an instruction fetch attempt is performed with the cacheable flag set to 1", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.genblk5.a_pma_obi_cacheon\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that instr_memtype[1] is set to 0 when an instruction fetch attempt is performed with the cacheable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.mpu_if_sva.a_pma_obi_cacheoff\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Instruction fetch attempts to PMA restricted regions should cause instr_req_o to be deasserted.", + "Verification Goal": "Ensure that PMA-violating instruction fetch attempts does not assert the instr_req_o signal by attempting execution of instructions from allowed and restricted areas of memory, checking that instr_req_o remains deasserted when restricted areas are accessed", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_req_prohibited\n\nCOV: *.pma_cov_instr_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "DataFetches", + "Feature Description": "Bufferable flag effects - data_memtype[0] should match the bufferable flag.", + "Verification Goal": "Ensure that data_memtype[0] is set to 1 when a data fetch attempt is performed with the bufferable flag set to 1", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk4.a_pma_obi_bufon\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that data_memtype[0] is set to 0 when a data fetch attempt is performed with the bufferable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_obi_bufoff\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_memtype_bufferable\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Cacheable flag effects - data_memtype[1] should match the cacheable flag", + "Verification Goal": "Ensure that data_memtype[1] is set to 1 when an data fetch attempt is performed with the cacheable flag set to 1", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.genblk5.a_pma_obi_cacheon\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that data_memtype[1] is set to 0 when an data fetch attempt is performed with the cacheable flag set to 0", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.mpu_lsu_sva.a_pma_obi_cacheoff\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "OBI transfer flags", + "Sub Feature": "", + "Feature Description": "Data fetch attempts to PMA restricted regions should cause data_req_o to be deasserted.", + "Verification Goal": "Ensure that PMA violating data fetch attempts does not assert the data_req_o signal", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_req_prohibited\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_allow_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "Non-naturally aligned data accesses shall only occur for Main memory accesses.", + "Feature Description": "Non-naturally aligned load access attempts to I/O shall\n cause a precise load access fault (exception code 5).", + "Verification Goal": "Attempt arbitrary non-naturally aligned load accesses to I/O regions specified by PMA and ensure that these accesses triggers precise load access fault exceptions (code 5). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions. \n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nld from addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nlw from addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nlh from addresses in IO space with and_reduce(addr_lsb[1:0]) = 1\n", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary non-naturally aligned load accesses to I/O regions specified by PMA and ensure that these accesses triggers precise load access fault exceptions (code 5). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions. \n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nld from addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nlw from addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nlh from addresses in IO space with and_reduce(addr_lsb[1:0]) = 1\n", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_aligned_main_loadstoreexec_*", + "Comment": "TODO missing \"ld/lw/lh\" specific covers." + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "Non-naturally aligned store access attempts to I/O shall\n cause a precise store access fault (exception code 7).", + "Verification Goal": "Attempt arbitrary non-naturally aligned store accesses to I/O regions specified by PMA and ensure that these accesses triggers precise store access fault exceptions (code 7). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nsd to addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nsw to addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nsh to addresses in IO space with and_reduce(addr_lsb[1:0]) = 1", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary non-naturally aligned store accesses to I/O regions specified by PMA and ensure that these accesses triggers precise store access fault exceptions (code 7). Ensure that non-aligned main memory accesses to permitted regions do not generate these exceptions\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval\n\nTest possible combinations of misalignment, the following are of particular interest as it will result in two memory access operations: \nsd to addresses in IO space with or_reduce(addr_lsb[2:0]) = 1\nsw to addresses in IO space with or_reduce(addr_lsb[1:0]) = 1\nsh to addresses in IO space with and_reduce(addr_lsb[1:0]) = 1", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_aligned_main_loadstoreexec_*", + "Comment": "TODO missing \"sd/sw/sh\" specific covers." + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "Multi-memory operation instructions", + "Feature Description": "When the first memory access of a non-naturally aligned load operation fails due to PMA checks, the second memory access shall also be supressed. ", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A :uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_failure_denies_subsequents\n\nRTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "If a PMA access fault occurs for any of the memory accesses in a non-naturally aligned load, the register file shall not be updated", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n- Boundary between IO region and memory region s.t. first access will be in memory and second access will be in IO.\n\nIn both cases, the register file should remain unchanged.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n- Boundary between IO region and memory region s.t. first access will be in memory and second access will be in IO.\n\nIn both cases, the register file should remain unchanged.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "When the first memory access of a non-naturally aligned store operation fails due to PMA checks, the second memory access shall also be supressed. ", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Non-Naturally Aligned Accesses", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt non-naturally aligned load instructions to:\n- IO\n- Boundary between IO region and memory region s.t. first access will be in IO and second access will be in main memory. \n\n\nIn both cases, data_req_o should remain low for both operations.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: cv32e40s/tests/programs/corev-dv/corev_rand_pma_test/\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_loadstore_firstfail_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_loadstore_boundary_bin_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Zce Extension", + "Sub Feature": "Push instructions", + "Feature Description": "push, push.e, c.push, c.push.e instructions shall only occur for main memory regions, any such *push* attempts to I/O shall cause a precise load access fault (exception code 5)", + "Verification Goal": "Attempt *push* operations to main memory and IO, verify that all *push* attempts to IO causes a precise store access fault (code 5) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt *push* operations to main memory and IO, verify that all *push* attempts to IO causes a precise store access fault (code 5) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_main_pushpop_*", + "Comment": "TODO missing random test?\n\nNote: Cover doesn't check that it goes through WB." + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "Pop instructions", + "Feature Description": "pop, popret, pop.e, popret.e, c.pop, c.popret, c.pop.e, c.popret.e shall only occur for main memory regions, any such *pop* attempts from I/O shall cause a precise load access fault (exception code 7)", + "Verification Goal": "Attempt *pop* operations to main memory and IO, verify that all *pop* attempts to IO causes a precise loac access fault (code 7) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out." + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt *pop* operations to main memory and IO, verify that all *pop* attempts to IO causes a precise loac access fault (code 7) and that this does not occur for main memory.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_loadstoreexec_main_pushpop_*", + "Comment": "TODO missing random test?\n\nNote: Cover doesn't check that it goes through WB." + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "Table Jump", + "Feature Description": "Both jumps from a Zce table jump should be checked by PMA and handled as instruction fetches. \n\nPMA failure in the first table jump should suppress the second jump - instr_fetch_o should be suppressed and no jump to the restricted address shall be performed", + "Verification Goal": "First jump: Testing a violating first jump (jump to the jump table) requires a custom linker script that deliberatly places the jump table in a non-executable (IO) region. A test must verify that instructions attempting to jump to the jump table location causes an instruction access fault (exception code 1) and that instr_req_o is suppressed\n\nThe second instruction fetch should be suppressed.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Second jump: Test should verify that a PMA access fault on the second jump (jump to the actual instruction address in IO region) should cause an instruction access fault (exception code 1), suppressing instr_req_o. ", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma/", + "Comment": "TODO test is commented out" + }, + { + "Requirement Location": "", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Coverpoint - Table jumps passing PMA checks crossed with region index or default unmapped memory region", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_pmafault_tablejump_*\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_aligned_pmafault_firstfail_tablejump:_*\n\nCOV: *.pma_cov_instr_i.cover_item_covergroup_cg_mpu_inst_mpu_cg_cross_x_allow_jvt_*", + "Comment": "TODO missing random test?\n\nNote: This is not maximally comprehensive, but the modelling that would otherwise be required is disproportionately complex." + }, + { + "Requirement Location": "Zce spec. proposal", + "Feature": "Zce Extension", + "Sub Feature": "", + "Feature Description": "Instruction fetch exceptions occurring when executing an address in the jump table should lead to mepc being set to the C.TBLJ* instruction, and mtval to the address in the jump table entry", + "Verification Goal": "Verify that an instruction fetch exception resulting from a jump table entry leads to mepc being set to the C.TBLJ* instruction and mtval to the address in the jump table entry.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: TODO", + "Comment": "TODO missing directed test?" + }, + { + "Requirement Location": "Risc-V Debug spec.", + "Feature": "Debug mode", + "Sub Feature": "Single step PMA exceptions", + "Feature Description": "Any instruction fetch exception that occurs while single stepping, causes debug mode to be re-entered after PC is changed to the exception handler and the appropriate tval and cause registers are updated", + "Verification Goal": "Verify that instruction fetches to PMA IO regions fails, the appropriate CSRs and PC is updated to the appropriate values and debug mode is reentered. ", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma_debug/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Debug mode", + "Sub Feature": "Program buffer PMA exceptions", + "Feature Description": "Exceptions in the program buffer should cause the program buffer code to end and cmderr set to 3 (exception error)", + "Verification Goal": "Verify that program buffer code attempting to fetch instructions from PMA IO region fails, PC is set to dm_exception_addr_i and cmderr is set to 3 (exception error). No other registers should be changed due to this exception.", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/pma_debug/", + "Comment": "" + }, + { + "Requirement Location": "40s UM 0.8.0", + "Feature": "DebugRange", + "Sub Feature": "DebugRange", + "Feature Description": "\"CV32E40S overrules the PMA and PMP settings for the Debug Module region when it is in debug mode\"", + "Verification Goal": "Attempt access within/outside the dm region, in both dmode/not, check that the combo within/dmode never gets blocked and that the other combos follow the ordinary rules.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Code Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pma_assert_instr_i.a_dm_region\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.a_dm_region\n\nA: (The other cases are covered by all other testing.)\n\nCOV: *.pma_cov_instr_i.cover_item_covergroup_cg_inst_cg_inst_cross_x_dmregion_dmode_*", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "40x: Atomic operations", + "Sub Feature": "Atomic operations shall only occur for regions in which Atomic operations are allowed. (Only applies for cores with A-extension)", + "Feature Description": "Load-Reserved attempts to a region where atomic operations are not permitted shall cause a precise load access fault (exception code 5)", + "Verification Goal": "Attempt arbitrary load-reserved memory operations to regions where atomic operations are not permitted and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that these operations do not generate these exceptions when performed on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Fow now: covered by assertions only.", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "40x: Atomic operations", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary load-reserved memory operations to regions where atomic operations are not permitted and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that these operations do not generate these exceptions when performed on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: a_atomic_access_atomic_regions_LRW, a_atomic_access_nonatomic_regions_LRW", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "40x: Atomic operations", + "Sub Feature": "", + "Feature Description": "Store-Conditional or Atomic Memory Operation (AMO) attempts to a region where Atomic operations are not allowed shall cause a precise store/AMO access fault (exception code 7).", + "Verification Goal": "Attempt arbitrary store-conditional and atomic memory operations to regions where atomic operations are not allowed and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that this fault is not triggered when performing these operations on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Self Checking Test", + "Test Type": "Directed Self-Checking", + "Coverage Method": "Testcase", + "Link to Coverage": "Fow now: covered by assertions only.", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "40x: Atomic operations", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Attempt arbitrary store-conditional and atomic memory operations to regions where atomic operations are not allowed and ensure that these operations trigger precise store/AMO access fault exceptions (code 7). Ensure that this fault is not triggered when performing these operations on supported regions.\n\nThe following CSRs must be verified: Verify mcause, mepc, mtval", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: a_atomic_access_atomic_regions_SCW, a_atomic_access_nonatomic_regions_SCW", + "Comment": "" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "Fence* instructions", + "Sub Feature": "Fence instructions disregards distinction between memory and IO", + "Feature Description": "Fence instruction shall not be impacted by PMA memory/IO attribute and execute as a conservative fence on all operations ", + "Verification Goal": "Coverpoint - Fence instructions (Fence, fence.i) should not be impacted by PMA.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "RTC: TODO\n\nCOV: *.pma_cov_data_i.gen_rvfi_cg.cover_item_covergroup_cg_rvfi_inst_rvfi_cg_cross_x_waspmafault_wasmain_wasloadstore_fence_*", + "Comment": "TODO missing random test?" + }, + { + "Requirement Location": "UM 0e447ac", + "Feature": "WriteBuffer", + "Sub Feature": "Bufferable operations", + "Feature Description": "Only bufferable store accesses should use the internal write buffer", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.gen_writebuf.a_writebuf_bufferable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pma_assert_data_i.gen_writebuf.gen_noregions_nobuf.a_writebuf_noregions\n\nCOV: uvm_pkg.uvm_test_top.env.pma_agent.region_cov_model*.pma_access_covg", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": " -------END---------", + "Feature": "WriteBuffer", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Assert that write buffer remains unchanged unless store accesses carry the bufferable flag", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "Link to Coverage": "", + "Comment": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx old mode 100755 new mode 100644 index 6e5553c3a0..d65209864c Binary files a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx and b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40SX_PMA_VerifPlan.xlsx differ diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json new file mode 100644 index 0000000000..43080652d0 --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_PMP.json @@ -0,0 +1,1718 @@ +[ + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "SmepmpOverrule", + "Feature Description": "The \"smepmp\" spec features can overrule the \"privspec\" (e.g. for locking). Both specs are included here, so be mindful that checking of certain vplan items could be conditional.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "FunctionalCoverage", + "Feature Description": "Functional coverage is encouraged to be creative in capturing a broad set of possible state, and evaluate it towards the checkers, to catch aspects of pmp functionality that this vplan might have overlooked.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "ImplementationChanges", + "Feature Description": "If test implementation reveals new knowledge that contradicts or augments this vplan, then the vplan should be updated.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Comments", + "Sub Feature": "TimeAllowance", + "Feature Description": "Some verification goals in this plan has a \"base level\" of checking plus some optional tweaks that might be tried. It is up to the testing implementation how to prioritize and potentially skip the extras, according to what time allows.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "privspec", + "Feature": "General", + "Sub Feature": "Configs", + "Feature Description": "The pmp must be tested in a wide range of configurations. That includes testing on both instruction-side and data-side, and it includes testing overlapping regions, non-overlaping, no regions, differing settings for overlapping regions, M-mode only, U-mode only, both M-mode and U-mode, etc, etc. Use functional coverage with plenty of crosses.", + "Verification Goal": "Run with different configs to test parameters in low/mid/high ranges and in combination with the other parameters, instantiate checking on both instruction-side and data-side, write coverage to see all relevant region overlap combinations and to see an exhaustive combination of block-level input combinations and functional-level states.", + "Pass/Fail Criteria": "Other", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "Smepmp", + "Feature Description": "Given 1) backwards-compatible reset values, and 2) no change in \"mseccfg\", then C) the PMP should be fully compatible with the privspec.", + "Verification Goal": "For all privspec-derived PMP assertions, check that they must hold as long as the two preconditions hold (i.e. must not be excusable/overridable by smepmp features).", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "UmodeAlways", + "Feature Description": "\"PMP checks are applied to all accesses whose effective privilege mode is S or U, including instruction fetches in S and U mode, data accesses in S and U mode when the MPRV bit in the mstatus register is clear, and data accesses in any mode when the MPRV bit in mstatus is set and the MPP field in mstatus contains S or U.\"\n\nNote: None of those scenarios should let an access bypass the pmp.", + "Verification Goal": "Set up the system to match each point in the listing, ensure that the pmp's decision matches all modelled expectations.\n\nNote: Also cover when none of the listed preconditions are active and the pmp's decision can disagree with the modelled expectations.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "DefaultNone", + "Feature Description": "\"PMP can grant permissions to S and U modes, which by default have none\"", + "Verification Goal": "Check that, out of reset, given no extraordinary reset values, and given no change to the pmp csrs, then U-mode has no access permissions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "General", + "Sub Feature": "DefaultFull", + "Feature Description": "\"can revoke permissions from M-mode, which\nby default has full permissions\"", + "Verification Goal": "Check that, out of reset, given no extraordinary reset values, and given no change to the pmp csrs, then M-mode has full access permissions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "ResetRegisters", + "Feature Description": "\"Writable PMP registers\u2019 A and L fields are set to 0, unless the platform mandates a different reset value for some PMP registers\u2019 A and L fields.\"", + "Verification Goal": "Read the A and L values right after reset, ensure that the default reset values are 0.\n\nNote: Should also be visible on rvfi without specifically using csr instructions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "Warl", + "Feature Description": "\"All PMP CSR fields are WARL and may be hardwired to zero\".\n\nNote: A field shall also not change its value when an attempt is made to write an illegal value to it. (XWR is one field.)", + "Verification Goal": "Try writing any values to the registers and read values out of them, ensure that neither reads nor writes causes exceptions, and ensure that all read values are legal or otherwise as expected and that illegally written fields don't change.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfg_expected[*].a_cfg_expected\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "MmodeOnly", + "Feature Description": "\"PMP CSRs are only accessible to M-mode.\"", + "Verification Goal": "Try to access any of the pmp CSRs from U-mode, ensure that it always gives \"illegal instruction exception\" and that the CSRs are not updated.\n\nNote: M-mode accesses are covered by AlwaysAccessible below.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_csrs_mmode_only\n\nCOV: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing cover (combine with \"Warl\" above)" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "Addr34bit", + "Feature Description": "\"Each PMP address register encodes bits 33\u20132 of a 34-bit physical address for RV32\"", + "Verification Goal": "Ensure that when the pmpaddr MSBs are set, then no NAPOT accesses matches. Cover that all bits have been matched against (\"toggle cross\"). Ensure that there are no attempted accesses to MSBs that the core should not be able to use.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Csrs", + "Sub Feature": "AddrImplemented", + "Feature Description": "\"Not all physical address bits may be implemented, and so the pmpaddr registers are WARL.\"", + "Verification Goal": "Cover (toggle) that all bits can be both written and set. (UnusedZero below covers the WARL(0x0) case.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "MatchDisabled", + "Feature Description": "\"When A=0, this PMP entry is disabled and matches no addresses\"\nWhen a cfg is set to off but its address(es) (interpreted as napot/tor) is the only rule that matches an attempted access, then it still does not count as a match.", + "Verification Goal": "Have a region's address(es) set up as tor and napot (separate runs), have all other regions not include the target address, have the target region's rule be OFF, make an access within that range, ensure that the outcome is the same as for when an access is outside of all address ranges.\n\nNote: For this and several other items, functional coverage is necessary because the checking doesn't necessarily have the above scenario in its antecedent.\n\nCoverage: Capture the above scenario, minus the checking.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "NapotMatching", + "Feature Description": "\"NAPOT ranges make use of the low-order bits of the associated address register to encode the size of the range [\"yyyy...yy01\" etc]\"\n\nNote: The napot address matching modes match on addresses that are equal to the requested access when masked to the granularity size.", + "Verification Goal": "Configure napot rules of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated sizes.\n\nNote: Includes NAPOT and NA4.\n\nNote: Try also max and min.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4is4byte.a_na4_is_4byte\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_napot_encoding_bin_auto[*]\ndut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_napot_encoding_disallowed_bin_auto[*]\n\nCOV: ???", + "Comment": "TODO missing coverage" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorMatching", + "Feature Description": "\"If TOR is selected, the associated address register forms the top of the address range, and the preceding PMP address register forms the bottom of the address range. If PMP entry i\u2019s A field is set to TOR, the entry matches any address y such that pmpaddri\u22121 \u2264 y < pmpaddri (irrespective of the value of pmpcfgi\u22121)\"", + "Verification Goal": "Configure tor regions of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated ranges.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_cg_common.cover_item_covergroup_cg_internals_common_inst_cg_int_coverpoint_cp_ismatch_tor_bin_auto[*]\n\nCOV: ???", + "Comment": "TODO missing coverage" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorZero", + "Feature Description": "\"If PMP entry 0\u2019s A field is set to TOR, zero is used for the lower bound, and so it matches any address y < pmpaddr0.\"", + "Verification Goal": "Configure entry 0 as tor regions of different sizes, try accesses within and outside the regions, ensure that the outcomes corresponds to the designated ranges.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorNomatch", + "Feature Description": "\"If pmpaddri\u22121 \u2265 pmpaddri and pmpcfgi.A=TOR, then PMP entry i matches no addresses.\"", + "Verification Goal": "Set up tor regions where the addresses are not in increasing order, try accesses on or within the designated \"reverse\" regions, ensure that they are treated as if there is no match.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???\n\nDTC: cv32e40s/tests/programs/custom/pmp/", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "SameGrain", + "Feature Description": "\"In general, the PMP grain [...] must be the same across all PMP regions.\"", + "Verification Goal": "Do the same as for the basic case of GranularityDetermination below, ensure that all read values are the same across all the pmp csrs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "Na4Unselectable", + "Feature Description": "\"When G \u2265 1, the NA4 mode is not selectable.\"", + "Verification Goal": "Have the G parameter set to at least 1, ensure that NA4 never gets selected (even when writing to non-locked cfg).\n\nNote: Formal should easily check this.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4onlyg0[*].a_na4_only_g0\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_na4onlyg0[*].a_na4_only_g0\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_na4onlyg0[*].a_na4_not_when_g uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_na4onlyg0[*].a_na4_not_when_g", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "NapotImplied", + "Feature Description": "\"When G \u2265 2 and pmpcfgi.A[1] is set, i.e. the mode is NAPOT\".", + "Verification Goal": "(Covered by Na4Unselectable above)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "NapotOnes", + "Feature Description": "\"When G \u2265 2 and pmpcfgi.A[1] is set, [...] then bits pmpaddri[G-2:0] read as all ones.\"", + "Verification Goal": "Have the G parameter set to at least 2, have A set, read pmpaddri, ensure the LSBs are all ones as specified.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_napot_ones_g2.gen_napot_ones_i[*].a_napot_ones", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "AllZeros", + "Feature Description": "\"When G \u2265 1 and pmpcfgi.A[1] is clear, i.e. the mode is OFF or TOR, then bits pmpaddri[G-1:0] read as all zeros.\"", + "Verification Goal": "Create the listed preconditions, ensure that the read value contains zeroes as specified.\n\nNote: Check both OFF/TOR, and for all configs fields (checking of all configs don't need 100% coverage in simulation).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_all_zeros_g1.gen_all_zeros_i[*].a_all_zeros\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "TorUnaffected", + "Feature Description": "\"Bits pmpaddri[G-1:0] do not affect the TOR address-matching logic.\"", + "Verification Goal": "Write different values to \"pmpaddri[G-1:0]\", ensure TOR mode matches the same either way.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "StorageUnaffected", + "Feature Description": "\"Although changing pmpcfgi.A[1] affects the value read from pmpaddri, it does not affect the underlying value stored in that register\"\n\"in particular, pmpaddri[G-1] retains its original value when pmpcfgi.A is changed from NAPOT to TOR/OFF then back to NAPOT.\"", + "Verification Goal": "Change in and out of (OFF || TOR) and !(OFF || TOR), ensure that different values can be read without having written anything new to the register.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_storage_unaffected[*].a_storage_unaffected\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "GranularityDetermination", + "Feature Description": "\"Software may determine the PMP granularity by writing zero to pmp0cfg, then writing all ones to pmpaddr0, then reading back pmpaddr0. If G is the index of the least-significant bit set, the PMP granularity is 2 G+2 bytes.\"", + "Verification Goal": "Write zero to pmpicfg, write ones to pmpaddri, read pmpaddri, ensure that the LSB index matches to granularity parameter.\n\nNote: Formal can maybe check this for all i.\n\nNote: If time allows, can write something else than zero and ensure that the rest follows as expected.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_granularity_determination", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "AddressMatching", + "Sub Feature": "XlenMatching", + "Feature Description": "\"If the current XLEN is greater than MXLEN, the PMP address registers are zero-extended from MXLEN to XLEN bits for the purposes of address matching.\"", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "UntilReset", + "Feature Description": "\"Locked PMP entries remain locked until the hart is reset.\"", + "Verification Goal": "Lock entry i (for all i, if feasible), ensure that the lock bit is never lifted before reset. (Unless if RLB interferes.)\n\nNote: Sim might do a second reset, formal most likely won't and shouldn't need to.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_until_reset[*].a_until_reset", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "IgnoreWrites", + "Feature Description": "\"If PMP entry i is locked, writes to pmpicfg and pmpaddri are ignored.\"", + "Verification Goal": "Lock entry i (for all i, if feasible), ensure that their value can't change, both when written to and otherwise. (Unless if RLB interferes.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rlb_locked[*].a_norlb_locked_rules_cannot_modify uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rlb_locked[*].a_norlb_locked_rules_cannot_modify\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_writes_notrap[*].a_ignore_writes_notrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_writes_nochange[*].a_ignore_writes_nochange\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "IgnoreTor", + "Feature Description": "\"Additionally, if PMP entry i is locked and pmpicfg.A is set to TOR, writes to pmpaddri-1 are ignored.\"", + "Verification Goal": "Lock entry i (\u2026), have A set and the mode be TOR, ensure that pmpaddri-1 can't change, both for explicit writes and otherwise. (Unless RLB.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_tor[*].a_ignore_tor_stable\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_ignore_tor[*].a_ignore_tor_wdata\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "NotIgnore", + "Feature Description": "When neither cfg i is locked, nor is cfg i+1 a locked TOR region, then writes to cfg and addr i are not ignored.", + "Verification Goal": "Have cfg i unlocked, write to cfg and addr csr i, check that it changes.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_addr_writes[*].a_addr_nonlocked\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_addr_tor[*].a_addr_nonlocked_tor", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "LockOff", + "Feature Description": "\"Setting the L bit locks the PMP entry even when the A field is set to OFF.\"", + "Verification Goal": "Lock entry i while the mode is OFF, ensure that it gets locked in this case too.\n\nNote: Ensure that checking and coverage handles locking for all possible modes.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: (Same checking as for \"IgnoreWrites\" and \"IgnoreTor\" above.)\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "RwxPrivmode", + "Feature Description": "\"In addition to locking the PMP entry, the L bit indicates whether the R/W/X permissions are enforced on M-mode accesses. When the L bit is set, these permissions are enforced for all privilege modes.\"", + "Verification Goal": "Be in M-mode and U-mode (separate runs), access a region where L is set and where RWX {grant, deny R, deny W, deny X}, ensure that the access is correspondingly granted/denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "MmodeSucceed", + "Feature Description": "\"When the L bit is clear, any M-mode access matching the PMP entry will succeed\"", + "Verification Goal": "Be in M-mode, access a region where L is clear, ensure that access is granted in all cases.\n\n(Note, see \"Smepmp\" above.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockingAndPrivmode", + "Sub Feature": "RwxUmode", + "Feature Description": "\"When the L bit is clear [\u2026] the R/W/X permissions apply only to S and U modes.\"", + "Verification Goal": "Be in U-mode, access a region where L is clear, ensure that access is granted/denied based on RWX.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_uorl_onlyif_rwx\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_uorl_onlyif_rwx\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "LowestDetermines", + "Feature Description": "\"PMP entries are statically prioritized. The lowest-numbered PMP entry that matches any byte of an access determines whether that access succeeds or fails.\"\n\nNote: \"any\" byte.", + "Verification Goal": "Access a region that is covered by multiple rules, ensure that the lowest indexed match determines the outcome.\n\nNote: Requires that the rules would disagree on the outcome.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MatchAll", + "Feature Description": "\"The matching PMP entry must match all bytes of an access, or the access fails, irrespective of the L, R, W, and X bits.\"", + "Verification Goal": "(Only relevant for 64-bit architectures.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "LrwxDetermines", + "Feature Description": "\"If a PMP entry matches all bytes of an access, then the L, R, W,and X bits determine whether the access succeeds or fails. [...] if the L bit is set or the privilege mode of the access is S or U, then the access succeeds only if the R, W,or X bit corresponding to the access type is set.\"", + "Verification Goal": "Access a pmp region where L and the privmode etc is such that nothing else would deny the access, ensure that each of (or a combination of) RWX can either grant or deny the access.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_lrwx_aftermatch\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_lrwx_aftermatch\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MmodeSucceed2", + "Feature Description": "\"If the L bit is clear and the privilege mode of the access is M, the access succeeds.\"", + "Verification Goal": "(Same as \"MmodeSucceed\" above)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MmodeNomatch", + "Feature Description": "\"If no PMP entry matches an M-mode access, the access succeeds.\"", + "Verification Goal": "Be in M-mode, access a region where no rule matches, ensure that the access is granted (where MMWP is off).\n\n(Note, see \"Smepmp\" above.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "UmodeNomatch", + "Feature Description": "\"If no PMP entry matches an S-mode or U-mode access, but at least one PMP entry is implemented, the access fails.\"\n\nNote: \"All PMP CSRs are always implemented\".", + "Verification Goal": "Be in U-mode, do an access that doesn't match any region, ensure that the access fails.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_nomatch_umode_fails\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_nomatch_umode_fails\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "UmodeOff", + "Feature Description": "\"If at least one PMP entry is implemented, but all PMP entries\u2019 A fields are set to OFF, then all S-mode and U-mode memory accesses will fail.\"", + "Verification Goal": "Be in U-mode, have all entries OFF, make an access, ensure that the access fails (for all variations of accesses).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "FailException", + "Feature Description": "\"Failed accesses generate an instruction, load, or store access-fault exception.\"", + "Verification Goal": "Cause failed accesses on instructions/loads/stores, ensure that an exception occurs and that it is the right one.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nA: ::uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "PriorityAndMatching", + "Sub Feature": "MultiAccess", + "Feature Description": "\"Note that a single instruction may generate multiple accesses, which may not be mutually atomic. An access-fault exception is generated if at least one access generated by an instruction fails, though other accesses generated by that instruction may succeed with visible side effects.\"\n\n\"On some implementations, misaligned loads, stores, and instruction fetches may also be decomposed into multiple accesses, some of which may succeed before an access-fault exception occurs. In particular, a portion of a misaligned store that passes the PMP check may become visible, even if another portion fails the PMP check.\"", + "Verification Goal": "Induce misaligned word instruction-fetch, load, and store, where the lower and upper (separate runs) parts are either accessible or blocked by pmp, ensure that exceptions occur while parts of the access might reach the bus.\n\nAlso check Zc's push/pop and table jump.\n\nNote: It is up to other vplans to check what happens upon the exception. It is up to this PMP vplan to check that the PMP will cause the exceptions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_splittrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_splittrap\n\nA: ???\n\nCOV: ???", + "Comment": "TODO missing assert (on split that errs on first)\n\nTODO missing cover" + }, + { + "Requirement Location": "smepmp", + "Feature": "MsecCfg", + "Sub Feature": "MmodeOnly", + "Feature Description": "\"Machine Security Configuration (mseccfg) is [...] only accessible to Machine mode.\"\n\nNote: Includes \"mseccfgh\".", + "Verification Goal": "Access (read/write) mseccfg (and mseccfgh) from M-mode, access mseccfg from U-mode, ensure that the first always works (WARL) and the second never works (exception).\n\nNote: Cover with MPRV too.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "MsecCfg", + "Sub Feature": "FieldsWarl", + "Feature Description": "\"All mseccfg fields defined on this proposal are WARL\"", + "Verification Goal": "Try writing any values to the fields (the defined ones, but also other bits) and read values out of the fields, ensure that neither reads nor writes causes exceptions, and ensure that all read values are legal or otherwise as expected.\n\nNote: This relates to the \"stickiness\" of those fields. Regardless of their values and current stickiness, the fields are WARL.\n\nNote: It might be difficult, when trying to write a checker for traps, to filter out all other causes for traps that can occur simultaneously. (Either reduce the scope of checking, or write re-usable helper signals for \"trap causality\" info.)\n\nNote: \"WPRI\" on some bits.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "MsecCfg", + "Sub Feature": "ReservedZero", + "Feature Description": "\"the remaining bits are reserved for future standard use and should always read zero.\"\n(This spec can't dictate that about other specs, but the user manual agrees on the hardwiring.)", + "Verification Goal": "Read mseccfg, ensure the non-smepmp-field bits are always zero.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "MsecCfg", + "Sub Feature": "ResetValue", + "Feature Description": "\"The reset value of mseccfg is implementation-specific, otherwise if backwards compatibility is a requirement it should reset to zero on hard reset.\"", + "Verification Goal": "Read the value of mseccfg right after reset, ensure that the default reset value is zero.\n\nNote: Should also be visible on rvfi without specifically using csr instructions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mseccfg_reset_val\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mseccfg_reset_val", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "ModifiableEntries", + "Feature Description": "\"When mseccfg.RLB is 1 locked PMP rules may be removed/modified and locked PMP entries may be edited.\"\n\nNote: Both \"cfg\" and \"addr\" registers, limited to fields within \"cfg\" reg, also TOR affects lower \"addr\" reg.", + "Verification Goal": "Have a locked pmp entry i, set RLB to 1, try modifying any(!) field within {pmpicfg, pmpaddri, pmpaddri-1(tor)}, ensure that values are updated succesfully (while respecting other rules like legal values and reserved bits).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_addr\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_exec\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_lock\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_mode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_read\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.*.gen_rlb_locked_cov[*].c_rlb_locked_rules_can_modify_write\n\nCOV: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "RemainZero", + "Feature Description": "\"When mseccfg.RLB is 0 and pmpcfg.L is 1 in any rule or entry (including disabled entries), then mseccfg.RLB remains 0 and any further modifications to mseccfg.RLB are ignored until a PMP reset\"\n\nNote: \"any\" entry.", + "Verification Goal": "Have RLB=0 and at least one L=1, ensure that RLB is 0 forever (until reset).\n\nNote: No exception occurs on attempted access, but one should try overwriting the value to stimulate the checking.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_rlb_never_fall_while_locked\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_rlb_never_fall_while_locked", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "UntilReset", + "Feature Description": "The sticky zero and update-ignores last until reset, and do not hold after reset.", + "Verification Goal": "Ensure that RLB is modifiable after reset. (Unless if reset values are set to activate the RemainZero condition.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_until_reset_notbefore\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockingBypass", + "Sub Feature": "HardwireZero", + "Feature Description": "\"Vendors who don\u2019t need this functionality may hardwire this field to 0.\"", + "Verification Goal": "(40s has not hardwired this to 0, it is RW.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WhiteList", + "Sub Feature": "StickyUntilReset", + "Feature Description": "\"[mseccfg.MMWP] is a sticky bit, meaning that once set it cannot be unset until a PMP reset.\"", + "Verification Goal": "Have MMWP set, ensure that it remains high forever (til reset).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mmwp_never_fall_until_reset\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mmwp_never_fall_until_reset", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "WhiteList", + "Sub Feature": "Denied", + "Feature Description": "\"When set it changes the default PMP policy for M-mode when accessing memory regions that don\u2019t have a matching PMP rule, to denied instead of ignored.\"", + "Verification Goal": "Have MMWP set, be in (effective mode) M-mode, access regions that don't match any rule (including OFF, \"reversed\" TOR, >32bit NAPOT, etc), ensure that the access is denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_nomatch_mmode_mmwp_fails\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_nomatch_mmode_mmwp_fails\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "StickyUntilReset", + "Feature Description": "\"[mseccfg.MML] is a sticky bit, meaning that once set it cannot be unset until a PMP reset.\"", + "Verification Goal": "Cover: Trying to clear the bit.\n\nCheck: Have MML set, ensure that it remains high forever (til reset).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_pmp_assert.a_mml_never_fall_until_reset\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_mml_never_fall_until_reset\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "ExecIgnored", + "Feature Description": "\"[When mseccfg.MML is set.] Adding an M-mode-only or a locked Shared-Region rule with executable privileges is not possible and such pmpcfg writes are ignored, leaving pmpcfg unchanged.\"\n\nNote: \"pmpcfg\" refers to a field, so the write to the CSR itself should still update other fields.", + "Verification Goal": "Have MML set, try adding an \"M-mode-only\" rule and a \"locked Shared-Region\" rule with X privileges, ensure that the relevant pmpcfg field is not updated but is left unchanged, ensure also that other fields can still get updated.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rlb_locked_cov[0].a_mmode_only_or_shared_executable_ignore\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rlb_locked_cov[0].a_mmode_only_or_shared_executable_ignore\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "ExecRlb", + "Feature Description": "\"[The above] restriction can be temporarily lifted e.g. during the boot process, by setting mseccfg.RLB.\"", + "Verification Goal": "Have RLB and MML set, try adding an \"M-mode-only\" rule and a \"locked Shared-Region\" rule with X privileges, ensure that the relevant pmpcfg field is in fact updated.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rlblifts_lockedexec[*].a_rlblifts_lockedexec", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "MmodeExec", + "Feature Description": "\"Executing code with Machine mode privileges is only possible from memory regions with a matching M-mode-only rule or a locked Shared-Region rule with executable privileges. Executing code from a region without a matching rule or with a matching S/U-mode-only rule is denied.\"", + "Verification Goal": "Execute from \"M-mode-only\" and \"locked Shared-Region\" regions, attempt execution without matching and from \"U-mode-only\" regions, ensure corresponding grant or deny.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownGeneral", + "Sub Feature": "RwReserved", + "Feature Description": "\"If mseccfg.MML is not set, the combination of pmpcfg.RW=01 remains reserved for future standard use.\"", + "Verification Goal": "Whitelist the conditions that allow RW=01 (including MML conditions), ensure that it is adhered to.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rwx_mml[*].a_rwx_mml\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_rwfuture[*].a_rw_futureuse\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_rwfuture[*].a_rw_futureuse", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeEnforce", + "Feature Description": "\"[When mseccfg.MML is set.] An M-mode-only rule is enforced on Machine mode\"", + "Verification Goal": "Be in M-mode, have MML set, access an \"M-mode-only\" region, ensure that the grant/deny is always in accordance to the rule. (E.g. it is not denied execute despite the execute bit being set.)\n\nNote: Exclude cases of interference from e.g. PMA.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "UmodeDeny", + "Feature Description": "\"[When mseccfg.MML is set.] An M-mode-only rule is [...] denied in Supervisor or User mode.\"", + "Verification Goal": "Be in U-mode, have MML set, access an \"M-mode-only\" region, ensure that the access is always denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "RemainLocked", + "Feature Description": "\"It also remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset\"\n\nCertain rules under MML are sticky. They cannot be modified again.", + "Verification Goal": "Configure rules for {\"M-mode-only\", \"U-mode-only, \"Shared-Region rule where pmpcfg.L is set\"(both kinds)}, have MML=1 (and RLB=0), ensure that the configs never change again (until reset).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "RlbUnlocks", + "Feature Description": "\"It also remains locked [...] unless mseccfg.RLB is set.\"", + "Verification Goal": "Have the same setup as in RemainLocked, but let RLB=1, try changing the configs, ensure that they are indeed changed.\n\nNote: \"Assertion check\" includes cover properties.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "UmodeEnforce", + "Feature Description": "\"[When mseccfg.MML is set.] An S/U-mode-only rule is enforced on Supervisor and User modes \"", + "Verification Goal": "Be in U-mode, have MML=1, access a \"U-mode-only\" region, ensure that the grant/deny is in accordance with the rule (apart from PMA etc).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cg_data\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_cp_instr_side.cg_instr\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeDeny", + "Feature Description": "\"An S/U-mode-only rule is [...] denied on Machine mode.\"", + "Verification Goal": "Be in M-mode, have MML=1, access a \"U-mode-only\" region, ensure that the access is always denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "TODO missing coverage. (Just do a cg with crosses of all of these variables.)" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "SharedEnforced", + "Feature Description": "\"A Shared-Region rule is enforced on all modes\"", + "Verification Goal": "Be in M-mode and U-mode (separate runs), access a \"Shared-Region\", ensure that the grant/deny is in accordance with the rule.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "SharedNoexec", + "Feature Description": "\"A Shared-Region rule where pmpcfg.L is not set can be used for sharing data between M-mode and S/U-mode, so is not executable.\"", + "Verification Goal": "Be in M-mode and U-mode, try to execute from \"A Shared-Region rule where pmpcfg.L is not set\", ensure that it does not work (exception).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeReadwrite", + "Feature Description": "\"[Shared-Region rule where pmpcfg.L is not set.] M-mode has read/write access to that region\"", + "Verification Goal": "Be in M-mode, perform reads and writes to such a region, ensure that the intended effects happen and that the accesses do not cause exceptions.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "UmodeRead", + "Feature Description": "\"[For a Shared-Region rule where pmpcfg.L is not set] S/U-mode has read access if pmpcfg.X is not set, or read/write access if pmpcfg.X is set.\"", + "Verification Goal": "Be in U-mode, perform reads and writes to such a region, ensure that the reads always work and that the writes depend on X.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "SharedNowrite", + "Feature Description": "\"A Shared-Region rule where pmpcfg.L is set can be used for sharing code between M-mode and S/U-mode, so is not writeable.\"\n\nNote: The spec is unclear here, but \"A Shared-Region rule where pmpcfg.L is set\" must refer to \"LRWX=101X\", because \"The encoding pmpcfg.LRWX=1111\" is a separate point. (This holds for the subsequent items below too.)", + "Verification Goal": "Be in M-mode and U-mode, write to such a region, ensure that the writes do not reach the bus and that an exception occurs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "BothExecute", + "Feature Description": "\"Both M-mode and S/U-mode have execute access on the [Shared-Region rule where pmpcfg.L is set]\"", + "Verification Goal": "Be in M-mode and U-mode, attempt to execute from such a region, ensure that the code is executed and that the attempt does not cause an exception.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "MmodeRead", + "Feature Description": "\"M-mode also has read access [to Shared-Region rule where pmpcfg.L is set] if pmpcfg.X is set.\"", + "Verification Goal": "Be in M-mode, attempt to read from such a region, ensure that the success depends accordingly on X.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: ???", + "Comment": "(Same as for \"MmodeDeny\")" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "IgnoreUntilReset", + "Feature Description": "\"The [Shared-Region rule where pmpcfg.L is set] remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set.\"", + "Verification Goal": "(Covered by RemainLocked above.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "BothReadonly", + "Feature Description": "\"The encoding pmpcfg.LRWX=1111 can be used for sharing data between M-mode and S/U mode, where both modes only have read-only access to the region.\"", + "Verification Goal": "Be in M-mode and U-mode, access such a region, ensure that only the reads work and that the rest (write/execute) excepts.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_accept_only_legal\nuvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.*.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_pmp_assert.a_deny_only_illegal\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_cp_instr_side.cover_item_covergroup_cg_internals_instr_side_inst_cg_instr_coverpoint_cp_r_mmode_mml_lrwx\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cover_item_covergroup_cg_internals_data_side_inst_cg_instr_coverpoint_cp_r_mmode_mml_lrwx\n\nCOV: dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_cp_data_side.cover_item_covergroup_cg_internals_data_side_inst_cg_instr_coverpoint_cp_r_umode_mml_lrwx\n\nCOV: ???", + "Comment": "TODO technically missing the \"the rest \u2026 excepts\" cover" + }, + { + "Requirement Location": "", + "Feature": "LockdownA", + "Sub Feature": "ReadonlyLocked", + "Feature Description": "\"The [pmpcfg.LRWX=1111] rule remains locked so that any further modifications to its associated configuration or address registers are ignored until a PMP reset, unless mseccfg.RLB is set.\"", + "Verification Goal": "(Covered by RemainLocked above.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "LegalRwx", + "Sub Feature": "", + "Feature Description": "Depending on the mseccfg control bits and L, some RWX combinations are reserved.\n\nNote: Use the table from the spec.", + "Verification Goal": "Ensure that illegal/reserved mseccfg/L/RWX combinations are unreachable.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfg_expected[*].a_cfg_expected\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgwdata_legal[*].a_cfgwdata_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Reachable", + "Sub Feature": "", + "Feature Description": "All legal states in the table are reachable. It could theoretically be that platform-specific constraints made certain states unreachable (particularily related to locking), but we should be able to reach all legal and supported combinations of settings.", + "Verification Goal": "Ensure that all legal states are reachable.", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "manual", + "Feature": "Parameters", + "Sub Feature": "MinimumGranularity", + "Feature Description": "\"The PMP_GRANULARITY parameter is used to configure the minimum granularity of PMP address matching. The minimum granularity is [2^(PMP_GRANULARITY+2)] bytes, so at least 4 bytes.\"", + "Verification Goal": "Have runs with max granularity, minimum granularity, and something in between. Make sure all checkers/covers are active for each relevant run configuration, so tor/napot/na4 is tested with different granularities. Cover cases where a match would otherwise occur but the granularity made the access not match.\n\nNote: Ensure TorMatching etc above heed this parameter.", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Parameters", + "Sub Feature": "NumRegions", + "Feature Description": "\"The PMP_NUM_REGIONS parameter is used to configure the number of PMP regions, starting from the lowest numbered region.\"\n\nNote: Including 0 regions.", + "Verification Goal": "Have runs with max number, minimum number, and something in between.", + "Pass/Fail Criteria": "Other", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Parameters", + "Sub Feature": "ResetValues", + "Feature Description": "\"The reset value of the PMP CSR registers can be set through the top level parameters PMP_PMPNCFG_RV[], PMP_PMPADDR_RV[] and PMP_MSECCFG_RV.\"", + "Verification Goal": "Have runs with different reset values. Ensure that after reset then the reset values are effectuated.\n\nNote: Try also, reset values with locked configs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Parameters", + "Sub Feature": "DefaultValues", + "Feature Description": "The reset value defaults should amount to a safe config. (Including no violation of reserved bits.)", + "Verification Goal": "(Covered by all the checks that handles the various legalities.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "AlwaysAccessible", + "Feature Description": "\"All PMP CSRs are always implemented\". \"MRW\". The CSRs are M-mode accessible, and their existence does not depend on PMP_NUM_REGIONS.\n\nNote: \"All\" pmp registers, and all fields within them.", + "Verification Goal": "Be in M-mode, access (reads/writes) all the pmp csrs, ensure that it always works without excepting (because the csrs exist and the mode is appropriate).\n\nNote: Potential overlap with CSR vplan.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "ReservedLegal", + "Feature Description": "Reserved bits/fields have legal values, matching the platform-specified defaults.", + "Verification Goal": "(Overlaps with LegalRwx and RwReservedabove.) Read all fields of all pmp-related csrs, ensure there are no unsupported values anywhere (at all times).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_cfgrdata_expected[*].a_cfgrdata_expected", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MseccfghZero", + "Feature Description": "\"Hardwired to 0\"", + "Verification Goal": "Read mseccfgh, ensure it is always 0.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "UnusedZero", + "Feature Description": "\"CSRs (or bitfields of CSRs) related to PMP entries with number PMP_NUM_REGIONS and above are hardwired to zero.\"\n\nNote: Including upper parts of pmpcfgn and also pmpaddr.", + "Verification Goal": "Read pmpcfg and pmpaddr csrs, ensure the values are zero as specified. Cover that the other values can be non-zero.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "Hardening", + "Feature Description": "Certain CSRs related to the PMP shall be \"hardened\" as per Xsecure.", + "Verification Goal": "(CSR hardening is the responsibility of the security features vplan, even the pmp-specific part of it.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "WaitUpdate", + "Feature Description": "Updates to pmp configs should NOT have an effect on earlier instructions (nor on the instruction itself).\n\nNote: Potential security hole.", + "Verification Goal": "The pmp grant/deny checking must be compared vs \"rvfi_csr__rdata\".\n(This will detect whether the actual pmp decision differs from what the rvfi csr data would incidate.)\n\nNote: Compare \"pc_rdata\" for execute, and \"mem_\" signals for read/write. (Might need additional decoding of \"rvfi_insn\".)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_musttrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_load\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_store\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_splittrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_musttrap\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_cause\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_splittrap\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Inject pmp csr write instructions in random testing, intermingled with all other kinds of instructions. This should include random interrupts, bus faults, random bus stalls, etc.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "AffectSuccessors", + "Feature Description": "Updates to pmp configs MUST have an effect on later instructions.\n\nNote: Potential security hole.\n\nNote: There was a known rtl bug here before (cv32e40s/issues/168).", + "Verification Goal": "The \"rvfi_csr__wdata\" (masked) for pmp csrs on one instruction, must match the \"_rdata\" value of the next instruction.\n(Combined with checking grant/deny on \"_rdata\", this should ensure that the subsequent instruction has been affected by any pmp csr update.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "(Shares asserts with \"WaitUpdate\" above.)\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rvfi_csr_writes[0].a_rvfi_cfg_writes\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.gen_rvfi_csr_writes[0].a_rvfi_addr_writes", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "(Same random testing as WaitUpdate above.)", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "ImplementationDetails", + "Feature Description": "Details about pipeline/prefetcher/bus flushing etc are not part of this vplan. Only black-box observable functional behavior is checked. (Such requirements exists in specs, but are deliberately not addressed here.)", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "Performance", + "Feature Description": "Requirements about performance and stalls etc are not covered here (unless review calls for the opposite).", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "MicroArchitecture", + "Sub Feature": "WriteBuffer", + "Feature Description": "Changes to the pmp config should not impact the write buffer such that a transaction can get its grant/deny status altered.", + "Verification Goal": "Cover cases of the write buffer being full while the pmp cfg changes. Checking of accidental grants is handled by SuppressReq below. Checking of guaranteed writes is not part of this vplan.\n\nNote: The Write buffer is situated between the pmp and the bus.", + "Pass/Fail Criteria": "Other", + "Test Type": "Other", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "COV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "SuppressReq", + "Feature Description": "When an access is denied by the pmp, the effect is that the attempted obi transaction is suppressed and does not reach the bus.\n\nNote: Both \"instr_req_o\" and \"data_req_o\".", + "Verification Goal": "Observe a transaction request coming in to the pmp module, observe the pmp denying the access, ensure that the obi bus is shielded from the transaction request.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i.u_pmp_assert_lsu.gen_supress_req_data.a_suppress_req_data\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i.u_pmp_assert_if_stage.gen_supress_req_instr.a_suppress_req_instr", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "InternalBuses", + "Feature Description": "(The transaction request feeding into the mpu and its response signaling is not covered by this vplan.)", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ExceptionExecute", + "Feature Description": "\"mcause [...] Instruction access fault [...] Execution attempt with address failing PMP check.\"", + "Verification Goal": "Attempt execution of a region that pmp denies execution of, ensure that an \"instruction access fault\" exception occurs (read mcause and rvfi signals).\n\nNote: Since ISS can check most of this, one could deprioritize this checking if it is not feasible to check within reasonable efforts. (Same for the next 2 items.)", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_cause", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ExceptionLoad", + "Feature Description": "\"mcause [...] Load access fault [...] Load attempt with address failing PMP check.\"\n\nNote: Holds for load-reserved too.", + "Verification Goal": "Attempt loads (and load-reserveds) of a region that pmp denies reading from, ensure that a \"load access fault\" exception occurs (read mcause and rvfi signals).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_load\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ExceptionStore", + "Feature Description": "\"mcause [...] Store/AMO access fault [...] Store attempt with address failing PMP check.\"\n\nNote: Holds for store-conditional and amo too.", + "Verification Goal": "Attempt stores (and store-conditionals and amo) to a region that pmp denies writing to, ensure that a \"store/amo access fault\" exception occurs (read mcause and rvfi signals).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_cause_store\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "TrapPrecisely", + "Feature Description": "\"All exceptions are precise\".\nMeaning mepc will point to the offending instruction, and exactly previous instructions have their side effects fully visible.\n\nNote: Applies to loads, stores, and executes.", + "Verification Goal": "Observe that the pmp causes an exception, ensure that mepc points to the offending instruction.\n\nNote: Let the Exceptions vplan deal with visibility of side effects for earlier instructions. (Zc push/pop does not follow this, but that is mostly the responsibility of the Zc vplan.)\n\nNote: If satisfactory mepc checking already exist then it is acceptable to just add covers for the pmp scenarios.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "AlertMinor", + "Feature Description": "\"The following issues result in a minor security alert: [...] Instruction access fault [...] Load access fault [...] Store/AMO access fault\"", + "Verification Goal": "(Responsibility of the xsecure vplan. But link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for xsecure vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "AlertNothing", + "Feature Description": "The manual lists which pmp-related events can cause an alert minor, but the pmp should in no other cases be the cause for an alert (major/minor).\n\nNote: Example, \"attempt to reprogram a locked PMP\"", + "Verification Goal": "Observe an alert signal going high while there is no pmp error that should have caused it, ensure that another viable reason for the alert was present.\n\nNote: This is slightly out of scope for this vplan, so if it is not very easy to hook on to existing xsecure (helper-)signals then this can be skipped.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "SplitLoadRegfile", + "Feature Description": "Even if parts of a split load can reach the bus, the instruction itself has failed and so the regfile should not get updated.", + "Verification Goal": "(Handled by \"SplitLoadException\" below, because: One only needs to show that an exception is caused, and the exceptions vplan is responsible for checking what that means for the regfile. (But link to coverage here too.))", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "Waiting for exceptions vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "SplitLoadException", + "Feature Description": "For split loads, regardless of which of the access that fails, the instruction should still cause an exception.", + "Verification Goal": "Perform a misaligned load that translates to multiple accesses, let any of the accesses be denied by pmp, ensure an exception occurs.\n\nCoverage: See rvfi retire with exception cause from pmp, while the \"low addr\" model checking gave access granted.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "FirstFail", + "Feature Description": "If a split load/store fails on its first transaction it should get an exception immediately, so it should not allow the second transaction reach the bus and mcause shall reflect the failing transactions.", + "Verification Goal": "Attempt such an instruction, ensure that the denied access does not reach the bus, ensure that following accesses also do not reach the bus.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "PushPop", + "Feature Description": "If a push/pop fails on a transaction it should get an exception immediately, so the remaining transactions should not reach the bus and mcause shall reflect the failing transaction.", + "Verification Goal": "(Responsibility of the zc vplan. But link to coverage here too.)\n\nNote: Could write a pmp-specific cover, but coordinate with Zc vplan to ensure the checker is written too.", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for zc vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "TableJump", + "Feature Description": "PMP applies to table jumps and Zc instructions in general.", + "Verification Goal": "(Responsibility of the zc vplan. But link to coverage here too.)\n\nNote: Could write a pmp-specific cover, but coordinate with Zc vplan to ensure the checker is written too.", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for zc vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "ClicVector", + "Feature Description": "Similarly to TableJump above, CLIC vector fetch needs execute permission.", + "Verification Goal": "(Analogous to TableJump above.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for clic vplan" + }, + { + "Requirement Location": "", + "Feature": "Violations", + "Sub Feature": "Priority", + "Feature Description": "Exceptions priority apply to the PMP as well. Particularily, PMP exception (instruction access fault) gets priority over bus errors (instruction bus fault) if an instruction is the result of two fetches were both of these occurred.\n\nNote: Both could be present in an attempted executed instruction at the same time, because no exception occurs before the point of execution so there is enough time for both to be captured and travel through the pipeline.", + "Verification Goal": "Keep track of words fetched with bus error and with pmp execute denied, check retired instructions for a pc that overlaps two such fetches (cover both orders), ensure that \"instruction access fault\" is the taken exception.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "TODO missing assert\n\nTODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RevokeExecutable", + "Feature Description": "Even if the pma should allow for execution, the pmp can overrule it and deny access.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma allow for execution, let the pmp deny it, attempt execution, ensure that execution is indeed denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RemainNonexecutable", + "Feature Description": "If the pma disallows execution, the pmp cannot change this fact and execution remains disallowed.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma disallow execution, let the pmp allow and deny execution (separate runs), attempt execution, ensure that execution is denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RevokePermissible", + "Feature Description": "Even if the pma allows for data access, the pmp can overrule it and deny access.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma allow for read and write (separate or same runs), let pmp deny read/write, attempt read/write, ensure that the pmp can overrule the pma.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Pma", + "Sub Feature": "RemainNonpermissible", + "Feature Description": "If the pma disallows data access, the pmp cannot change this fact and data access remains disallowed.", + "Verification Goal": "Set up pma and pmp regions such that both have rules covering the same addresses, let the pma deny read and write, let pmp allow or deny it, attempt read/write, ensure that the access is always denied.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "misc", + "Feature": "Misc", + "Sub Feature": "DisallowDebug", + "Feature Description": "The PMP can deny usage of debug mode by setting up regions for dm_halt_addr and dm_exception_addr.", + "Verification Goal": "Set up pmp rules so all D-mode entries are blocked from execution, attempt to enter debug mode, ensure that nohing is executed in debug mode.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Directed Non-Self-Checking", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "Waiting for ongoing spec changes to be resolved" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "40x", + "Feature Description": "The 40x does not have PMP.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Xif", + "Feature Description": "The X-interface can do memory operations, but the 40x does not have PMP and the 40s does not have XIF.", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "RvfiReliable", + "Feature Description": "Rvfi is used for checking some pmp functionality, so the link between rvfi and pmp must be checked.", + "Verification Goal": "If feasible to model within reasonable effort, check that 1) the PMPs' privmode inputs and 2) CSRs and 3) wdata/wmask is for csr write instrs, are properly correlated between access attempts and rvfi reportings.\nOtherwise, leave this to general ISS checking.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\n(Indirectly checked by those asserts)", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "RvfiTrap", + "Feature Description": "The \"rvfi_trap\" table has PMP-specific fields.", + "Verification Goal": "Augment the exception checkers above with checking of \"rvfi_trap.cause_type\" to ensure that specifically PMP is reported as the cause.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "UntilReset", + "Feature Description": "Everything that can get locked \"until reset\" must be possible to change after a reset. It should not be possible that these settings lock up so even resets cannot unlock them.\n\nNote: Formal's reset analysis should in principle be able to find every state that is possible to be in after a reset.", + "Verification Goal": "(Covered by ResetValues above. As long as those always take effect out of reset, then a permanent lock up should be either impossible or intentional.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Xsecure", + "Feature Description": "(Will be covered by its own vplan.)", + "Verification Goal": "N/A", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "High Priority?": "", + "Link to Coverage": "N/A", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Reset", + "Feature Description": "The PMP module is never reset without the whole core being reset. (As this could lift all the locks and stickies and grant privilege escalation.)", + "Verification Goal": "Check that the core's reset is always equal to the pmp module's reset.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "UmodeZeroRegions", + "Feature Description": "If the parameters are set to have 0 pmp regions, then all rules are OFF and U-mode matches nothing and defaults to not have any access.", + "Verification Goal": "Be in U-mode, have PMP_NUM_REGIONS=0, ensure all accesses fail (read/write/execute).", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "High Priority?": "", + "Link to Coverage": "A: ???", + "Comment": "TODO missing assert" + }, + { + "Requirement Location": "debug", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "\"All operations are executed with machine mode privilege\".\nIt is mostly the responsibility of other vplans to check D-mode relationship to M-mode and U-mode, but the pmp inputs should be checked against debug mode.\n\nNote: Refer to user-mode vplan and debug vplan if necessary.\n\nNote: It is assumed that once 1) dmode is shown to be interpreted as mmode by pmp, and 2) all mmode features are verified, then C) the mmode features will work in dmode. But one alternative is to duplicate all the mmode-related checking with dmode variants.", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "High Priority?": "High Priority", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noexec_*\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.pmprvfi_assert_i.a_noloadstore_*\n\n(Indirectly checked by those asserts, together with effective priv mode and umode asserts for dmode/mmode.)\n\nCOV: ???", + "Comment": "TODO missing cover" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + }, + { + "Requirement Location": " -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- END -----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------", + "Feature": "Mmode", + "Sub Feature": "", + "Feature Description": "", + "Verification Goal": "Ensure that the PMP inputs receive the correct mode while in D-mode.\n\nNote: Test w/wo MPRV too.", + "Pass/Fail Criteria": "", + "Test Type": "", + "Coverage Method": "", + "High Priority?": "", + "Link to Coverage": "", + "Comment": "" + } +] \ No newline at end of file diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.csv b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.csv index 05ab44153d..6794dc80b2 100644 --- a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.csv +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.csv @@ -23,37 +23,25 @@ COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_umo COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_mmode_trap", obi,,InstrProt,"""prot[2:1] User/Application (2’b00), Supervisor (2’b01), Reserved (2’b10), Machine (2’b11) -This matches the privilege levels from [RISC-V-PRIV].""","Track prot[2:1] on instruction fetches on obi, observe retirements on rvfi, ensure the privilege mode of the instruction's execution matches what it was fetched as on obi. - -Coverage: Explicitly observe U/M both.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_instr_prot +This matches the privilege levels from [RISC-V-PRIV].""","Track prot[2:1] on instruction fetches on obi, observe retirements on rvfi, ensure the privilege mode of the instruction's execution matches what it was fetched as on obi.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_instr_prot A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_instr_prot_legal -A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prot_iside_legal - -COV: ???", +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prot_iside_legal", ,,DataProt,"""prot[2:1] User/Application (2’b00), Supervisor (2’b01), Reserved (2’b10), Machine (2’b11) -This matches the privilege levels from [RISC-V-PRIV].""","Track prot[2:1] on data loads/stores, observe retirements on rvfi, ensure the effective privilege mode of the retirement matches what was used on obi. - -Coverage: Explicitly observe U/M both.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot +This matches the privilege levels from [RISC-V-PRIV].""","Track prot[2:1] on data loads/stores, observe retirements on rvfi, ensure the effective privilege mode of the retirement matches what was used on obi.",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot_legal A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prot_dside_legal -A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot_equal - -COV: ???", +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot_equal", ,,DbgProt,"Since dmode execs as mmode, and obi has corresponding signals, the relationship should be visible on obi.","When obi has a transaction with `dbg` high, check that `prot[2:1]` is M-mode on I-side, and ""effective"" mode on D-side. -Note: Consider checking before MPU. - -Coverage: Observe U-/M-mode on D-side.",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_iside +Note: Consider checking before MPU",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_iside -A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_dside - -COV: ???", +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_dside", privspec,CSRs,IllegalAccess,"""Attempts to access a CSR without appropriate privilege level […] also raise illegal instruction exceptions""","Try all kinds of accesses (R, W, RW, S, C, …) to all M-level CSRs while in U-level; ensure illegal instruction exception happens. (Hint: Assert RVFI vs csr[9:8]) @@ -64,8 +52,7 @@ COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csr DTC: cv32e40s/tests/programs/custom/csr_priv_gen_test/", ,,AccessLevel,"""The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR.""","Try all kinds of accesses to all implemented M-level and U-level CSRs while in M-mode and U-mode (cross), ensure appropriate access grant/deny.",Check against RM,Constrained-Random,Functional Coverage,COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr, -,,Warl,U-level CSRs may have WARL fields.,"(There is only JVT, and must be handled by the Zc vplan. Link to cov here still.)",Other,N/A,N/A,"A: ??? -COV: ???",Waiting for Zc vplan linkage +,,Warl,U-level CSRs may have WARL fields.,JVT is the only URW CSR. Write and nread operations in User mode must be covered,Check against RM,Constrained-Random,Functional Coverage,"DTC: cv32e40s/tests/programs/custom/zcmt_test :: jvt_rw_m, jvt_rw_u_illegal, jvt_rw_u_legal", ,,MisaU,"""The “U” and “S” bits will be set if there is support for user and supervisor modes respectively.""","Read misa and see that ""U"" is always on. Coverage: Ensure actual csr read instruction read misa.",Assertion Check,"ENV capability, not specific test",Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_misa_bits @@ -101,8 +88,9 @@ COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mscratch_ch COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs DTC: cv32e40s/tests/programs/custom/privilege_test/", -,,Mcsratchcsw,"The clic spec introduces ""conditional swapping"" of mscratch.",(Relevant user-mode related functionality must be handled by the CLIC vplan. Link to cov here still),N/A,N/A,N/A,"A: ??? -COV: ???",Waiting for CLIC vplan linkage. +,,Mcsratchcsw,"The clic spec introduces ""conditional swapping"" of mscratch.",(Relevant user-mode related functionality must be handled by the CLIC vplan. Link to cov here still),N/A,N/A,N/A,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.clic_assert_i.a_mscratchcsw_value +COV: ??? +DTC: cv32e40s/tests/programs/custom/clic :: rw_mscratchcsw, rw_mscratchcsw_illegal",Waiting for CLIC vplan linkage. ,,MppValues,"""xPP fields are WARL fields that can hold only privilege mode x and any implemented privilege mode lower than x"" @@ -137,7 +125,7 @@ COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csr DTC: cv32e40s/tests/programs/custom/privilege_test/", manual,,Jvt,"The vector table jump CSR is accessible and effective in U-mode. ""Smstateen"" applies. Both CSR access and instruction execution is affected.","(Zc vplan should be responsible, but link to coverage here too.)",N/A,N/A,N/A,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_jvt_access -COV: ???",Waiting for Zc vplan linkage +DTC: cv32e40s/tests/programs/custom/zcmt_test", privspec,Traps,SoftwareInterrupts,U-mode software interrupts are not supported.,"Check that the zero-bits in `mie` and `mip` are always zero, and mcause is never S/U-mode software interrupt.",Assertion Check,Constrained-Random,Assertion Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_zeromie A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_zeromip @@ -180,9 +168,8 @@ A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mret_mprv_write A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mret_mprv_poststate A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mprv_poststate", -,,Mepc,"""xRET sets the pc to the value stored in the xepc register.""",(Assumed to be covered by the exceptions vplan. Should apply regardless of privilege mode. Link to coverage here too.),N/A,N/A,N/A,"A: ??? - -COV: ???",Waiting for exceptions vplan linkage. +,,Mepc,"""xRET sets the pc to the value stored in the xepc register.""",(Assumed to be covered by the exceptions vplan. Should apply regardless of privilege mode. Link to coverage here too.),N/A,N/A,N/A,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.clic_assert_i.gen_clic_assertions.a_mret_pc_intended, +A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.clic_assert_i.gen_clic_assertions.a_dret_pc_intended,", ,,TrapsMmode,"""By default, all traps at any privilege level are handled in machine mode,""","Observe traps (interrupts and exceptions) getting triggered while in M-mode and U-mode, ensure the handler always starts in M-mode. Coverage: See rvfi_valid with exception/interrupt, while previous rvfi_valid was U/M. (Works in conjunction with ""TrapMpp"".)",Assertion Check,Constrained-Random,Functional Coverage,"A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_traps_mmode @@ -244,11 +231,8 @@ DTC: cv32e40s/tests/programs/custom/mcounteren_priv_gen_test/", ,,McounterenSet,"""When one of these bits is set, access to the corresponding register is permitted in the next implemented privilege mode (S-mode if implemented, otherwise U-mode).""","Check that mcounteren is MRW WARL(0x0). Coverage: ""mcounteren"" attempt written from M/U mode, ""corresponding register"" attempted read/write from M/U mode. (Let CSRs or Counters vplan have the responsibility, but ""link to coverage"" here.)",Assertion Check,Constrained-Random,Assertion Coverage,A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mcounteren_zeros, -debug,Debug,TriggersAccess,"""The trigger registers, except scontext and hcontext, are only accessible in machine and Debug Mode to prevent untrusted user code from causing entry into Debug Mode without the OS’s permission.""",(Exceptions vplan should handle this. Link to coverage here too.),N/A,N/A,N/A,"A: ??? - -COV: ??? - -DTC: cv32e40s/tests/programs/custom/privilege_test/",Waiting for exceptions vplan linkage. +debug,Debug,TriggersAccess,"""The trigger registers, except scontext and hcontext, are only accessible in machine and Debug Mode to prevent untrusted user code from causing entry into Debug Mode without the OS’s permission.""",(Exceptions vplan should handle this. Link to coverage here too.),N/A,N/A,N/A,"A: a_dt_no_access_to_tdata_in_umode +DTC: cv32e40s/tests/programs/custom/privilege_test/", ,,EbreakuOff,"""ebreak instructions in U-mode behave as described in the Privileged Spec.""","Have dcsr.ebreaku=0, be in U-mode, execute ebreak, ensure ""normal"" ebreak behavior and no debug entry. Note: Only need to check that correct exception occurs, priv spec exception details should be part of the Exceptions vplan.",Assertion Check,Constrained-Random,Assertion Coverage,"A: A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_ebreaku_off_cause @@ -273,27 +257,17 @@ COV: ??? DTC: cv32e40s/tests/programs/custom/debug_priv_test/", ,,Mcontrol6Umode0,"""When set, enable this trigger in U-mode."" -With ""mcontrol6.u=0"" trigger condition should not be acted upon.",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A: ??? - -COV: ???",Waiting for debug vplan linkage. +With ""mcontrol6.u=0"" trigger condition should not be acted upon.",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A:a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_tie_offs_*", ,,Mcontrol6Umode1,"""When set, enable this trigger in U-mode."" -With ""mcontrol6.u=1"" trigger condition should be acted upon.",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A: ??? - -COV: ???",Waiting for debug vplan linkage. +With ""mcontrol6.u=1"" trigger condition should be acted upon.",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A:a_dt_instr_trigger_hit_*, a_dt_load_trigger_hit_*, a_dt_store_trigger_hit_*, a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_tie_offs_*", ,,EtriggerUmode0,"""When set, enable this trigger for exceptions that are taken from U mode."" -With ""etrigger.u=0"" trigger condition should not be acted upon.",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A: ??? - -COV: ???",Waiting for debug vplan linkage. +With ""etrigger.u=0"" trigger condition should not be acted upon.",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A: a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_warl_tselect, a_dt_warl_tdata1_general, a_dt_warl_tdata1_m2, a_dt_warl_tdata1_etrigger, a_dt_warl_tdata1_m6, a_dt_warl_tdata1_disabled, a_dt_warl_tdata2_etrigger, a_dt_warl_tinfo. ", ,,EtriggerUmode1,"""When set, enable this trigger for exceptions that are taken from U mode."" -With ""etrigger.u=1"" trigger condition should be acted upon.",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A: ??? - -COV: ???",Waiting for debug vplan linkage. -,,TriggersMmode,"(Same as Mcontrol6 and Triggers above, but for "".m"" bit.)",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A: ??? - -COV: ???",Waiting for debug vplan linkage. +With ""etrigger.u=1"" trigger condition should be acted upon.",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A: a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_warl_tselect, a_dt_warl_tdata1_general, a_dt_warl_tdata1_m2, a_dt_warl_tdata1_etrigger, a_dt_warl_tdata1_m6, a_dt_warl_tdata1_disabled, a_dt_warl_tdata2_etrigger, a_dt_warl_tinfo. ", +,,TriggersMmode,"(Same as Mcontrol6 and Triggers above, but for "".m"" bit.)",(Is the responsibility of the debug/triggers vplan. Link to coverage here too.),Other,Other,N/A,"A: a_dt_exception_trigger_hit_*, a_dt_enter_dbg_reason, a_dt_warl_tselect, a_dt_warl_tdata1_general, a_dt_warl_tdata1_m2, a_dt_warl_tdata1_etrigger, a_dt_warl_tdata1_m6, a_dt_warl_tdata1_disabled, a_dt_warl_tdata2_etrigger, a_dt_warl_tinfo. ", ,,ExecuteMmode,"""All operations are executed with machine mode privilege […]""","Ensure that all rvfi retirements in D-mode also shows M-mode. Additionally, check that loads/stores act as if M-mode and that CSRs are accessible as in M-mode. @@ -316,9 +290,6 @@ COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_dmode_mp COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_dmode_loadstore_mprv_mpp", ,,Relaxedpriv,"""Full permission checks, or a relaxed set of permission checks, will apply according to relaxedpriv.""","(This field is in a DM registers and pertains to subsystem integration, not the core itself.)",N/A,N/A,N/A,N/A, -,,UnspecifiedBehav,"""Almost all instructions that change the privilege mode have unspecified behavior. This includes ecall, mret, sret, and uret.""",(The behavior is specified in the user manual. But the effects are debug-specific and not user-mode-specific so it is the responsibility of the debug vplan. Link to coverage here too.),N/A,N/A,N/A,"A: ??? - -COV: ???",Waiting for debug vplan linkage. ,,ResumePriv,"""When a hart resumes [...] The current privilege mode and virtualization mode are changed to that specified by prv and v."" ""prv [...] A debugger can change this value to change the hart’s privilege mode when exiting Debug Mode."" @@ -367,9 +338,6 @@ COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_prv_support COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.gen_try_set_prv[*].cov_try_set_prv DTC: cv32e40s/tests/programs/custom/debug_priv_test/", -,,NativeTriggers,"""Triggers can be used for native debugging when action =0. If supported by the hart and desired by the debugger, triggers will often be programmed to have m=0 so that when they fire they cause a breakpoint exception to trap to a more privileged mode.""",(Must be covered by the debug/triggers vplan. But link to coverage here too.),N/A,N/A,N/A,"A: ??? - -COV: ???",Waiting for debug vplan linkage. ,,Mprven0Simulate,"""If hardware ties mprven to 0 then the external debugger is expected to simulate all the effects of MPRV, including any extensions that affect memory accesses. For these reasons it is recommended to tie mprven to 1.""","(""mprven"" is not tied 0.)",N/A,N/A,N/A,N/A, ,,Mprven0Ignore,"""mprven 0: MPRV in mstatus is ignored in Debug Mode.""","(mprven is tied ""1"". Handled by ExecuteMprven above.)",N/A,N/A,N/A,N/A, ,,,,,,,,, diff --git a/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.json b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.json new file mode 100644 index 0000000000..a9adf6e7df --- /dev/null +++ b/cv32e40s/docs/VerifPlans/Simulation/privileged_spec/CV32E40S_UserMode.json @@ -0,0 +1,806 @@ +[ + { + "Requirement Location": "privspec", + "Feature": "Misc", + "Sub Feature": "SupportedLevels", + "Feature Description": "\"At any time, a RISC-V hardware thread (hart) is running at some privilege level encoded as a mode\nin one or more CSRs [User, Supervisor, (Reserved), Machine]\"", + "Verification Goal": "Run all supported levels (U-mode, M-mode); ensure no unsupported levels can be run (S-mode, reserved).\n\nCoverage: Attempts to set various modes.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_no_unsupported_modes\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_umode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mmode\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "ResetMode", + "Feature Description": "\"M-mode [...] is the first mode entered at reset.\"", + "Verification Goal": "Wait for reset to end, ensure that the core is in M-mode.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_initial_mode\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "Refetch", + "Feature Description": "Before a mode change, instructions can have been prefetched and exist in the pipeline but the fetching was done in a different mode than what is changed to. This should not allow for privilege escalation so the instructions must be refetched.", + "Verification Goal": "Checking: Handled by \"InstrProt\" below.\n\nCoverage: Instr fetched twice (same pc, different prot).", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_umode_notrap\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_mmode_notrap\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_umode_trap\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cov_refetch_as_mmode_trap", + "Comment": "" + }, + { + "Requirement Location": "obi", + "Feature": "Misc", + "Sub Feature": "InstrProt", + "Feature Description": "\"prot[2:1]\nUser/Application (2\u2019b00), Supervisor (2\u2019b01), Reserved (2\u2019b10), Machine (2\u2019b11)\nThis matches the privilege levels from [RISC-V-PRIV].\"", + "Verification Goal": "Track prot[2:1] on instruction fetches on obi, observe retirements on rvfi, ensure the privilege mode of the instruction's execution matches what it was fetched as on obi.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_instr_prot\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_instr_prot_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prot_iside_legal", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "DataProt", + "Feature Description": "\"prot[2:1]\nUser/Application (2\u2019b00), Supervisor (2\u2019b01), Reserved (2\u2019b10), Machine (2\u2019b11)\nThis matches the privilege levels from [RISC-V-PRIV].\"", + "Verification Goal": "Track prot[2:1] on data loads/stores, observe retirements on rvfi, ensure the effective privilege mode of the retirement matches what was used on obi.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_prot_dside_legal\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_data_prot_equal", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Misc", + "Sub Feature": "DbgProt", + "Feature Description": "Since dmode execs as mmode, and obi has corresponding signals, the relationship should be visible on obi.", + "Verification Goal": "When obi has a transaction with `dbg` high, check that `prot[2:1]` is M-mode on I-side, and \"effective\" mode on D-side.\n\nNote: Consider checking before MPU", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_iside\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_dbg_prot_dside", + "Comment": "" + }, + { + "Requirement Location": "privspec", + "Feature": "CSRs", + "Sub Feature": "IllegalAccess", + "Feature Description": "\"Attempts to access a CSR without appropriate privilege level [\u2026] also raise illegal instruction exceptions\"", + "Verification Goal": "Try all kinds of accesses (R, W, RW, S, C, \u2026) to all M-level CSRs while in U-level; ensure illegal instruction exception happens.\n\n(Hint: Assert RVFI vs csr[9:8])\n\nFunctional coverage can do a full cross of modes vs all CSRs.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_illegal_csr_access\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr\n\nDTC: cv32e40s/tests/programs/custom/csr_priv_gen_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "AccessLevel", + "Feature Description": "\"The next two bits (csr[9:8]) encode the lowest privilege level that can access the CSR.\"", + "Verification Goal": "Try all kinds of accesses to all implemented M-level and U-level CSRs while in M-mode and U-mode (cross), ensure appropriate access grant/deny.", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "COV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "Warl", + "Feature Description": "U-level CSRs may have WARL fields.", + "Verification Goal": "JVT is the only URW CSR. Write and nread operations in User mode must be covered", + "Pass/Fail Criteria": "Check against RM", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "DTC: cv32e40s/tests/programs/custom/zcmt_test :: jvt_rw_m, jvt_rw_u_illegal, jvt_rw_u_legal", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MisaU", + "Feature Description": "\"The \u201cU\u201d and \u201cS\u201d bits will be set if there is support for user and supervisor modes respectively.\"", + "Verification Goal": "Read misa and see that \"U\" is always on.\n\nCoverage: Ensure actual csr read instruction read misa.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_misa_bits\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MisaN", + "Feature Description": "\"N Tentatively reserved for User-Level Interrupts extension\"", + "Verification Goal": "Read misa and see that \"N\" is always off.\n\nCoverage: Ensure actual csr read instruction read misa.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_misa_bits\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "UserExtensions", + "Feature Description": "\"If both XS and FS are hardwired to zero, then SD is also always zero.\"\n\n\"In systems without additional user extensions requiring new state, the XS field is hardwired to zero.\"\n\n\"If neither the F extension nor S-mode is implemented, then FS is hardwired to zero.\"\n\nNone of those 3 are implemented, so they should all be zero.", + "Verification Goal": "Check that mstatus {XS, FS, SD} are all 0.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "ENV capability, not specific test", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_umode_extensions\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MscratchReliable", + "Feature Description": "\"the OS can rely on holding a value in the mscratch register while the user context\nis running.\"", + "Verification Goal": "Check that mscratch never changes in U-mode.\n\n(CLIC vplan must handle \"mscratchcsw\" and \"mscratchcswl\", but link to coverage of that here too.)\n\nCoverage: See that mscratch is attempted written from umode.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mscratch_reliable\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mscratch_changing\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "Mcsratchcsw", + "Feature Description": "The clic spec introduces \"conditional swapping\" of mscratch.", + "Verification Goal": "(Relevant user-mode related functionality must be handled by the CLIC vplan. Link to cov here still)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.clic_assert_i.a_mscratchcsw_value\nCOV: ???\nDTC: cv32e40s/tests/programs/custom/clic :: rw_mscratchcsw, rw_mscratchcsw_illegal", + "Comment": "Waiting for CLIC vplan linkage." + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MppValues", + "Feature Description": "\"xPP fields are WARL fields that can hold only privilege mode x and any implemented privilege\nmode lower than x\"\n\n\"M-mode software can determine whether a privilege mode is implemented by writing that mode to MPP then reading it back.\"", + "Verification Goal": "Checking: Check that MPP can hold \"M\" and \"U\" and that it can hold nothing else.\n\nCoverage: Write and read instrs with each 2-bit permutation.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mpp_mode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mpp_umode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.cov_mpp_mmode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.gen_try_goto_mode[*].cov_try_goto_mode\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.gen_try_goto_mode[*].cov_write_mpp", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "SppValues", + "Feature Description": "\"If privilege mode x is not implemented, then xPP must be hardwired to 0.\"", + "Verification Goal": "Check that SPP is always 0.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_spp_zero", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "MedelegMideleg", + "Feature Description": "\"In systems without S-mode, the medeleg and mideleg registers should not exist.\"", + "Verification Goal": "Attempt access to these CSRs.\n\nCoverage: Instrs attempt (R/W) access.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_medeleg_mideleg\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_csrreadwrite_mode_umodecsrs\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "CSRs", + "Sub Feature": "Mcounteren", + "Feature Description": "\"In systems with U-mode, the mcounteren must be implemented\"", + "Verification Goal": "Attempt access to this CSR. (See Counters section below too.)\n\nCoverage: Instrs attempt (R/W) access.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_mcounteren_access\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "n-ext", + "Feature": "CSRs", + "Sub Feature": "NExt", + "Feature Description": "N-extension CSRs used to be supported earlier in the legacy of the core's source code.", + "Verification Goal": "Check that the old N-ext CSRs are not accessible (ustatus, uie, utvec, uscratch, uepc, ucause, utval, uip), and traps upon access attempts.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_next_csrs\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mode_csraddr\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "manual", + "Feature": "CSRs", + "Sub Feature": "Jvt", + "Feature Description": "The vector table jump CSR is accessible and effective in U-mode. \"Smstateen\" applies. Both CSR access and instruction execution is affected.", + "Verification Goal": "(Zc vplan should be responsible, but link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_jvt_access\n\nDTC: cv32e40s/tests/programs/custom/zcmt_test", + "Comment": "" + }, + { + "Requirement Location": "privspec", + "Feature": "Traps", + "Sub Feature": "SoftwareInterrupts", + "Feature Description": "U-mode software interrupts are not supported.", + "Verification Goal": "Check that the zero-bits in `mie` and `mip` are always zero, and mcause is never S/U-mode software interrupt.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Assertion Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_zeromie\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_zeromip\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_softwareinterrupts_mcausemode\n\nDTC: cv32e40s/tests/programs/custom/privilege_test/", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "TrapMpp", + "Feature Description": "\"When a trap is taken from privilege mode y into privilege mode x, [\u2026] xPP is set to y.\"", + "Verification Goal": "Checking: Be in mode y, observe exception and interrupt, check MPP is mode y.\n\nCover: Cross U/M with Exc/Int.", + "Pass/Fail Criteria": "Assertion Check", + "Test Type": "Constrained-Random", + "Coverage Method": "Functional Coverage", + "Link to Coverage": "A: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_trap_mpp_exception\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_trap_mpp_general\n\nA: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_assert_i.a_trap_mpp_debug\n\nCOV: uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.umode_cov_i.cg_inst.x_mpp_excint", + "Comment": "" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "HigherEnabled", + "Feature Description": "\"Interrupts for higher-privilege modes, y>x ,are always globally enabled regardless of the setting of the global yIE bit for the higher-privilege mode.\"", + "Verification Goal": "(Responsibility of Interrupts and Clic vplans. Link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\nCOV: ???", + "Comment": "Waiting for interrupts vplans" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "HigherDisable", + "Feature Description": "\"Higher-privilege-level code can use separate per-interrupt enable bits to disable selected higher-privilege-mode interrupts before ceding control to a lower-privilege mode.\"", + "Verification Goal": "(Responsibility of Interrupts and Clic vplans. Link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\nCOV: ???", + "Comment": "Waiting for interrupts vplans" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "HigherNone", + "Feature Description": "\"A higher-privilege mode y could disable all of its interrupts before ceding control to a lower-privilege mode\"", + "Verification Goal": "(Responsibility of Interrupts and Clic vplans. Link to coverage here too.)", + "Pass/Fail Criteria": "N/A", + "Test Type": "N/A", + "Coverage Method": "N/A", + "Link to Coverage": "A: ???\n\nCOV: ???", + "Comment": "Waiting for interrupts vplans" + }, + { + "Requirement Location": "", + "Feature": "Traps", + "Sub Feature": "LowerLevel", + "Feature Description": "\"Interrupts for lower-privilege modes, w= cnt_rvfi_ifaulthandl) - else `uvm_error(info_tag, "more instr fault handler than actual err retirements"); - if ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) != cnt_rvfi_ifaulthandl) - `uvm_warning(info_tag, $sformatf("err retires (%0d) != handler entries (%0d)", (cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug), cnt_rvfi_ifaulthandl)); - - // Check OBI I-side vs RVFI - assert (cnt_obii_err >= cnt_rvfi_ifaulthandl) - else `uvm_error(info_tag, $sformatf("less I-side err (%0d) than exception handling (%0d)", cnt_obii_err, cnt_rvfi_ifaulthandl)); - if (cnt_obii_err < cnt_rvfi_errmatch) - `uvm_warning(info_tag, "more retired errs than fetches"); - - // Check RVFI (just a sanity check) - if (cnt_rvfi_trn == 0) - `uvm_warning(info_tag, "zero rvfi transactions received"); - - // Inform about the end state - `uvm_info(info_tag, $sformatf("received %0d D-side 'err' transactions", cnt_obid_err), UVM_NONE) - `uvm_info(info_tag, $sformatf("received %0d D-side 'first err' transactions", cnt_obid_firsterr), UVM_NONE) - `uvm_info(info_tag, $sformatf("observed %0d rvfi nmi handler entries", cnt_rvfi_nmihandl), UVM_NONE) - `uvm_info(info_tag, $sformatf("received %0d I-side 'err' transactions", cnt_obii_err), UVM_NONE) - `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions", cnt_rvfi_errmatch), UVM_NONE) - `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions during debug", cnt_rvfi_errmatch_debug), UVM_NONE) - `uvm_info(info_tag, $sformatf("observed %0d rvfi ifault handler entries", cnt_rvfi_ifaulthandl), UVM_NONE) - -endfunction : check_phase - - -function bit uvme_cv32e40s_buserr_sb_c::should_instr_err(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_trn); - // This function may have corners that will incorrectly trigger errors when - // an error transaction is followed by a non-error transaction to the same address. - // To avoid this the scoreboard needs to be re-written to not rely on the addresses to identify transactions - - uvma_obi_memory_addr_l_t err_addrs[$]; + // TODO: silabs-hfegran needs rewrite - currently gives frequent false positives + //assert ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) >= cnt_rvfi_ifaulthandl) + // else `uvm_error(info_tag, "more instr fault handler than actual err retirements"); + if ((cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug) != cnt_rvfi_ifaulthandl) + `uvm_warning(info_tag, $sformatf("err retires (%0d) != handler entries (%0d)", (cnt_rvfi_errmatch - cnt_rvfi_errmatch_debug), cnt_rvfi_ifaulthandl)); + + // Check OBI I-side vs RVFI + assert (cnt_obii_err >= cnt_rvfi_ifaulthandl) + else `uvm_error(info_tag, $sformatf("less I-side err (%0d) than exception handling (%0d)", cnt_obii_err, cnt_rvfi_ifaulthandl)); + if (cnt_obii_err < cnt_rvfi_errmatch) + `uvm_warning(info_tag, "more retired errs than fetches"); + + // Check RVFI (just a sanity check) + if (cnt_rvfi_trn == 0) + `uvm_warning(info_tag, "zero rvfi transactions received"); + + // Inform about the end state + `uvm_info(info_tag, $sformatf("received %0d D-side 'err' transactions", cnt_obid_err), UVM_NONE) + `uvm_info(info_tag, $sformatf("received %0d D-side 'first err' transactions", cnt_obid_firsterr), UVM_NONE) + `uvm_info(info_tag, $sformatf("observed %0d rvfi nmi handler entries", cnt_rvfi_nmihandl), UVM_NONE) + `uvm_info(info_tag, $sformatf("received %0d I-side 'err' transactions", cnt_obii_err), UVM_NONE) + `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions", cnt_rvfi_errmatch), UVM_NONE) + `uvm_info(info_tag, $sformatf("retired %0d expectedly ifault instructions during debug", cnt_rvfi_errmatch_debug), UVM_NONE) + `uvm_info(info_tag, $sformatf("observed %0d rvfi ifault handler entries", cnt_rvfi_ifaulthandl), UVM_NONE) + + endfunction : check_phase + + + function bit uvme_cv32e40s_buserr_sb_c::should_instr_err(uvma_rvfi_instr_seq_item_c#(ILEN,XLEN) rvfi_trn); + // This function may have corners that will incorrectly trigger errors when + // an error transaction is followed by a non-error transaction to the same address. + // To avoid this the scoreboard needs to be re-written to not rely on the addresses to identify transactions + + uvma_obi_memory_addr_l_t err_addrs[$]; bit [31:0] rvfi_addr = rvfi_trn.pc_rdata; // Extract all addrs from queue of I-side OBI "err" transactions diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_cfg.sv b/cv32e40s/env/uvme/uvme_cv32e40s_cfg.sv index 47348aa9db..48804c2db2 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_cfg.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_cfg.sv @@ -297,6 +297,8 @@ class uvme_cv32e40s_cfg_c extends uvma_core_cntrl_cfg_c; isacov_cfg.cov_model_enabled == 1; debug_cfg.cov_model_enabled == 1; pma_cfg.cov_model_enabled == 1; + clic_cfg.cov_model_enabled == clic_interrupt_enable; + interrupt_cfg.cov_model_enabled == basic_interrupt_enable; obi_memory_instr_cfg.cov_model_enabled == 1; obi_memory_data_cfg.cov_model_enabled == 1; } diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_env.sv b/cv32e40s/env/uvme/uvme_cv32e40s_env.sv index c164d9ac74..caf1983d17 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_env.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_env.sv @@ -530,12 +530,14 @@ function void uvme_cv32e40s_env_c::connect_coverage_model(); isacov_agent.monitor.ap.connect(cov_model.exceptions_covg.isacov_mon_export); isacov_agent.monitor.ap.connect(cov_model.counters_covg.isacov_mon_export); + isacov_agent.monitor.ap.connect(cov_model.interrupt_covg.isacov_mon_export); + isacov_agent.monitor.ap.connect(cov_model.clic_covg.isacov_mon_export); obi_memory_data_agent.mon_ap.connect(pma_agent.monitor.obi_d_export); foreach (rvfi_agent.instr_mon_ap[i]) begin rvfi_agent.instr_mon_ap[i].connect(isacov_agent.monitor.rvfi_instr_imp); rvfi_agent.instr_mon_ap[i].connect(cov_model.interrupt_covg.interrupt_mon_export); - //rvfi_agent.instr_mon_ap[i].connect(cov_model.clic_covg.clic_mon_export); // TODO: silabs-hfegran + rvfi_agent.instr_mon_ap[i].connect(cov_model.clic_covg.clic_mon_export); rvfi_agent.instr_mon_ap[i].connect(pma_agent.monitor.rvfi_instr_export); end diff --git a/cv32e40s/env/uvme/uvme_cv32e40s_pkg.sv b/cv32e40s/env/uvme/uvme_cv32e40s_pkg.sv index bbe32f5ff2..6134e59ee0 100644 --- a/cv32e40s/env/uvme/uvme_cv32e40s_pkg.sv +++ b/cv32e40s/env/uvme/uvme_cv32e40s_pkg.sv @@ -92,6 +92,7 @@ package uvme_cv32e40s_pkg; `include "uvma_cv32e40s_core_cntrl_drv.sv" `include "uvma_cv32e40s_core_cntrl_agent.sv" `include "uvme_interrupt_covg.sv" + `include "uvme_clic_covg.sv" `include "uvme_debug_covg.sv" `include "uvme_exceptions_covg.sv" `include "uvme_counters_covg.sv" diff --git a/cv32e40s/fv/README.md b/cv32e40s/fv/README.md index eee8653c39..87470a6e15 100644 --- a/cv32e40s/fv/README.md +++ b/cv32e40s/fv/README.md @@ -7,12 +7,15 @@ Read the Makefile for more info. ## Usage Examples -Simply: +Simple example: ``` make jg ``` -More advanced: +Advanced examples: ``` -make jg USER_DEFINES=+define+MYDEFINE USER_INCDIRS=+incdir+MYINCDIR JG_EXTRAS="" +make jg USER_DEFINES=+define+MYDEFINE USER_INCDIRS=+incdir+MYINCDIR +make jg JG_EXTRAS="" +make jg USER_DEFINES=+define+COREV_ASSERT_OFF +make jg USER_DEFINES=+define+DEFONE+DEFTWO+DEFTHREE ``` diff --git a/cv32e40s/fv/defines.sv b/cv32e40s/fv/defines.sv index 7ccd5dcd3d..9836ac7cd3 100644 --- a/cv32e40s/fv/defines.sv +++ b/cv32e40s/fv/defines.sv @@ -1,4 +1 @@ `define FORMAL 1 - -// TODO:silabs-robin Re-enable core asserts. -`define COREV_ASSERT_OFF 1 diff --git a/cv32e40s/regress/cv32e40s_full.yaml b/cv32e40s/regress/cv32e40s_full.yaml index 10e46a74c2..66ba231d96 100644 --- a/cv32e40s/regress/cv32e40s_full.yaml +++ b/cv32e40s/regress/cv32e40s_full.yaml @@ -104,6 +104,11 @@ builds: cfg: debug_trigger_cfg4 dir: cv32e40s/sim/uvmt + uvmt_cv32e40s_xsecure_disable_std: + cmd: make comp_corev-dv comp + cfg: xsecure_disable_std + dir: cv32e40s/sim/uvmt + # List of tests tests: @@ -207,189 +212,183 @@ tests: corev_rand_arithmetic_base_test: description: Generated corev-dv arithmetic test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_xsecure_disable_std ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_arithmetic_base_test num: 4 corev_rand_instr_test: description: Generated corev-dv random instruction test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_xsecure_disable_std ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_instr_test num: 5 corev_rand_instr_long_stall: description: Generated corev-dv random instruction test with long stalls - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_instr_long_stall num: 2 corev_rand_illegal_instr_test: description: Generated corev-dv random instruction test with illegal instructions - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_illegal_instr_test num: 5 corev_rand_jump_stress_test: description: Generated corev-dv jump stress test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_jump_stress_test num: 5 corev_rand_interrupt: description: Generated corev-dv random interrupt test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt num: 5 corev_rand_debug: description: Generated corev-dv random debug test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_debug num: 5 corev_rand_debug_single_step: description: debug random test with single-stepping - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_debug_single_step num: 5 corev_rand_debug_ebreak: description: debug random test with ebreaks from ROM - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_debug_ebreak num: 5 corev_rand_interrupt_wfi: description: Generated corev-dv random interrupt WFI test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi num: 5 corev_rand_fencei: description: Generated corev-dv random fence.i test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_fencei num: 2 corev_rand_interrupt_wfi_mem_stress: description: Generated corev-dv random interrupt WFI test with memory stress - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_wfi_mem_stress num: 5 corev_rand_interrupt_debug: description: Generated corev-dv random interrupt WFI test with debug - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_debug num: 5 corev_rand_interrupt_exception: description: Generated corev-dv random interrupt WFI test with exceptions - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_exception num: 5 corev_rand_interrupt_nested: description: Generated corev-dv random interrupt WFI test with random nested interrupts - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_interrupt_nested num: 5 corev_rand_pma_test: description: Generated corev-dv random PMA test - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5 ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_pma_test num: 3 corev_rand_instr_obi_err: description: Random OBI instruction bus error test - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_instr_obi_err num: 6 corev_rand_instr_obi_err_debug: description: Random OBI instruction bus error test with debug - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_instr_obi_err_debug num: 6 corev_rand_data_obi_err: description: Random OBI data bus error test - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_data_obi_err num: 6 corev_rand_data_obi_err_debug: description: Random OBI data bus error test with debug - builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s_pma_1, uvmt_cv32e40s_pma_2, uvmt_cv32e40s_pma_3, uvmt_cv32e40s_pma_4, uvmt_cv32e40s_pma_5, uvmt_cv32e40s_dummy_instr, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make gen_corev-dv test TEST=corev_rand_data_obi_err_debug num: 10 illegal: description: Illegal-riscv-tests - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=illegal fibonacci: description: Fibonacci test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=fibonacci misalign: description: Misalign test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=misalign dhrystone: description: Dhrystone test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=dhrystone debug_test2: description: Debug Test 2 - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=debug_test2 debug_test_reset: description: Debug reset test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=debug_test_reset - debug_test_trigger: - description: Debug trigger test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] - dir: cv32e40s/sim/uvmt - cmd: make test TEST=debug_test_trigger - debug_test_boot_set: description: Debug test target debug_req at BOOT_SET - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=debug_test_boot_set num: 10 @@ -408,31 +407,37 @@ tests: clic: description: CLIC interrupt test - builds: [ uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=clic isa_fcov_holes: description: ISA function coverage test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=isa_fcov_holes + cov_holes_generic: + description: Generic coverage closure test for known coverage holes + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=cov_holes_generic + instr_bus_error: description: Directed instruction bus error test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=instr_bus_error data_bus_error: description: Directed data bus error test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=data_bus_error load_store_rs1_zero: description: Directed rs1 coverage test - builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_clic ] dir: cv32e40s/sim/uvmt cmd: make test TEST=load_store_rs1_zero @@ -449,90 +454,125 @@ tests: pma: description: PMA directed tests - builds: [uvmt_cv32e40s_pma] + builds: [ uvmt_cv32e40s_pma ] dir: cv32e40s/sim/uvmt cmd: make test TEST=pma pma_0reg: description: PMA directed tests with zero registers - builds: [uvmt_cv32e40s] + builds: [ uvmt_cv32e40s ] dir: cv32e40s/sim/uvmt cmd: make test TEST=pma_0reg pma_debug: description: PMA directed tests relating to debug - builds: [uvmt_cv32e40s_pma_debug] + builds: [ uvmt_cv32e40s_pma_debug ] dir: cv32e40s/sim/uvmt cmd: make test TEST=pma_debug pmp: description: PMP directed tests - builds: [uvmt_cv32e40s_pmp] + builds: [ uvmt_cv32e40s_pmp ] dir: cv32e40s/sim/uvmt cmd: make test TEST=pmp + pmp_csr_access_test: + description: Test to write to all bits of all 64 PMP CSRs + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=pmp_csr_access_test + b_ext_test: description: Directed Zb extension test - builds: [ uvmt_cv32e40s_b_ext_all] + builds: [ uvmt_cv32e40s_b_ext_all ] dir: cv32e40s/sim/uvmt cmd: make test TEST=b_ext_test csr_priv_gen_test: description: Generated U-mode CSR access tests - builds: [uvmt_cv32e40s_pmp] + builds: [ uvmt_cv32e40s_pmp ] dir: cv32e40s/sim/uvmt cmd: make test TEST=csr_priv_gen_test # custom_priv_gen_test: # description: Generated U-mode custom instr tests -# builds: [uvmt_cv32e40s_pmp] +# builds: [ uvmt_cv32e40s_pmp ] # dir: cv32e40s/sim/uvmt # cmd: make test TEST=custom_priv_gen_test # TODO:silabs-robin This test times out. debug_priv_test: description: D-mode vs U-mode tests - builds: [uvmt_cv32e40s_pmp] + builds: [ uvmt_cv32e40s_pmp ] dir: cv32e40s/sim/uvmt cmd: make test TEST=debug_priv_test interrupt_priv_test: description: Interrupts vs U-mode tests - builds: [uvmt_cv32e40s_pmp] + builds: [ uvmt_cv32e40s_pmp ] dir: cv32e40s/sim/uvmt cmd: make test TEST=interrupt_priv_test mcounteren_priv_gen_test: description: U-mode access and privilege instructions - builds: [uvmt_cv32e40s_pmp] + builds: [ uvmt_cv32e40s_pmp ] dir: cv32e40s/sim/uvmt cmd: make test TEST=mcounteren_priv_gen_test privilege_test: description: Privilege mode accesses and csr behavior - builds: [uvmt_cv32e40s_pmp] + builds: [ uvmt_cv32e40s_pmp ] dir: cv32e40s/sim/uvmt cmd: make test TEST=privilege_test zc_test: description: Zc directed test - builds: [uvmt_cv32e40s, uvmt_cv32e40s_pma_1] + builds: [ uvmt_cv32e40s, uvmt_cv32e40s_pma_1 ] dir: cv32e40s/sim/uvmt cmd: make test TEST=zc_test num: 5 + pushpop_debug_triggers: + description: Zc push/pop vs debug triggers + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=pushpop_debug_triggers + debug_test_trigger: description: Test of debug triggers - builds: [uvmt_cv32e40s_debug_trigger_cfg1, - uvmt_cv32e40s_debug_trigger_cfg2, - uvmt_cv32e40s_debug_trigger_cfg3, - uvmt_cv32e40s_debug_trigger_cfg4] + builds: [ uvmt_cv32e40s_debug_trigger_cfg1, + uvmt_cv32e40s_debug_trigger_cfg2, + uvmt_cv32e40s_debug_trigger_cfg3, + uvmt_cv32e40s_debug_trigger_cfg4 ] dir: cv32e40s/sim/uvmt cmd: make test TEST=debug_test_trigger debug_test_0_triggers: description: Test of debug triggers - builds: [uvmt_cv32e40s_debug_trigger_cfg0] + builds: [ uvmt_cv32e40s_debug_trigger_cfg0 ] dir: cv32e40s/sim/uvmt cmd: make test TEST=debug_test_0_triggers + wfe_test: + description: Short directed wfe test + builds: [ uvmt_cv32e40s_clic, uvmt_cv32e40s ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=wfe_test + + xsecure_test: + description: xsecure test + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=xsecure_test + + xsecure_csrs: + description: xsecure csr test + builds: [ uvmt_cv32e40s_clic, uvmt_cv32e40s ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=xsecure_csrs + + zcmt_test: + description: zcmt user-mode, mstateen0 directed test + builds: [ uvmt_cv32e40s_clic ] + dir: cv32e40s/sim/uvmt + cmd: make test TEST=zcmt_test diff --git a/cv32e40s/sim/ExternalRepos.mk b/cv32e40s/sim/ExternalRepos.mk index fa7a997dbe..d2cb18a691 100644 --- a/cv32e40s/sim/ExternalRepos.mk +++ b/cv32e40s/sim/ExternalRepos.mk @@ -15,7 +15,7 @@ export SHELL = /bin/bash CV_CORE_REPO ?= https://github.com/openhwgroup/cv32e40s CV_CORE_BRANCH ?= master -CV_CORE_HASH ?= 9a66cb971edca4613d5df12a869db3511ee24a75 +CV_CORE_HASH ?= 61e1535c8d5e3086a88cc03dc8d984ba274b81f0 CV_CORE_TAG ?= none #RISCVDV_REPO ?= https://github.com/google/riscv-dv diff --git a/cv32e40s/sim/tools/xrun/covfile.tcl b/cv32e40s/sim/tools/xrun/covfile.tcl index 7dac801908..7b7e375990 100644 --- a/cv32e40s/sim/tools/xrun/covfile.tcl +++ b/cv32e40s/sim/tools/xrun/covfile.tcl @@ -48,6 +48,9 @@ set_expr_coverable_statements -all # Toggle coverage smart refinement (refinement for toggle with traverse hierarchy) set_toggle_smart_refinement +# Score toggle coverage for ports only +set_toggle_portsonly + # ---------------------------------------------------------------------------------- # Covergroup coverage configuration # ---------------------------------------------------------------------------------- diff --git a/cv32e40s/sim/tools/xrun/cv32e40s.manual_expression_cov_todo.vRefine b/cv32e40s/sim/tools/xrun/cv32e40s.manual_expression_cov_todo.vRefine new file mode 100644 index 0000000000..1a5d0be46d --- /dev/null +++ b/cv32e40s/sim/tools/xrun/cv32e40s.manual_expression_cov_todo.vRefine @@ -0,0 +1,164 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/cv32e40s/sim/tools/xrun/cv32e40s.xsecure_trigger_express_cov.vRefine b/cv32e40s/sim/tools/xrun/cv32e40s.xsecure_trigger_express_cov.vRefine new file mode 100644 index 0000000000..bc1bc137da --- /dev/null +++ b/cv32e40s/sim/tools/xrun/cv32e40s.xsecure_trigger_express_cov.vRefine @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + \ No newline at end of file diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_fencei_assert.sv b/cv32e40s/tb/assertions/uvmt_cv32e40s_fencei_assert.sv similarity index 84% rename from cv32e40s/tb/uvmt/uvmt_cv32e40s_fencei_assert.sv rename to cv32e40s/tb/assertions/uvmt_cv32e40s_fencei_assert.sv index 0b99374db5..dbc2e2fe99 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_fencei_assert.sv +++ b/cv32e40s/tb/assertions/uvmt_cv32e40s_fencei_assert.sv @@ -48,12 +48,10 @@ module uvmt_cv32e40s_fencei_assert input wire data_gnt_i, input wire data_rvalid_i, - input wire rvfi_valid, - input wire rvfi_intr, - input wire rvfi_dbg_mode, - input wire [31:0] rvfi_insn + uvma_rvfi_instr_if_t rvfi_if ); + default clocking @(posedge clk_i); endclocking default disable iff !rst_ni; @@ -65,6 +63,7 @@ module uvmt_cv32e40s_fencei_assert localparam int FENCE_IDATA = 32'b 000000000000_00000_000_00000_0001111; localparam int FENCE_IMASK = 32'b 000000000000_00000_111_00000_1111111; + // Helper Signals/Functions logic is_fencei_in_wb; @@ -72,16 +71,17 @@ module uvmt_cv32e40s_fencei_assert logic is_rvfiinstr_fencei; assign is_rvfiinstr_fencei = ( - ((rvfi_insn & FENCEI_IMASK) == FENCEI_IDATA) + rvfi_if.rvfi_valid && + ((rvfi_if.rvfi_insn & FENCEI_IMASK) == FENCEI_IDATA) ); logic is_rvfiinstr_fence; assign is_rvfiinstr_fence = ( - ((rvfi_insn & FENCE_IMASK) == FENCE_IDATA) + ((rvfi_if.rvfi_insn & FENCE_IMASK) == FENCE_IDATA) ); int obi_outstanding; - always @(posedge clk_i, negedge rst_ni) begin + always_ff @(posedge clk_i, negedge rst_ni) begin if (~rst_ni) begin obi_outstanding <= 0; end else if (data_req_o && data_gnt_i && !data_rvalid_i) begin @@ -160,16 +160,18 @@ module uvmt_cv32e40s_fencei_assert a_req_must_rvfi_fencei: assert property ( fencei_flush_req_o - |=> - (rvfi_valid [->1]) ##0 + ##1 + (rvfi_if.rvfi_valid [->1]) + |-> is_rvfiinstr_fencei ) else `uvm_error(info_tag, "A handshake must results in fencei retire"); // (Just a helper/sanity assert complementing the above) a_req_mustnt_rvfi_fence: assert property ( fencei_flush_req_o - |=> - (rvfi_valid [->1]) ##0 + ##1 + (rvfi_if.rvfi_valid [->1]) + |-> !is_rvfiinstr_fence ) else `uvm_error(info_tag, "A handshake must not results in a fence retire"); @@ -186,8 +188,8 @@ module uvmt_cv32e40s_fencei_assert ##0 (instr_addr_o == pc_next) ) or ( // Exception execution - rvfi_valid [->2:3] // retire: fencei, (optionally "rvfi_trap"), interrupt/debug handler - ##0 (rvfi_intr || rvfi_dbg_mode) + rvfi_if.rvfi_valid [->2:3] // retire: fencei, (optionally "rvfi_if.rvfi_trap"), interrupt/debug handler + ##0 (rvfi_if.rvfi_intr || rvfi_if.rvfi_dbg_mode) ); endproperty @@ -216,19 +218,29 @@ module uvmt_cv32e40s_fencei_assert // vplan:BranchInitiated + sequence seq_branch_after_retire_ante; + $fell(fencei_flush_req_o) + ##0 + rvfi_if.rvfi_valid [->2] + ; + endsequence + + sequence seq_branch_after_retire_conse (pc_at_fencei); + (rvfi_if.rvfi_pc_rdata == pc_at_fencei + 32'd 4) + || rvfi_if.rvfi_intr + || rvfi_if.rvfi_dbg_mode + ; + endsequence + property p_branch_after_retire; - int pc_next; + logic [31:0] pc_at_fencei; - (fencei_flush_req_o, pc_next=wb_pc+4) - ##1 !fencei_flush_req_o - |=> - ( - wb_valid [->1:2] - ##0 (wb_pc == pc_next) - ) or ( - rvfi_valid [->2] - ##0 (rvfi_intr || rvfi_dbg_mode) - ); + (fencei_flush_req_o, pc_at_fencei = wb_pc) + ##1 + seq_branch_after_retire_ante + |-> + seq_branch_after_retire_conse (pc_at_fencei) + ; endproperty a_branch_after_retire: assert property ( @@ -236,9 +248,11 @@ module uvmt_cv32e40s_fencei_assert ) else `uvm_error(info_tag, "the pc following fencei did not enter WB"); cov_branch_after_retire: cover property ( - reject_on - (rvfi_intr || rvfi_dbg_mode) - p_branch_after_retire + seq_branch_after_retire_ante + ##0 + ! rvfi_if.rvfi_intr + ##0 + ! rvfi_if.rvfi_dbg_mode ); @@ -250,6 +264,12 @@ module uvmt_cv32e40s_fencei_assert !data_req_o ) else `uvm_error(info_tag, "obi data req shall not happen while fencei is flushing"); + a_flush_pipeline: assert property ( + is_rvfiinstr_fencei + |=> + (! rvfi_if.rvfi_valid)[*3] // (Because, 4-stage.) + ) else `uvm_error(info_tag, "fencei must cause flushing"); + // vplan:MultiCycle @@ -329,6 +349,29 @@ module uvmt_cv32e40s_fencei_assert ) else `uvm_error(info_tag, "fencei_flush_req_o should be held low until write buffer is empty"); + // vplan:StoresVisible + + property p_stores_visible_store_fencei_exec; + logic [31:0] addr; + + rvfi_if.rvfi_valid ##0 + rvfi_if.rvfi_mem_wmask ##0 + (1, addr = rvfi_if.rvfi_mem_addr[31:0]) + ##1 + + (is_rvfiinstr_fencei [->1]) + ##1 + + (rvfi_if.rvfi_valid [->1]) ##0 + (rvfi_if.rvfi_pc_rdata == addr) + ; + endproperty + + cov_stores_visible_store_fencei_exec: cover property ( + p_stores_visible_store_fencei_exec + ); + + // vplan:AckChange covergroup cg_reqack(string name) @(posedge clk_i); diff --git a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_fifo.sv b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_fifo.sv new file mode 100644 index 0000000000..ba0a61bdd8 --- /dev/null +++ b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_fifo.sv @@ -0,0 +1,107 @@ +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 + +/* + +This is a configurable FIFO. +It inputs item_in when add_item is set. +It always outputs the "oldest" fifo item. +It shifts the fifo on the next clock cycle when shift_fifo is set. + +The figure shows how the FIFO behaves: + +t1: | t2: | t3: | +add_item | add_item | !add_item | +&& !shift_fifo | && !shift_fifo | && !shift_fifo | +_____________ | _____________ | _____________ | +| | | | | | | | | | | | | | | +| | | X | | | i1| | X | | | i1| i2| X | | +|___|___|___| | |___|___|___| | |___|___|___| | + ^ ^ ^ +t4: | t5: | t6: | +!add_item | !add_item | !add_item | +&& shift_fifo | && shift_fifo | && !shift_fifo | +_____________ | _____________ | _____________ | +| | | | | | | | | | | | | | | +| i1| i2| X | | | i2| | X | | | | | X | | +|___|___|___| | |___|___|___| | |___|___|___| | + ^ ^ ^ +t7: | t8: | t9: | +add_item | add_item | !add_item | +&& !shift_fifo | && shift_fifo | && !shift_fifo | +_____________ | _____________ | _____________ | +| | | | | | | | | | | | | | | +| | | X | | | i3| | X | | | i4| | X | | +|___|___|___| | |___|___|___| | |___|___|___| | + ^ ^ ^ +*/ + +module uvmt_cv32e40s_sl_fifo + import cv32e40s_pkg::*; + #( + parameter type FIFO_TYPE_T = obi_inst_req_t, + parameter FIFO_SIZE = 2 + ) + ( + input logic rst_ni, + input logic clk_i, + + input logic add_item, + input logic shift_fifo, + + input FIFO_TYPE_T item_in, + output FIFO_TYPE_T item_out + ); + + // Extend the FIFO with one elemet to make sure the pointer will not underflow + localparam FIFO_PTR_SIZE = $clog2(FIFO_SIZE+1); + + // Extend the FIFO with one elemet to make sure the pointer will not underflow + FIFO_TYPE_T [FIFO_SIZE:0] fifo; + logic [FIFO_PTR_SIZE-1:0] ptr; + FIFO_TYPE_T zero; + + assign item_out = fifo[FIFO_SIZE]; + + always_ff @(posedge clk_i, negedge rst_ni) begin + if(!rst_ni) begin + fifo <= '0; + ptr <= FIFO_SIZE; + zero <= '0; + end else begin + if (add_item && !shift_fifo) begin + fifo[ptr] <= item_in; + ptr <= ptr - 1'b1; + + end else if (!add_item && shift_fifo) begin + ptr <= ptr + 1'b1; + + fifo[FIFO_SIZE:1] <= fifo[FIFO_SIZE-1:0]; + fifo[0] <= zero; + + // If used correctly the fifo should not shift unless there already is an item in the fifo. + // For safety we add this as a requirement for entering this fifo state. + end else if (add_item && shift_fifo && ptr < FIFO_SIZE) begin + fifo[FIFO_SIZE:1] <= fifo[FIFO_SIZE-1:0]; + fifo[0] <= zero; + + fifo[ptr+1'b1] <= item_in; + end + end + end + + +endmodule : uvmt_cv32e40s_sl_fifo diff --git a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_req_attribute_fifo.sv b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_req_attribute_fifo.sv deleted file mode 100644 index e95d041af4..0000000000 --- a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_sl_req_attribute_fifo.sv +++ /dev/null @@ -1,104 +0,0 @@ -// Copyright 2022 Silicon Labs, Inc. -// -// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); -// you may not use this file except in compliance with the License. -// You may obtain a copy of the License at -// -// https://solderpad.org/licenses/ -// -// Unless required by applicable law or agreed to in writing, software -// distributed under the License is distributed on an "AS IS" BASIS, -// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -// See the License for the specific language governing permissions and -// limitations under the License. -// -// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 - -/* -This support logic submodule monitors the OBI handshake, which consists of a request and a response. -The request can contain attributes that affect the response. -This module aims to monitor an attribute of the request, and when receiving the corresponding response, output the response's request's attribute value. -What complicates the described task is that a request is not always directly followed by a response. -In other words, we need to keep track of which request belongs to which response. -The module uses a FIFO to keep track of the requests and the responses. -The FIFO can only hold 2 requests at once. -The figure shows how the FIFO behaves when requests are generated ((gnt && reg)==1) and responses are received (rvalid==1). -In the figure, the FIFO is the container, the pointer is illustrated as a ^, and rN is the request number N's attribute value. -The attribute value in FIFO[2] is read whenever rvalid==1. -t1: | t2: | t3: | -gnt && req | gnt && req | !(gnt && req) | -&& !rvalid | && !rvalid | && !rvalid | -_____________ | _____________ | _____________ | -| | | | | | | | | | | | | | | -| X | | | | | X | | r1| | | X | r2| r1| | -|___|___|___| | |___|___|___| | |___|___|___| | - ^ ^ ^ -t4: | t5: | t6: | -!(gnt && req) | !(gnt && req) | !(gnt && req) | -&& rvalid | && rvalid | && !rvalid | -_____________ | _____________ | _____________ | -| | | | | | | | | | | | | | | -| X | r2| r1| | | X | | r2| | | X | | | | -|___|___|___| | |___|___|___| | |___|___|___| | - ^ ^ ^ -t7: | t8: | t9: | -gnt && req | gnt && req | !(gnt && req) | -&& !rvalid | && rvalid | && !rvalid | -_____________ | _____________ | _____________ | -| | | | | | | | | | | | | | | -| X | | | | | X | | r3| | | X | | r4| | -|___|___|___| | |___|___|___| | |___|___|___| | - ^ ^ ^ -*/ - - -module uvmt_cv32e40s_sl_req_attribute_fifo - #( - parameter int XLEN = 1 - ) - ( - input logic rst_ni, - input logic clk_i, - - //OBI handshake signals - input logic gnt, - input logic req, - input logic rvalid, - - //Attribute in the current request - input logic [XLEN-1:0] req_attribute_i, - - //Indicates if the response's request contained the attribute or not - output logic [XLEN-1:0] is_req_attribute_in_response_o - ); - - logic [2:0][XLEN-1:0] fifo; - logic [1:0] pointer; - - assign is_req_attribute_in_response_o = rvalid ? fifo[2] : '0; - - always @(posedge clk_i, negedge rst_ni) begin - if(!rst_ni) begin - fifo <= 3'b000; - pointer = 2'd2; - end else begin - //This logic is demonstrated in time t1, t2 and t3 in the figure above - if ((gnt && req) && !rvalid) begin - fifo[pointer] = req_attribute_i; - pointer <= pointer - 2'd1; - - //This logic is demonstrated in time t4, t5 and t6 in the figure above - end else if (!(gnt && req) && rvalid) begin - pointer <= pointer + 2'd1; - fifo <= {fifo[1:0], '0}; - - //This logic is demonstrated in time t8 and t9 in the figure above (and uses t7 to generate a situation where this part of the logic can be used) - end else if ((gnt && req) && rvalid) begin - fifo[pointer] = req_attribute_i; - fifo <= {fifo[1:0], '0}; - - end - end - end - -endmodule : uvmt_cv32e40s_sl_req_attribute_fifo diff --git a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_support_logic.sv b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_support_logic.sv index c9d9892141..bdbfec8f38 100644 --- a/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_support_logic.sv +++ b/cv32e40s/tb/uvmt/support_logic/uvmt_cv32e40s_support_logic.sv @@ -25,7 +25,9 @@ module uvmt_cv32e40s_support_logic ( uvma_rvfi_instr_if_t rvfi, uvmt_cv32e40s_support_logic_module_i_if_t.driver_mp in_support_if, - uvmt_cv32e40s_support_logic_module_o_if_t.master_mp out_support_if + uvmt_cv32e40s_support_logic_module_o_if_t.master_mp out_support_if, + uvma_obi_memory_if_t data_obi_if, + uvma_obi_memory_if_t instr_obi_if ); @@ -36,11 +38,11 @@ module uvmt_cv32e40s_support_logic default clocking @(posedge in_support_if.clk); endclocking default disable iff (!in_support_if.rst_n); - // --------------------------------------------------------------------------- // Local parameters // --------------------------------------------------------------------------- + localparam MAX_NUM_OUTSTANDING_OBI_REQUESTS = 2; // --------------------------------------------------------------------------- // Local variables @@ -63,6 +65,25 @@ module uvmt_cv32e40s_support_logic int req_vs_valid_cnt; + obi_data_req_t data_obi_req; + assign data_obi_req.addr = data_obi_if.addr; + assign data_obi_req.we = data_obi_if.we; + assign data_obi_req.be = data_obi_if.be; + assign data_obi_req.wdata = data_obi_if.wdata; + assign data_obi_req.memtype = data_obi_if.memtype; + assign data_obi_req.prot = data_obi_if.prot; + assign data_obi_req.dbg = data_obi_if.dbg; + assign data_obi_req.achk = data_obi_if.achk; + assign data_obi_req.integrity = '0; + + obi_inst_req_t instr_obi_req; + assign instr_obi_req.addr = instr_obi_if.addr; + assign instr_obi_req.memtype = instr_obi_if.memtype; + assign instr_obi_req.prot = instr_obi_if.prot; + assign instr_obi_req.dbg = instr_obi_if.dbg; + assign instr_obi_req.achk = instr_obi_if.achk; + assign instr_obi_req.integrity = '0; + // --------------------------------------------------------------------------- // Support logic blocks // --------------------------------------------------------------------------- @@ -299,81 +320,89 @@ end ); - //The submodule instance under will tell if the - //the response's request required a store operation. + //The submodule instances under will tell if the + //the response's request had integrity - uvmt_cv32e40s_sl_req_attribute_fifo + uvmt_cv32e40s_sl_fifo #( - .XLEN (1) - ) req_was_store_i + .FIFO_TYPE_T (logic), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) instr_req_had_integrity_i ( .clk_i (in_support_if.clk), .rst_ni (in_support_if.rst_n), - .gnt (in_support_if.data_bus_gnt), - .req (in_support_if.data_bus_req), - .rvalid (in_support_if.data_bus_rvalid), - .req_attribute_i (in_support_if.req_is_store & in_support_if.rst_n), + .add_item (in_support_if.instr_bus_gnt && in_support_if.instr_bus_req), + .shift_fifo (in_support_if.instr_bus_rvalid), - .is_req_attribute_in_response_o (out_support_if.req_was_store) + .item_in (in_support_if.req_instr_integrity), + .item_out (out_support_if.instr_req_had_integrity) ); - uvmt_cv32e40s_sl_req_attribute_fifo + uvmt_cv32e40s_sl_fifo #( - .XLEN (32) - ) instr_resp_pc_i + .FIFO_TYPE_T (logic), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) data_req_had_integrity_i ( .clk_i (in_support_if.clk), .rst_ni (in_support_if.rst_n), - .gnt (in_support_if.instr_bus_gnt), - .req (in_support_if.instr_bus_req), - .rvalid (in_support_if.instr_bus_rvalid), - .req_attribute_i (in_support_if.instr_req_pc & !in_support_if.rst_n), + .add_item (in_support_if.data_bus_gnt && in_support_if.data_bus_req), + .shift_fifo (in_support_if.data_bus_rvalid), - .is_req_attribute_in_response_o (out_support_if.instr_resp_pc) + .item_in (in_support_if.req_data_integrity), + .item_out (out_support_if.data_req_had_integrity) ); - //The submodule instance under will tell if the - //the response's request had integrity - //in the transfere of instructions on the OBI instruction bus. - - uvmt_cv32e40s_sl_req_attribute_fifo + uvmt_cv32e40s_sl_fifo #( - .XLEN (1) - ) instr_req_had_integrity_i + .FIFO_TYPE_T (obi_data_req_t), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) fifo_obi_data_req ( .clk_i (in_support_if.clk), .rst_ni (in_support_if.rst_n), - .gnt (in_support_if.instr_bus_gnt), - .req (in_support_if.instr_bus_req), - .rvalid (in_support_if.instr_bus_rvalid), - .req_attribute_i (in_support_if.req_instr_integrity & in_support_if.rst_n), + .add_item (data_obi_if.gnt && data_obi_if.req), + .shift_fifo (data_obi_if.rvalid), - .is_req_attribute_in_response_o (out_support_if.instr_req_had_integrity) + .item_in (data_obi_req), + .item_out (out_support_if.obi_data_packet.req) ); - //The submodule instance under will tell if the - //the response's request had integrity - //in the transfere of data on the OBI data bus. + assign out_support_if.obi_data_packet.resp.rdata = data_obi_if.rdata; + assign out_support_if.obi_data_packet.resp.err = data_obi_if.err; + assign out_support_if.obi_data_packet.resp.rchk = data_obi_if.rchk; + assign out_support_if.obi_data_packet.resp.integrity_err = '0; + assign out_support_if.obi_data_packet.resp.integrity = '0; + assign out_support_if.obi_data_packet.valid = data_obi_if.rvalid; + - uvmt_cv32e40s_sl_req_attribute_fifo + uvmt_cv32e40s_sl_fifo #( - .XLEN (1) - ) data_req_had_integrity_i + .FIFO_TYPE_T (obi_inst_req_t), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) + ) fifo_obi_instr_req ( .clk_i (in_support_if.clk), .rst_ni (in_support_if.rst_n), - .gnt (in_support_if.data_bus_gnt), - .req (in_support_if.data_bus_req), - .rvalid (in_support_if.data_bus_rvalid), - .req_attribute_i (in_support_if.req_data_integrity & in_support_if.rst_n), + .add_item (instr_obi_if.gnt && instr_obi_if.req), + .shift_fifo (instr_obi_if.rvalid), - .is_req_attribute_in_response_o (out_support_if.data_req_had_integrity) + .item_in (instr_obi_req), + .item_out (out_support_if.obi_instr_packet.req) ); + assign out_support_if.obi_instr_packet.resp.rdata = instr_obi_if.rdata; + assign out_support_if.obi_instr_packet.resp.err = instr_obi_if.err; + assign out_support_if.obi_instr_packet.resp.rchk = instr_obi_if.rchk; + assign out_support_if.obi_instr_packet.resp.integrity_err = '0; + assign out_support_if.obi_instr_packet.resp.integrity = '0; + assign out_support_if.obi_instr_packet.valid = instr_obi_if.rvalid; + + //The submodule instance under will tell if the //the response's request had a gntpar error //in the transfere of instructions on the OBI instruction bus. @@ -407,40 +436,40 @@ end end end - uvmt_cv32e40s_sl_req_attribute_fifo + uvmt_cv32e40s_sl_fifo #( - .XLEN (1) + .FIFO_TYPE_T (logic), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) ) sl_req_gntpar_error_in_resp_instr_i ( - .clk_i (in_support_if.clk), + .clk_i (in_support_if.clk), .rst_ni (in_support_if.rst_n), - .gnt (in_support_if.instr_bus_gnt), - .req (in_support_if.instr_bus_req), - .rvalid (in_support_if.instr_bus_rvalid), - .req_attribute_i (instr_gntpar_error), + .add_item (in_support_if.instr_bus_gnt && in_support_if.instr_bus_req), + .shift_fifo (in_support_if.instr_bus_rvalid), - .is_req_attribute_in_response_o (out_support_if.gntpar_error_in_response_instr) + .item_in (instr_gntpar_error), + .item_out (out_support_if.gntpar_error_in_response_instr) ); //The submodule instance under will tell if the //the response's request had a gntpar error //in the transfere of data on the OBI data bus. - uvmt_cv32e40s_sl_req_attribute_fifo + uvmt_cv32e40s_sl_fifo #( - .XLEN (1) + .FIFO_TYPE_T (logic), + .FIFO_SIZE (MAX_NUM_OUTSTANDING_OBI_REQUESTS) ) sl_req_gntpar_error_in_resp_data_i ( - .clk_i (in_support_if.clk), + .clk_i (in_support_if.clk), .rst_ni (in_support_if.rst_n), - .gnt (in_support_if.data_bus_gnt), - .req (in_support_if.data_bus_req), - .rvalid (in_support_if.data_bus_rvalid), - .req_attribute_i (data_gntpar_error), + .add_item (in_support_if.data_bus_gnt && in_support_if.data_bus_req), + .shift_fifo (in_support_if.data_bus_rvalid), - .is_req_attribute_in_response_o (out_support_if.gntpar_error_in_response_data) + .item_in (data_gntpar_error), + .item_out (out_support_if.gntpar_error_in_response_data) ); endmodule : uvmt_cv32e40s_support_logic diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv index 63b1b74081..0645e77a23 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_clic_interrupt_assert.sv @@ -500,10 +500,10 @@ module uvmt_cv32e40s_clic_interrupt_assert } instr_names_e; typedef struct packed { - logic [35:32] tag; - logic [31:0] addr; logic is_mret; logic is_clicv; + logic [35:32] tag; + logic [31:0] addr; } obi_tagged_txn_t; @@ -681,7 +681,6 @@ module uvmt_cv32e40s_clic_interrupt_assert logic delayed_clicv_req; logic [31:0] next_pc; logic irq_ack_occurred_between_valid; - logic minhv_high_between_valid; logic [7:0] mintstatus_mil_q; logic [7:0] expected_mpil; logic prev_was_valid_mnxti_write; @@ -713,7 +712,7 @@ module uvmt_cv32e40s_clic_interrupt_assert || rvfi_trap.exception_cause == INSTR_PARITY_FAULT) && rvfi_trap.exception == 1'b1 && rvfi_trap.trap == 1'b1); - assign is_instr_clicptr_fault = (rvfi_trap.exception_cause == INSTR_BUS_FAULT + assign is_instr_clicptr_fault = (rvfi_trap.exception_cause inside { INSTR_BUS_FAULT, INSTR_PARITY_FAULT, INSTR_ACCESS_FAULT } && rvfi_trap.clicptr == 1'b1); assign is_trap_exception = rvfi_trap.exception == 1'b1 && rvfi_trap.trap == 1'b1; @@ -847,6 +846,75 @@ module uvmt_cv32e40s_clic_interrupt_assert end end + // Checks if a single bit of a csr is cleared by sw + function bit csr_bit_cleared_by_sw(bit[31:0] index); + case (csr_instr.funct3) + CSRRCI: begin + if (index > 4) begin + return 0; + end else begin + return csr_instr.n.uimm[index]; + end + end + CSRRWI: begin + if (index > 4) begin + return 1; + end else begin + return !csr_instr.n.uimm[index]; + end + end + CSRRC: begin + return rvfi_rs1_rdata[index]; + end + CSRRW: begin + return !rvfi_rs1_rdata[index]; + end + CSRRS, CSRRSI: begin + return 0; + end + endcase + + return 0; + endfunction : csr_bit_cleared_by_sw + + // Checks if a single bit of a csr is set by sw + function bit csr_bit_set_by_sw(bit[31:0] index); + case (csr_instr.funct3) + CSRRCI: begin + return 0; + end + CSRRWI: begin + if (index > 4) begin + return 0; + end else begin + return csr_instr.n.uimm[index]; + end + end + CSRRC: begin + return 0; + end + CSRRW, CSRRS: begin + return rvfi_rs1_rdata[index]; + end + CSRRSI: begin + if (index > 4) begin + return 0; + end else begin + return csr_instr.n.uimm[index]; + end + end + endcase + + return 0; + endfunction : csr_bit_set_by_sw + + bit is_minhv_set_by_sw; + bit is_minhv_cleared_by_sw; + + always_comb begin + is_minhv_set_by_sw = rvfi_valid && is_csr_write && is_mcause_access_instr && csr_bit_set_by_sw(30); + is_minhv_cleared_by_sw = rvfi_valid && is_csr_write && is_mcause_access_instr && csr_bit_cleared_by_sw(30); + end function is_instr(uncompressed_instr_t instr, instr_names_e instr_type); if (is_invalid_instr_word) begin @@ -971,7 +1039,7 @@ module uvmt_cv32e40s_clic_interrupt_assert $rose(fetch_enable) |=> ##1 mtvec_fields.base_31_7 == mtvec_addr_i[31:7] && mtvec_fields.base_6_2 == 5'h00 && - mtvec_fields.mode == M_MODE; + mtvec_fields.mode == 2'b11; endproperty : p_mtvec_reset_value_correct; a_mtvec_reset_value_correct: assert property (p_mtvec_reset_value_correct) @@ -1011,7 +1079,6 @@ module uvmt_cv32e40s_clic_interrupt_assert ##0 rvfi_pc_rdata == ({$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + NMI_OFFSET) && !rvfi_dbg_mode or - // rvfi_valid[->1] ##0 rvfi_pc_rdata == debug_halt_addr && rvfi_dbg_mode ; @@ -1288,12 +1355,6 @@ module uvmt_cv32e40s_clic_interrupt_assert end always_comb begin - //if (!rst_ni) begin - // obi_instr_request_n <= '0; - // obi_instr_service_n <= '0; - // obi_data_request_n <= '0; - // obi_data_service_n <= '0; - //end else begin if (obi_instr_push) begin obi_instr_request_n <= obi_instr_request == 3'd7 ? obi_instr_request + 3'd2 : obi_instr_request + 3'd1; end else begin @@ -1317,7 +1378,6 @@ module uvmt_cv32e40s_clic_interrupt_assert end else begin obi_data_service_n <= obi_data_service; end - //end end // New obi_instr read request @@ -1370,13 +1430,10 @@ module uvmt_cv32e40s_clic_interrupt_assert assign is_mtvt_store_event = is_store_instr_addr_in_mtvt_region(rvfi_insn) && !rvfi_trap.exception && rvfi_valid; assign is_mtvt_load_event = is_read_mtvt_table_val_obi; + `ifdef FORMAL always@* begin if (!rst_ni) begin no_mtvt_store_event_occurred <= 1'b1; - `ifndef FORMAL - // We don't want this table to be initialized in formal, should be free net for formal - mtvt_table_value <= {<<{ '0}}; - `endif end if (is_mtvt_store_event) begin mtvt_write_offset <= rvfi_rs1_rdata + s_imm - mtvt; @@ -1388,6 +1445,15 @@ module uvmt_cv32e40s_clic_interrupt_assert mtvt_table_value[(CLIC_ID_WIDTH)'(mtvt_read_offset/'d4)] <= rvfi_rd_wdata; end end + `else + always @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + mtvt_table_value <= {<<{'0}}; + end else if (is_read_from_mtvt) begin + mtvt_table_value[(CLIC_ID_WIDTH)'((obi_instr_fifo_tag_out.addr - mtvt)/4)] <= obi_instr_rdata; + end + end + `endif sequence s_store_mtvt_value; @(posedge clk_i) @@ -1473,21 +1539,24 @@ module uvmt_cv32e40s_clic_interrupt_assert always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin obi_instr_fifo_tag_ff[i] <= '0; + obi_data_fifo_tag_ff[i] <= '0; end else begin if (obi_instr_fifo_tag_wena[i]) begin - obi_instr_fifo_tag_ff[i].tag <= obi_instr_request_n; - obi_instr_fifo_tag_ff[i].addr <= obi_instr_addr; - obi_instr_fifo_tag_ff[i].is_mret <= obi_req_is_mret; + obi_instr_fifo_tag_ff[i].tag <= obi_instr_request_n; + obi_instr_fifo_tag_ff[i].addr <= obi_instr_addr; + obi_instr_fifo_tag_ff[i].is_mret <= obi_req_is_mret; obi_instr_fifo_tag_ff[i].is_clicv <= obi_req_is_clicv; end else begin - obi_instr_fifo_tag_ff[i] <= obi_instr_fifo_tag_ff[i]; + obi_instr_fifo_tag_ff[i] <= obi_instr_fifo_tag_ff[i]; end if (obi_data_fifo_tag_wena[i]) begin - obi_data_fifo_tag_ff[i].tag <= obi_data_request_n; - obi_data_fifo_tag_ff[i].addr <= obi_data_addr; + obi_data_fifo_tag_ff[i].tag <= obi_data_request_n; + obi_data_fifo_tag_ff[i].addr <= obi_data_addr; + obi_data_fifo_tag_ff[i].is_mret <= 0; // Not used for data fifo + obi_data_fifo_tag_ff[i].is_clicv <= 0; // Not used for data fifo end else begin - obi_data_fifo_tag_ff[i] <= obi_data_fifo_tag_ff[i]; + obi_data_fifo_tag_ff[i] <= obi_data_fifo_tag_ff[i]; end end end @@ -1524,6 +1593,7 @@ module uvmt_cv32e40s_clic_interrupt_assert always_ff @(posedge clk_i or negedge rst_ni) begin if (!rst_ni) begin mepc_as_pointer_rdata <= '0; + //logic is_first_instr; end else begin if (obi_instr_fifo_tag_rena && obi_instr_fifo_tag_out.is_mret) begin mepc_as_pointer_rdata <= {obi_instr_rdata[31:1], 1'b0}; @@ -1640,12 +1710,169 @@ module uvmt_cv32e40s_clic_interrupt_assert `uvm_error(info_tag, $sformatf("Fencei should _always_ make writes to mtvt visible to next taken shv interrupt")); + // ------------------------------------------------------------------------ + // dpc correct when interrupting clic-interrupts + // ------------------------------------------------------------------------ + property p_dpc_to_mtvt_shv; + irq_ack + && clic_core.shv + ##1 rvfi_valid[->1] + ##0 $rose(support_if.first_debug_ins) + && rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ + |-> + // Regular case + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == (($past(mtvt_table_value[clic_oic.id]) >> 1) << 1) + && rvfi_intr.interrupt + or + // NMI + rvfi_intr.interrupt + && rvfi_intr.cause >= 11'h400 + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == {$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + or + // Trap + rvfi_trap.exception + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == debug_exc_addr + ; + endproperty : p_dpc_to_mtvt_shv + + a_dpc_to_mtvt_shv : assert property (p_dpc_to_mtvt_shv) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + property p_dpc_to_mtvec_nonshv; + irq_ack + && !clic_core.shv + ##1 rvfi_valid[->1] + ##0 $rose(support_if.first_debug_ins) + && rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ + |-> + // Regular case && nmi (identical behavior) + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == {$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + && rvfi_intr.interrupt + or + // Trap + rvfi_trap.exception + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == debug_exc_addr + ; + endproperty : p_dpc_to_mtvec_nonshv + + a_dpc_to_mtvec_nonshv : assert property (p_dpc_to_mtvec_nonshv) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + logic [31:0] past_rvfi_pc_wdata; + always @(posedge clk_i or negedge rst_ni) begin + if (!rst_ni) begin + past_rvfi_pc_wdata <= 0; + end else begin + if ($rose(dut_wrap.cv32e40s_wrapper_i.core_i.fetch_enable)) begin + past_rvfi_pc_wdata <= {dut_wrap.cv32e40s_wrapper_i.core_i.boot_addr_i[31:2] , 2'b00}; + end else if (rvfi_valid) begin + past_rvfi_pc_wdata <= rvfi_pc_wdata; + end + end + end + + property p_dpc_to_pc_halt; + $rose(support_if.first_debug_ins) + ##0 rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ + |-> + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && rvfi_dpc_rdata == past_rvfi_pc_wdata + or + // Interrupt or nmi (checked above) + rvfi_intr.interrupt + or + // Trap + rvfi_trap.exception + ; + endproperty : p_dpc_to_pc_halt + + a_dpc_to_pc_halt : assert property (p_dpc_to_pc_halt) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + property p_dpc_to_pc_step; + $rose(support_if.first_debug_ins) + ##0 rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP + |-> + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && rvfi_dpc_rdata == past_rvfi_pc_wdata + or + // Interrupt or nmi (checked below) + rvfi_intr.interrupt + or + // Trap + rvfi_trap.exception + ; + endproperty : p_dpc_to_pc_step + + a_dpc_to_pc_step : assert property (p_dpc_to_pc_step) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + property p_dpc_to_mtvt_step_irq_shv; + irq_ack + && clic_core.shv + ##1 rvfi_valid[->1] + ##0 $rose(support_if.first_debug_ins) + && rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP + |-> + // Regular case + rvfi_dbg_mode + && rvfi_pc_rdata == debug_halt_addr + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == (($past(mtvt_table_value[clic_oic.id]) >> 1) << 1) + && rvfi_intr.interrupt + or + // NMI + rvfi_intr.interrupt + && rvfi_intr.cause >= 11'h400 + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == {$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + ; + endproperty : p_dpc_to_mtvt_step_irq_shv + + a_dpc_to_mtvt_step_irq_shv : assert property (p_dpc_to_mtvt_step_irq_shv) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + property p_dpc_to_mtvec_step_irq_nonshv; + irq_ack + && !clic_core.shv + ##1 rvfi_valid[->1] + ##0 $rose(support_if.first_debug_ins) + && rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP + |-> + // Regular case && nmi (identical behavior) + rvfi_dbg + && rvfi_pc_rdata == debug_halt_addr + && (rvfi_dpc_rdata & rvfi_dpc_rmask) == {$past(mtvec_fields.base_31_7), $past(mtvec_fields.base_6_2), 2'b00} + && rvfi_intr.interrupt + ; + endproperty : p_dpc_to_mtvec_step_irq_nonshv + + a_dpc_to_mtvec_step_irq_nonshv : assert property (p_dpc_to_mtvec_step_irq_nonshv) + else + `uvm_error(info_tag, + $sformatf("dpc updated incorrectly")); + + // ------------------------------------------------------------------------ // mtvt aligned correctly // ------------------------------------------------------------------------ property p_mtvt_alignment_correct; - accept_on(N_MTVT <= 6) // Pass if field does not exist + disable iff (!rst_ni || N_MTVT <= 6) // Disable if field does not exist mtvt_fields.base_n_0 == '0; endproperty : p_mtvt_alignment_correct @@ -2221,108 +2448,77 @@ module uvmt_cv32e40s_clic_interrupt_assert mintstatus_fields)); // ------------------------------------------------------------------------ - // Minhv should be set when an shv interrupt is taken + // Minhv should be set when an shv interrupt is taken but ptr fetch fails + // otherwise it should be cleared on an interrupt // ------------------------------------------------------------------------ - property p_mcause_minhv_set_at_hw_vectoring_start; - clic.shv - ##1 irq_ack - |=> - mcause_fields.minhv; - endproperty : p_mcause_minhv_set_at_hw_vectoring_start + property p_mcause_minhv_set_at_failing_ptr_fetch; - a_mcause_minhv_set_at_hw_vectoring_start: assert property (p_mcause_minhv_set_at_hw_vectoring_start) - else - `uvm_error(info_tag, - $sformatf("mcause.minhv not set at hw vectored ISR entry")); - - // ------------------------------------------------------------------------ - // Minhv should be cleared on successful pointer fetch - // ------------------------------------------------------------------------ - - property p_mcause_minhv_cleared_at_hw_vectoring_end; - $rose(mcause_fields.minhv) - && !(csr_instr.csr == MCAUSE) - ##1 rvfi_valid[->1] + (clic.shv ##1 irq_ack ##1 rvfi_valid[->1]) + within + (1 ##1 rvfi_valid ##1 rvfi_valid[->1]) |-> - mcause_fields.minhv == 1'b0 - or - // minhv set by write to mcause - is_mcause_access_instr - && is_csr_write - && rvfi_rs1_rdata[30] == 1'b1 - && mcause_fields.minhv == 1'b1 - or - is_instr_clicptr_fault - && mcause_fields.minhv == 1'b1 - or - // vectored address failed - is_invalid_instr_word - && mcause_fields.minhv == 1'b1 - or - // Access fault to destination - (is_cause_instr_access_fault || is_cause_instr_bus_fault || is_cause_instr_parity_fault) - && mcause_fields.minhv == 1'b1 + // No minhv without clic ptr exception + // and no clic ptr exception without minhv + rvfi_mcause_wdata_fields.minhv ^~ (rvfi_trap.exception && is_instr_clicptr_fault) + or + is_minhv_set_by_sw ; - endproperty : p_mcause_minhv_cleared_at_hw_vectoring_end + endproperty : p_mcause_minhv_set_at_failing_ptr_fetch - a_mcause_minhv_cleared_at_hw_vectoring_end: assert property (p_mcause_minhv_cleared_at_hw_vectoring_end) + a_mcause_minhv_set_at_failing_ptr_fetch: assert property (p_mcause_minhv_set_at_failing_ptr_fetch) else `uvm_error(info_tag, - $sformatf("mcause.minhv not cleared at hw vectored fetch") - ); - - // ------------------------------------------------------------------------ - // Cover: minhv cleared at hw vectoring end (successful pointer fetch) - // ------------------------------------------------------------------------ - - property cp_mcause_minhv_cleared_at_hw_vectoring_end; - strong( - $rose(mcause_fields.minhv) - && !(csr_instr.csr == MCAUSE) - ##1 $fell(mcause_fields.minhv)[->1] - and - 1 ##1 rvfi_valid[->1] - ); - endproperty : cp_mcause_minhv_cleared_at_hw_vectoring_end + $sformatf("mcause.minhv not set/cleared correctly")); - cov_mcause_minhv_cleared_at_hw_vectoring_end: cover property(cp_mcause_minhv_cleared_at_hw_vectoring_end); // ------------------------------------------------------------------------ - // No prefetches between pointer fetch and final target + // mcause.minhv set, should only have happened if sw set it + // or we took a trap that with a clicptr fault // ------------------------------------------------------------------------ + property p_mcause_minhv_set_valid; - property p_no_prefetches_between_ptr_fetch_and_final_target; - clic.shv - ##1 irq_ack - ##1 mcause_fields.minhv - && !(csr_instr.csr == MCAUSE) - |=> - (obi_instr_req && obi_instr_gnt)[->1] - ##0 $fell(mcause_fields.minhv)[->1]; - endproperty : p_no_prefetches_between_ptr_fetch_and_final_target + (rvfi_valid && !rvfi_mcause_fields.minhv && !rvfi_mcause_wmask_fields.minhv) + ##1 (!rvfi_valid)[*0:$] + ##1 (rvfi_valid && rvfi_mcause_wdata_fields.minhv && rvfi_mcause_wmask_fields.minhv) + |-> + rvfi_trap.exception && is_instr_clicptr_fault + or + is_minhv_set_by_sw + ; + endproperty : p_mcause_minhv_set_valid - a_no_prefetches_between_ptr_fetch_and_final_target: assert property (p_no_prefetches_between_ptr_fetch_and_final_target) + a_mcause_minhv_set_valid: assert property (p_mcause_minhv_set_valid) else `uvm_error(info_tag, - $sformatf("There should be no prefeches between ptr fetch and final target")); + $sformatf("mcause.minhv not set in a valid way")); // ------------------------------------------------------------------------ - // Cover: No prefetches between pointer fetch and final target + // mcause.minhv cleared, should only have happened if sw cleared it + // or we took a trap that did not have a clicptr fault // ------------------------------------------------------------------------ + property p_mcause_minhv_clear_valid; - property cp_no_prefetches_between_ptr_fetch_and_final_target; - reject_on(core_in_debug) - clic.shv - ##1 irq_ack - ##1 mcause_fields.minhv - && !(csr_instr.csr == MCAUSE) - #=# - (obi_instr_req && obi_instr_gnt)[->1] - ##0 $fell(mcause_fields.minhv)[->1]; - endproperty : cp_no_prefetches_between_ptr_fetch_and_final_target + (rvfi_valid && rvfi_mcause_fields.minhv && !rvfi_mcause_wmask_fields.minhv) + ##1 (!rvfi_valid)[*0:$] + ##1 (rvfi_valid && !rvfi_mcause_wdata_fields.minhv && rvfi_mcause_wmask_fields.minhv) + |-> + // There should be no clicptr fault + not strong (rvfi_trap.exception && is_instr_clicptr_fault) + and ( + // and sw cleared it + is_minhv_cleared_by_sw + or + // or we encountered a trap that did not have a clicptr fault + (rvfi_trap || rvfi_intr) && !is_instr_clicptr_fault + ) + ; + endproperty : p_mcause_minhv_clear_valid - cov_no_prefetches_between_ptr_fetch_and_final_target: cover property (cp_no_prefetches_between_ptr_fetch_and_final_target); + a_mcause_minhv_clear_valid: assert property (p_mcause_minhv_clear_valid) + else + `uvm_error(info_tag, + $sformatf("mcause.minhv not cleared in a valid way")); // ------------------------------------------------------------------------ // PC should be set to the address fetched from the mtvt pointer after @@ -2359,7 +2555,6 @@ module uvmt_cv32e40s_clic_interrupt_assert // Wait for rdata and sample expected pc ##1 ((pointer_req == obi_instr_service_n)[->1]) ##0 (1, pointer_value = obi_instr_rdata) - ##0 mcause_fields.minhv ##0 rvfi_valid[->1] |-> rvfi_pc_rdata == (pointer_value & ~1) @@ -2410,7 +2605,6 @@ module uvmt_cv32e40s_clic_interrupt_assert // Wait for rdata and sample expected pc ##1 ((pointer_req == obi_instr_service_n)[->1]) ##0 (1, pointer_value = obi_instr_rdata) - ##0 mcause_fields.minhv ##0 rvfi_valid[->1] |-> // Normal case, should end up at mtvt @@ -2697,14 +2891,6 @@ module uvmt_cv32e40s_clic_interrupt_assert end end - always @(posedge clk_i) begin - if (!rst_ni || rvfi_valid && !mcause_fields.minhv) begin - minhv_high_between_valid <= 1'b0; - end else begin - minhv_high_between_valid <= minhv_high_between_valid ? 1'b1 : mcause_fields.minhv; - end - end - property p_irq_ack_occurred_zero_out_of_reset; !fetch_enable |-> irq_ack_occurred_between_valid == 1'b0; endproperty : p_irq_ack_occurred_zero_out_of_reset @@ -2718,7 +2904,7 @@ module uvmt_cv32e40s_clic_interrupt_assert |-> rvfi_if.rvfi_pc_wdata == csr_mepc_if.rvfi_csr_rdata or - (rvfi_mcause_fields.minhv && rvfi_mcause_fields.mpp != U_MODE) && rvfi_if.rvfi_pc_wdata == mepc_as_pointer_rdata; + rvfi_mcause_fields.minhv && rvfi_if.rvfi_pc_wdata == mepc_as_pointer_rdata; endproperty : p_mret_pc_intended a_mret_pc_intended: assert property (p_mret_pc_intended) @@ -2757,7 +2943,6 @@ module uvmt_cv32e40s_clic_interrupt_assert `uvm_error(info_tag, $sformatf("mret to umode does not clear mintthresh")); - // this assert verifies that mode is correctly restored on an mret property p_mret_mode_mpp; logic [1:0] prev_mpp = '0; diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_debug_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_debug_assert.sv index 19564ee771..670362fd93 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_debug_assert.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_debug_assert.sv @@ -160,17 +160,20 @@ module uvmt_cv32e40s_debug_assert rvfi.rvfi_pc_rdata == halt_addr ) else `uvm_error(info_tag, $sformatf("Debug mode entered with wrong pc. pc==%08x", rvfi.rvfi_pc_rdata)); - a_debug_mode_pc_dpc: assert property( - $rose(support_if.first_debug_ins) && - // ignore CLIC, checked in clic asserts - !(rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt && (csr_mtvec.rvfi_csr_rdata[1:0] == 3)) - |-> - (rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt - ##1 - dpc_rdata_q == pc_at_dbg_req) - or - (csr_dpc.rvfi_csr_rdata == pc_at_dbg_req) - ) else `uvm_error(info_tag, $sformatf("Debug mode entered with wrong dpc. dpc==%08x", csr_dpc.rvfi_csr_rdata)); + + generate // ignore CLIC, checked in clic asserts + if (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC==0) begin + a_debug_mode_pc_dpc: assert property( + $rose(support_if.first_debug_ins) + |-> + (rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt + ##1 + dpc_rdata_q == pc_at_dbg_req) + or + (csr_dpc.rvfi_csr_rdata == pc_at_dbg_req) + ) else `uvm_error(info_tag, $sformatf("Debug mode entered with wrong dpc. dpc==%08x", csr_dpc.rvfi_csr_rdata)); + end + endgenerate // Breaking down the above assert in to debug causes, to improve runtime property p_dpc_dbg_ebreak; @@ -194,9 +197,7 @@ module uvmt_cv32e40s_debug_assert //TODO:MT Fully covered by those below, remove? property p_dpc_dbg_step; $rose(support_if.first_debug_ins) && - rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP && - // ignore CLIC, checked in clic asserts - !(rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt && (csr_mtvec.rvfi_csr_rdata[1:0] == 3)) + rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_STEP |-> (csr_dpc.rvfi_csr_rdata == dpc_dbg_step) or @@ -204,8 +205,12 @@ module uvmt_cv32e40s_debug_assert ##1 dpc_rdata_q == dpc_dbg_step); endproperty - a_dpc_dbg_step: assert property(p_dpc_dbg_step) - else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a step, dpc==%08x", csr_dpc.rvfi_csr_rdata)); + generate // ignore CLIC, checked in clic asserts + if (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC==0) begin + a_dpc_dbg_step: assert property(p_dpc_dbg_step) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a step, dpc==%08x", csr_dpc.rvfi_csr_rdata)); + end + endgenerate property p_dpc_dbg_step_notrap; @@ -252,9 +257,7 @@ module uvmt_cv32e40s_debug_assert //TODO:MT Fully covered by those below, remove? property p_dpc_dbg_haltreq; $rose(support_if.first_debug_ins) && - (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ) && - // ignore CLIC, checked in clic asserts - !(rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt && (csr_mtvec.rvfi_csr_rdata[1:0] == 3)) + (rvfi.rvfi_dbg == cv32e40s_pkg::DBG_CAUSE_HALTREQ) |-> (csr_dpc.rvfi_csr_rdata == dpc_dbg_haltreq) or @@ -262,8 +265,12 @@ module uvmt_cv32e40s_debug_assert ##1 dpc_rdata_q == dpc_dbg_haltreq); endproperty - a_dpc_dbg_haltreq: assert property(p_dpc_dbg_haltreq) - else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a haltreq, dpc==%08x", csr_dpc.rvfi_csr_rdata)); + generate // ignore CLIC, checked in clic asserts + if (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC==0) begin + a_dpc_dbg_haltreq: assert property(p_dpc_dbg_haltreq) + else `uvm_error(info_tag, $sformatf("DPC csr does not match expected on a haltreq, dpc==%08x", csr_dpc.rvfi_csr_rdata)); + end + endgenerate property p_dpc_dbg_haltreq_notrap; $rose(support_if.first_debug_ins) && @@ -704,7 +711,7 @@ module uvmt_cv32e40s_debug_assert endproperty a_stepie_irq_dis : assert property(p_stepie_irq_dis) - else `uvm_error(info_tag, "Single stepping should ignore all interrupts if stepie is set"); + else `uvm_error(info_tag, "Single stepping should ignore all interrupts if stepie is not set"); cov_step_stepie_nmi : cover property ( rvfi.is_dret @@ -713,6 +720,19 @@ module uvmt_cv32e40s_debug_assert && csr_dcsr.rvfi_csr_rdata[DCSR_NMIP_POS] ); + property p_stepie_irq_en; + rvfi.is_dret + && csr_dcsr.rvfi_csr_rdata[DCSR_STEP_POS] + && csr_dcsr.rvfi_csr_rdata[DCSR_STEPIE_POS] + && csr_dcsr.rvfi_csr_rdata[DCSR_NMIP_POS] + ##1 rvfi.rvfi_valid[->1] + |-> + rvfi.rvfi_intr.intr && rvfi.rvfi_intr.interrupt; + endproperty + + a_stepie_irq_en : assert property(p_stepie_irq_en) + else `uvm_error(info_tag, "Single stepping should take NMI if stepie is set"); + // step trap handler entry, no retire // if the next instruction after a single step dret is in debug mode, @@ -1093,7 +1113,7 @@ module uvmt_cv32e40s_debug_assert endproperty : p_dbg_with_nmi_dret_stepie - cov_dbg_with_nmi_dret_stepie: cover property (p_dbg_with_nmi_dret_stepie(1)); - cov_dbg_with_nmi_dret_stepie_n: cover property (p_dbg_with_nmi_dret_stepie(0)); + cov_dbg_with_nmi_dret_stepie: cover property (p_dbg_with_nmi_dret_stepie(1'b1)); + cov_dbg_with_nmi_dret_stepie_n: cover property (p_dbg_with_nmi_dret_stepie(1'b0)); endmodule : uvmt_cv32e40s_debug_assert diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_cov.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_cov.sv index 31ba372671..7b61b49a81 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_cov.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pma_cov.sv @@ -371,12 +371,9 @@ module uvmt_cv32e40s_pma_cov // Table Jump Crosses - x_aligned_pmafault_firstfail_tablejump: - cross cp_aligned, cp_pmafault, cp_firstfail, cp_tablejump - { - ignore_bins ignore = - binsof(cp_firstfail.yes) && binsof(cp_tablejump.jump); - } + // TODO: silabs-hfegran: these need vector table access on IF side, currently + // only data side is used. + //x_pmafault_firstfail_tablejump: cross cp_pmafault, cp_firstfail, cp_tablejump; x_pmafault_tablejump: cross cp_pmafault, cp_tablejump; diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmp_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmp_assert.sv index 745e407225..52b14563fc 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmp_assert.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_pmp_assert.sv @@ -81,7 +81,6 @@ module uvmt_cv32e40s_pmp_assert .* ); - // Extra covers and asserts to comprehensively match the spec // Cover the helper-RTL internals @@ -202,13 +201,13 @@ module uvmt_cv32e40s_pmp_assert cp_ismatch_tor: coverpoint model_i.is_match_tor(match_status.val_index) iff (match_status.is_matched); - cp_napot_min_8byte: coverpoint { pmp_req_addr_i[2], csr_pmp_i.addr[match_status.val_index][2] } + cp_napot_min_8byte: coverpoint { pmp_req_addr_i[2+PMP_GRANULARITY], csr_pmp_i.addr[match_status.val_index][2+PMP_GRANULARITY] } iff (csr_pmp_i.cfg[match_status.val_index].mode == PMP_MODE_NAPOT && match_status.is_matched == 1'b1 && match_status.is_access_allowed == 1'b1 ); - cp_napot_min_8byte_disallowed: coverpoint { pmp_req_addr_i[2], csr_pmp_i.addr[match_status.val_index][2] } + cp_napot_min_8byte_disallowed: coverpoint { pmp_req_addr_i[2+PMP_GRANULARITY], csr_pmp_i.addr[match_status.val_index][2+PMP_GRANULARITY] } iff (csr_pmp_i.cfg[match_status.val_index].mode == PMP_MODE_NAPOT && match_status.is_matched == 1'b1 && match_status.is_access_allowed == 1'b0 @@ -318,14 +317,20 @@ module uvmt_cv32e40s_pmp_assert // such pmpcfg writes are ignored, leaving pmpcfg unchanged. This restriction can be temporarily lifted // e.g. during the boot process, by setting mseccfg.RLB. // (vplan:ExecIgnored) + + property p_mmode_only_or_shared_executable_ignore; + logic [3:0] lrwx; + csr_pmp_i.mseccfg.mml === 1'b1 && + csr_pmp_i.mseccfg.rlb === 1'b0 ##1 + ($changed(csr_pmp_i.cfg[region]), + lrwx = { csr_pmp_i.cfg[region].lock, csr_pmp_i.cfg[region].read, csr_pmp_i.cfg[region].write, csr_pmp_i.cfg[region].exec } + ) + |-> + !(lrwx inside { 4'b1?01, 4'b101? }); + endproperty : p_mmode_only_or_shared_executable_ignore + a_mmode_only_or_shared_executable_ignore: assert property ( - csr_pmp_i.mseccfg.mml === 1'b1 && csr_pmp_i.mseccfg.rlb === 1'b0 |=> - $stable(csr_pmp_i.cfg[region]) - or - not ($changed(csr_pmp_i.cfg[region]) ##0 - csr_pmp_i.cfg[region].lock === 1'b1 ##0 - csr_pmp_i.cfg[region].read === 1'b0 ##0 - csr_pmp_i.cfg[region].write || csr_pmp_i.cfg[region].exec) + p_mmode_only_or_shared_executable_ignore ) else `uvm_error(info_tag, "certain rules can't be added"); cov_mmode_only_or_shared_executable: cover property ( diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb.sv index c10a3116a6..30ff8a953d 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb.sv @@ -441,6 +441,7 @@ module uvmt_cv32e40s_tb; .rvfi_csr_wdata(rvfi_i.rvfi_csr_dscratch_wdata[0]) ); + // dscratch1 bind cv32e40s_wrapper uvma_rvfi_csr_if_t#(uvmt_cv32e40s_base_test_pkg::XLEN) rvfi_csr_dscratch1_if(.clk(clk_i), @@ -473,6 +474,8 @@ module uvmt_cv32e40s_tb; + // Bind in verification modules to the design + bind uvmt_cv32e40s_dut_wrap uvma_obi_memory_assert_if_wrp#( .ADDR_WIDTH(uvmt_cv32e40s_base_test_pkg::ENV_PARAM_INSTR_ADDR_WIDTH), @@ -500,277 +503,286 @@ module uvmt_cv32e40s_tb; ) obi_data_memory_assert_i(.obi(obi_data_if)); - // Bind in verification modules to the design - if (CORE_PARAM_CLIC == 0) begin: gen_interrupt_assert - bind cv32e40s_core - uvmt_cv32e40s_interrupt_assert interrupt_assert_i ( - .dcsr_step (cs_registers_i.dcsr_q.step), - .mcause_n ({cs_registers_i.mcause_n.irq, cs_registers_i.mcause_n.exception_code[4:0]}), - .mie_q (cs_registers_i.mie_q), - .mip (cs_registers_i.mip_rdata), - .mstatus_mie (cs_registers_i.mstatus_q.mie), - .mstatus_tw (cs_registers_i.mstatus_q.tw), - .mtvec_mode_q (cs_registers_i.mtvec_q.mode), - - .if_stage_instr_rdata_i (if_stage_i.m_c_obi_instr_if.resp_payload.rdata), - .if_stage_instr_req_o (if_stage_i.m_c_obi_instr_if.s_req.req), - .if_stage_instr_rvalid_i (if_stage_i.m_c_obi_instr_if.s_rvalid.rvalid), - .alignbuf_outstanding (if_stage_i.prefetch_unit_i.alignment_buffer_i.outstanding_cnt_q), - - .ex_stage_instr_valid (ex_stage_i.id_ex_pipe_i.instr_valid), - - .wb_kill (ctrl_fsm.kill_wb), - .wb_stage_instr_err_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.err), - .wb_stage_instr_mpu_status (wb_stage_i.ex_wb_pipe_i.instr.mpu_status), - .wb_stage_instr_rdata_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.rdata), - .wb_stage_instr_valid_i (wb_stage_i.ex_wb_pipe_i.instr_valid), - .wb_trigger (controller_i.controller_fsm_i.trigger_match_in_wb), - .wb_valid (wb_stage_i.wb_valid), - - .branch_taken_ex (controller_i.controller_fsm_i.branch_taken_ex), - .debug_mode_q (controller_i.controller_fsm_i.debug_mode_q), - .pending_nmi (controller_i.controller_fsm_i.pending_nmi), - - .irq_ack_o (core_i.irq_ack), - .irq_id_o (core_i.irq_id), - - .mpu_instr_rvalid (if_stage_i.mpu_i.core_resp_valid_o), - .obi_instr_if (dut_wrap.obi_instr_if), - .obi_data_if (dut_wrap.obi_data_if), - - .writebufstate (load_store_unit_i.write_buffer_i.state), - .rvfi (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), - .support_if (cv32e40s_wrapper.support_logic_module_o_if.slave_mp), - - .* - ); + `ifndef COREV_ASSERT_OFF + bind cv32e40s_core + uvmt_cv32e40s_interrupt_assert interrupt_assert_i ( + .dcsr_step (cs_registers_i.dcsr_q.step), + .mcause_n ({cs_registers_i.mcause_n.irq, cs_registers_i.mcause_n.exception_code[4:0]}), + .mie_q (cs_registers_i.mie_q), + .mip (cs_registers_i.mip_rdata), + .mstatus_mie (cs_registers_i.mstatus_q.mie), + .mstatus_tw (cs_registers_i.mstatus_q.tw), + .mtvec_mode_q (cs_registers_i.mtvec_q.mode), + + .if_stage_instr_rdata_i (if_stage_i.m_c_obi_instr_if.resp_payload.rdata), + .if_stage_instr_req_o (if_stage_i.m_c_obi_instr_if.s_req.req), + .if_stage_instr_rvalid_i (if_stage_i.m_c_obi_instr_if.s_rvalid.rvalid), + .alignbuf_outstanding (if_stage_i.prefetch_unit_i.alignment_buffer_i.outstanding_cnt_q), + + .ex_stage_instr_valid (ex_stage_i.id_ex_pipe_i.instr_valid), + + .wb_kill (ctrl_fsm.kill_wb), + .wb_stage_instr_err_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.err), + .wb_stage_instr_mpu_status (wb_stage_i.ex_wb_pipe_i.instr.mpu_status), + .wb_stage_instr_rdata_i (wb_stage_i.ex_wb_pipe_i.instr.bus_resp.rdata), + .wb_stage_instr_valid_i (wb_stage_i.ex_wb_pipe_i.instr_valid), + .wb_trigger (controller_i.controller_fsm_i.trigger_match_in_wb), + .wb_valid (wb_stage_i.wb_valid), + + .branch_taken_ex (controller_i.controller_fsm_i.branch_taken_ex), + .debug_mode_q (controller_i.controller_fsm_i.debug_mode_q), + .pending_nmi (controller_i.controller_fsm_i.pending_nmi), + + .irq_ack_o (core_i.irq_ack), + .irq_id_o (core_i.irq_id), + + .mpu_instr_rvalid (if_stage_i.mpu_i.core_resp_valid_o), + .obi_instr_if (dut_wrap.obi_instr_if), + .obi_data_if (dut_wrap.obi_data_if), + + .writebufstate (load_store_unit_i.write_buffer_i.state), + .rvfi (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .support_if (cv32e40s_wrapper.support_logic_module_o_if.slave_mp), + + .* + ); + `endif end : gen_interrupt_assert if (CORE_PARAM_CLIC == 1) begin: gen_clic_assert // CLIC assertions - bind cv32e40s_core - uvmt_cv32e40s_clic_interrupt_assert#( - .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC), - .CLIC_ID_WIDTH (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH) - ) clic_assert_i( - .support_if (cv32e40s_wrapper.support_logic_module_o_if.slave_mp), - .rvfi_if(cv32e40s_wrapper.rvfi_instr_if), - .csr_mepc_if(cv32e40s_wrapper.rvfi_csr_mepc_if), - .csr_mstatus_if(cv32e40s_wrapper.rvfi_csr_mstatus_if), - .csr_mcause_if(cv32e40s_wrapper.rvfi_csr_mcause_if), - .csr_mintthresh_if(cv32e40s_wrapper.rvfi_csr_mintthresh_if), - .csr_mintstatus_if(cv32e40s_wrapper.rvfi_csr_mintstatus_if), - .csr_dcsr_if(cv32e40s_wrapper.rvfi_csr_dcsr_if), - - .dpc (cs_registers_i.dpc_rdata), - .mintstatus (cs_registers_i.mintstatus_rdata), - .mintthresh (cs_registers_i.mintthresh_rdata), - .mcause (cs_registers_i.mcause_rdata), - .mtvec (cs_registers_i.mtvec_rdata), - .mtvt (cs_registers_i.mtvt_rdata), - .mepc (cs_registers_i.mepc_rdata), - .mip (cs_registers_i.mip_rdata), - .mie (cs_registers_i.mie_rdata), - .mnxti (cs_registers_i.mnxti_rdata), - .mscratch (cs_registers_i.mscratch_rdata), - .mscratchcsw (cs_registers_i.mscratchcsw_rdata), - .mscratchcswl (cs_registers_i.mscratchcswl_rdata), - .dcsr (cs_registers_i.dcsr_rdata), - - //Control signals: - .pc_set (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_set), - .pc_mux (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_mux), - - .rvfi_mepc_wdata (rvfi_i.rvfi_csr_mepc_wdata), - .rvfi_mepc_wmask (rvfi_i.rvfi_csr_mepc_wmask), - .rvfi_mepc_rdata (rvfi_i.rvfi_csr_mepc_rdata), - .rvfi_mepc_rmask (rvfi_i.rvfi_csr_mepc_rmask), - .rvfi_dpc_rdata (rvfi_i.rvfi_csr_dpc_rdata), - .rvfi_dpc_rmask (rvfi_i.rvfi_csr_dpc_rmask), - .rvfi_mscratch_rdata (rvfi_i.rvfi_csr_mscratch_rdata), - .rvfi_mscratch_rmask (rvfi_i.rvfi_csr_mscratch_rmask), - .rvfi_mscratch_wdata (rvfi_i.rvfi_csr_mscratch_wdata), - .rvfi_mscratch_wmask (rvfi_i.rvfi_csr_mscratch_wmask), - .rvfi_mcause_wdata (rvfi_i.rvfi_csr_mcause_wdata), - .rvfi_mcause_wmask (rvfi_i.rvfi_csr_mcause_wmask), - - .irq_i (core_i.irq_i), - .irq_ack (core_i.irq_ack), - .fetch_enable (core_i.fetch_enable), - .current_priv_mode (core_i.priv_lvl), - .mtvec_addr_i (core_i.mtvec_addr_i), - // External inputs - .clic_if (dut_wrap.clic_if), - // Internal sampled variants - .irq_id (core_i.irq_id[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH-1:0]), - .irq_level (core_i.irq_level), - .irq_priv (core_i.irq_priv), - .irq_shv (core_i.irq_shv), - - .obi_instr_req (core_i.instr_req_o), - .obi_instr_gnt (core_i.instr_gnt_i), - .obi_instr_rvalid (core_i.instr_rvalid_i), - .obi_instr_addr (core_i.instr_addr_o), - .obi_instr_rdata (core_i.instr_rdata_i), - .obi_instr_rready (1'b1), - .obi_instr_err (core_i.instr_err_i), - - .obi_data_addr (core_i.data_addr_o), - .obi_data_wdata (core_i.data_wdata_o), - .obi_data_we (core_i.data_we_o), - .obi_data_be (core_i.data_be_o), - .obi_data_req (core_i.data_req_o), - .obi_data_gnt (core_i.data_gnt_i), - .obi_data_rvalid (core_i.data_rvalid_i), - .obi_data_rready (1'b1), - .obi_data_err (core_i.data_err_i), - - .debug_mode (controller_i.controller_fsm_i.debug_mode_q), - .debug_req (core_i.debug_req_i), - .debug_havereset (core_i.debug_havereset_o), - .debug_running (core_i.debug_running_o), - .debug_halt_addr (dut_wrap.cv32e40s_wrapper_i.dm_halt_addr_i), - .debug_exc_addr (dut_wrap.cv32e40s_wrapper_i.dm_exception_addr_i), - - .rvfi_mode (rvfi_i.rvfi_mode), - .rvfi_insn (rvfi_i.rvfi_insn), - .rvfi_intr (rvfi_i.rvfi_intr), - .rvfi_rs1_rdata (rvfi_i.rvfi_rs1_rdata), - .rvfi_rs2_rdata (rvfi_i.rvfi_rs2_rdata), - .rvfi_rd_wdata (rvfi_i.rvfi_rd_wdata), - .rvfi_valid (rvfi_i.rvfi_valid), - .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), - .rvfi_pc_wdata (rvfi_i.rvfi_pc_wdata), - .rvfi_trap (rvfi_i.rvfi_trap), - .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), - .rvfi_dbg (rvfi_i.rvfi_dbg), - - .wu_wfe (dut_wrap.cv32e40s_wrapper_i.wu_wfe_i), - .core_sleep_o (core_i.core_sleep_o), - .* - ); + `ifndef COREV_ASSERT_OFF + bind cv32e40s_core + uvmt_cv32e40s_clic_interrupt_assert#( + .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC), + .CLIC_ID_WIDTH (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH) + ) clic_assert_i( + .support_if (cv32e40s_wrapper.support_logic_module_o_if.slave_mp), + .rvfi_if(cv32e40s_wrapper.rvfi_instr_if), + .csr_mepc_if(cv32e40s_wrapper.rvfi_csr_mepc_if), + .csr_mstatus_if(cv32e40s_wrapper.rvfi_csr_mstatus_if), + .csr_mcause_if(cv32e40s_wrapper.rvfi_csr_mcause_if), + .csr_mintthresh_if(cv32e40s_wrapper.rvfi_csr_mintthresh_if), + .csr_mintstatus_if(cv32e40s_wrapper.rvfi_csr_mintstatus_if), + .csr_dcsr_if(cv32e40s_wrapper.rvfi_csr_dcsr_if), + + .dpc (cs_registers_i.dpc_rdata), + .mintstatus (cs_registers_i.mintstatus_rdata), + .mintthresh (cs_registers_i.mintthresh_rdata), + .mcause (cs_registers_i.mcause_rdata), + .mtvec (cs_registers_i.mtvec_rdata), + .mtvt (cs_registers_i.mtvt_rdata), + .mepc (cs_registers_i.mepc_rdata), + .mip (cs_registers_i.mip_rdata), + .mie (cs_registers_i.mie_rdata), + .mnxti (cs_registers_i.mnxti_rdata), + .mscratch (cs_registers_i.mscratch_rdata), + .mscratchcsw (cs_registers_i.mscratchcsw_rdata), + .mscratchcswl (cs_registers_i.mscratchcswl_rdata), + .dcsr (cs_registers_i.dcsr_rdata), + + //Control signals: + .pc_set (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_set), + .pc_mux (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_mux), + + .rvfi_mepc_wdata (rvfi_i.rvfi_csr_mepc_wdata), + .rvfi_mepc_wmask (rvfi_i.rvfi_csr_mepc_wmask), + .rvfi_mepc_rdata (rvfi_i.rvfi_csr_mepc_rdata), + .rvfi_mepc_rmask (rvfi_i.rvfi_csr_mepc_rmask), + .rvfi_dpc_rdata (rvfi_i.rvfi_csr_dpc_rdata), + .rvfi_dpc_rmask (rvfi_i.rvfi_csr_dpc_rmask), + .rvfi_mscratch_rdata (rvfi_i.rvfi_csr_mscratch_rdata), + .rvfi_mscratch_rmask (rvfi_i.rvfi_csr_mscratch_rmask), + .rvfi_mscratch_wdata (rvfi_i.rvfi_csr_mscratch_wdata), + .rvfi_mscratch_wmask (rvfi_i.rvfi_csr_mscratch_wmask), + .rvfi_mcause_wdata (rvfi_i.rvfi_csr_mcause_wdata), + .rvfi_mcause_wmask (rvfi_i.rvfi_csr_mcause_wmask), + + .irq_i (core_i.irq_i), + .irq_ack (core_i.irq_ack), + .fetch_enable (core_i.fetch_enable), + .current_priv_mode (core_i.priv_lvl), + .mtvec_addr_i (core_i.mtvec_addr_i), + // External inputs + .clic_if (dut_wrap.clic_if), + // Internal sampled variants + .irq_id (core_i.irq_id[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH-1:0]), + .irq_level (core_i.irq_level), + .irq_priv (core_i.irq_priv), + .irq_shv (core_i.irq_shv), + + .obi_instr_req (core_i.instr_req_o), + .obi_instr_gnt (core_i.instr_gnt_i), + .obi_instr_rvalid (core_i.instr_rvalid_i), + .obi_instr_addr (core_i.instr_addr_o), + .obi_instr_rdata (core_i.instr_rdata_i), + .obi_instr_rready (1'b1), + .obi_instr_err (core_i.instr_err_i), + + .obi_data_addr (core_i.data_addr_o), + .obi_data_wdata (core_i.data_wdata_o), + .obi_data_we (core_i.data_we_o), + .obi_data_be (core_i.data_be_o), + .obi_data_req (core_i.data_req_o), + .obi_data_gnt (core_i.data_gnt_i), + .obi_data_rvalid (core_i.data_rvalid_i), + .obi_data_rready (1'b1), + .obi_data_err (core_i.data_err_i), + + .debug_mode (controller_i.controller_fsm_i.debug_mode_q), + .debug_req (core_i.debug_req_i), + .debug_havereset (core_i.debug_havereset_o), + .debug_running (core_i.debug_running_o), + .debug_halt_addr (dut_wrap.cv32e40s_wrapper_i.dm_halt_addr_i), + .debug_exc_addr (dut_wrap.cv32e40s_wrapper_i.dm_exception_addr_i), + + .rvfi_mode (rvfi_i.rvfi_mode), + .rvfi_insn (rvfi_i.rvfi_insn), + .rvfi_intr (rvfi_i.rvfi_intr), + .rvfi_rs1_rdata (rvfi_i.rvfi_rs1_rdata), + .rvfi_rs2_rdata (rvfi_i.rvfi_rs2_rdata), + .rvfi_rd_wdata (rvfi_i.rvfi_rd_wdata), + .rvfi_valid (rvfi_i.rvfi_valid), + .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), + .rvfi_pc_wdata (rvfi_i.rvfi_pc_wdata), + .rvfi_trap (rvfi_i.rvfi_trap), + .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), + .rvfi_dbg (rvfi_i.rvfi_dbg), + + .wu_wfe (dut_wrap.cv32e40s_wrapper_i.wu_wfe_i), + .core_sleep_o (core_i.core_sleep_o), + .* + ); + `endif end : gen_clic_assert // User-Mode Assertions - bind cv32e40s_wrapper - uvmt_cv32e40s_umode_assert #( - .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC) - ) umode_assert_i ( - .rvfi_valid (rvfi_i.rvfi_valid), - .rvfi_mode (rvfi_i.rvfi_mode), - .rvfi_order (rvfi_i.rvfi_order), - .rvfi_trap (rvfi_i.rvfi_trap), - .rvfi_intr (rvfi_i.rvfi_intr), - .rvfi_insn (rvfi_i.rvfi_insn), - .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), - .rvfi_dbg (rvfi_i.rvfi_dbg), - .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), - .rvfi_if (rvfi_instr_if), - - .rvfi_csr_dcsr_rdata (rvfi_i.rvfi_csr_dcsr_rdata), - .rvfi_csr_mcause_rdata (rvfi_i.rvfi_csr_mcause_rdata), - .rvfi_csr_mcause_wdata (rvfi_i.rvfi_csr_mcause_wdata), - .rvfi_csr_mcause_wmask (rvfi_i.rvfi_csr_mcause_wmask), - .rvfi_csr_mcounteren_rdata (rvfi_i.rvfi_csr_mcounteren_rdata), - .rvfi_csr_mie_rdata (rvfi_i.rvfi_csr_mie_rdata), - .rvfi_csr_mip_rdata (rvfi_i.rvfi_csr_mip_rdata), - .rvfi_csr_misa_rdata (rvfi_i.rvfi_csr_misa_rdata), - .rvfi_csr_mscratch_rdata (rvfi_i.rvfi_csr_mscratch_rdata), - .rvfi_csr_mscratch_rmask (rvfi_i.rvfi_csr_mscratch_rmask), - .rvfi_csr_mscratch_wdata (rvfi_i.rvfi_csr_mscratch_wdata), - .rvfi_csr_mscratch_wmask (rvfi_i.rvfi_csr_mscratch_wmask), - .rvfi_csr_mstateen0_rdata (rvfi_i.rvfi_csr_mstateen0_rdata), - .rvfi_csr_mstatus_rdata (rvfi_i.rvfi_csr_mstatus_rdata), - .rvfi_csr_mstatus_wdata (rvfi_i.rvfi_csr_mstatus_wdata), - .rvfi_csr_mstatus_wmask (rvfi_i.rvfi_csr_mstatus_wmask), - - .mpu_iside_valid (core_i.if_stage_i.mpu_i.core_trans_valid_i), - .mpu_iside_addr (core_i.if_stage_i.mpu_i.core_trans_i.addr), - - .obi_iside_prot (core_i.instr_prot_o), - .obi_dside_prot (core_i.data_prot_o), + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_umode_assert #( + .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC) + ) umode_assert_i ( + .rvfi_valid (rvfi_i.rvfi_valid), + .rvfi_mode (rvfi_i.rvfi_mode), + .rvfi_order (rvfi_i.rvfi_order), + .rvfi_trap (rvfi_i.rvfi_trap), + .rvfi_intr (rvfi_i.rvfi_intr), + .rvfi_insn (rvfi_i.rvfi_insn), + .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), + .rvfi_dbg (rvfi_i.rvfi_dbg), + .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), + .rvfi_if (rvfi_instr_if), + + .rvfi_csr_dcsr_rdata (rvfi_i.rvfi_csr_dcsr_rdata), + .rvfi_csr_mcause_rdata (rvfi_i.rvfi_csr_mcause_rdata), + .rvfi_csr_mcause_wdata (rvfi_i.rvfi_csr_mcause_wdata), + .rvfi_csr_mcause_wmask (rvfi_i.rvfi_csr_mcause_wmask), + .rvfi_csr_mcounteren_rdata (rvfi_i.rvfi_csr_mcounteren_rdata), + .rvfi_csr_mie_rdata (rvfi_i.rvfi_csr_mie_rdata), + .rvfi_csr_mip_rdata (rvfi_i.rvfi_csr_mip_rdata), + .rvfi_csr_misa_rdata (rvfi_i.rvfi_csr_misa_rdata), + .rvfi_csr_mscratch_rdata (rvfi_i.rvfi_csr_mscratch_rdata), + .rvfi_csr_mscratch_rmask (rvfi_i.rvfi_csr_mscratch_rmask), + .rvfi_csr_mscratch_wdata (rvfi_i.rvfi_csr_mscratch_wdata), + .rvfi_csr_mscratch_wmask (rvfi_i.rvfi_csr_mscratch_wmask), + .rvfi_csr_mstateen0_rdata (rvfi_i.rvfi_csr_mstateen0_rdata), + .rvfi_csr_mstatus_rdata (rvfi_i.rvfi_csr_mstatus_rdata), + .rvfi_csr_mstatus_wdata (rvfi_i.rvfi_csr_mstatus_wdata), + .rvfi_csr_mstatus_wmask (rvfi_i.rvfi_csr_mstatus_wmask), + + .mpu_iside_valid (core_i.if_stage_i.mpu_i.core_trans_valid_i), + .mpu_iside_addr (core_i.if_stage_i.mpu_i.core_trans_i.addr), + + .obi_iside_prot (core_i.instr_prot_o), + .obi_dside_prot (core_i.data_prot_o), - .* - ); + .* + ); + `endif // User-mode Coverage - bind cv32e40s_wrapper - uvmt_cv32e40s_umode_cov umode_cov_i ( - .rvfi_valid (rvfi_i.rvfi_valid), - .rvfi_trap (rvfi_i.rvfi_trap), - .rvfi_intr (rvfi_i.rvfi_intr), - .rvfi_insn (rvfi_i.rvfi_insn), - .rvfi_rs1_rdata (rvfi_i.rvfi_rs1_rdata), - .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), - .rvfi_mode (rvfi_i.rvfi_mode), - .rvfi_rd_addr (rvfi_i.rvfi_rd_addr), - .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), - .rvfi_order (rvfi_i.rvfi_order), - .rvfi_mem_rmask (rvfi_i.rvfi_mem_rmask), - .rvfi_mem_wmask (rvfi_i.rvfi_mem_wmask), - - .rvfi_csr_mstatus_rdata (rvfi_i.rvfi_csr_mstatus_rdata), - .rvfi_csr_mstatus_rmask (rvfi_i.rvfi_csr_mstatus_rmask), - .rvfi_csr_dcsr_rdata (rvfi_i.rvfi_csr_dcsr_rdata), - .rvfi_csr_dcsr_rmask (rvfi_i.rvfi_csr_dcsr_rmask), - - .obi_iside_req (core_i.instr_req_o), - .obi_iside_gnt (core_i.instr_gnt_i), - .obi_iside_addr (core_i.instr_addr_o), - .obi_iside_prot (core_i.instr_prot_o), + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_umode_cov umode_cov_i ( + .rvfi_valid (rvfi_i.rvfi_valid), + .rvfi_trap (rvfi_i.rvfi_trap), + .rvfi_intr (rvfi_i.rvfi_intr), + .rvfi_insn (rvfi_i.rvfi_insn), + .rvfi_rs1_rdata (rvfi_i.rvfi_rs1_rdata), + .rvfi_pc_rdata (rvfi_i.rvfi_pc_rdata), + .rvfi_mode (rvfi_i.rvfi_mode), + .rvfi_rd_addr (rvfi_i.rvfi_rd_addr), + .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), + .rvfi_order (rvfi_i.rvfi_order), + .rvfi_mem_rmask (rvfi_i.rvfi_mem_rmask), + .rvfi_mem_wmask (rvfi_i.rvfi_mem_wmask), + + .rvfi_csr_mstatus_rdata (rvfi_i.rvfi_csr_mstatus_rdata), + .rvfi_csr_mstatus_rmask (rvfi_i.rvfi_csr_mstatus_rmask), + .rvfi_csr_dcsr_rdata (rvfi_i.rvfi_csr_dcsr_rdata), + .rvfi_csr_dcsr_rmask (rvfi_i.rvfi_csr_dcsr_rmask), + + .obi_iside_req (core_i.instr_req_o), + .obi_iside_gnt (core_i.instr_gnt_i), + .obi_iside_addr (core_i.instr_addr_o), + .obi_iside_prot (core_i.instr_prot_o), - .* - ); + .* + ); + `endif // Fence.i assertions - bind cv32e40s_wrapper - uvmt_cv32e40s_fencei_assert #( - .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), - .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG) - ) fencei_assert_i ( - .wb_valid (core_i.wb_stage_i.wb_valid), - .wb_instr_valid (core_i.ex_wb_pipe.instr_valid), - .wb_sys_en (core_i.ex_wb_pipe.sys_en), - .wb_sys_fencei_insn (core_i.ex_wb_pipe.sys_fencei_insn), - .wb_pc (core_i.ex_wb_pipe.pc), - .wb_rdata (core_i.ex_wb_pipe.instr.bus_resp.rdata), - .wb_buffer_state (core_i.load_store_unit_i.write_buffer_i.state), - - .rvfi_valid (rvfi_i.rvfi_valid), - .rvfi_intr (rvfi_i.rvfi_intr.intr), - .rvfi_dbg_mode (rvfi_i.rvfi_dbg_mode), - .rvfi_insn (rvfi_i.rvfi_insn), + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_fencei_assert #( + .PMA_NUM_REGIONS (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_NUM_REGIONS), + .PMA_CFG (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMA_CFG) + ) fencei_assert_i ( + .wb_valid (core_i.wb_stage_i.wb_valid), + .wb_instr_valid (core_i.ex_wb_pipe.instr_valid), + .wb_sys_en (core_i.ex_wb_pipe.sys_en), + .wb_sys_fencei_insn (core_i.ex_wb_pipe.sys_fencei_insn), + .wb_pc (core_i.ex_wb_pipe.pc), + .wb_rdata (core_i.ex_wb_pipe.instr.bus_resp.rdata), + .wb_buffer_state (core_i.load_store_unit_i.write_buffer_i.state), - .* - ); + .rvfi_if (rvfi_instr_if), + + .* + ); + `endif // RVFI Asserts & Covers - bind dut_wrap.cv32e40s_wrapper_i.rvfi_i - uvmt_cv32e40s_rvfi_assert #( - .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC), - .CLIC_ID_WIDTH (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH) - ) rvfi_assert_i ( - .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), - .support_if (dut_wrap.cv32e40s_wrapper_i.support_logic_module_o_if.slave_mp), - .writebuf_ready_o (dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.write_buffer_i.ready_o), - .writebuf_valid_i (dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.write_buffer_i.valid_i), - .* - ); + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.rvfi_i + uvmt_cv32e40s_rvfi_assert #( + .CLIC (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC), + .CLIC_ID_WIDTH (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_CLIC_ID_WIDTH) + ) rvfi_assert_i ( + .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .support_if (dut_wrap.cv32e40s_wrapper_i.support_logic_module_o_if.slave_mp), + .writebuf_ready_o (dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.write_buffer_i.ready_o), + .writebuf_valid_i (dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.write_buffer_i.valid_i), + .* + ); + `endif - bind dut_wrap.cv32e40s_wrapper_i.rvfi_i - uvmt_cv32e40s_rvfi_cov rvfi_cov_i ( - .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), - .* - ); + `ifndef COREV_ASSERT_OFF + bind dut_wrap.cv32e40s_wrapper_i.rvfi_i + uvmt_cv32e40s_rvfi_cov rvfi_cov_i ( + .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), + .* + ); + `endif // Core integration assertions @@ -783,158 +795,98 @@ module uvmt_cv32e40s_tb; ); - bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_data_independent_timing_assert #( - .SECURE (SECURE) - ) xsecure_data_independent_timing_assert_i ( - - //Signals: - .clk_i (clknrst_if.clk), - .rst_ni (clknrst_if.reset_n), - - //Interfaces: - .rvfi_if (rvfi_instr_if), - .rvfi_cpuctrl (rvfi_csr_cpuctrl_if), - - //CSRs: - .dataindtiming_enabled (core_i.xsecure_ctrl.cpuctrl.dataindtiming) - ); + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_data_independent_timing_assert #( + .SECURE (SECURE) + ) xsecure_data_independent_timing_assert_i ( - bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_hardened_pc_assert #( - .SECURE (SECURE) - ) xsecure_hardened_pc_assert_i ( - - //Signals: - .clk_i (clknrst_if.clk), - .rst_ni (clknrst_if.reset_n), - - //CSRs: - .pc_hardening_enabled (core_i.xsecure_ctrl.cpuctrl.pc_hardening), - .dataindtiming_enabled (core_i.xsecure_ctrl.cpuctrl.dataindtiming), - - //Alert: - .alert_major_due_to_pc_err (core_i.alert_i.pc_err_i), - - //IF: - .if_valid (core_i.if_valid), - .ptr_in_if (core_i.if_stage_i.ptr_in_if_o), - .if_instr_cmpr (core_i.if_stage_i.compressed_decoder_i.is_compressed_o), - .if_pc (core_i.pc_if), - .dummy_insert (dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.dummy_insert), - - //ID: - .id_ready (core_i.id_ready), - .id_pc (core_i.id_stage_i.if_id_pipe_i.pc), - .id_last_op (core_i.if_id_pipe.last_op), - .id_first_op (core_i.if_id_pipe.first_op), - .jump_in_id (core_i.controller_i.controller_fsm_i.jump_in_id), - .kill_id (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_id), - .halt_id (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.halt_id), - - //EX: - .ex_first_op (core_i.id_ex_pipe.first_op), - .branch_in_ex (core_i.controller_i.controller_fsm_i.branch_in_ex), - .kill_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_ex), - .halt_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.halt_ex), - - //Controll signals: - .pc_set (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_set), - .pc_mux (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_mux), - - //Signals to glitch check: - .branch_target (core_i.ex_stage_i.branch_target_o), - .branch_decision (core_i.ex_stage_i.alu_i.cmp_result_o), - .jump_target (core_i.jump_target_id), - .mepc (core_i.cs_registers_i.mepc_rdata) + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), - ); + //Interfaces: + .rvfi_if (rvfi_instr_if), + .rvfi_cpuctrl (rvfi_csr_cpuctrl_if), - bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_reduced_profiling_infrastructure_assert #( - .SECURE (SECURE) - ) xsecure_reduced_profiling_infrastructure_assert_i ( + //CSRs: + .dataindtiming_enabled (core_i.xsecure_ctrl.cpuctrl.dataindtiming) + ); + `endif - //Signals: - .clk_i (clknrst_if.clk), - .rst_ni (clknrst_if.reset_n), + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_hardened_pc_assert #( + .SECURE (SECURE) + ) xsecure_hardened_pc_assert_i ( - .mhpmevent (core_i.cs_registers_i.mhpmevent_rdata), - .mhpmcounter (core_i.cs_registers_i.mhpmcounter_rdata), - .mcountinhibit (core_i.cs_registers_i.mcountinhibit_rdata) - ); + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), - bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_hardened_csrs_assert #( - .SECURE (SECURE) - ) xsecure_hardened_csrs_assert_i ( - - //Signals: - .clk_i (clknrst_if.clk), - .rst_ni (clknrst_if.reset_n), - - //Alert: - .alert_major (core_i.alert_major_o), - - //CSRs: - .mstateen0 (core_i.cs_registers_i.mstateen0_csr_i.rdata_q), - .priv_lvl (core_i.cs_registers_i.privlvl_user.priv_lvl_i.rdata_q), - .jvt (core_i.cs_registers_i.jvt_csr_i.rdata_q), - .mstatus (core_i.cs_registers_i.mstatus_csr_i.rdata_q), - .cpuctrl (core_i.cs_registers_i.xsecure.cpuctrl_csr_i.rdata_q), - .dcsr (core_i.cs_registers_i.gen_debug_csr.dcsr_csr_i.rdata_q), - .mepc (core_i.cs_registers_i.mepc_csr_i.rdata_q), - .mscratch (core_i.cs_registers_i.mscratch_csr_i.rdata_q), - - //Shadows: - .mstateen0_shadow (core_i.cs_registers_i.mstateen0_csr_i.gen_hardened.shadow_q), - .priv_lvl_shadow (core_i.cs_registers_i.privlvl_user.priv_lvl_i.gen_hardened.shadow_q), - .jvt_shadow (core_i.cs_registers_i.jvt_csr_i.gen_hardened.shadow_q), - .mstatus_shadow (core_i.cs_registers_i.mstatus_csr_i.gen_hardened.shadow_q), - .cpuctrl_shadow (core_i.cs_registers_i.xsecure.cpuctrl_csr_i.gen_hardened.shadow_q), - .dcsr_shadow (core_i.cs_registers_i.gen_debug_csr.dcsr_csr_i.gen_hardened.shadow_q), - .mepc_shadow (core_i.cs_registers_i.mepc_csr_i.gen_hardened.shadow_q), - .mscratch_shadow (core_i.cs_registers_i.mscratch_csr_i.gen_hardened.shadow_q) + //CSRs: + .pc_hardening_enabled (core_i.xsecure_ctrl.cpuctrl.pc_hardening), + .dataindtiming_enabled (core_i.xsecure_ctrl.cpuctrl.dataindtiming), - ); + //Alert: + .alert_major_due_to_pc_err (core_i.alert_i.pc_err_i), + + //IF: + .if_valid (core_i.if_valid), + .ptr_in_if (core_i.if_stage_i.ptr_in_if_o), + .if_instr_cmpr (core_i.if_stage_i.compressed_decoder_i.is_compressed_o), + .if_pc (core_i.pc_if), + .dummy_insert (dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.dummy_insert), + + //ID: + .id_ready (core_i.id_ready), + .id_pc (core_i.id_stage_i.if_id_pipe_i.pc), + .id_last_op (core_i.if_id_pipe.last_op), + .id_first_op (core_i.if_id_pipe.first_op), + .jump_in_id (core_i.controller_i.controller_fsm_i.jump_in_id), + .kill_id (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_id), + .halt_id (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.halt_id), + + //EX: + .ex_first_op (core_i.id_ex_pipe.first_op), + .branch_in_ex (core_i.controller_i.controller_fsm_i.branch_in_ex), + .kill_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_ex), + .halt_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.halt_ex), + + //Controll signals: + .pc_set (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_set), + .pc_mux (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.pc_mux), + + //Signals to glitch check: + .branch_target (core_i.ex_stage_i.branch_target_o), + .branch_decision (core_i.ex_stage_i.alu_i.cmp_result_o), + .jump_target (core_i.jump_target_id), + .mepc (core_i.cs_registers_i.mepc_rdata) - if (CORE_PARAM_CLIC == 1) begin: gen_hardened_csrs_clic_assert + ); + `endif + `ifndef COREV_ASSERT_OFF bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_hardened_csrs_clic_assert #( + uvmt_cv32e40s_xsecure_reduced_profiling_infrastructure_assert #( .SECURE (SECURE) - ) xsecure_hardened_csrs_clic_assert_i ( + ) xsecure_reduced_profiling_infrastructure_assert_i ( //Signals: .clk_i (clknrst_if.clk), .rst_ni (clknrst_if.reset_n), - //Alert: - .alert_major (core_i.alert_major_o), - - //CSRs: - .mcause (core_i.cs_registers_i.clic_csrs.mcause_csr_i.rdata_q), - .mtvt (core_i.cs_registers_i.clic_csrs.mtvt_csr_i.rdata_q), - .mtvec (core_i.cs_registers_i.clic_csrs.mtvec_csr_i.rdata_q), - .mintstatus (core_i.cs_registers_i.clic_csrs.mintstatus_csr_i.rdata_q), - .mintthresh (core_i.cs_registers_i.clic_csrs.mintthresh_csr_i.rdata_q), - - //Shadows: - .mcause_shadow (core_i.cs_registers_i.clic_csrs.mcause_csr_i.gen_hardened.shadow_q), - .mtvt_shadow (core_i.cs_registers_i.clic_csrs.mtvt_csr_i.gen_hardened.shadow_q), - .mtvec_shadow (core_i.cs_registers_i.clic_csrs.mtvec_csr_i.gen_hardened.shadow_q), - .mintstatus_shadow (core_i.cs_registers_i.clic_csrs.mintstatus_csr_i.gen_hardened.shadow_q), - .mintthresh_shadow (core_i.cs_registers_i.clic_csrs.mintthresh_csr_i.gen_hardened.shadow_q) - + .mhpmevent (core_i.cs_registers_i.mhpmevent_rdata), + .mhpmcounter (core_i.cs_registers_i.mhpmcounter_rdata), + .mcountinhibit (core_i.cs_registers_i.mcountinhibit_rdata) ); - end : gen_hardened_csrs_clic_assert - - if (CORE_PARAM_CLIC == 0) begin: gen_hardened_csrs_interrupt_assert + `endif + `ifndef COREV_ASSERT_OFF bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_hardened_csrs_interrupt_assert #( + uvmt_cv32e40s_xsecure_hardened_csrs_assert #( .SECURE (SECURE) - ) xsecure_hardened_csrs_interrupt_assert_i ( + ) xsecure_hardened_csrs_assert_i ( //Signals: .clk_i (clknrst_if.clk), @@ -944,15 +896,85 @@ module uvmt_cv32e40s_tb; .alert_major (core_i.alert_major_o), //CSRs: - .mcause (core_i.cs_registers_i.basic_mode_csrs.mcause_csr_i.rdata_q), - .mtvec (core_i.cs_registers_i.basic_mode_csrs.mtvec_csr_i.rdata_q), - .mie (core_i.cs_registers_i.basic_mode_csrs.mie_csr_i.rdata_q), + .mstateen0 (core_i.cs_registers_i.mstateen0_csr_i.rdata_q), + .priv_lvl (core_i.cs_registers_i.privlvl_user.priv_lvl_i.rdata_q), + .jvt (core_i.cs_registers_i.jvt_csr_i.rdata_q), + .mstatus (core_i.cs_registers_i.mstatus_csr_i.rdata_q), + .cpuctrl (core_i.cs_registers_i.xsecure.cpuctrl_csr_i.rdata_q), + .dcsr (core_i.cs_registers_i.gen_debug_csr.dcsr_csr_i.rdata_q), + .mepc (core_i.cs_registers_i.mepc_csr_i.rdata_q), + .mscratch (core_i.cs_registers_i.mscratch_csr_i.rdata_q), //Shadows: - .mcause_shadow (core_i.cs_registers_i.basic_mode_csrs.mcause_csr_i.gen_hardened.shadow_q), - .mtvec_shadow (core_i.cs_registers_i.basic_mode_csrs.mtvec_csr_i.gen_hardened.shadow_q), - .mie_shadow (core_i.cs_registers_i.basic_mode_csrs.mie_csr_i.gen_hardened.shadow_q) + .mstateen0_shadow (core_i.cs_registers_i.mstateen0_csr_i.gen_hardened.shadow_q), + .priv_lvl_shadow (core_i.cs_registers_i.privlvl_user.priv_lvl_i.gen_hardened.shadow_q), + .jvt_shadow (core_i.cs_registers_i.jvt_csr_i.gen_hardened.shadow_q), + .mstatus_shadow (core_i.cs_registers_i.mstatus_csr_i.gen_hardened.shadow_q), + .cpuctrl_shadow (core_i.cs_registers_i.xsecure.cpuctrl_csr_i.gen_hardened.shadow_q), + .dcsr_shadow (core_i.cs_registers_i.gen_debug_csr.dcsr_csr_i.gen_hardened.shadow_q), + .mepc_shadow (core_i.cs_registers_i.mepc_csr_i.gen_hardened.shadow_q), + .mscratch_shadow (core_i.cs_registers_i.mscratch_csr_i.gen_hardened.shadow_q) + ); + `endif + + if (CORE_PARAM_CLIC == 1) begin: gen_hardened_csrs_clic_assert + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_hardened_csrs_clic_assert #( + .SECURE (SECURE) + ) xsecure_hardened_csrs_clic_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alert: + .alert_major (core_i.alert_major_o), + + //CSRs: + .mcause (core_i.cs_registers_i.clic_csrs.mcause_csr_i.rdata_q), + .mtvt (core_i.cs_registers_i.clic_csrs.mtvt_csr_i.rdata_q), + .mtvec (core_i.cs_registers_i.clic_csrs.mtvec_csr_i.rdata_q), + .mintstatus (core_i.cs_registers_i.clic_csrs.mintstatus_csr_i.rdata_q), + .mintthresh (core_i.cs_registers_i.clic_csrs.mintthresh_csr_i.rdata_q), + + //Shadows: + .mcause_shadow (core_i.cs_registers_i.clic_csrs.mcause_csr_i.gen_hardened.shadow_q), + .mtvt_shadow (core_i.cs_registers_i.clic_csrs.mtvt_csr_i.gen_hardened.shadow_q), + .mtvec_shadow (core_i.cs_registers_i.clic_csrs.mtvec_csr_i.gen_hardened.shadow_q), + .mintstatus_shadow (core_i.cs_registers_i.clic_csrs.mintstatus_csr_i.gen_hardened.shadow_q), + .mintthresh_shadow (core_i.cs_registers_i.clic_csrs.mintthresh_csr_i.gen_hardened.shadow_q) + + ); + `endif + end : gen_hardened_csrs_clic_assert + + if (CORE_PARAM_CLIC == 0) begin: gen_hardened_csrs_interrupt_assert + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_hardened_csrs_interrupt_assert #( + .SECURE (SECURE) + ) xsecure_hardened_csrs_interrupt_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alert: + .alert_major (core_i.alert_major_o), + + //CSRs: + .mcause (core_i.cs_registers_i.basic_mode_csrs.mcause_csr_i.rdata_q), + .mtvec (core_i.cs_registers_i.basic_mode_csrs.mtvec_csr_i.rdata_q), + .mie (core_i.cs_registers_i.basic_mode_csrs.mie_csr_i.rdata_q), + + //Shadows: + .mcause_shadow (core_i.cs_registers_i.basic_mode_csrs.mcause_csr_i.gen_hardened.shadow_q), + .mtvec_shadow (core_i.cs_registers_i.basic_mode_csrs.mtvec_csr_i.gen_hardened.shadow_q), + .mie_shadow (core_i.cs_registers_i.basic_mode_csrs.mie_csr_i.gen_hardened.shadow_q) + ); + `endif end : gen_hardened_csrs_interrupt_assert @@ -975,12 +997,43 @@ module uvmt_cv32e40s_tb; end + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_hardened_csrs_pmp_assert #( + .SECURE (SECURE), + .PMP_ADDR_WIDTH (core_i.cs_registers_i.PMP_ADDR_WIDTH), + .PMP_NUM_REGIONS (PMP_NUM_REGIONS) + ) xsecure_hardened_csrs_pmp_assert_i ( + + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + + //Alert: + .alert_major (core_i.alert_major_o), + + //CSRs: + .pmp_mseccfg (core_i.cs_registers_i.csr_pmp.pmp_mseccfg_csr_i.rdata_q), + .pmpncfg (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmpncfg), + .pmp_addr (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmp_addr), + + //Shadows: + .pmp_mseccfg_shadow (core_i.cs_registers_i.csr_pmp.pmp_mseccfg_csr_i.gen_hardened.shadow_q), + .pmpncfg_shadow (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmpncfg_shadow), + .pmp_addr_shadow (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmp_addr_shadow) + ); + `endif + + end : gen_hardened_csrs_pmp_assert + + `ifndef COREV_ASSERT_OFF bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_hardened_csrs_pmp_assert #( - .SECURE (SECURE), - .PMP_ADDR_WIDTH (core_i.cs_registers_i.PMP_ADDR_WIDTH), - .PMP_NUM_REGIONS (PMP_NUM_REGIONS) - ) xsecure_hardened_csrs_pmp_assert_i ( + uvmt_cv32e40s_xsecure_register_file_ecc_assert #( + .SECURE (SECURE) + ) xsecure_register_file_ecc_assert_i ( + + //Interfaces: + .rvfi_if (rvfi_instr_if), //Signals: .clk_i (clknrst_if.clk), @@ -989,359 +1042,341 @@ module uvmt_cv32e40s_tb; //Alert: .alert_major (core_i.alert_major_o), - //CSRs: - .pmp_mseccfg (core_i.cs_registers_i.csr_pmp.pmp_mseccfg_csr_i.rdata_q), - .pmpncfg (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmpncfg), - .pmp_addr (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmp_addr), + //Register file memory: + .gpr_mem (core_i.register_file_wrapper_i.register_file_i.mem_gated), - //Shadows: - .pmp_mseccfg_shadow (core_i.cs_registers_i.csr_pmp.pmp_mseccfg_csr_i.gen_hardened.shadow_q), - .pmpncfg_shadow (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmpncfg_shadow), - .pmp_addr_shadow (uvmt_cv32e40s_tb.gen_hardened_csrs_pmp_assert.pmp_addr_shadow) - ); + //Soruce registers: + .rs1 (core_i.if_id_pipe.instr.bus_resp.rdata[19:15]), + .rs2 (core_i.if_id_pipe.instr.bus_resp.rdata[24:20]), - end : gen_hardened_csrs_pmp_assert + //Writing of GPRs: + .gpr_we (core_i.rf_we_wb), + .gpr_waddr (core_i.rf_waddr_wb), + .gpr_wdata (core_i.rf_wdata_wb) - bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_register_file_ecc_assert #( + ); + `endif + + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_security_alerts_assert #( .SECURE (SECURE) - ) xsecure_register_file_ecc_assert_i ( + ) xsecure_security_alerts_assert_i ( - //Interfaces: - .rvfi_if (rvfi_instr_if), + //Interfaces: + .rvfi_if (rvfi_instr_if), + .support_if (support_logic_module_o_if.slave_mp), - //Signals: - .clk_i (clknrst_if.clk), - .rst_ni (clknrst_if.reset_n), + //Signals: + .rst_ni (clknrst_if.reset_n), + .clk_i (clknrst_if.clk), - //Alert: - .alert_major (core_i.alert_major_o), + //alerts: + .alert_minor (core_i.alert_minor_o), + .alert_major (core_i.alert_major_o), - //Register file memory: - .gpr_mem (core_i.register_file_wrapper_i.register_file_i.mem_gated), + //wb: + .wb_valid (core_i.wb_valid), + .exception_in_wb (core_i.controller_i.controller_fsm_i.exception_in_wb), + .exception_cause_wb (core_i.controller_i.controller_fsm_i.exception_cause_wb), + + //dummy and hint: + .dummy_en (core_i.xsecure_ctrl.cpuctrl.rnddummy), + .hint_en (core_i.xsecure_ctrl.cpuctrl.rndhint), + .lfsr0_clock_en (core_i.cs_registers_i.xsecure.lfsr0_i.clock_en), + .lfsr1_clock_en (core_i.cs_registers_i.xsecure.lfsr1_i.clock_en), + .lfsr2_clock_en (core_i.cs_registers_i.xsecure.lfsr2_i.clock_en), + .seed0_we (core_i.cs_registers_i.xsecure.lfsr0_i.seed_we_i), + .seed1_we (core_i.cs_registers_i.xsecure.lfsr1_i.seed_we_i), + .seed2_we (core_i.cs_registers_i.xsecure.lfsr2_i.seed_we_i), + .seed0_i (core_i.cs_registers_i.xsecure.lfsr0_i.seed_i), + .seed1_i (core_i.cs_registers_i.xsecure.lfsr1_i.seed_i), + .seed2_i (core_i.cs_registers_i.xsecure.lfsr2_i.seed_i), + .lfsr0_n (core_i.cs_registers_i.xsecure.lfsr0_i.lfsr_n), + .lfsr1_n (core_i.cs_registers_i.xsecure.lfsr1_i.lfsr_n), + .lfsr2_n (core_i.cs_registers_i.xsecure.lfsr2_i.lfsr_n), + + //OBI: + .obi_data_rvalid (core_i.data_rvalid_i), + .obi_data_err (core_i.data_err_i), + + //NMI: + .nmip (core_i.dcsr.nmip), + + //debug: + .debug_mode (core_i.controller_i.controller_fsm_i.debug_mode_q) - //Soruce registers: - .rs1 (core_i.if_id_pipe.instr.bus_resp.rdata[19:15]), - .rs2 (core_i.if_id_pipe.instr.bus_resp.rdata[24:20]), + ); + `endif - //Writing of GPRs: - .gpr_we (core_i.rf_we_wb), - .gpr_waddr (core_i.rf_waddr_wb), - .gpr_wdata (core_i.rf_wdata_wb) + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert #( + .SECURE (SECURE) + ) xsecure_bus_protocol_hardening_assert_i ( - ); + //Interfaces: + .support_if (support_logic_module_o_if.slave_mp), - bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_security_alerts_assert #( - .SECURE (SECURE) - ) xsecure_security_alerts_assert_i ( + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), - //Interfaces: - .rvfi_if (rvfi_instr_if), - .support_if (support_logic_module_o_if.slave_mp), + //Alerts: + .alert_major (core_i.alert_major_o), + .bus_protocol_hardening_glitch (core_i.alert_i.itf_prot_err_i), - //Signals: - .rst_ni (clknrst_if.reset_n), - .clk_i (clknrst_if.clk), - - //alerts: - .alert_minor (core_i.alert_minor_o), - .alert_major (core_i.alert_major_o), - - //wb: - .wb_valid (core_i.wb_valid), - .exception_in_wb (core_i.controller_i.controller_fsm_i.exception_in_wb), - .exception_cause_wb (core_i.controller_i.controller_fsm_i.exception_cause_wb), - - //dummy and hint: - .dummy_en (core_i.xsecure_ctrl.cpuctrl.rnddummy), - .hint_en (core_i.xsecure_ctrl.cpuctrl.rndhint), - .lfsr0_clock_en (core_i.cs_registers_i.xsecure.lfsr0_i.clock_en), - .lfsr1_clock_en (core_i.cs_registers_i.xsecure.lfsr1_i.clock_en), - .lfsr2_clock_en (core_i.cs_registers_i.xsecure.lfsr2_i.clock_en), - .seed0_we (core_i.cs_registers_i.xsecure.lfsr0_i.seed_we_i), - .seed1_we (core_i.cs_registers_i.xsecure.lfsr1_i.seed_we_i), - .seed2_we (core_i.cs_registers_i.xsecure.lfsr2_i.seed_we_i), - .seed0_i (core_i.cs_registers_i.xsecure.lfsr0_i.seed_i), - .seed1_i (core_i.cs_registers_i.xsecure.lfsr1_i.seed_i), - .seed2_i (core_i.cs_registers_i.xsecure.lfsr2_i.seed_i), - .lfsr0_n (core_i.cs_registers_i.xsecure.lfsr0_i.lfsr_n), - .lfsr1_n (core_i.cs_registers_i.xsecure.lfsr1_i.lfsr_n), - .lfsr2_n (core_i.cs_registers_i.xsecure.lfsr2_i.lfsr_n), - - //OBI: - .obi_data_rvalid (core_i.data_rvalid_i), - .obi_data_err (core_i.data_err_i), - - //NMI: - .nmip (core_i.dcsr.nmip), - - //debug: - .debug_mode (core_i.controller_i.controller_fsm_i.debug_mode_q) + //OBI: + .obi_data_rvalid (core_i.m_c_obi_data_if.s_rvalid.rvalid), + .obi_instr_rvalid (core_i.m_c_obi_instr_if.s_rvalid.rvalid), - ); + //Resp valids: + .instr_if_mpu_resp (core_i.if_stage_i.prefetch_resp_valid), + .lsu_mpu_resp (core_i.load_store_unit_i.resp_valid), - bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert #( - .SECURE (SECURE) - ) xsecure_bus_protocol_hardening_assert_i ( + //Counters: + .lsu_rf_core_side_cnt (core_i.load_store_unit_i.response_filter_i.core_cnt_q), + .lsu_rf_bus_side_cnt (core_i.load_store_unit_i.response_filter_i.bus_cnt_q) - //Interfaces: - .support_if (support_logic_module_o_if.slave_mp), + ); + `endif - //Signals: - .clk_i (clknrst_if.clk), - .rst_ni (clknrst_if.reset_n), + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_interface_integrity_assert #( + .SECURE (SECURE), + .ALBUF_DEPTH (core_i.if_stage_i.ALBUF_DEPTH), + .ALBUF_CNT_WIDTH (core_i.if_stage_i.ALBUF_CNT_WIDTH) + ) xsecure_interface_integrity_assert_i ( - //Alerts: - .alert_major (core_i.alert_major_o), - .bus_protocol_hardening_glitch (core_i.alert_i.itf_prot_err_i), + //Interfaces: + .support_if (support_logic_module_o_if.slave_mp), - //OBI: - .obi_data_rvalid (core_i.m_c_obi_data_if.s_rvalid.rvalid), - .obi_instr_rvalid (core_i.m_c_obi_instr_if.s_rvalid.rvalid), + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), - //Resp valids: - .instr_if_mpu_resp (core_i.if_stage_i.prefetch_resp_valid), - .lsu_mpu_resp (core_i.load_store_unit_i.resp_valid), + //Alert: + .alert_major (core_i.alert_major_o), + .alert_major_due_to_integrity_err (core_i.alert_i.itf_int_err_i), - //Counters: - .lsu_rf_core_side_cnt (core_i.load_store_unit_i.response_filter_i.core_cnt_q), - .lsu_rf_bus_side_cnt (core_i.load_store_unit_i.response_filter_i.bus_cnt_q) + //CSRs: + .integrity_enabled (core_i.xsecure_ctrl.cpuctrl.integrity), + .nmip (core_i.cs_registers_i.dcsr_rdata.nmip), + .mcause_exception_code (core_i.cs_registers_i.mcause_rdata.exception_code), + + //OBI data: + .obi_data_req_packet (core_i.m_c_obi_data_if.req_payload), + .obi_data_resp_packet (core_i.m_c_obi_data_if.resp_payload), + .obi_data_addr (core_i.data_addr_o), + .obi_data_req (core_i.m_c_obi_data_if.s_req.req), + .obi_data_reqpar (core_i.m_c_obi_data_if.s_req.reqpar), + .obi_data_gnt (core_i.m_c_obi_data_if.s_gnt.gnt), + .obi_data_gntpar (core_i.m_c_obi_data_if.s_gnt.gntpar), + .obi_data_rvalid (core_i.m_c_obi_data_if.s_rvalid.rvalid), + .obi_data_rvalidpar (core_i.m_c_obi_data_if.s_rvalid.rvalidpar), + + //OBI instr: + .obi_instr_req_packet (core_i.m_c_obi_instr_if.req_payload), + .obi_instr_resp_packet (core_i.m_c_obi_instr_if.resp_payload), + .obi_instr_addr (core_i.instr_addr_o), + .obi_instr_req (core_i.m_c_obi_instr_if.s_req.req), + .obi_instr_reqpar (core_i.m_c_obi_instr_if.s_req.reqpar), + .obi_instr_gnt (core_i.m_c_obi_instr_if.s_gnt.gnt), + .obi_instr_gntpar (core_i.m_c_obi_instr_if.s_gnt.gntpar), + .obi_instr_rvalid (core_i.m_c_obi_instr_if.s_rvalid.rvalid), + .obi_instr_rvalidpar (core_i.m_c_obi_instr_if.s_rvalid.rvalidpar), + + //Register file memory: + .gpr_mem (core_i.register_file_wrapper_i.register_file_i.mem_gated), + .rf_we (core_i.rf_we_wb), + .rf_waddr (core_i.rf_waddr_wb), + .rf_wdata (core_i.rf_wdata_wb), + + //Alignment buffer: + .alb_resp_i (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.resp_i), + .alb_resp_q (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.resp_q), + .alb_valid (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.valid_q), + .alb_wptr (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.wptr), + .alb_rptr1 (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.rptr), + .alb_rptr2 (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.rptr2), + + //If: + .if_valid (core_i.if_valid), + .if_instr_integrity_err (core_i.if_stage_i.bus_resp.integrity_err), + .if_instr_cmpr (core_i.if_stage_i.compressed_decoder_i.is_compressed_o), + .if_instr_pc (core_i.if_stage_i.pc_if_o), + .dummy_insert (dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.dummy_insert), + + //Id: + .id_ready (core_i.id_ready), + .id_instr_integrity_err (core_i.if_id_pipe.instr.bus_resp.integrity_err), + .id_abort_op (dut_wrap.cv32e40s_wrapper_i.core_i.if_id_pipe.abort_op), + .id_illegal_insn (dut_wrap.cv32e40s_wrapper_i.core_i.if_id_pipe.illegal_c_insn), + + //Wb: + .wb_valid (core_i.wb_valid), + .wb_integrity_err (core_i.ex_wb_pipe.instr.bus_resp.integrity_err), + .wb_instr_opcode (core_i.ex_wb_pipe.instr.bus_resp.rdata[6:0]), + .wb_exception (core_i.controller_i.controller_fsm_i.exception_in_wb), + .wb_exception_code (core_i.controller_i.controller_fsm_i.exception_cause_wb), + .data_integrity_err (core_i.load_store_unit_i.bus_resp.integrity_err), + + //MISC: + .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), + .pc_mux (dut_wrap.cv32e40s_wrapper_i.core_i.ctrl_fsm.pc_mux), + .pc_set (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.ctrl_fsm_i.pc_set), + .seq_valid (core_i.if_stage_i.seq_valid), + .kill_if (core_i.ctrl_fsm.kill_if), + .n_flush_q (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.n_flush_q), + .rchk_err_instr (core_i.if_stage_i.instruction_obi_i.rchk_err_resp), + .rchk_err_data (core_i.load_store_unit_i.data_obi_i.rchk_err_resp) - ); + ); + `endif - bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_interface_integrity_assert #( - .SECURE (SECURE), - .ALBUF_DEPTH (core_i.if_stage_i.ALBUF_DEPTH), - .ALBUF_CNT_WIDTH (core_i.if_stage_i.ALBUF_CNT_WIDTH) - ) xsecure_interface_integrity_assert_i ( - //Interfaces: - .support_if (support_logic_module_o_if.slave_mp), + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_xsecure_dummy_and_hint_assert #( + .SECURE (SECURE) + ) xsecure_dummy_and_hint_assert_i ( - //Signals: - .clk_i (clknrst_if.clk), - .rst_ni (clknrst_if.reset_n), - - //Alert: - .alert_major (core_i.alert_major_o), - .alert_major_due_to_integrity_err (core_i.alert_i.itf_int_err_i), - - //CSRs: - .integrity_enabled (core_i.xsecure_ctrl.cpuctrl.integrity), - .nmip (core_i.cs_registers_i.dcsr_rdata.nmip), - .mcause_exception_code (core_i.cs_registers_i.mcause_rdata.exception_code), - - //OBI data: - .obi_data_req_packet (core_i.m_c_obi_data_if.req_payload), - .obi_data_resp_packet (core_i.m_c_obi_data_if.resp_payload), - .obi_data_addr (core_i.data_addr_o), - .obi_data_req (core_i.m_c_obi_data_if.s_req.req), - .obi_data_reqpar (core_i.m_c_obi_data_if.s_req.reqpar), - .obi_data_gnt (core_i.m_c_obi_data_if.s_gnt.gnt), - .obi_data_gntpar (core_i.m_c_obi_data_if.s_gnt.gntpar), - .obi_data_rvalid (core_i.m_c_obi_data_if.s_rvalid.rvalid), - .obi_data_rvalidpar (core_i.m_c_obi_data_if.s_rvalid.rvalidpar), - - //OBI instr: - .obi_instr_req_packet (core_i.m_c_obi_instr_if.req_payload), - .obi_instr_resp_packet (core_i.m_c_obi_instr_if.resp_payload), - .obi_instr_addr (core_i.instr_addr_o), - .obi_instr_req (core_i.m_c_obi_instr_if.s_req.req), - .obi_instr_reqpar (core_i.m_c_obi_instr_if.s_req.reqpar), - .obi_instr_gnt (core_i.m_c_obi_instr_if.s_gnt.gnt), - .obi_instr_gntpar (core_i.m_c_obi_instr_if.s_gnt.gntpar), - .obi_instr_rvalid (core_i.m_c_obi_instr_if.s_rvalid.rvalid), - .obi_instr_rvalidpar (core_i.m_c_obi_instr_if.s_rvalid.rvalidpar), - - //Register file memory: - .gpr_mem (core_i.register_file_wrapper_i.register_file_i.mem_gated), - .rf_we (core_i.rf_we_wb), - .rf_waddr (core_i.rf_waddr_wb), - .rf_wdata (core_i.rf_wdata_wb), - - //Alignment buffer: - .alb_resp_i (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.resp_i), - .alb_resp_q (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.resp_q), - .alb_valid (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.valid_q), - .alb_wptr (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.wptr), - .alb_rptr1 (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.rptr), - .alb_rptr2 (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.rptr2), - - //If: - .if_valid (core_i.if_valid), - .if_instr_integrity_err (core_i.if_stage_i.bus_resp.integrity_err), - .if_instr_cmpr (core_i.if_stage_i.compressed_decoder_i.is_compressed_o), - .if_instr_pc (core_i.if_stage_i.pc_if_o), - .dummy_insert (dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.dummy_insert), - - //Id: - .id_ready (core_i.id_ready), - .id_instr_integrity_err (core_i.if_id_pipe.instr.bus_resp.integrity_err), - .id_abort_op (dut_wrap.cv32e40s_wrapper_i.core_i.if_id_pipe.abort_op), - .id_illegal_insn (dut_wrap.cv32e40s_wrapper_i.core_i.if_id_pipe.illegal_c_insn), - - //Wb: - .wb_valid (core_i.wb_valid), - .wb_integrity_err (core_i.ex_wb_pipe.instr.bus_resp.integrity_err), - .wb_instr_opcode (core_i.ex_wb_pipe.instr.bus_resp.rdata[6:0]), - .wb_exception (core_i.controller_i.controller_fsm_i.exception_in_wb), - .wb_exception_code (core_i.controller_i.controller_fsm_i.exception_cause_wb), - .data_integrity_err (core_i.load_store_unit_i.bus_resp.integrity_err), - - //MISC: - .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), - .pc_mux (dut_wrap.cv32e40s_wrapper_i.core_i.ctrl_fsm.pc_mux), - .pc_set (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.ctrl_fsm_i.pc_set), - .seq_valid (core_i.if_stage_i.seq_valid), - .kill_if (core_i.ctrl_fsm.kill_if), - .n_flush_q (core_i.if_stage_i.prefetch_unit_i.alignment_buffer_i.n_flush_q), - .rchk_err_instr (core_i.if_stage_i.instruction_obi_i.rchk_err_resp), - .rchk_err_data (core_i.load_store_unit_i.data_obi_i.rchk_err_resp) + //Interfaces: + .rvfi_if (rvfi_instr_if), + .rvfi_mcountinhibit_if (rvfi_csr_mcountinhibit_if), + .rvfi_dcsr_if (rvfi_csr_dcsr_if), - ); + //Signals: + .clk_i (clknrst_if.clk), + .rst_ni (clknrst_if.reset_n), + .gated_clk_enabled (core_i.sleep_unit_i.clock_en), - bind cv32e40s_wrapper - uvmt_cv32e40s_xsecure_dummy_and_hint_assert #( - .SECURE (SECURE) - ) xsecure_dummy_and_hint_assert_i ( - - //Interfaces: - .rvfi_if (rvfi_instr_if), - .rvfi_mcountinhibit_if (rvfi_csr_mcountinhibit_if), - .rvfi_dcsr_if (rvfi_csr_dcsr_if), - - //Signals: - .clk_i (clknrst_if.clk), - .rst_ni (clknrst_if.reset_n), - - .gated_clk_enabled (core_i.sleep_unit_i.clock_en), - - //CSRs: - .rnddummy_enabled (core_i.xsecure_ctrl.cpuctrl.rnddummy), - .rndhint_enabled (core_i.xsecure_ctrl.cpuctrl.rndhint), - .dummy_freq (core_i.xsecure_ctrl.cpuctrl.rnddummyfreq), - .mhpmcounter (core_i.cs_registers_i.mhpmcounter_rdata), - .mcountinhibit (core_i.cs_registers_i.mcountinhibit_rdata), - .csr_waddr(core_i.cs_registers_i.csr_waddr), - - //LFSR: - .lfsr0_seed_we (core_i.cs_registers_i.xsecure.lfsr0_i.seed_we_i), - .lfsr1_seed_we (core_i.cs_registers_i.xsecure.lfsr1_i.seed_we_i), - .lfsr2_seed_we (core_i.cs_registers_i.xsecure.lfsr2_i.seed_we_i), - .lfsr0_seed (core_i.cs_registers_i.xsecure.lfsr0_i.seed_i), - .lfsr1_seed (core_i.cs_registers_i.xsecure.lfsr1_i.seed_i), - .lfsr2_seed (core_i.cs_registers_i.xsecure.lfsr2_i.seed_i), - .lfsr0 (core_i.cs_registers_i.xsecure.lfsr0_i.lfsr_q), - .lfsr1 (core_i.cs_registers_i.xsecure.lfsr1_i.lfsr_q), - .lfsr2 (core_i.cs_registers_i.xsecure.lfsr2_i.lfsr_q), - .lfsr0_n (core_i.cs_registers_i.xsecure.lfsr0_i.lfsr_n), - .lfsr1_n (core_i.cs_registers_i.xsecure.lfsr1_i.lfsr_n), - .lfsr2_n (core_i.cs_registers_i.xsecure.lfsr2_i.lfsr_n), - .lfsr0_clk_en (core_i.cs_registers_i.xsecure.lfsr0_i.clock_en), - .lfsr1_clk_en (core_i.cs_registers_i.xsecure.lfsr1_i.clock_en), - .lfsr2_clk_en (core_i.cs_registers_i.xsecure.lfsr2_i.clock_en), - - //IF: - .if_hint (core_i.if_stage_i.instr_hint), - .if_dummy (core_i.if_stage_i.dummy_insert), - .kill_if (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_if), - .if_valid (core_i.if_valid), - .ptr_in_if (core_i.if_stage_i.ptr_in_if_o), - .if_first_op (core_i.if_stage_i.first_op), - - //ID: - .operand_a (core_i.id_stage_i.operand_a), - .operand_b (core_i.id_stage_i.operand_b), - .id_instr (core_i.if_id_pipe.instr.bus_resp.rdata), - .id_dummy (core_i.if_id_pipe.instr_meta.dummy), - .id_hint (core_i.if_id_pipe.instr_meta.hint), - .kill_id (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_id), - .id_ready (core_i.id_ready), - .id_valid (core_i.id_valid), - .id_last_op (core_i.id_stage_i.last_op), - - //EX: - .kill_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_ex), - .ex_ready (core_i.ex_ready), - - //WB: - .kill_wb (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_wb), - .wb_dummy (core_i.ex_wb_pipe.instr_meta.dummy), - .wb_hint (core_i.ex_wb_pipe.instr_meta.hint), - .wb_valid (core_i.wb_valid), - .wb_instr (core_i.ex_wb_pipe.instr.bus_resp.rdata), + //CSRs: + .rnddummy_enabled (core_i.xsecure_ctrl.cpuctrl.rnddummy), + .rndhint_enabled (core_i.xsecure_ctrl.cpuctrl.rndhint), + .dummy_freq (core_i.xsecure_ctrl.cpuctrl.rnddummyfreq), + .mhpmcounter (core_i.cs_registers_i.mhpmcounter_rdata), + .mcountinhibit (core_i.cs_registers_i.mcountinhibit_rdata), + .csr_waddr(core_i.cs_registers_i.csr_waddr), + + //LFSR: + .lfsr0_seed_we (core_i.cs_registers_i.xsecure.lfsr0_i.seed_we_i), + .lfsr1_seed_we (core_i.cs_registers_i.xsecure.lfsr1_i.seed_we_i), + .lfsr2_seed_we (core_i.cs_registers_i.xsecure.lfsr2_i.seed_we_i), + .lfsr0_seed (core_i.cs_registers_i.xsecure.lfsr0_i.seed_i), + .lfsr1_seed (core_i.cs_registers_i.xsecure.lfsr1_i.seed_i), + .lfsr2_seed (core_i.cs_registers_i.xsecure.lfsr2_i.seed_i), + .lfsr0 (core_i.cs_registers_i.xsecure.lfsr0_i.lfsr_q), + .lfsr1 (core_i.cs_registers_i.xsecure.lfsr1_i.lfsr_q), + .lfsr2 (core_i.cs_registers_i.xsecure.lfsr2_i.lfsr_q), + .lfsr0_n (core_i.cs_registers_i.xsecure.lfsr0_i.lfsr_n), + .lfsr1_n (core_i.cs_registers_i.xsecure.lfsr1_i.lfsr_n), + .lfsr2_n (core_i.cs_registers_i.xsecure.lfsr2_i.lfsr_n), + .lfsr0_clk_en (core_i.cs_registers_i.xsecure.lfsr0_i.clock_en), + .lfsr1_clk_en (core_i.cs_registers_i.xsecure.lfsr1_i.clock_en), + .lfsr2_clk_en (core_i.cs_registers_i.xsecure.lfsr2_i.clock_en), + + //IF: + .if_hint (core_i.if_stage_i.instr_hint), + .if_dummy (core_i.if_stage_i.dummy_insert), + .kill_if (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_if), + .if_valid (core_i.if_valid), + .ptr_in_if (core_i.if_stage_i.ptr_in_if_o), + .if_first_op (core_i.if_stage_i.first_op), + + //ID: + .operand_a (core_i.id_stage_i.operand_a), + .operand_b (core_i.id_stage_i.operand_b), + .id_instr (core_i.if_id_pipe.instr.bus_resp.rdata), + .id_dummy (core_i.if_id_pipe.instr_meta.dummy), + .id_hint (core_i.if_id_pipe.instr_meta.hint), + .kill_id (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_id), + .id_ready (core_i.id_ready), + .id_valid (core_i.id_valid), + .id_last_op (core_i.id_stage_i.last_op), + + //EX: + .kill_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_ex), + .ex_ready (core_i.ex_ready), + + //WB: + .kill_wb (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.kill_wb), + .wb_dummy (core_i.ex_wb_pipe.instr_meta.dummy), + .wb_hint (core_i.ex_wb_pipe.instr_meta.hint), + .wb_valid (core_i.wb_valid), + .wb_instr (core_i.ex_wb_pipe.instr.bus_resp.rdata), - //Controller: - .debug_mode (core_i.controller_i.controller_fsm_i.debug_mode_q), - .stopcount_in_debug (core_i.cs_registers_i.debug_stopcount) - ); + //Controller: + .debug_mode (core_i.controller_i.controller_fsm_i.debug_mode_q), + .stopcount_in_debug (core_i.cs_registers_i.debug_stopcount) + ); + `endif // Debug assertion and coverage interface // Instantiate debug assertions - bind cv32e40s_wrapper - uvmt_cv32e40s_debug_cov_assert_if_t debug_cov_assert_if ( - .id_valid (core_i.id_stage_i.id_valid_o), - .sys_fence_insn_i (core_i.id_stage_i.decoder_i.sys_fencei_insn_o), - - .ex_stage_csr_en (core_i.id_ex_pipe.csr_en), - .ex_valid (core_i.ex_stage_i.instr_valid), - .ex_stage_instr_rdata_i (core_i.id_ex_pipe.instr.bus_resp.rdata), - .ex_stage_pc (core_i.id_ex_pipe.pc), - - .wb_stage_instr_rdata_i (core_i.ex_wb_pipe.instr.bus_resp.rdata), - .wb_stage_instr_valid_i (core_i.ex_wb_pipe.instr_valid), - .wb_stage_pc (core_i.wb_stage_i.ex_wb_pipe_i.pc), - .wb_err (core_i.ex_wb_pipe.instr.bus_resp.err), - .wb_illegal (core_i.ex_wb_pipe.illegal_insn), - .wb_valid (core_i.wb_stage_i.wb_valid_o), - .wb_mpu_status (core_i.ex_wb_pipe.instr.mpu_status), - .illegal_insn_i (core_i.ex_wb_pipe.illegal_insn), - .sys_en_i (core_i.ex_wb_pipe.sys_en), - .sys_ecall_insn_i (core_i.ex_wb_pipe.sys_ecall_insn), - - .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), - .debug_req_i (core_i.controller_i.controller_fsm_i.debug_req_i), - .debug_havereset (core_i.debug_havereset_o), - .debug_running (core_i.debug_running_o), - .debug_halted (core_i.debug_halted_o), - .debug_pc_o (core_i.debug_pc_o), - .debug_pc_valid_o (core_i.debug_pc_valid_o), - - .ctrl_fsm_async_debug_allowed (core_i.controller_i.controller_fsm_i.async_debug_allowed), - .pending_sync_debug (core_i.controller_i.controller_fsm_i.pending_sync_debug), - .pending_async_debug (core_i.controller_i.controller_fsm_i.pending_async_debug), - .pending_nmi (core_i.controller_i.controller_fsm_i.pending_nmi), - .nmi_allowed (core_i.controller_i.controller_fsm_i.nmi_allowed), - .debug_mode_q (core_i.controller_i.controller_fsm_i.debug_mode_q), - .debug_mode_if (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.debug_mode_if), - .ctrl_halt_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.halt_ex), - .trigger_match_in_wb (core_i.controller_i.controller_fsm_i.trigger_match_in_wb), - .etrigger_in_wb (core_i.controller_i.controller_fsm_i.etrigger_in_wb), - .branch_in_ex (core_i.controller_i.controller_fsm_i.branch_in_ex), - - .mie_q (core_i.cs_registers_i.mie_q), - .dcsr_q (core_i.cs_registers_i.dcsr_q), - .dpc_q (core_i.cs_registers_i.dpc_q), - .dpc_n (core_i.cs_registers_i.dpc_n), - .mcause_q (core_i.cs_registers_i.mcause_q), - .mtvec (core_i.cs_registers_i.mtvec_q), - .mepc_q (core_i.cs_registers_i.mepc_q), - .tdata1 (core_i.cs_registers_i.tdata1_rdata), - .tdata2 (core_i.cs_registers_i.tdata2_rdata), - .mcountinhibit_q (core_i.cs_registers_i.mcountinhibit_q), - .mcycle (core_i.cs_registers_i.mhpmcounter_q[0]), - .minstret (core_i.cs_registers_i.mhpmcounter_q[2]), - .csr_we_int (core_i.cs_registers_i.csr_we_int), - - // TODO: review this change from CV32E40S_HASH f6196bf to a26b194. It should be logically equivalent. - //assign debug_cov_assert_if.inst_ret = core_i.cs_registers_i.inst_ret; + `ifndef COREV_ASSERT_OFF + bind cv32e40s_wrapper + uvmt_cv32e40s_debug_cov_assert_if_t debug_cov_assert_if ( + .id_valid (core_i.id_stage_i.id_valid_o), + .sys_fence_insn_i (core_i.id_stage_i.decoder_i.sys_fencei_insn_o), + + .ex_stage_csr_en (core_i.id_ex_pipe.csr_en), + .ex_valid (core_i.ex_stage_i.instr_valid), + .ex_stage_instr_rdata_i (core_i.id_ex_pipe.instr.bus_resp.rdata), + .ex_stage_pc (core_i.id_ex_pipe.pc), + + .wb_stage_instr_rdata_i (core_i.ex_wb_pipe.instr.bus_resp.rdata), + .wb_stage_instr_valid_i (core_i.ex_wb_pipe.instr_valid), + .wb_stage_pc (core_i.wb_stage_i.ex_wb_pipe_i.pc), + .wb_err (core_i.ex_wb_pipe.instr.bus_resp.err), + .wb_illegal (core_i.ex_wb_pipe.illegal_insn), + .wb_valid (core_i.wb_stage_i.wb_valid_o), + .wb_mpu_status (core_i.ex_wb_pipe.instr.mpu_status), + .illegal_insn_i (core_i.ex_wb_pipe.illegal_insn), + .sys_en_i (core_i.ex_wb_pipe.sys_en), + .sys_ecall_insn_i (core_i.ex_wb_pipe.sys_ecall_insn), + + .ctrl_fsm_cs (core_i.controller_i.controller_fsm_i.ctrl_fsm_cs), + .debug_req_i (core_i.controller_i.controller_fsm_i.debug_req_i), + .debug_havereset (core_i.debug_havereset_o), + .debug_running (core_i.debug_running_o), + .debug_halted (core_i.debug_halted_o), + .debug_pc_o (core_i.debug_pc_o), + .debug_pc_valid_o (core_i.debug_pc_valid_o), + + .ctrl_fsm_async_debug_allowed (core_i.controller_i.controller_fsm_i.async_debug_allowed), + .pending_sync_debug (core_i.controller_i.controller_fsm_i.pending_sync_debug), + .pending_async_debug (core_i.controller_i.controller_fsm_i.pending_async_debug), + .pending_nmi (core_i.controller_i.controller_fsm_i.pending_nmi), + .nmi_allowed (core_i.controller_i.controller_fsm_i.nmi_allowed), + .debug_mode_q (core_i.controller_i.controller_fsm_i.debug_mode_q), + .debug_mode_if (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.debug_mode_if), + .ctrl_halt_ex (core_i.controller_i.controller_fsm_i.ctrl_fsm_o.halt_ex), + .trigger_match_in_wb (core_i.controller_i.controller_fsm_i.trigger_match_in_wb), + .etrigger_in_wb (core_i.controller_i.controller_fsm_i.etrigger_in_wb), + .branch_in_ex (core_i.controller_i.controller_fsm_i.branch_in_ex), + + .mie_q (core_i.cs_registers_i.mie_q), + .dcsr_q (core_i.cs_registers_i.dcsr_q), + .dpc_q (core_i.cs_registers_i.dpc_q), + .dpc_n (core_i.cs_registers_i.dpc_n), + .mcause_q (core_i.cs_registers_i.mcause_q), + .mtvec (core_i.cs_registers_i.mtvec_q), + .mepc_q (core_i.cs_registers_i.mepc_q), + .tdata1 (core_i.cs_registers_i.tdata1_rdata), + .tdata2 (core_i.cs_registers_i.tdata2_rdata), + .mcountinhibit_q (core_i.cs_registers_i.mcountinhibit_q), + .mcycle (core_i.cs_registers_i.mhpmcounter_q[0]), + .minstret (core_i.cs_registers_i.mhpmcounter_q[2]), + .csr_we_int (core_i.cs_registers_i.csr_we_int), + + // TODO: review this change from CV32E40S_HASH f6196bf to a26b194. It should be logically equivalent. + //assign debug_cov_assert_if.inst_ret = core_i.cs_registers_i.inst_ret; // First attempt: this causes unexpected failures of a_minstret_count //assign debug_cov_assert_if.inst_ret = (core_i.id_valid & // core_i.is_decoding); @@ -1372,6 +1407,7 @@ module uvmt_cv32e40s_tb; .* ); + `endif logic [31:0] tdata1_array[uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DBG_NUM_TRIGGERS+1]; @@ -1391,64 +1427,63 @@ module uvmt_cv32e40s_tb; end - bind cv32e40s_wrapper - uvmt_cv32e40s_support_logic_module_i_if_t support_logic_module_i_if ( - .clk (core_i.clk), - .rst_n (rst_ni), + bind cv32e40s_wrapper + uvmt_cv32e40s_support_logic_module_i_if_t support_logic_module_i_if ( + .clk (core_i.clk), + .rst_n (rst_ni), - .if_instr (core_i.if_stage_i.prefetch_instr.bus_resp.rdata), - .id_instr (core_i.if_id_pipe.instr.bus_resp.rdata), - .ex_instr (core_i.id_ex_pipe.instr.bus_resp.rdata), - .wb_instr (core_i.ex_wb_pipe.instr.bus_resp.rdata), + .if_instr (core_i.if_stage_i.prefetch_instr.bus_resp.rdata), + .id_instr (core_i.if_id_pipe.instr.bus_resp.rdata), + .ex_instr (core_i.id_ex_pipe.instr.bus_resp.rdata), + .wb_instr (core_i.ex_wb_pipe.instr.bus_resp.rdata), - .tdata1_array (uvmt_cv32e40s_tb.tdata1_array), - .tdata2_array (uvmt_cv32e40s_tb.tdata2_array), - - .ctrl_fsm_o (core_i.controller_i.controller_fsm_i.ctrl_fsm_o), - - .fetch_enable (core_i.fetch_enable), - .debug_req_i (core_i.debug_req_i), - .irq_ack (core_i.irq_ack), - - .wb_valid (core_i.wb_stage_i.wb_valid_o), - .wb_tselect (core_i.cs_registers_i.tselect_rdata), - .wb_tdata1 (core_i.cs_registers_i.tdata1_rdata), - .wb_tdata2 (core_i.cs_registers_i.tdata2_rdata), - - .data_bus_rvalid (core_i.m_c_obi_data_if.s_rvalid.rvalid), - .data_bus_req (core_i.m_c_obi_data_if.s_req.req), - .data_bus_gnt (core_i.m_c_obi_data_if.s_gnt.gnt), - .data_bus_gntpar (core_i.m_c_obi_data_if.s_gnt.gntpar), - - .instr_bus_rvalid (core_i.m_c_obi_instr_if.s_rvalid.rvalid), - .instr_bus_req (core_i.m_c_obi_instr_if.s_req.req), - .instr_bus_gnt (core_i.m_c_obi_instr_if.s_gnt.gnt), - .instr_bus_gntpar (core_i.m_c_obi_instr_if.s_gnt.gntpar), - - //obi protocol between alignmentbuffer (ab) and instructoin (i) interface (i) mpu (m) is refered to as abiim - .abiim_bus_rvalid (core_i.if_stage_i.prefetch_resp_valid), - .abiim_bus_req (core_i.if_stage_i.prefetch_trans_ready), - .abiim_bus_gnt (core_i.if_stage_i.prefetch_trans_valid), - - //obi protocol between LSU (l) mpu (m) and LSU (l) is refered to as lml - .lml_bus_rvalid (core_i.load_store_unit_i.resp_valid), - .lml_bus_req (core_i.load_store_unit_i.trans_ready), - .lml_bus_gnt (core_i.load_store_unit_i.trans_valid), - - //obi protocol between LSU (l) respons (r) filter (f) and OBI (o) data (d) interface (i) is refered to as lrfodi - .lrfodi_bus_rvalid (core_i.load_store_unit_i.bus_resp_valid), - .lrfodi_bus_req (core_i.load_store_unit_i.buffer_trans_valid), - .lrfodi_bus_gnt (core_i.load_store_unit_i.buffer_trans_ready), - - .req_is_store (core_i.m_c_obi_data_if.req_payload.we), - .req_instr_integrity (core_i.m_c_obi_instr_if.req_payload.integrity), - .req_data_integrity (core_i.m_c_obi_data_if.req_payload.integrity), - .instr_req_pc ({core_i.m_c_obi_instr_if.req_payload.addr[31:2], 2'b0}) - ); + .tdata1_array (uvmt_cv32e40s_tb.tdata1_array), + .tdata2_array (uvmt_cv32e40s_tb.tdata2_array), + + .ctrl_fsm_o (core_i.controller_i.controller_fsm_i.ctrl_fsm_o), + + .fetch_enable (core_i.fetch_enable), + .debug_req_i (core_i.debug_req_i), + .irq_ack (core_i.irq_ack), + + .wb_valid (core_i.wb_stage_i.wb_valid_o), + .wb_tselect (core_i.cs_registers_i.tselect_rdata), + .wb_tdata1 (core_i.cs_registers_i.tdata1_rdata), + .wb_tdata2 (core_i.cs_registers_i.tdata2_rdata), + + .data_bus_rvalid (core_i.m_c_obi_data_if.s_rvalid.rvalid), + .data_bus_req (core_i.m_c_obi_data_if.s_req.req), + .data_bus_gnt (core_i.m_c_obi_data_if.s_gnt.gnt), + .data_bus_gntpar (core_i.m_c_obi_data_if.s_gnt.gntpar), + + .instr_bus_rvalid (core_i.m_c_obi_instr_if.s_rvalid.rvalid), + .instr_bus_req (core_i.m_c_obi_instr_if.s_req.req), + .instr_bus_gnt (core_i.m_c_obi_instr_if.s_gnt.gnt), + .instr_bus_gntpar (core_i.m_c_obi_instr_if.s_gnt.gntpar), + + //obi protocol between alignmentbuffer (ab) and instructoin (i) interface (i) mpu (m) is refered to as abiim + .abiim_bus_rvalid (core_i.if_stage_i.prefetch_resp_valid), + .abiim_bus_req (core_i.if_stage_i.prefetch_trans_ready), + .abiim_bus_gnt (core_i.if_stage_i.prefetch_trans_valid), + + //obi protocol between LSU (l) mpu (m) and LSU (l) is refered to as lml + .lml_bus_rvalid (core_i.load_store_unit_i.resp_valid), + .lml_bus_req (core_i.load_store_unit_i.trans_ready), + .lml_bus_gnt (core_i.load_store_unit_i.trans_valid), + + //obi protocol between LSU (l) respons (r) filter (f) and OBI (o) data (d) interface (i) is refered to as lrfodi + .lrfodi_bus_rvalid (core_i.load_store_unit_i.bus_resp_valid), + .lrfodi_bus_req (core_i.load_store_unit_i.buffer_trans_valid), + .lrfodi_bus_gnt (core_i.load_store_unit_i.buffer_trans_ready), + + .req_instr_integrity (core_i.m_c_obi_instr_if.req_payload.integrity), + .req_data_integrity (core_i.m_c_obi_data_if.req_payload.integrity) + ); - bind cv32e40s_wrapper - uvmt_cv32e40s_support_logic_module_o_if_t support_logic_module_o_if(); + bind cv32e40s_wrapper + uvmt_cv32e40s_support_logic_module_o_if_t support_logic_module_o_if(); + `ifndef COREV_ASSERT_OFF bind cv32e40s_pmp : uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i.pmp.pmp_i uvmt_cv32e40s_pmp_assert #( @@ -1465,7 +1500,9 @@ module uvmt_cv32e40s_tb; .rvfi_pc_rdata (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.rvfi_pc_rdata), .rvfi_valid (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.rvfi_valid), .*); + `endif + `ifndef COREV_ASSERT_OFF bind cv32e40s_pmp : uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i.pmp.pmp_i uvmt_cv32e40s_pmp_assert#( @@ -1482,7 +1519,9 @@ module uvmt_cv32e40s_tb; .rvfi_pc_rdata (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.rvfi_pc_rdata), .rvfi_valid (uvmt_cv32e40s_tb.dut_wrap.cv32e40s_wrapper_i.rvfi_i.rvfi_valid), .*); + `endif + `ifndef COREV_ASSERT_OFF bind dut_wrap.cv32e40s_wrapper_i.rvfi_i uvmt_cv32e40s_pmprvfi_assert #( .PMP_GRANULARITY (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_PMP_GRANULARITY), @@ -1494,15 +1533,17 @@ module uvmt_cv32e40s_tb; .rvfi_mem_rmask (rvfi_mem_rmask[ 3:0]), .* ); + `endif - // PMA Asserts & Covers + // PMA Asserts & Covers - wire pma_status_t pma_status_instr; - wire pma_status_t pma_status_data; - wire pma_status_t pma_status_rvfidata_word0lowbyte; - wire pma_status_t pma_status_rvfidata_word0highbyte; + wire pma_status_t pma_status_instr; + wire pma_status_t pma_status_data; + wire pma_status_t pma_status_rvfidata_word0lowbyte; + wire pma_status_t pma_status_rvfidata_word0highbyte; + `ifndef COREV_ASSERT_OFF bind dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i uvmt_cv32e40s_pma_model #( .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), @@ -1517,7 +1558,9 @@ module uvmt_cv32e40s_tb; .pma_status_o (uvmt_cv32e40s_tb.pma_status_instr), .* ); + `endif + `ifndef COREV_ASSERT_OFF bind dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i uvmt_cv32e40s_pma_model #( .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), @@ -1532,7 +1575,9 @@ module uvmt_cv32e40s_tb; .pma_status_o (uvmt_cv32e40s_tb.pma_status_data), .* ); + `endif + `ifndef COREV_ASSERT_OFF bind dut_wrap.cv32e40s_wrapper_i uvmt_cv32e40s_pma_model #( .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), @@ -1551,7 +1596,9 @@ module uvmt_cv32e40s_tb; .misaligned_access_i (rvfi_instr_if.is_split_datatrans_intended), .pma_status_o (uvmt_cv32e40s_tb.pma_status_rvfidata_word0lowbyte) ); + `endif + `ifndef COREV_ASSERT_OFF bind dut_wrap.cv32e40s_wrapper_i uvmt_cv32e40s_pma_model #( .DM_REGION_END (uvmt_cv32e40s_base_test_pkg::CORE_PARAM_DM_REGION_END), @@ -1571,7 +1618,9 @@ module uvmt_cv32e40s_tb; .misaligned_access_i (rvfi_instr_if.is_split_datatrans_intended), .pma_status_o (uvmt_cv32e40s_tb.pma_status_rvfidata_word0highbyte) ); + `endif + `ifndef COREV_ASSERT_OFF bind dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i uvmt_cv32e40s_pma_assert #( .CORE_REQ_TYPE (cv32e40s_pkg::obi_inst_req_t), @@ -1589,7 +1638,9 @@ module uvmt_cv32e40s_tb; .pma_status_i (uvmt_cv32e40s_tb.pma_status_instr), .* ); + `endif + `ifndef COREV_ASSERT_OFF bind dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i uvmt_cv32e40s_pma_assert #( .CORE_REQ_TYPE (cv32e40s_pkg::obi_data_req_t), @@ -1607,7 +1658,9 @@ module uvmt_cv32e40s_tb; .pma_status_i (uvmt_cv32e40s_tb.pma_status_data), .* ); + `endif + `ifndef COREV_ASSERT_OFF bind dut_wrap.cv32e40s_wrapper_i.core_i.if_stage_i.mpu_i uvmt_cv32e40s_pma_cov #( .CORE_REQ_TYPE (cv32e40s_pkg::obi_inst_req_t), @@ -1621,7 +1674,9 @@ module uvmt_cv32e40s_tb; .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), .* ); + `endif + `ifndef COREV_ASSERT_OFF bind dut_wrap.cv32e40s_wrapper_i.core_i.load_store_unit_i.mpu_i uvmt_cv32e40s_pma_cov #( .CORE_REQ_TYPE (cv32e40s_pkg::obi_data_req_t), @@ -1635,16 +1690,20 @@ module uvmt_cv32e40s_tb; .rvfi_if (dut_wrap.cv32e40s_wrapper_i.rvfi_instr_if), .* ); + `endif - // Support Logic + // Support Logic - bind cv32e40s_wrapper uvmt_cv32e40s_support_logic u_support_logic(.rvfi (rvfi_instr_if), - .in_support_if (support_logic_module_i_if.driver_mp), - .out_support_if (support_logic_module_o_if.master_mp) - ); + bind cv32e40s_wrapper uvmt_cv32e40s_support_logic u_support_logic(.rvfi (rvfi_instr_if), + .in_support_if (support_logic_module_i_if.driver_mp), + .out_support_if (support_logic_module_o_if.master_mp), + .data_obi_if (dut_wrap.obi_data_if), + .instr_obi_if (dut_wrap.obi_instr_if) + ); + `ifndef COREV_ASSERT_OFF bind cv32e40s_wrapper uvmt_cv32e40s_debug_assert u_debug_assert(.rvfi(rvfi_instr_if), .csr_dcsr(rvfi_csr_dcsr_if), .csr_dpc(rvfi_csr_dpc_if), @@ -1661,7 +1720,9 @@ module uvmt_cv32e40s_tb; .cov_assert_if(debug_cov_assert_if), .support_if (support_logic_module_o_if.slave_mp) ); + `endif + `ifndef COREV_ASSERT_OFF bind cv32e40s_wrapper uvmt_cv32e40s_triggers_assert_cov debug_trigger_assert_i( .tdata1_array (uvmt_cv32e40s_tb.tdata1_array), .priv_lvl (core_i.priv_lvl), @@ -1675,12 +1736,20 @@ module uvmt_cv32e40s_tb; .dcsr_if (rvfi_csr_dcsr_if), .dpc_if (rvfi_csr_dpc_if) ); + `endif + `ifndef COREV_ASSERT_OFF bind cv32e40s_wrapper uvmt_cv32e40s_zc_assert u_zc_assert(.rvfi(rvfi_instr_if), .support_if(support_logic_module_o_if.slave_mp) ); + `endif + `ifndef COREV_ASSERT_OFF + `ifdef PARAM_SET_0 + `include "cvverif_sva_binds.svh" + `endif + `endif //uvmt_cv32e40s_rvvi_handcar u_rvvi_handcar(); diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_files.flist b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_files.flist index daac323490..d913d0e03c 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_files.flist +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_files.flist @@ -21,7 +21,7 @@ ${DV_UVMT_PATH}/uvmt_cv32e40s_tb.sv ${DV_UVMT_PATH}/uvmt_cv32e40s_clic_interrupt_assert.sv ${DV_UVMT_PATH}/uvmt_cv32e40s_debug_assert.sv ${DV_UVMT_PATH}/uvmt_cv32e40s_triggers_assert_cov.sv -${DV_UVMT_PATH}/uvmt_cv32e40s_fencei_assert.sv +${DV_UVMT_PATH}/../assertions/uvmt_cv32e40s_fencei_assert.sv ${DV_UVMT_PATH}/uvmt_cv32e40s_integration_assert.sv ${DV_UVMT_PATH}/uvmt_cv32e40s_interrupt_assert.sv ${DV_UVMT_PATH}/uvmt_cv32e40s_pma_assert.sv @@ -46,7 +46,7 @@ ${DV_UVMT_PATH}/uvmt_cv32e40s_zc_assert.sv ${DV_UVMT_PATH}/../assertions/uvmt_cv32e40s_pma_model.sv ${DV_UVMT_PATH}/../assertions/uvmt_cv32e40s_pmp_model.sv ${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_sl_obi_phases_monitor.sv -${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_sl_req_attribute_fifo.sv +${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_sl_fifo.sv ${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_sl_trigger_match_mem.sv ${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_sl_trigger_match.sv ${DV_UVMT_PATH}/support_logic/uvmt_cv32e40s_support_logic.sv diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_ifs.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_ifs.sv index 65e6bd0f5b..54aaeacee1 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_ifs.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_tb_ifs.sv @@ -320,10 +320,8 @@ interface uvmt_cv32e40s_support_logic_module_i_if_t input logic lrfodi_bus_req, //Obi request information - input logic req_is_store, input logic req_instr_integrity, - input logic req_data_integrity, - input logic [31:0] instr_req_pc + input logic req_data_integrity ); @@ -371,10 +369,8 @@ interface uvmt_cv32e40s_support_logic_module_i_if_t lrfodi_bus_gnt, lrfodi_bus_req, - req_is_store, req_instr_integrity, - req_data_integrity, - instr_req_pc + req_data_integrity ); endinterface : uvmt_cv32e40s_support_logic_module_i_if_t @@ -393,6 +389,10 @@ interface uvmt_cv32e40s_support_logic_module_o_if_t; asm_t asm_wb; asm_t asm_rvfi; + //OBI packets: + obi_data_packet_t obi_data_packet; + obi_instr_packet_t obi_instr_packet; + // Indicates that a new obi data req arrives after an exception is triggered. // Used to verify exception timing with multiop instruction logic req_after_exception; @@ -433,12 +433,10 @@ interface uvmt_cv32e40s_support_logic_module_o_if_t; logic [31:0] cnt_rvfi_irqs; //Signals stating whether the request for the current response had the attribute value or not - logic req_was_store; - logic instr_req_had_integrity; - logic data_req_had_integrity; - logic gntpar_error_in_response_instr; - logic gntpar_error_in_response_data; - logic [31:0] instr_resp_pc; + logic instr_req_had_integrity; + logic data_req_had_integrity; + logic gntpar_error_in_response_instr; + logic gntpar_error_in_response_data; // indicates that the current rvfi_valid instruction is the first in a debug handler logic first_debug_ins; @@ -486,12 +484,12 @@ interface uvmt_cv32e40s_support_logic_module_o_if_t; cnt_irq_ack, cnt_rvfi_irqs, - req_was_store, + obi_data_packet, + obi_instr_packet, instr_req_had_integrity, data_req_had_integrity, gntpar_error_in_response_instr, gntpar_error_in_response_data, - instr_resp_pc, first_debug_ins, first_fetch, recorded_dbg_req @@ -532,12 +530,12 @@ interface uvmt_cv32e40s_support_logic_module_o_if_t; cnt_irq_ack, cnt_rvfi_irqs, - req_was_store, + obi_data_packet, + obi_instr_packet, instr_req_had_integrity, data_req_had_integrity, gntpar_error_in_response_instr, gntpar_error_in_response_data, - instr_resp_pc, first_debug_ins, first_fetch, recorded_dbg_req diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_triggers_assert_cov.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_triggers_assert_cov.sv index f74a9712d3..dc4774fa84 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_triggers_assert_cov.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_triggers_assert_cov.sv @@ -137,8 +137,6 @@ module uvmt_cv32e40s_triggers_assert_cov localparam MAX_MEM_ACCESS = 13; //Push and pop can do 13 memory access. TODO: XIF, can potentially do more, so for XIF assertion a_dt_max_memory_transaction might fail. localparam MAX_MEM_ACCESS_PLUS_ONE = 53'b1_0000__0000_0000_0000_0000__0000_0000_0000_0000__0000_0000_0000_0000; - - /////////// Signals /////////// logic [31:0] tdata1_pre_state; @@ -201,7 +199,6 @@ module uvmt_cv32e40s_triggers_assert_cov csri_uimm = rvfi_if.rvfi_insn[19:15]; end - /////////// Sequences /////////// sequence seq_csr_read_mmode(csr_addr); @@ -359,44 +356,15 @@ module uvmt_cv32e40s_triggers_assert_cov //- Vplan: //Check that attempts to access "tdata3" raise an illegal instruction exception, always. (Unless overruled by a higher priority.) - //Verify that tdata3 is illegal for all tdata2 types. //- Assertion verification: //1) Check that attempts to access "tdata3" raise an illegal instruction exception, always. (Unless overruled by a higher priorit - //2) Verify that tdata3 is illegal for all tdata2 types. //1) a_dt_tdata3_not_implemented: assert property ( p_dt_tcsr_not_implemented(ADDR_TDATA3) ) else `uvm_error(info_tag, "Access to tdata3 does not cause an illegal exception (when no higher priority exception has occured)\n"); - - // Assertions and coverages for when there are debug triggers: - if (CORE_PARAM_DBG_NUM_TRIGGERS != 0) begin - - //2) - c_dt_access_tdata3_m2: cover property ( - rvfi_if.is_csr_instr(ADDR_TDATA3) - && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL - ); - - c_dt_access_tdata3_etrigger: cover property ( - rvfi_if.is_csr_instr(ADDR_TDATA3) - && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_ETRIGGER - ); - - c_dt_access_tdata3_m6: cover property ( - rvfi_if.is_csr_instr(ADDR_TDATA3) - && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_MCONTROL6 - ); - - c_dt_access_tdata3_disabled: cover property ( - rvfi_if.is_csr_instr(ADDR_TDATA3) - && tdata1_pre_state[MSB_TYPE:LSB_TYPE] == TTYPE_DISABLED - ); - end - - //- Vplan: //Have 0 triggers, access any trigger register and check that illegal instruction exception occurs. //Check that no triggers ever fire. Check that "tselect" is 0. @@ -647,7 +615,7 @@ module uvmt_cv32e40s_triggers_assert_cov //2) Try changing "tdata1.dmode" and check that it is WARL (0x1) - //1) //a_dt_access_csr_not_dbg_mode --> changed to the two following assertions: a_dt_not_access_tdata1_dbg_mode, a_dt_not_access_tdata2_dbg_mode + //1) a_dt_not_access_tdata1_dbg_mode: assert property ( !rvfi_if.rvfi_dbg_mode && rvfi_if.is_csr_instr(ADDR_TDATA1) @@ -1000,12 +968,13 @@ module uvmt_cv32e40s_triggers_assert_cov //2) Verify that we do not enter debug when triggering unenabled exceptions //1) - a_dt_exception_trigger_hit_m_instr_access_fault: assert property( + //TODO: krdosvik, fails, need rtl fix. + /*a_dt_exception_trigger_hit_m_instr_access_fault: assert property( p_etrigger_hit( t, rvfi_if.is_mmode, EXC_CAUSE_INSTR_FAULT) - ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, instruction fault) does not send the core into debug mode.\n"); + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, instruction fault) does not send the core into debug mode.\n");*/ a_dt_exception_trigger_hit_u_instr_access_fault: assert property( p_etrigger_hit( @@ -1084,12 +1053,13 @@ module uvmt_cv32e40s_triggers_assert_cov EXC_CAUSE_ECALL_UMODE) ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, ecall in user mode) does not send the core into debug mode.\n"); - a_dt_exception_trigger_hit_m_instr_bus_fault: assert property( + //TODO: krdosvik, fails, need rtl fix. + /*a_dt_exception_trigger_hit_m_instr_bus_fault: assert property( p_etrigger_hit( t, rvfi_if.is_mmode, EXC_CAUSE_INSTR_BUS_FAULT) - ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, instruction bus fault) does not send the core into debug mode.\n"); + ) else `uvm_error(info_tag, "The trigger match (exception match, machine mode, instruction bus fault) does not send the core into debug mode.\n");*/ a_dt_exception_trigger_hit_u_instr_bus_fault: assert property( p_etrigger_hit( @@ -1098,7 +1068,8 @@ module uvmt_cv32e40s_triggers_assert_cov EXC_CAUSE_INSTR_BUS_FAULT) ) else `uvm_error(info_tag, "The trigger match (exception match, user mode, instruction bus fault) does not send the core into debug mode.\n"); - if (INTEGRITY_ERRORS_ENABLED) begin + //TODO: krdosvik, fails, need rtl fix. + /*if (INTEGRITY_ERRORS_ENABLED) begin a_glitch_dt_exception_trigger_hit_m_instr_integrity_fault: assert property( p_etrigger_hit( @@ -1130,7 +1101,7 @@ module uvmt_cv32e40s_triggers_assert_cov EXC_CAUSE_INSTR_INTEGRITY_FAULT) ) else `uvm_error(info_tag, "exception trigger hit precondition is met for user mode even though we assueme no integrity faults.\n"); - end + end*/ //2) see a_dt_enter_dbg_reason @@ -1325,7 +1296,8 @@ module uvmt_cv32e40s_triggers_assert_cov //2) - a_dt_enter_dbg_reason: assert property ( + //TODO: krdosvik, fails, need rtl fix. + /*a_dt_enter_dbg_reason: assert property ( rvfi_if.rvfi_valid && rvfi_if.rvfi_trap.debug && rvfi_if.rvfi_trap.debug_cause == TRIGGER_MATCH @@ -1333,8 +1305,7 @@ module uvmt_cv32e40s_triggers_assert_cov |-> support_if.is_trigger_match - ) else `uvm_error(info_tag, "We have entered debug mode due to triggers but not due to any of the listed reasons.\n"); - + ) else `uvm_error(info_tag, "We have entered debug mode due to triggers but not due to any of the listed reasons.\n");*/ //- Vplan: //Change the type to 2/6/15 and write any data to "tdata2", read it back and check that it always gets set. diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_assert.sv index d3bb6b73ea..fa86e34698 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_assert.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_umode_assert.sv @@ -202,7 +202,7 @@ module uvmt_cv32e40s_umode_assert assign clk_rvfi = clk_i & was_rvfi_valid; reg [1:0] effective_rvfi_privmode; - always @(*) begin + always_comb begin if (rvfi_csr_mstatus_rdata[MPRV_POS+:MPRV_LEN]) begin effective_rvfi_privmode = rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN]; end else begin @@ -213,7 +213,7 @@ module uvmt_cv32e40s_umode_assert reg [1:0] was_rvfi_mode; reg [1:0] was_rvfi_mode_wdata; // Expected next mode (ignoring dmode) reg was_rvfi_dbg_mode; - always @(posedge clk_i) begin + always_ff @(posedge clk_i) begin if (rvfi_valid) begin was_rvfi_mode <= rvfi_mode; was_rvfi_dbg_mode <= rvfi_dbg_mode; @@ -236,11 +236,12 @@ module uvmt_cv32e40s_umode_assert end end - wire logic [MPP_LEN-1:0] mpp_rdata; - wire logic [MPP_LEN-1:0] mpp_rdata_past; - assign mpp_rdata = rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN]; - assign mpp_rdata_past = $past(mpp_rdata, , ,@(posedge clk_rvfi)); - + logic [MPP_LEN-1:0] mpp_rdata; + logic [MPP_LEN-1:0] mpp_rdata_past; + always_comb begin + mpp_rdata = rvfi_csr_mstatus_rdata[MPP_POS+:MPP_LEN]; + mpp_rdata_past = $past(mpp_rdata, , ,@(posedge clk_rvfi)); + end // vplan:MisaU & vplan:MisaN @@ -867,12 +868,16 @@ module uvmt_cv32e40s_umode_assert // vplan:PrvEntry - - property p_prv_entry; + sequence seq_dbg_entry; (rvfi_valid && !rvfi_dbg_mode) ##1 - (rvfi_valid [->1]) ##0 - rvfi_dbg_mode + rvfi_valid[->1] + ##0 + rvfi_dbg_mode; + endsequence : seq_dbg_entry + + property p_prv_entry; + seq_dbg_entry |-> if (!rvfi_intr[0]) ( (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == was_rvfi_mode_wdata) @@ -887,15 +892,11 @@ module uvmt_cv32e40s_umode_assert ) else `uvm_error(info_tag, "on dbg entry, dcsr.prv should be previous privmode"); cov_prv_entry_u: cover property ( - reject_on - (rvfi_valid && rvfi_dbg_mode && (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] != MODE_U)) - p_prv_entry + seq_dbg_entry ##0 rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == MODE_U ); cov_prv_entry_m: cover property ( - reject_on - (rvfi_valid && rvfi_dbg_mode && (rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] != MODE_M)) - p_prv_entry + seq_dbg_entry ##0 rvfi_csr_dcsr_rdata[PRV_POS+:PRV_LEN] == MODE_M ); @@ -972,11 +973,13 @@ module uvmt_cv32e40s_umode_assert obi_dside_prot inside {3'b 001, 3'b 111} ) else `uvm_error(info_tag, "the prot on loadstore must be legal"); - wire logic [NMEM-1:0] data_prot_equals; - wire logic [NMEM-1:0] mem_act; + logic [NMEM-1:0] data_prot_equals; + logic [NMEM-1:0] mem_act; for (genvar i = 0; i < NMEM; i++) begin: gen_data_prot_equals - assign data_prot_equals[i] = (rvfi_if.mem_prot[i*3+:3] == rvfi_if.mem_prot[2:0]); - assign mem_act[i] = |rvfi_if.check_mem_act(i); + always_comb begin + data_prot_equals[i] = (rvfi_if.mem_prot[i*3+:3] == rvfi_if.mem_prot[2:0]); + mem_act[i] = |rvfi_if.check_mem_act(i); + end end a_data_prot_equal: assert property ( diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert.sv index ab6b0a9c03..d6c94f3db9 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert.sv @@ -127,12 +127,11 @@ module uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert //Verify that major alert is set when there is a response packet even though there are no outstanding requests, in the following OBI protocols - property p_resp_no_outstanding_req(obi_rvalid, resp_ph_cont, v_addr_ph_cnt); + property p_resp_no_outstanding_req(obi_rvalid, v_addr_ph_cnt); //If there has already been a bus protpcol fault the there will be an underflow error and the system acts strangely !bus_protocol_hardening_glitch_sticky && obi_rvalid - && !resp_ph_cont && v_addr_ph_cnt == 0 |=> alert_major; @@ -141,28 +140,24 @@ module uvmt_cv32e40s_xsecure_bus_protocol_hardening_assert a_glitch_xsecure_bus_hardening_no_outstanding_obi_instr_trans: assert property ( p_resp_no_outstanding_req( obi_instr_rvalid, - support_if.instr_bus_resp_ph_cont, support_if.instr_bus_v_addr_ph_cnt) ) else `uvm_error(info_tag_glitch, "A response before a request in the OBI instruction bus handshake, but the alert major is not set.\n"); a_glitch_xsecure_bus_hardening_no_outstanding_obi_data_trans: assert property ( p_resp_no_outstanding_req( obi_data_rvalid, - support_if.data_bus_resp_ph_cont, support_if.data_bus_v_addr_ph_cnt) ) else `uvm_error(info_tag_glitch, "A response before a request in the OBI data bus handshake, but the alert major is not set.\n"); a_glitch_xsecure_bus_hardening_alignment_buff_receive_instr_if_mpu_resp: assert property ( p_resp_no_outstanding_req( instr_if_mpu_resp, - support_if.alignment_buff_resp_ph_cont, support_if.alignment_buff_addr_ph_cnt) ) else `uvm_error(info_tag_glitch, "The alignment buffer does not have outstanding requests but receives a response from the instruction interface MPU, but the alert major is not set.\n"); a_glitch_xsecure_bus_hardening_lsu_receive_lsu_mpu_resp: assert property ( p_resp_no_outstanding_req( lsu_mpu_resp, - support_if.lsu_resp_ph_cont, support_if.lsu_addr_ph_cnt) ) else `uvm_error(info_tag_glitch, "The load-store unit does not have outstanding requests but receives a response from the load-store unit MPU, but the alert major is not set.\n"); diff --git a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv index 56a80d9ad6..68480736fa 100644 --- a/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv +++ b/cv32e40s/tb/uvmt/uvmt_cv32e40s_xsecure_assert/uvmt_cv32e40s_xsecure_interface_integrity_assert.sv @@ -298,7 +298,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert a_xsecure_integrity_store_data_rchk: assert property ( p_checksum_data_rchk( - support_if.req_was_store, + support_if.obi_data_packet.req.we, obi_data_rvalid, obi_data_resp_packet.rchk[RCHK_STORE], rchk_data_calculated[RCHK_STORE]) @@ -307,7 +307,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert a_xsecure_integrity_load_data_rchk: assert property ( p_checksum_data_rchk( - !support_if.req_was_store, + !support_if.obi_data_packet.req.we, obi_data_rvalid, obi_data_resp_packet.rchk, rchk_data_calculated) @@ -394,7 +394,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert ##0 seq_checksum_fault( obi_data_rvalid, support_if.data_req_had_integrity, - support_if.req_was_store, + support_if.obi_data_packet.req.we, obi_data_resp_packet.rchk[RCHK_STORE], rchk_data_calculated[RCHK_STORE]) @@ -408,7 +408,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert ##0 seq_checksum_fault( obi_data_rvalid, support_if.data_req_had_integrity, - !support_if.req_was_store, + !support_if.obi_data_packet.req.we, obi_data_resp_packet.rchk, rchk_data_calculated) @@ -442,7 +442,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert ##0 seq_checksum_fault( obi_data_rvalid, support_if.data_req_had_integrity, - support_if.req_was_store, + support_if.obi_data_packet.req.we, obi_data_resp_packet.rchk[RCHK_STORE], rchk_data_calculated[RCHK_STORE]) @@ -457,7 +457,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert ##0 seq_checksum_fault( obi_data_rvalid, support_if.data_req_had_integrity, - !support_if.req_was_store, + !support_if.obi_data_packet.req.we, obi_data_resp_packet.rchk, rchk_data_calculated) @@ -554,7 +554,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert a_glitch_xsecure_integrity_data_rchk_fault_integrity_err_store: assert property ( p_rchk_fault_integrity_err( support_if.data_req_had_integrity, - support_if.req_was_store, + support_if.obi_data_packet.req.we, obi_data_rvalid, obi_data_resp_packet.rchk[RCHK_STORE], rchk_data_calculated[RCHK_STORE], @@ -564,7 +564,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert a_glitch_xsecure_integrity_data_rchk_fault_integrity_err_load: assert property ( p_rchk_fault_integrity_err( support_if.data_req_had_integrity, - !support_if.req_was_store, + !support_if.obi_data_packet.req.we, obi_data_rvalid, obi_data_resp_packet.rchk, rchk_data_calculated, @@ -706,7 +706,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert ) else `uvm_error(info_tag_glitch, "The NMI caused by an associated parity/checksum error does not have exception code 1027 or 1026.\n"); //Load instructions - c_glitch_xsecure_security_parity_checksum_fault_NMI_load_instruction: cover property ( + c_glitch_xsecure_integrity_parity_checksum_fault_NMI_load_instruction: cover property ( obi_data_rvalid && data_integrity_err @@ -715,7 +715,7 @@ module uvmt_cv32e40s_xsecure_interface_integrity_assert ); //Store instructions - c_glitch_xsecure_security_parity_checksum_fault_NMI_store_instruction: cover property ( + c_glitch_xsecure_integrity_parity_checksum_fault_NMI_store_instruction: cover property ( obi_data_rvalid && data_integrity_err diff --git a/cv32e40s/tests/cfg/clic_default.yaml b/cv32e40s/tests/cfg/clic_default.yaml index 403bad9a57..a1906d591e 100644 --- a/cv32e40s/tests/cfg/clic_default.yaml +++ b/cv32e40s/tests/cfg/clic_default.yaml @@ -5,6 +5,7 @@ compile_flags: +define+CLIC_EN +define+PMP_ENABLE_64 ovpsim: > + --override cpu/hpmcounter_undefined=T --override cpu/CLICLEVELS=256 --override cpu/CLICXCSW=T --override cpu/CLICXNXTI=T diff --git a/cv32e40s/tests/cfg/param_set_0.yaml b/cv32e40s/tests/cfg/param_set_0.yaml new file mode 100644 index 0000000000..6f07fc3c68 --- /dev/null +++ b/cv32e40s/tests/cfg/param_set_0.yaml @@ -0,0 +1,8 @@ +name: param_set_0 +description: > + Compile with external parameter configuration. + USER_COMPILE_FLAGS="+incdir+path_to_your_param_set_0_directory" + Tests will fail, but you get the coverage model and data. +compile_flags: > + +define+PARAM_SET_0 +cv_sw_march: rv32im_zba1p00_zbb1p00_zbc1p00_zbs1p00_zicsr_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/cfg/param_set_1.yaml b/cv32e40s/tests/cfg/param_set_1.yaml new file mode 100644 index 0000000000..c1caa6140b --- /dev/null +++ b/cv32e40s/tests/cfg/param_set_1.yaml @@ -0,0 +1,9 @@ +name: param_set_1 +description: > + Compile with external parameter configuration. + USER_COMPILE_FLAGS="+incdir+path_to_your_param_set_1_directory" + Tests will fail, but you get the coverage model and data. +compile_flags: > + +define+PARAM_SET_1 +cflags: > +cv_sw_march: rv32emc diff --git a/cv32e40s/tests/cfg/xsecure_disable_std.yaml b/cv32e40s/tests/cfg/xsecure_disable_std.yaml new file mode 100644 index 0000000000..a96cdb4db4 --- /dev/null +++ b/cv32e40s/tests/cfg/xsecure_disable_std.yaml @@ -0,0 +1,202 @@ +name: xsecure_disable_std +description: Default configuration for CV32E40S random simulations that includes dummy instructions but disables pc hardening and data independent timing features +compile_flags: + +define+ZBA_ZBB_ZBC_ZBS + +define+CLIC_EN + +define+PMP_ENABLE_64 + +define+LFSR_CFG_0 +plusargs: > + +enable_clic=1 + +enable_zba_extension=1 + +enable_zbb_extension=1 + +enable_zbc_extension=1 + +enable_zbs_extension=1 + +fix_sp=1 + +fix_ra=1 + +enable_zca_extension=1 + +enable_zcb_extension=1 + +enable_zcmt_extension=1 + +enable_zcmp_extension=1 + +enable_dummy=1 + +enable_hint=1 + +disable_data_independent_timing=1 + +disable_pc_hardening=1 +ovpsim: > + --override cpu/CLICLEVELS=256 + --override cpu/CLICXCSW=T + --override cpu/CLICXNXTI=T + --override cpu/CLICSELHVEC=T + --override cpu/CLICINTCTLBITS=8 + --override cpu/CLIC_version=master + --override cpu/externalCLIC=T + --override cpu/mtvt_mask=0xffffffffffffff80 + --override cpu/PMP_registers=64 + --override cpu/PMP_registers=64 + --override cpu/PMP_undefined=T + --override cpu/PMP_initialparams=T + --override cpu/PMP_maskparams=T + --override cpu/pmpaddr0=0 + --override cpu/pmpaddr1=0 + --override cpu/pmpaddr2=0 + --override cpu/pmpaddr3=0 + --override cpu/pmpaddr4=0 + --override cpu/pmpaddr5=0 + --override cpu/pmpaddr6=0 + --override cpu/pmpaddr7=0 + --override cpu/pmpaddr8=0 + --override cpu/pmpaddr9=0 + --override cpu/pmpaddr10=0 + --override cpu/pmpaddr11=0 + --override cpu/pmpaddr12=0 + --override cpu/pmpaddr13=0 + --override cpu/pmpaddr14=0 + --override cpu/pmpaddr15=0 + --override cpu/pmpaddr16=0 + --override cpu/pmpaddr17=0 + --override cpu/pmpaddr18=0 + --override cpu/pmpaddr19=0 + --override cpu/pmpaddr20=0 + --override cpu/pmpaddr21=0 + --override cpu/pmpaddr22=0 + --override cpu/pmpaddr23=0 + --override cpu/pmpaddr24=0 + --override cpu/pmpaddr25=0 + --override cpu/pmpaddr26=0 + --override cpu/pmpaddr27=0 + --override cpu/pmpaddr28=0 + --override cpu/pmpaddr29=0 + --override cpu/pmpaddr30=0 + --override cpu/pmpaddr31=0 + --override cpu/pmpaddr32=0 + --override cpu/pmpaddr33=0 + --override cpu/pmpaddr34=0 + --override cpu/pmpaddr35=0 + --override cpu/pmpaddr36=0 + --override cpu/pmpaddr37=0 + --override cpu/pmpaddr38=0 + --override cpu/pmpaddr39=0 + --override cpu/pmpaddr40=0 + --override cpu/pmpaddr41=0 + --override cpu/pmpaddr42=0 + --override cpu/pmpaddr43=0 + --override cpu/pmpaddr44=0 + --override cpu/pmpaddr45=0 + --override cpu/pmpaddr46=0 + --override cpu/pmpaddr47=0 + --override cpu/pmpaddr48=0 + --override cpu/pmpaddr49=0 + --override cpu/pmpaddr50=0 + --override cpu/pmpaddr51=0 + --override cpu/pmpaddr52=0 + --override cpu/pmpaddr53=0 + --override cpu/pmpaddr54=0 + --override cpu/pmpaddr55=0 + --override cpu/pmpaddr56=0 + --override cpu/pmpaddr57=0 + --override cpu/pmpaddr58=0 + --override cpu/pmpaddr59=0 + --override cpu/pmpaddr60=0 + --override cpu/pmpaddr61=0 + --override cpu/pmpaddr62=0 + --override cpu/pmpaddr63=0 + --override cpu/pmpcfg0=0 + --override cpu/pmpcfg1=0 + --override cpu/pmpcfg2=0 + --override cpu/pmpcfg3=0 + --override cpu/pmpcfg4=0 + --override cpu/pmpcfg5=0 + --override cpu/pmpcfg6=0 + --override cpu/pmpcfg7=0 + --override cpu/pmpcfg8=0 + --override cpu/pmpcfg9=0 + --override cpu/pmpcfg10=0 + --override cpu/pmpcfg11=0 + --override cpu/pmpcfg12=0 + --override cpu/pmpcfg13=0 + --override cpu/pmpcfg14=0 + --override cpu/pmpcfg15=0 + --override cpu/mask_pmpaddr0=0x00000000 + --override cpu/mask_pmpaddr1=0x00000000 + --override cpu/mask_pmpaddr2=0x00000000 + --override cpu/mask_pmpaddr3=0x00000000 + --override cpu/mask_pmpaddr4=0x00000000 + --override cpu/mask_pmpaddr5=0x00000000 + --override cpu/mask_pmpaddr6=0x00000000 + --override cpu/mask_pmpaddr7=0x00000000 + --override cpu/mask_pmpaddr8=0x00000000 + --override cpu/mask_pmpaddr9=0x00000000 + --override cpu/mask_pmpaddr10=0x00000000 + --override cpu/mask_pmpaddr11=0x00000000 + --override cpu/mask_pmpaddr12=0x00000000 + --override cpu/mask_pmpaddr13=0x00000000 + --override cpu/mask_pmpaddr14=0x00000000 + --override cpu/mask_pmpaddr15=0x00000000 + --override cpu/mask_pmpaddr16=0x00000000 + --override cpu/mask_pmpaddr17=0x00000000 + --override cpu/mask_pmpaddr18=0x00000000 + --override cpu/mask_pmpaddr19=0x00000000 + --override cpu/mask_pmpaddr20=0x00000000 + --override cpu/mask_pmpaddr21=0x00000000 + --override cpu/mask_pmpaddr22=0x00000000 + --override cpu/mask_pmpaddr23=0x00000000 + --override cpu/mask_pmpaddr24=0x00000000 + --override cpu/mask_pmpaddr25=0x00000000 + --override cpu/mask_pmpaddr26=0x00000000 + --override cpu/mask_pmpaddr27=0x00000000 + --override cpu/mask_pmpaddr28=0x00000000 + --override cpu/mask_pmpaddr29=0x00000000 + --override cpu/mask_pmpaddr30=0x00000000 + --override cpu/mask_pmpaddr31=0x00000000 + --override cpu/mask_pmpaddr32=0x00000000 + --override cpu/mask_pmpaddr33=0x00000000 + --override cpu/mask_pmpaddr34=0x00000000 + --override cpu/mask_pmpaddr35=0x00000000 + --override cpu/mask_pmpaddr36=0x00000000 + --override cpu/mask_pmpaddr37=0x00000000 + --override cpu/mask_pmpaddr38=0x00000000 + --override cpu/mask_pmpaddr39=0x00000000 + --override cpu/mask_pmpaddr40=0x00000000 + --override cpu/mask_pmpaddr41=0x00000000 + --override cpu/mask_pmpaddr42=0x00000000 + --override cpu/mask_pmpaddr43=0x00000000 + --override cpu/mask_pmpaddr44=0x00000000 + --override cpu/mask_pmpaddr45=0x00000000 + --override cpu/mask_pmpaddr46=0x00000000 + --override cpu/mask_pmpaddr47=0x00000000 + --override cpu/mask_pmpaddr48=0x00000000 + --override cpu/mask_pmpaddr49=0x00000000 + --override cpu/mask_pmpaddr50=0x00000000 + --override cpu/mask_pmpaddr51=0x00000000 + --override cpu/mask_pmpaddr52=0x00000000 + --override cpu/mask_pmpaddr53=0x00000000 + --override cpu/mask_pmpaddr54=0x00000000 + --override cpu/mask_pmpaddr55=0x00000000 + --override cpu/mask_pmpaddr56=0x00000000 + --override cpu/mask_pmpaddr57=0x00000000 + --override cpu/mask_pmpaddr58=0x00000000 + --override cpu/mask_pmpaddr59=0x00000000 + --override cpu/mask_pmpaddr60=0x00000000 + --override cpu/mask_pmpaddr61=0x00000000 + --override cpu/mask_pmpaddr62=0x00000000 + --override cpu/mask_pmpaddr63=0x00000000 + --override cpu/mask_pmpcfg0=0x00000000 + --override cpu/mask_pmpcfg1=0x00000000 + --override cpu/mask_pmpcfg2=0x00000000 + --override cpu/mask_pmpcfg3=0x00000000 + --override cpu/mask_pmpcfg4=0x00000000 + --override cpu/mask_pmpcfg5=0x00000000 + --override cpu/mask_pmpcfg6=0x00000000 + --override cpu/mask_pmpcfg7=0x00000000 + --override cpu/mask_pmpcfg8=0x00000000 + --override cpu/mask_pmpcfg9=0x00000000 + --override cpu/mask_pmpcfg10=0x00000000 + --override cpu/mask_pmpcfg11=0x00000000 + --override cpu/mask_pmpcfg12=0x00000000 + --override cpu/mask_pmpcfg13=0x00000000 + --override cpu/mask_pmpcfg14=0x00000000 + --override cpu/mask_pmpcfg15=0x00000000 + # --showoverrides + # --trace --tracechange --traceshowicount --monitornets +cflags: > + -Wl,--nmagic +cv_sw_march: rv32im_zicsr_zba1p00_zbb1p00_zbc1p00_zbs1p00_zca_zcb_zcmp_zcmt_zifencei diff --git a/cv32e40s/tests/programs/custom/clic/clic.c b/cv32e40s/tests/programs/custom/clic/clic.c index b6b12651d3..e8e4d27b3d 100644 --- a/cv32e40s/tests/programs/custom/clic/clic.c +++ b/cv32e40s/tests/programs/custom/clic/clic.c @@ -148,27 +148,27 @@ typedef union { typedef union { struct { - volatile uint8_t uie : 1; // 0 - volatile uint8_t sie : 1; // 1 - volatile uint8_t wpri : 1; // 2 - volatile uint8_t mie : 1; // 3 - volatile uint8_t upie : 1; // 4 - volatile uint8_t spie : 1; // 5 - volatile uint8_t wpri0 : 1; // 6 - volatile uint8_t mpie : 1; // 7 - volatile uint8_t spp : 1; // 8 - volatile uint8_t wpri1 : 2; // 10: 9 - volatile uint8_t mpp : 2; // 12:11 - volatile uint8_t fs : 2; // 14:13 - volatile uint8_t xs : 2; // 16:15 - volatile uint8_t mprv : 1; // 17 - volatile uint8_t sum : 1; // 18 - volatile uint8_t mxr : 1; // 19 - volatile uint8_t tvm : 1; // 20 - volatile uint8_t tw : 1; // 21 - volatile uint8_t tsr : 1; // 22 - volatile uint8_t wpri3 : 8; // 30:23 - volatile uint8_t sd : 1; // 31 + volatile uint32_t uie : 1; // 0 + volatile uint32_t sie : 1; // 1 + volatile uint32_t wpri : 1; // 2 + volatile uint32_t mie : 1; // 3 + volatile uint32_t upie : 1; // 4 + volatile uint32_t spie : 1; // 5 + volatile uint32_t wpri0 : 1; // 6 + volatile uint32_t mpie : 1; // 7 + volatile uint32_t spp : 1; // 8 + volatile uint32_t wpri1 : 2; // 10: 9 + volatile uint32_t mpp : 2; // 12:11 + volatile uint32_t fs : 2; // 14:13 + volatile uint32_t xs : 2; // 16:15 + volatile uint32_t mprv : 1; // 17 + volatile uint32_t sum : 1; // 18 + volatile uint32_t mxr : 1; // 19 + volatile uint32_t tvm : 1; // 20 + volatile uint32_t tw : 1; // 21 + volatile uint32_t tsr : 1; // 22 + volatile uint32_t wpri3 : 8; // 30:23 + volatile uint32_t sd : 1; // 31 } volatile fields; volatile uint32_t raw; } __attribute__((packed)) mstatus_t; @@ -1709,6 +1709,85 @@ uint32_t rw_mnxti_without_irq_illegal(uint32_t index, uint8_t report_name) { test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + // CSRRS with rs1 != x0 - illegal + *g_expect_illegal = 31; + __asm__ volatile ( R"( + .option push + .option norvc + csrrs %[rd], 0x345, x1 + csrrs %[rd], 0x345, x2 + csrrs %[rd], 0x345, x3 + csrrs %[rd], 0x345, x4 + csrrs %[rd], 0x345, x5 + csrrs %[rd], 0x345, x6 + csrrs %[rd], 0x345, x7 + csrrs %[rd], 0x345, x8 + csrrs %[rd], 0x345, x9 + csrrs %[rd], 0x345, x10 + csrrs %[rd], 0x345, x11 + csrrs %[rd], 0x345, x12 + csrrs %[rd], 0x345, x13 + csrrs %[rd], 0x345, x14 + csrrs %[rd], 0x345, x15 + csrrs %[rd], 0x345, x16 + csrrs %[rd], 0x345, x17 + csrrs %[rd], 0x345, x18 + csrrs %[rd], 0x345, x19 + csrrs %[rd], 0x345, x20 + csrrs %[rd], 0x345, x21 + csrrs %[rd], 0x345, x22 + csrrs %[rd], 0x345, x23 + csrrs %[rd], 0x345, x24 + csrrs %[rd], 0x345, x25 + csrrs %[rd], 0x345, x26 + csrrs %[rd], 0x345, x27 + csrrs %[rd], 0x345, x28 + csrrs %[rd], 0x345, x29 + csrrs %[rd], 0x345, x30 + csrrs %[rd], 0x345, x31 + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + + // CSRRSI with imm[0, 2, 4] = 1 - illegal + *g_expect_illegal = 11; + __asm__ volatile ( R"( + .option push + .option norvc + # bit 0, 2, 4 + csrrsi %[rd], 0x345, 1 << 0 | 1 << 2 | 1 << 4 + # bit 0 + csrrsi %[rd], 0x345, 1 << 0 + # bit 2 + csrrsi %[rd], 0x345, 1 << 2 + # bit 4 + csrrsi %[rd], 0x345, 1 << 4 + # all bits + csrrsi %[rd], 0x345, 0x1f + # all bits without bit 0 and 2 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 0) & ~(1 << 2) + # all bits without bit 2 and 4 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 2) & ~(1 << 4) + # all bits without bit 0 and 4 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 0) & ~(1 << 4) + # all bits without 0 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 0) + # all bits without 2 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 2) + # all bits without 4 + csrrsi %[rd], 0x345, 0x1f & ~(1 << 4) + nop + .option pop + )":[rd] "=r"(mnxti_rval) + :: + ); + + test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); + if (test_fail) { cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); return index + 1; @@ -2250,6 +2329,7 @@ uint32_t rw_mscratchcsw_illegal(uint32_t index, uint8_t report_name) { __asm__ volatile (R"( csrrc zero, mstatus, %[rs1])" :: [rs1] "r"(mstatus_rval.raw):); + *g_expect_illegal = 1; __asm__ volatile (R"( csrrs %[rd], 0x348, sp)" : [rd] "=r"(reg_backup_1) ::); test_fail += (uint8_t)((*g_expect_illegal ? 1 : 0)); @@ -2721,6 +2801,13 @@ uint32_t mret_with_minhv(uint32_t index, uint8_t report_name) { :[mcause] "r"(mcause.raw) :"t0"); + // Clear minhv-bit + mcause.clic.minhv = 0; + + __asm__ volatile (R"( + csrrw zero, mcause, %[mcause] + )"::[mcause] "r"(mcause.raw)); + test_fail += (result != 0); if (test_fail) { @@ -2748,6 +2835,7 @@ void reset_cpu_interrupt_lvl(void) { mcause.clic.mpil = 0; mcause.clic.mpie = mstatus.fields.mie; mcause.clic.mpp = 0x3; + mcause.clic.minhv = 0; __asm__ volatile ( R"( la %[pc], continued @@ -3066,7 +3154,7 @@ __attribute__((interrupt("machine"))) void u_sw_irq_handler(void) { } if (mcause.clic.interrupt == 0 && mcause.clic.exccode == 2) { - *g_expect_illegal = 0; + (*g_expect_illegal)--; increment_mepc(0); return; } diff --git a/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c b/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c index 6fbaf41bc3..6795dad584 100644 --- a/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c +++ b/cv32e40s/tests/programs/custom/debug_test2/debug_test2.c @@ -215,137 +215,137 @@ typedef union { typedef union { struct { - volatile uint16_t load : 1; - volatile uint16_t store : 1; - volatile uint16_t execute : 1; - volatile uint16_t u : 1; - volatile uint16_t s : 1; - volatile uint16_t res_5_5 : 1; - volatile uint16_t m : 1; - volatile uint16_t match : 4; - volatile uint16_t chain : 1; - volatile uint16_t action : 4; - volatile uint16_t sizelo : 2; - volatile uint16_t timing : 1; - volatile uint16_t select : 1; - volatile uint16_t hit : 1; - volatile uint16_t maskmax : 6; - volatile uint16_t dmode : 1; - volatile uint16_t type : 4; + volatile uint32_t load : 1; + volatile uint32_t store : 1; + volatile uint32_t execute : 1; + volatile uint32_t u : 1; + volatile uint32_t s : 1; + volatile uint32_t res_5_5 : 1; + volatile uint32_t m : 1; + volatile uint32_t match : 4; + volatile uint32_t chain : 1; + volatile uint32_t action : 4; + volatile uint32_t sizelo : 2; + volatile uint32_t timing : 1; + volatile uint32_t select : 1; + volatile uint32_t hit : 1; + volatile uint32_t maskmax : 6; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; } __attribute__((packed)) volatile fields; volatile uint32_t raw; } __attribute__((packed)) mcontrol_t; typedef union { struct { - volatile uint16_t load : 1; - volatile uint16_t store : 1; - volatile uint16_t execute : 1; - volatile uint16_t u : 1; - volatile uint16_t s : 1; - volatile uint16_t res_5_5 : 1; - volatile uint16_t m : 1; - volatile uint16_t match : 4; - volatile uint16_t chain : 1; - volatile uint16_t action : 4; - volatile uint16_t size : 4; - volatile uint16_t timing : 1; - volatile uint16_t select : 1; - volatile uint16_t hit : 1; - volatile uint16_t vu : 1; - volatile uint16_t vs : 1; - volatile uint16_t res_26_25: 2; - volatile uint16_t dmode : 1; - volatile uint16_t type : 4; + volatile uint32_t load : 1; + volatile uint32_t store : 1; + volatile uint32_t execute : 1; + volatile uint32_t u : 1; + volatile uint32_t s : 1; + volatile uint32_t res_5_5 : 1; + volatile uint32_t m : 1; + volatile uint32_t match : 4; + volatile uint32_t chain : 1; + volatile uint32_t action : 4; + volatile uint32_t size : 4; + volatile uint32_t timing : 1; + volatile uint32_t select : 1; + volatile uint32_t hit : 1; + volatile uint32_t vu : 1; + volatile uint32_t vs : 1; + volatile uint32_t res_26_25: 2; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; } __attribute__((packed)) volatile fields; volatile uint32_t raw; } __attribute__((packed)) mcontrol6_t; typedef union { struct { - volatile uint8_t action : 6; - volatile uint8_t u : 1; - volatile uint8_t s : 1; - volatile uint8_t res_8_8 : 1; - volatile uint8_t m : 1; - volatile uint8_t res_10_10 : 1; - volatile uint8_t vu : 1; - volatile uint8_t vs : 1; - volatile uint16_t res_25_13 : 13; - volatile uint8_t hit : 1; - volatile uint8_t dmode : 1; - volatile uint8_t type : 4; + volatile uint32_t action : 6; + volatile uint32_t u : 1; + volatile uint32_t s : 1; + volatile uint32_t res_8_8 : 1; + volatile uint32_t m : 1; + volatile uint32_t res_10_10 : 1; + volatile uint32_t vu : 1; + volatile uint32_t vs : 1; + volatile uint32_t res_25_13 : 13; + volatile uint32_t hit : 1; + volatile uint32_t dmode : 1; + volatile uint32_t type : 4; } __attribute__((packed)) volatile fields; volatile uint32_t raw; } __attribute__((packed)) etrigger_t; typedef union { struct { - volatile uint16_t info : 16; - volatile uint16_t res_23_16 : 8; - volatile uint16_t version : 8; + volatile uint32_t info : 16; + volatile uint32_t res_23_16 : 8; + volatile uint32_t version : 8; } __attribute__((packed)) volatile fields; volatile uint32_t raw; } __attribute__((packed)) tinfo_t; typedef union { struct { - volatile uint8_t uie : 1; // 0 - volatile uint8_t sie : 1; // 1 - volatile uint8_t wpri : 1; // 2 - volatile uint8_t mie : 1; // 3 - volatile uint8_t upie : 1; // 4 - volatile uint8_t spie : 1; // 5 - volatile uint8_t wpri0 : 1; // 6 - volatile uint8_t mpie : 1; // 7 - volatile uint8_t spp : 1; // 8 - volatile uint8_t wpri1 : 2; // 10: 9 - volatile uint8_t mpp : 2; // 12:11 - volatile uint8_t fs : 2; // 14:13 - volatile uint8_t xs : 2; // 16:15 - volatile uint8_t mprv : 1; // 17 - volatile uint8_t sum : 1; // 18 - volatile uint8_t mxr : 1; // 19 - volatile uint8_t tvm : 1; // 20 - volatile uint8_t tw : 1; // 21 - volatile uint8_t tsr : 1; // 22 - volatile uint8_t wpri3 : 8; // 30:23 - volatile uint8_t sd : 1; // 31 + volatile uint32_t uie : 1; // 0 + volatile uint32_t sie : 1; // 1 + volatile uint32_t wpri : 1; // 2 + volatile uint32_t mie : 1; // 3 + volatile uint32_t upie : 1; // 4 + volatile uint32_t spie : 1; // 5 + volatile uint32_t wpri0 : 1; // 6 + volatile uint32_t mpie : 1; // 7 + volatile uint32_t spp : 1; // 8 + volatile uint32_t wpri1 : 2; // 10: 9 + volatile uint32_t mpp : 2; // 12:11 + volatile uint32_t fs : 2; // 14:13 + volatile uint32_t xs : 2; // 16:15 + volatile uint32_t mprv : 1; // 17 + volatile uint32_t sum : 1; // 18 + volatile uint32_t mxr : 1; // 19 + volatile uint32_t tvm : 1; // 20 + volatile uint32_t tw : 1; // 21 + volatile uint32_t tsr : 1; // 22 + volatile uint32_t wpri3 : 8; // 30:23 + volatile uint32_t sd : 1; // 31 } volatile clint; volatile uint32_t raw; } __attribute__((packed)) mstatus_t; typedef union { struct { - volatile uint16_t start_delay : 15; // 14: 0 - volatile uint16_t rand_start_delay : 1; // 15 - volatile uint16_t pulse_width : 13; // 28:16 - volatile uint16_t rand_pulse_width : 1; // 29 - volatile uint16_t pulse_mode : 1; // 30 0 = level, 1 = pulse - volatile uint16_t value : 1; // 31 + volatile uint32_t start_delay : 15; // 14: 0 + volatile uint32_t rand_start_delay : 1; // 15 + volatile uint32_t pulse_width : 13; // 28:16 + volatile uint32_t rand_pulse_width : 1; // 29 + volatile uint32_t pulse_mode : 1; // 30 0 = level, 1 = pulse + volatile uint32_t value : 1; // 31 } volatile fields; volatile uint32_t raw; } __attribute__((packed)) debug_req_control_t; typedef union { struct { - volatile uint16_t prv : 2; // 1:0 WARL (0x0, 0x3) PRV. Returns the privilege mode before debug entry. - volatile uint16_t step : 1; // 2 RW STEP. Set to enable single stepping. - volatile uint16_t nmip : 1; // 3 R NMIP. If set, an NMI is pending - volatile uint16_t mprven : 1; // 4 WARL (0x1) MPRVEN. Hardwired to 1. - volatile uint16_t res_5_5 : 1; // 5 WARL (0x0) V. Hardwired to 0. - volatile uint16_t cause : 3; // 8:6 R CAUSE. Return the cause of debug entry. - volatile uint16_t stoptime : 1; // 9 WARL (0x0) STOPTIME. Hardwired to 0. - volatile uint16_t stopcount : 1; // 10 WARL STOPCOUNT. - volatile uint16_t stepie : 1; // 11 WARL STEPIE. Set to enable interrupts during single stepping. - volatile uint16_t ebreaku : 1; // 12 WARL EBREAKU. Set to enter debug mode on ebreak during user mode. - volatile uint16_t ebreaks : 1; // 13 WARL (0x0) EBREAKS. Hardwired to 0. - volatile uint16_t res_14_14 : 1; // 14 WARL (0x0) Hardwired to 0. - volatile uint16_t ebreakm : 1; // 15 RW EBREAKM. Set to enter debug mode on ebreak during machine mode. - volatile uint16_t ebreakvu : 1; // 16 WARL (0x0) EBREAKVU. Hardwired to 0. - volatile uint16_t ebreakvs : 1; // 17 WARL (0x0) EBREAKVS. Hardwired to 0 - volatile uint16_t res_27_18 : 10; // 27:18 WARL (0x0) Reserved - volatile uint16_t xdebugver : 4; // 31:28 R (0x4) XDEBUGVER. External debug support exists as described in [RISC-V-DEBUG]. + volatile uint32_t prv : 2; // 1:0 WARL (0x0, 0x3) PRV. Returns the privilege mode before debug entry. + volatile uint32_t step : 1; // 2 RW STEP. Set to enable single stepping. + volatile uint32_t nmip : 1; // 3 R NMIP. If set, an NMI is pending + volatile uint32_t mprven : 1; // 4 WARL (0x1) MPRVEN. Hardwired to 1. + volatile uint32_t res_5_5 : 1; // 5 WARL (0x0) V. Hardwired to 0. + volatile uint32_t cause : 3; // 8:6 R CAUSE. Return the cause of debug entry. + volatile uint32_t stoptime : 1; // 9 WARL (0x0) STOPTIME. Hardwired to 0. + volatile uint32_t stopcount : 1; // 10 WARL STOPCOUNT. + volatile uint32_t stepie : 1; // 11 WARL STEPIE. Set to enable interrupts during single stepping. + volatile uint32_t ebreaku : 1; // 12 WARL EBREAKU. Set to enter debug mode on ebreak during user mode. + volatile uint32_t ebreaks : 1; // 13 WARL (0x0) EBREAKS. Hardwired to 0. + volatile uint32_t res_14_14 : 1; // 14 WARL (0x0) Hardwired to 0. + volatile uint32_t ebreakm : 1; // 15 RW EBREAKM. Set to enter debug mode on ebreak during machine mode. + volatile uint32_t ebreakvu : 1; // 16 WARL (0x0) EBREAKVU. Hardwired to 0. + volatile uint32_t ebreakvs : 1; // 17 WARL (0x0) EBREAKVS. Hardwired to 0 + volatile uint32_t res_27_18 : 10; // 27:18 WARL (0x0) Reserved + volatile uint32_t xdebugver : 4; // 31:28 R (0x4) XDEBUGVER. External debug support exists as described in [RISC-V-DEBUG]. } volatile fields; volatile uint32_t raw; } __attribute__((packed)) dcsr_t; diff --git a/cv32e40s/tests/programs/custom/debug_test_trigger/test.yaml b/cv32e40s/tests/programs/custom/debug_test_trigger/test.yaml index 332d7f4107..3fd76f835d 100644 --- a/cv32e40s/tests/programs/custom/debug_test_trigger/test.yaml +++ b/cv32e40s/tests/programs/custom/debug_test_trigger/test.yaml @@ -1,6 +1,3 @@ -# Test definition YAML for test - -# Debug trigger directed test name: debug_test_trigger uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c description: > diff --git a/cv32e40s/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c b/cv32e40s/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c index 7068b7da18..ba68d5f4fe 100644 --- a/cv32e40s/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c +++ b/cv32e40s/tests/programs/custom/hpmcounter_basic_nostall_test/hpmcounter_basic_nostall_test.c @@ -94,7 +94,7 @@ int main(int argc, char *argv[]) printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); printf("\nMCYCLE counted cycles = %d\n", mcycle_count); - err_cnt += chck(mcycle_count, 6); + err_cnt += chck(mcycle_count, 5); ////////////////////////////////////////////////////////////// // IF_INVALID diff --git a/cv32e40s/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c b/cv32e40s/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c index 75b1b90af9..1287b08c63 100644 --- a/cv32e40s/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c +++ b/cv32e40s/tests/programs/custom/hpmcounter_basic_test/hpmcounter_basic_test.c @@ -107,7 +107,7 @@ int main(int argc, char *argv[]) printf("\nminstret count = %d\n", minstret); err_cnt += chck(minstret, 4); printf("\nMCYCLE counted cycles = %d\n", mcycle_count); - err_cnt += chck_with_pos_margin(mcycle_count, 6, 4*MAX_STALL_CYCLES); + err_cnt += chck_with_pos_margin(mcycle_count, 5, 4*MAX_STALL_CYCLES); ////////////////////////////////////////////////////////////// // IF_INVALID diff --git a/cv32e40s/tests/programs/custom/pmp_csr_access_test/pmp_csr_access_test.c b/cv32e40s/tests/programs/custom/pmp_csr_access_test/pmp_csr_access_test.c new file mode 100644 index 0000000000..4f6c0a9bbf --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp_csr_access_test/pmp_csr_access_test.c @@ -0,0 +1,395 @@ +// +// Copyright 2023 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Henrik Fegran +// +// PMP CSR access test +// +///////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include "bsp.h" +#include "corev_uvmt.h" + +// MUST be 31 or less (bit position-1 in result array determines test pass/fail +// status, thus we are limited to 31 tests with this construct. +#define NUM_TESTS 2 +// Set which test index to start testing at (for quickly running specific tests during development) +#define START_TEST_IDX 0 + +// __FUNCTION__ is C99 and newer, -Wpedantic flags a warning that +// this is not ISO C, thus we wrap this instatiation in a macro +// ignoring this GCC warning to avoid a long list of warnings during +// compilation. +#define SET_FUNC_INFO \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wpedantic\"") \ + const volatile char * const volatile name = __FUNCTION__; \ + _Pragma("GCC diagnostic pop") + +// --------------------------------------------------------------- +// Convenience macros for bit fields +// --------------------------------------------------------------- +#define OPCODE_SYSTEM 0x73 +#define PMPCFG_BASE 0x3a0 +#define PMPADDR_BASE 0x3b0 +#define MSECCFG_BASE 0x747 + +// --------------------------------------------------------------- +// Global variables +// --------------------------------------------------------------- +// Print verbosity, consider implementing this as a virtual +// peripheral setting to be controlled from UVM. +volatile verbosity_t global_verbosity = V_LOW; + +volatile uint32_t * volatile g_csr_instr; +volatile uint32_t * volatile g_csr_instr_rd_val; +volatile uint32_t * volatile g_csr_instr_rs1_val; +// --------------------------------------------------------------- +// Test prototypes - should match +// uint32_t (uint32_t index, uint8_t report_name) +// +// Use template below for implementation +// --------------------------------------------------------------- +uint32_t pmp_write_addr_regs(uint32_t index, uint8_t report_name); +uint32_t pmp_write_cfg_regs(uint32_t index, uint8_t report_name); + +// --------------------------------------------------------------- +// Generic test template: +// --------------------------------------------------------------- +// uint32_t (uint32_t index, uint8_t report_name){ +// volatile uint8_t test_fail = 0; +// /* Test variable instantiation */ +// +// SET_FUNC_INFO +// +// if (report_name) { +// cvprintf(V_LOW, "\"%s\"", name); +// return 0; +// } +// +// /* Insert test code here /* +// +// if (test_fail) { +// cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); +// return index + 1; +// } +// cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); +// return 0; +// } +// --------------------------------------------------------------- + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +/* + * set_test_status + * + * Sets the pass/fail criteria for a given tests and updates + * the 32bit test status variable. + * + * - test_no: current test index + * - val_prev: status vector variable, holding previous test results + */ +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev); + +/* + * get_result + * + * Reports result of self checking tests + * + * - res: result-vector from previously run tests + * - ptr: Pointer to test functions, this is intended to be + * invoked with "report_name == 1" here, as that will + * only print the name of the test and not actually + * run it. + */ +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)); + +/* + * cvprintf + * + * verbosity controlled printf + * use as printf, but with an added verbosity-level setting + * + */ +int cvprintf(verbosity_t verbosity, const char *format, ...); + +/* + * call_word_instr + * + * Sets up the system to execute a 32bit word as an instruction + * and return to the regular execution flow + */ +void call_word_instr(uint32_t instr_word); + +/* + * csr_instr + * + * Execute a csr access instruction + * + * - funct3: CSRRW, CSRRS, CSRRC, CSRRWI, CSRRSI, CSRRCI + * - addr: csr register address (numeric) + * - rs1_uimm_val: rs1/uimm _value_ to supply to instruction + * - return value contains value read from csr + * + */ +uint32_t csr_instr(csr_instr_access_t funct3, uint32_t addr, uint32_t rs1_uimm_val); + +// --------------------------------------------------------------- +// Test entry point +// --------------------------------------------------------------- +int main(int argc, char **argv){ + + volatile uint32_t (* volatile tests[NUM_TESTS])(volatile uint32_t, volatile uint8_t); + + volatile uint32_t test_res = 0x1; + volatile int retval = 0; + + g_csr_instr = calloc(1, sizeof(uint32_t)); + g_csr_instr_rd_val = calloc(1, sizeof(uint32_t)); + g_csr_instr_rs1_val = calloc(1, sizeof(uint32_t)); + + // Add function pointers to new tests here + tests[0] = pmp_write_addr_regs; + tests[1] = pmp_write_cfg_regs; + + // Run all tests in list above + cvprintf(V_LOW, "\nPMP CSR Test start\n\n"); + for (volatile int i = START_TEST_IDX; i < NUM_TESTS; i++) { + test_res = set_test_status(tests[i](i, (volatile uint32_t)(0)), test_res); + } + + // Report failures + retval = get_result(test_res, tests); + + free((void *)g_csr_instr ); + free((void *)g_csr_instr_rd_val ); + free((void *)g_csr_instr_rs1_val ); + return retval; // Nonzero for failing tests +} + +// ----------------------------------------------------------------------------- + +int cvprintf(volatile verbosity_t verbosity, const char * volatile format, ...){ + va_list args; + volatile int retval = 0; + + va_start(args, format); + + if (verbosity <= global_verbosity){ + retval = vprintf(format, args); + } + va_end(args); + return retval; +} + +// ----------------------------------------------------------------------------- + +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev){ + volatile uint32_t res; + res = val_prev | (1 << test_no); + return res; +} + +// ----------------------------------------------------------------------------- + +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)){ + cvprintf(V_LOW, "=========================\n"); + cvprintf(V_LOW, "= SUMMARY =\n"); + cvprintf(V_LOW, "=========================\n"); + for (int i = START_TEST_IDX; i < NUM_TESTS; i++){ + if ((res >> (i+1)) & 0x1) { + cvprintf (V_LOW, "Test %0d FAIL: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } else { + cvprintf (V_LOW, "Test %0d PASS: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } + } + if (res == 1) { + cvprintf(V_LOW, "\n\tALL SELF CHECKS PASS!\n\n"); + return 0; + } else { + cvprintf(V_LOW, "\n\tSELF CHECK FAILURES OCCURRED!\n\n"); + return res; + } +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) call_word_instr(uint32_t instr_word){ + __asm__ volatile ( R"( + .global ptr_loc + addi sp, sp, -8 + sw a0, 0(sp) + sw s0, 4(sp) + + la s0, ptr_loc + sw a0, 0(s0) + fence.i + # ensure that we have a location to write our pointer + ptr_loc: .word(0x00000000) + + lw s0, 4(sp) + lw a0, 0(sp) + addi sp, sp, 8 + ret + )"); +} + +// ----------------------------------------------------------------------------- + +uint32_t csr_instr(csr_instr_access_t funct3, uint32_t addr, uint32_t rs1_uimm_val) { + volatile csr_instr_t csr_instr = { 0 }; + + *g_csr_instr_rd_val = 0; + *g_csr_instr_rs1_val = rs1_uimm_val; + + switch (funct3) { + case CSRRW: + case CSRRS: + case CSRRC: + csr_instr = (csr_instr_t){ + .fields.opcode = OPCODE_SYSTEM, + .fields.rd = 11, // a1 reg + .fields.funct3 = funct3, + .fields.rs1_uimm = (rs1_uimm_val == 0) ? 0 : 12, // a2 reg unless zero specified + .fields.csr = addr + }; + break; + case CSRRWI: + case CSRRSI: + case CSRRCI: + csr_instr = (csr_instr_t){ + .fields.opcode = OPCODE_SYSTEM, + .fields.rd = 11, // a1 reg + .fields.funct3 = funct3, + .fields.rs1_uimm = rs1_uimm_val, + .fields.csr = addr + }; + break; + default: return 0; + } + + *g_csr_instr = csr_instr.raw; + + __asm__ volatile ( R"( + addi sp, sp, -16 + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + sw ra, 12(sp) + + lw a0, g_csr_instr + lw a0, 0(a0) + lw a2, g_csr_instr_rs1_val + lw a2, 0(a2) + jal ra, call_word_instr + lw a2, g_csr_instr_rd_val + sw a1, 0(a2) + + lw ra, 12(sp) + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 16 + )"); + + return *g_csr_instr_rd_val; +} + +// ----------------------------------------------------------------------------- + +uint32_t pmp_write_addr_regs(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + for (int i = 0; i < 64; i++) { + (void)csr_instr(CSRRW, PMPADDR_BASE + i, 0xffffffffUL); + (void)csr_instr(CSRRW, PMPADDR_BASE + i, 0x00000000UL); + (void)csr_instr(CSRRS, PMPADDR_BASE + i, 0xffffffffUL); + (void)csr_instr(CSRRC, PMPADDR_BASE + i, 0xffffffffUL); + test_fail = 63 - i; // fail test if we somehow did not run through the entire loop + } + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t pmp_write_cfg_regs(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Set rlb in mseccfg to enable us to revert changes to pmp regions + (void)csr_instr(CSRRS, MSECCFG_BASE, 4UL); + + // Set all addr regs to top of memory (unused) to avoid lockout + for (int i = 0; i < 64; i++) { + (void)csr_instr(CSRRW, PMPADDR_BASE + i, 0xffffffffUL); + } + + // Set/clear all cfg reg bits to 1 + for (int i = 0; i < 16; i++) { + (void)csr_instr(CSRRW, PMPCFG_BASE + i, 0xffffffffUL); + (void)csr_instr(CSRRW, PMPCFG_BASE + i, 0x00000000UL); + (void)csr_instr(CSRRS, PMPCFG_BASE + i, 0xffffffffUL); + (void)csr_instr(CSRRC, PMPCFG_BASE + i, 0xffffffffUL); + test_fail = 15 - i; // fail test if we somehow did not run through the entire loop + } + + // Clear all addr reg bits + for (int i = 0; i < 64; i++) { + (void)csr_instr(CSRRCI, PMPADDR_BASE + i, 0x00000000UL); + } + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + diff --git a/cv32e40s/tests/programs/custom/pmp_csr_access_test/test.yaml b/cv32e40s/tests/programs/custom/pmp_csr_access_test/test.yaml new file mode 100644 index 0000000000..9c31162c82 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pmp_csr_access_test/test.yaml @@ -0,0 +1,7 @@ +name: pmp_csr_access_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + PMP csr access directed test +plusargs: > +cflags: > + -mno-relax diff --git a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c new file mode 100644 index 0000000000..aca7c7a4d3 --- /dev/null +++ b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/pushpop_debug_triggers.c @@ -0,0 +1,301 @@ +// Copyright 2023 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you +// may not use this file except in compliance with the License, or, at your +// option, the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + +#include +#include +#include + +#include "bsp.h" +#include "corev_uvmt.h" + + +volatile uint32_t g_debug_entered = 0; +volatile uint32_t g_debug_expected = 0; +volatile uint32_t g_debug_function_incr_dpc = 0; +volatile uint32_t g_debug_function_setup_triggers = 0; + +volatile uint32_t g_exception_expected = 0; + +volatile uint32_t g_pushpop_area [32]; + +void disable_debug_req(void) { + CV_VP_DEBUG_CONTROL = ( + CV_VP_DEBUG_CONTROL_DBG_REQ(0) | + CV_VP_DEBUG_CONTROL_REQ_MODE(0) | + CV_VP_DEBUG_CONTROL_RAND_PULSE_DURATION(0) | + CV_VP_DEBUG_CONTROL_PULSE_DURATION(0) | + CV_VP_DEBUG_CONTROL_RAND_START_DELAY(0) | + CV_VP_DEBUG_CONTROL_START_DELAY(0) + ); +} + +__attribute__((interrupt("machine"))) +void u_sw_irq_handler(void){ + if (! g_exception_expected) { + printf("error: exception handler entered unexpectedly\n"); + exit(EXIT_FAILURE); + } + + g_exception_expected = 0; +} + +__attribute__((section(".debugger"), naked)) +void debug_start(void) { + __asm__ volatile (R"( + # Backup "sp", use debug's own stack + csrw dscratch0, sp + la sp, __debugger_stack_start + + # Backup all GPRs + sw a0, -4(sp) + sw a1, -8(sp) + sw a2, -12(sp) + sw a3, -16(sp) + sw a4, -20(sp) + sw a5, -24(sp) + sw a6, -28(sp) + sw a7, -32(sp) + sw t0, -36(sp) + sw t1, -40(sp) + sw t2, -44(sp) + sw t3, -48(sp) + sw t4, -52(sp) + sw t5, -56(sp) + sw t6, -60(sp) + addi sp, sp, -64 + cm.push {ra, s0-s11}, -64 + + # Call the handler actual + call ra, debug_handler + + # Restore all GPRs + cm.pop {ra, s0-s11}, 64 + addi sp, sp, 64 + lw a0, -4(sp) + lw a1, -8(sp) + lw a2, -12(sp) + lw a3, -16(sp) + lw a4, -20(sp) + lw a5, -24(sp) + lw a6, -28(sp) + lw a7, -32(sp) + lw t0, -36(sp) + lw t1, -40(sp) + lw t2, -44(sp) + lw t3, -48(sp) + lw t4, -52(sp) + lw t5, -56(sp) + lw t6, -60(sp) + + # Restore "sp" + csrr sp, dscratch0 + + # Done + dret + )"); +} + +static void setup_triggers(void){ + mcontrol6_t mcontrol6; + uint32_t trigger_addr; + + mcontrol6.raw = 0x00000000; + mcontrol6.fields.load = 1; + mcontrol6.fields.store = 1; + mcontrol6.fields.m = 1; + mcontrol6.fields.match = 0; // (match exact address) + mcontrol6.fields.type = 6; + + trigger_addr = (uint32_t) &(g_pushpop_area[2]); // (arbitrary index) + + __asm__ volatile( + R"( + # Use trigger 0 + csrwi tselect, 0 + + # Disable trigger + csrwi tdata1, 0 + + # Set trigger address + csrw tdata2, %[trigger_addr] + + # Configure trigger + csrw tdata1, %[mcontrol6] + )" + : + : [mcontrol6] "r" (mcontrol6.raw), + [trigger_addr] "r" (trigger_addr) + ); +} + +static void incr_dpc(void){ + uint32_t dpc; + uint32_t instr_word; + + __asm__ volatile( + "csrr %[dpc], dpc" + : [dpc] "=r" (dpc) + ); + + instr_word = *(uint32_t *)dpc; + + if ((instr_word & 0x3) == 0x3) { + dpc += 4; + } else { + dpc += 2; + } + + __asm__ volatile( + "csrw dpc, %[dpc]" + : : [dpc] "r" (dpc) + ); +} + +void debug_handler(void){ + g_debug_entered = 1; + disable_debug_req(); + printf("debug handler entered\n"); + + if (! g_debug_expected) { + printf("error: debug entered unexpectedly\n"); + exit(EXIT_FAILURE); + } + g_debug_expected = 0; + + if (g_debug_function_setup_triggers) { + g_debug_function_setup_triggers = 0; + setup_triggers(); + return; + } + if (g_debug_function_incr_dpc) { + g_debug_function_incr_dpc = 0; + incr_dpc(); + return; + } + + printf("error: debug handler function not specified\n"); + exit(EXIT_FAILURE); +} + +__attribute__((naked)) +static void push_debug_trigger(void){ + __asm__ volatile( + R"( + # Save old "sp" + mv t0, sp + + # Setup temporary "sp" + la sp, g_pushpop_area + addi sp, sp, 16 + + # Push to temporary "sp" + cm.push {x1, x8-x9}, -16 + + # Restore old "sp" + mv sp, t0 + + ret + )" + ); +} + +__attribute__((naked)) +static void pop_debug_trigger(void){ + __asm__ volatile( + R"( + # Save old "sp" and GPRs + cm.push {x1, x8-x9}, -16 + mv t0, sp + + # Setup temporary "sp" + la sp, g_pushpop_area + + # Pop from temporary "sp" + cm.pop {x1, x8-x9}, 16 + + # Restore old "sp" and GPRs + mv sp, t0 + cm.pop {x1, x8-x9}, 16 + + ret + )" + ); +} + +static void let_dmode_setup_triggers(void){ + printf("setup trigs\n"); + + g_debug_expected = 1; + g_debug_entered = 0; + g_debug_function_setup_triggers = 1; + + // Prolonged pulse duration so debug req has a chance to be acked and taken + CV_VP_DEBUG_CONTROL = ( + CV_VP_DEBUG_CONTROL_DBG_REQ(1) | + CV_VP_DEBUG_CONTROL_REQ_MODE(1) | + CV_VP_DEBUG_CONTROL_RAND_PULSE_DURATION(0) | + CV_VP_DEBUG_CONTROL_PULSE_DURATION(0x1fff) | + CV_VP_DEBUG_CONTROL_RAND_START_DELAY(0) | + CV_VP_DEBUG_CONTROL_START_DELAY(200) + ); + + while (! g_debug_entered) { + ; + } +} + +static void test_push_debug_trigger(void){ + printf("push trigger\n"); + + g_debug_expected = 1; + g_debug_function_incr_dpc = 1; + g_debug_entered = 0; + + push_debug_trigger(); + + if (! g_debug_entered) { + printf("error: push should trigger debug\n"); + exit(EXIT_FAILURE); + } +} + +static void test_pop_debug_trigger(void){ + printf("pop trigger\n"); + + g_debug_expected = 1; + g_debug_function_incr_dpc = 1; + g_debug_entered = 0; + + pop_debug_trigger(); + + if (! g_debug_entered) { + printf("error: pop should trigger debug\n"); + exit(EXIT_FAILURE); + } + + return; +} + +int main(int argc, char **argv){ + let_dmode_setup_triggers(); + test_push_debug_trigger(); + test_pop_debug_trigger(); + + return EXIT_SUCCESS; +} diff --git a/cv32e40s/tests/programs/custom/pushpop_debug_triggers/test.yaml b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/test.yaml new file mode 100644 index 0000000000..f92d937bcb --- /dev/null +++ b/cv32e40s/tests/programs/custom/pushpop_debug_triggers/test.yaml @@ -0,0 +1,5 @@ +name: pushpop_debug_triggers +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +program: pushpop_debug_triggers +description: > + Let Zc push/pop watchpoint triggers cause debug entry. diff --git a/cv32e40s/tests/programs/custom/wfe_test/wfe_test.c b/cv32e40s/tests/programs/custom/wfe_test/wfe_test.c index 0a32b518b3..ae18571fcd 100644 --- a/cv32e40s/tests/programs/custom/wfe_test/wfe_test.c +++ b/cv32e40s/tests/programs/custom/wfe_test/wfe_test.c @@ -18,6 +18,7 @@ // Author: Henrik Fegran // // WFE directed test +// Also includes test for wfi + mstatus.tw = 1 => illegal instruction in U-mode // ///////////////////////////////////////////////////////////////////////////////// @@ -26,16 +27,20 @@ #include #include #include +#include "bsp.h" #include "corev_uvmt.h" // MUST be 31 or less (bit position-1 in result array determines test pass/fail // status, thus we are limited to 31 tests with this construct. -#define NUM_TESTS 1 +#define NUM_TESTS 3 // Set which test index to start testing at (for quickly running specific tests during development) #define START_TEST_IDX 0 #define WFE_INSTR 0x8c000073 +#define MARCHID_CV32E40X 0x14 +#define MARCHID_CV32E40S 0x15 + // __FUNCTION__ is C99 and newer, -Wpedantic flags a warning that // this is not ISO C, thus we wrap this instatiation in a macro // ignoring this GCC warning to avoid a long list of warnings during @@ -50,15 +55,6 @@ // Convenience macros for bit fields // --------------------------------------------------------------- -// Verbosity levels (Akin to the uvm verbosity concept) -typedef enum { - V_OFF = 0, - V_LOW = 1, - V_MEDIUM = 2, - V_HIGH = 3, - V_DEBUG = 4 -} verbosity_t; - // --------------------------------------------------------------- // Global variables // --------------------------------------------------------------- @@ -66,6 +62,7 @@ typedef enum { // peripheral setting to be controlled from UVM. volatile verbosity_t global_verbosity = V_LOW; +volatile uint32_t * volatile g_illegal_instr_exp; // --------------------------------------------------------------- // Test prototypes - should match // uint32_t (uint32_t index, uint8_t report_name) @@ -73,6 +70,8 @@ volatile verbosity_t global_verbosity = V_LOW; // Use template below for implementation // --------------------------------------------------------------- uint32_t wfe_wakeup(uint32_t index, uint8_t report_name); +uint32_t wfe_wakeup_umode(uint32_t index, uint8_t report_name); +uint32_t wfi_mstatus_tw_umode_illegal(uint32_t index, uint8_t report_name); // --------------------------------------------------------------- // Generic test template: @@ -135,6 +134,46 @@ int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)); */ int cvprintf(verbosity_t verbosity, const char *format, ...); +/* + * set_mseccfg + * + * Sets up mseccfg with the provided + * mseccfg_t object + */ +void set_mseccfg(mseccfg_t mseccfg); + +/* + * set_pmpcfg + * + * Sets up pmp configuration for a given region + * (defined in pmpcfg_t object) + */ +void set_pmpcfg(pmpsubcfg_t pmpsubcfg, uint32_t reg_no); + +/* + * increment_mepc + * + * Increments mepc, + * incr_val 0 = auto detect + * 2 = halfword + * 4 = word + */ +void increment_mepc(volatile uint32_t incr_val); + +/* + * has_pmp_configured + * + * Returns 1 if pmp is enabled/supported else returns 0 + */ +uint32_t has_pmp_configured(void); + +/* + * Non-standard illegal instruction and ecall handlers + */ +void handle_illegal_insn(void); +void handle_ecall(void); +void handle_ecall_u(void); + // --------------------------------------------------------------- // Test entry point // --------------------------------------------------------------- @@ -145,8 +184,12 @@ int main(int argc, char **argv){ volatile uint32_t test_res = 0x1; volatile int retval = 0; + g_illegal_instr_exp = calloc(1, sizeof(uint32_t)); + // Add function pointers to new tests here tests[0] = wfe_wakeup; + tests[1] = wfe_wakeup_umode; + tests[2] = wfi_mstatus_tw_umode_illegal; // Run all tests in list above cvprintf(V_LOW, "\nWFE Test start\n\n"); @@ -157,6 +200,7 @@ int main(int argc, char **argv){ // Report failures retval = get_result(test_res, tests); + free((void *)g_illegal_instr_exp ); return retval; // Nonzero for failing tests } @@ -211,8 +255,353 @@ int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)){ // ----------------------------------------------------------------------------- +uint32_t has_pmp_configured(void) { + volatile uint32_t pmpaddr0 = 0xffffffff; + volatile uint32_t pmpaddr0_backup = 0; + volatile uint32_t marchid = 0x0; + + __asm__ volatile (R"( + csrrs %[marchid], marchid, zero + )":[marchid] "=r"(marchid)); + + // CV32E40X does not support PMP, skip + switch (marchid) { + case (MARCHID_CV32E40X): + return 0; + break; + case (MARCHID_CV32E40S): + ;; // Do nothing and continue execution + break; + } + + __asm__ volatile (R"( + csrrw %[pmpaddr0_backup] , pmpaddr0, %[pmpaddr0] + csrrw %[pmpaddr0], pmpaddr0, %[pmpaddr0_backup] + )" :[pmpaddr0_backup] "+r"(pmpaddr0_backup), + [pmpaddr0] "+r"(pmpaddr0)); + + return (pmpaddr0 != 0); +} + +// ----------------------------------------------------------------------------- + +void set_mseccfg(mseccfg_t mseccfg){ + + __asm__ volatile ( R"( + csrrs x0, mseccfg, %[cfg_vec] + )" + : + : [cfg_vec] "r"(mseccfg.raw) + :); + + cvprintf(V_DEBUG, "Wrote mseccfg: 0x%08lx\n", mseccfg.raw); +} + +// ----------------------------------------------------------------------------- + +void set_pmpcfg(pmpsubcfg_t pmpsubcfg, uint32_t reg_no){ + volatile pmpcfg_t temp = { 0 }; + volatile pmpcfg_t pmpcfg = { 0 }; + + pmpcfg.reg_idx[reg_no % 4].cfg = pmpsubcfg.raw; + + temp.reg_idx[reg_no % 4].cfg = 0xff; + + switch (reg_no / 4) { + case 0: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg0, t0 + csrrs zero, pmpcfg0, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 1: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg1, t0 + csrrs zero, pmpcfg1, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 2: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg2, t0 + csrrs zero, pmpcfg2, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 3: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg3, t0 + csrrs zero, pmpcfg3, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 4: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg4, t0 + csrrs zero, pmpcfg4, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + case 5: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg5, t0 + csrrs zero, pmpcfg5, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 6: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg6, t0 + csrrs zero, pmpcfg6, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 7: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg7, t0 + csrrs zero, pmpcfg7, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 8: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg8, t0 + csrrs zero, pmpcfg8, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 9: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg9, t0 + csrrs zero, pmpcfg9, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 10: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg10, t0 + csrrs zero, pmpcfg10, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 11: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg11, t0 + csrrs zero, pmpcfg11, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 12: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg12, t0 + csrrs zero, pmpcfg12, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 13: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg13, t0 + csrrs zero, pmpcfg13, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 14: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg14, t0 + csrrs zero, pmpcfg14, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + case 15: + __asm__ volatile ( R"( + add t0, x0, %[tmp] + csrrc x0, pmpcfg15, t0 + csrrs zero, pmpcfg15, %[cfg_vec] + )" + : [cfg_vec] "+r"(pmpcfg.raw) + : [tmp] "r"(temp.raw) + : "t0" + ); + break; + } + + cvprintf(V_DEBUG, "Set pmpcfg_vector: 0x%08lx\n", pmpcfg.raw); + return; +} + +// ----------------------------------------------------------------------------- + +void increment_mepc(volatile uint32_t incr_val) { + volatile uint32_t mepc = 0; + + __asm__ volatile ( R"( + csrrs %[mepc], mepc, zero + )" : [mepc] "=r"(mepc)); + + if (incr_val == 0) { + // No increment specified, check *mepc instruction + if (((*(uint32_t *)mepc) & 0x3UL) == 0x3UL) { + // non-compressed + mepc += 4; + } else { + // compressed + mepc += 2; + } + } else { + // explicitly requested increment + mepc += incr_val; + } + + __asm__ volatile ( R"( + csrrw zero, mepc, %[mepc] + )" :: [mepc] "r"(mepc)); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) handle_ecall(void){ + __asm__ volatile ( R"( + j handle_ecall_u + )"); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) handle_ecall_u(void){ + __asm__ volatile ( R"( + ## handle_ecall_u swaps privilege level, + ## if in M-mode -> mret to U + ## else U-mode -> mret to M + + addi sp, sp, -12 + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + + # Get current priv-mode + csrrs a2, mstatus, zero + + # clear out non-mpp bits and set up a2 to update mpp + lui a1, 2 + addi a1, a1, -2048 + and a2, a2, a1 + + # check if we trapped from U or M-mode + beq a1, a2, 1f + j 2f + + # mpp = M-mode -> U-mode + 1: + csrrc zero, mstatus, a1 + j 3f + + # mpp = U-mode -> M-mode + 2: + csrrs zero, mstatus, a1 + + 3: + # Set 0 as argument for increment_mepc + addi a0, zero, 0 + call increment_mepc + + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 12 + + # return to regular bsp handler flow + j end_handler_ret + + )"); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) handle_illegal_insn(void) { + __asm__ volatile ( R"( + addi sp, sp, -8 + sw s0, 0(sp) + sw s1, 4(sp) + + # Decrement *g_illegal_instr_exp + lw s0, g_illegal_instr_exp + lw s1, 0(s0) + addi s1, s1, -1 + sw s1, 0(s0) + + lw s1, 4(sp) + lw s0, 0(sp) + addi sp, sp, 8 + + j end_handler_incr_mepc + )"); +} + +// ----------------------------------------------------------------------------- + uint32_t wfe_wakeup(uint32_t index, uint8_t report_name){ volatile uint8_t test_fail = 0; + volatile mstatus_t mstatus = { 0 }; SET_FUNC_INFO @@ -221,6 +610,8 @@ uint32_t wfe_wakeup(uint32_t index, uint8_t report_name){ return 0; } + *g_illegal_instr_exp = 0; + // Execute wfe instructions and wait for wfe noise gen to wake core up // Expected to be checked by ISS __asm__ volatile (R"( @@ -240,11 +631,32 @@ uint32_t wfe_wakeup(uint32_t index, uint8_t report_name){ )"::[wfe] "i"(WFE_INSTR)); // print another string to execute many instructions - cvprintf(V_LOW, "abcdefghijklmnopqrstuvwxyz"); + cvprintf(V_LOW, "abcdefghijklmnopqrstuvwxyz\n"); + __asm__ volatile (R"( + .word(%[wfe]) + )"::[wfe] "i"(WFE_INSTR)); + + // Set timeout wait (mstatus.tw) + mstatus.fields.tw = 1; + __asm__ volatile ( R"( + csrrs zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + __asm__ volatile (R"( .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) )"::[wfe] "i"(WFE_INSTR)); + __asm__ volatile ( R"( + csrrc zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + test_fail = (*g_illegal_instr_exp != 0); + if (test_fail) { // Should never be here in this test case unless something goes really wrong cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); @@ -254,4 +666,148 @@ uint32_t wfe_wakeup(uint32_t index, uint8_t report_name){ return 0; } +// ----------------------------------------------------------------------------- + +uint32_t wfe_wakeup_umode(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile uint32_t pmpaddr = 0xffffffff; + volatile mstatus_t mstatus = { 0 }; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Check if there user mode support + if (!has_pmp_configured()) { + cvprintf(V_LOW, "Skipping test: User mode/PMP not supported\n"); + return 0; + } + + // Setup PMP access for u-mode (otherwise all deny) + set_mseccfg((mseccfg_t){ + .fields.mml = 0, + .fields.mmwp = 0, + .fields.rlb = 1, + }); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + __asm__ volatile ( R"( + csrrw zero, pmpaddr0, %[pmpaddr] + )":: [pmpaddr] "r"(pmpaddr)); + + *g_illegal_instr_exp = 0; + __asm__ volatile ( R"( + ecall + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + ecall + # add safe return location + nop + )"::[wfe] "i"(WFE_INSTR)); + + test_fail = (*g_illegal_instr_exp != 0); + + // Set timeout wait (mstatus.tw) + mstatus.fields.tw = 1; + __asm__ volatile ( R"( + csrrs zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + *g_illegal_instr_exp = 6; + __asm__ volatile ( R"( + ecall + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + .word(%[wfe]) + ecall + # add safe return location + nop + )"::[wfe] "i"(WFE_INSTR)); + + __asm__ volatile ( R"( + csrrc zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + test_fail = (*g_illegal_instr_exp != 0); + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t wfi_mstatus_tw_umode_illegal(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mstatus_t mstatus = { 0 }; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Check if there user mode support + if (!has_pmp_configured()) { + cvprintf(V_LOW, "Skipping test: User mode/pmp not supported\n"); + return 0; + } + + // Set timeout wait (mstatus.tw) + mstatus.fields.tw = 1; + __asm__ volatile ( R"( + csrrs zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + *g_illegal_instr_exp = 6; + __asm__ volatile ( R"( + ecall + wfi + wfi + wfi + wfi + wfi + wfi + ecall + # add safe return location + nop + )":::); + + __asm__ volatile ( R"( + csrrc zero, mstatus, %[mstatus] + )":: [mstatus] "r"(mstatus.raw)); + + test_fail = (*g_illegal_instr_exp != 0); + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + + // ----------------------------------------------------------------------------- diff --git a/cv32e40s/tests/programs/custom/xsecure_csrs/xsecure_csrs.c b/cv32e40s/tests/programs/custom/xsecure_csrs/xsecure_csrs.c index 21a0969720..8a2e247f25 100644 --- a/cv32e40s/tests/programs/custom/xsecure_csrs/xsecure_csrs.c +++ b/cv32e40s/tests/programs/custom/xsecure_csrs/xsecure_csrs.c @@ -1,7 +1,28 @@ +// Copyright 2022 Silicon Labs, Inc. +// +// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1 +// +// Licensed under the Solderpad Hardware License v 2.1 (the "License"); you +// may not use this file except in compliance with the License, or, at your +// option, the Apache License version 2.0. +// +// You may obtain a copy of the License at +// https://solderpad.org/licenses/SHL-2.1/ +// +// Unless required by applicable law or agreed to in writing, any work +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// +// See the License for the specific language governing permissions and +// limitations under the License. + + #include #include #include +#include "bsp.h" + #define CSRADDR_CPUCTRL 0xBF0 #define CSRADDR_SECURESEED0 0xBF9 #define CSRADDR_SECURESEED1 0xBFA @@ -11,7 +32,68 @@ #define S(x) #x #define STR(s) S(s) -int main(void) { + +volatile uint32_t g_got_illegal_instruction_exception; +volatile uint32_t g_got_trap; + + +__attribute__((interrupt("machine"))) +void u_sw_irq_handler(void){ + uint32_t exccode; + uint32_t instr_word; + uint32_t mcause; + uint32_t ret_addr; + uint32_t *mepc; + + + // Read CSRs + + __asm__ volatile( + "csrr %[mcause], mcause" + : [mcause] "=r" (mcause) + ); + + exccode = mcause & 0xFFF; + + + // Handle causes + + g_got_trap = 1; + + if (exccode == EXC_CAUSE_ILLEGAL_INSTR) { + g_got_illegal_instruction_exception = 1; + } + + + // Setup mepc + + __asm__ volatile( + "csrr %[mepc], mepc" + : [mepc] "=r" (mepc) + ); + + instr_word = *mepc; + + if ((instr_word & 0x3) == 0x3) { + ret_addr = ((uint32_t)mepc) + 4; + } else { + ret_addr = ((uint32_t)mepc) + 2; + } + + __asm__ volatile( + "csrw mepc, %[ret_addr]" + : : [ret_addr] "r" (ret_addr) + ); + + return; +} + +static void turn_on_dummies(void){ + // "cpuctrl.rnddummy" + __asm__ volatile( "csrrs x0, 0xBF0, 2" ); +} + +static void test_csr_accesses(void) { uint32_t rd; const uint32_t rs1 = 0xFFFFFFFF; @@ -38,10 +120,113 @@ int main(void) { __asm__ volatile("csrwi " STR(CSRADDR_SECURESEED2) ", 0xF"); __asm__ volatile("csrrs %0, " STR(CSRADDR_SECURESEED2) ", %1" : "=r"(rd) : "r"(rs1)); __asm__ volatile("csrrc %0, " STR(CSRADDR_SECURESEED2) ", %1" : "=r"(rd) : "r"(rs1)); +} - // Test the one particular line that first caught a problem +static void test_previous_issues(void) { + // This particular line has previously caught a problem __asm__ volatile("csrwi 0xBF0, 0x2"); +} + +static void test_lfsr_lockup(void){ + volatile uint32_t zero = 0; + + turn_on_dummies(); + + + // "secureseed0" (Have to copy-paste because csr instr...) + + g_got_trap = 0; + + __asm__ volatile( + "csrrw x0, 0xBF9, %[zero]" + : : [zero] "r" (zero) + ); + + if (g_got_trap) { + printf("error: writing 0 to secureseed0 shouldn't trap\n"); + exit(EXIT_FAILURE); + } + + + // "secureseed1" + + g_got_trap = 0; + + __asm__ volatile( + "csrrw x0, 0xBFA, %[zero]" + : : [zero] "r" (zero) + ); + + if (g_got_trap) { + printf("error: writing 0 to secureseed1 shouldn't trap\n"); + exit(EXIT_FAILURE); + } + + + // "secureseed2" + + g_got_trap = 0; + + __asm__ volatile( + "csrrw x0, 0xBFC, %[zero]" + : : [zero] "r" (zero) + ); + + if (g_got_trap) { + printf("error: writing 0 to secureseed2 shouldn't trap\n"); + exit(EXIT_FAILURE); + } + + + // These checks of LFSR lockups could include an additional check that a + // minor alert gets signaled on each lockup. + // (E.g. make a new virtual peripheral for it.) + // It is not done now, as the primary goal is only to close a coverage hole. +} + +static void test_secureseed_rs1_x0(void){ + // "secureseed0" (Have to copy-paste because csr instr...) + + g_got_illegal_instruction_exception = 0; + + __asm__ volatile( "csrrw x0, 0xBF9, x0" ); + + if (g_got_illegal_instruction_exception == 0) { + printf("error: 'secureseed0' access w/ rs1=x0 should trap\n"); + exit(EXIT_FAILURE); + } + + + // "secureseed1" + + g_got_illegal_instruction_exception = 0; + + __asm__ volatile( "csrrw x0, 0xBFA, x0" ); + + if (g_got_illegal_instruction_exception == 0) { + printf("error: 'secureseed1' access w/ rs1=x0 should trap\n"); + exit(EXIT_FAILURE); + } + + + // "secureseed2" + + g_got_illegal_instruction_exception = 0; + + __asm__ volatile( "csrrw x0, 0xBFC, x0" ); + + if (g_got_illegal_instruction_exception == 0) { + printf("error: 'secureseed2' access w/ rs1=x0 should trap\n"); + exit(EXIT_FAILURE); + } +} + +int main(void) { + test_csr_accesses(); + test_previous_issues(); + test_lfsr_lockup(); + test_secureseed_rs1_x0(); - printf("Test xsecure_csrs done\n"); + printf("Test 'xsecure_csrs' done\n"); return EXIT_SUCCESS; } diff --git a/cv32e40s/tests/programs/custom/zcmt_test/test.yaml b/cv32e40s/tests/programs/custom/zcmt_test/test.yaml new file mode 100644 index 0000000000..5fae51129d --- /dev/null +++ b/cv32e40s/tests/programs/custom/zcmt_test/test.yaml @@ -0,0 +1,7 @@ +name: zcmt_test +uvm_test: uvmt_$(CV_CORE_LC)_firmware_test_c +description: > + zcmt directed test +plusargs: > +cflags: > + -mno-relax diff --git a/cv32e40s/tests/programs/custom/zcmt_test/zcmt_test.c b/cv32e40s/tests/programs/custom/zcmt_test/zcmt_test.c new file mode 100644 index 0000000000..1ae81f0bb1 --- /dev/null +++ b/cv32e40s/tests/programs/custom/zcmt_test/zcmt_test.c @@ -0,0 +1,1744 @@ +// +// Copyright 2022 Silicon Labs, Inc. +// +// Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// https://solderpad.org/licenses/ +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +/////////////////////////////////////////////////////////////////////////////// +// +// Author: Henrik Fegran +// +// zcmt directed test +// +///////////////////////////////////////////////////////////////////////////////// + +#include +#include +#include +#include +#include +#include "bsp.h" +#include "corev_uvmt.h" + +// MUST be 31 or less (bit position-1 in result array determines test pass/fail +// status, thus we are limited to 31 tests with this construct. +#define NUM_TESTS 11 +// Set which test index to start testing at (for quickly running specific tests during development) +#define START_TEST_IDX 0 + + +// __FUNCTION__ is C99 and newer, -Wpedantic flags a warning that +// this is not ISO C, thus we wrap this instatiation in a macro +// ignoring this GCC warning to avoid a long list of warnings during +// compilation. +#define SET_FUNC_INFO \ + _Pragma("GCC diagnostic push") \ + _Pragma("GCC diagnostic ignored \"-Wpedantic\"") \ + const volatile char * const volatile name = __FUNCTION__; \ + _Pragma("GCC diagnostic pop") + + +// --------------------------------------------------------------- +// Convenience macros for bit fields +// --------------------------------------------------------------- +#define MARCHID_CV32E40X 0x14 +#define MARCHID_CV32E40S 0x15 + +#define OPCODE_SYSTEM 0x73 + +#define MSTATEEN0_ADDR 0x30c +#define MSECCFG_ADDR 0x747 +#define PMPCFG0_ADDR 0x3a0 +#define PMPADDR0_ADDR 0x3b0 +#define JVT_ADDR 0x017 + + +// --------------------------------------------------------------- +// Global variables +// --------------------------------------------------------------- +// Print verbosity, consider implementing this as a virtual +// peripheral setting to be controlled from UVM. +volatile verbosity_t global_verbosity = V_LOW; + +volatile uint32_t * volatile g_expect_illegal; +volatile uint32_t * volatile g_expect_tablejmp; +volatile uint32_t * volatile g_csr_instr; +volatile uint32_t * volatile g_csr_instr_rd_val; +volatile uint32_t * volatile g_csr_instr_rs1_val; + +volatile uint32_t * volatile g_recovery_cm_jt; + +extern volatile uint32_t jvt_table; +extern volatile uint32_t recovery_cm_jt_m_0; +extern volatile uint32_t recovery_cm_jt_m_1; +extern volatile uint32_t recovery_cm_jt_m_31; +extern volatile uint32_t recovery_cm_jt_u_0; +extern volatile uint32_t recovery_cm_jt_u_1; +extern volatile uint32_t recovery_cm_jt_u_31; +// --------------------------------------------------------------- +// Test prototypes - should match +// uint32_t (uint32_t index, uint8_t report_name) +// +// Use template below for implementation +// --------------------------------------------------------------- +uint32_t mstateen0_rw_m(uint32_t index, uint8_t report_name); +uint32_t mstateen0_rw_u_illegal(uint32_t index, uint8_t report_name); +uint32_t jvt_rw_m(uint32_t index, uint8_t report_name); +uint32_t jvt_rw_u_illegal(uint32_t index, uint8_t report_name); +uint32_t jvt_rw_u_legal(uint32_t index, uint8_t report_name); +uint32_t cm_jt_m(uint32_t index, uint8_t report_name); +uint32_t cm_jalt_m(uint32_t index, uint8_t report_name); +uint32_t cm_jt_u_illegal(uint32_t index, uint8_t report_name); +uint32_t cm_jalt_u_illegal(uint32_t index, uint8_t report_name); +uint32_t cm_jt_u_legal(uint32_t index, uint8_t report_name); +uint32_t cm_jalt_u_legal(uint32_t index, uint8_t report_name); + +// --------------------------------------------------------------- +// Generic test template: +// --------------------------------------------------------------- +// uint32_t (uint32_t index, uint8_t report_name){ +// volatile uint8_t test_fail = 0; +// /* Test variable instantiation */ +// +// SET_FUNC_INFO +// +// if (report_name) { +// cvprintf(V_LOW, "\"%s\"", name); +// return 0; +// } +// +// /* Insert test code here /* +// +// if (test_fail) { +// cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); +// return index + 1; +// } +// cvprintf(V_MEDIUM, "\nTest: \"%s\" OK!\n", name); +// return 0; +// } +// --------------------------------------------------------------- + +// --------------------------------------------------------------- +// Helper functions +// --------------------------------------------------------------- +/* + * set_test_status + * + * Sets the pass/fail criteria for a given tests and updates + * the 32bit test status variable. + * + * - test_no: current test index + * - val_prev: status vector variable, holding previous test results + */ +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev); + +/* + * get_result + * + * Reports result of self checking tests + * + * - res: result-vector from previously run tests + * - ptr: Pointer to test functions, this is intended to be + * invoked with "report_name == 1" here, as that will + * only print the name of the test and not actually + * run it. + */ +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)); + +/* + * cvprintf + * + * verbosity controlled printf + * use as printf, but with an added verbosity-level setting + * + */ +int cvprintf(verbosity_t verbosity, const char *format, ...); + +/* + * set_mseccfg + * + * Sets up mseccfg with the provided + * mseccfg_t object + */ +void set_mseccfg(mseccfg_t mseccfg); + +/* + * set_pmpcfg + * + * Sets up pmp configuration for a given region + * (defined in pmpcfg_t object) + */ +void set_pmpcfg(pmpsubcfg_t pmpsubcfg, uint32_t reg_no); + +/* + * increment_mepc + * + * Increments mepc, + * incr_val 0 = auto detect + * 2 = halfword + * 4 = word + */ +void increment_mepc(volatile uint32_t incr_val); + +/* + * has_pmp_configured + * + * Returns 1 if pmp is enabled/supported else returns 0 + */ +uint32_t has_pmp_configured(void); + +/* + * Non-standard illegal instruction and ecall handlers + */ +void handle_illegal_insn(void); +void handle_ecall(void); +void handle_ecall_u(void); + +// --------------------------------------------------------------- +// Test entry point +// --------------------------------------------------------------- +int main(int argc, char **argv){ + + volatile uint32_t (* volatile tests[NUM_TESTS])(volatile uint32_t, volatile uint8_t); + + volatile uint32_t test_res = 0x1; + volatile int retval = 0; + + g_expect_illegal = calloc(1, sizeof(uint32_t)); + g_expect_tablejmp = calloc(1, sizeof(uint32_t)); + g_csr_instr = calloc(1, sizeof(uint32_t)); + g_csr_instr_rd_val = calloc(1, sizeof(uint32_t)); + g_csr_instr_rs1_val = calloc(1, sizeof(uint32_t)); + g_recovery_cm_jt = calloc(1, sizeof(uint32_t)); + + // Add function pointers to new tests here + tests[0] = mstateen0_rw_m; + tests[1] = mstateen0_rw_u_illegal; + tests[2] = jvt_rw_m; + tests[3] = jvt_rw_u_illegal; + tests[4] = jvt_rw_u_legal; + tests[5] = cm_jt_m; + tests[6] = cm_jalt_m; + tests[7] = cm_jt_u_illegal; + tests[8] = cm_jalt_u_illegal; + tests[9] = cm_jt_u_legal; + tests[10] = cm_jalt_u_legal; + + // TODO silabs-hfegran: defering these tests to a later PR + //tests[11] = cm_jt_m_trap_m; + //tests[12] = cm_jt_u_trap_u; + //tests[11] = cm_jalt_m_trap; + //tests[12] = cm_jalt_u_trap; + + // Run all tests in list above + cvprintf(V_LOW, "\nZcmt Test start\n\n"); + for (volatile int i = START_TEST_IDX; i < NUM_TESTS; i++) { + test_res = set_test_status(tests[i](i, (volatile uint32_t)(0)), test_res); + } + + // Report failures + retval = get_result(test_res, tests); + + free((void *)g_expect_illegal ); + free((void *)g_csr_instr ); + free((void *)g_csr_instr_rd_val ); + free((void *)g_csr_instr_rs1_val ); + free((void *)g_recovery_cm_jt ); + return retval; // Nonzero for failing tests +} + +// ----------------------------------------------------------------------------- + +int cvprintf(volatile verbosity_t verbosity, const char * volatile format, ...){ + va_list args; + volatile int retval = 0; + + va_start(args, format); + + if (verbosity <= global_verbosity){ + retval = vprintf(format, args); + } + va_end(args); + return retval; +} + +// ----------------------------------------------------------------------------- + +uint32_t set_test_status(uint32_t test_no, uint32_t val_prev){ + volatile uint32_t res; + res = val_prev | (1 << test_no); + return res; +} + +// ----------------------------------------------------------------------------- + +int get_result(uint32_t res, uint32_t (* volatile ptr[])(uint32_t, uint8_t)){ + cvprintf(V_LOW, "=========================\n"); + cvprintf(V_LOW, "= SUMMARY =\n"); + cvprintf(V_LOW, "=========================\n"); + for (int i = START_TEST_IDX; i < NUM_TESTS; i++){ + if ((res >> (i+1)) & 0x1) { + cvprintf (V_LOW, "Test %0d FAIL: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } else { + cvprintf (V_LOW, "Test %0d PASS: ", i); + (void)ptr[i](i, 1); + cvprintf (V_LOW, "\n"); + } + } + if (res == 1) { + cvprintf(V_LOW, "\n\tALL SELF CHECKS PASS!\n\n"); + return 0; + } else { + cvprintf(V_LOW, "\n\tSELF CHECK FAILURES OCCURRED!\n\n"); + return res; + } +} + +// ----------------------------------------------------------------------------- + +uint32_t has_pmp_configured(void) { + volatile uint32_t pmpaddr0 = 0xffffffff; + volatile uint32_t pmpaddr0_backup = 0; + volatile uint32_t marchid = 0x0; + + __asm__ volatile (R"( + csrrs %[marchid], marchid, zero + )":[marchid] "=r"(marchid)); + + // CV32E40X does not support PMP, skip + switch (marchid) { + case (MARCHID_CV32E40X): + return 0; + break; + case (MARCHID_CV32E40S): + ;; // Do nothing and continue execution + break; + } + + __asm__ volatile (R"( + csrrw %[pmpaddr0_backup] , pmpaddr0, %[pmpaddr0] + csrrw %[pmpaddr0], pmpaddr0, %[pmpaddr0_backup] + )" :[pmpaddr0_backup] "+r"(pmpaddr0_backup), + [pmpaddr0] "+r"(pmpaddr0)); + + return (pmpaddr0 != 0); +} + +// ----------------------------------------------------------------------------- + +void set_mseccfg(mseccfg_t mseccfg){ + + __asm__ volatile ( R"( + csrrs x0, mseccfg, %[cfg_vec] + )" + : + : [cfg_vec] "r"(mseccfg.raw) + :); + + cvprintf(V_DEBUG, "Wrote mseccfg: 0x%08lx\n", mseccfg.raw); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) call_word_instr(uint32_t instr_word){ + __asm__ volatile ( R"( + .global ptr_loc + addi sp, sp, -8 + sw a0, 0(sp) + sw s0, 4(sp) + + la s0, ptr_loc + sw a0, 0(s0) + fence.i + # ensure that we have a location to write our pointer + ptr_loc: .word(0x00000000) + + lw s0, 4(sp) + lw a0, 0(sp) + addi sp, sp, 8 + ret + )"); +} + +// ----------------------------------------------------------------------------- + +uint32_t csr_instr(csr_instr_access_t funct3, uint32_t addr, uint32_t rs1_uimm_val) { + volatile csr_instr_t csr_instr = { 0 }; + + *g_csr_instr_rd_val = 0; + *g_csr_instr_rs1_val = rs1_uimm_val; + + switch (funct3) { + case CSRRW: + case CSRRS: + case CSRRC: + csr_instr = (csr_instr_t){ + .fields.opcode = OPCODE_SYSTEM, + .fields.rd = 11, // a1 reg + .fields.funct3 = funct3, + .fields.rs1_uimm = (rs1_uimm_val == 0) ? 0 : 12, // a2 reg unless zero specified + .fields.csr = addr + }; + break; + case CSRRWI: + case CSRRSI: + case CSRRCI: + csr_instr = (csr_instr_t){ + .fields.opcode = OPCODE_SYSTEM, + .fields.rd = 11, // a1 reg + .fields.funct3 = funct3, + .fields.rs1_uimm = rs1_uimm_val, + .fields.csr = addr + }; + break; + default: return 0; + } + + *g_csr_instr = csr_instr.raw; + + __asm__ volatile ( R"( + addi sp, sp, -16 + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + sw ra, 12(sp) + + lw a0, g_csr_instr + lw a0, 0(a0) + lw a2, g_csr_instr_rs1_val + lw a2, 0(a2) + # must ensure that a1 is not some garbage value + add a1, zero, zero + jal ra, call_word_instr + lw a2, g_csr_instr_rd_val + sw a1, 0(a2) + + lw ra, 12(sp) + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 16 + )"); + + return *g_csr_instr_rd_val; +} + +// ----------------------------------------------------------------------------- + +void increment_mepc(volatile uint32_t incr_val) { + volatile uint32_t mepc = 0; + + __asm__ volatile ( R"( + csrrs %[mepc], mepc, zero + )" : [mepc] "=r"(mepc)); + + if (incr_val == 0) { + // No increment specified, check *mepc instruction + if (((*(uint32_t *)mepc) & 0x3UL) == 0x3UL) { + // non-compressed + mepc += 4; + } else { + // compressed + mepc += 2; + } + } else { + // explicitly requested increment + mepc += incr_val; + } + + __asm__ volatile ( R"( + csrrw zero, mepc, %[mepc] + )" :: [mepc] "r"(mepc)); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) handle_ecall(void){ + __asm__ volatile ( R"( + j handle_ecall_u + )"); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) handle_ecall_u(void){ + __asm__ volatile ( R"( + ## handle_ecall_u swaps privilege level, + ## if in M-mode -> mret to U + ## else U-mode -> mret to M + + addi sp, sp, -12 + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + + # Get current priv-mode + csrrs a2, mstatus, zero + + # clear out non-mpp bits and set up a2 to update mpp + lui a1, 2 + addi a1, a1, -2048 + and a2, a2, a1 + + # check if we trapped from U or M-mode + beq a1, a2, 1f + j 2f + + # mpp = M-mode -> U-mode + 1: + csrrc zero, mstatus, a1 + j 3f + + # mpp = U-mode -> M-mode + 2: + csrrs zero, mstatus, a1 + + 3: + # Set 0 as argument for increment_mepc + addi a0, zero, 0 + call increment_mepc + + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 12 + + # return to regular bsp handler flow + j end_handler_ret + + )"); +} + +// ----------------------------------------------------------------------------- + +void __attribute__((naked)) handle_illegal_insn(void) { + __asm__ volatile ( R"( + addi sp, sp, -8 + sw s0, 0(sp) + sw s1, 4(sp) + + # Decrement *g_expect_illegal + lw s0, g_expect_illegal + lw s1, 0(s0) + addi s1, s1, -1 + sw s1, 0(s0) + + lw s1, 4(sp) + lw s0, 0(sp) + addi sp, sp, 8 + + j end_handler_incr_mepc + )"); +} + +// ----------------------------------------------------------------------------- + +void set_pmpcfg(pmpsubcfg_t pmpsubcfg, uint32_t reg_no){ + volatile pmpcfg_t temp = { 0 }; + volatile pmpcfg_t pmpcfg = { 0 }; + + temp.reg_idx[reg_no % 4].cfg = 0xff; + pmpcfg.reg_idx[reg_no % 4].cfg = pmpsubcfg.raw; + + (void)csr_instr(CSRRC, PMPCFG0_ADDR + (reg_no / 4), temp.raw); + (void)csr_instr(CSRRS, PMPCFG0_ADDR + (reg_no / 4), pmpcfg.raw); + + return; +} + +// ----------------------------------------------------------------------------- + +__attribute__((naked)) void jvt_code(void) { + __asm__ volatile ( R"( + .option push + .option norvc + .global jvt_table + .extern jvt_index_1 + .align 6 + jvt_table: + index_0: .word(jvt_index_0) + index_1: .word(jvt_index_1) + .space 116, 0x0 + index_31: .word(jvt_index_31) + index_32: .word(jvt_index_32) + .space 8 + index_35: nop + .space 172, 0x0 + index_79: .word(jvt_index_79) + .space 172, 0x0 + index_123: nop + .space 524, 0x0 + index_255: .word(jvt_index_255) + .option pop + )"); +} + +// ----------------------------------------------------------------------------- + + +__attribute__((optimize("align-functions=4"), naked)) void jvt_index_0(void) { + __asm__ volatile ( R"( + lw a0, g_recovery_cm_jt + lw a0, 0(a0) + jalr zero, 0(a0) + )"); +} + +// ----------------------------------------------------------------------------- + +__attribute__((optimize("align-functions=4"), naked)) void jvt_index_1(void) { + __asm__ volatile ( R"( + addi sp, sp, -8 + sw a0, 0(sp) + sw a1, 4(sp) + + lw a0, g_expect_tablejmp + lw a1, 0(a0) + addi a1, a1, -1 + sw a1, 0(a0) + + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 8 + + lw a0, g_recovery_cm_jt + lw a0, 0(a0) + jalr zero, 0(a0) + + )"); +} + +// ----------------------------------------------------------------------------- + +__attribute__((optimize("align-functions=4"), naked)) void jvt_index_31(void) { + __asm__ volatile ( R"( + addi sp, sp, -8 + sw a0, 0(sp) + sw a1, 4(sp) + + lw a0, g_expect_tablejmp + lw a1, 0(a0) + addi a1, a1, -31 + sw a1, 0(a0) + + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 8 + + lw a0, g_recovery_cm_jt + lw a0, 0(a0) + jalr zero, 0(a0) + + )"); +} + +// ----------------------------------------------------------------------------- + +__attribute__((optimize("align-functions=4"), naked)) void jvt_index_32(void) { + __asm__ volatile ( R"( + addi sp, sp, -8 + sw a0, 0(sp) + sw a1, 4(sp) + + lw a0, g_expect_tablejmp + lw a1, 0(a0) + addi a1, a1, -32 + sw a1, 0(a0) + + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 8 + ret + + )"); +} + +// ----------------------------------------------------------------------------- + +__attribute__((optimize("align-functions=4"), naked)) void jvt_index_79(void) { + __asm__ volatile ( R"( + addi sp, sp, -8 + sw a0, 0(sp) + sw a1, 4(sp) + + lw a0, g_expect_tablejmp + lw a1, 0(a0) + addi a1, a1, -79 + sw a1, 0(a0) + + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 8 + ret + + )"); +} + +// ----------------------------------------------------------------------------- + +__attribute__((optimize("align-functions=4"), naked)) void jvt_index_255(void) { + __asm__ volatile ( R"( + addi sp, sp, -8 + sw a0, 0(sp) + sw a1, 4(sp) + + lw a0, g_expect_tablejmp + lw a1, 0(a0) + addi a1, a1, -255 + sw a1, 0(a0) + + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 8 + ret + + )"); +} + +// ----------------------------------------------------------------------------- + +uint32_t mstateen0_rw_m(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mstateen0_t mstateen0 = { 0 }; + volatile mstateen0_t mstateen0_rval = { 0 }; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // CSRRW 0 + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRW 1 to bit 2 (jvt) + *g_expect_illegal = 0; + mstateen0.fields.jvt_access = 1; + mstateen0_rval.raw = csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + // Read pre-value, should be zero + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRW 0 to bit 2 (jvt) + *g_expect_illegal = 0; + mstateen0.fields.jvt_access = 0; + mstateen0_rval.raw = csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + // Read pre-value, jvt should be one + test_fail += (mstateen0_rval.fields.jvt_access != 1) ? 1 : 0; + mstateen0_rval.fields.jvt_access = 0; + // Check that all others bits were zero (RO bits) + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRW all 1s + *g_expect_illegal = 0; + mstateen0.raw = 0xffffffffUL; + mstateen0_rval.raw = csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + // Check pre-value, all bits should be zero + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRC clear all bits + *g_expect_illegal = 0; + mstateen0.raw = 0xffffffffUL; + mstateen0_rval.raw = csr_instr(CSRRC, MSTATEEN0_ADDR, mstateen0.raw); + // Check pre-value, only bit 2 should be 1 + test_fail += (mstateen0_rval.fields.jvt_access != 1) ? 1 : 0; + mstateen0_rval.fields.jvt_access = 0; + // Remaining bits should be zero + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRS set bit 2 (jvt) + *g_expect_illegal = 0; + mstateen0.raw = 0x0UL; + mstateen0.fields.jvt_access = 1; + mstateen0_rval.raw = csr_instr(CSRRS, MSTATEEN0_ADDR, mstateen0.raw); + // Check pre-value, all bits should be zero + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRC bit 2 (jvt) + *g_expect_illegal = 0; + mstateen0.raw = 0x0UL; + mstateen0.fields.jvt_access = 1; + mstateen0_rval.raw = csr_instr(CSRRC, MSTATEEN0_ADDR, mstateen0.raw); + // Read pre-value, jvt should be one + test_fail += (mstateen0_rval.fields.jvt_access != 1) ? 1 : 0; + mstateen0_rval.fields.jvt_access = 0; + // Check that all others bits were zero (RO bits) + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRS set all bits + *g_expect_illegal = 0; + mstateen0.raw = 0xffffffffUL; + mstateen0_rval.raw = csr_instr(CSRRS, MSTATEEN0_ADDR, mstateen0.raw); + // Check pre-value, all bits should be zero + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI clear bit 2 (jvt) + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x0UL); + // Read pre-value, jvt should be one + test_fail += (mstateen0_rval.fields.jvt_access != 1) ? 1 : 0; + mstateen0_rval.fields.jvt_access = 0; + // Check that all others bits were zero (RO bits) + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI set bit 2 (jvt) + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x4UL); + // Check pre-value, all bits should be zero + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRCI bit 2 (jvt) + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRCI, MSTATEEN0_ADDR, 0x4UL); + // Read pre-value, jvt should be one + test_fail += (mstateen0_rval.fields.jvt_access != 1) ? 1 : 0; + mstateen0_rval.fields.jvt_access = 0; + // Check that all others bits were zero (RO bits) + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI set all lower bits + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x1fUL); + // Check pre-value, all bits should be zero + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI clear all lower bits + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x0UL); + // Read pre-value, jvt should be one + test_fail += (mstateen0_rval.fields.jvt_access != 1) ? 1 : 0; + mstateen0_rval.fields.jvt_access = 0; + // Check that all others bits were zero (RO bits) + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRSI set bit 2 + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRSI, MSTATEEN0_ADDR, 0x4UL); + // Check pre-value, all bits should be zero + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRCI all lower bits + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRCI, MSTATEEN0_ADDR, 0x1fUL); + // Read pre-value, jvt should be one + test_fail += (mstateen0_rval.fields.jvt_access != 1) ? 1 : 0; + mstateen0_rval.fields.jvt_access = 0; + // Check that all others bits were zero (RO bits) + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRSI set all lower bits + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRSI, MSTATEEN0_ADDR, 0x1fUL); + // Check pre-value, all bits should be zero + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRCI bit 2 (jvt) + *g_expect_illegal = 0; + mstateen0_rval.raw = csr_instr(CSRRCI, MSTATEEN0_ADDR, 0x4UL); + // Read pre-value, jvt should be one + test_fail += (mstateen0_rval.fields.jvt_access != 1) ? 1 : 0; + mstateen0_rval.fields.jvt_access = 0; + // Check that all others bits were zero (RO bits) + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t mstateen0_rw_u_illegal(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mseccfg_t mseccfg = { 0 }; + volatile mstateen0_t mstateen0 = { 0 }; + volatile mstateen0_t mstateen0_rval = { 0 }; + volatile uint32_t pmpaddr = 0xffffffffUL; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Enable pmp-access for u-mode *full access for convenience* + mseccfg.fields.rlb = 1; + (void)csr_instr(CSRRW, MSECCFG_ADDR, mseccfg.raw); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + (void)csr_instr(CSRRW, PMPADDR0_ADDR, pmpaddr); + + // Switch to user mode + __asm__ volatile ( R"( ecall )"); + + // CSRRW 0 + *g_expect_illegal = 2; + (void)csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + mstateen0_rval.raw = csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRW 1 to bit 2 (jvt) + *g_expect_illegal = 2; + mstateen0.fields.jvt_access = 1; + (void)csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + mstateen0_rval.raw = csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRW 0 to bit 2 (jvt) + *g_expect_illegal = 2; + mstateen0.fields.jvt_access = 0; + (void)csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + mstateen0_rval.raw = csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRW all 1s + *g_expect_illegal = 2; + mstateen0.raw = 0xffffffffUL; + (void)csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + mstateen0_rval.raw = csr_instr(CSRRW, MSTATEEN0_ADDR, mstateen0.raw); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRC clear all bits + *g_expect_illegal = 2; + mstateen0.raw = 0xffffffffUL; + (void)csr_instr(CSRRC, MSTATEEN0_ADDR, mstateen0.raw); + mstateen0_rval.raw = csr_instr(CSRRC, MSTATEEN0_ADDR, mstateen0.raw); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRS set bit 2 (jvt) + *g_expect_illegal = 2; + mstateen0.raw = 0x0UL; + mstateen0.fields.jvt_access = 1; + (void)csr_instr(CSRRS, MSTATEEN0_ADDR, mstateen0.raw); + mstateen0_rval.raw = csr_instr(CSRRS, MSTATEEN0_ADDR, mstateen0.raw); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRC bit 2 (jvt) + *g_expect_illegal = 2; + mstateen0.raw = 0x0UL; + mstateen0.fields.jvt_access = 1; + (void)csr_instr(CSRRC, MSTATEEN0_ADDR, mstateen0.raw); + mstateen0_rval.raw = csr_instr(CSRRC, MSTATEEN0_ADDR, mstateen0.raw); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRS set all bits + *g_expect_illegal = 2; + mstateen0.raw = 0xffffffffUL; + (void)csr_instr(CSRRS, MSTATEEN0_ADDR, mstateen0.raw); + mstateen0_rval.raw = csr_instr(CSRRS, MSTATEEN0_ADDR, mstateen0.raw); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRWI clear bit 2 (jvt) + *g_expect_illegal = 2; + (void)csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x0UL); + mstateen0_rval.raw = csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x0UL); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRWI set bit 2 (jvt) + *g_expect_illegal = 2; + (void)csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x4UL); + mstateen0_rval.raw = csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x4UL); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRCI bit 2 (jvt) + *g_expect_illegal = 2; + (void)csr_instr(CSRRCI, MSTATEEN0_ADDR, 0x4UL); + mstateen0_rval.raw = csr_instr(CSRRCI, MSTATEEN0_ADDR, 0x4UL); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRWI set all bits + *g_expect_illegal = 2; + (void)csr_instr(CSRRWI, MSTATEEN0_ADDR, 0xfffUL); + mstateen0_rval.raw = csr_instr(CSRRWI, MSTATEEN0_ADDR, 0xfffUL); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRWI clear all bits + *g_expect_illegal = 2; + (void)csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x0UL); + mstateen0_rval.raw = csr_instr(CSRRWI, MSTATEEN0_ADDR, 0x0UL); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRSI set bit 2 + *g_expect_illegal = 2; + (void)csr_instr(CSRRSI, MSTATEEN0_ADDR, 0x4UL); + mstateen0_rval.raw = csr_instr(CSRRSI, MSTATEEN0_ADDR, 0x4UL); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRCI all lower bits + *g_expect_illegal = 2; + (void)csr_instr(CSRRCI, MSTATEEN0_ADDR, 0x1fUL); + mstateen0_rval.raw = csr_instr(CSRRCI, MSTATEEN0_ADDR, 0x1fUL); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRSI set all lower bits + *g_expect_illegal = 2; + (void)csr_instr(CSRRSI, MSTATEEN0_ADDR, 0x1fUL); + mstateen0_rval.raw = csr_instr(CSRRSI, MSTATEEN0_ADDR, 0x1fUL); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + // CSRRCI bit 2 (jvt) + *g_expect_illegal = 2; + (void)csr_instr(CSRRCI, MSTATEEN0_ADDR, 0x4UL); + mstateen0_rval.raw = csr_instr(CSRRCI, MSTATEEN0_ADDR, 0x4UL); + test_fail += (mstateen0_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + assert(!test_fail); + + + // Switch back to machine mode + __asm__ volatile ( R"( ecall )"); + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t jvt_rw_m(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile jvt_t jvt = { 0 }; + volatile jvt_t jvt_rval = { 0 }; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // CSRRW 0 + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRW, JVT_ADDR, jvt.raw); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRW all 1s + *g_expect_illegal = 0; + jvt.raw = 0xffffffffUL; + jvt_rval.raw = csr_instr(CSRRW, JVT_ADDR, jvt.raw); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.fields.mode != 0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRC clear all bits + *g_expect_illegal = 0; + jvt.raw = 0xffffffffUL; + jvt_rval.raw = csr_instr(CSRRC, JVT_ADDR, jvt.raw); + // Check pre-value, should be all 1s + test_fail += (jvt_rval.fields.mode != 0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x3ffffffUL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRS set all bits + *g_expect_illegal = 0; + jvt.raw = 0xffffffffUL; + jvt_rval.raw = csr_instr(CSRRS, JVT_ADDR, jvt.raw); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.fields.mode != 0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI clear all bits + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRWI, JVT_ADDR, 0x0UL); + // Read pre-value, all bits should be 1 + test_fail += (jvt_rval.fields.mode != 0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x3ffffffUL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI set all lower bits + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRWI, JVT_ADDR, 0x1fUL); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.fields.mode != 0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRCI clear all lower bits + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRCI, JVT_ADDR, 0x1fUL); + // Read pre-value, all bits should be 1 + test_fail += (jvt_rval.fields.mode != 0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRSI set all lower bits + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRWI, JVT_ADDR, 0x1fUL); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.fields.mode != 0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI clear all + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRWI, JVT_ADDR, 0x0UL); + // Read pre-value, all bits should be 1 + test_fail += (jvt_rval.fields.mode != 0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t jvt_rw_u_illegal(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mseccfg_t mseccfg = { 0 }; + volatile uint32_t jvt_rval = 0UL; + volatile uint32_t jvt = 0UL; + volatile uint32_t pmpaddr = 0xffffffffUL; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Enable pmp-access for u-mode *full access for convenience* + mseccfg.fields.rlb = 1; + (void)csr_instr(CSRRW, MSECCFG_ADDR, mseccfg.raw); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + (void)csr_instr(CSRRW, PMPADDR0_ADDR, pmpaddr); + + // Switch to user mode + __asm__ volatile ( R"( ecall )"); + + // CSRRW 0 + *g_expect_illegal = 2; + jvt_rval = csr_instr(CSRRW, JVT_ADDR, jvt); + (void)csr_instr(CSRRW, JVT_ADDR, jvt); + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRW all 1s + *g_expect_illegal = 2; + jvt = 0xffffffffUL; + jvt_rval = csr_instr(CSRRW, JVT_ADDR, jvt); + (void)csr_instr(CSRRW, JVT_ADDR, jvt); + test_fail += (jvt_rval != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRC clear all bits + *g_expect_illegal = 2; + jvt = 0xffffffffUL; + jvt_rval = csr_instr(CSRRC, JVT_ADDR, jvt); + (void)csr_instr(CSRRC, JVT_ADDR, jvt); + test_fail += (jvt_rval != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRS set all bits + *g_expect_illegal = 2; + jvt = 0xffffffffUL; + jvt_rval = csr_instr(CSRRS, JVT_ADDR, jvt); + (void)csr_instr(CSRRS, JVT_ADDR, jvt); + test_fail += (jvt_rval != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI clear all bits + *g_expect_illegal = 2; + jvt_rval = csr_instr(CSRRWI, JVT_ADDR, 0x0UL); + (void)csr_instr(CSRRWI, JVT_ADDR, 0x0UL); + test_fail += (jvt_rval != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI set all lower bits + *g_expect_illegal = 2; + jvt_rval = csr_instr(CSRRWI, JVT_ADDR, 0xfffUL); + (void)csr_instr(CSRRWI, JVT_ADDR, 0xfffUL); + test_fail += (jvt_rval != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRCI clear all lower bits + *g_expect_illegal = 2; + jvt_rval = csr_instr(CSRRCI, JVT_ADDR, 0xfffUL); + (void)csr_instr(CSRRCI, JVT_ADDR, 0xfffUL); + test_fail += (jvt_rval != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRSI set all lower bits + *g_expect_illegal = 2; + jvt_rval = csr_instr(CSRRWI, JVT_ADDR, 0xfffUL); + (void)csr_instr(CSRRWI, JVT_ADDR, 0xfffUL); + test_fail += (jvt_rval != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI clear all + *g_expect_illegal = 2; + jvt_rval = csr_instr(CSRRWI, JVT_ADDR, 0x0UL); + (void)csr_instr(CSRRWI, JVT_ADDR, 0x0UL); + test_fail += (jvt_rval != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // Switch back to machine mode + __asm__ volatile ( R"( ecall )"); + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t jvt_rw_u_legal(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mseccfg_t mseccfg = { 0 }; + volatile jvt_t jvt_rval = { 0 }; + volatile jvt_t jvt = { 0 }; + volatile mstateen0_t mstateen0 = { 0 }; + volatile uint32_t pmpaddr = 0xffffffffUL; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Enable pmp-access for u-mode *full access for convenience* + mseccfg.fields.rlb = 1; + (void)csr_instr(CSRRW, MSECCFG_ADDR, mseccfg.raw); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + (void)csr_instr(CSRRW, PMPADDR0_ADDR, pmpaddr); + + mstateen0.fields.jvt_access = 1; + (void)csr_instr(CSRRS, MSTATEEN0_ADDR, mstateen0.raw); + + // Switch to user mode + __asm__ volatile ( R"( ecall )"); + + // CSRRW jvt_t + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRW, JVT_ADDR, jvt.raw); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRW all 1s + *g_expect_illegal = 0; + jvt.raw = 0xffffffffUL; + jvt_rval.raw = csr_instr(CSRRW, JVT_ADDR, jvt.raw); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRC clear all bits + *g_expect_illegal = 0; + jvt.raw = 0xffffffffUL; + jvt_rval.raw = csr_instr(CSRRC, JVT_ADDR, jvt.raw); + // Check pre-value, should be all 1s + test_fail += (jvt_rval.fields.mode != 0x0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x3ffffffUL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRS set all bits + *g_expect_illegal = 0; + jvt.raw = 0xffffffffUL; + jvt_rval.raw = csr_instr(CSRRS, JVT_ADDR, jvt.raw); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.raw != 0) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI clear all + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRWI, JVT_ADDR, 0x0UL); + // Read pre-value, all bits should be 1 + test_fail += (jvt_rval.fields.mode != 0x0) ? 1 : 0; + test_fail += (jvt_rval.fields.base != 0x3ffffffUL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI set all lower bits + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRWI, JVT_ADDR, 0x1fUL); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.raw != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRCI clear all lower bits + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRCI, JVT_ADDR, 0x1fUL); + // Read pre-value, all bits should be 0 due to RO .mode + test_fail += (jvt_rval.raw != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRSI set all bits + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRWI, JVT_ADDR, 0x1fUL); + // Check pre-value, all bits should be zero + test_fail += (jvt_rval.raw != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // CSRRWI clear all + *g_expect_illegal = 0; + jvt_rval.raw = csr_instr(CSRRWI, JVT_ADDR, 0x0UL); + // Read pre-value, all bits should be 0 due to RO .mode + test_fail += (jvt_rval.raw != 0x0UL) ? 1 : 0; + test_fail += (*g_expect_illegal != 0) ? 1 : 0; + + // Switch back to machine mode + __asm__ volatile ( R"( ecall )"); + + mstateen0.fields.jvt_access = 1; + (void)csr_instr(CSRRC, MSTATEEN0_ADDR, mstateen0.raw); + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t cm_jt_m(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + (void)csr_instr(CSRRW, JVT_ADDR, ((uint32_t)&jvt_table)); + + *g_expect_tablejmp = 1 + 31; + __asm__ volatile ( R"( + .global recovery_cm_jt_m_0 + .global recovery_cm_jt_m_1 + .global recovery_cm_jt_m_31 + addi sp, sp, -12 + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + + lw a0, g_recovery_cm_jt + la a1, recovery_cm_jt_m_0 + sw a1, 0(a0) + + cm.jt 0 + recovery_cm_jt_m_0: + + lw a0, g_recovery_cm_jt + la a1, recovery_cm_jt_m_1 + sw a1, 0(a0) + + cm.jt 1 + recovery_cm_jt_m_1: + + lw a0, g_recovery_cm_jt + la a1, recovery_cm_jt_m_31 + sw a1, 0(a0) + + cm.jt 31 + recovery_cm_jt_m_31: + + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 12 + )" ::: "ra", "memory"); + + test_fail += (*g_expect_tablejmp != 0) ? 1 : 0; + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t cm_jalt_m(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + (void)csr_instr(CSRRW, JVT_ADDR, ((uint32_t)&jvt_table)); + *g_expect_tablejmp = 32 + 79 + 255; + + __asm__ volatile ( R"( + cm.jalt 32 + cm.jalt 79 + cm.jalt 255 + )" ::: "ra", "memory"); + + test_fail += (*g_expect_tablejmp != 0) ? 1 : 0; + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t cm_jt_u_illegal(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mseccfg_t mseccfg = { 0 }; + volatile uint32_t pmpaddr = 0xffffffffUL; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Enable pmp-access for u-mode *full access for convenience* + mseccfg.fields.rlb = 1; + (void)csr_instr(CSRRW, MSECCFG_ADDR, mseccfg.raw); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + (void)csr_instr(CSRRW, PMPADDR0_ADDR, pmpaddr); + + (void)csr_instr(CSRRW, JVT_ADDR, ((uint32_t)&jvt_table)); + *g_expect_tablejmp = 0; + + __asm__ volatile ( R"( + ecall + cm.jt 0 + cm.jt 1 + cm.jt 15 + cm.jt 16 + cm.jt 30 + cm.jt 31 + ecall + )" ::: "ra", "memory"); + + test_fail += (*g_expect_tablejmp != 0) ? 1 : 0; + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- +uint32_t cm_jalt_u_illegal(uint32_t index, uint8_t report_name) { + volatile uint8_t test_fail = 0; + volatile mseccfg_t mseccfg = { 0 }; + volatile uint32_t pmpaddr = 0xffffffffUL; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Enable pmp-access for u-mode *full access for convenience* + mseccfg.fields.rlb = 1; + (void)csr_instr(CSRRW, MSECCFG_ADDR, mseccfg.raw); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + (void)csr_instr(CSRRW, PMPADDR0_ADDR, pmpaddr); + + (void)csr_instr(CSRRW, JVT_ADDR, ((uint32_t)&jvt_table)); + *g_expect_tablejmp = 0; + + __asm__ volatile ( R"( + ecall + cm.jalt 32 + cm.jalt 33 + cm.jalt 127 + cm.jalt 128 + cm.jalt 254 + cm.jalt 255 + ecall + )" ::: "ra", "memory"); + + test_fail += (*g_expect_tablejmp != 0) ? 1 : 0; + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t cm_jt_u_legal(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mseccfg_t mseccfg = { 0 }; + volatile mstateen0_t mstateen0 = { 0 }; + volatile uint32_t pmpaddr = 0xffffffffUL; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + // Enable pmp-access for u-mode *full access for convenience* + mseccfg.fields.rlb = 1; + (void)csr_instr(CSRRW, MSECCFG_ADDR, mseccfg.raw); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + (void)csr_instr(CSRRW, PMPADDR0_ADDR, pmpaddr); + + mstateen0.fields.jvt_access = 1; + (void)csr_instr(CSRRS, MSTATEEN0_ADDR, mstateen0.raw); + + (void)csr_instr(CSRRW, JVT_ADDR, ((uint32_t)&jvt_table)); + + *g_expect_tablejmp = 0 + 1 + 31; + + __asm__ volatile ( R"( + .global recovery_cm_jt_u_0 + .global recovery_cm_jt_u_1 + .global recovery_cm_jt_u_31 + ecall + addi sp, sp, -12 + sw a0, 0(sp) + sw a1, 4(sp) + sw a2, 8(sp) + + lw a0, g_recovery_cm_jt + la a1, recovery_cm_jt_u_0 + sw a1, 0(a0) + + cm.jt 0 + recovery_cm_jt_u_0: + + lw a0, g_recovery_cm_jt + la a1, recovery_cm_jt_u_1 + sw a1, 0(a0) + + cm.jt 1 + recovery_cm_jt_u_1: + + lw a0, g_recovery_cm_jt + la a1, recovery_cm_jt_u_31 + sw a1, 0(a0) + + cm.jt 31 + recovery_cm_jt_u_31: + + lw a2, 8(sp) + lw a1, 4(sp) + lw a0, 0(sp) + addi sp, sp, 12 + ecall + )" ::: "ra", "memory"); + + mstateen0.fields.jvt_access = 1; + (void)csr_instr(CSRRC, MSTATEEN0_ADDR, mstateen0.raw); + + test_fail += (*g_expect_tablejmp != 0) ? 1 : 0; + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + +// ----------------------------------------------------------------------------- + +uint32_t cm_jalt_u_legal(uint32_t index, uint8_t report_name){ + volatile uint8_t test_fail = 0; + volatile mseccfg_t mseccfg = { 0 }; + volatile mstateen0_t mstateen0 = { 0 }; + volatile uint32_t pmpaddr = 0xffffffffUL; + + SET_FUNC_INFO + + if (report_name) { + cvprintf(V_LOW, "\"%s\"", name); + return 0; + } + + // Enable pmp-access for u-mode *full access for convenience* + mseccfg.fields.rlb = 1; + (void)csr_instr(CSRRW, MSECCFG_ADDR, mseccfg.raw); + + set_pmpcfg((pmpsubcfg_t){ + .fields.r = 1, + .fields.w = 1, + .fields.x = 1, + .fields.a = PMPMODE_TOR, + .fields.l = 0 + }, 0); + + (void)csr_instr(CSRRW, PMPADDR0_ADDR, pmpaddr); + + mstateen0.fields.jvt_access = 1; + (void)csr_instr(CSRRS, MSTATEEN0_ADDR, mstateen0.raw); + + (void)csr_instr(CSRRW, JVT_ADDR, ((uint32_t)&jvt_table)); + + *g_expect_tablejmp = 32 + 79 + 255; + + __asm__ volatile ( R"( + ecall + cm.jalt 32 + cm.jalt 79 + cm.jalt 255 + ecall + )" ::: "ra", "memory"); + + mstateen0.fields.jvt_access = 1; + (void)csr_instr(CSRRC, MSTATEEN0_ADDR, mstateen0.raw); + + test_fail += (*g_expect_tablejmp != 0) ? 1 : 0; + + if (test_fail) { + // Should never be here in this test case unless something goes really wrong + cvprintf(V_LOW, "\nTest: \"%s\" FAIL!\n", name); + return index + 1; + } + cvprintf(V_MEDIUM, "\nTest: \"%s\" No self checking in this test, OK!\n", name); + return 0; +} + diff --git a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_constants.sv b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_constants.sv index fdcfa1b4b6..2feb828cc4 100644 --- a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_constants.sv +++ b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_constants.sv @@ -173,9 +173,9 @@ parameter logic CLIC = CORE_PARAM_CLIC; parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR1_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h80000062, default_seed : 32'hbeef1234 }; parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR2_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h8000007a, default_seed : 32'ha5a5a5a5 }; `else - parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR0_CFG = cv32e40s_pkg::LFSR_CFG_DEFAULT; - parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR1_CFG = cv32e40s_pkg::LFSR_CFG_DEFAULT; - parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR2_CFG = cv32e40s_pkg::LFSR_CFG_DEFAULT; + parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR0_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h80000057, default_seed : 32'habbacafe }; + parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR1_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h80000062, default_seed : 32'hbeef1234 }; + parameter cv32e40s_pkg::lfsr_cfg_t CORE_PARAM_LFSR2_CFG = cv32e40s_pkg::lfsr_cfg_t'{ coeffs : 32'h8000007a, default_seed : 32'ha5a5a5a5 }; `endif diff --git a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_tdefs.sv b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_tdefs.sv index ba160bed8c..e64405f7f3 100644 --- a/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_tdefs.sv +++ b/cv32e40s/tests/uvmt/base-tests/uvmt_cv32e40s_base_test_tdefs.sv @@ -126,5 +126,17 @@ typedef struct packed { logic accesses_jvt; } pma_status_t; +typedef struct packed { + obi_data_req_t req; + obi_data_resp_t resp; + logic valid; +} obi_data_packet_t; + +typedef struct packed { + obi_inst_req_t req; + obi_inst_resp_t resp; + logic valid; +} obi_instr_packet_t; + `endif // __UVMT_CV32E40S_BASE_TEST_TDEFS_SV__ diff --git a/lib/isa_decoder/isa_decoder.sv b/lib/isa_decoder/isa_decoder.sv index cdc2030e73..1a0b0d593b 100644 --- a/lib/isa_decoder/isa_decoder.sv +++ b/lib/isa_decoder/isa_decoder.sv @@ -23,7 +23,7 @@ // --------------------------------------------------------------------------- // Stack_adj for zcmp instructions // --------------------------------------------------------------------------- - function int get_stack_adj( rlist_t rlist, logic[5:4] spimm); + function automatic int get_stack_adj( rlist_t rlist, logic[5:4] spimm); int stack_adj_base; int stack_adj; @@ -43,7 +43,7 @@ // --------------------------------------------------------------------------- // Non-trivial immediate decoder // --------------------------------------------------------------------------- - function logic [20:1] get_sort_j_imm(instr_t instr); + function automatic logic [20:1] get_sort_j_imm(instr_t instr); get_sort_j_imm = { instr.uncompressed.format.j.imm[31], instr.uncompressed.format.j.imm[21:12], @@ -52,14 +52,14 @@ }; endfunction : get_sort_j_imm - function logic [11:0] get_sort_s_imm(instr_t instr); + function automatic logic [11:0] get_sort_s_imm(instr_t instr); get_sort_s_imm = { instr.uncompressed.format.s.imm_h, instr.uncompressed.format.s.imm_l }; endfunction : get_sort_s_imm - function logic [12:1] get_sort_b_imm(instr_t instr); + function automatic logic [12:1] get_sort_b_imm(instr_t instr); get_sort_b_imm = { instr.uncompressed.format.b.imm_h[31], instr.uncompressed.format.b.imm_l[7], @@ -68,7 +68,7 @@ }; endfunction : get_sort_b_imm - function logic [5:0] get_sort_ci_imm_lwsp(instr_t instr); + function automatic logic [5:0] get_sort_ci_imm_lwsp(instr_t instr); get_sort_ci_imm_lwsp = { instr.compressed.format.ci.imm_6_2[3:2], instr.compressed.format.ci.imm_12, @@ -76,7 +76,7 @@ }; endfunction : get_sort_ci_imm_lwsp - function logic [5:0] get_sort_ci_imm_addi16sp(instr_t instr); + function automatic logic [5:0] get_sort_ci_imm_addi16sp(instr_t instr); get_sort_ci_imm_addi16sp = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2[4:3], @@ -86,7 +86,7 @@ }; endfunction : get_sort_ci_imm_addi16sp - function logic [8:0] get_sort_cb_imm_not_sequential(instr_t instr); + function automatic logic [7:0] get_sort_cb_imm_not_sequential(instr_t instr); get_sort_cb_imm_not_sequential = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2[6:5], @@ -96,7 +96,7 @@ }; endfunction : get_sort_cb_imm_not_sequential - function logic [5:0] get_sort_cj_imm(instr_t instr); + function automatic logic [10:0] get_sort_cj_imm(instr_t instr); get_sort_cj_imm = { instr.compressed.format.cj.imm[12], instr.compressed.format.cj.imm[8], @@ -109,7 +109,7 @@ }; endfunction : get_sort_cj_imm - function logic [4:0] get_sort_cl_imm(instr_t instr); + function automatic logic [4:0] get_sort_cl_imm(instr_t instr); get_sort_cl_imm = { instr.compressed.format.cl.imm_6_5[5], instr.compressed.format.cl.imm_12_10, @@ -117,7 +117,7 @@ }; endfunction : get_sort_cl_imm - function logic [4:0] get_sort_cs_imm(instr_t instr); + function automatic logic [4:0] get_sort_cs_imm(instr_t instr); get_sort_cs_imm = { instr.compressed.format.cs.imm_6_5[5], instr.compressed.format.cs.imm_12_10, @@ -125,7 +125,7 @@ }; endfunction : get_sort_cs_imm - function logic [7:0] get_sort_ciw_imm(instr_t instr); + function automatic logic [7:0] get_sort_ciw_imm(instr_t instr); get_sort_ciw_imm = { instr.compressed.format.ciw.imm[10:7], instr.compressed.format.ciw.imm[12:11], @@ -134,10 +134,27 @@ }; endfunction : get_sort_ciw_imm + function automatic gpr_t get_gpr_from_gpr_rvc(gpr_rvc_t gpr); + gpr_t uncompressed_gpr; + casex (gpr.gpr) + C_X8: uncompressed_gpr.gpr = X8; + C_X9: uncompressed_gpr.gpr = X9; + C_X10: uncompressed_gpr.gpr = X10; + C_X11: uncompressed_gpr.gpr = X11; + C_X12: uncompressed_gpr.gpr = X12; + C_X13: uncompressed_gpr.gpr = X13; + C_X14: uncompressed_gpr.gpr = X14; + C_X15: uncompressed_gpr.gpr = X15; + default: uncompressed_gpr.gpr = X0; // Function used wrong if we ever end up here + endcase + + return uncompressed_gpr; + endfunction : get_gpr_from_gpr_rvc + // --------------------------------------------------------------------------- // Find the value of immediate // --------------------------------------------------------------------------- - function int get_imm_value_i(logic[11:0] imm); + function automatic int get_imm_value_i(logic[11:0] imm); if(imm[11] == 1) begin get_imm_value_i = {20'hfffff, imm}; end else begin @@ -145,7 +162,7 @@ end endfunction : get_imm_value_i - function int get_imm_value_j(logic[20:1] imm); + function automatic int get_imm_value_j(logic[20:1] imm); if(imm[20] == 1) begin get_imm_value_j = {11'h7ff, imm, 1'b0}; end else begin @@ -153,7 +170,7 @@ end endfunction : get_imm_value_j - function int get_imm_value_b(logic[12:1] imm); + function automatic int get_imm_value_b(logic[12:1] imm); if(imm[12] == 1) begin get_imm_value_b = {19'h7ffff, imm, 1'b0}; end else begin @@ -161,7 +178,7 @@ end endfunction : get_imm_value_b - function int get_imm_value_ci(logic[5:0] imm); + function automatic int get_imm_value_ci(logic[5:0] imm); if(imm[5] == 1) begin get_imm_value_ci = {26'h3ffffff, imm}; end else begin @@ -169,7 +186,7 @@ end endfunction : get_imm_value_ci - function int get_imm_value_ci_lui(logic[17:12] imm); + function automatic int get_imm_value_ci_lui(logic[17:12] imm); if(imm[17] == 1) begin get_imm_value_ci_lui = {14'h3fff, imm, 12'b0}; end else begin @@ -177,7 +194,7 @@ end endfunction : get_imm_value_ci_lui - function int get_imm_value_ci_addi16sp(logic[9:4] imm); + function automatic int get_imm_value_ci_addi16sp(logic[9:4] imm); if(imm[9] == 1) begin get_imm_value_ci_addi16sp = {22'h3fffff, imm, 4'b0}; end else begin @@ -185,7 +202,7 @@ end endfunction : get_imm_value_ci_addi16sp - function int get_imm_value_cb(logic[8:1] imm); + function automatic int get_imm_value_cb(logic[8:1] imm); if(imm[8] == 1) begin get_imm_value_cb = {23'h7fffff, imm, 1'b0}; end else begin @@ -193,7 +210,7 @@ end endfunction : get_imm_value_cb - function int get_imm_value_cj(logic[11:1] imm); + function automatic int get_imm_value_cj(logic[11:1] imm); if(imm[11] == 1) begin get_imm_value_cj = {20'hfffff, imm, 1'b0}; end else begin @@ -203,7 +220,7 @@ // Get the correspopnding name of the hint instruction - function hint_name_e get_hint_name(instr_name_e name); + function automatic hint_name_e get_hint_name(instr_name_e name); hint_name_e hint_name; casex(name) @@ -234,7 +251,7 @@ endfunction // Find out if the instruction is a HINT. - function logic check_if_hint(instr_name_e name, instr_format_e format, instr_t instr); + function automatic logic check_if_hint(instr_name_e name, instr_format_e format, instr_t instr); logic hint; casex (get_hint_name(name)) @@ -265,7 +282,7 @@ endfunction - function logic[11:0] read_s_imm(logic[31:0] instr); + function automatic logic[11:0] read_s_imm(logic[31:0] instr); automatic logic [11:0] imm; imm = {instr[31:25], instr[11:7]}; return imm; @@ -293,11 +310,11 @@ casex (format) I_TYPE: begin - if (asm.instr inside { FENCEI, ECALL, EBREAK, MRET, DRET, WFI, WFE }) begin - asm.rd.valid = 0; - asm.rs1.valid = 0; - asm.rs2.valid = 0; - asm.imm.valid = 0; + if (asm.instr inside { FENCE_I, ECALL, EBREAK, MRET, DRET, WFI, WFE }) begin + asm.rd.valid = 0; + asm.rs1.valid = 0; + asm.rs2.valid = 0; + asm.imm.valid = 0; end else if (asm.instr inside { FENCE }) begin asm.imm.imm_raw = instr.uncompressed.format.i.imm; asm.imm.imm_raw_sorted = instr.uncompressed.format.i.imm; @@ -307,12 +324,12 @@ asm.imm.imm_value = get_imm_value_i(instr.uncompressed.format.i.imm); asm.imm.valid = 1; end else if (asm.instr inside { CSRRW, CSRRS, CSRRC }) begin - asm.rd.gpr = instr.uncompressed.format.i.rd.gpr; - asm.rs1.gpr = instr.uncompressed.format.i.rs1.gpr; - asm.csr.address = instr.uncompressed.format.i.imm; - asm.rd.valid = 1; - asm.rs1.valid = 1; - asm.csr.valid = 1; + asm.rd.gpr = instr.uncompressed.format.i.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.i.rs1.gpr; + asm.csr.address = instr.uncompressed.format.i.imm; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.csr.valid = 1; end else if (asm.instr inside { CSRRWI, CSRRSI, CSRRCI }) begin asm.rd.gpr = instr.uncompressed.format.i.rd.gpr; asm.imm.imm_raw = instr.uncompressed.format.i.rs1; @@ -350,109 +367,109 @@ end end J_TYPE: begin - asm.rd.gpr = instr.uncompressed.format.j.rd.gpr; - asm.imm.imm_raw = instr.uncompressed.format.j.imm; - asm.imm.imm_raw_sorted = get_sort_j_imm(instr); - asm.imm.imm_type = OFFSET; - asm.imm.width = 20; - asm.imm.sign_ext = 1; - asm.imm.imm_value = get_imm_value_j(get_sort_j_imm(instr)); - asm.rd.valid = 1; - asm.imm.valid = 1; + asm.rd.gpr = instr.uncompressed.format.j.rd.gpr; + asm.imm.imm_raw = instr.uncompressed.format.j.imm; + asm.imm.imm_raw_sorted = get_sort_j_imm(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 20; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_j(get_sort_j_imm(instr)); + asm.rd.valid = 1; + asm.imm.valid = 1; end S_TYPE: begin - asm.rs1.gpr = instr.uncompressed.format.s.rs1.gpr; - asm.rs2.gpr = instr.uncompressed.format.s.rs2.gpr; - asm.imm.imm_raw = get_sort_s_imm(instr); - asm.imm.imm_raw_sorted = get_sort_s_imm(instr); - asm.imm.imm_type = IMM; - asm.imm.width = 12; - asm.imm.sign_ext = 1; - asm.imm.imm_value = get_imm_value_i(get_sort_s_imm(instr)); - asm.rs1.valid = 1; - asm.rs2.valid = 1; - asm.imm.valid = 1; + asm.rs1.gpr = instr.uncompressed.format.s.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.s.rs2.gpr; + asm.imm.imm_raw = get_sort_s_imm(instr); + asm.imm.imm_raw_sorted = get_sort_s_imm(instr); + asm.imm.imm_type = IMM; + asm.imm.width = 12; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_i(get_sort_s_imm(instr)); + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.imm.valid = 1; end R_TYPE: begin if ( asm.instr inside { LR_W, SC_W, AMOSWAP_W, AMOADD_W, AMOXOR_W, AMOAND_W, AMOOR_W, AMOMIN_W, AMOMAX_W, AMOMINU_W, AMOMAXU_W } ) begin - asm.rd.gpr = instr.uncompressed.format.r.rd.gpr; - asm.rs1.gpr = instr.uncompressed.format.r.rs1.gpr; - asm.rs2.gpr = instr.uncompressed.format.r.rs2.gpr; - asm.atomic.aq = instr.uncompressed.format.r.funct7[26]; - asm.atomic.rl = instr.uncompressed.format.r.funct7[25]; - asm.rd.valid = 1; - asm.rs1.valid = 1; - asm.rs2.valid = 1; - asm.atomic.valid = 1; + asm.rd.gpr = instr.uncompressed.format.r.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.r.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.r.rs2.gpr; + asm.atomic.aq = instr.uncompressed.format.r.funct7[26]; + asm.atomic.rl = instr.uncompressed.format.r.funct7[25]; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.atomic.valid = 1; end else begin - asm.rd.gpr = instr.uncompressed.format.r.rd.gpr; - asm.rs1.gpr = instr.uncompressed.format.r.rs1.gpr; - asm.rs2.gpr = instr.uncompressed.format.r.rs2.gpr; - asm.rd.valid = 1; - asm.rs1.valid = 1; - asm.rs2.valid = 1; + asm.rd.gpr = instr.uncompressed.format.r.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.r.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.r.rs2.gpr; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.rs2.valid = 1; end end R4_TYPE: begin - asm.rd.gpr = instr.uncompressed.format.r4.rd.gpr; - asm.rs1.gpr = instr.uncompressed.format.r4.rs1.gpr; - asm.rs2.gpr = instr.uncompressed.format.r4.rs2.gpr; - asm.rs3.gpr = instr.uncompressed.format.r4.rs3.gpr; - asm.rd.valid = 1; - asm.rs1.valid = 1; - asm.rs2.valid = 1; - asm.rs3.valid = 1; + asm.rd.gpr = instr.uncompressed.format.r4.rd.gpr; + asm.rs1.gpr = instr.uncompressed.format.r4.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.r4.rs2.gpr; + asm.rs3.gpr = instr.uncompressed.format.r4.rs3.gpr; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.rs3.valid = 1; end B_TYPE: begin - asm.rs1.gpr = instr.uncompressed.format.b.rs1.gpr; - asm.rs2.gpr = instr.uncompressed.format.b.rs2.gpr; - asm.imm.imm_raw = {instr.uncompressed.format.b.imm_h, instr.uncompressed.format.b.imm_l}; - asm.imm.imm_raw_sorted = get_sort_b_imm(instr); - asm.imm.imm_type = IMM; - asm.imm.width = 12; - asm.imm.sign_ext = 1; - asm.imm.imm_value = get_imm_value_b(get_sort_b_imm(instr)); - asm.rs1.valid = 1; - asm.rs2.valid = 1; - asm.imm.valid = 1; + asm.rs1.gpr = instr.uncompressed.format.b.rs1.gpr; + asm.rs2.gpr = instr.uncompressed.format.b.rs2.gpr; + asm.imm.imm_raw = {instr.uncompressed.format.b.imm_h, instr.uncompressed.format.b.imm_l}; + asm.imm.imm_raw_sorted = get_sort_b_imm(instr); + asm.imm.imm_type = IMM; + asm.imm.width = 12; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_b(get_sort_b_imm(instr)); + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.imm.valid = 1; end U_TYPE: begin - asm.rd.gpr = instr.uncompressed.format.u.rd.gpr; - asm.imm.imm_raw = instr.uncompressed.format.u.imm; - asm.imm.imm_raw_sorted = instr.uncompressed.format.u.imm; - asm.imm.imm_type = IMM; - asm.imm.width = 20; - asm.imm.imm_value = { instr.uncompressed.format.u.imm, 12'b0000_0000_0000 }; - asm.rd.valid = 1; - asm.imm.valid = 1; + asm.rd.gpr = instr.uncompressed.format.u.rd.gpr; + asm.imm.imm_raw = instr.uncompressed.format.u.imm; + asm.imm.imm_raw_sorted = instr.uncompressed.format.u.imm; + asm.imm.imm_type = IMM; + asm.imm.width = 20; + asm.imm.imm_value = { instr.uncompressed.format.u.imm, 12'b0000_0000_0000 }; + asm.rd.valid = 1; + asm.imm.valid = 1; end // Compressed CR_TYPE: begin if (name inside { C_EBREAK }) begin - asm.rd.valid = 0; - asm.rs1.valid = 0; - asm.rs2.valid = 0; - asm.rs3.valid = 0; - asm.imm.valid = 0; + asm.rd.valid = 0; + asm.rs1.valid = 0; + asm.rs2.valid = 0; + asm.rs3.valid = 0; + asm.imm.valid = 0; end else if (name inside { C_MV }) begin - asm.rd.gpr = instr.compressed.format.cr.rd_rs1.gpr; - asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr; - asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr; - asm.rd.valid = 1; - asm.rs2.valid = 1; - asm.rs1.valid = 1; + asm.rd.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr; + asm.rd.valid = 1; + asm.rs2.valid = 1; + asm.rs1.valid = 1; end else if (name inside { C_ADD }) begin - asm.rd.gpr = instr.compressed.format.cr.rd_rs1.gpr; - asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr; - asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr; - asm.rd.valid = 1; - asm.rs1.valid = 1; - asm.rs2.valid = 1; + asm.rd.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr; + asm.rd.valid = 1; + asm.rs1.valid = 1; + asm.rs2.valid = 1; end else if (name inside { C_JR, C_JALR }) begin - asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr; - asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr; - asm.rs1.valid = 1; - asm.rs2.valid = 1; + asm.rs1.gpr = instr.compressed.format.cr.rd_rs1.gpr; + asm.rs2.gpr = instr.compressed.format.cr.rs2.gpr; + asm.rs1.valid = 1; + asm.rs2.valid = 1; end end CI_TYPE: begin @@ -468,7 +485,7 @@ asm.rd.valid = 1; asm.rs1.valid = 1; asm.imm.valid = 1; - end else if (name == C_LI) begin + end else if (name == C_LI) begin asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr; asm.imm.imm_raw = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; asm.imm.imm_raw_sorted = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; @@ -478,7 +495,7 @@ asm.imm.imm_value = get_imm_value_ci({ instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }); asm.rd.valid = 1; asm.imm.valid = 1; - end else if (name == C_LUI) begin + end else if (name == C_LUI) begin asm.rd.gpr = instr.compressed.format.ci.rd_rs1.gpr; asm.imm.imm_raw = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; asm.imm.imm_raw_sorted = { instr.compressed.format.ci.imm_12, instr.compressed.format.ci.imm_6_2 }; @@ -523,71 +540,92 @@ end end CSS_TYPE: begin - asm.rs2.gpr = instr.compressed.format.css.rs2.gpr; - asm.imm.imm_raw = instr.compressed.format.css.imm; - asm.imm.imm_raw_sorted = { instr.compressed.format.css.imm[9:7], instr.compressed.format.css.imm[12:10] }; - asm.imm.imm_type = OFFSET; - asm.imm.width = 6; - asm.imm.imm_value = { 24'b0, instr.compressed.format.css.imm[9:7], instr.compressed.format.css.imm[12:10], 2'b0 }; - asm.rs2.valid = 1; - asm.imm.valid = 1; + asm.rs2.gpr = instr.compressed.format.css.rs2.gpr; + asm.imm.imm_raw = instr.compressed.format.css.imm; + asm.imm.imm_raw_sorted = { instr.compressed.format.css.imm[9:7], instr.compressed.format.css.imm[12:10] }; + asm.imm.imm_type = OFFSET; + asm.imm.width = 6; + asm.imm.imm_value = { 24'b0, instr.compressed.format.css.imm[9:7], instr.compressed.format.css.imm[12:10], 2'b0 }; + asm.rs2.valid = 1; + asm.imm.valid = 1; end CIW_TYPE: begin - asm.rd.gpr = instr.compressed.format.ciw.rd.gpr; - asm.imm.imm_raw = instr.compressed.format.ciw.imm; - asm.imm.imm_raw_sorted = get_sort_ciw_imm(instr); - asm.imm.imm_type = NZUIMM; - asm.imm.width = 8; - asm.imm.imm_value = { 22'b0, get_sort_ciw_imm(instr), 2'b0 }; - asm.imm.valid = 1; - asm.rd.valid = 1; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.ciw.rd.gpr); + asm.rd.gpr_rvc = instr.compressed.format.ciw.rd.gpr; + asm.imm.imm_raw = instr.compressed.format.ciw.imm; + asm.imm.imm_raw_sorted = get_sort_ciw_imm(instr); + asm.imm.imm_type = NZUIMM; + asm.imm.width = 8; + asm.imm.imm_value = { 22'b0, get_sort_ciw_imm(instr), 2'b0 }; + asm.imm.valid = 1; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; end CL_TYPE: begin - asm.rd.gpr = instr.compressed.format.cl.rd.gpr; - asm.rs1.gpr = instr.compressed.format.cl.rs1.gpr; - asm.imm.imm_raw = { instr.compressed.format.cl.imm_12_10, instr.compressed.format.cl.imm_6_5 }; - asm.imm.imm_raw_sorted = get_sort_cl_imm(instr); - asm.imm.imm_type = OFFSET; - asm.imm.width = 5; - asm.imm.imm_value = { 25'b0, get_sort_cl_imm(instr), 2'b0 }; - asm.rd.valid = 1; - asm.rs1.valid = 1; - asm.imm.valid = 1; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cl.rd.gpr); + asm.rd.gpr_rvc = instr.compressed.format.cl.rd.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cl.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cl.rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.cl.imm_12_10, instr.compressed.format.cl.imm_6_5 }; + asm.imm.imm_raw_sorted = get_sort_cl_imm(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 5; + asm.imm.imm_value = { 25'b0, get_sort_cl_imm(instr), 2'b0 }; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.imm.valid = 1; end CS_TYPE: begin - asm.rs2.gpr = instr.compressed.format.cs.rs2.gpr; - asm.rs1.gpr = instr.compressed.format.cs.rs1.gpr; - asm.imm.imm_raw = { instr.compressed.format.cs.imm_12_10, instr.compressed.format.cs.imm_6_5 }; - asm.imm.imm_raw_sorted = get_sort_cs_imm(instr); - asm.imm.imm_type = OFFSET; - asm.imm.width = 5; - asm.imm.imm_value = { 25'b0, get_sort_cs_imm(instr), 2'b0 }; - asm.rs2.valid = 1; - asm.rs1.valid = 1; - asm.imm.valid = 1; + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cs.rs2.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.cs.rs2.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cs.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cs.rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.cs.imm_12_10, instr.compressed.format.cs.imm_6_5 }; + asm.imm.imm_raw_sorted = get_sort_cs_imm(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 5; + asm.imm.imm_value = { 25'b0, get_sort_cs_imm(instr), 2'b0 }; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.imm.valid = 1; end CA_TYPE: begin - asm.rd.gpr = instr.compressed.format.ca.rd_rs1.gpr; - asm.rs1.gpr = instr.compressed.format.ca.rd_rs1.gpr; - asm.rs2.gpr = instr.compressed.format.ca.rs2.gpr; - asm.rd.valid = 1; - asm.rs1.valid = 1; - asm.rs2.valid = 1; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.ca.rd_rs1.gpr); + asm.rd.gpr_rvc = instr.compressed.format.ca.rd_rs1.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.ca.rd_rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.ca.rd_rs1.gpr; + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.ca.rs2.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.ca.rs2.gpr; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; end CB_TYPE: begin if (name inside { C_SRLI, C_SRAI }) begin - asm.rd.gpr = instr.compressed.format.cb.rd_rs1.gpr; - asm.rs1.gpr = instr.compressed.format.cb.rd_rs1.gpr; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr); + asm.rd.gpr_rvc = instr.compressed.format.cb.rd_rs1.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cb.rd_rs1.gpr; asm.imm.imm_raw = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 }; asm.imm.imm_raw_sorted = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 }; asm.imm.imm_type = SHAMT; asm.imm.width = 6; asm.imm.imm_value = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 }; asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; asm.imm.valid = 1; end else if (name inside { C_BEQZ, C_BNEZ }) begin - asm.rs1.gpr = instr.compressed.format.cb.rd_rs1.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cb.rd_rs1.gpr; asm.imm.imm_raw = { instr.compressed.format.cb.offset_12_10, instr.compressed.format.cb.offset_6_2 }; asm.imm.imm_raw_sorted = get_sort_cb_imm_not_sequential(instr); asm.imm.imm_type = OFFSET; @@ -595,100 +633,141 @@ asm.imm.sign_ext = 1; asm.imm.imm_value = get_imm_value_cb(get_sort_cb_imm_not_sequential(instr)); asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.imm.valid = 1; + end else if (name inside { C_ANDI }) begin + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr); + asm.rd.gpr_rvc = instr.compressed.format.cb.rd_rs1.gpr; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cb.rd_rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cb.rd_rs1.gpr; + asm.imm.imm_raw = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 }; + asm.imm.imm_raw_sorted = { instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 }; + asm.imm.imm_type = IMM; + asm.imm.width = 6; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_cb({ instr.compressed.format.cb.offset_12_10[12], instr.compressed.format.cb.offset_6_2 }); + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; asm.imm.valid = 1; end end CJ_TYPE: begin - asm.imm.imm_raw = instr.compressed.format.cj.imm; - asm.imm.imm_raw_sorted = get_sort_cj_imm(instr); - asm.imm.imm_type = OFFSET; - asm.imm.width = 11; - asm.imm.sign_ext = 1; - asm.imm.imm_value = get_imm_value_cj(get_sort_cj_imm(instr)); - asm.imm.valid = 1; + asm.imm.imm_raw = instr.compressed.format.cj.imm; + asm.imm.imm_raw_sorted = get_sort_cj_imm(instr); + asm.imm.imm_type = OFFSET; + asm.imm.width = 11; + asm.imm.sign_ext = 1; + asm.imm.imm_value = get_imm_value_cj(get_sort_cj_imm(instr)); + asm.imm.valid = 1; end CLB_TYPE: begin - asm.imm.imm_raw = instr.compressed.format.clb.uimm; - asm.imm.imm_raw_sorted = { instr.compressed.format.clb.uimm[5], instr.compressed.format.clb.uimm[6] }; - asm.imm.imm_type = UIMM; - asm.imm.width = 2; - asm.imm.imm_value = { instr.compressed.format.clb.uimm[5], instr.compressed.format.clb.uimm[6] }; - asm.rs1.gpr = instr.compressed.format.clb.rs1.gpr; - asm.rd.gpr = instr.compressed.format.clb.rd.gpr; - asm.rs1.valid = 1; - asm.rd.valid = 1; - asm.imm.valid = 1; + asm.imm.imm_raw = instr.compressed.format.clb.uimm; + asm.imm.imm_raw_sorted = { instr.compressed.format.clb.uimm[5], instr.compressed.format.clb.uimm[6] }; + asm.imm.imm_type = UIMM; + asm.imm.width = 2; + asm.imm.imm_value = { instr.compressed.format.clb.uimm[5], instr.compressed.format.clb.uimm[6] }; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.clb.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.clb.rs1.gpr; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.clb.rd.gpr); + asm.rd.gpr_rvc = instr.compressed.format.clb.rd.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.imm.valid = 1; end CSB_TYPE: begin - asm.imm.imm_raw = instr.compressed.format.csb.uimm; - asm.imm.imm_raw_sorted = { instr.compressed.format.csb.uimm[5], instr.compressed.format.csb.uimm[6] }; - asm.imm.imm_type = UIMM; - asm.imm.width = 2; - asm.imm.imm_value = { instr.compressed.format.csb.uimm[5], instr.compressed.format.csb.uimm[6] }; - asm.rs1.gpr = instr.compressed.format.csb.rs1.gpr; - asm.rs2.gpr = instr.compressed.format.csb.rs2.gpr; - asm.rs1.valid = 1; - asm.rs2.valid = 1; - asm.imm.valid = 1; + asm.imm.imm_raw = instr.compressed.format.csb.uimm; + asm.imm.imm_raw_sorted = { instr.compressed.format.csb.uimm[5], instr.compressed.format.csb.uimm[6] }; + asm.imm.imm_type = UIMM; + asm.imm.width = 2; + asm.imm.imm_value = { instr.compressed.format.csb.uimm[5], instr.compressed.format.csb.uimm[6] }; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.csb.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.csb.rs1.gpr; + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.csb.rs2.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.csb.rs2.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; + asm.imm.valid = 1; end CLH_TYPE: begin - asm.imm.imm_raw = instr.compressed.format.clh.uimm; - asm.imm.imm_raw_sorted = instr.compressed.format.clh.uimm; - asm.imm.imm_type = UIMM; - asm.imm.width = 1; - asm.imm.imm_value = { 30'b0, instr.compressed.format.clh.uimm }; - asm.rs1.gpr = instr.compressed.format.clh.rs1.gpr; - asm.rd.gpr = instr.compressed.format.clh.rd.gpr; - asm.rs1.valid = 1; - asm.rd.valid = 1; - asm.imm.valid = 1; + asm.imm.imm_raw = instr.compressed.format.clh.uimm; + asm.imm.imm_raw_sorted = instr.compressed.format.clh.uimm; + asm.imm.imm_type = UIMM; + asm.imm.width = 1; + asm.imm.imm_value = { 30'b0, instr.compressed.format.clh.uimm }; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.clh.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.clh.rs1.gpr; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.clh.rd.gpr); + asm.rd.gpr_rvc = instr.compressed.format.clh.rd.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; + asm.imm.valid = 1; end CSH_TYPE: begin - asm.imm.imm_raw = instr.compressed.format.csh.uimm; - asm.imm.imm_raw_sorted = instr.compressed.format.csh.uimm; - asm.imm.imm_type = UIMM; - asm.imm.width = 1; - asm.imm.imm_value = {30'b0, instr.compressed.format.csh.uimm, 1'b0}; - asm.rs1.gpr = instr.compressed.format.csh.rs1.gpr; - asm.rs2.gpr = instr.compressed.format.csh.rs2.gpr; - asm.rs1.valid = 1; - asm.rs2.valid = 1; - asm.imm.valid = 1; + asm.imm.imm_raw = instr.compressed.format.csh.uimm; + asm.imm.imm_raw_sorted = instr.compressed.format.csh.uimm; + asm.imm.imm_type = UIMM; + asm.imm.width = 1; + asm.imm.imm_value = {30'b0, instr.compressed.format.csh.uimm, 1'b0}; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.csh.rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.csh.rs1.gpr; + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.csh.rs2.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.csh.rs2.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; + asm.imm.valid = 1; end CU_TYPE: begin - asm.rs1.gpr = instr.compressed.format.cu.rd_rs1.gpr; - asm.rd.gpr = instr.compressed.format.cu.rd_rs1.gpr; - asm.rs1.valid = 1; - asm.rd.valid = 1; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cu.rd_rs1.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cu.rd_rs1.gpr; + asm.rd.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cu.rd_rs1.gpr); + asm.rd.gpr_rvc = instr.compressed.format.cu.rd_rs1.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rd.valid = 1; + asm.rd.valid_gpr_rvc = 1; end CMMV_TYPE: begin - asm.rs1.gpr = instr.compressed.format.cmmv.r1s.gpr; - asm.rs2.gpr = instr.compressed.format.cmmv.r2s.gpr; - asm.rs1.valid = 1; - asm.rs2.valid = 1; + asm.rs1.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cmmv.r1s.gpr); + asm.rs1.gpr_rvc = instr.compressed.format.cmmv.r1s.gpr; + asm.rs2.gpr = get_gpr_from_gpr_rvc(instr.compressed.format.cmmv.r2s.gpr); + asm.rs2.gpr_rvc = instr.compressed.format.cmmv.r2s.gpr; + asm.rs1.valid = 1; + asm.rs1.valid_gpr_rvc = 1; + asm.rs2.valid = 1; + asm.rs2.valid_gpr_rvc = 1; end CMJT_TYPE: begin - asm.imm.imm_raw = instr.compressed.format.cmjt.index; - asm.imm.imm_raw_sorted = instr.compressed.format.cmjt.index; - asm.imm.imm_type = INDEX; - asm.imm.width = 1; - asm.imm.imm_value = instr.compressed.format.cmjt.index; - asm.imm.valid = 1; + asm.imm.imm_raw = instr.compressed.format.cmjt.index; + asm.imm.imm_raw_sorted = instr.compressed.format.cmjt.index; + asm.imm.imm_type = INDEX; + asm.imm.width = 1; + asm.imm.imm_value = instr.compressed.format.cmjt.index; + asm.imm.valid = 1; end CMPP_TYPE: begin - asm.imm.imm_raw = instr.compressed.format.cmpp.spimm; - asm.imm.imm_raw_sorted = instr.compressed.format.cmpp.spimm; - asm.imm.imm_type = SPIMM; - asm.imm.width = 1; - asm.rlist.rlist = instr.compressed.format.cmpp.urlist; - asm.stack_adj.stack_adj = get_stack_adj(instr.compressed.format.cmpp.urlist, instr.compressed.format.cmpp.spimm); - asm.imm.valid = 1; - asm.rs1.gpr = instr.compressed.format.csh.rs1.gpr; - asm.rs2.gpr = instr.compressed.format.csh.rs2.gpr; - asm.rs1.valid = 1; - asm.rs2.valid = 1; - asm.rlist.valid = 1; - asm.stack_adj.valid = 1; + asm.imm.imm_raw = instr.compressed.format.cmpp.spimm; + asm.imm.imm_raw_sorted = instr.compressed.format.cmpp.spimm; + asm.imm.imm_type = SPIMM; + asm.imm.width = 1; + asm.rlist.rlist = instr.compressed.format.cmpp.urlist; + asm.stack_adj.stack_adj = get_stack_adj(instr.compressed.format.cmpp.urlist, instr.compressed.format.cmpp.spimm); + asm.imm.valid = 1; + asm.rs1.gpr = instr.compressed.format.csh.rs1.gpr; + asm.rs2.gpr = instr.compressed.format.csh.rs2.gpr; + asm.rs1.valid = 1; + asm.rs2.valid = 1; + asm.rlist.valid = 1; + asm.stack_adj.valid = 1; end default : ; @@ -711,7 +790,7 @@ ( (instr.uncompressed.opcode == MISC_MEM) && (instr.uncompressed.format.i.funct3 == 3'b001)) : - asm = build_asm(FENCEI, I_TYPE, instr); + asm = build_asm(FENCE_I, I_TYPE, instr); ( (instr.uncompressed.opcode == SYSTEM) && (instr.uncompressed.format.i.imm == 12'b0000_0000_0000)) : @@ -1032,9 +1111,9 @@ asm = build_asm(CTZ, I_TYPE, instr); ( (instr.uncompressed.opcode == OP_IMM) - && (instr.uncompressed.format.i.funct3 == FUNCT3_ORCB) + && (instr.uncompressed.format.i.funct3 == FUNCT3_ORC_B) && (instr.uncompressed.format.i.imm == 12'b0010_1000_0111)) : - asm = build_asm(ORCB, I_TYPE, instr); + asm = build_asm(ORC_B, I_TYPE, instr); ( (instr.uncompressed.opcode == OP) && (instr.uncompressed.format.r.funct3 == FUNCT3_ORN) @@ -1079,17 +1158,17 @@ ( (instr.uncompressed.opcode == OP_IMM) && (instr.uncompressed.format.i.funct3 == FUNCT3_SEXT) && (instr.uncompressed.format.i.imm == 12'b0110_0000_0100)) : - asm = build_asm(SEXTB, I_TYPE, instr); + asm = build_asm(SEXT_B, I_TYPE, instr); ( (instr.uncompressed.opcode == OP_IMM) && (instr.uncompressed.format.i.funct3 == FUNCT3_SEXT) && (instr.uncompressed.format.i.imm == 12'b0110_0000_0101)) : - asm = build_asm(SEXTH, I_TYPE, instr); + asm = build_asm(SEXT_H, I_TYPE, instr); ( (instr.uncompressed.opcode == OP) - && (instr.uncompressed.format.i.funct3 == FUNCT3_ZEXTH) + && (instr.uncompressed.format.i.funct3 == FUNCT3_ZEXT_H) && (instr.uncompressed.format.i.imm == 12'b0000_1000_0000)) : - asm = build_asm(ZEXTH, I_TYPE, instr); + asm = build_asm(ZEXT_H, I_TYPE, instr); //Zbc ( (instr.uncompressed.opcode == OP) @@ -1331,24 +1410,24 @@ //Zcb ( (instr.compressed.opcode == C1) - && (instr.compressed.format.cu.funct5 == FUNCT5_C_ZEXTB) + && (instr.compressed.format.cu.funct5 == FUNCT5_C_ZEXT_B) && (instr.compressed.format.cu.funct6 == 6'b100111)) : - asm = build_asm(C_ZEXTB, CU_TYPE, instr); + asm = build_asm(C_ZEXT_B, CU_TYPE, instr); ( (instr.compressed.opcode == C1) - && (instr.compressed.format.cu.funct5 == FUNCT5_C_SEXTB) + && (instr.compressed.format.cu.funct5 == FUNCT5_C_SEXT_B) && (instr.compressed.format.cu.funct6 == 6'b100111)) : - asm = build_asm(C_SEXTB, CU_TYPE, instr); + asm = build_asm(C_SEXT_B, CU_TYPE, instr); ( (instr.compressed.opcode == C1) - && (instr.compressed.format.cu.funct5 == FUNCT5_C_ZEXTH) + && (instr.compressed.format.cu.funct5 == FUNCT5_C_ZEXT_H) && (instr.compressed.format.cu.funct6 == 6'b100111)) : - asm = build_asm(C_ZEXTH, CU_TYPE, instr); + asm = build_asm(C_ZEXT_H, CU_TYPE, instr); ( (instr.compressed.opcode == C1) - && (instr.compressed.format.cu.funct5 == FUNCT5_C_SEXTH) + && (instr.compressed.format.cu.funct5 == FUNCT5_C_SEXT_H) && (instr.compressed.format.cu.funct6 == 6'b100111)) : - asm = build_asm(C_SEXTH, CU_TYPE, instr); + asm = build_asm(C_SEXT_H, CU_TYPE, instr); ( (instr.compressed.opcode == C1) && (instr.compressed.format.cu.funct5 == FUNCT5_C_NOT) @@ -1436,7 +1515,7 @@ // --------------------------------------------------------------------------- // Identify if a given instruction matches an expected instruction name // --------------------------------------------------------------------------- - function match_instr(instr_t instr, instr_name_e instr_type); + function automatic match_instr(instr_t instr, instr_name_e instr_type); match_instr = (decode_instr(instr).instr == instr_type); endfunction : match_instr diff --git a/lib/isa_decoder/isa_typedefs.sv b/lib/isa_decoder/isa_typedefs.sv index e54b1e9c72..374985c103 100644 --- a/lib/isa_decoder/isa_typedefs.sv +++ b/lib/isa_decoder/isa_typedefs.sv @@ -27,7 +27,7 @@ // Unknown for instructions that cannot be decoded UNKNOWN_INSTR = 0, FENCE, - FENCEI, + FENCE_I, MRET, DRET, ECALL, @@ -101,7 +101,7 @@ MAXU, CPOP, CTZ, - ORCB, + ORC_B, ORN, CLZ, ANDN, @@ -110,9 +110,9 @@ RORI, XNOR, REV8, - SEXTB, - SEXTH, - ZEXTH, + SEXT_B, + SEXT_H, + ZEXT_H, //Zbc CLMUL, CLMULH, @@ -171,10 +171,10 @@ C_LH, C_SB, C_SH, - C_ZEXTB, - C_SEXTB, - C_ZEXTH, - C_SEXTH, + C_ZEXT_B, + C_SEXT_B, + C_ZEXT_H, + C_SEXT_H, C_NOT, C_MUL, //Zcmp @@ -282,7 +282,7 @@ C_X13 = 3'b101, C_X14 = 3'b110, C_X15 = 3'b111 - } c_gpr_name_e; + } gpr_rvc_name_e; typedef enum logic [2:0] { C_S0 = 3'b000, @@ -293,13 +293,13 @@ C_A3 = 3'b101, C_A4 = 3'b110, C_A5 = 3'b111 - } c_gpr_abi_name_e; + } gpr_rvc_abi_name_e; typedef union packed { - bit [2:0] raw; - c_gpr_name_e gpr; - c_gpr_abi_name_e gpr_abi; - } c_gpr_t; + bit [2:0] raw; + gpr_rvc_name_e gpr; + gpr_rvc_abi_name_e gpr_abi; + } gpr_rvc_t; typedef union packed { bit [4:0] raw; @@ -438,11 +438,11 @@ // Minor opcodes for logical operators and sign extend (FUNCT3_SEXT) typedef enum logic [2:0] { - FUNCT3_XNOR = 3'b100, - FUNCT3_ORCB = 3'b101, - FUNCT3_ORN = 3'b110, - FUNCT3_ANDN = 3'b111, - FUNCT3_SEXT = 3'b001 + FUNCT3_XNOR = 3'b100, + FUNCT3_ORC_B = 3'b101, + FUNCT3_ORN = 3'b110, + FUNCT3_ANDN = 3'b111, + FUNCT3_SEXT = 3'b001 } zbb_logical_minor_opcode_e; // Minor opcodes for rotate instructions @@ -455,9 +455,9 @@ // and zero extend halfword instruction (FUNCT3_ZEXTH). // FUNCT3_C is correct for all count isntructions. typedef enum logic [2:0] { - FUNCT3_REV8 = 3'b101, - FUNCT3_C = 3'b001, - FUNCT3_ZEXTH = 3'b100 + FUNCT3_REV8 = 3'b101, + FUNCT3_C = 3'b001, + FUNCT3_ZEXT_H = 3'b100 } zbb_rev8_c_zexth_minor_opcode_e; typedef enum logic [2:0] { @@ -523,10 +523,10 @@ } a_minor_opcode_e; typedef enum logic [4:0] { - FUNCT5_C_SEXTB = 5'b11001, - FUNCT5_C_ZEXTB = 5'b11000, - FUNCT5_C_ZEXTH = 5'b11010, - FUNCT5_C_SEXTH = 5'b11011, + FUNCT5_C_SEXT_B = 5'b11001, + FUNCT5_C_ZEXT_B = 5'b11000, + FUNCT5_C_ZEXT_H = 5'b11010, + FUNCT5_C_SEXT_H = 5'b11011, FUNCT5_C_NOT = 5'b11101 } funct5_compressed_e; @@ -668,42 +668,42 @@ typedef struct packed { logic[15:13] funct3; logic[12:7] imm; - gpr_t rs2; + gpr_t rs2; } css_type_t; typedef struct packed { logic[15:13] funct3; logic[12:5] imm; - c_gpr_t rd; + gpr_rvc_t rd; } ciw_type_t; typedef struct packed { logic[15:13] funct3; logic[12:10] imm_12_10; - c_gpr_t rs1; + gpr_rvc_t rs1; logic[6:5] imm_6_5; - c_gpr_t rd; + gpr_rvc_t rd; } cl_type_t; typedef struct packed { logic[15:13] funct3; logic[12:10] imm_12_10; - c_gpr_t rs1; + gpr_rvc_t rs1; logic[6:5] imm_6_5; - c_gpr_t rs2; + gpr_rvc_t rs2; } cs_type_t; typedef struct packed { logic[15:10] funct6; - c_gpr_t rd_rs1; + gpr_rvc_t rd_rs1; logic[6:5] funct2; - c_gpr_t rs2; + gpr_rvc_t rs2; } ca_type_t; typedef struct packed { logic[15:13] funct3; logic[12:10] offset_12_10; - c_gpr_t rd_rs1; + gpr_rvc_t rd_rs1; logic[6:2] offset_6_2; } cb_type_t; @@ -714,45 +714,45 @@ typedef struct packed { logic[15:10] funct6; - c_gpr_t rs1; + gpr_rvc_t rs1; logic[6:5] uimm; - c_gpr_t rd; + gpr_rvc_t rd; } clb_type_t; typedef struct packed { logic[15:10] funct6; - c_gpr_t rs1; + gpr_rvc_t rs1; logic[6:5] uimm; - c_gpr_t rs2; + gpr_rvc_t rs2; } csb_type_t; typedef struct packed { logic[15:10] funct6; - c_gpr_t rs1; + gpr_rvc_t rs1; logic funct1; logic uimm; - c_gpr_t rd; + gpr_rvc_t rd; } clh_type_t; typedef struct packed { logic[15:10] funct6; - c_gpr_t rs1; + gpr_rvc_t rs1; logic funct1; logic uimm; - c_gpr_t rs2; + gpr_rvc_t rs2; } csh_type_t; typedef struct packed { logic[15:10] funct6; - c_gpr_t rd_rs1; + gpr_rvc_t rd_rs1; logic[6:2] funct5; } cu_type_t; typedef struct packed { logic[15:10] funct6; - c_gpr_t r1s; + gpr_rvc_t r1s; logic[6:5] funct2; - c_gpr_t r2s; + gpr_rvc_t r2s; } cmmv_type_t; typedef struct packed { @@ -810,8 +810,10 @@ // and enumerated abi register names // --------------------------------------------------------------------------- typedef struct packed { - gpr_t gpr; - bit valid; + gpr_t gpr; + gpr_rvc_t gpr_rvc; + bit valid; + bit valid_gpr_rvc; } reg_operand_t; // --------------------------------------------------------------------------- @@ -919,16 +921,16 @@ // Main _decoded_ and _disassembled_ data structure // --------------------------------------------------------------------------- typedef struct packed { - instr_name_e instr; // Instruction name - instr_format_e format; // Instruction format type - reg_operand_t rd; // Destination register, qualified by rd.valid - reg_operand_t rs1; // source register 1, qualified by rs1.valid - reg_operand_t rs2; // -- 2, -- 2 - reg_operand_t rs3; // -- 3, -- 3 - imm_operand_t imm; // Immediate, qualified by imm.valid - csr_operand_t csr; // CSR register address, qualified by csr.valid - logic is_hint; // Indicates whether the current instruction is a HINT. - rlist_operand_t rlist; // structure to handle rlist fields for Zcmp-instructions + instr_name_e instr; // Instruction name + instr_format_e format; // Instruction format type + reg_operand_t rd; // Destination register, qualified by rd.valid + reg_operand_t rs1; // source register 1, qualified by rs1.valid + reg_operand_t rs2; // -- 2, -- 2 + reg_operand_t rs3; // -- 3, -- 3 + imm_operand_t imm; // Immediate, qualified by imm.valid + csr_operand_t csr; // CSR register address, qualified by csr.valid + logic is_hint; // Indicates whether the current instruction is a HINT. + rlist_operand_t rlist; // structure to handle rlist fields for Zcmp-instructions stack_adj_operand_t stack_adj; // structure to handle stack_adj fields for Zcmp-instructions atomic_operand_t atomic; } asm_t; diff --git a/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv b/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv index e04d55df88..adf1842114 100644 --- a/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv +++ b/lib/uvm_agents/uvma_isacov/uvma_isacov_mon.sv @@ -210,13 +210,20 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL end else if (cfg.decoder == ISA_SUPPORT) begin // Attempt to decode instruction with isa_support - mon_trn.instr.c_rdrs1 = instr_asm.rd.gpr; - mon_trn.instr.c_rdp = instr_asm.rd.gpr; - mon_trn.instr.c_rs1s = instr_asm.rs1.gpr; - mon_trn.instr.c_rs2s = instr_asm.rs2.gpr; - mon_trn.instr.rs1 = instr_asm.rs1.gpr; - mon_trn.instr.rs2 = instr_asm.rs2.gpr; - mon_trn.instr.rd = instr_asm.rd.gpr; + + // TODO: silabs-hefegran, isa decoder representation changed for compressed 'rx registers, + // we supply the old (non-translated) value to avoid having to rewrite that logic now, which + // might also interfere with the spike implementation. + // the "get_rx"-functions should no longer be needed if we supply the translated values to + // the coverage model. + mon_trn.instr.c_rdrs1 = instr_asm.rd.valid ? ( instr_asm.rd.valid_gpr_rvc ? instr_asm.rd.gpr_rvc : instr_asm.rd.gpr ) + : ( instr_asm.rs1.valid_gpr_rvc ? instr_asm.rs1.gpr_rvc : instr_asm.rs1.gpr ); + mon_trn.instr.c_rdp = instr_asm.rd.valid_gpr_rvc ? instr_asm.rd.gpr_rvc : instr_asm.rd.gpr; + mon_trn.instr.c_rs1s = instr_asm.rs1.valid_gpr_rvc ? instr_asm.rs1.gpr_rvc : instr_asm.rs1.gpr; + mon_trn.instr.c_rs2s = instr_asm.rs2.valid_gpr_rvc ? instr_asm.rs2.gpr_rvc : instr_asm.rs2.gpr; + mon_trn.instr.rs1 = instr_asm.rs1.valid_gpr_rvc ? instr_asm.rs1.gpr_rvc : instr_asm.rs1.gpr; + mon_trn.instr.rs2 = instr_asm.rs2.valid_gpr_rvc ? instr_asm.rs2.gpr_rvc : instr_asm.rs1.gpr; + mon_trn.instr.rd = instr_asm.rd.valid_gpr_rvc ? instr_asm.rd.gpr_rvc : instr_asm.rd.gpr; mon_trn.instr.immi = instr_asm.imm.imm_raw_sorted; mon_trn.instr.imms = instr_asm.imm.imm_raw_sorted; mon_trn.instr.immb = instr_asm.imm.imm_raw_sorted; @@ -329,7 +336,13 @@ function void uvma_isacov_mon_c::write_rvfi_instr(uvma_rvfi_instr_seq_item_c#(IL endcase end - mon_trn.instr.set_valid_flags(); + if (cfg.decoder == SPIKE) begin + mon_trn.instr.set_valid_flags(); + end else begin // if ISA_DECODER + mon_trn.instr.rd_valid = instr_asm.rd.valid; + mon_trn.instr.rs1_valid = instr_asm.rs1.valid; + mon_trn.instr.rs2_valid = instr_asm.rs2.valid; + end // Set enumerations for register values as reported from RVFI if (mon_trn.instr.rs1_valid) begin diff --git a/mk/uvmt/xrun.mk b/mk/uvmt/xrun.mk index 47db9f25d7..bb1b69757d 100644 --- a/mk/uvmt/xrun.mk +++ b/mk/uvmt/xrun.mk @@ -46,6 +46,7 @@ XRUN_COMP_FLAGS ?= \ -access +rwc \ -nowarn UEXPSC \ -lwdgen \ + -nocsf \ -sv \ -uvm \ -uvmhome $(XRUN_UVMHOME_ARG) \ @@ -56,6 +57,7 @@ XRUN_LDGEN_COMP_FLAGS ?= \ -64bit \ -disable_sem2009 \ -access +rwc \ + -nocsf \ -nowarn UEXPSC \ -nowarn DLCPTH \ -sv \ @@ -68,10 +70,10 @@ XRUN_RUN_BASE_FLAGS ?= -64bit $(XRUN_GUI) -licqueue +UVM_VERBOSITY=$(XRUN_UVM_VE $(XRUN_PLUSARGS) -svseed $(RNDSEED) XRUN_GUI ?= XRUN_SINGLE_STEP ?= -XRUN_ELAB_COV = -covdut uvmt_$(CV_CORE_LC)_tb -coverage b:e:f:u +XRUN_ELAB_COV = -covdut uvmt_$(CV_CORE_LC)_tb -coverage b:e:f:t:u XRUN_ELAB_COVFILE = -covfile $(abspath $(MAKE_PATH)/../tools/xrun/covfile.tcl) XRUN_RUN_COV = -covscope uvmt_$(CV_CORE_LC)_tb -nowarn CGDEFN -XRUN_RUN_BASE_FLAGS += -sv_lib $(DPI_DASM_LIB) +XRUN_RUN_BASE_FLAGS += -nocsf -sv_lib $(DPI_DASM_LIB) # Only append the IMPERAS_DV_MODEL sv_lib flag if the file actually exists) ifneq (,$(wildcard $(IMPERAS_DV_MODEL))) @@ -279,6 +281,16 @@ XRUN_COMP_FLAGS += -nowarn CGPIDF # deselect_coverage -all warnings XRUN_COMP_FLAGS += -nowarn CGNSWA +# Newer tool version has different fsm coverage options than old version. Ok. +XRUN_COMP_FLAGS += -nowarn COVFDP + +# Certain data types are not supported for toggle cov. Ok. +XRUN_COMP_FLAGS += -nowarn COVUTA + +# MORE toggle cov support CAN be enabled. +XRUN_COMP_FLAGS += -nowarn COVNOEN +XRUN_COMP_FLAGS += -nowarn COVMDD + # Value Parameters without default values XRUN_COMP_FLAGS += -setenv CADENCE_ENABLE_AVSREQ_44905_PHASE_1=1