From 11a15f2a20be6f88f82514ce71e4a6b5511ef3c2 Mon Sep 17 00:00:00 2001 From: Ayoub Jalali Date: Thu, 13 Jul 2023 10:46:25 +0200 Subject: [PATCH 1/4] CVXIF : Add yaml description for xif tests --- cva6/regress/dv-generated-tests.sh | 29 +++--- cva6/regress/dv-generated-xif-tests.sh | 101 ++++++++++++++++++++ cva6/sim/Makefile | 2 +- cva6/sim/cva6.py | 2 +- cva6/sim/cva6_base_testlist.yaml | 124 ++++++++++++++++++++++--- 5 files changed, 233 insertions(+), 25 deletions(-) create mode 100644 cva6/regress/dv-generated-xif-tests.sh diff --git a/cva6/regress/dv-generated-tests.sh b/cva6/regress/dv-generated-tests.sh index f2f6492d9a..5eb47b7d13 100644 --- a/cva6/regress/dv-generated-tests.sh +++ b/cva6/regress/dv-generated-tests.sh @@ -15,6 +15,7 @@ fi # install the required tools source ./cva6/regress/install-cva6.sh source ./cva6/regress/install-riscv-dv.sh +source ./cva6/regress/install-spike.sh if ! [ -n "$DV_TARGET" ]; then DV_TARGET=cv32a60x @@ -51,6 +52,13 @@ if [[ "$list_num" = 1 ]];then ); I=(100 100 20 100 20 20); elif [[ "$list_num" = 2 ]];then + TEST_NAME=( + "riscv_arithmetic_basic_same_reg_test" + "riscv_arithmetic_basic_hazard_rdrs1_test" + "riscv_arithmetic_basic_hazard_rdrs2_test" + ); + I=(100 100 100); +elif [[ "$list_num" = 3 ]];then TEST_NAME=( "riscv_arithmetic_basic_csr_dummy" "riscv_arithmetic_basic_Randcsr_test" @@ -58,34 +66,34 @@ elif [[ "$list_num" = 2 ]];then "riscv_arithmetic_basic_illegal_csr" ); I=(20 20 20 20); -elif [[ "$list_num" = 3 ]];then +elif [[ "$list_num" = 4 ]];then TEST_NAME=( "riscv_mmu_stress_hint_test" "riscv_mmu_stress_test" ); I=(100 100); -elif [[ "$list_num" = 4 ]];then +elif [[ "$list_num" = 5 ]];then TEST_NAME=( "riscv_load_store_test" "riscv_load_store_cmp_test" - "riscv_load_store_hint_test" + "riscv_load_store_hazard_test" "riscv_unaligned_load_store_test" ); I=(50 50 50 50); -elif [[ "$list_num" = 5 ]];then +elif [[ "$list_num" = 6 ]];then TEST_NAME=( "riscv_rand_jump_hint_comp_test" "riscv_rand_jump_no_cmp_test" "riscv_rand_jump_illegal_test" "riscv_arithmetic_basic_sub_prog_test" ); - I=(75 75 50 30); + I=(75 75 50 20); fi if [[ "$list_num" != 0 ]];then if [[ ${#TEST_NAME[@]} != ${#I[@]} ]];then echo "***********ERROR***************" - echo "The length of TEST_NAME and I should be equal !!!!" + echo "The length of TEST_NAME and Iteration should be equal !!!!" echo "Fix the length of one of the arrays" exit fi @@ -106,16 +114,16 @@ while [[ $j -lt ${#TEST_NAME[@]} ]];do cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imac/ --mabi ilp32 --isa rv32imac --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 n=0 - echo "Generate the test : ${TEST_NAME[j]}" + echo "Generate the test: ${TEST_NAME[j]}" #this while loop detects the failed tests from the log file and remove them - echo "Deleting failed tests : " + echo "Deleting failed tests: " while read line;do if [[ "$line" = "" ]];then n=$((n+1)) fi for word in $line;do if [[ "$word" = "$key_word" ]];then - echo -e ""${TEST_NAME[j]}"_"$n" : Failed" + echo -e ""${TEST_NAME[j]}"_"$n": Failed" rm -rf vcs_results/default/vcs.d/simv.vdb/snps/coverage/db/testdata/"${TEST_NAME[j]}"_"$n"/ fi done @@ -126,8 +134,7 @@ done #Execute directed tests to improve functional coverage of ISA j=0 elif [[ "$list_num" = 0 ]];then - printf "==== Execute Directed tests to improve functional coverage of isa, by hiting some corners !!! ====\n\n" - printf "==== These tests are generated by RISCV-DV before modify to hit some specific values ====\n\n" + printf "==== Execute Directed tests to improve functional coverage of isa, by hitting corners !!! ====\n\n" python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike fi cd - diff --git a/cva6/regress/dv-generated-xif-tests.sh b/cva6/regress/dv-generated-xif-tests.sh new file mode 100644 index 0000000000..28a8bdcb85 --- /dev/null +++ b/cva6/regress/dv-generated-xif-tests.sh @@ -0,0 +1,101 @@ +# Copyright 2023 Thales DIS SAS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +if ! [ -n "$RISCV" ]; then + echo "Error: RISCV variable undefined" + return +fi + +# install the required tools +source ./cva6/regress/install-cva6.sh +source ./cva6/regress/install-riscv-dv.sh +source ./cva6/regress/install-spike.sh + +if ! [ -n "$DV_TARGET" ]; then + DV_TARGET=cv32a60x +fi + +if ! [ -n "$DV_SIMULATORS" ]; then + DV_SIMULATORS=vcs-uvm,spike +fi + +if ! [ -n "$list_num" ]; then + list_num=1 #default test list +fi + +export cov=1 #enable the Code Coverage + +cd cva6/sim/ +dd=$(date '+%Y-%m-%d') +key_word="Mismatch[1]:" +#Read from the iss_regr.log to detect the failed tests +logfile=out_$dd/iss_regr.log +TESTLIST_FILE=cva6_base_testlist.yaml +DIRECTED_TESTLIST=../tests/testlist_cvxif.yaml +j=0; +rm -rf out_$dd + +if [[ "$list_num" = 1 ]];then + TEST_NAME=( + "riscv_arithmetic_basic_xif_test" + "riscv_arithmetic_basic_xif_illegal_test" + "riscv_load_store_xif_test" + "riscv_rand_jump_xif_test" + ); + I=(100 100 100 100); +fi + +if [[ "$list_num" != 0 ]];then +if [[ ${#TEST_NAME[@]} != ${#I[@]} ]];then + echo "***********ERROR***************" + echo "The length of TEST_NAME and Iteration should be equal !!!!" + echo "Fix the length of one of the arrays" + exit +fi +printf "+====================================================================================+" +header="\n %-50s %-20s %s\n" +format=" %-50s %-20d %d\n" +printf "$header" "TEST NAME" "ITERATION" "BATCH SIZE" +printf "+====================================================================================+\n" + +while [[ $j -lt ${#TEST_NAME[@]} ]];do + printf "$format" \ + ${TEST_NAME[j]} ${I[j]} ${BZ[j]} + j=$((j+1)) +done +printf "+====================================================================================+\n" +j=0 +while [[ $j -lt ${#TEST_NAME[@]} ]];do + cp ../env/corev-dv/custom/riscv_custom_instr_enum.sv ./dv/src/isa/custom/ + python3 cva6.py --testlist=$TESTLIST_FILE --test ${TEST_NAME[j]} --iss_yaml cva6.yaml --target $DV_TARGET -cs ../env/corev-dv/target/rv32imc/ --mabi ilp32 --isa rv32imc --simulator_yaml ../env/corev-dv/simulator.yaml --iss=vcs-uvm,spike -i ${I[j]} -bz 1 --iss_timeout 300 + n=0 + echo "Generate the test: ${TEST_NAME[j]}" +#this while loop detects the failed tests from the log file and remove them + echo "Deleting failed tests: " + while read line;do + if [[ "$line" = "" ]];then + n=$((n+1)) + fi + for word in $line;do + if [[ "$word" = "$key_word" ]];then + echo -e ""${TEST_NAME[j]}"_"$n": Failed" + rm -rf vcs_results/default/vcs.d/simv.vdb/snps/coverage/db/testdata/"${TEST_NAME[j]}"_"$n"/ + fi + done + done < $logfile + rm -rf out_$dd + j=$((j+1)) +done +#Execute directed tests to improve functional coverage of ISA +j=0 +elif [[ "$list_num" = 0 ]];then + printf "==== Execute Directed tests to improve functional coverage of isa, by hitting corners !!! ====\n\n" + python3 cva6.py --testlist=$DIRECTED_TESTLIST --iss_yaml cva6.yaml --target $DV_TARGET --iss=vcs-uvm,spike +fi +cd - diff --git a/cva6/sim/Makefile b/cva6/sim/Makefile index c4c05cbc10..542df6d8a4 100644 --- a/cva6/sim/Makefile +++ b/cva6/sim/Makefile @@ -105,7 +105,7 @@ endif # Spike specific commands, variables ############################################################################### spike: - $(tool_path)/spike $(spike_stepout) --log-commits --isa=$(variant) -l $(elf) + $(tool_path)/spike $(spike_stepout) --extension=cvxif --log-commits --isa=$(variant) -l $(elf) cp $(log).iss $(log) ############################################################################### diff --git a/cva6/sim/cva6.py b/cva6/sim/cva6.py index 9c6ee5856b..7cbd8ed3a6 100644 --- a/cva6/sim/cva6.py +++ b/cva6/sim/cva6.py @@ -421,7 +421,7 @@ def run_assembly(asm_test, iss_yaml, isa, target, mabi, gcc_opts, iss_opts, outp cmd = ("%s -static -mcmodel=medany \ -fvisibility=hidden -nostdlib \ -nostartfiles %s \ - -I%s/dv/user_extension \ + -I%s/../env/corev-dv/user_extension \ -T%s %s -o %s " % \ (get_env_var("RISCV_GCC", debug_cmd = debug_cmd), asm_test, cwd, linker, gcc_opts, elf)) diff --git a/cva6/sim/cva6_base_testlist.yaml b/cva6/sim/cva6_base_testlist.yaml index d5f08d2f23..dd026edd88 100644 --- a/cva6/sim/cva6_base_testlist.yaml +++ b/cva6/sim/cva6_base_testlist.yaml @@ -128,17 +128,19 @@ gen_test: cva6_instr_base_test_c rtl_test: core_base_test -- test: riscv_load_store_hint_test +- test: riscv_load_store_hazard_test description: > - Unaligned load/store test + Arithmetic instruction test, no load/store/branch instructions no compressed gen_opts: > +instr_cnt=500 +num_of_sub_program=0 - +no_load_store=0 - +no_branch_jump=0 - +directed_instr_0=riscv_load_store_rand_instr_stream,20 - +directed_instr_1=riscv_load_store_hazard_instr_stream,50 - +hint_instr_ratio=500 + +no_fence=1 + +directed_instr_1=riscv_multi_page_load_store_instr_stream,20 + +no_data_page=0 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +disable_compressed_instr=0 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -149,7 +151,6 @@ gen_opts: > +instr_cnt=500 +num_of_sub_program=0 - +directed_instr_0=riscv_int_numeric_corner_stream,4 +no_fence=1 +no_data_page=1 +no_branch_jump=1 @@ -162,6 +163,52 @@ gen_test: cva6_instr_base_test_c rtl_test: core_base_test +- test: riscv_arithmetic_basic_xif_illegal_test + description: > + Arithmetic instruction test, no load/store/branch instructions + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_x_extension=1 + +illegal_instr_ratio=100 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_load_store_xif_test + description: > + Unaligned load/store test + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +no_load_store=0 + +no_branch_jump=1 + +directed_instr_0=riscv_load_store_rand_instr_stream,20 + +directed_instr_1=riscv_load_store_hazard_instr_stream,50 + +tvec_alignment=8 + +enable_x_extension=1 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + +- test: riscv_rand_jump_xif_test + description: > + Jump among large number of sub-programs, stress testing iTLB operations. + gen_opts: > + +instr_cnt=500 + +num_of_sub_program=0 + +directed_instr_1=riscv_jal_instr,70 + +enable_x_extension=1 + +tvec_alignment=8 + iterations: 2 + gen_test: cva6_instr_base_test_c + rtl_test: core_base_test + - test: riscv_arithmetic_basic_test_no_comp description: > Arithmetic instruction test, no load/store/branch instructions no compressed @@ -248,14 +295,16 @@ gcc_opts: > -mno-strict-align gen_opts: > - +instr_cnt=300 - +num_of_sub_program=5 + +instr_cnt=100 + +num_of_sub_program=0 + +no_branch_jump=1 + +no_data_page=0 +directed_instr_0=riscv_load_store_rand_instr_stream,20 +directed_instr_1=riscv_load_store_hazard_instr_stream,20 - +directed_instr_2=riscv_multi_page_load_store_instr_stream,5 - +directed_instr_3=riscv_mem_region_stress_test,5 +enable_unaligned_load_store=1 +tvec_alignment=8 + +disable_compressed_instr=1 + +enable_x_extension=1 iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test @@ -404,3 +453,54 @@ iterations: 2 gen_test: cva6_instr_base_test_c rtl_test: core_base_test + +- test: riscv_arithmetic_basic_same_reg_test + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=1000 + +num_of_sub_program=0 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_same_reg=1 + +disable_compressed_instr=1 + iterations: 2 + gen_test: cva6_instr_hazard_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_hazard_rdrs1_test + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=1000 + +num_of_sub_program=0 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_rdrs1_hazard=1 + +disable_compressed_instr=1 + iterations: 2 + gen_test: cva6_instr_hazard_test_c + rtl_test: core_base_test + +- test: riscv_arithmetic_basic_hazard_rdrs2_test + description: > + Arithmetic instruction test, no load/store/branch instructions no compressed + gen_opts: > + +instr_cnt=1000 + +num_of_sub_program=0 + +no_fence=1 + +no_data_page=1 + +no_branch_jump=1 + +boot_mode=m + +no_csr_instr=1 + +enable_rdrs2_hazard=1 + +disable_compressed_instr=1 + iterations: 2 + gen_test: cva6_instr_hazard_test_c + rtl_test: core_base_test From 6801ac2bba42e2956d7c7ea19a5fa8a004ee9bf7 Mon Sep 17 00:00:00 2001 From: Ayoub Jalali Date: Thu, 13 Jul 2023 10:47:55 +0200 Subject: [PATCH 2/4] CVXIF : Add job for xif tests --- .gitlab-ci/cva6.yml | 72 +++++++++++++++++++++++++++++++++++++++------ 1 file changed, 63 insertions(+), 9 deletions(-) diff --git a/.gitlab-ci/cva6.yml b/.gitlab-ci/cva6.yml index 66ed23c368..93dcf82ca5 100644 --- a/.gitlab-ci/cva6.yml +++ b/.gitlab-ci/cva6.yml @@ -447,19 +447,22 @@ pub_generated_tests: matrix: - list_num: 1 DASHBOARD_JOB_TITLE: "Generated Random Arithmetic tests" - DASHBOARD_JOB_DESCRIPTION: "Generate Random Arithmetic tests using the RISCV-DV" + DASHBOARD_JOB_DESCRIPTION: "Generate Random Arithmetic tests using CVA6-DV" - list_num: 2 - DASHBOARD_JOB_TITLE: "Generated CSR tests" - DASHBOARD_JOB_DESCRIPTION: "Generate Random CSR tests using the RISCV-DV" + DASHBOARD_JOB_TITLE: "Generated Hazard Arithmetic tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Hazard register (RAW) Arithmetic tests using CVA6-DV" - list_num: 3 - DASHBOARD_JOB_TITLE: "Generated MMU tests" - DASHBOARD_JOB_DESCRIPTION: "Generate Random MMU tests using the RISCV-DV" + DASHBOARD_JOB_TITLE: "Generated CSR tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random CSR tests using CVA6-DV" - list_num: 4 - DASHBOARD_JOB_TITLE: "Generated Random Load_store tests" - DASHBOARD_JOB_DESCRIPTION: "Generate Random Load_store tests using the RISCV-DV" + DASHBOARD_JOB_TITLE: "Generated MMU tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random MMU tests using CVA6-DV" - list_num: 5 + DASHBOARD_JOB_TITLE: "Generated Random Load_store tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random Load_store tests using CVA6-DV" + - list_num: 6 DASHBOARD_JOB_TITLE: "Generated Jump tests" - DASHBOARD_JOB_DESCRIPTION: "Generate Random Arithmetic Jump tests using the RISCV-DV" + DASHBOARD_JOB_DESCRIPTION: "Generate Random Arithmetic Jump tests using CVA6-DV" script: - mkdir -p artifacts/coverage - source ./cva6/regress/dv-generated-tests.sh @@ -473,6 +476,31 @@ pub_generated_tests: artifacts: expire_in: 3 week +pub_generated_xif_tests: + tags: [$TAGS_RUNNER] + extends: + - .verif_test + variables: + DASHBOARD_SORT_INDEX: 12 + DASHBOARD_JOB_CATEGORY: "Code Coverage" + parallel: + matrix: + - list_num: 1 + DASHBOARD_JOB_TITLE: "Generated Random xif tests" + DASHBOARD_JOB_DESCRIPTION: "Generate Random tests for cvxif using CVA6-DV" + script: + - mkdir -p artifacts/coverage + - source ./cva6/regress/dv-generated-xif-tests.sh + - mv cva6/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage + - mv cva6/sim/seedlist.yaml artifacts/coverage + - python3 .gitlab-ci/scripts/report_pass.py + rules: + - when: manual + allow_failure: true + timeout: 4h + artifacts: + expire_in: 3 week + pub_directed_isacov-tests: tags: [$TAGS_RUNNER] extends: @@ -497,6 +525,30 @@ pub_directed_isacov-tests: artifacts: expire_in: 3 week +pub_directed_xif-tests: + tags: [$TAGS_RUNNER] + extends: + - .verif_test + variables: + DASHBOARD_SORT_INDEX: 15 + DASHBOARD_JOB_CATEGORY: "Functional Coverage" + parallel: + matrix: + - list_num: 0 + DASHBOARD_JOB_TITLE: "Directed tests" + DASHBOARD_JOB_DESCRIPTION: "Execute directed tests to improve functional coverage of cvxif" + script: + - mkdir -p artifacts/coverage + - source ./cva6/regress/dv-generated-xif-tests.sh + - mv cva6/sim/vcs_results/default/vcs.d/simv.vdb artifacts/coverage + - python3 .gitlab-ci/scripts/report_pass.py + rules: + - when: manual + allow_failure: true + timeout: 4h + artifacts: + expire_in: 3 week + pub_fpga-boot: tags: [fpga,shell] extends: @@ -530,10 +582,12 @@ code_coverage-report: - *initjob - pub_generated_tests - pub_directed_isacov-tests + - pub_generated_xif_tests + - pub_directed_xif-tests variables: DASHBOARD_JOB_TITLE: "Report merge coverage" DASHBOARD_JOB_DESCRIPTION: "Report merge coverage of generated tests" - DASHBOARD_SORT_INDEX: 12 + DASHBOARD_SORT_INDEX: 14 DASHBOARD_JOB_CATEGORY: "Code Coverage" script: - echo $SYN_VCS_BASHRC; source $SYN_VCS_BASHRC From 1ddf160c510325454afd8c3c6dd2b9a039137820 Mon Sep 17 00:00:00 2001 From: Ayoub Jalali Date: Mon, 17 Jul 2023 13:25:06 +0200 Subject: [PATCH 3/4] CVA6-DV : Add hazard data test generation and remove U & S mode section generation --- cva6/env/corev-dv/cva6_instr_gen_config.sv | 18 +++++- cva6/env/corev-dv/cva6_instr_hazard_test.sv | 61 ++++++++++++++++++ cva6/env/corev-dv/cva6_instr_test_pkg.sv | 2 + cva6/env/corev-dv/cva6_reg_hazard_stream.sv | 62 +++++++++++++++++++ .../target/rv32imc/riscv_core_setting.sv | 2 +- 5 files changed, 143 insertions(+), 2 deletions(-) create mode 100644 cva6/env/corev-dv/cva6_instr_hazard_test.sv create mode 100644 cva6/env/corev-dv/cva6_reg_hazard_stream.sv diff --git a/cva6/env/corev-dv/cva6_instr_gen_config.sv b/cva6/env/corev-dv/cva6_instr_gen_config.sv index 6e60e06109..05aab13db6 100644 --- a/cva6/env/corev-dv/cva6_instr_gen_config.sv +++ b/cva6/env/corev-dv/cva6_instr_gen_config.sv @@ -26,15 +26,31 @@ class cva6_instr_gen_config_c extends riscv_instr_gen_config; //----------------------------------------------------------------------------- // cvxif extension support - bit enable_x_extension ; + bit enable_x_extension; + bit enable_rdrs1_hazard; + bit enable_rdrs2_hazard; + bit enable_same_reg; + + constraint hazard_reg_c { + if (enable_same_reg) { + enable_rdrs1_hazard == 1'b0; + enable_rdrs2_hazard == 1'b0; + } + } `uvm_object_utils_begin(cva6_instr_gen_config_c) `uvm_field_int(enable_x_extension, UVM_DEFAULT) + `uvm_field_int(enable_rdrs1_hazard, UVM_DEFAULT) + `uvm_field_int(enable_rdrs2_hazard, UVM_DEFAULT) + `uvm_field_int(enable_same_reg, UVM_DEFAULT) `uvm_object_utils_end function new (string name = ""); super.new(name); get_bool_arg_value("+enable_x_extension=", enable_x_extension); + get_bool_arg_value("+enable_rdrs1_hazard=", enable_rdrs1_hazard); + get_bool_arg_value("+enable_rdrs2_hazard=", enable_rdrs2_hazard); + get_bool_arg_value("+enable_same_reg=", enable_same_reg); endfunction endclass : cva6_instr_gen_config_c diff --git a/cva6/env/corev-dv/cva6_instr_hazard_test.sv b/cva6/env/corev-dv/cva6_instr_hazard_test.sv new file mode 100644 index 0000000000..2652dbf5e9 --- /dev/null +++ b/cva6/env/corev-dv/cva6_instr_hazard_test.sv @@ -0,0 +1,61 @@ +/* + * Copyright 2018 Google LLC + * Copyright 2020 OpenHW Group + * Copyright 2023 Thales + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +//------------------------------------------------------------------------------ +// CORE-V instruction generator base test: +// - extension of the RISC-V instruction generator base test. +// +//------------------------------------------------------------------------------ + +class cva6_instr_hazard_test_c extends riscv_instr_base_test; + + `uvm_component_utils(cva6_instr_hazard_test_c) + + function new(string name="", uvm_component parent=null); + super.new(name, parent); + endfunction + + virtual function void build_phase(uvm_phase phase); + override_asm_program_gen(); + override_gen_config(); + override_rand_stream(); + super.build_phase(phase); + endfunction + + virtual function void override_asm_program_gen(); + `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) + uvm_factory::get().set_type_override_by_type(riscv_asm_program_gen::get_type(), + cva6_asm_program_gen_c::get_type()); + `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + endfunction + + virtual function void override_gen_config(); + `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) + uvm_factory::get().set_type_override_by_type(riscv_instr_gen_config::get_type(), + cva6_instr_gen_config_c::get_type()); + `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + endfunction + + virtual function void override_rand_stream(); + `uvm_info("CVA6_DV", $sformatf("Overriding ..."), UVM_LOW) + uvm_factory::get().set_type_override_by_type(riscv_rand_instr_stream::get_type(), + cva6_reg_hazard_stream_c::get_type()); + `uvm_info("CVA6_DV", $sformatf("Overrid done "), UVM_LOW) + endfunction + +endclass : cva6_instr_hazard_test_c diff --git a/cva6/env/corev-dv/cva6_instr_test_pkg.sv b/cva6/env/corev-dv/cva6_instr_test_pkg.sv index df23d5ca7b..6019226563 100644 --- a/cva6/env/corev-dv/cva6_instr_test_pkg.sv +++ b/cva6/env/corev-dv/cva6_instr_test_pkg.sv @@ -18,8 +18,10 @@ package cva6_instr_test_pkg; import cva6_signature_pkg::*; `include "cva6_instr_gen_config.sv" + `include "cva6_reg_hazard_stream.sv" `include "cva6_asm_program_gen.sv" `include "cva6_instr_base_test.sv" + `include "cva6_instr_hazard_test.sv" `include "cvxif_custom_instr.sv" `include "rv32x_instr.sv" diff --git a/cva6/env/corev-dv/cva6_reg_hazard_stream.sv b/cva6/env/corev-dv/cva6_reg_hazard_stream.sv new file mode 100644 index 0000000000..0b4ff473c5 --- /dev/null +++ b/cva6/env/corev-dv/cva6_reg_hazard_stream.sv @@ -0,0 +1,62 @@ +// class for hazard instruction stream (RAW) +// that means destination register of previous instruction is the same source register of the current instruction + +class cva6_reg_hazard_stream_c extends riscv_rand_instr_stream; + + `uvm_object_utils(cva6_reg_hazard_stream_c) + + string label; + + function new(string name = ""); + super.new(name); + endfunction + + virtual function void gen_instr(bit no_branch = 1'b0, bit no_load_store = 1'b1, + bit is_debug_program = 1'b0); + riscv_reg_t prev_reg; + cva6_instr_gen_config_c cfg_cva6; + `DV_CHECK_FATAL($cast(cfg_cva6, cfg), "Could not cast cfg into cfg_cva6") + setup_allowed_instr(no_branch, no_load_store); + foreach(instr_list[i]) begin + if (i == 0) begin + randomize_instr(instr_list[i], is_debug_program); + prev_reg = instr_list[i].rd; + end + else if (i >= 1) begin + randomize_instr(instr_list[i], is_debug_program); + if (!instr_list[i].is_compressed) begin + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr_list[i], + if (has_rs1 && cfg_cva6.enable_rdrs1_hazard) { + instr_list[i].rs1 == prev_reg; + } + if (has_rs2 && cfg_cva6.enable_rdrs2_hazard) { + instr_list[i].rs2 == prev_reg; + } + if (cfg_cva6.enable_same_reg) { + instr_list[i].rd == instr_list[i].rs1; + instr_list[i].rs1 == instr_list[i].rs2; + }) + prev_reg = instr_list[i].rd; + end + else begin + `DV_CHECK_RANDOMIZE_WITH_FATAL(instr_list[i], + if (instr_list[i-1].rd inside {[S0:A5]}) { + if (has_rs1 && cfg_cva6.enable_rdrs1_hazard) { + instr_list[i].rs1 == prev_reg; + } + if (has_rs2 && cfg_cva6.enable_rdrs2_hazard) { + instr_list[i].rs2 == prev_reg; + }}) + prev_reg = instr_list[i].rd; + end + end + end + // Do not allow branch instruction as the last instruction because there's no + // forward branch target + while (instr_list[$].category == BRANCH) begin + void'(instr_list.pop_back()); + if (instr_list.size() == 0) break; + end + endfunction + +endclass diff --git a/cva6/env/corev-dv/target/rv32imc/riscv_core_setting.sv b/cva6/env/corev-dv/target/rv32imc/riscv_core_setting.sv index 9cbbe98d96..0ebba66baf 100644 --- a/cva6/env/corev-dv/target/rv32imc/riscv_core_setting.sv +++ b/cva6/env/corev-dv/target/rv32imc/riscv_core_setting.sv @@ -24,7 +24,7 @@ parameter int XLEN = 32; parameter satp_mode_t SATP_MODE = BARE; // Supported Privileged mode -privileged_mode_t supported_privileged_mode[] = {USER_MODE, SUPERVISOR_MODE, MACHINE_MODE}; +privileged_mode_t supported_privileged_mode[] = {MACHINE_MODE}; // Unsupported instructions riscv_instr_name_t unsupported_instr[]; From 8148bbb8db0703b0ba86d91747227b6ee566bfba Mon Sep 17 00:00:00 2001 From: Ayoub Jalali Date: Thu, 27 Jul 2023 14:25:00 +0200 Subject: [PATCH 4/4] CVXIF:Add directed test in supervisor and user mode --- cva6/tests/custom/cv_xif/cvxif_macros.h | 12 ++-- cva6/tests/custom/cv_xif/cvxif_s_mode.S | 73 +++++++++++++++++++++++++ cva6/tests/custom/cv_xif/cvxif_u_mode.S | 73 +++++++++++++++++++++++++ cva6/tests/testlist_cvxif.yaml | 26 ++++++--- 4 files changed, 170 insertions(+), 14 deletions(-) create mode 100644 cva6/tests/custom/cv_xif/cvxif_s_mode.S create mode 100644 cva6/tests/custom/cv_xif/cvxif_u_mode.S diff --git a/cva6/tests/custom/cv_xif/cvxif_macros.h b/cva6/tests/custom/cv_xif/cvxif_macros.h index 75aa131d13..f7e4448ce8 100644 --- a/cva6/tests/custom/cv_xif/cvxif_macros.h +++ b/cva6/tests/custom/cv_xif/cvxif_macros.h @@ -10,12 +10,10 @@ #define LOAD_RS(rs,value) li rs, value #define COMP_RS(rs1,rs2,rd) xor rd, rs1, rs2 -#define CUS_ADD(rs1,rs2,rs3,rd) .word 0b##0000000##rs2####rs1##001##rd##1111011 -#define CUS_NOP(rs1,rs2,rs3,rd) .word 0b##0000000##00000####00000##000##00000##1111011 -#define CUS_NOP_EXC(rs1,rs2,rs3,rd) .word 0b##0100000##00000####00000##000##00000##1111011 -#define CUS_ISS_EXC(rs1,rs2,rs3,rd) .word 0b##1100000##00000####00000##010##00000##1111011 +#define CUS_ADD(rs1,rs2,rd) .word 0b##0000000##rs2####rs1##001##rd##1111011 +#define CUS_NOP(rs1,rs2,rd) .word 0b##0000000##00000####00000##000##00000##1111011 #define CUS_ADD_RS3(rs1,rs2,rs3,rd) .word 0b##rs3##01##rs2####rs1##000##rd##1111011 -#define CUS_ADD_MULTI(rs1,rs2,rs3,rd) .word 0b##0001000##rs2####rs1##000##rd##1111011 +#define CUS_ADD_MULTI(rs1,rs2,rd) .word 0b##0001000##rs2####rs1##000##rd##1111011 #define CUS_EXC(rs1,rs2,rs3,rd) .word 0b####1100000##rs2####rs1##010##rd##1111011 -#define CUS_M_ADD(rs1,rs2,rs3,rd) .word 0b####0000010##rs2####rs1##011##rd##1111011 -#define CUS_S_ADD(rs1,rs2,rs3,rd) .word 0b####0000110##rs2####rs1##001##rd##1111011 +#define CUS_U_ADD(rs1,rs2,rd) .word 0b####0000010##rs2####rs1##000##rd##1111011 +#define CUS_S_ADD(rs1,rs2,rd) .word 0b####0000110##rs2####rs1##000##rd##1111011 diff --git a/cva6/tests/custom/cv_xif/cvxif_s_mode.S b/cva6/tests/custom/cv_xif/cvxif_s_mode.S new file mode 100644 index 0000000000..2da7522374 --- /dev/null +++ b/cva6/tests/custom/cv_xif/cvxif_s_mode.S @@ -0,0 +1,73 @@ +# Copyright 2023 Thales DIS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +#include "cvxif_macros.h" + +#***************************************************************************** +# cvxif_s_mode.S +#----------------------------------------------------------------------------- +# + + .globl main +main: + ## set start address range t0 x7 + la x7, supervisor_code + li x28, 0x10000 + add x7, x7, x28 + # Enable R,W,X,TOR IN PMPCFG CSR t0 x8 + li x8, 0x0F + #set PMPADDR0 CSR with x7 + csrw 0x3B0, x7 + # set PMPCFG0 CSR with x8 + csrw 0x3A0, x8 + + # Set the MPP field to supervisor mode (1) + li x29, 0b01 + slli x29, x29, 11 + or x28, x28, x29 + + # Write the modified MSTATUS value back to the CSR + csrw 0x300, x28 + + # Load address of supervisor code + la x28, supervisor_code + #set MEPC register to address of supervisor code + csrw 0x341, x28 + + csrr x31, 0x300 + mret +supervisor_code: + + CUS_S_ADD(01010,01010,01011); + CUS_S_ADD(01010,11111,11010); + CUS_ADD_MULTI(01010,01010,01011); + CUS_ADD(11010,11001,11011); + CUS_ADD(01010,01010,01011); + CUS_S_ADD(10000,00010,00000); + CUS_S_ADD(11111,11110,11111); + CUS_S_ADD(00000,01010,01011); + CUS_S_ADD(01010,01010,01011); + CUS_ADD_MULTI(01010,00000,01011); + CUS_S_ADD(11111,11111,01011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/cva6/tests/custom/cv_xif/cvxif_u_mode.S b/cva6/tests/custom/cv_xif/cvxif_u_mode.S new file mode 100644 index 0000000000..fd03ebe8b4 --- /dev/null +++ b/cva6/tests/custom/cv_xif/cvxif_u_mode.S @@ -0,0 +1,73 @@ +# Copyright 2023 Thales DIS +# +# Licensed under the Solderpad Hardware Licence, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# SPDX-License-Identifier: Apache-2.0 WITH SHL-2.0 +# You may obtain a copy of the License at https://solderpad.org/licenses/ +# +# Original Author: Ayoub JALALI (ayoub.jalali@external.thalesgroup.com) + +#include "cvxif_macros.h" + +#***************************************************************************** +# cvxif_s_mode.S +#----------------------------------------------------------------------------- +# + + .globl main +main: + ## set start address range t0 x7 + la x7, user_code + li x28, 0x10000 + add x7, x7, x28 + # Enable R,W,X,TOR IN PMPCFG CSR t0 x8 + li x8, 0x0F + #set PMPADDR0 CSR with x7 + csrw 0x3B0, x7 + # set PMPCFG0 CSR with x8 + csrw 0x3A0, x8 + + # Set the MPP field to user mode (0) + li x29, 0b00 + slli x29, x29, 11 + or x28, x28, x29 + + # Write the modified MSTATUS value back to the CSR + csrw 0x300, x28 + + # Load address of user code + la x28, user_code + #set MEPC register to address of user code + csrw 0x341, x28 + + csrr x31, 0x300 + mret +user_code: + + CUS_U_ADD(01010,01010,01011); + CUS_U_ADD(01010,11111,11010); + CUS_ADD_MULTI(01010,01010,01011); + CUS_ADD(11010,11001,11011); + CUS_ADD(01010,01010,01011); + CUS_U_ADD(10000,00010,00000); + CUS_U_ADD(11111,11110,11111); + CUS_U_ADD(00000,01010,01011); + CUS_U_ADD(01010,01010,01011); + CUS_ADD_MULTI(01010,00000,01011); + CUS_U_ADD(11111,11111,01011); + +# (example of) final self-check test + li a0, 0xCAFE; + li a1, 0xCAFE; + xor a2, a0, a1; + beqz a2, pass; + +fail: + # Failure post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; + +pass: + # Success post-processing (messages, ecall setup etc.) + li a0, 0x0; + jal exit; diff --git a/cva6/tests/testlist_cvxif.yaml b/cva6/tests/testlist_cvxif.yaml index 45d08d3336..f8861a1025 100644 --- a/cva6/tests/testlist_cvxif.yaml +++ b/cva6/tests/testlist_cvxif.yaml @@ -26,43 +26,55 @@ # -------------------------------------------------------------------------------- - test: cvxif_add_nop - iterations: 1 + iterations: 0 path_var: TESTS_PATH gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" asm_tests: /custom/cv_xif/cvxif_add_nop.S - test: cvxif_multi - iterations: 1 + iterations: 0 path_var: TESTS_PATH gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" asm_tests: /custom/cv_xif/cvxif_multi.S - test: cvxif_rs3 - iterations: 1 + iterations: 0 path_var: TESTS_PATH gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" asm_tests: /custom/cv_xif/cvxif_rs3.S - test: cvxif_exc - iterations: 1 + iterations: 0 path_var: TESTS_PATH gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" asm_tests: /custom/cv_xif/cvxif_exc.S - test: cvxif_illegal - iterations: 1 + iterations: 0 path_var: TESTS_PATH gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" asm_tests: /custom/cv_xif/cvxif_illegal.S - test: cvxif_nopexc - iterations: 1 + iterations: 0 path_var: TESTS_PATH gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" asm_tests: /custom/cv_xif/cvxif_nopexc.S - test: cvxif_issexc - iterations: 1 + iterations: 0 path_var: TESTS_PATH gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld" asm_tests: /custom/cv_xif/cvxif_issexc.S + +- test: cvxif_s_mode + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: /custom/cv_xif/cvxif_s_mode.S + +- test: cvxif_u_mode + iterations: 1 + path_var: TESTS_PATH + gcc_opts: "-static -mcmodel=medany -fvisibility=hidden -nostdlib -nostartfiles ../tests/custom/common/syscalls.c ../tests/custom/common/crt.S -I../tests/custom/env -I../tests/custom/common -T ../tests/custom/common/test.ld -lgcc" + asm_tests: /custom/cv_xif/cvxif_u_mode.S