From a23d10f294aec6a98ef9ff3fd0331a8c662ac437 Mon Sep 17 00:00:00 2001 From: Ayoub Jalali Date: Fri, 4 Aug 2023 16:42:49 +0200 Subject: [PATCH] CVXIF : Fix cus_exc format & invalid values --- cva6/env/uvme/cvxif_vseq/custom_instruction.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/cva6/env/uvme/cvxif_vseq/custom_instruction.rst b/cva6/env/uvme/cvxif_vseq/custom_instruction.rst index 3d9a09b9b4..ca973d2600 100644 --- a/cva6/env/uvme/cvxif_vseq/custom_instruction.rst +++ b/cva6/env/uvme/cvxif_vseq/custom_instruction.rst @@ -87,14 +87,14 @@ All instructions use opcode `CUSTOM_3`(0x7b, 0b111_1011). - **CUS_EXC**: Custom Exception - **Format**: cus_exc rd, rs1, rs2 -> |1100000|rs2|rs1|010|rd|111_1011| + **Format**: cus_exc rs1 -> |1100000|00000|rs1|010|00000|111_1011| **Description**: raise an exception. **Pseudocode**: mcause[5:0] = rs1 - **Invalid values**: rd = 0x0 & rs2 = 0x0 + **Invalid values**: NONE - **Exception raised**: raise an exception based on the rs1 register address,also raised an illegal instruction exception if rd != 0x0 or rs2 != 0x0 + **Exception raised**: raise an exception based on the rs1 register address. When a CV-X-IF exception is raised, mcause[5:0] of the corresponding CORE-V hart is assumed set to exccode[5:0] of CV-X-IF.