From 25edcad6f4a8323a9d70c03c4011bdedf34dd2ff Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Mon, 8 Jul 2024 13:50:31 +0200 Subject: [PATCH 1/7] updated GH links for future release --- cv32e40p/docs/VerifPlans/README.md | 42 +++++++++++++++--------------- 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/cv32e40p/docs/VerifPlans/README.md b/cv32e40p/docs/VerifPlans/README.md index e8709b7b64..518e9c7b90 100644 --- a/cv32e40p/docs/VerifPlans/README.md +++ b/cv32e40p/docs/VerifPlans/README.md @@ -32,27 +32,27 @@ Under the heading `Link`, the name shown corresponds to the filename of the vpla | Category | Feature | VPlan Status | Review Status | Comment | Link | |---------------------|----------------|--------------|---------------|---------|------| -| **Base Instruction Set** | RV32IMC + F + Zfinx + Zifencei | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| **Interrupts** | CLINT | v1-updated | Complete | Addition of missing XPULP / F / Zfinx interrupts | [CV32E40Pv2_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40Pv2_interrupts.xlsx "Interrupts Vplan")| -| **Debug & Trace** | Debug | v1-reused | Complete | Missing XPULP-specific debug are in a separate vplan | [CV32E40Pv2_debug.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40Pv2_debug.xlsx "Debug Vplan")| -| **Privileged Spec** | CSRs / Zicsr | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| **Micro-architecture** | OBI | v1-reused | Complete | | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "OBI Vplan") | -| | Pipeline / Sleep Unit | v1-reused | Complete | | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") | -| | FPU Register File | v2-sim-new | Complete | | [CV32E40Pv2_FPU_register_file.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx "FPU Reg. File Vplan") | -| **Additional ISA** | F / Zfinx | v2-sim-new | Complete | Includes uncoverable items from formal verification | [CV32E40Pv2_F-Zfinx-instructions.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40Pv2_F-Zfinx-instructions.xlsx "Add. F/Zfinx Vplan") | -| **XPULP** | Post-Increment Load/Store (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | Post-Increment Load/Store (Simulation) | v2-sim-new | Complete | Addition of "pipeline" with simulation (preceeding F multicycle) | [CV32E40Pv2_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx "Post-Inc Load/Store simu Vplan") | -| | Bitmanipulation (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | Bitmanipulation (Simulation) | v2-sim-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-bitmanipulations.xlsx "Bitmanip simu Vplan") | -| | General ALU (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | General ALU (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-general-alu.xlsx "General ALU simu Vplan") | -| | Immediate Branching (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | Immediate Branching (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx "Imm Branching simu Vplan") | -| | MAC (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | MAC (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx "MAC simu Vplan") | -| | SIMD (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | SIMD (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx "SIMD simu Vplan") | -| | HWLoop (Simulation) | v2-sim-new | Complete | Feature not test at all in formal verification | [CV32E40Pv2_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p/dev/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-hwloop.xlsx "HWLoop Vplan") | +| **Base Instruction Set** | RV32IMC + F + Zfinx + Zifencei | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| **Interrupts** | CLINT | v1-updated | Complete | Addition of missing XPULP / F / Zfinx interrupts | [CV32E40Pv2_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40Pv2_interrupts.xlsx "Interrupts Vplan")| +| **Debug & Trace** | Debug | v1-reused | Complete | Missing XPULP-specific debug are in a separate vplan | [CV32E40Pv2_debug.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40Pv2_debug.xlsx "Debug Vplan")| +| **Privileged Spec** | CSRs / Zicsr | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| **Micro-architecture** | OBI | v1-reused | Complete | | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "OBI Vplan") | +| | Pipeline / Sleep Unit | v1-reused | Complete | | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") | +| | FPU Register File | v2-sim-new | Complete | | [CV32E40Pv2_FPU_register_file.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx "FPU Reg. File Vplan") | +| **Additional ISA** | F / Zfinx | v2-sim-new | Complete | Includes uncoverable items from formal verification | [CV32E40Pv2_F-Zfinx-instructions.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40Pv2_F-Zfinx-instructions.xlsx "Add. F/Zfinx Vplan") | +| **XPULP** | Post-Increment Load/Store (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | Post-Increment Load/Store (Simulation) | v2-sim-new | Complete | Addition of "pipeline" with simulation (preceeding F multicycle) | [CV32E40Pv2_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx "Post-Inc Load/Store simu Vplan") | +| | Bitmanipulation (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | Bitmanipulation (Simulation) | v2-sim-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-bitmanipulations.xlsx "Bitmanip simu Vplan") | +| | General ALU (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | General ALU (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-general-alu.xlsx "General ALU simu Vplan") | +| | Immediate Branching (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | Immediate Branching (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx "Imm Branching simu Vplan") | +| | MAC (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | MAC (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx "MAC simu Vplan") | +| | SIMD (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | SIMD (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx "SIMD simu Vplan") | +| | HWLoop (Simulation) | v2-sim-new | Complete | Feature not test at all in formal verification | [CV32E40Pv2_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-hwloop.xlsx "HWLoop Vplan") |
From f0ac265138f585c010ded611ae7f95b27bd71aaa Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Wed, 10 Jul 2024 09:37:47 +0200 Subject: [PATCH 2/7] added missing links --- cv32e40p/docs/VerifPlans/README.md | 74 +++++++++++++++--------------- 1 file changed, 37 insertions(+), 37 deletions(-) diff --git a/cv32e40p/docs/VerifPlans/README.md b/cv32e40p/docs/VerifPlans/README.md index 518e9c7b90..2011ce9bc9 100644 --- a/cv32e40p/docs/VerifPlans/README.md +++ b/cv32e40p/docs/VerifPlans/README.md @@ -10,8 +10,8 @@ Below are two different chapters describing verification plans status and direct ## Short verification methodology introduction For CV32E40Pv2 verification, the formal verification methodology has been chosen over the stimuli-based simulation that was done for v1 version of the core. However, full verification closure is not feasible using only formal verification due to complexity of specific scenarios. All these specific uncoverable scenarios from formal verification are then exercised by stimuli-based simulation using a reference model of the core. These scenarios along with formal assertions are described inside verifications plans, for which details are given in a table below. Regarding already available v1 plans, their re-use or not is specified in this table. -RISC-V ISA Formal Verification methodology is described [here](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p/dev/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_RISCV_vPlan_v1.1.pdf). -Setup and script files to launch RISC-V ISA Formal Verification using Siemens Questa Processor tool are available [here](https://github.com/openhwgroup/cv32e40p/tree/dev/scripts/riscv_isa_formal). +RISC-V ISA Formal Verification methodology is described [here](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_RISCV_vPlan_v1.1.pdf). +Setup and script files to launch RISC-V ISA Formal Verification using Siemens Questa Processor tool are available [here](https://github.com/openhwgroup/cv32e40p/tree/cv32e40p_v1.8.3/scripts/riscv_isa_formal). ## Verification Plan Status @@ -32,27 +32,27 @@ Under the heading `Link`, the name shown corresponds to the filename of the vpla | Category | Feature | VPlan Status | Review Status | Comment | Link | |---------------------|----------------|--------------|---------------|---------|------| -| **Base Instruction Set** | RV32IMC + F + Zfinx + Zifencei | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| **Interrupts** | CLINT | v1-updated | Complete | Addition of missing XPULP / F / Zfinx interrupts | [CV32E40Pv2_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40Pv2_interrupts.xlsx "Interrupts Vplan")| -| **Debug & Trace** | Debug | v1-reused | Complete | Missing XPULP-specific debug are in a separate vplan | [CV32E40Pv2_debug.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40Pv2_debug.xlsx "Debug Vplan")| -| **Privileged Spec** | CSRs / Zicsr | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| **Micro-architecture** | OBI | v1-reused | Complete | | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "OBI Vplan") | -| | Pipeline / Sleep Unit | v1-reused | Complete | | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") | -| | FPU Register File | v2-sim-new | Complete | | [CV32E40Pv2_FPU_register_file.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx "FPU Reg. File Vplan") | -| **Additional ISA** | F / Zfinx | v2-sim-new | Complete | Includes uncoverable items from formal verification | [CV32E40Pv2_F-Zfinx-instructions.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40Pv2_F-Zfinx-instructions.xlsx "Add. F/Zfinx Vplan") | -| **XPULP** | Post-Increment Load/Store (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | Post-Increment Load/Store (Simulation) | v2-sim-new | Complete | Addition of "pipeline" with simulation (preceeding F multicycle) | [CV32E40Pv2_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx "Post-Inc Load/Store simu Vplan") | -| | Bitmanipulation (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | Bitmanipulation (Simulation) | v2-sim-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-bitmanipulations.xlsx "Bitmanip simu Vplan") | -| | General ALU (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | General ALU (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-general-alu.xlsx "General ALU simu Vplan") | -| | Immediate Branching (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | Immediate Branching (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx "Imm Branching simu Vplan") | -| | MAC (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | MAC (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx "MAC simu Vplan") | -| | SIMD (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | SIMD (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx "SIMD simu Vplan") | -| | HWLoop (Simulation) | v2-sim-new | Complete | Feature not test at all in formal verification | [CV32E40Pv2_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-hwloop.xlsx "HWLoop Vplan") | +| **Base Instruction Set** | RV32IMC + F + Zfinx + Zifencei | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| **Interrupts** | CLINT | v1-updated | Reviewed | Addition of missing XPULP / F / Zfinx interrupts | [CV32E40Pv2_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40Pv2_interrupts.xlsx "Interrupts Vplan")| +| **Debug & Trace** | Debug | v1-reused | Reviewed | Missing XPULP-specific debug are in a separate vplan | [CV32E40Pv2_debug.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40Pv2_debug.xlsx "Debug Vplan")| +| **Privileged Spec** | CSRs / Zicsr | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| **Micro-architecture** | OBI | v1-reused | Reviewed | | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "OBI Vplan") | +| | Pipeline / Sleep Unit | v1-reused | Reviewed | | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") | +| | FPU Register File | v2-sim-new | Reviewed | | [CV32E40Pv2_FPU_register_file.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx "FPU Reg. File Vplan") | +| **Additional ISA** | F / Zfinx | v2-sim-new | Reviewed | Includes uncoverable items from formal verification | [CV32E40Pv2_F-Zfinx-instructions.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40Pv2_F-Zfinx-instructions.xlsx "Add. F/Zfinx Vplan") | +| **XPULP** | Post-Increment Load/Store (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | Post-Increment Load/Store (Simulation) | v2-sim-new | Reviewed | Addition of "pipeline" with simulation (preceeding F multicycle) | [CV32E40Pv2_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx "Post-Inc Load/Store simu Vplan") | +| | Bitmanipulation (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | Bitmanipulation (Simulation) | v2-sim-new | Reviewed | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-bitmanipulations.xlsx "Bitmanip simu Vplan") | +| | General ALU (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | General ALU (Simulation) | v2-simu-new | Reviewed | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-general-alu.xlsx "General ALU simu Vplan") | +| | Immediate Branching (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | Immediate Branching (Simulation) | v2-simu-new | Reviewed | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx "Imm Branching simu Vplan") | +| | MAC (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | MAC (Simulation) | v2-sim-new | Reviewed | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx "MAC simu Vplan") | +| | SIMD (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | SIMD (Simulation) | v2-sim-new | Reviewed | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx "SIMD simu Vplan") | +| | HWLoop (Simulation) | v2-sim-new | Reviewed | Feature not test at all in formal verification | [CV32E40Pv2_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-hwloop.xlsx "HWLoop Vplan") |
@@ -75,19 +75,19 @@ The tables below capture the current status of the Verification Plan for the CV3 ### Base instruction set plus standard instruction extensions -_Refer to the [VerifPlans/ISA/RV32/Simulation](https://github.com/openhwgroup/core-v-verif/tree/4bb9858cd7c58f8856ff544f53fe102c76ea9683/docs/VerifPlans/ISA/RV32/Simulation "ISA Simulation vPlans") directory for specific Verification Plan status for each supported extension._ +_Refer to the [VerifPlans/ISA/RV32/Simulation](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/docs/VerifPlans/ISA/RV32/Simulation "ISA Simulation vPlans") directory for specific Verification Plan status for each supported extension._ ### Interrupts | Feature | VPlan Status | Review Status | Comment | Link | |----------------|--------------|---------------|---------|------| -| CLINT | Captured | Complete | | [CV32E40P_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40P_interrupts.xlsx "v1 Interrupts Vplan") | +| CLINT | Captured | Complete | | [CV32E40P_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40P_interrupts.xlsx "v1 Interrupts Vplan") | | CLIC | | | Not a CV32E40P Feature | | ### Debug & Trace | Feature | VPlan Status | Review Status | Comment | Link | |----------------|--------------|---------------|---------|------| -| Debug | Captured | Complete | | [CV32E40P_debug.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40P_debug.xlsx "Debug Vplan") | +| Debug | Captured | Complete | | [CV32E40P_debug.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40P_debug.xlsx "Debug Vplan") | | Trigger module | Captured | Complete | Not a CV32E40P Feature | | | Tracer | N/A | N/A | Behavioral model, not RTL | | @@ -95,7 +95,7 @@ _Refer to the [VerifPlans/ISA/RV32/Simulation](https://github.com/openhwgroup/co | Feature | VPlan Status | Review Status | Comment | Link | |----------------|--------------|---------------|---------|------| -| CSRs | Incomplete | | | [CSR_Vplan.md](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CSR_Vplan.md "v1 CSR Vplan") | +| CSRs | Incomplete | | | [CSR_Vplan.md](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CSR_Vplan.md "v1 CSR Vplan") | | User mode | N/A| N/A | Not a CV32E40P Feature | | | PMP | N/A | N/A | Not a CV32E40P Feature | | @@ -103,22 +103,22 @@ _Refer to the [VerifPlans/ISA/RV32/Simulation](https://github.com/openhwgroup/co | Feature | VPlan Status | Review Status | Comment | Link | |----------------|--------------|---------------|---------|------| -| OBI | Complete | Reviewed | | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "v1 OBI Vplan") | -| Sleep Unit | Complete | Reviewed | Updates pending based on review feedback | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "v1 Pipeline Sleep Vplan") | -| Pipelines | Complete | Reviewed | Updates pending based on review feedback | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "v1 Pipeline Sleep Vplan") | +| OBI | Complete | Reviewed | | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "v1 OBI Vplan") | +| Sleep Unit | Complete | Reviewed | Updates pending based on review feedback | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "v1 Pipeline Sleep Vplan") | +| Pipelines | Complete | Reviewed | Updates pending based on review feedback | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "v1 Pipeline Sleep Vplan") | ### Xpulp instruction extensions **Note**: Xpulp instructions are "exercised, but not fully verified" in CV32E40P. | Feature | VPlan Status | Review Status | Comment | Link | |----------------|--------------|---------------|---------|------| -| Post-increment load/store | Preliminary draft | | | [CV32E40P_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-postinc-loadstore.xlsx "v1 Post-Inc Load/Store simu Vplan") | | -| Hardware Loop | Preliminary draft | | On-going discussions with Cores TWG | [CV32E40P_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-hwloop.xlsx "v1 HWLoop Vplan") | -| Bit Manipulation | Preliminary draft | | | [CV32E40P_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-bitmanipulations.xlsx "v1 Bitmanip simu Vplan") | -| General ALU | Preliminary draft | | | [CV32E40P_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-general-alu.xlsx "v1 General ALU simu Vplan") | -| Immediate branching | Preliminary draft | | | [CV32E40P_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-immediate-branching.xlsx "v1 Imm Branching simu Vplan") | -| SIMD | Preliminary draft | | | [CV32E40P_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-packed-simd.xlsx "v1 SIMD simu Vplan") | -| MAC | Preliminary draft | | | [CV32E40P_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/blob/4bb9858cd7c58f8856ff544f53fe102c76ea9683/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-multiply-accumulate.xlsx "v1 MAC simu Vplan") | +| Post-increment load/store | Preliminary draft | | | [CV32E40P_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-postinc-loadstore.xlsx "v1 Post-Inc Load/Store simu Vplan") | | +| Hardware Loop | Preliminary draft | | On-going discussions with Cores TWG | [CV32E40P_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-hwloop.xlsx "v1 HWLoop Vplan") | +| Bit Manipulation | Preliminary draft | | | [CV32E40P_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-bitmanipulations.xlsx "v1 Bitmanip simu Vplan") | +| General ALU | Preliminary draft | | | [CV32E40P_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-general-alu.xlsx "v1 General ALU simu Vplan") | +| Immediate branching | Preliminary draft | | | [CV32E40P_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-immediate-branching.xlsx "v1 Imm Branching simu Vplan") | +| SIMD | Preliminary draft | | | [CV32E40P_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-packed-simd.xlsx "v1 SIMD simu Vplan") | +| MAC | Preliminary draft | | | [CV32E40P_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40P_xpulp-multiply-accumulate.xlsx "v1 MAC simu Vplan") | ### Custom circuitry From a41fc55fe7dab28465a09a520497bf84b0a9ccea Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Thu, 11 Jul 2024 16:13:00 +0200 Subject: [PATCH 3/7] corrected broken links --- CONTRIBUTING.md | 10 ++++----- MergeTest.md | 59 ++++++++++++++++++++++++------------------------- 2 files changed, 34 insertions(+), 35 deletions(-) diff --git a/CONTRIBUTING.md b/CONTRIBUTING.md index 42a6b278ed..628e9d207b 100644 --- a/CONTRIBUTING.md +++ b/CONTRIBUTING.md @@ -18,11 +18,11 @@ All pull-requests to OpenHW Group git repositories must be signed-off using the `--signoff` (or `-s`) option to the git commit command (see below). ## Branches -The core-v-verif repository provides testbenches for multiple OpenHW cores. As such the core-v-verif repository uses branches for maintaining stability between -the different core testbenches as well as recognizing independent development streams. An adapted form of the Git Flow is used in this repository. +The core-v-verif repository provides testbenches for multiple OpenHW cores. As such the core-v-verif repository uses branches for maintaining stability between +the different core testbenches as well as recognizing independent development streams. An adapted form of the Git Flow is used in this repository. The following are the official branches for core-v-verif - Branch | Example (if applicable) | Usage + Branch | Example (if applicable) | Usage --------------------- | ----------------------- | ----------------------- _\_/dev | cv32e40p/dev | Main line of development for a core testbench. Most contributinos should target a dev branch. _\_/release | cv32e40p/release | Staging branch for merge dev branches into master (and vice versa). In general only OpenHW Committers will utilize these branches @@ -32,7 +32,7 @@ In most cases a contribution should be made on a _dev_ branch.
Common infrastructure fixes and updates may target the _master_ branch using the hotfix flow to directly address issues requiring timely fixes.
More information on core-v-verif branch usage can be found here: -https://github.com/openhwgroup/core-v-docs/blob/master/verif/Common/Presentations/20210311-Branches%20and%20CIs%20for%20core-v-verif.pptx +https://github.com/openhwgroup/core-v-docs/blob/master/TGs/verification-task-group/documents/presentations/20210311-Branches_and_CIs_for_core-v-verif.pptx ## The Mechanics 1. [Fork](https://help.github.com/articles/fork-a-repo/) the [core-v-verif](https://github.com/openhwgroup/core-v-verif) repository @@ -43,4 +43,4 @@ https://github.com/openhwgroup/core-v-docs/blob/master/verif/Common/Presentation 6. Commit your changes: `git commit -m 'Add some feature' --signoff`
...take note of that **--signoff**, it's important! 7. Push feature branch: `git push origin ` 8. Submit a [pull request](https://help.github.com/en/github/collaborating-with-issues-and-pull-requests/creating-a-pull-request-from-a-fork). -9. If known, it is advisable to select one or more appropriate reviewers for your PR. For hotfix PRs, request either Steve Richmond or Mike Thompson for proper review. \ No newline at end of file +9. If known, it is advisable to select one or more appropriate reviewers for your PR. For hotfix PRs, request either Steve Richmond or Mike Thompson for proper review. diff --git a/MergeTest.md b/MergeTest.md index 4e8972a092..5a70009db2 100644 --- a/MergeTest.md +++ b/MergeTest.md @@ -1,7 +1,7 @@ # Merge Test Use this file to exercise the GitHub portions of the OpenHW Group workflow. -Parts of the [OpenHW Group workflow](https://github.com/openhwgroup/core-v-docs/blob/master/verif/Common/OpenHWGroup_WorkFlow.pdf) +Parts of the [OpenHW Group workflow](https://github.com/openhwgroup/programs/blob/master/TGs/verification-task-group/documents/presentations/OpenHWGroup_WorkFlow.pdf) are modeled after Vincent Driessen's [git branching model](https://nvie.com/posts/a-successful-git-branching-model/). When you first register as a member of OpenHW, you can use this file to safely test whether you have the appropriate GitHub contributor priviledges for this repo. Try this: * Fork the repository: https://help.github.com/en/github/getting-started-with-github/fork-a-repo @@ -13,12 +13,11 @@ you first register as a member of OpenHW, you can use this file to safely test w When all of that works, you are ready to make contributions to the OpenHW Group CORE-V projects. -If you are new to git, or unfamiliar with using branches and pull-requests, have a look at our [Git Cheat Sheet](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.txt). +If you are new to git, or unfamiliar with using branches and pull-requests, have a look at our [Git Cheat Sheet](https://github.com/openhwgroup/core-v-verif/blob/master/GitCheats.md). ## Make your changes below this line. Extra marks for creativity and wit. - ### Madcat ``` /^v^\ @@ -46,39 +45,39 @@ Extra marks for creativity and wit. >_< >_< || || || || || || || || - || || || || -- Jay Thaler + || || || || -- Jay Thaler __|\_/|__ __|\_/|__ -- David Poulin /___n_n___\ /___n_n___\ ``` ### Gecko ``` - ## ## - ##### * - ###/ - ##### - *######### ########. - ######################## - ############################### - #####&@&&&&&&&&%################(((/ - %%%##########(((((((( - ( %######(((((((((((( - ( ###((((((((((((((((. - ( (((( ((((((((((((( - ( *# (((( ((((((((((((( - (( ###(((( ((((((((((((( - (( * (( (((((((((((( - /( ((((( ((((((((((( - /(( (( ((((((((((((((((((((((((( - /(( ,((((((((((((((((//(((((((((((( - //( (.( ((((((////////(((((( (( - ,//// ((( (( (((((////// ///////// - ///// ((((///// / /* - /////// (((((///// // // - ////////. /((((((///// - **///////////, *((((((((((////// - ****//////////((((((((//////// - /******************* + ## ## + ##### * + ###/ + ##### + *######### ########. + ######################## + ############################### + #####&@&&&&&&&&%################(((/ + %%%##########(((((((( + ( %######(((((((((((( + ( ###((((((((((((((((. + ( (((( ((((((((((((( + ( *# (((( ((((((((((((( + (( ###(((( ((((((((((((( + (( * (( (((((((((((( + /( ((((( ((((((((((( + /(( (( ((((((((((((((((((((((((( + /(( ,((((((((((((((((//(((((((((((( + //( (.( ((((((////////(((((( (( + ,//// ((( (( (((((////// ///////// + ///// ((((///// / /* + /////// (((((///// // // + ////////. /((((((///// + **///////////, *((((((((((////// + ****//////////((((((((//////// + /******************* ``` {signal: [ From 2fb67b56902d1f3ed6fffe4ee9224d6b9c70ffb5 Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Thu, 11 Jul 2024 16:14:30 +0200 Subject: [PATCH 4/7] corrected broken links and added a small information about cv32e40pv2 RTL freeze --- NEWS_ARCHIVE.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/NEWS_ARCHIVE.md b/NEWS_ARCHIVE.md index 66ba37f049..3c9a5188ae 100644 --- a/NEWS_ARCHIVE.md +++ b/NEWS_ARCHIVE.md @@ -1,15 +1,15 @@ ### NEWS UPDATES (going back to early 2020): +**2024-07-01**: CV32E40Pv2 has reached RTL freeze [CV32E40Pv2 final RTL Freeze status](https://github.com/openhwgroup/programs/blob/master/TGs/cores-task-group/MeetingPresentations/Cores-TG-07.01.2024.pdf) **2020-12-10**: OpenHW formally decalres [RTL Freeze for CV32E40P](https://www.openhwgroup.org/news/2020/12/10/core-v-cve4-rtl-freeze-milestone-achieved/)
-**2020-10-15**: Aldec's Riviera-PRO SystemVerilog simulator is now supported by core-v-verif. Check out the README in [mk/uvmt](https://github.com/openhwgroup/core-v-verif/tree/master/mk/uvmt#running-the-environment-with-aldec-riviera-pro-riviera) for more information. +**2020-10-15**: Aldec's Riviera-PRO SystemVerilog simulator is now supported by core-v-verif. Check out the README in [mk](https://github.com/openhwgroup/core-v-verif/tree/master/mk/#running-the-environment-with-aldec-riviera-pro-riviera) for more information.
-**2020-09-04**: a new (and _much_ better) method of specifying and organizating test-programs and simulations is now merged in. See slide "_Test Specification Updates_" in the [2020-08-31 CV32E40P project update](https://github.com/openhwgroup/core-v-docs/blob/master/verif/MeetingPresentations/20200831-CV32E40P-ProjectScheduleUpdate.pptx). +**2020-09-04**: a new (and _much_ better) method of specifying and organizating test-programs and simulations is now merged in. See slide "_Test Specification Updates_" in the [2020-08-31 CV32E40P project update](https://github.com/openhwgroup/programs/blob/master/TGs/verification-task-group/projects/CV32E40P_v1.0.0/documents/20200831-CV32E40P-ProjectScheduleUpdate.pptx).
-**2020-06-12**: a new "Board Support Package" for CV32E40P simulations is installed at `cv32/bsp`. This BSP should be used to compile/assemble your [test-programs](https://core-v-docs-verif-strat.readthedocs.io/en/latest/test_program_environment.html). The Makefiles for both the CORE testbench and UVM verification environment have been updated to use this BSP. +**2020-06-12**: a new "Board Support Package" for CV32E40P simulations is installed at `cv32/bsp`. This BSP should be used to compile/assemble your [test-programs](https://docs.openhwgroup.org/projects/core-v-verif/en/latest/test_programs.html). The Makefiles for both the CORE testbench and UVM verification environment have been updated to use this BSP.
**2020-06-02:** The [Imperas OVPsim Instruction Set Generator](http://www.ovpworld.org/) has been integrated into the UVM environment as the Referenece Model for the CV32E40(P). You will need to obtain a license from Imperas to use it.
-**2020-02-28:** The OpenHW Group CV32E40P is now live!
This repository no longer contains a local copy of the RTL. The RTL is cloned from the appropriate [core-v-cores](https://github.com/openhwgroup/core-v-cores) repository as needed. The specific branch and hash of the RTL is controlled by a set of variables in `cv32e40p/sim/Common.mk`. +**2020-02-28:** The OpenHW Group CV32E40P is now live!
This reposito of variables in `cv32e40p/sim/Common.mk`.ry no longer contains a local copy of the RTL. The RTL is cloned from the appropriate [core-v-cores](https://github.com/openhwgroup/core-v-cores) repository as needed. The specific branch and hash of the RTL is controlled by a set
**2020-02-10:** The core-v-verif repository now supports multiple cores. The previously named cv32 directory is now cv32e40p to represent the testbench for the CV32E40P core. Future cores will be verified in respectively named directories in core-v-verif as siblings to cva6 and cv32e40p. - From 62a283c6276221a0b3ea651ca3d7fbe23796fa2d Mon Sep 17 00:00:00 2001 From: Xavier Aubert Date: Thu, 11 Jul 2024 16:28:23 +0200 Subject: [PATCH 5/7] moved cv32e40pv2 RTL freeze info from news_archive to README --- NEWS_ARCHIVE.md | 1 - README.md | 1 + 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/NEWS_ARCHIVE.md b/NEWS_ARCHIVE.md index 3c9a5188ae..f9b53c53f7 100644 --- a/NEWS_ARCHIVE.md +++ b/NEWS_ARCHIVE.md @@ -1,5 +1,4 @@ ### NEWS UPDATES (going back to early 2020): -**2024-07-01**: CV32E40Pv2 has reached RTL freeze [CV32E40Pv2 final RTL Freeze status](https://github.com/openhwgroup/programs/blob/master/TGs/cores-task-group/MeetingPresentations/Cores-TG-07.01.2024.pdf) **2020-12-10**: OpenHW formally decalres [RTL Freeze for CV32E40P](https://www.openhwgroup.org/news/2020/12/10/core-v-cve4-rtl-freeze-milestone-achieved/)
**2020-10-15**: Aldec's Riviera-PRO SystemVerilog simulator is now supported by core-v-verif. Check out the README in [mk](https://github.com/openhwgroup/core-v-verif/tree/master/mk/#running-the-environment-with-aldec-riviera-pro-riviera) for more information. diff --git a/README.md b/README.md index 97d1c47f52..7e98733be2 100644 --- a/README.md +++ b/README.md @@ -23,6 +23,7 @@ Functional verification project for the CORE-V family of RISC-V cores. ## Getting Started @@ -84,8 +84,8 @@ We highly appreciate community contributions. You can get a sense of our current within a project are defined as [issues](https://github.com/openhwgroup/core-v-verif/issues) with a `task` label.

To ease our work of reviewing your contributions, please: -* Review [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/master/CONTRIBUTING.md) -and our [SV/UVM coding style guidelines](https://github.com/openhwgroup/core-v-verif/blob/master/docs/CodingStyleGuidelines.md). +* Review [CONTRIBUTING](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/CONTRIBUTING.md) +and our [SV/UVM coding style guidelines](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/docs/CodingStyleGuidelines.md). * Split large contributions into smaller commits addressing individual changes or bug fixes. Do not mix unrelated changes into the same commit! * Write meaningful commit messages. diff --git a/cv32e40p/docs/VerifPlans/README.md b/cv32e40p/docs/VerifPlans/README.md index 2011ce9bc9..f7b6d08840 100644 --- a/cv32e40p/docs/VerifPlans/README.md +++ b/cv32e40p/docs/VerifPlans/README.md @@ -32,27 +32,28 @@ Under the heading `Link`, the name shown corresponds to the filename of the vpla | Category | Feature | VPlan Status | Review Status | Comment | Link | |---------------------|----------------|--------------|---------------|---------|------| -| **Base Instruction Set** | RV32IMC + F + Zfinx + Zifencei | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| **Interrupts** | CLINT | v1-updated | Reviewed | Addition of missing XPULP / F / Zfinx interrupts | [CV32E40Pv2_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40Pv2_interrupts.xlsx "Interrupts Vplan")| -| **Debug & Trace** | Debug | v1-reused | Reviewed | Missing XPULP-specific debug are in a separate vplan | [CV32E40Pv2_debug.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40Pv2_debug.xlsx "Debug Vplan")| -| **Privileged Spec** | CSRs / Zicsr | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| **Micro-architecture** | OBI | v1-reused | Reviewed | | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "OBI Vplan") | -| | Pipeline / Sleep Unit | v1-reused | Reviewed | | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") | -| | FPU Register File | v2-sim-new | Reviewed | | [CV32E40Pv2_FPU_register_file.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx "FPU Reg. File Vplan") | -| **Additional ISA** | F / Zfinx | v2-sim-new | Reviewed | Includes uncoverable items from formal verification | [CV32E40Pv2_F-Zfinx-instructions.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40Pv2_F-Zfinx-instructions.xlsx "Add. F/Zfinx Vplan") | -| **XPULP** | Post-Increment Load/Store (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | Post-Increment Load/Store (Simulation) | v2-sim-new | Reviewed | Addition of "pipeline" with simulation (preceeding F multicycle) | [CV32E40Pv2_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx "Post-Inc Load/Store simu Vplan") | -| | Bitmanipulation (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | Bitmanipulation (Simulation) | v2-sim-new | Reviewed | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-bitmanipulations.xlsx "Bitmanip simu Vplan") | -| | General ALU (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | General ALU (Simulation) | v2-simu-new | Reviewed | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-general-alu.xlsx "General ALU simu Vplan") | -| | Immediate Branching (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | Immediate Branching (Simulation) | v2-simu-new | Reviewed | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx "Imm Branching simu Vplan") | -| | MAC (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | MAC (Simulation) | v2-sim-new | Reviewed | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx "MAC simu Vplan") | -| | SIMD (Formal) | v2-formal-new | Reviewed | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | -| | SIMD (Simulation) | v2-sim-new | Reviewed | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx "SIMD simu Vplan") | -| | HWLoop (Simulation) | v2-sim-new | Reviewed | Feature not test at all in formal verification | [CV32E40Pv2_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-hwloop.xlsx "HWLoop Vplan") | +| **Base Instruction Set** | RV32IMC + F + Zfinx + Zifencei | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| **Interrupts** | CLINT | v1-updated | Complete | Addition of missing XPULP / F / Zfinx interrupts | [CV32E40Pv2_interrupts.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/interrupts/CV32E40Pv2_interrupts.xlsx "Interrupts Vplan")| +| **Debug & Trace** | Debug | v1-reused | Complete | Missing XPULP-specific debug are in a separate vplan | [CV32E40Pv2_debug.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/debug-trace/CV32E40Pv2_debug.xlsx "Debug Vplan")| +| **Privileged Spec** | CSRs / Zicsr | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | CSRs / Zicsr | v2-sim-new | Complete | | [CV32E40Pv2_CSR_Vplan.md](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CV32E40Pv2_CSR_Vplan.md) | +| **Micro-architecture** | OBI | v1-reused | Complete | | [CV32E40P_OBI_VerifPlan.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_OBI_VerifPlan.xlsx "OBI Vplan") | +| | Pipeline / Sleep Unit | v1-reused | Complete | | [CV32E40P_Pipeline_Sleep.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40P_Pipeline_Sleep.xlsx "Pipeline Sleep Vplan") | +| | FPU Register File | v2-sim-new | Complete | | [CV32E40Pv2_FPU_register_file.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/micro_architecture/CV32E40Pv2_FPU_register_file.xlsx "FPU Reg. File Vplan") | +| **Additional ISA** | F / Zfinx | v2-sim-new | Complete | Includes uncoverable items from formal verification | [CV32E40Pv2_F-Zfinx-instructions.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/Zfinx_F_instructions/CV32E40Pv2_F-Zfinx-instructions.xlsx "Add. F/Zfinx Vplan") | +| **XPULP** | Post-Increment Load/Store (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | Post-Increment Load/Store (Simulation) | v2-sim-new | Complete | Addition of "pipeline" with simulation (preceeding F multicycle) | [CV32E40Pv2_xpulp-postinc-loadstore.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-postinc-loadstore.xlsx "Post-Inc Load/Store simu Vplan") | +| | Bitmanipulation (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | Bitmanipulation (Simulation) | v2-sim-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-bitmanipulation.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-bitmanipulations.xlsx "Bitmanip simu Vplan") | +| | General ALU (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | General ALU (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-general-alu.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-general-alu.xlsx "General ALU simu Vplan") | +| | Immediate Branching (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | Immediate Branching (Simulation) | v2-simu-new | Complete | Lowest priority as formal already checks everything needed, added because corev-dv generator will generate those instructions anyway | [CV32E40Pv2_xpulp-immediate-branching.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-immediate-branching.xlsx "Imm Branching simu Vplan") | +| | MAC (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | MAC (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-multiply-accumulate.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-multiply-accumulate.xlsx "MAC simu Vplan") | +| | SIMD (Formal) | v2-formal-new | Complete | | [CV32E40Pv2_Formal_VerificationPlans.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/RISC-V_ISA_Formal/CV32E40Pv2_Formal_VerificationPlans.xlsx) | +| | SIMD (Simulation) | v2-sim-new | Complete | Addition of missing coverage from formal (operands "toggle") | [CV32E40Pv2_xpulp-packed-simd.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-packed-simd.xlsx "SIMD simu Vplan") | +| | HWLoop (Simulation) | v2-sim-new | Complete | Feature not test at all in formal verification | [CV32E40Pv2_xpulp-hwloop.xlsx](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/docs/VerifPlans/Simulation/xpulp_instruction_extensions/CV32E40Pv2_xpulp-hwloop.xlsx "HWLoop Vplan") |
diff --git a/cv32e40p/docs/VerifPlans/Simulation/custom_circuitry/README.md b/cv32e40p/docs/VerifPlans/Simulation/custom_circuitry/README.md index 8c13877f5c..a9b0635667 100644 --- a/cv32e40p/docs/VerifPlans/Simulation/custom_circuitry/README.md +++ b/cv32e40p/docs/VerifPlans/Simulation/custom_circuitry/README.md @@ -1,2 +1,2 @@ -Placeholder directory for a specific [CV32E40P high-level feature](https://github.com/openhwgroup/core-v-verif/tree/master/doc). The Verification Plan (aka +Placeholder directory for a specific [CV32E40P high-level feature](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/doc). The Verification Plan (aka Test Plan) for this feature will be committed here as soon as is available. diff --git a/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CSR_Vplan.md b/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CSR_Vplan.md index b61859b64a..b944737cd8 100644 --- a/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CSR_Vplan.md +++ b/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CSR_Vplan.md @@ -37,7 +37,7 @@ what the core will do when a given CSR has a specific value. In RISC-V cores, access mode behavior has four dimensions: access mode, privilege, existance and field specification. These are discussed in turn, -with emphasis placed on pre-silicon functional verification (as opposed to +with emphasis placed on pre-silicon functional verification (as opposed to post-silicon use by software). #### Access Mode @@ -104,7 +104,7 @@ values) and then check that these values have the desired affect. A good exampl is ensuring that interrupts are asserted when MSTATUS[MIE] is both 0/1 and ensuring that interrupts are ignored or responded to, as appropriate. -Control register verification of RISC-V cores is not conceptually different than +Control register verification of RISC-V cores is not conceptually different than control register verification of non-processor ASIC/FPGA RTL. One difference is that in non-processor RTL, the control path (reading the writing the CSRs) is typically independent of the data path (events that are affected by control @@ -151,7 +151,7 @@ machine-mode CSRs. For example, address range 0x307 : 0x33F between Machine Trap Setup CSRs and Machine Trap Handling CSRs. ### 4 -Access mode test of all CSRs. This is a generated test based on [cv32e40p_csr_template.yaml](https://github.com/openhwgroup/core-v-verif/blob/master/vendor_lib/google/corev-dv/cv32e40p_csr_template.yaml). +Access mode test of all CSRs. This is a generated test based on [cv32e40p_csr_template.yaml](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/vendor_lib/google/corev-dv/cv32e40p_csr_template.yaml). ### 5 Same as [4](#4), run in Debug mode. Add access mode testing of Debug CSRs. diff --git a/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CV32E40Pv2_CSR_Vplan.md b/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CV32E40Pv2_CSR_Vplan.md index ab0ac39315..7831eb5ad9 100644 --- a/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CV32E40Pv2_CSR_Vplan.md +++ b/cv32e40p/docs/VerifPlans/Simulation/privileged_spec/CV32E40Pv2_CSR_Vplan.md @@ -148,12 +148,12 @@ all\_por\_csr was not mentionned in v1 plan but it seems to fill the same purpos **Updated note for CV32E40Pv2 (2024-04-03):** These tests were not mentionned in v1 plan, but existed at the beginning of v2 verification effort. Their behavior is as described in the table : brute-force for all Zicsr instructions, and a shorter version. ### 3 -Access mode test of all CSRs. This is a generated test based on [cv32e40p_csr_template.yaml](https://github.com/openhwgroup/core-v-verif/blob/master/vendor_lib/google/corev-dv/cv32e40p_csr_template.yaml). +Access mode test of all CSRs. This is a generated test based on [cv32e40p_csr_template.yaml](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/vendor_lib/google/corev-dv/cv32e40p_csr_template.yaml). **Updated note for CV32E40Pv2 (2024-04-03):** Due to the high number of CSR R/W accesses to mstatus, only the first few accesses are self-checking in F configurations. ### 4 -Access mode test of all CSRs. This is a generated test based on [cv32e40p_csr_template.yaml](https://github.com/openhwgroup/core-v-verif/blob/master/vendor_lib/google/corev-dv/cv32e40p_csr_template.yaml). +Access mode test of all CSRs. This is a generated test based on [cv32e40p_csr_template.yaml](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/vendor_lib/google/corev-dv/cv32e40p_csr_template.yaml). **Updated note for CV32E40Pv2 (2024-04-03):** Test was missing some registers for v2 verification, it has been left as-is, updated just to run correctly without error with v2 configurations and diff --git a/docs/VerifPlans/VerificationPlanning101.md b/docs/VerifPlans/VerificationPlanning101.md index 47e25ae9e1..95fd985082 100644 --- a/docs/VerifPlans/VerificationPlanning101.md +++ b/docs/VerifPlans/VerificationPlanning101.md @@ -21,7 +21,7 @@ # How to Write a Verification Plan (Testplan) Verification plans are documents that defines _what_ is to be verified. They go by many names including Testplan, DV plan or just Vplan. A complete, high quality verification plan can be the most valuable item produced by a verification project. ## Format of a Verificaton Plan -CORE-V projects use spreadsheets to capture Testplans1. The template for the spreadsheet is simple enough that you can use either Microsoft Office Excel or LibreOffice Calc. The Verification Plan [template](https://github.com/openhwgroup/core-v-verif/blob/master/docs/VerifPlans/templates/CORE-V_Simulation_VerifPlan_Template.xlsx) for the CORE-V-VERIF is located at the root of the [VerificationPlan](https://github.com/openhwgroup/core-v-verif/tree/master/docs/VerifPlans) directory. +CORE-V projects use spreadsheets to capture Testplans1. The template for the spreadsheet is simple enough that you can use either Microsoft Office Excel or LibreOffice Calc. The Verification Plan [template](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/docs/VerifPlans/templates/CORE-V_Simulation_VerifPlan_Template.xlsx) for the CORE-V-VERIF is located at the root of the [VerificationPlan](https://github.com/openhwgroup/core-v-verif/tree/cv32e40p_v1.8.3/docs/VerifPlans) directory. ## Verification Planning A key activity of any verification effort is to capture a Verification Plan. The purpose of a verification plan is to identify what features need to be verified; the success criteria of the feature and the coverage metrics for testing the feature. Testplans also allow us to reason about the capabilities of the verification environment. @@ -49,13 +49,13 @@ The key point is that taking the time to specify a Testplan for each feature in The template used for this project attempts to provide an easy-to-use format to capture and review this information for every feature in the design. ## HOWTO: The CORE-V Simulation Verification Plan Template -The following sub-sections explain each of the columns in the [simulation verification template spreadsheet](https://github.com/openhwgroup/core-v-verif/blob/master/docs/VerifPlans/templates/CORE-V_Simulation_VerifPlan_Template.xlsx). +The following sub-sections explain each of the columns in the [simulation verification template spreadsheet](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/docs/VerifPlans/templates/CORE-V_Simulation_VerifPlan_Template.xlsx). ### Requirement Location This is a pointer to the source Requirements document of the Features in question. It can be a standards document, such as the RISC-V ISA, or a micro-architecture specification. The CV32E40P [User Manual](https://cv32e40p.readthedocs.io/en/latest/intro/) lists sources of documentation relevant to the CV32E40P. _Every item in a Verification Plan must be attributed to one or more of these sources_. Please also include a chapter or section number. Note that if you are using the [CV32E40P User Manual](https://core-v-docs-verif-strat.readthedocs.io/projects/cv32e40p_um/en/latest/) as a reference, you **must** provide a release/version number as well since this document is currently in active development. ### Feature The high-level feature you are trying to verify. For example, RV32I Register-Immediate Instructions. In some cases, it may be natural to use the section header name of the reference document. ### Sub-Feature -This is an optional, but often used column. Using our previous examples, ADDI is a sub-feature of RV32I Register-Immediate Instructions. If it makes sense to decompose the Feature into two or more sub-features, use this columnn for that. If required, add a column for sub-sub-features. +This is an optional, but often used column. Using our previous examples, ADDI is a sub-feature of RV32I Register-Immediate Instructions. If it makes sense to decompose the Feature into two or more sub-features, use this columnn for that. If required, add a column for sub-sub-features. ### Feature Description A summary of what the features does. It should be a _summary_, not a verbatium copy-n-paste from the Requirements Document. ### Verification Goals @@ -93,7 +93,7 @@ This field is used to link the Feature to coverage data generated in Regression. 1I know, I know, we _all_ hate spreadsheets, but they really are the best format for this type of data. ## HOWTO: The CORE-V Formal Verification Plan Template -The following sub-sections explain each of the columns in the [formal verification template spreadsheet](https://github.com/openhwgroup/core-v-verif/blob/master/docs/VerifPlans/templates/CORE-V_Formal_VerifPlan_Template.xlsx). +The following sub-sections explain each of the columns in the [formal verification template spreadsheet](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/docs/VerifPlans/templates/CORE-V_Formal_VerifPlan_Template.xlsx). For obvious reasons, the **Requirement Location**, **Feature**, **Sub-Feature**, **Feature Description** and **Verification Goals** are the same as as the simulation verification template. ### Property or Checker This is the name of the SystemVerilog _property_ or _checker_ that is used to verify the Feature in question. diff --git a/mk/README.md b/mk/README.md index 7c97e7c75f..9b37578ccc 100644 --- a/mk/README.md +++ b/mk/README.md @@ -99,7 +99,7 @@ This Makefile is largely empty and include: This include the RTL repo to simulate; Google riscv-dv; RISCV compliance suite and other external repositories. - `CORE-V-VERIF/mk/uvmt/uvmt.mk`, which implements simulation execution targets and: - `CORE-V-VERIF/mk/Common.mk` supports all common variables, rules and targets, including specific targets to clone the RTL. -

+

Simulator-specific Makefiles are used to build the command-line to run a specific test with a specific simulator. These files are organized as shown below: ``` @@ -139,7 +139,7 @@ is the name of a [test-program](https://core-v-docs-verif-strat.readthedocs.io/e Importing the source code in DVT Eclipse IDE [dvt](https://www.dvteclipse.com/products/dvt-eclipse-ide) ---------------------- Alongside the simulator-specific Makefiles, there is also a makefile called `dvt.mk`. -The command `make SIMULATOR= open_in_dvt_ide` will import the core-v-verif testbench and RTL source code +The command `make SIMULATOR= open_in_dvt_ide` will import the core-v-verif testbench and RTL source code in the DVT Eclipse IDE.

**Note:** `CV_CORE/sim/uvmt/Makefile` is the 'root' Makefile from which users can invoke DVT. @@ -318,7 +318,7 @@ make compliance_regression RISCV_ISA=rv32imc will run all compressed instruction tests in the compliance test-suite, diff the signature files and produce a summary report. Note that four of the test-programs in the rv32i compliance suite are deliberately ignored. See [issue #412](https://github.com/openhwgroup/core-v-verif/issues/412).

-The _cv_regress_ utility can also be used to run the compliance regression tests found in the [cv32_compliance](https://github.com/openhwgroup/core-v-verif/blob/master/cv32e40p/regress/cv32_compliance.yaml) YAML regression +The _cv_regress_ utility can also be used to run the compliance regression tests found in the [cv32_compliance](https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/cv32e40p/regress/cv32_compliance.yaml) YAML regression specification. This is supported for Metrics JSON (--metrics), shell script (--sh), and Cadence Vmanager VSIF (--vsif) output formats. Use the following example: ``` # Shell script output @@ -386,7 +386,7 @@ For certain simulators multiple debug tools are available that enable advanced d ### Interactive Simulation -To run a simulation in interactive mode (to enable single-stepping, breakpoints, restarting), use the GUI=1 command when running a test. +To run a simulation in interactive mode (to enable single-stepping, breakpoints, restarting), use the GUI=1 command when running a test. If applicable for a simulator, line debugging will be enabled in the compile to enable single-stepping. @@ -398,7 +398,7 @@ The Makefiles support a user controllable variable **USER_RUN_FLAGS** which can #### Set the UVM quit count -All error signaling and handling is routed through the standard UVM report server for all OpenHW testbenches. By default the UVM is configured +All error signaling and handling is routed through the standard UVM report server for all OpenHW testbenches. By default the UVM is configured to allow up to 5 errors to be signaled before aborting the test. There is a run-time plusarg to configure this that should work for all tests. Use the USER_RUN_FLAGS make variable with the standard UVM_MAX_QUIT_COUNT plusarg as below. Please note that the NO is required and signals that you want UVM to use your plusarg over any internally configured quit count values. @@ -488,4 +488,3 @@ Generate coverage report for all executed tests with coverage databases. Invoke GUI coverage browser for all executed tests with coverage databases. **make cov MERGE=1 GUI=1** - diff --git a/tools/vptool/README.md b/tools/vptool/README.md index be78643b5f..987930a860 100644 --- a/tools/vptool/README.md +++ b/tools/vptool/README.md @@ -11,7 +11,7 @@ the information associated with the given Feature. The user interface of VPTOOL provides a means of entering all information mentioned in the CORE-V "How to Write a Verification Plan" document available at -https://github.com/openhwgroup/core-v-verif/blob/master/docs/VerifPlans/VerificationPlanning101.md. +https://github.com/openhwgroup/core-v-verif/blob/cv32e40p_v1.8.3/docs/VerifPlans/VerificationPlanning101.md. When creating new Feature Test descriptions, text fields provide the user with cues about the kind of information to enter in each field. All text fields support an "Undo" feature that allows to