From bcbafd11b3fc57ee5d61cb815fa874bc5f00356e Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 14 May 2024 09:15:08 +0800 Subject: [PATCH 1/3] Add esle clause on assertion Signed-off-by: dd-baoshan --- cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 5a517e3788..b80269d40c 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -607,7 +607,8 @@ interface uvmt_cv32e40p_cov_if detect_apu_rvalid = 1; end else begin - assert (clk_cycle_window <= MAX_FP_XACT_CYCLE); + assert (clk_cycle_window <= MAX_FP_XACT_CYCLE) + else `uvm_error("uvmt_cv32e40p_cov_if", $sformatf("clk_cycle_window (%0d) > MAX_FP_XACT_CYCLE (%0d)", clk_cycle_window, MAX_FP_XACT_CYCLE)); if (apu_req && apu_gnt && apu_rvalid_i && detect_apu_rvalid) begin : IS_0_CYC_FPU clk_cycle_window = 0; detect_apu_rvalid = 0; From 123b6cebaeb5c6c8d7382b4d874088c446d1786a Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 14 May 2024 09:45:46 +0800 Subject: [PATCH 2/3] Add restriction to use random store instr that uses sp Signed-off-by: dd-baoshan --- .../env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv index bdaf1955ae..e36d85ef87 100644 --- a/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv +++ b/cv32e40p/env/corev-dv/instr_lib/cv32e40p_pulp_hwloop_instr_lib.sv @@ -990,6 +990,10 @@ class cv32e40p_xpulp_hwloop_base_stream extends cv32e40p_xpulp_rand_stream; if(no_fence) riscv_exclude_instr = {riscv_exclude_instr, FENCE, FENCE_I}; + if(cfg.sp != SP) begin // prevent corruption due to sw(sp) + riscv_exclude_instr = {riscv_exclude_instr, C_SWSP, C_FSWSP}; + end + `uvm_info("cv32e40p_xpulp_hwloop_base_stream", $sformatf("insert_rand_instr- Number of Random instr to generate= %0d",num_rand_instr), UVM_HIGH) From abbece74c7195dd656c4392a0d6885fbd7aca038 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Tue, 14 May 2024 12:18:01 +0800 Subject: [PATCH 3/3] Add custom test to improve functional coverage holes (uvme_cv32e40p_zfinx_instr_covg) Signed-off-by: dd-baoshan --- .../zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S index ee2efc40b1..6efba347b3 100644 --- a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S +++ b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S @@ -3685,6 +3685,8 @@ _fsgnjx_jr31: fsgnjx.s x31, x31, x31 flt.s x1, x15, x15 cv.lbu x7, (x1), 4 fle.s x1, x7, x7 + cv.lbu x6, (x1), 4 + fdiv.s x1, x6, x6 cv.lbu x9, (x1), 4 fdiv.s x1, x9, x9 cv.lbu x22, (x1), 4